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// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the serial port on the 21285 StrongArm-110 core logic chip.
*
* Based on drivers/char/serial.c
*/
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/device.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/system_info.h>
#include <asm/hardware/dec21285.h>
#include <mach/hardware.h>
#define BAUD_BASE (mem_fclk_21285/64)
#define SERIAL_21285_NAME "ttyFB"
#define SERIAL_21285_MAJOR 204
#define SERIAL_21285_MINOR 4
#define RXSTAT_DUMMY_READ 0x80000000
#define RXSTAT_FRAME (1 << 0)
#define RXSTAT_PARITY (1 << 1)
#define RXSTAT_OVERRUN (1 << 2)
#define RXSTAT_ANYERR (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
#define H_UBRLCR_BREAK (1 << 0)
#define H_UBRLCR_PARENB (1 << 1)
#define H_UBRLCR_PAREVN (1 << 2)
#define H_UBRLCR_STOPB (1 << 3)
#define H_UBRLCR_FIFO (1 << 4)
static const char serial21285_name[] = "Footbridge UART";
/*
* We only need 2 bits of data, so instead of creating a whole structure for
* this, use bits of the private_data pointer of the uart port structure.
*/
#define tx_enabled_bit 0
#define rx_enabled_bit 1
static bool is_enabled(struct uart_port *port, int bit)
{
unsigned long *private_data = (unsigned long *)&port->private_data;
if (test_bit(bit, private_data))
return true;
return false;
}
static void enable(struct uart_port *port, int bit)
{
unsigned long *private_data = (unsigned long *)&port->private_data;
set_bit(bit, private_data);
}
static void disable(struct uart_port *port, int bit)
{
unsigned long *private_data = (unsigned long *)&port->private_data;
clear_bit(bit, private_data);
}
#define is_tx_enabled(port) is_enabled(port, tx_enabled_bit)
#define tx_enable(port) enable(port, tx_enabled_bit)
#define tx_disable(port) disable(port, tx_enabled_bit)
#define is_rx_enabled(port) is_enabled(port, rx_enabled_bit)
#define rx_enable(port) enable(port, rx_enabled_bit)
#define rx_disable(port) disable(port, rx_enabled_bit)
/*
* The documented expression for selecting the divisor is:
* BAUD_BASE / baud - 1
* However, typically BAUD_BASE is not divisible by baud, so
* we want to select the divisor that gives us the minimum
* error. Therefore, we want:
* int(BAUD_BASE / baud - 0.5) ->
* int(BAUD_BASE / baud - (baud >> 1) / baud) ->
* int((BAUD_BASE - (baud >> 1)) / baud)
*/
static void serial21285_stop_tx(struct uart_port *port)
{
if (is_tx_enabled(port)) {
disable_irq_nosync(IRQ_CONTX);
tx_disable(port);
}
}
static void serial21285_start_tx(struct uart_port *port)
{
if (!is_tx_enabled(port)) {
enable_irq(IRQ_CONTX);
tx_enable(port);
}
}
static void serial21285_stop_rx(struct uart_port *port)
{
if (is_rx_enabled(port)) {
disable_irq_nosync(IRQ_CONRX);
rx_disable(port);
}
}
static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
unsigned int status, rxs, max_count = 256;
u8 ch, flag;
status = *CSR_UARTFLG;
while (!(status & 0x10) && max_count--) {
ch = *CSR_UARTDR;
flag = TTY_NORMAL;
port->icount.rx++;
rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
if (unlikely(rxs & RXSTAT_ANYERR)) {
if (rxs & RXSTAT_PARITY)
port->icount.parity++;
else if (rxs & RXSTAT_FRAME)
port->icount.frame++;
if (rxs & RXSTAT_OVERRUN)
port->icount.overrun++;
rxs &= port->read_status_mask;
if (rxs & RXSTAT_PARITY)
flag = TTY_PARITY;
else if (rxs & RXSTAT_FRAME)
flag = TTY_FRAME;
}
uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
status = *CSR_UARTFLG;
}
tty_flip_buffer_push(&port->state->port);
return IRQ_HANDLED;
}
static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
u8 ch;
uart_port_tx_limited(port, ch, 256,
!(*CSR_UARTFLG & 0x20),
*CSR_UARTDR = ch,
({}));
return IRQ_HANDLED;
}
static unsigned int serial21285_tx_empty(struct uart_port *port)
{
return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
}
/* no modem control lines */
static unsigned int serial21285_get_mctrl(struct uart_port *port)
{
return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
}
static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}
static void serial21285_break_ctl(struct uart_port *port, int break_state)
{
unsigned long flags;
unsigned int h_lcr;
spin_lock_irqsave(&port->lock, flags);
h_lcr = *CSR_H_UBRLCR;
if (break_state)
h_lcr |= H_UBRLCR_BREAK;
else
h_lcr &= ~H_UBRLCR_BREAK;
*CSR_H_UBRLCR = h_lcr;
spin_unlock_irqrestore(&port->lock, flags);
}
static int serial21285_startup(struct uart_port *port)
{
int ret;
tx_enable(port);
rx_enable(port);
ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
serial21285_name, port);
if (ret == 0) {
ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
serial21285_name, port);
if (ret)
free_irq(IRQ_CONRX, port);
}
return ret;
}
static void serial21285_shutdown(struct uart_port *port)
{
free_irq(IRQ_CONTX, port);
free_irq(IRQ_CONRX, port);
}
static void
serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
unsigned long flags;
unsigned int baud, quot, h_lcr, b;
/*
* We don't support modem control lines.
*/
termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
termios->c_cflag |= CLOCAL;
/*
* We don't support BREAK character recognition.
*/
termios->c_iflag &= ~(IGNBRK | BRKINT);
/*
* Ask the core to calculate the divisor for us.
*/
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
quot = uart_get_divisor(port, baud);
b = port->uartclk / (16 * quot);
tty_termios_encode_baud_rate(termios, b, b);
switch (termios->c_cflag & CSIZE) {
case CS5:
h_lcr = 0x00;
break;
case CS6:
h_lcr = 0x20;
break;
case CS7:
h_lcr = 0x40;
break;
default: /* CS8 */
h_lcr = 0x60;
break;
}
if (termios->c_cflag & CSTOPB)
h_lcr |= H_UBRLCR_STOPB;
if (termios->c_cflag & PARENB) {
h_lcr |= H_UBRLCR_PARENB;
if (!(termios->c_cflag & PARODD))
h_lcr |= H_UBRLCR_PAREVN;
}
if (port->fifosize)
h_lcr |= H_UBRLCR_FIFO;
spin_lock_irqsave(&port->lock, flags);
/*
* Update the per-port timeout.
*/
uart_update_timeout(port, termios->c_cflag, baud);
/*
* Which character status flags are we interested in?
*/
port->read_status_mask = RXSTAT_OVERRUN;
if (termios->c_iflag & INPCK)
port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
/*
* Which character status flags should we ignore?
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
port->ignore_status_mask |= RXSTAT_OVERRUN;
/*
* Ignore all characters if CREAD is not set.
*/
if ((termios->c_cflag & CREAD) == 0)
port->ignore_status_mask |= RXSTAT_DUMMY_READ;
quot -= 1;
*CSR_UARTCON = 0;
*CSR_L_UBRLCR = quot & 0xff;
*CSR_M_UBRLCR = (quot >> 8) & 0x0f;
*CSR_H_UBRLCR = h_lcr;
*CSR_UARTCON = 1;
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *serial21285_type(struct uart_port *port)
{
return port->type == PORT_21285 ? "DC21285" : NULL;
}
static void serial21285_release_port(struct uart_port *port)
{
release_mem_region(port->mapbase, 32);
}
static int serial21285_request_port(struct uart_port *port)
{
return request_mem_region(port->mapbase, 32, serial21285_name)
!= NULL ? 0 : -EBUSY;
}
static void serial21285_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
port->type = PORT_21285;
}
/*
* verify the new serial_struct (for TIOCSSERIAL).
*/
static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
ret = -EINVAL;
if (ser->irq <= 0)
ret = -EINVAL;
if (ser->baud_base != port->uartclk / 16)
ret = -EINVAL;
return ret;
}
static const struct uart_ops serial21285_ops = {
.tx_empty = serial21285_tx_empty,
.get_mctrl = serial21285_get_mctrl,
.set_mctrl = serial21285_set_mctrl,
.stop_tx = serial21285_stop_tx,
.start_tx = serial21285_start_tx,
.stop_rx = serial21285_stop_rx,
.break_ctl = serial21285_break_ctl,
.startup = serial21285_startup,
.shutdown = serial21285_shutdown,
.set_termios = serial21285_set_termios,
.type = serial21285_type,
.release_port = serial21285_release_port,
.request_port = serial21285_request_port,
.config_port = serial21285_config_port,
.verify_port = serial21285_verify_port,
};
static struct uart_port serial21285_port = {
.mapbase = 0x42000160,
.iotype = UPIO_MEM,
.irq = 0,
.fifosize = 16,
.ops = &serial21285_ops,
.flags = UPF_BOOT_AUTOCONF,
};
static void serial21285_setup_ports(void)
{
serial21285_port.uartclk = mem_fclk_21285 / 4;
}
#ifdef CONFIG_SERIAL_21285_CONSOLE
static void serial21285_console_putchar(struct uart_port *port, unsigned char ch)
{
while (*CSR_UARTFLG & 0x20)
barrier();
*CSR_UARTDR = ch;
}
static void
serial21285_console_write(struct console *co, const char *s,
unsigned int count)
{
uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
}
static void __init
serial21285_get_options(struct uart_port *port, int *baud,
int *parity, int *bits)
{
if (*CSR_UARTCON == 1) {
unsigned int tmp;
tmp = *CSR_H_UBRLCR;
switch (tmp & 0x60) {
case 0x00:
*bits = 5;
break;
case 0x20:
*bits = 6;
break;
case 0x40:
*bits = 7;
break;
default:
case 0x60:
*bits = 8;
break;
}
if (tmp & H_UBRLCR_PARENB) {
*parity = 'o';
if (tmp & H_UBRLCR_PAREVN)
*parity = 'e';
}
tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
*baud = port->uartclk / (16 * (tmp + 1));
}
}
static int __init serial21285_console_setup(struct console *co, char *options)
{
struct uart_port *port = &serial21285_port;
int baud = 9600;
int bits = 8;
int parity = 'n';
int flow = 'n';
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
else
serial21285_get_options(port, &baud, &parity, &bits);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver serial21285_reg;
static struct console serial21285_console =
{
.name = SERIAL_21285_NAME,
.write = serial21285_console_write,
.device = uart_console_device,
.setup = serial21285_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &serial21285_reg,
};
static int __init rs285_console_init(void)
{
serial21285_setup_ports();
register_console(&serial21285_console);
return 0;
}
console_initcall(rs285_console_init);
#define SERIAL_21285_CONSOLE &serial21285_console
#else
#define SERIAL_21285_CONSOLE NULL
#endif
static struct uart_driver serial21285_reg = {
.owner = THIS_MODULE,
.driver_name = "ttyFB",
.dev_name = "ttyFB",
.major = SERIAL_21285_MAJOR,
.minor = SERIAL_21285_MINOR,
.nr = 1,
.cons = SERIAL_21285_CONSOLE,
};
static int __init serial21285_init(void)
{
int ret;
printk(KERN_INFO "Serial: 21285 driver\n");
serial21285_setup_ports();
ret = uart_register_driver(&serial21285_reg);
if (ret == 0)
uart_add_one_port(&serial21285_reg, &serial21285_port);
return ret;
}
static void __exit serial21285_exit(void)
{
uart_remove_one_port(&serial21285_reg, &serial21285_port);
uart_unregister_driver(&serial21285_reg);
}
module_init(serial21285_init);
module_exit(serial21285_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
| linux-master | drivers/tty/serial/21285.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for PowerMac Z85c30 based ESCC cell found in the
* "macio" ASICs of various PowerMac models
*
* Copyright (C) 2003 Ben. Herrenschmidt ([email protected])
*
* Derived from drivers/macintosh/macserial.c by Paul Mackerras
* and drivers/serial/sunzilog.c by David S. Miller
*
* Hrm... actually, I ripped most of sunzilog (Thanks David !) and
* adapted special tweaks needed for us. I don't think it's worth
* merging back those though. The DMA code still has to get in
* and once done, I expect that driver to remain fairly stable in
* the long term, unless we change the driver model again...
*
* 2004-08-06 Harald Welte <[email protected]>
* - Enable BREAK interrupt
* - Add support for sysreq
*
* TODO: - Add DMA support
* - Defer port shutdown to a few seconds after close
* - maybe put something right into uap->clk_divisor
*/
#undef DEBUG
#undef USE_CTRL_O_SYSRQ
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/adb.h>
#include <linux/pmu.h>
#include <linux/bitops.h>
#include <linux/sysrq.h>
#include <linux/mutex.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/sections.h>
#include <linux/io.h>
#include <asm/irq.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/machdep.h>
#include <asm/pmac_feature.h>
#include <asm/macio.h>
#else
#include <linux/platform_device.h>
#define of_machine_is_compatible(x) (0)
#endif
#include <linux/serial.h>
#include <linux/serial_core.h>
#include "pmac_zilog.h"
MODULE_AUTHOR("Benjamin Herrenschmidt <[email protected]>");
MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
MODULE_LICENSE("GPL");
#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
#define PMACZILOG_MAJOR TTY_MAJOR
#define PMACZILOG_MINOR 64
#define PMACZILOG_NAME "ttyS"
#else
#define PMACZILOG_MAJOR 204
#define PMACZILOG_MINOR 192
#define PMACZILOG_NAME "ttyPZ"
#endif
#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
/*
* For the sake of early serial console, we can do a pre-probe
* (optional) of the ports at rather early boot time.
*/
static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
static int pmz_ports_count;
static struct uart_driver pmz_uart_reg = {
.owner = THIS_MODULE,
.driver_name = PMACZILOG_NAME,
.dev_name = PMACZILOG_NAME,
.major = PMACZILOG_MAJOR,
.minor = PMACZILOG_MINOR,
};
/*
* Load all registers to reprogram the port
* This function must only be called when the TX is not busy. The UART
* port lock must be held and local interrupts disabled.
*/
static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
{
int i;
/* Let pending transmits finish. */
for (i = 0; i < 1000; i++) {
unsigned char stat = read_zsreg(uap, R1);
if (stat & ALL_SNT)
break;
udelay(100);
}
ZS_CLEARERR(uap);
zssync(uap);
ZS_CLEARFIFO(uap);
zssync(uap);
ZS_CLEARERR(uap);
/* Disable all interrupts. */
write_zsreg(uap, R1,
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
/* Set parity, sync config, stop bits, and clock divisor. */
write_zsreg(uap, R4, regs[R4]);
/* Set misc. TX/RX control bits. */
write_zsreg(uap, R10, regs[R10]);
/* Set TX/RX controls sans the enable bits. */
write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
/* now set R7 "prime" on ESCC */
write_zsreg(uap, R15, regs[R15] | EN85C30);
write_zsreg(uap, R7, regs[R7P]);
/* make sure we use R7 "non-prime" on ESCC */
write_zsreg(uap, R15, regs[R15] & ~EN85C30);
/* Synchronous mode config. */
write_zsreg(uap, R6, regs[R6]);
write_zsreg(uap, R7, regs[R7]);
/* Disable baud generator. */
write_zsreg(uap, R14, regs[R14] & ~BRENAB);
/* Clock mode control. */
write_zsreg(uap, R11, regs[R11]);
/* Lower and upper byte of baud rate generator divisor. */
write_zsreg(uap, R12, regs[R12]);
write_zsreg(uap, R13, regs[R13]);
/* Now rewrite R14, with BRENAB (if set). */
write_zsreg(uap, R14, regs[R14]);
/* Reset external status interrupts. */
write_zsreg(uap, R0, RES_EXT_INT);
write_zsreg(uap, R0, RES_EXT_INT);
/* Rewrite R3/R5, this time without enables masked. */
write_zsreg(uap, R3, regs[R3]);
write_zsreg(uap, R5, regs[R5]);
/* Rewrite R1, this time without IRQ enabled masked. */
write_zsreg(uap, R1, regs[R1]);
/* Enable interrupts */
write_zsreg(uap, R9, regs[R9]);
}
/*
* We do like sunzilog to avoid disrupting pending Tx
* Reprogram the Zilog channel HW registers with the copies found in the
* software state struct. If the transmitter is busy, we defer this update
* until the next TX complete interrupt. Else, we do it right now.
*
* The UART port lock must be held and local interrupts disabled.
*/
static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
{
if (!ZS_REGS_HELD(uap)) {
if (ZS_TX_ACTIVE(uap)) {
uap->flags |= PMACZILOG_FLAG_REGS_HELD;
} else {
pmz_debug("pmz: maybe_update_regs: updating\n");
pmz_load_zsregs(uap, uap->curregs);
}
}
}
static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
{
if (enable) {
uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
if (!ZS_IS_EXTCLK(uap))
uap->curregs[1] |= EXT_INT_ENAB;
} else {
uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
}
write_zsreg(uap, R1, uap->curregs[1]);
}
static bool pmz_receive_chars(struct uart_pmac_port *uap)
__must_hold(&uap->port.lock)
{
struct tty_port *port;
unsigned char ch, r1, drop, flag;
int loops = 0;
/* Sanity check, make sure the old bug is no longer happening */
if (uap->port.state == NULL) {
WARN_ON(1);
(void)read_zsdata(uap);
return false;
}
port = &uap->port.state->port;
while (1) {
drop = 0;
r1 = read_zsreg(uap, R1);
ch = read_zsdata(uap);
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
write_zsreg(uap, R0, ERR_RES);
zssync(uap);
}
ch &= uap->parity_mask;
if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
uap->flags &= ~PMACZILOG_FLAG_BREAK;
}
#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
#ifdef USE_CTRL_O_SYSRQ
/* Handle the SysRq ^O Hack */
if (ch == '\x0f') {
uap->port.sysrq = jiffies + HZ*5;
goto next_char;
}
#endif /* USE_CTRL_O_SYSRQ */
if (uap->port.sysrq) {
int swallow;
spin_unlock(&uap->port.lock);
swallow = uart_handle_sysrq_char(&uap->port, ch);
spin_lock(&uap->port.lock);
if (swallow)
goto next_char;
}
#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
/* A real serial line, record the character and status. */
if (drop)
goto next_char;
flag = TTY_NORMAL;
uap->port.icount.rx++;
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
if (r1 & BRK_ABRT) {
pmz_debug("pmz: got break !\n");
r1 &= ~(PAR_ERR | CRC_ERR);
uap->port.icount.brk++;
if (uart_handle_break(&uap->port))
goto next_char;
}
else if (r1 & PAR_ERR)
uap->port.icount.parity++;
else if (r1 & CRC_ERR)
uap->port.icount.frame++;
if (r1 & Rx_OVR)
uap->port.icount.overrun++;
r1 &= uap->port.read_status_mask;
if (r1 & BRK_ABRT)
flag = TTY_BREAK;
else if (r1 & PAR_ERR)
flag = TTY_PARITY;
else if (r1 & CRC_ERR)
flag = TTY_FRAME;
}
if (uap->port.ignore_status_mask == 0xff ||
(r1 & uap->port.ignore_status_mask) == 0) {
tty_insert_flip_char(port, ch, flag);
}
if (r1 & Rx_OVR)
tty_insert_flip_char(port, 0, TTY_OVERRUN);
next_char:
/* We can get stuck in an infinite loop getting char 0 when the
* line is in a wrong HW state, we break that here.
* When that happens, I disable the receive side of the driver.
* Note that what I've been experiencing is a real irq loop where
* I'm getting flooded regardless of the actual port speed.
* Something strange is going on with the HW
*/
if ((++loops) > 1000)
goto flood;
ch = read_zsreg(uap, R0);
if (!(ch & Rx_CH_AV))
break;
}
return true;
flood:
pmz_interrupt_control(uap, 0);
pmz_error("pmz: rx irq flood !\n");
return true;
}
static void pmz_status_handle(struct uart_pmac_port *uap)
{
unsigned char status;
status = read_zsreg(uap, R0);
write_zsreg(uap, R0, RES_EXT_INT);
zssync(uap);
if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
if (status & SYNC_HUNT)
uap->port.icount.dsr++;
/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
* But it does not tell us which bit has changed, we have to keep
* track of this ourselves.
* The CTS input is inverted for some reason. -- paulus
*/
if ((status ^ uap->prev_status) & DCD)
uart_handle_dcd_change(&uap->port,
(status & DCD));
if ((status ^ uap->prev_status) & CTS)
uart_handle_cts_change(&uap->port,
!(status & CTS));
wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
}
if (status & BRK_ABRT)
uap->flags |= PMACZILOG_FLAG_BREAK;
uap->prev_status = status;
}
static void pmz_transmit_chars(struct uart_pmac_port *uap)
{
struct circ_buf *xmit;
if (ZS_IS_CONS(uap)) {
unsigned char status = read_zsreg(uap, R0);
/* TX still busy? Just wait for the next TX done interrupt.
*
* It can occur because of how we do serial console writes. It would
* be nice to transmit console writes just like we normally would for
* a TTY line. (ie. buffered and TX interrupt driven). That is not
* easy because console writes cannot sleep. One solution might be
* to poll on enough port->xmit space becoming free. -DaveM
*/
if (!(status & Tx_BUF_EMP))
return;
}
uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
if (ZS_REGS_HELD(uap)) {
pmz_load_zsregs(uap, uap->curregs);
uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
}
if (ZS_TX_STOPPED(uap)) {
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
goto ack_tx_int;
}
/* Under some circumstances, we see interrupts reported for
* a closed channel. The interrupt mask in R1 is clear, but
* R3 still signals the interrupts and we see them when taking
* an interrupt for the other channel (this could be a qemu
* bug but since the ESCC doc doesn't specify precsiely whether
* R3 interrup status bits are masked by R1 interrupt enable
* bits, better safe than sorry). --BenH.
*/
if (!ZS_IS_OPEN(uap))
goto ack_tx_int;
if (uap->port.x_char) {
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
write_zsdata(uap, uap->port.x_char);
zssync(uap);
uap->port.icount.tx++;
uap->port.x_char = 0;
return;
}
if (uap->port.state == NULL)
goto ack_tx_int;
xmit = &uap->port.state->xmit;
if (uart_circ_empty(xmit)) {
uart_write_wakeup(&uap->port);
goto ack_tx_int;
}
if (uart_tx_stopped(&uap->port))
goto ack_tx_int;
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
write_zsdata(uap, xmit->buf[xmit->tail]);
zssync(uap);
uart_xmit_advance(&uap->port, 1);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
return;
ack_tx_int:
write_zsreg(uap, R0, RES_Tx_P);
zssync(uap);
}
/* Hrm... we register that twice, fixme later.... */
static irqreturn_t pmz_interrupt(int irq, void *dev_id)
{
struct uart_pmac_port *uap = dev_id;
struct uart_pmac_port *uap_a;
struct uart_pmac_port *uap_b;
int rc = IRQ_NONE;
bool push;
u8 r3;
uap_a = pmz_get_port_A(uap);
uap_b = uap_a->mate;
spin_lock(&uap_a->port.lock);
r3 = read_zsreg(uap_a, R3);
/* Channel A */
push = false;
if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
if (!ZS_IS_OPEN(uap_a)) {
pmz_debug("ChanA interrupt while not open !\n");
goto skip_a;
}
write_zsreg(uap_a, R0, RES_H_IUS);
zssync(uap_a);
if (r3 & CHAEXT)
pmz_status_handle(uap_a);
if (r3 & CHARxIP)
push = pmz_receive_chars(uap_a);
if (r3 & CHATxIP)
pmz_transmit_chars(uap_a);
rc = IRQ_HANDLED;
}
skip_a:
spin_unlock(&uap_a->port.lock);
if (push)
tty_flip_buffer_push(&uap->port.state->port);
if (!uap_b)
goto out;
spin_lock(&uap_b->port.lock);
push = false;
if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
if (!ZS_IS_OPEN(uap_b)) {
pmz_debug("ChanB interrupt while not open !\n");
goto skip_b;
}
write_zsreg(uap_b, R0, RES_H_IUS);
zssync(uap_b);
if (r3 & CHBEXT)
pmz_status_handle(uap_b);
if (r3 & CHBRxIP)
push = pmz_receive_chars(uap_b);
if (r3 & CHBTxIP)
pmz_transmit_chars(uap_b);
rc = IRQ_HANDLED;
}
skip_b:
spin_unlock(&uap_b->port.lock);
if (push)
tty_flip_buffer_push(&uap->port.state->port);
out:
return rc;
}
/*
* Peek the status register, lock not held by caller
*/
static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
{
unsigned long flags;
u8 status;
spin_lock_irqsave(&uap->port.lock, flags);
status = read_zsreg(uap, R0);
spin_unlock_irqrestore(&uap->port.lock, flags);
return status;
}
/*
* Check if transmitter is empty
* The port lock is not held.
*/
static unsigned int pmz_tx_empty(struct uart_port *port)
{
unsigned char status;
status = pmz_peek_status(to_pmz(port));
if (status & Tx_BUF_EMP)
return TIOCSER_TEMT;
return 0;
}
/*
* Set Modem Control (RTS & DTR) bits
* The port lock is held and interrupts are disabled.
* Note: Shall we really filter out RTS on external ports or
* should that be dealt at higher level only ?
*/
static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char set_bits, clear_bits;
/* Do nothing for irda for now... */
if (ZS_IS_IRDA(uap))
return;
/* We get called during boot with a port not up yet */
if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
return;
set_bits = clear_bits = 0;
if (ZS_IS_INTMODEM(uap)) {
if (mctrl & TIOCM_RTS)
set_bits |= RTS;
else
clear_bits |= RTS;
}
if (mctrl & TIOCM_DTR)
set_bits |= DTR;
else
clear_bits |= DTR;
/* NOTE: Not subject to 'transmitter active' rule. */
uap->curregs[R5] |= set_bits;
uap->curregs[R5] &= ~clear_bits;
write_zsreg(uap, R5, uap->curregs[R5]);
pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
set_bits, clear_bits, uap->curregs[R5]);
zssync(uap);
}
/*
* Get Modem Control bits (only the input ones, the core will
* or that with a cached value of the control ones)
* The port lock is held and interrupts are disabled.
*/
static unsigned int pmz_get_mctrl(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char status;
unsigned int ret;
status = read_zsreg(uap, R0);
ret = 0;
if (status & DCD)
ret |= TIOCM_CAR;
if (status & SYNC_HUNT)
ret |= TIOCM_DSR;
if (!(status & CTS))
ret |= TIOCM_CTS;
return ret;
}
/*
* Stop TX side. Dealt like sunzilog at next Tx interrupt,
* though for DMA, we will have to do a bit more.
* The port lock is held and interrupts are disabled.
*/
static void pmz_stop_tx(struct uart_port *port)
{
to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
}
/*
* Kick the Tx side.
* The port lock is held and interrupts are disabled.
*/
static void pmz_start_tx(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char status;
uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
status = read_zsreg(uap, R0);
/* TX busy? Just wait for the TX done interrupt. */
if (!(status & Tx_BUF_EMP))
return;
/* Send the first character to jump-start the TX done
* IRQ sending engine.
*/
if (port->x_char) {
write_zsdata(uap, port->x_char);
zssync(uap);
port->icount.tx++;
port->x_char = 0;
} else {
struct circ_buf *xmit = &port->state->xmit;
if (uart_circ_empty(xmit))
return;
write_zsdata(uap, xmit->buf[xmit->tail]);
zssync(uap);
uart_xmit_advance(port, 1);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
}
}
/*
* Stop Rx side, basically disable emitting of
* Rx interrupts on the port. We don't disable the rx
* side of the chip proper though
* The port lock is held.
*/
static void pmz_stop_rx(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
/* Disable all RX interrupts. */
uap->curregs[R1] &= ~RxINT_MASK;
pmz_maybe_update_regs(uap);
}
/*
* Enable modem status change interrupts
* The port lock is held.
*/
static void pmz_enable_ms(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char new_reg;
if (ZS_IS_IRDA(uap))
return;
new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
if (new_reg != uap->curregs[R15]) {
uap->curregs[R15] = new_reg;
/* NOTE: Not subject to 'transmitter active' rule. */
write_zsreg(uap, R15, uap->curregs[R15]);
}
}
/*
* Control break state emission
* The port lock is not held.
*/
static void pmz_break_ctl(struct uart_port *port, int break_state)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned char set_bits, clear_bits, new_reg;
unsigned long flags;
set_bits = clear_bits = 0;
if (break_state)
set_bits |= SND_BRK;
else
clear_bits |= SND_BRK;
spin_lock_irqsave(&port->lock, flags);
new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
if (new_reg != uap->curregs[R5]) {
uap->curregs[R5] = new_reg;
write_zsreg(uap, R5, uap->curregs[R5]);
}
spin_unlock_irqrestore(&port->lock, flags);
}
#ifdef CONFIG_PPC_PMAC
/*
* Turn power on or off to the SCC and associated stuff
* (port drivers, modem, IR port, etc.)
* Returns the number of milliseconds we should wait before
* trying to use the port.
*/
static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
{
int delay = 0;
int rc;
if (state) {
rc = pmac_call_feature(
PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
pmz_debug("port power on result: %d\n", rc);
if (ZS_IS_INTMODEM(uap)) {
rc = pmac_call_feature(
PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
delay = 2500; /* wait for 2.5s before using */
pmz_debug("modem power result: %d\n", rc);
}
} else {
/* TODO: Make that depend on a timer, don't power down
* immediately
*/
if (ZS_IS_INTMODEM(uap)) {
rc = pmac_call_feature(
PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
pmz_debug("port power off result: %d\n", rc);
}
pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
}
return delay;
}
#else
static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
{
return 0;
}
#endif /* !CONFIG_PPC_PMAC */
/*
* FixZeroBug....Works around a bug in the SCC receiving channel.
* Inspired from Darwin code, 15 Sept. 2000 -DanM
*
* The following sequence prevents a problem that is seen with O'Hare ASICs
* (most versions -- also with some Heathrow and Hydra ASICs) where a zero
* at the input to the receiver becomes 'stuck' and locks up the receiver.
* This problem can occur as a result of a zero bit at the receiver input
* coincident with any of the following events:
*
* The SCC is initialized (hardware or software).
* A framing error is detected.
* The clocking option changes from synchronous or X1 asynchronous
* clocking to X16, X32, or X64 asynchronous clocking.
* The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
*
* This workaround attempts to recover from the lockup condition by placing
* the SCC in synchronous loopback mode with a fast clock before programming
* any of the asynchronous modes.
*/
static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
{
write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
zssync(uap);
udelay(10);
write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
zssync(uap);
write_zsreg(uap, 4, X1CLK | MONSYNC);
write_zsreg(uap, 3, Rx8);
write_zsreg(uap, 5, Tx8 | RTS);
write_zsreg(uap, 9, NV); /* Didn't we already do this? */
write_zsreg(uap, 11, RCBR | TCBR);
write_zsreg(uap, 12, 0);
write_zsreg(uap, 13, 0);
write_zsreg(uap, 14, (LOOPBAK | BRSRC));
write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
write_zsreg(uap, 3, Rx8 | RxENABLE);
write_zsreg(uap, 0, RES_EXT_INT);
write_zsreg(uap, 0, RES_EXT_INT);
write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
/* The channel should be OK now, but it is probably receiving
* loopback garbage.
* Switch to asynchronous mode, disable the receiver,
* and discard everything in the receive buffer.
*/
write_zsreg(uap, 9, NV);
write_zsreg(uap, 4, X16CLK | SB_MASK);
write_zsreg(uap, 3, Rx8);
while (read_zsreg(uap, 0) & Rx_CH_AV) {
(void)read_zsreg(uap, 8);
write_zsreg(uap, 0, RES_EXT_INT);
write_zsreg(uap, 0, ERR_RES);
}
}
/*
* Real startup routine, powers up the hardware and sets up
* the SCC. Returns a delay in ms where you need to wait before
* actually using the port, this is typically the internal modem
* powerup delay. This routine expect the lock to be taken.
*/
static int __pmz_startup(struct uart_pmac_port *uap)
{
int pwr_delay = 0;
memset(&uap->curregs, 0, sizeof(uap->curregs));
/* Power up the SCC & underlying hardware (modem/irda) */
pwr_delay = pmz_set_scc_power(uap, 1);
/* Nice buggy HW ... */
pmz_fix_zero_bug_scc(uap);
/* Reset the channel */
uap->curregs[R9] = 0;
write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
zssync(uap);
udelay(10);
write_zsreg(uap, 9, 0);
zssync(uap);
/* Clear the interrupt registers */
write_zsreg(uap, R1, 0);
write_zsreg(uap, R0, ERR_RES);
write_zsreg(uap, R0, ERR_RES);
write_zsreg(uap, R0, RES_H_IUS);
write_zsreg(uap, R0, RES_H_IUS);
/* Setup some valid baud rate */
uap->curregs[R4] = X16CLK | SB1;
uap->curregs[R3] = Rx8;
uap->curregs[R5] = Tx8 | RTS;
if (!ZS_IS_IRDA(uap))
uap->curregs[R5] |= DTR;
uap->curregs[R12] = 0;
uap->curregs[R13] = 0;
uap->curregs[R14] = BRENAB;
/* Clear handshaking, enable BREAK interrupts */
uap->curregs[R15] = BRKIE;
/* Master interrupt enable */
uap->curregs[R9] |= NV | MIE;
pmz_load_zsregs(uap, uap->curregs);
/* Enable receiver and transmitter. */
write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
/* Remember status for DCD/CTS changes */
uap->prev_status = read_zsreg(uap, R0);
return pwr_delay;
}
static void pmz_irda_reset(struct uart_pmac_port *uap)
{
unsigned long flags;
spin_lock_irqsave(&uap->port.lock, flags);
uap->curregs[R5] |= DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
spin_unlock_irqrestore(&uap->port.lock, flags);
msleep(110);
spin_lock_irqsave(&uap->port.lock, flags);
uap->curregs[R5] &= ~DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
spin_unlock_irqrestore(&uap->port.lock, flags);
msleep(10);
}
/*
* This is the "normal" startup routine, using the above one
* wrapped with the lock and doing a schedule delay
*/
static int pmz_startup(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long flags;
int pwr_delay = 0;
uap->flags |= PMACZILOG_FLAG_IS_OPEN;
/* A console is never powered down. Else, power up and
* initialize the chip
*/
if (!ZS_IS_CONS(uap)) {
spin_lock_irqsave(&port->lock, flags);
pwr_delay = __pmz_startup(uap);
spin_unlock_irqrestore(&port->lock, flags);
}
sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
uap->irq_name, uap)) {
pmz_error("Unable to register zs interrupt handler.\n");
pmz_set_scc_power(uap, 0);
return -ENXIO;
}
/* Right now, we deal with delay by blocking here, I'll be
* smarter later on
*/
if (pwr_delay != 0) {
pmz_debug("pmz: delaying %d ms\n", pwr_delay);
msleep(pwr_delay);
}
/* IrDA reset is done now */
if (ZS_IS_IRDA(uap))
pmz_irda_reset(uap);
/* Enable interrupt requests for the channel */
spin_lock_irqsave(&port->lock, flags);
pmz_interrupt_control(uap, 1);
spin_unlock_irqrestore(&port->lock, flags);
return 0;
}
static void pmz_shutdown(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
/* Disable interrupt requests for the channel */
pmz_interrupt_control(uap, 0);
if (!ZS_IS_CONS(uap)) {
/* Disable receiver and transmitter */
uap->curregs[R3] &= ~RxENABLE;
uap->curregs[R5] &= ~TxENABLE;
/* Disable break assertion */
uap->curregs[R5] &= ~SND_BRK;
pmz_maybe_update_regs(uap);
}
spin_unlock_irqrestore(&port->lock, flags);
/* Release interrupt handler */
free_irq(uap->port.irq, uap);
spin_lock_irqsave(&port->lock, flags);
uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
if (!ZS_IS_CONS(uap))
pmz_set_scc_power(uap, 0); /* Shut the chip down */
spin_unlock_irqrestore(&port->lock, flags);
}
/* Shared by TTY driver and serial console setup. The port lock is held
* and local interrupts are disabled.
*/
static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
unsigned int iflag, unsigned long baud)
{
int brg;
/* Switch to external clocking for IrDA high clock rates. That
* code could be re-used for Midi interfaces with different
* multipliers
*/
if (baud >= 115200 && ZS_IS_IRDA(uap)) {
uap->curregs[R4] = X1CLK;
uap->curregs[R11] = RCTRxCP | TCTRxCP;
uap->curregs[R14] = 0; /* BRG off */
uap->curregs[R12] = 0;
uap->curregs[R13] = 0;
uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
} else {
switch (baud) {
case ZS_CLOCK/16: /* 230400 */
uap->curregs[R4] = X16CLK;
uap->curregs[R11] = 0;
uap->curregs[R14] = 0;
break;
case ZS_CLOCK/32: /* 115200 */
uap->curregs[R4] = X32CLK;
uap->curregs[R11] = 0;
uap->curregs[R14] = 0;
break;
default:
uap->curregs[R4] = X16CLK;
uap->curregs[R11] = TCBR | RCBR;
brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
uap->curregs[R12] = (brg & 255);
uap->curregs[R13] = ((brg >> 8) & 255);
uap->curregs[R14] = BRENAB;
}
uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
}
/* Character size, stop bits, and parity. */
uap->curregs[3] &= ~RxN_MASK;
uap->curregs[5] &= ~TxN_MASK;
switch (cflag & CSIZE) {
case CS5:
uap->curregs[3] |= Rx5;
uap->curregs[5] |= Tx5;
uap->parity_mask = 0x1f;
break;
case CS6:
uap->curregs[3] |= Rx6;
uap->curregs[5] |= Tx6;
uap->parity_mask = 0x3f;
break;
case CS7:
uap->curregs[3] |= Rx7;
uap->curregs[5] |= Tx7;
uap->parity_mask = 0x7f;
break;
case CS8:
default:
uap->curregs[3] |= Rx8;
uap->curregs[5] |= Tx8;
uap->parity_mask = 0xff;
break;
}
uap->curregs[4] &= ~(SB_MASK);
if (cflag & CSTOPB)
uap->curregs[4] |= SB2;
else
uap->curregs[4] |= SB1;
if (cflag & PARENB)
uap->curregs[4] |= PAR_ENAB;
else
uap->curregs[4] &= ~PAR_ENAB;
if (!(cflag & PARODD))
uap->curregs[4] |= PAR_EVEN;
else
uap->curregs[4] &= ~PAR_EVEN;
uap->port.read_status_mask = Rx_OVR;
if (iflag & INPCK)
uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
if (iflag & (IGNBRK | BRKINT | PARMRK))
uap->port.read_status_mask |= BRK_ABRT;
uap->port.ignore_status_mask = 0;
if (iflag & IGNPAR)
uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
if (iflag & IGNBRK) {
uap->port.ignore_status_mask |= BRK_ABRT;
if (iflag & IGNPAR)
uap->port.ignore_status_mask |= Rx_OVR;
}
if ((cflag & CREAD) == 0)
uap->port.ignore_status_mask = 0xff;
}
/*
* Set the irda codec on the imac to the specified baud rate.
*/
static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
{
u8 cmdbyte;
int t, version;
switch (*baud) {
/* SIR modes */
case 2400:
cmdbyte = 0x53;
break;
case 4800:
cmdbyte = 0x52;
break;
case 9600:
cmdbyte = 0x51;
break;
case 19200:
cmdbyte = 0x50;
break;
case 38400:
cmdbyte = 0x4f;
break;
case 57600:
cmdbyte = 0x4e;
break;
case 115200:
cmdbyte = 0x4d;
break;
/* The FIR modes aren't really supported at this point, how
* do we select the speed ? via the FCR on KeyLargo ?
*/
case 1152000:
cmdbyte = 0;
break;
case 4000000:
cmdbyte = 0;
break;
default: /* 9600 */
cmdbyte = 0x51;
*baud = 9600;
break;
}
/* Wait for transmitter to drain */
t = 10000;
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
|| (read_zsreg(uap, R1) & ALL_SNT) == 0) {
if (--t <= 0) {
pmz_error("transmitter didn't drain\n");
return;
}
udelay(10);
}
/* Drain the receiver too */
t = 100;
(void)read_zsdata(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
mdelay(10);
while (read_zsreg(uap, R0) & Rx_CH_AV) {
read_zsdata(uap);
mdelay(10);
if (--t <= 0) {
pmz_error("receiver didn't drain\n");
return;
}
}
/* Switch to command mode */
uap->curregs[R5] |= DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
mdelay(1);
/* Switch SCC to 19200 */
pmz_convert_to_zs(uap, CS8, 0, 19200);
pmz_load_zsregs(uap, uap->curregs);
mdelay(1);
/* Write get_version command byte */
write_zsdata(uap, 1);
t = 5000;
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
if (--t <= 0) {
pmz_error("irda_setup timed out on get_version byte\n");
goto out;
}
udelay(10);
}
version = read_zsdata(uap);
if (version < 4) {
pmz_info("IrDA: dongle version %d not supported\n", version);
goto out;
}
/* Send speed mode */
write_zsdata(uap, cmdbyte);
t = 5000;
while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
if (--t <= 0) {
pmz_error("irda_setup timed out on speed mode byte\n");
goto out;
}
udelay(10);
}
t = read_zsdata(uap);
if (t != cmdbyte)
pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
*baud, version);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
out:
/* Switch back to data mode */
uap->curregs[R5] &= ~DTR;
write_zsreg(uap, R5, uap->curregs[R5]);
zssync(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
(void)read_zsdata(uap);
}
static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long baud;
/* XXX Check which revs of machines actually allow 1 and 4Mb speeds
* on the IR dongle. Note that the IRTTY driver currently doesn't know
* about the FIR mode and high speed modes. So these are unused. For
* implementing proper support for these, we should probably add some
* DMA as well, at least on the Rx side, which isn't a simple thing
* at this point.
*/
if (ZS_IS_IRDA(uap)) {
/* Calc baud rate */
baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
/* Cet the irda codec to the right rate */
pmz_irda_setup(uap, &baud);
/* Set final baud rate */
pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
pmz_load_zsregs(uap, uap->curregs);
zssync(uap);
} else {
baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
/* Make sure modem status interrupts are correctly configured */
if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
} else {
uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
}
/* Load registers to the chip */
pmz_maybe_update_regs(uap);
}
uart_update_timeout(port, termios->c_cflag, baud);
}
/* The port lock is not held. */
static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_pmac_port *uap = to_pmz(port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
/* Disable IRQs on the port */
pmz_interrupt_control(uap, 0);
/* Setup new port configuration */
__pmz_set_termios(port, termios, old);
/* Re-enable IRQs on the port */
if (ZS_IS_OPEN(uap))
pmz_interrupt_control(uap, 1);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *pmz_type(struct uart_port *port)
{
struct uart_pmac_port *uap = to_pmz(port);
if (ZS_IS_IRDA(uap))
return "Z85c30 ESCC - Infrared port";
else if (ZS_IS_INTMODEM(uap))
return "Z85c30 ESCC - Internal modem";
return "Z85c30 ESCC - Serial port";
}
/* We do not request/release mappings of the registers here, this
* happens at early serial probe time.
*/
static void pmz_release_port(struct uart_port *port)
{
}
static int pmz_request_port(struct uart_port *port)
{
return 0;
}
/* These do not need to do anything interesting either. */
static void pmz_config_port(struct uart_port *port, int flags)
{
}
/* We do not support letting the user mess with the divisor, IRQ, etc. */
static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
{
return -EINVAL;
}
#ifdef CONFIG_CONSOLE_POLL
static int pmz_poll_get_char(struct uart_port *port)
{
struct uart_pmac_port *uap =
container_of(port, struct uart_pmac_port, port);
int tries = 2;
while (tries) {
if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
return read_zsdata(uap);
if (tries--)
udelay(5);
}
return NO_POLL_CHAR;
}
static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
{
struct uart_pmac_port *uap =
container_of(port, struct uart_pmac_port, port);
/* Wait for the transmit buffer to empty. */
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
udelay(5);
write_zsdata(uap, c);
}
#endif /* CONFIG_CONSOLE_POLL */
static const struct uart_ops pmz_pops = {
.tx_empty = pmz_tx_empty,
.set_mctrl = pmz_set_mctrl,
.get_mctrl = pmz_get_mctrl,
.stop_tx = pmz_stop_tx,
.start_tx = pmz_start_tx,
.stop_rx = pmz_stop_rx,
.enable_ms = pmz_enable_ms,
.break_ctl = pmz_break_ctl,
.startup = pmz_startup,
.shutdown = pmz_shutdown,
.set_termios = pmz_set_termios,
.type = pmz_type,
.release_port = pmz_release_port,
.request_port = pmz_request_port,
.config_port = pmz_config_port,
.verify_port = pmz_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = pmz_poll_get_char,
.poll_put_char = pmz_poll_put_char,
#endif
};
#ifdef CONFIG_PPC_PMAC
/*
* Setup one port structure after probing, HW is down at this point,
* Unlike sunzilog, we don't need to pre-init the spinlock as we don't
* register our console before uart_add_one_port() is called
*/
static int __init pmz_init_port(struct uart_pmac_port *uap)
{
struct device_node *np = uap->node;
const char *conn;
const struct slot_names_prop {
int count;
char name[1];
} *slots;
int len;
struct resource r_ports;
/*
* Request & map chip registers
*/
if (of_address_to_resource(np, 0, &r_ports))
return -ENODEV;
uap->port.mapbase = r_ports.start;
uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
uap->control_reg = uap->port.membase;
uap->data_reg = uap->control_reg + 0x10;
/*
* Detect port type
*/
if (of_device_is_compatible(np, "cobalt"))
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
conn = of_get_property(np, "AAPL,connector", &len);
if (conn && (strcmp(conn, "infrared") == 0))
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
uap->port_type = PMAC_SCC_ASYNC;
/* 1999 Powerbook G3 has slot-names property instead */
slots = of_get_property(np, "slot-names", &len);
if (slots && slots->count > 0) {
if (strcmp(slots->name, "IrDA") == 0)
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
else if (strcmp(slots->name, "Modem") == 0)
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
}
if (ZS_IS_IRDA(uap))
uap->port_type = PMAC_SCC_IRDA;
if (ZS_IS_INTMODEM(uap)) {
struct device_node* i2c_modem =
of_find_node_by_name(NULL, "i2c-modem");
if (i2c_modem) {
const char* mid =
of_get_property(i2c_modem, "modem-id", NULL);
if (mid) switch(*mid) {
case 0x04 :
case 0x05 :
case 0x07 :
case 0x08 :
case 0x0b :
case 0x0c :
uap->port_type = PMAC_SCC_I2S1;
}
printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
mid ? (*mid) : 0);
of_node_put(i2c_modem);
} else {
printk(KERN_INFO "pmac_zilog: serial modem detected\n");
}
}
/*
* Init remaining bits of "port" structure
*/
uap->port.iotype = UPIO_MEM;
uap->port.irq = irq_of_parse_and_map(np, 0);
uap->port.uartclk = ZS_CLOCK;
uap->port.fifosize = 1;
uap->port.ops = &pmz_pops;
uap->port.type = PORT_PMAC_ZILOG;
uap->port.flags = 0;
/*
* Fixup for the port on Gatwick for which the device-tree has
* missing interrupts. Normally, the macio_dev would contain
* fixed up interrupt info, but we use the device-tree directly
* here due to early probing so we need the fixup too.
*/
if (uap->port.irq == 0 &&
np->parent && np->parent->parent &&
of_device_is_compatible(np->parent->parent, "gatwick")) {
/* IRQs on gatwick are offset by 64 */
uap->port.irq = irq_create_mapping(NULL, 64 + 15);
}
/* Setup some valid baud rate information in the register
* shadows so we don't write crap there before baud rate is
* first initialized.
*/
pmz_convert_to_zs(uap, CS8, 0, 9600);
return 0;
}
/*
* Get rid of a port on module removal
*/
static void pmz_dispose_port(struct uart_pmac_port *uap)
{
struct device_node *np;
np = uap->node;
iounmap(uap->control_reg);
uap->node = NULL;
of_node_put(np);
memset(uap, 0, sizeof(struct uart_pmac_port));
}
/*
* Called upon match with an escc node in the device-tree.
*/
static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
{
struct uart_pmac_port *uap;
int i;
/* Iterate the pmz_ports array to find a matching entry
*/
for (i = 0; i < MAX_ZS_PORTS; i++)
if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
break;
if (i >= MAX_ZS_PORTS)
return -ENODEV;
uap = &pmz_ports[i];
uap->dev = mdev;
uap->port.dev = &mdev->ofdev.dev;
dev_set_drvdata(&mdev->ofdev.dev, uap);
/* We still activate the port even when failing to request resources
* to work around bugs in ancient Apple device-trees
*/
if (macio_request_resources(uap->dev, "pmac_zilog"))
printk(KERN_WARNING "%pOFn: Failed to request resource"
", port still active\n",
uap->node);
else
uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
return uart_add_one_port(&pmz_uart_reg, &uap->port);
}
/*
* That one should not be called, macio isn't really a hotswap device,
* we don't expect one of those serial ports to go away...
*/
static int pmz_detach(struct macio_dev *mdev)
{
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
if (!uap)
return -ENODEV;
uart_remove_one_port(&pmz_uart_reg, &uap->port);
if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
macio_release_resources(uap->dev);
uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
}
dev_set_drvdata(&mdev->ofdev.dev, NULL);
uap->dev = NULL;
uap->port.dev = NULL;
return 0;
}
static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
{
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
if (uap == NULL) {
printk("HRM... pmz_suspend with NULL uap\n");
return 0;
}
uart_suspend_port(&pmz_uart_reg, &uap->port);
return 0;
}
static int pmz_resume(struct macio_dev *mdev)
{
struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
if (uap == NULL)
return 0;
uart_resume_port(&pmz_uart_reg, &uap->port);
return 0;
}
/*
* Probe all ports in the system and build the ports array, we register
* with the serial layer later, so we get a proper struct device which
* allows the tty to attach properly. This is later than it used to be
* but the tty layer really wants it that way.
*/
static int __init pmz_probe(void)
{
struct device_node *node_p, *node_a, *node_b, *np;
int count = 0;
int rc;
/*
* Find all escc chips in the system
*/
for_each_node_by_name(node_p, "escc") {
/*
* First get channel A/B node pointers
*
* TODO: Add routines with proper locking to do that...
*/
node_a = node_b = NULL;
for_each_child_of_node(node_p, np) {
if (of_node_name_prefix(np, "ch-a"))
node_a = of_node_get(np);
else if (of_node_name_prefix(np, "ch-b"))
node_b = of_node_get(np);
}
if (!node_a && !node_b) {
of_node_put(node_a);
of_node_put(node_b);
printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
(!node_a) ? 'a' : 'b', node_p);
continue;
}
/*
* Fill basic fields in the port structures
*/
if (node_b != NULL) {
pmz_ports[count].mate = &pmz_ports[count+1];
pmz_ports[count+1].mate = &pmz_ports[count];
}
pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
pmz_ports[count].node = node_a;
pmz_ports[count+1].node = node_b;
pmz_ports[count].port.line = count;
pmz_ports[count+1].port.line = count+1;
/*
* Setup the ports for real
*/
rc = pmz_init_port(&pmz_ports[count]);
if (rc == 0 && node_b != NULL)
rc = pmz_init_port(&pmz_ports[count+1]);
if (rc != 0) {
of_node_put(node_a);
of_node_put(node_b);
memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
continue;
}
count += 2;
}
pmz_ports_count = count;
return 0;
}
#else
/* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
* tree to obtain the device_nodes needed to start the console before the
* macio driver. On Macs without OpenFirmware, global platform_devices take
* the place of those device_nodes.
*/
extern struct platform_device scc_a_pdev, scc_b_pdev;
static int __init pmz_init_port(struct uart_pmac_port *uap)
{
struct resource *r_ports;
int irq;
r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
if (!r_ports)
return -ENODEV;
irq = platform_get_irq(uap->pdev, 0);
if (irq < 0)
return irq;
uap->port.mapbase = r_ports->start;
uap->port.membase = (unsigned char __iomem *) r_ports->start;
uap->port.iotype = UPIO_MEM;
uap->port.irq = irq;
uap->port.uartclk = ZS_CLOCK;
uap->port.fifosize = 1;
uap->port.ops = &pmz_pops;
uap->port.type = PORT_PMAC_ZILOG;
uap->port.flags = 0;
uap->control_reg = uap->port.membase;
uap->data_reg = uap->control_reg + 4;
uap->port_type = 0;
uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
pmz_convert_to_zs(uap, CS8, 0, 9600);
return 0;
}
static int __init pmz_probe(void)
{
int err;
pmz_ports_count = 0;
pmz_ports[0].port.line = 0;
pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
pmz_ports[0].pdev = &scc_a_pdev;
err = pmz_init_port(&pmz_ports[0]);
if (err)
return err;
pmz_ports_count++;
pmz_ports[0].mate = &pmz_ports[1];
pmz_ports[1].mate = &pmz_ports[0];
pmz_ports[1].port.line = 1;
pmz_ports[1].flags = 0;
pmz_ports[1].pdev = &scc_b_pdev;
err = pmz_init_port(&pmz_ports[1]);
if (err)
return err;
pmz_ports_count++;
return 0;
}
static void pmz_dispose_port(struct uart_pmac_port *uap)
{
memset(uap, 0, sizeof(struct uart_pmac_port));
}
static int __init pmz_attach(struct platform_device *pdev)
{
struct uart_pmac_port *uap;
int i;
/* Iterate the pmz_ports array to find a matching entry */
for (i = 0; i < pmz_ports_count; i++)
if (pmz_ports[i].pdev == pdev)
break;
if (i >= pmz_ports_count)
return -ENODEV;
uap = &pmz_ports[i];
uap->port.dev = &pdev->dev;
platform_set_drvdata(pdev, uap);
return uart_add_one_port(&pmz_uart_reg, &uap->port);
}
static int __exit pmz_detach(struct platform_device *pdev)
{
struct uart_pmac_port *uap = platform_get_drvdata(pdev);
if (!uap)
return -ENODEV;
uart_remove_one_port(&pmz_uart_reg, &uap->port);
uap->port.dev = NULL;
return 0;
}
#endif /* !CONFIG_PPC_PMAC */
#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
static void pmz_console_write(struct console *con, const char *s, unsigned int count);
static int __init pmz_console_setup(struct console *co, char *options);
static struct console pmz_console = {
.name = PMACZILOG_NAME,
.write = pmz_console_write,
.device = uart_console_device,
.setup = pmz_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &pmz_uart_reg,
};
#define PMACZILOG_CONSOLE &pmz_console
#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
#define PMACZILOG_CONSOLE (NULL)
#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
/*
* Register the driver, console driver and ports with the serial
* core
*/
static int __init pmz_register(void)
{
pmz_uart_reg.nr = pmz_ports_count;
pmz_uart_reg.cons = PMACZILOG_CONSOLE;
/*
* Register this driver with the serial core
*/
return uart_register_driver(&pmz_uart_reg);
}
#ifdef CONFIG_PPC_PMAC
static const struct of_device_id pmz_match[] =
{
{
.name = "ch-a",
},
{
.name = "ch-b",
},
{},
};
MODULE_DEVICE_TABLE (of, pmz_match);
static struct macio_driver pmz_driver = {
.driver = {
.name = "pmac_zilog",
.owner = THIS_MODULE,
.of_match_table = pmz_match,
},
.probe = pmz_attach,
.remove = pmz_detach,
.suspend = pmz_suspend,
.resume = pmz_resume,
};
#else
static struct platform_driver pmz_driver = {
.remove = __exit_p(pmz_detach),
.driver = {
.name = "scc",
},
};
#endif /* !CONFIG_PPC_PMAC */
static int __init init_pmz(void)
{
int rc, i;
/*
* First, we need to do a direct OF-based probe pass. We
* do that because we want serial console up before the
* macio stuffs calls us back, and since that makes it
* easier to pass the proper number of channels to
* uart_register_driver()
*/
if (pmz_ports_count == 0)
pmz_probe();
/*
* Bail early if no port found
*/
if (pmz_ports_count == 0)
return -ENODEV;
/*
* Now we register with the serial layer
*/
rc = pmz_register();
if (rc) {
printk(KERN_ERR
"pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
"pmac_zilog: Did another serial driver already claim the minors?\n");
/* effectively "pmz_unprobe()" */
for (i=0; i < pmz_ports_count; i++)
pmz_dispose_port(&pmz_ports[i]);
return rc;
}
/*
* Then we register the macio driver itself
*/
#ifdef CONFIG_PPC_PMAC
return macio_register_driver(&pmz_driver);
#else
return platform_driver_probe(&pmz_driver, pmz_attach);
#endif
}
static void __exit exit_pmz(void)
{
int i;
#ifdef CONFIG_PPC_PMAC
/* Get rid of macio-driver (detach from macio) */
macio_unregister_driver(&pmz_driver);
#else
platform_driver_unregister(&pmz_driver);
#endif
for (i = 0; i < pmz_ports_count; i++) {
struct uart_pmac_port *uport = &pmz_ports[i];
#ifdef CONFIG_PPC_PMAC
if (uport->node != NULL)
pmz_dispose_port(uport);
#else
if (uport->pdev != NULL)
pmz_dispose_port(uport);
#endif
}
/* Unregister UART driver */
uart_unregister_driver(&pmz_uart_reg);
}
#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
static void pmz_console_putchar(struct uart_port *port, unsigned char ch)
{
struct uart_pmac_port *uap =
container_of(port, struct uart_pmac_port, port);
/* Wait for the transmit buffer to empty. */
while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
udelay(5);
write_zsdata(uap, ch);
}
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*/
static void pmz_console_write(struct console *con, const char *s, unsigned int count)
{
struct uart_pmac_port *uap = &pmz_ports[con->index];
unsigned long flags;
spin_lock_irqsave(&uap->port.lock, flags);
/* Turn of interrupts and enable the transmitter. */
write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
uart_console_write(&uap->port, s, count, pmz_console_putchar);
/* Restore the values in the registers. */
write_zsreg(uap, R1, uap->curregs[1]);
/* Don't disable the transmitter. */
spin_unlock_irqrestore(&uap->port.lock, flags);
}
/*
* Setup the serial console
*/
static int __init pmz_console_setup(struct console *co, char *options)
{
struct uart_pmac_port *uap;
struct uart_port *port;
int baud = 38400;
int bits = 8;
int parity = 'n';
int flow = 'n';
unsigned long pwr_delay;
/*
* XServe's default to 57600 bps
*/
if (of_machine_is_compatible("RackMac1,1")
|| of_machine_is_compatible("RackMac1,2")
|| of_machine_is_compatible("MacRISC4"))
baud = 57600;
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= pmz_ports_count)
co->index = 0;
uap = &pmz_ports[co->index];
#ifdef CONFIG_PPC_PMAC
if (uap->node == NULL)
return -ENODEV;
#else
if (uap->pdev == NULL)
return -ENODEV;
#endif
port = &uap->port;
/*
* Mark port as beeing a console
*/
uap->flags |= PMACZILOG_FLAG_IS_CONS;
/*
* Temporary fix for uart layer who didn't setup the spinlock yet
*/
spin_lock_init(&port->lock);
/*
* Enable the hardware
*/
pwr_delay = __pmz_startup(uap);
if (pwr_delay)
mdelay(pwr_delay);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static int __init pmz_console_init(void)
{
/* Probe ports */
pmz_probe();
if (pmz_ports_count == 0)
return -ENODEV;
/* TODO: Autoprobe console based on OF */
/* pmz_console.index = i; */
register_console(&pmz_console);
return 0;
}
console_initcall(pmz_console_init);
#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
module_init(init_pmz);
module_exit(exit_pmz);
| linux-master | drivers/tty/serial/pmac_zilog.c |
// SPDX-License-Identifier: GPL-2.0
/* sunzilog.c: Zilog serial driver for Sparc systems.
*
* Driver for Zilog serial chips found on Sun workstations and
* servers. This driver could actually be made more generic.
*
* This is based on the old drivers/sbus/char/zs.c code. A lot
* of code has been simply moved over directly from there but
* much has been rewritten. Credits therefore go out to Eddie
* C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
* work there.
*
* Copyright (C) 2002, 2006, 2007 David S. Miller ([email protected])
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/sysrq.h>
#include <linux/console.h>
#include <linux/spinlock.h>
#ifdef CONFIG_SERIO
#include <linux/serio.h>
#endif
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <linux/serial_core.h>
#include <linux/sunserialcore.h>
#include "sunzilog.h"
/* On 32-bit sparcs we need to delay after register accesses
* to accommodate sun4 systems, but we do not need to flush writes.
* On 64-bit sparc we only need to flush single writes to ensure
* completion.
*/
#ifndef CONFIG_SPARC64
#define ZSDELAY() udelay(5)
#define ZSDELAY_LONG() udelay(20)
#define ZS_WSYNC(channel) do { } while (0)
#else
#define ZSDELAY()
#define ZSDELAY_LONG()
#define ZS_WSYNC(__channel) \
readb(&((__channel)->control))
#endif
#define ZS_CLOCK 4915200 /* Zilog input clock rate. */
#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
/*
* We wrap our port structure around the generic uart_port.
*/
struct uart_sunzilog_port {
struct uart_port port;
/* IRQ servicing chain. */
struct uart_sunzilog_port *next;
/* Current values of Zilog write registers. */
unsigned char curregs[NUM_ZSREGS];
unsigned int flags;
#define SUNZILOG_FLAG_CONS_KEYB 0x00000001
#define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
#define SUNZILOG_FLAG_IS_CONS 0x00000004
#define SUNZILOG_FLAG_IS_KGDB 0x00000008
#define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
#define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
#define SUNZILOG_FLAG_REGS_HELD 0x00000040
#define SUNZILOG_FLAG_TX_STOPPED 0x00000080
#define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
#define SUNZILOG_FLAG_ESCC 0x00000200
#define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
unsigned int cflag;
unsigned char parity_mask;
unsigned char prev_status;
#ifdef CONFIG_SERIO
struct serio serio;
int serio_open;
#endif
};
static void sunzilog_putchar(struct uart_port *port, unsigned char ch);
#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
#define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
#define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
#define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
#define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
#define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
#define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
#define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
#define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
/* Reading and writing Zilog8530 registers. The delays are to make this
* driver work on the Sun4 which needs a settling delay after each chip
* register access, other machines handle this in hardware via auxiliary
* flip-flops which implement the settle time we do in software.
*
* The port lock must be held and local IRQs must be disabled
* when {read,write}_zsreg is invoked.
*/
static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
unsigned char reg)
{
unsigned char retval;
writeb(reg, &channel->control);
ZSDELAY();
retval = readb(&channel->control);
ZSDELAY();
return retval;
}
static void write_zsreg(struct zilog_channel __iomem *channel,
unsigned char reg, unsigned char value)
{
writeb(reg, &channel->control);
ZSDELAY();
writeb(value, &channel->control);
ZSDELAY();
}
static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
{
int i;
for (i = 0; i < 32; i++) {
unsigned char regval;
regval = readb(&channel->control);
ZSDELAY();
if (regval & Rx_CH_AV)
break;
regval = read_zsreg(channel, R1);
readb(&channel->data);
ZSDELAY();
if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
writeb(ERR_RES, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
}
}
}
/* This function must only be called when the TX is not busy. The UART
* port lock must be held and local interrupts disabled.
*/
static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
{
int i;
int escc;
unsigned char r15;
/* Let pending transmits finish. */
for (i = 0; i < 1000; i++) {
unsigned char stat = read_zsreg(channel, R1);
if (stat & ALL_SNT)
break;
udelay(100);
}
writeb(ERR_RES, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
sunzilog_clear_fifo(channel);
/* Disable all interrupts. */
write_zsreg(channel, R1,
regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
/* Set parity, sync config, stop bits, and clock divisor. */
write_zsreg(channel, R4, regs[R4]);
/* Set misc. TX/RX control bits. */
write_zsreg(channel, R10, regs[R10]);
/* Set TX/RX controls sans the enable bits. */
write_zsreg(channel, R3, regs[R3] & ~RxENAB);
write_zsreg(channel, R5, regs[R5] & ~TxENAB);
/* Synchronous mode config. */
write_zsreg(channel, R6, regs[R6]);
write_zsreg(channel, R7, regs[R7]);
/* Don't mess with the interrupt vector (R2, unused by us) and
* master interrupt control (R9). We make sure this is setup
* properly at probe time then never touch it again.
*/
/* Disable baud generator. */
write_zsreg(channel, R14, regs[R14] & ~BRENAB);
/* Clock mode control. */
write_zsreg(channel, R11, regs[R11]);
/* Lower and upper byte of baud rate generator divisor. */
write_zsreg(channel, R12, regs[R12]);
write_zsreg(channel, R13, regs[R13]);
/* Now rewrite R14, with BRENAB (if set). */
write_zsreg(channel, R14, regs[R14]);
/* External status interrupt control. */
write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
/* ESCC Extension Register */
r15 = read_zsreg(channel, R15);
if (r15 & 0x01) {
write_zsreg(channel, R7, regs[R7p]);
/* External status interrupt and FIFO control. */
write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
escc = 1;
} else {
/* Clear FIFO bit case it is an issue */
regs[R15] &= ~FIFOEN;
escc = 0;
}
/* Reset external status interrupts. */
write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
/* Rewrite R3/R5, this time without enables masked. */
write_zsreg(channel, R3, regs[R3]);
write_zsreg(channel, R5, regs[R5]);
/* Rewrite R1, this time without IRQ enabled masked. */
write_zsreg(channel, R1, regs[R1]);
return escc;
}
/* Reprogram the Zilog channel HW registers with the copies found in the
* software state struct. If the transmitter is busy, we defer this update
* until the next TX complete interrupt. Else, we do it right now.
*
* The UART port lock must be held and local interrupts disabled.
*/
static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
struct zilog_channel __iomem *channel)
{
if (!ZS_REGS_HELD(up)) {
if (ZS_TX_ACTIVE(up)) {
up->flags |= SUNZILOG_FLAG_REGS_HELD;
} else {
__load_zsregs(channel, up->curregs);
}
}
}
static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
{
unsigned int cur_cflag = up->cflag;
int brg, new_baud;
up->cflag &= ~CBAUD;
up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
up->curregs[R12] = (brg & 0xff);
up->curregs[R13] = (brg >> 8) & 0xff;
sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
}
static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
unsigned char ch, int is_break)
{
if (ZS_IS_KEYB(up)) {
/* Stop-A is handled by drivers/char/keyboard.c now. */
#ifdef CONFIG_SERIO
if (up->serio_open)
serio_interrupt(&up->serio, ch, 0);
#endif
} else if (ZS_IS_MOUSE(up)) {
int ret = suncore_mouse_baud_detection(ch, is_break);
switch (ret) {
case 2:
sunzilog_change_mouse_baud(up);
fallthrough;
case 1:
break;
case 0:
#ifdef CONFIG_SERIO
if (up->serio_open)
serio_interrupt(&up->serio, ch, 0);
#endif
break;
}
}
}
static struct tty_port *
sunzilog_receive_chars(struct uart_sunzilog_port *up,
struct zilog_channel __iomem *channel)
{
struct tty_port *port = NULL;
unsigned char ch, r1, flag;
if (up->port.state != NULL) /* Unopened serial console */
port = &up->port.state->port;
for (;;) {
r1 = read_zsreg(channel, R1);
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
writeb(ERR_RES, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
}
ch = readb(&channel->control);
ZSDELAY();
/* This funny hack depends upon BRK_ABRT not interfering
* with the other bits we care about in R1.
*/
if (ch & BRK_ABRT)
r1 |= BRK_ABRT;
if (!(ch & Rx_CH_AV))
break;
ch = readb(&channel->data);
ZSDELAY();
ch &= up->parity_mask;
if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
sunzilog_kbdms_receive_chars(up, ch, 0);
continue;
}
/* A real serial line, record the character and status. */
flag = TTY_NORMAL;
up->port.icount.rx++;
if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
if (r1 & BRK_ABRT) {
r1 &= ~(PAR_ERR | CRC_ERR);
up->port.icount.brk++;
if (uart_handle_break(&up->port))
continue;
}
else if (r1 & PAR_ERR)
up->port.icount.parity++;
else if (r1 & CRC_ERR)
up->port.icount.frame++;
if (r1 & Rx_OVR)
up->port.icount.overrun++;
r1 &= up->port.read_status_mask;
if (r1 & BRK_ABRT)
flag = TTY_BREAK;
else if (r1 & PAR_ERR)
flag = TTY_PARITY;
else if (r1 & CRC_ERR)
flag = TTY_FRAME;
}
if (uart_handle_sysrq_char(&up->port, ch) || !port)
continue;
if (up->port.ignore_status_mask == 0xff ||
(r1 & up->port.ignore_status_mask) == 0) {
tty_insert_flip_char(port, ch, flag);
}
if (r1 & Rx_OVR)
tty_insert_flip_char(port, 0, TTY_OVERRUN);
}
return port;
}
static void sunzilog_status_handle(struct uart_sunzilog_port *up,
struct zilog_channel __iomem *channel)
{
unsigned char status;
status = readb(&channel->control);
ZSDELAY();
writeb(RES_EXT_INT, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
if (status & BRK_ABRT) {
if (ZS_IS_MOUSE(up))
sunzilog_kbdms_receive_chars(up, 0, 1);
if (ZS_IS_CONS(up)) {
/* Wait for BREAK to deassert to avoid potentially
* confusing the PROM.
*/
while (1) {
status = readb(&channel->control);
ZSDELAY();
if (!(status & BRK_ABRT))
break;
}
sun_do_break();
return;
}
}
if (ZS_WANTS_MODEM_STATUS(up)) {
if (status & SYNC)
up->port.icount.dsr++;
/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
* But it does not tell us which bit has changed, we have to keep
* track of this ourselves.
*/
if ((status ^ up->prev_status) ^ DCD)
uart_handle_dcd_change(&up->port,
(status & DCD));
if ((status ^ up->prev_status) ^ CTS)
uart_handle_cts_change(&up->port,
(status & CTS));
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
}
up->prev_status = status;
}
static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
struct zilog_channel __iomem *channel)
{
struct circ_buf *xmit;
if (ZS_IS_CONS(up)) {
unsigned char status = readb(&channel->control);
ZSDELAY();
/* TX still busy? Just wait for the next TX done interrupt.
*
* It can occur because of how we do serial console writes. It would
* be nice to transmit console writes just like we normally would for
* a TTY line. (ie. buffered and TX interrupt driven). That is not
* easy because console writes cannot sleep. One solution might be
* to poll on enough port->xmit space becoming free. -DaveM
*/
if (!(status & Tx_BUF_EMP))
return;
}
up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
if (ZS_REGS_HELD(up)) {
__load_zsregs(channel, up->curregs);
up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
}
if (ZS_TX_STOPPED(up)) {
up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
goto ack_tx_int;
}
if (up->port.x_char) {
up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
writeb(up->port.x_char, &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
up->port.icount.tx++;
up->port.x_char = 0;
return;
}
if (up->port.state == NULL)
goto ack_tx_int;
xmit = &up->port.state->xmit;
if (uart_circ_empty(xmit))
goto ack_tx_int;
if (uart_tx_stopped(&up->port))
goto ack_tx_int;
up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
writeb(xmit->buf[xmit->tail], &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
uart_xmit_advance(&up->port, 1);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
return;
ack_tx_int:
writeb(RES_Tx_P, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
}
static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
{
struct uart_sunzilog_port *up = dev_id;
while (up) {
struct zilog_channel __iomem *channel
= ZILOG_CHANNEL_FROM_PORT(&up->port);
struct tty_port *port;
unsigned char r3;
spin_lock(&up->port.lock);
r3 = read_zsreg(channel, R3);
/* Channel A */
port = NULL;
if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
writeb(RES_H_IUS, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
if (r3 & CHARxIP)
port = sunzilog_receive_chars(up, channel);
if (r3 & CHAEXT)
sunzilog_status_handle(up, channel);
if (r3 & CHATxIP)
sunzilog_transmit_chars(up, channel);
}
spin_unlock(&up->port.lock);
if (port)
tty_flip_buffer_push(port);
/* Channel B */
up = up->next;
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
spin_lock(&up->port.lock);
port = NULL;
if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
writeb(RES_H_IUS, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
if (r3 & CHBRxIP)
port = sunzilog_receive_chars(up, channel);
if (r3 & CHBEXT)
sunzilog_status_handle(up, channel);
if (r3 & CHBTxIP)
sunzilog_transmit_chars(up, channel);
}
spin_unlock(&up->port.lock);
if (port)
tty_flip_buffer_push(port);
up = up->next;
}
return IRQ_HANDLED;
}
/* A convenient way to quickly get R0 status. The caller must _not_ hold the
* port lock, it is acquired here.
*/
static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
{
struct zilog_channel __iomem *channel;
unsigned char status;
channel = ZILOG_CHANNEL_FROM_PORT(port);
status = readb(&channel->control);
ZSDELAY();
return status;
}
/* The port lock is not held. */
static unsigned int sunzilog_tx_empty(struct uart_port *port)
{
unsigned long flags;
unsigned char status;
unsigned int ret;
spin_lock_irqsave(&port->lock, flags);
status = sunzilog_read_channel_status(port);
spin_unlock_irqrestore(&port->lock, flags);
if (status & Tx_BUF_EMP)
ret = TIOCSER_TEMT;
else
ret = 0;
return ret;
}
/* The port lock is held and interrupts are disabled. */
static unsigned int sunzilog_get_mctrl(struct uart_port *port)
{
unsigned char status;
unsigned int ret;
status = sunzilog_read_channel_status(port);
ret = 0;
if (status & DCD)
ret |= TIOCM_CAR;
if (status & SYNC)
ret |= TIOCM_DSR;
if (status & CTS)
ret |= TIOCM_CTS;
return ret;
}
/* The port lock is held and interrupts are disabled. */
static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
unsigned char set_bits, clear_bits;
set_bits = clear_bits = 0;
if (mctrl & TIOCM_RTS)
set_bits |= RTS;
else
clear_bits |= RTS;
if (mctrl & TIOCM_DTR)
set_bits |= DTR;
else
clear_bits |= DTR;
/* NOTE: Not subject to 'transmitter active' rule. */
up->curregs[R5] |= set_bits;
up->curregs[R5] &= ~clear_bits;
write_zsreg(channel, R5, up->curregs[R5]);
}
/* The port lock is held and interrupts are disabled. */
static void sunzilog_stop_tx(struct uart_port *port)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
up->flags |= SUNZILOG_FLAG_TX_STOPPED;
}
/* The port lock is held and interrupts are disabled. */
static void sunzilog_start_tx(struct uart_port *port)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
unsigned char status;
up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
status = readb(&channel->control);
ZSDELAY();
/* TX busy? Just wait for the TX done interrupt. */
if (!(status & Tx_BUF_EMP))
return;
/* Send the first character to jump-start the TX done
* IRQ sending engine.
*/
if (port->x_char) {
writeb(port->x_char, &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
port->icount.tx++;
port->x_char = 0;
} else {
struct circ_buf *xmit = &port->state->xmit;
if (uart_circ_empty(xmit))
return;
writeb(xmit->buf[xmit->tail], &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
uart_xmit_advance(port, 1);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
}
}
/* The port lock is held. */
static void sunzilog_stop_rx(struct uart_port *port)
{
struct uart_sunzilog_port *up = UART_ZILOG(port);
struct zilog_channel __iomem *channel;
if (ZS_IS_CONS(up))
return;
channel = ZILOG_CHANNEL_FROM_PORT(port);
/* Disable all RX interrupts. */
up->curregs[R1] &= ~RxINT_MASK;
sunzilog_maybe_update_regs(up, channel);
}
/* The port lock is held. */
static void sunzilog_enable_ms(struct uart_port *port)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
unsigned char new_reg;
new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
if (new_reg != up->curregs[R15]) {
up->curregs[R15] = new_reg;
/* NOTE: Not subject to 'transmitter active' rule. */
write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
}
}
/* The port lock is not held. */
static void sunzilog_break_ctl(struct uart_port *port, int break_state)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
unsigned char set_bits, clear_bits, new_reg;
unsigned long flags;
set_bits = clear_bits = 0;
if (break_state)
set_bits |= SND_BRK;
else
clear_bits |= SND_BRK;
spin_lock_irqsave(&port->lock, flags);
new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
if (new_reg != up->curregs[R5]) {
up->curregs[R5] = new_reg;
/* NOTE: Not subject to 'transmitter active' rule. */
write_zsreg(channel, R5, up->curregs[R5]);
}
spin_unlock_irqrestore(&port->lock, flags);
}
static void __sunzilog_startup(struct uart_sunzilog_port *up)
{
struct zilog_channel __iomem *channel;
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
up->prev_status = readb(&channel->control);
/* Enable receiver and transmitter. */
up->curregs[R3] |= RxENAB;
up->curregs[R5] |= TxENAB;
up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
sunzilog_maybe_update_regs(up, channel);
}
static int sunzilog_startup(struct uart_port *port)
{
struct uart_sunzilog_port *up = UART_ZILOG(port);
unsigned long flags;
if (ZS_IS_CONS(up))
return 0;
spin_lock_irqsave(&port->lock, flags);
__sunzilog_startup(up);
spin_unlock_irqrestore(&port->lock, flags);
return 0;
}
/*
* The test for ZS_IS_CONS is explained by the following e-mail:
*****
* From: Russell King <[email protected]>
* Date: Sun, 8 Dec 2002 10:18:38 +0000
*
* On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
* > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
* > and I noticed that something is not right with reference
* > counting in this case. It seems that when the console
* > is open by kernel initially, this is not accounted
* > as an open, and uart_startup is not called.
*
* That is correct. We are unable to call uart_startup when the serial
* console is initialised because it may need to allocate memory (as
* request_irq does) and the memory allocators may not have been
* initialised.
*
* 1. initialise the port into a state where it can send characters in the
* console write method.
*
* 2. don't do the actual hardware shutdown in your shutdown() method (but
* do the normal software shutdown - ie, free irqs etc)
*****
*/
static void sunzilog_shutdown(struct uart_port *port)
{
struct uart_sunzilog_port *up = UART_ZILOG(port);
struct zilog_channel __iomem *channel;
unsigned long flags;
if (ZS_IS_CONS(up))
return;
spin_lock_irqsave(&port->lock, flags);
channel = ZILOG_CHANNEL_FROM_PORT(port);
/* Disable receiver and transmitter. */
up->curregs[R3] &= ~RxENAB;
up->curregs[R5] &= ~TxENAB;
/* Disable all interrupts and BRK assertion. */
up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
up->curregs[R5] &= ~SND_BRK;
sunzilog_maybe_update_regs(up, channel);
spin_unlock_irqrestore(&port->lock, flags);
}
/* Shared by TTY driver and serial console setup. The port lock is held
* and local interrupts are disabled.
*/
static void
sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
unsigned int iflag, int brg)
{
up->curregs[R10] = NRZ;
up->curregs[R11] = TCBR | RCBR;
/* Program BAUD and clock source. */
up->curregs[R4] &= ~XCLK_MASK;
up->curregs[R4] |= X16CLK;
up->curregs[R12] = brg & 0xff;
up->curregs[R13] = (brg >> 8) & 0xff;
up->curregs[R14] = BRSRC | BRENAB;
/* Character size, stop bits, and parity. */
up->curregs[R3] &= ~RxN_MASK;
up->curregs[R5] &= ~TxN_MASK;
switch (cflag & CSIZE) {
case CS5:
up->curregs[R3] |= Rx5;
up->curregs[R5] |= Tx5;
up->parity_mask = 0x1f;
break;
case CS6:
up->curregs[R3] |= Rx6;
up->curregs[R5] |= Tx6;
up->parity_mask = 0x3f;
break;
case CS7:
up->curregs[R3] |= Rx7;
up->curregs[R5] |= Tx7;
up->parity_mask = 0x7f;
break;
case CS8:
default:
up->curregs[R3] |= Rx8;
up->curregs[R5] |= Tx8;
up->parity_mask = 0xff;
break;
}
up->curregs[R4] &= ~0x0c;
if (cflag & CSTOPB)
up->curregs[R4] |= SB2;
else
up->curregs[R4] |= SB1;
if (cflag & PARENB)
up->curregs[R4] |= PAR_ENAB;
else
up->curregs[R4] &= ~PAR_ENAB;
if (!(cflag & PARODD))
up->curregs[R4] |= PAR_EVEN;
else
up->curregs[R4] &= ~PAR_EVEN;
up->port.read_status_mask = Rx_OVR;
if (iflag & INPCK)
up->port.read_status_mask |= CRC_ERR | PAR_ERR;
if (iflag & (IGNBRK | BRKINT | PARMRK))
up->port.read_status_mask |= BRK_ABRT;
up->port.ignore_status_mask = 0;
if (iflag & IGNPAR)
up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
if (iflag & IGNBRK) {
up->port.ignore_status_mask |= BRK_ABRT;
if (iflag & IGNPAR)
up->port.ignore_status_mask |= Rx_OVR;
}
if ((cflag & CREAD) == 0)
up->port.ignore_status_mask = 0xff;
}
/* The port lock is not held. */
static void
sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
unsigned long flags;
int baud, brg;
baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
spin_lock_irqsave(&up->port.lock, flags);
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
if (UART_ENABLE_MS(&up->port, termios->c_cflag))
up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
else
up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
up->cflag = termios->c_cflag;
sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
uart_update_timeout(port, termios->c_cflag, baud);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static const char *sunzilog_type(struct uart_port *port)
{
struct uart_sunzilog_port *up = UART_ZILOG(port);
return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
}
/* We do not request/release mappings of the registers here, this
* happens at early serial probe time.
*/
static void sunzilog_release_port(struct uart_port *port)
{
}
static int sunzilog_request_port(struct uart_port *port)
{
return 0;
}
/* These do not need to do anything interesting either. */
static void sunzilog_config_port(struct uart_port *port, int flags)
{
}
/* We do not support letting the user mess with the divisor, IRQ, etc. */
static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
{
return -EINVAL;
}
#ifdef CONFIG_CONSOLE_POLL
static int sunzilog_get_poll_char(struct uart_port *port)
{
unsigned char ch, r1;
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
struct zilog_channel __iomem *channel
= ZILOG_CHANNEL_FROM_PORT(&up->port);
r1 = read_zsreg(channel, R1);
if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
writeb(ERR_RES, &channel->control);
ZSDELAY();
ZS_WSYNC(channel);
}
ch = readb(&channel->control);
ZSDELAY();
/* This funny hack depends upon BRK_ABRT not interfering
* with the other bits we care about in R1.
*/
if (ch & BRK_ABRT)
r1 |= BRK_ABRT;
if (!(ch & Rx_CH_AV))
return NO_POLL_CHAR;
ch = readb(&channel->data);
ZSDELAY();
ch &= up->parity_mask;
return ch;
}
static void sunzilog_put_poll_char(struct uart_port *port,
unsigned char ch)
{
struct uart_sunzilog_port *up =
container_of(port, struct uart_sunzilog_port, port);
sunzilog_putchar(&up->port, ch);
}
#endif /* CONFIG_CONSOLE_POLL */
static const struct uart_ops sunzilog_pops = {
.tx_empty = sunzilog_tx_empty,
.set_mctrl = sunzilog_set_mctrl,
.get_mctrl = sunzilog_get_mctrl,
.stop_tx = sunzilog_stop_tx,
.start_tx = sunzilog_start_tx,
.stop_rx = sunzilog_stop_rx,
.enable_ms = sunzilog_enable_ms,
.break_ctl = sunzilog_break_ctl,
.startup = sunzilog_startup,
.shutdown = sunzilog_shutdown,
.set_termios = sunzilog_set_termios,
.type = sunzilog_type,
.release_port = sunzilog_release_port,
.request_port = sunzilog_request_port,
.config_port = sunzilog_config_port,
.verify_port = sunzilog_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = sunzilog_get_poll_char,
.poll_put_char = sunzilog_put_poll_char,
#endif
};
static int uart_chip_count;
static struct uart_sunzilog_port *sunzilog_port_table;
static struct zilog_layout __iomem **sunzilog_chip_regs;
static struct uart_sunzilog_port *sunzilog_irq_chain;
static struct uart_driver sunzilog_reg = {
.owner = THIS_MODULE,
.driver_name = "sunzilog",
.dev_name = "ttyS",
.major = TTY_MAJOR,
};
static int __init sunzilog_alloc_tables(int num_sunzilog)
{
struct uart_sunzilog_port *up;
unsigned long size;
int num_channels = num_sunzilog * 2;
int i;
size = num_channels * sizeof(struct uart_sunzilog_port);
sunzilog_port_table = kzalloc(size, GFP_KERNEL);
if (!sunzilog_port_table)
return -ENOMEM;
for (i = 0; i < num_channels; i++) {
up = &sunzilog_port_table[i];
spin_lock_init(&up->port.lock);
if (i == 0)
sunzilog_irq_chain = up;
if (i < num_channels - 1)
up->next = up + 1;
else
up->next = NULL;
}
size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
if (!sunzilog_chip_regs) {
kfree(sunzilog_port_table);
sunzilog_irq_chain = NULL;
return -ENOMEM;
}
return 0;
}
static void sunzilog_free_tables(void)
{
kfree(sunzilog_port_table);
sunzilog_irq_chain = NULL;
kfree(sunzilog_chip_regs);
}
#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
static void __maybe_unused sunzilog_putchar(struct uart_port *port, unsigned char ch)
{
struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
int loops = ZS_PUT_CHAR_MAX_DELAY;
/* This is a timed polling loop so do not switch the explicit
* udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
*/
do {
unsigned char val = readb(&channel->control);
if (val & Tx_BUF_EMP) {
ZSDELAY();
break;
}
udelay(5);
} while (--loops);
writeb(ch, &channel->data);
ZSDELAY();
ZS_WSYNC(channel);
}
#ifdef CONFIG_SERIO
static DEFINE_SPINLOCK(sunzilog_serio_lock);
static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
{
struct uart_sunzilog_port *up = serio->port_data;
unsigned long flags;
spin_lock_irqsave(&sunzilog_serio_lock, flags);
sunzilog_putchar(&up->port, ch);
spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
return 0;
}
static int sunzilog_serio_open(struct serio *serio)
{
struct uart_sunzilog_port *up = serio->port_data;
unsigned long flags;
int ret;
spin_lock_irqsave(&sunzilog_serio_lock, flags);
if (!up->serio_open) {
up->serio_open = 1;
ret = 0;
} else
ret = -EBUSY;
spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
return ret;
}
static void sunzilog_serio_close(struct serio *serio)
{
struct uart_sunzilog_port *up = serio->port_data;
unsigned long flags;
spin_lock_irqsave(&sunzilog_serio_lock, flags);
up->serio_open = 0;
spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
}
#endif /* CONFIG_SERIO */
#ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
static void
sunzilog_console_write(struct console *con, const char *s, unsigned int count)
{
struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
unsigned long flags;
int locked = 1;
if (up->port.sysrq || oops_in_progress)
locked = spin_trylock_irqsave(&up->port.lock, flags);
else
spin_lock_irqsave(&up->port.lock, flags);
uart_console_write(&up->port, s, count, sunzilog_putchar);
udelay(2);
if (locked)
spin_unlock_irqrestore(&up->port.lock, flags);
}
static int __init sunzilog_console_setup(struct console *con, char *options)
{
struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
unsigned long flags;
int baud, brg;
if (up->port.type != PORT_SUNZILOG)
return -EINVAL;
printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
(sunzilog_reg.minor - 64) + con->index, con->index);
/* Get firmware console settings. */
sunserial_console_termios(con, up->port.dev->of_node);
/* Firmware console speed is limited to 150-->38400 baud so
* this hackish cflag thing is OK.
*/
switch (con->cflag & CBAUD) {
case B150: baud = 150; break;
case B300: baud = 300; break;
case B600: baud = 600; break;
case B1200: baud = 1200; break;
case B2400: baud = 2400; break;
case B4800: baud = 4800; break;
default: case B9600: baud = 9600; break;
case B19200: baud = 19200; break;
case B38400: baud = 38400; break;
}
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
spin_lock_irqsave(&up->port.lock, flags);
up->curregs[R15] |= BRKIE;
sunzilog_convert_to_zs(up, con->cflag, 0, brg);
sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
__sunzilog_startup(up);
spin_unlock_irqrestore(&up->port.lock, flags);
return 0;
}
static struct console sunzilog_console_ops = {
.name = "ttyS",
.write = sunzilog_console_write,
.device = uart_console_device,
.setup = sunzilog_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &sunzilog_reg,
};
static inline struct console *SUNZILOG_CONSOLE(void)
{
return &sunzilog_console_ops;
}
#else
#define SUNZILOG_CONSOLE() (NULL)
#endif
static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
{
int baud, brg;
if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
up->cflag = B1200 | CS8 | CLOCAL | CREAD;
baud = 1200;
} else {
up->cflag = B4800 | CS8 | CLOCAL | CREAD;
baud = 4800;
}
up->curregs[R15] |= BRKIE;
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
sunzilog_convert_to_zs(up, up->cflag, 0, brg);
sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
__sunzilog_startup(up);
}
#ifdef CONFIG_SERIO
static void sunzilog_register_serio(struct uart_sunzilog_port *up)
{
struct serio *serio = &up->serio;
serio->port_data = up;
serio->id.type = SERIO_RS232;
if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
serio->id.proto = SERIO_SUNKBD;
strscpy(serio->name, "zskbd", sizeof(serio->name));
} else {
serio->id.proto = SERIO_SUN;
serio->id.extra = 1;
strscpy(serio->name, "zsms", sizeof(serio->name));
}
strscpy(serio->phys,
((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
"zs/serio0" : "zs/serio1"),
sizeof(serio->phys));
serio->write = sunzilog_serio_write;
serio->open = sunzilog_serio_open;
serio->close = sunzilog_serio_close;
serio->dev.parent = up->port.dev;
serio_register_port(serio);
}
#endif
static void sunzilog_init_hw(struct uart_sunzilog_port *up)
{
struct zilog_channel __iomem *channel;
unsigned long flags;
int baud, brg;
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
spin_lock_irqsave(&up->port.lock, flags);
if (ZS_IS_CHANNEL_A(up)) {
write_zsreg(channel, R9, FHWRES);
ZSDELAY_LONG();
(void) read_zsreg(channel, R0);
}
if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
SUNZILOG_FLAG_CONS_MOUSE)) {
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
up->curregs[R3] = RxENAB | Rx8;
up->curregs[R5] = TxENAB | Tx8;
up->curregs[R6] = 0x00; /* SDLC Address */
up->curregs[R7] = 0x7E; /* SDLC Flag */
up->curregs[R9] = NV;
up->curregs[R7p] = 0x00;
sunzilog_init_kbdms(up);
/* Only enable interrupts if an ISR handler available */
if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
up->curregs[R9] |= MIE;
write_zsreg(channel, R9, up->curregs[R9]);
} else {
/* Normal serial TTY. */
up->parity_mask = 0xff;
up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
up->curregs[R3] = RxENAB | Rx8;
up->curregs[R5] = TxENAB | Tx8;
up->curregs[R6] = 0x00; /* SDLC Address */
up->curregs[R7] = 0x7E; /* SDLC Flag */
up->curregs[R9] = NV;
up->curregs[R10] = NRZ;
up->curregs[R11] = TCBR | RCBR;
baud = 9600;
brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
up->curregs[R12] = (brg & 0xff);
up->curregs[R13] = (brg >> 8) & 0xff;
up->curregs[R14] = BRSRC | BRENAB;
up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
if (__load_zsregs(channel, up->curregs)) {
up->flags |= SUNZILOG_FLAG_ESCC;
}
/* Only enable interrupts if an ISR handler available */
if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
up->curregs[R9] |= MIE;
write_zsreg(channel, R9, up->curregs[R9]);
}
spin_unlock_irqrestore(&up->port.lock, flags);
#ifdef CONFIG_SERIO
if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
SUNZILOG_FLAG_CONS_MOUSE))
sunzilog_register_serio(up);
#endif
}
static int zilog_irq;
static int zs_probe(struct platform_device *op)
{
static int kbm_inst, uart_inst;
int inst;
struct uart_sunzilog_port *up;
struct zilog_layout __iomem *rp;
int keyboard_mouse = 0;
int err;
if (of_property_present(op->dev.of_node, "keyboard"))
keyboard_mouse = 1;
/* uarts must come before keyboards/mice */
if (keyboard_mouse)
inst = uart_chip_count + kbm_inst;
else
inst = uart_inst;
sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
sizeof(struct zilog_layout),
"zs");
if (!sunzilog_chip_regs[inst])
return -ENOMEM;
rp = sunzilog_chip_regs[inst];
if (!zilog_irq)
zilog_irq = op->archdata.irqs[0];
up = &sunzilog_port_table[inst * 2];
/* Channel A */
up[0].port.mapbase = op->resource[0].start + 0x00;
up[0].port.membase = (void __iomem *) &rp->channelA;
up[0].port.iotype = UPIO_MEM;
up[0].port.irq = op->archdata.irqs[0];
up[0].port.uartclk = ZS_CLOCK;
up[0].port.fifosize = 1;
up[0].port.ops = &sunzilog_pops;
up[0].port.type = PORT_SUNZILOG;
up[0].port.flags = 0;
up[0].port.line = (inst * 2) + 0;
up[0].port.dev = &op->dev;
up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
if (keyboard_mouse)
up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
sunzilog_init_hw(&up[0]);
/* Channel B */
up[1].port.mapbase = op->resource[0].start + 0x04;
up[1].port.membase = (void __iomem *) &rp->channelB;
up[1].port.iotype = UPIO_MEM;
up[1].port.irq = op->archdata.irqs[0];
up[1].port.uartclk = ZS_CLOCK;
up[1].port.fifosize = 1;
up[1].port.ops = &sunzilog_pops;
up[1].port.type = PORT_SUNZILOG;
up[1].port.flags = 0;
up[1].port.line = (inst * 2) + 1;
up[1].port.dev = &op->dev;
up[1].flags |= 0;
up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
if (keyboard_mouse)
up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
sunzilog_init_hw(&up[1]);
if (!keyboard_mouse) {
if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
&sunzilog_reg, up[0].port.line,
false))
up->flags |= SUNZILOG_FLAG_IS_CONS;
err = uart_add_one_port(&sunzilog_reg, &up[0].port);
if (err) {
of_iounmap(&op->resource[0],
rp, sizeof(struct zilog_layout));
return err;
}
if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
&sunzilog_reg, up[1].port.line,
false))
up->flags |= SUNZILOG_FLAG_IS_CONS;
err = uart_add_one_port(&sunzilog_reg, &up[1].port);
if (err) {
uart_remove_one_port(&sunzilog_reg, &up[0].port);
of_iounmap(&op->resource[0],
rp, sizeof(struct zilog_layout));
return err;
}
uart_inst++;
} else {
printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
"is a %s\n",
dev_name(&op->dev),
(unsigned long long) up[0].port.mapbase,
op->archdata.irqs[0], sunzilog_type(&up[0].port));
printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
"is a %s\n",
dev_name(&op->dev),
(unsigned long long) up[1].port.mapbase,
op->archdata.irqs[0], sunzilog_type(&up[1].port));
kbm_inst++;
}
platform_set_drvdata(op, &up[0]);
return 0;
}
static void zs_remove_one(struct uart_sunzilog_port *up)
{
if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
#ifdef CONFIG_SERIO
serio_unregister_port(&up->serio);
#endif
} else
uart_remove_one_port(&sunzilog_reg, &up->port);
}
static int zs_remove(struct platform_device *op)
{
struct uart_sunzilog_port *up = platform_get_drvdata(op);
struct zilog_layout __iomem *regs;
zs_remove_one(&up[0]);
zs_remove_one(&up[1]);
regs = sunzilog_chip_regs[up[0].port.line / 2];
of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
return 0;
}
static const struct of_device_id zs_match[] = {
{
.name = "zs",
},
{},
};
MODULE_DEVICE_TABLE(of, zs_match);
static struct platform_driver zs_driver = {
.driver = {
.name = "zs",
.of_match_table = zs_match,
},
.probe = zs_probe,
.remove = zs_remove,
};
static int __init sunzilog_init(void)
{
struct device_node *dp;
int err;
int num_keybms = 0;
int num_sunzilog = 0;
for_each_node_by_name(dp, "zs") {
num_sunzilog++;
if (of_property_present(dp, "keyboard"))
num_keybms++;
}
if (num_sunzilog) {
err = sunzilog_alloc_tables(num_sunzilog);
if (err)
goto out;
uart_chip_count = num_sunzilog - num_keybms;
err = sunserial_register_minors(&sunzilog_reg,
uart_chip_count * 2);
if (err)
goto out_free_tables;
}
err = platform_driver_register(&zs_driver);
if (err)
goto out_unregister_uart;
if (zilog_irq) {
struct uart_sunzilog_port *up = sunzilog_irq_chain;
err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
"zs", sunzilog_irq_chain);
if (err)
goto out_unregister_driver;
/* Enable Interrupts */
while (up) {
struct zilog_channel __iomem *channel;
/* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
up->curregs[R9] |= MIE;
write_zsreg(channel, R9, up->curregs[R9]);
up = up->next;
}
}
out:
return err;
out_unregister_driver:
platform_driver_unregister(&zs_driver);
out_unregister_uart:
if (num_sunzilog) {
sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
sunzilog_reg.cons = NULL;
}
out_free_tables:
sunzilog_free_tables();
goto out;
}
static void __exit sunzilog_exit(void)
{
platform_driver_unregister(&zs_driver);
if (zilog_irq) {
struct uart_sunzilog_port *up = sunzilog_irq_chain;
/* Disable Interrupts */
while (up) {
struct zilog_channel __iomem *channel;
/* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
up->curregs[R9] &= ~MIE;
write_zsreg(channel, R9, up->curregs[R9]);
up = up->next;
}
free_irq(zilog_irq, sunzilog_irq_chain);
zilog_irq = 0;
}
if (sunzilog_reg.nr) {
sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
sunzilog_free_tables();
}
}
module_init(sunzilog_init);
module_exit(sunzilog_exit);
MODULE_AUTHOR("David S. Miller");
MODULE_DESCRIPTION("Sun Zilog serial port driver");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/sunzilog.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* High Speed Serial Ports on NXP LPC32xx SoC
*
* Authors: Kevin Wells <[email protected]>
* Roland Stigge <[email protected]>
*
* Copyright (C) 2010 NXP Semiconductors
* Copyright (C) 2012 Roland Stigge
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/nmi.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/sizes.h>
#include <linux/soc/nxp/lpc32xx-misc.h>
/*
* High Speed UART register offsets
*/
#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
#define LPC32XX_HSU_BREAK_DATA (1 << 10)
#define LPC32XX_HSU_ERROR_DATA (1 << 9)
#define LPC32XX_HSU_RX_EMPTY (1 << 8)
#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
#define LPC32XX_HSU_TX_INT_SET (1 << 6)
#define LPC32XX_HSU_RX_OE_INT (1 << 5)
#define LPC32XX_HSU_BRK_INT (1 << 4)
#define LPC32XX_HSU_FE_INT (1 << 3)
#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
#define LPC32XX_HSU_TX_INT (1 << 0)
#define LPC32XX_HSU_HRTS_INV (1 << 21)
#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
#define LPC32XX_HSU_HRTS_EN (1 << 18)
#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
#define LPC32XX_HSU_HCTS_INV (1 << 15)
#define LPC32XX_HSU_HCTS_EN (1 << 14)
#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
#define LPC32XX_HSU_BREAK (1 << 8)
#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
#define LPC32XX_HSU_RX_INT_EN (1 << 6)
#define LPC32XX_HSU_TX_INT_EN (1 << 5)
#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
#define LPC32XX_MAIN_OSC_FREQ 13000000
#define MODNAME "lpc32xx_hsuart"
struct lpc32xx_hsuart_port {
struct uart_port port;
};
#define FIFO_READ_LIMIT 128
#define MAX_PORTS 3
#define LPC32XX_TTY_NAME "ttyTX"
static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
static void wait_for_xmit_empty(struct uart_port *port)
{
unsigned int timeout = 10000;
do {
if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
port->membase))) == 0)
break;
if (--timeout == 0)
break;
udelay(1);
} while (1);
}
static void wait_for_xmit_ready(struct uart_port *port)
{
unsigned int timeout = 10000;
while (1) {
if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
port->membase))) < 32)
break;
if (--timeout == 0)
break;
udelay(1);
}
}
static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch)
{
wait_for_xmit_ready(port);
writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
}
static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
unsigned int count)
{
struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
unsigned long flags;
int locked = 1;
touch_nmi_watchdog();
local_irq_save(flags);
if (up->port.sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock(&up->port.lock);
else
spin_lock(&up->port.lock);
uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
wait_for_xmit_empty(&up->port);
if (locked)
spin_unlock(&up->port.lock);
local_irq_restore(flags);
}
static int __init lpc32xx_hsuart_console_setup(struct console *co,
char *options)
{
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (co->index >= MAX_PORTS)
co->index = 0;
port = &lpc32xx_hs_ports[co->index].port;
if (!port->membase)
return -ENODEV;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver lpc32xx_hsuart_reg;
static struct console lpc32xx_hsuart_console = {
.name = LPC32XX_TTY_NAME,
.write = lpc32xx_hsuart_console_write,
.device = uart_console_device,
.setup = lpc32xx_hsuart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &lpc32xx_hsuart_reg,
};
static int __init lpc32xx_hsuart_console_init(void)
{
register_console(&lpc32xx_hsuart_console);
return 0;
}
console_initcall(lpc32xx_hsuart_console_init);
#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
#else
#define LPC32XX_HSUART_CONSOLE NULL
#endif
static struct uart_driver lpc32xx_hs_reg = {
.owner = THIS_MODULE,
.driver_name = MODNAME,
.dev_name = LPC32XX_TTY_NAME,
.nr = MAX_PORTS,
.cons = LPC32XX_HSUART_CONSOLE,
};
static int uarts_registered;
static unsigned int __serial_get_clock_div(unsigned long uartclk,
unsigned long rate)
{
u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
u32 rate_diff;
/* Find the closest divider to get the desired clock rate */
div = uartclk / rate;
goodrate = hsu_rate = (div / 14) - 1;
if (hsu_rate != 0)
hsu_rate--;
/* Tweak divider */
l_hsu_rate = hsu_rate + 3;
rate_diff = 0xFFFFFFFF;
while (hsu_rate < l_hsu_rate) {
comprate = uartclk / ((hsu_rate + 1) * 14);
if (abs(comprate - rate) < rate_diff) {
goodrate = hsu_rate;
rate_diff = abs(comprate - rate);
}
hsu_rate++;
}
if (hsu_rate > 0xFF)
hsu_rate = 0xFF;
return goodrate;
}
static void __serial_uart_flush(struct uart_port *port)
{
int cnt = 0;
while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
(cnt++ < FIFO_READ_LIMIT))
readl(LPC32XX_HSUART_FIFO(port->membase));
}
static void __serial_lpc32xx_rx(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
unsigned int tmp, flag;
/* Read data from FIFO and push into terminal */
tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
flag = TTY_NORMAL;
port->icount.rx++;
if (tmp & LPC32XX_HSU_ERROR_DATA) {
/* Framing error */
writel(LPC32XX_HSU_FE_INT,
LPC32XX_HSUART_IIR(port->membase));
port->icount.frame++;
flag = TTY_FRAME;
tty_insert_flip_char(tport, 0, TTY_FRAME);
}
tty_insert_flip_char(tport, (tmp & 0xFF), flag);
tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
}
tty_flip_buffer_push(tport);
}
static bool serial_lpc32xx_tx_ready(struct uart_port *port)
{
u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase));
return LPC32XX_HSU_TX_LEV(level) < 64;
}
static void __serial_lpc32xx_tx(struct uart_port *port)
{
u8 ch;
uart_port_tx(port, ch,
serial_lpc32xx_tx_ready(port),
writel(ch, LPC32XX_HSUART_FIFO(port->membase)));
}
static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct tty_port *tport = &port->state->port;
u32 status;
spin_lock(&port->lock);
/* Read UART status and clear latched interrupts */
status = readl(LPC32XX_HSUART_IIR(port->membase));
if (status & LPC32XX_HSU_BRK_INT) {
/* Break received */
writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
port->icount.brk++;
uart_handle_break(port);
}
/* Framing error */
if (status & LPC32XX_HSU_FE_INT)
writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
if (status & LPC32XX_HSU_RX_OE_INT) {
/* Receive FIFO overrun */
writel(LPC32XX_HSU_RX_OE_INT,
LPC32XX_HSUART_IIR(port->membase));
port->icount.overrun++;
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
tty_flip_buffer_push(tport);
}
/* Data received? */
if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
__serial_lpc32xx_rx(port);
/* Transmit data request? */
if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
__serial_lpc32xx_tx(port);
}
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
/* port->lock is not held. */
static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
{
unsigned int ret = 0;
if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
ret = TIOCSER_TEMT;
return ret;
}
/* port->lock held by caller. */
static void serial_lpc32xx_set_mctrl(struct uart_port *port,
unsigned int mctrl)
{
/* No signals are supported on HS UARTs */
}
/* port->lock is held by caller and interrupts are disabled. */
static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
{
/* No signals are supported on HS UARTs */
return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
}
/* port->lock held by caller. */
static void serial_lpc32xx_stop_tx(struct uart_port *port)
{
u32 tmp;
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
tmp &= ~LPC32XX_HSU_TX_INT_EN;
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
}
/* port->lock held by caller. */
static void serial_lpc32xx_start_tx(struct uart_port *port)
{
u32 tmp;
__serial_lpc32xx_tx(port);
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
tmp |= LPC32XX_HSU_TX_INT_EN;
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
}
/* port->lock held by caller. */
static void serial_lpc32xx_stop_rx(struct uart_port *port)
{
u32 tmp;
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
}
/* port->lock is not held. */
static void serial_lpc32xx_break_ctl(struct uart_port *port,
int break_state)
{
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&port->lock, flags);
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
if (break_state != 0)
tmp |= LPC32XX_HSU_BREAK;
else
tmp &= ~LPC32XX_HSU_BREAK;
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
spin_unlock_irqrestore(&port->lock, flags);
}
/* port->lock is not held. */
static int serial_lpc32xx_startup(struct uart_port *port)
{
int retval;
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&port->lock, flags);
__serial_uart_flush(port);
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
LPC32XX_HSUART_IIR(port->membase));
writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
/*
* Set receiver timeout, HSU offset of 20, no break, no interrupts,
* and default FIFO trigger levels
*/
tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
spin_unlock_irqrestore(&port->lock, flags);
retval = request_irq(port->irq, serial_lpc32xx_interrupt,
0, MODNAME, port);
if (!retval)
writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
LPC32XX_HSUART_CTRL(port->membase));
return retval;
}
/* port->lock is not held. */
static void serial_lpc32xx_shutdown(struct uart_port *port)
{
u32 tmp;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
spin_unlock_irqrestore(&port->lock, flags);
free_irq(port->irq, port);
}
/* port->lock is not held. */
static void serial_lpc32xx_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
unsigned long flags;
unsigned int baud, quot;
u32 tmp;
/* Always 8-bit, no parity, 1 stop bit */
termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
termios->c_cflag |= CS8;
termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
baud = uart_get_baud_rate(port, termios, old, 0,
port->uartclk / 14);
quot = __serial_get_clock_div(port->uartclk, baud);
spin_lock_irqsave(&port->lock, flags);
/* Ignore characters? */
tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
if ((termios->c_cflag & CREAD) == 0)
tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
else
tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
writel(quot, LPC32XX_HSUART_RATE(port->membase));
uart_update_timeout(port, termios->c_cflag, baud);
spin_unlock_irqrestore(&port->lock, flags);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);
}
static const char *serial_lpc32xx_type(struct uart_port *port)
{
return MODNAME;
}
static void serial_lpc32xx_release_port(struct uart_port *port)
{
if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
port->membase = NULL;
}
release_mem_region(port->mapbase, SZ_4K);
}
}
static int serial_lpc32xx_request_port(struct uart_port *port)
{
int ret = -ENODEV;
if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
ret = 0;
if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
ret = -EBUSY;
else if (port->flags & UPF_IOREMAP) {
port->membase = ioremap(port->mapbase, SZ_4K);
if (!port->membase) {
release_mem_region(port->mapbase, SZ_4K);
ret = -ENOMEM;
}
}
}
return ret;
}
static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
{
int ret;
ret = serial_lpc32xx_request_port(port);
if (ret < 0)
return;
port->type = PORT_UART00;
port->fifosize = 64;
__serial_uart_flush(port);
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
LPC32XX_HSUART_IIR(port->membase));
writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
/* Set receiver timeout, HSU offset of 20, no break, no interrupts,
and default FIFO trigger levels */
writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
LPC32XX_HSUART_CTRL(port->membase));
}
static int serial_lpc32xx_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UART00)
ret = -EINVAL;
return ret;
}
static const struct uart_ops serial_lpc32xx_pops = {
.tx_empty = serial_lpc32xx_tx_empty,
.set_mctrl = serial_lpc32xx_set_mctrl,
.get_mctrl = serial_lpc32xx_get_mctrl,
.stop_tx = serial_lpc32xx_stop_tx,
.start_tx = serial_lpc32xx_start_tx,
.stop_rx = serial_lpc32xx_stop_rx,
.break_ctl = serial_lpc32xx_break_ctl,
.startup = serial_lpc32xx_startup,
.shutdown = serial_lpc32xx_shutdown,
.set_termios = serial_lpc32xx_set_termios,
.type = serial_lpc32xx_type,
.release_port = serial_lpc32xx_release_port,
.request_port = serial_lpc32xx_request_port,
.config_port = serial_lpc32xx_config_port,
.verify_port = serial_lpc32xx_verify_port,
};
/*
* Register a set of serial devices attached to a platform device
*/
static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
{
struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
int ret = 0;
struct resource *res;
if (uarts_registered >= MAX_PORTS) {
dev_err(&pdev->dev,
"Error: Number of possible ports exceeded (%d)!\n",
uarts_registered + 1);
return -ENXIO;
}
memset(p, 0, sizeof(*p));
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev,
"Error getting mem resource for HS UART port %d\n",
uarts_registered);
return -ENXIO;
}
p->port.mapbase = res->start;
p->port.membase = NULL;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
p->port.irq = ret;
p->port.iotype = UPIO_MEM32;
p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
p->port.regshift = 2;
p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
p->port.dev = &pdev->dev;
p->port.ops = &serial_lpc32xx_pops;
p->port.line = uarts_registered++;
spin_lock_init(&p->port.lock);
/* send port to loopback mode by default */
lpc32xx_loopback_set(p->port.mapbase, 1);
ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
platform_set_drvdata(pdev, p);
return ret;
}
/*
* Remove serial ports registered against a platform device.
*/
static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
{
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
return 0;
}
#ifdef CONFIG_PM
static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
pm_message_t state)
{
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
uart_suspend_port(&lpc32xx_hs_reg, &p->port);
return 0;
}
static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
{
struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
uart_resume_port(&lpc32xx_hs_reg, &p->port);
return 0;
}
#else
#define serial_hs_lpc32xx_suspend NULL
#define serial_hs_lpc32xx_resume NULL
#endif
static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
{ .compatible = "nxp,lpc3220-hsuart" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
static struct platform_driver serial_hs_lpc32xx_driver = {
.probe = serial_hs_lpc32xx_probe,
.remove = serial_hs_lpc32xx_remove,
.suspend = serial_hs_lpc32xx_suspend,
.resume = serial_hs_lpc32xx_resume,
.driver = {
.name = MODNAME,
.of_match_table = serial_hs_lpc32xx_dt_ids,
},
};
static int __init lpc32xx_hsuart_init(void)
{
int ret;
ret = uart_register_driver(&lpc32xx_hs_reg);
if (ret)
return ret;
ret = platform_driver_register(&serial_hs_lpc32xx_driver);
if (ret)
uart_unregister_driver(&lpc32xx_hs_reg);
return ret;
}
static void __exit lpc32xx_hsuart_exit(void)
{
platform_driver_unregister(&serial_hs_lpc32xx_driver);
uart_unregister_driver(&lpc32xx_hs_reg);
}
module_init(lpc32xx_hsuart_init);
module_exit(lpc32xx_hsuart_exit);
MODULE_AUTHOR("Kevin Wells <[email protected]>");
MODULE_AUTHOR("Roland Stigge <[email protected]>");
MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/lpc32xx_hs.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Serial base bus layer for controllers
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
* Author: Tony Lindgren <[email protected]>
*
* The serial core bus manages the serial core controller instances.
*/
#include <linux/container_of.h>
#include <linux/device.h>
#include <linux/idr.h>
#include <linux/module.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include "serial_base.h"
static bool serial_base_initialized;
static const struct device_type serial_ctrl_type = {
.name = "ctrl",
};
static const struct device_type serial_port_type = {
.name = "port",
};
static int serial_base_match(struct device *dev, struct device_driver *drv)
{
if (dev->type == &serial_ctrl_type &&
str_has_prefix(drv->name, serial_ctrl_type.name))
return 1;
if (dev->type == &serial_port_type &&
str_has_prefix(drv->name, serial_port_type.name))
return 1;
return 0;
}
static struct bus_type serial_base_bus_type = {
.name = "serial-base",
.match = serial_base_match,
};
int serial_base_driver_register(struct device_driver *driver)
{
driver->bus = &serial_base_bus_type;
return driver_register(driver);
}
void serial_base_driver_unregister(struct device_driver *driver)
{
driver_unregister(driver);
}
static int serial_base_device_init(struct uart_port *port,
struct device *dev,
struct device *parent_dev,
const struct device_type *type,
void (*release)(struct device *dev),
unsigned int ctrl_id,
unsigned int port_id)
{
device_initialize(dev);
dev->type = type;
dev->parent = parent_dev;
dev->bus = &serial_base_bus_type;
dev->release = release;
if (!serial_base_initialized) {
dev_dbg(port->dev, "uart_add_one_port() called before arch_initcall()?\n");
return -EPROBE_DEFER;
}
if (type == &serial_ctrl_type)
return dev_set_name(dev, "%s:%d", dev_name(port->dev), ctrl_id);
if (type == &serial_port_type)
return dev_set_name(dev, "%s:%d.%d", dev_name(port->dev),
ctrl_id, port_id);
return -EINVAL;
}
static void serial_base_ctrl_release(struct device *dev)
{
struct serial_ctrl_device *ctrl_dev = to_serial_base_ctrl_device(dev);
kfree(ctrl_dev);
}
void serial_base_ctrl_device_remove(struct serial_ctrl_device *ctrl_dev)
{
if (!ctrl_dev)
return;
device_del(&ctrl_dev->dev);
put_device(&ctrl_dev->dev);
}
struct serial_ctrl_device *serial_base_ctrl_add(struct uart_port *port,
struct device *parent)
{
struct serial_ctrl_device *ctrl_dev;
int err;
ctrl_dev = kzalloc(sizeof(*ctrl_dev), GFP_KERNEL);
if (!ctrl_dev)
return ERR_PTR(-ENOMEM);
ida_init(&ctrl_dev->port_ida);
err = serial_base_device_init(port, &ctrl_dev->dev,
parent, &serial_ctrl_type,
serial_base_ctrl_release,
port->ctrl_id, 0);
if (err)
goto err_put_device;
err = device_add(&ctrl_dev->dev);
if (err)
goto err_put_device;
return ctrl_dev;
err_put_device:
put_device(&ctrl_dev->dev);
return ERR_PTR(err);
}
static void serial_base_port_release(struct device *dev)
{
struct serial_port_device *port_dev = to_serial_base_port_device(dev);
kfree(port_dev);
}
struct serial_port_device *serial_base_port_add(struct uart_port *port,
struct serial_ctrl_device *ctrl_dev)
{
struct serial_port_device *port_dev;
int min = 0, max = -1; /* Use -1 for max to apply IDA defaults */
int err;
port_dev = kzalloc(sizeof(*port_dev), GFP_KERNEL);
if (!port_dev)
return ERR_PTR(-ENOMEM);
/* Device driver specified port_id vs automatic assignment? */
if (port->port_id) {
min = port->port_id;
max = port->port_id;
}
err = ida_alloc_range(&ctrl_dev->port_ida, min, max, GFP_KERNEL);
if (err < 0) {
kfree(port_dev);
return ERR_PTR(err);
}
port->port_id = err;
err = serial_base_device_init(port, &port_dev->dev,
&ctrl_dev->dev, &serial_port_type,
serial_base_port_release,
port->ctrl_id, port->port_id);
if (err)
goto err_put_device;
port_dev->port = port;
err = device_add(&port_dev->dev);
if (err)
goto err_put_device;
return port_dev;
err_put_device:
put_device(&port_dev->dev);
ida_free(&ctrl_dev->port_ida, port->port_id);
return ERR_PTR(err);
}
void serial_base_port_device_remove(struct serial_port_device *port_dev)
{
struct serial_ctrl_device *ctrl_dev;
struct device *parent;
if (!port_dev)
return;
parent = port_dev->dev.parent;
ctrl_dev = to_serial_base_ctrl_device(parent);
device_del(&port_dev->dev);
ida_free(&ctrl_dev->port_ida, port_dev->port->port_id);
put_device(&port_dev->dev);
}
static int serial_base_init(void)
{
int ret;
ret = bus_register(&serial_base_bus_type);
if (ret)
return ret;
ret = serial_base_ctrl_init();
if (ret)
goto err_bus_unregister;
ret = serial_base_port_init();
if (ret)
goto err_ctrl_exit;
serial_base_initialized = true;
return 0;
err_ctrl_exit:
serial_base_ctrl_exit();
err_bus_unregister:
bus_unregister(&serial_base_bus_type);
return ret;
}
arch_initcall(serial_base_init);
static void serial_base_exit(void)
{
serial_base_port_exit();
serial_base_ctrl_exit();
bus_unregister(&serial_base_bus_type);
}
module_exit(serial_base_exit);
MODULE_AUTHOR("Tony Lindgren <[email protected]>");
MODULE_DESCRIPTION("Serial core bus");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/serial_base_bus.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for CLPS711x serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/console.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/clps711x.h>
#include "serial_mctrl_gpio.h"
#define UART_CLPS711X_DEVNAME "ttyCL"
#define UART_CLPS711X_NR 2
#define UART_CLPS711X_MAJOR 204
#define UART_CLPS711X_MINOR 40
#define UARTDR_OFFSET (0x00)
#define UBRLCR_OFFSET (0x40)
#define UARTDR_FRMERR (1 << 8)
#define UARTDR_PARERR (1 << 9)
#define UARTDR_OVERR (1 << 10)
#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
#define UBRLCR_BREAK (1 << 12)
#define UBRLCR_PRTEN (1 << 13)
#define UBRLCR_EVENPRT (1 << 14)
#define UBRLCR_XSTOP (1 << 15)
#define UBRLCR_FIFOEN (1 << 16)
#define UBRLCR_WRDLEN5 (0 << 17)
#define UBRLCR_WRDLEN6 (1 << 17)
#define UBRLCR_WRDLEN7 (2 << 17)
#define UBRLCR_WRDLEN8 (3 << 17)
#define UBRLCR_WRDLEN_MASK (3 << 17)
struct clps711x_port {
struct uart_port port;
unsigned int tx_enabled;
int rx_irq;
struct regmap *syscon;
struct mctrl_gpios *gpios;
};
static struct uart_driver clps711x_uart = {
.owner = THIS_MODULE,
.driver_name = UART_CLPS711X_DEVNAME,
.dev_name = UART_CLPS711X_DEVNAME,
.major = UART_CLPS711X_MAJOR,
.minor = UART_CLPS711X_MINOR,
.nr = UART_CLPS711X_NR,
};
static void uart_clps711x_stop_tx(struct uart_port *port)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
if (s->tx_enabled) {
disable_irq(port->irq);
s->tx_enabled = 0;
}
}
static void uart_clps711x_start_tx(struct uart_port *port)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
if (!s->tx_enabled) {
s->tx_enabled = 1;
enable_irq(port->irq);
}
}
static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct clps711x_port *s = dev_get_drvdata(port->dev);
unsigned int status;
u16 ch;
u8 flg;
for (;;) {
u32 sysflg = 0;
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
if (sysflg & SYSFLG_URXFE)
break;
ch = readw(port->membase + UARTDR_OFFSET);
status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
ch &= 0xff;
port->icount.rx++;
flg = TTY_NORMAL;
if (unlikely(status)) {
if (status & UARTDR_PARERR)
port->icount.parity++;
else if (status & UARTDR_FRMERR)
port->icount.frame++;
else if (status & UARTDR_OVERR)
port->icount.overrun++;
status &= port->read_status_mask;
if (status & UARTDR_PARERR)
flg = TTY_PARITY;
else if (status & UARTDR_FRMERR)
flg = TTY_FRAME;
else if (status & UARTDR_OVERR)
flg = TTY_OVERRUN;
}
if (uart_handle_sysrq_char(port, ch))
continue;
if (status & port->ignore_status_mask)
continue;
uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
}
tty_flip_buffer_push(&port->state->port);
return IRQ_HANDLED;
}
static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct clps711x_port *s = dev_get_drvdata(port->dev);
struct circ_buf *xmit = &port->state->xmit;
if (port->x_char) {
writew(port->x_char, port->membase + UARTDR_OFFSET);
port->icount.tx++;
port->x_char = 0;
return IRQ_HANDLED;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
if (s->tx_enabled) {
disable_irq_nosync(port->irq);
s->tx_enabled = 0;
}
return IRQ_HANDLED;
}
while (!uart_circ_empty(xmit)) {
u32 sysflg = 0;
writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
uart_xmit_advance(port, 1);
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
if (sysflg & SYSFLG_UTXFF)
break;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
return IRQ_HANDLED;
}
static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
u32 sysflg = 0;
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
}
static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
{
unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
struct clps711x_port *s = dev_get_drvdata(port->dev);
return mctrl_gpio_get(s->gpios, &result);
}
static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
mctrl_gpio_set(s->gpios, mctrl);
}
static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
{
unsigned int ubrlcr;
ubrlcr = readl(port->membase + UBRLCR_OFFSET);
if (break_state)
ubrlcr |= UBRLCR_BREAK;
else
ubrlcr &= ~UBRLCR_BREAK;
writel(ubrlcr, port->membase + UBRLCR_OFFSET);
}
static void uart_clps711x_set_ldisc(struct uart_port *port,
struct ktermios *termios)
{
if (!port->line) {
struct clps711x_port *s = dev_get_drvdata(port->dev);
regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN,
(termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0);
}
}
static int uart_clps711x_startup(struct uart_port *port)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
/* Disable break */
writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
port->membase + UBRLCR_OFFSET);
/* Enable the port */
return regmap_update_bits(s->syscon, SYSCON_OFFSET,
SYSCON_UARTEN, SYSCON_UARTEN);
}
static void uart_clps711x_shutdown(struct uart_port *port)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
/* Disable the port */
regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
}
static void uart_clps711x_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
u32 ubrlcr;
unsigned int baud, quot;
/* Mask termios capabilities we don't support */
termios->c_cflag &= ~CMSPAR;
termios->c_iflag &= ~(BRKINT | IGNBRK);
/* Ask the core to calculate the divisor for us */
baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
port->uartclk / 16);
quot = uart_get_divisor(port, baud);
switch (termios->c_cflag & CSIZE) {
case CS5:
ubrlcr = UBRLCR_WRDLEN5;
break;
case CS6:
ubrlcr = UBRLCR_WRDLEN6;
break;
case CS7:
ubrlcr = UBRLCR_WRDLEN7;
break;
case CS8:
default:
ubrlcr = UBRLCR_WRDLEN8;
break;
}
if (termios->c_cflag & CSTOPB)
ubrlcr |= UBRLCR_XSTOP;
if (termios->c_cflag & PARENB) {
ubrlcr |= UBRLCR_PRTEN;
if (!(termios->c_cflag & PARODD))
ubrlcr |= UBRLCR_EVENPRT;
}
/* Enable FIFO */
ubrlcr |= UBRLCR_FIFOEN;
/* Set read status mask */
port->read_status_mask = UARTDR_OVERR;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
/* Set status ignore mask */
port->ignore_status_mask = 0;
if (!(termios->c_cflag & CREAD))
port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
UARTDR_FRMERR;
uart_update_timeout(port, termios->c_cflag, baud);
writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
}
static const char *uart_clps711x_type(struct uart_port *port)
{
return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
}
static void uart_clps711x_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_CLPS711X;
}
static void uart_clps711x_nop_void(struct uart_port *port)
{
}
static int uart_clps711x_nop_int(struct uart_port *port)
{
return 0;
}
static const struct uart_ops uart_clps711x_ops = {
.tx_empty = uart_clps711x_tx_empty,
.set_mctrl = uart_clps711x_set_mctrl,
.get_mctrl = uart_clps711x_get_mctrl,
.stop_tx = uart_clps711x_stop_tx,
.start_tx = uart_clps711x_start_tx,
.stop_rx = uart_clps711x_nop_void,
.break_ctl = uart_clps711x_break_ctl,
.set_ldisc = uart_clps711x_set_ldisc,
.startup = uart_clps711x_startup,
.shutdown = uart_clps711x_shutdown,
.set_termios = uart_clps711x_set_termios,
.type = uart_clps711x_type,
.config_port = uart_clps711x_config_port,
.release_port = uart_clps711x_nop_void,
.request_port = uart_clps711x_nop_int,
};
#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
static void uart_clps711x_console_putchar(struct uart_port *port, unsigned char ch)
{
struct clps711x_port *s = dev_get_drvdata(port->dev);
u32 sysflg = 0;
/* Wait for FIFO is not full */
do {
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
} while (sysflg & SYSFLG_UTXFF);
writew(ch, port->membase + UARTDR_OFFSET);
}
static void uart_clps711x_console_write(struct console *co, const char *c,
unsigned n)
{
struct uart_port *port = clps711x_uart.state[co->index].uart_port;
struct clps711x_port *s = dev_get_drvdata(port->dev);
u32 sysflg = 0;
uart_console_write(port, c, n, uart_clps711x_console_putchar);
/* Wait for transmitter to become empty */
do {
regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
} while (sysflg & SYSFLG_UBUSY);
}
static int uart_clps711x_console_setup(struct console *co, char *options)
{
int baud = 38400, bits = 8, parity = 'n', flow = 'n';
int ret, index = co->index;
struct clps711x_port *s;
struct uart_port *port;
unsigned int quot;
u32 ubrlcr;
if (index < 0 || index >= UART_CLPS711X_NR)
return -EINVAL;
port = clps711x_uart.state[index].uart_port;
if (!port)
return -ENODEV;
s = dev_get_drvdata(port->dev);
if (!options) {
u32 syscon = 0;
regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
if (syscon & SYSCON_UARTEN) {
ubrlcr = readl(port->membase + UBRLCR_OFFSET);
if (ubrlcr & UBRLCR_PRTEN) {
if (ubrlcr & UBRLCR_EVENPRT)
parity = 'e';
else
parity = 'o';
}
if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
bits = 7;
quot = ubrlcr & UBRLCR_BAUD_MASK;
baud = port->uartclk / (16 * (quot + 1));
}
} else
uart_parse_options(options, &baud, &parity, &bits, &flow);
ret = uart_set_options(port, co, baud, parity, bits, flow);
if (ret)
return ret;
return regmap_update_bits(s->syscon, SYSCON_OFFSET,
SYSCON_UARTEN, SYSCON_UARTEN);
}
static struct console clps711x_console = {
.name = UART_CLPS711X_DEVNAME,
.device = uart_console_device,
.write = uart_clps711x_console_write,
.setup = uart_clps711x_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
};
#endif
static int uart_clps711x_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct clps711x_port *s;
struct resource *res;
struct clk *uart_clk;
int irq, ret;
s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
if (!s)
return -ENOMEM;
uart_clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(uart_clk))
return PTR_ERR(uart_clk);
s->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(s->port.membase))
return PTR_ERR(s->port.membase);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
s->port.irq = irq;
s->rx_irq = platform_get_irq(pdev, 1);
if (s->rx_irq < 0)
return s->rx_irq;
s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
if (IS_ERR(s->syscon))
return PTR_ERR(s->syscon);
s->port.line = of_alias_get_id(np, "serial");
s->port.dev = &pdev->dev;
s->port.iotype = UPIO_MEM32;
s->port.mapbase = res->start;
s->port.type = PORT_CLPS711X;
s->port.fifosize = 16;
s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CLPS711X_CONSOLE);
s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
s->port.uartclk = clk_get_rate(uart_clk);
s->port.ops = &uart_clps711x_ops;
platform_set_drvdata(pdev, s);
s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0);
if (IS_ERR(s->gpios))
return PTR_ERR(s->gpios);
ret = uart_add_one_port(&clps711x_uart, &s->port);
if (ret)
return ret;
/* Disable port */
if (!uart_console(&s->port))
regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
s->tx_enabled = 1;
ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
dev_name(&pdev->dev), &s->port);
if (ret) {
uart_remove_one_port(&clps711x_uart, &s->port);
return ret;
}
ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
dev_name(&pdev->dev), &s->port);
if (ret)
uart_remove_one_port(&clps711x_uart, &s->port);
return ret;
}
static int uart_clps711x_remove(struct platform_device *pdev)
{
struct clps711x_port *s = platform_get_drvdata(pdev);
uart_remove_one_port(&clps711x_uart, &s->port);
return 0;
}
static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
{ .compatible = "cirrus,ep7209-uart", },
{ }
};
MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
static struct platform_driver clps711x_uart_platform = {
.driver = {
.name = "clps711x-uart",
.of_match_table = of_match_ptr(clps711x_uart_dt_ids),
},
.probe = uart_clps711x_probe,
.remove = uart_clps711x_remove,
};
static int __init uart_clps711x_init(void)
{
int ret;
#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
clps711x_uart.cons = &clps711x_console;
clps711x_console.data = &clps711x_uart;
#endif
ret = uart_register_driver(&clps711x_uart);
if (ret)
return ret;
return platform_driver_register(&clps711x_uart_platform);
}
module_init(uart_clps711x_init);
static void __exit uart_clps711x_exit(void)
{
platform_driver_unregister(&clps711x_uart_platform);
uart_unregister_driver(&clps711x_uart);
}
module_exit(uart_clps711x_exit);
MODULE_AUTHOR("Deep Blue Solutions Ltd");
MODULE_DESCRIPTION("CLPS711X serial driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/clps711x.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Application UART driver for:
* Freescale STMP37XX/STMP378X
* Alphascale ASM9260
*
* Author: dmitry pervushin <[email protected]>
*
* Copyright 2014 Oleksij Rempel <[email protected]>
* Provide Alphascale ASM9260 support.
* Copyright 2008-2010 Freescale Semiconductor, Inc.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/tty.h>
#include <linux/tty_driver.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/irq.h>
#include "serial_mctrl_gpio.h"
#define MXS_AUART_PORTS 5
#define MXS_AUART_FIFO_SIZE 16
#define SET_REG 0x4
#define CLR_REG 0x8
#define TOG_REG 0xc
#define AUART_CTRL0 0x00000000
#define AUART_CTRL1 0x00000010
#define AUART_CTRL2 0x00000020
#define AUART_LINECTRL 0x00000030
#define AUART_LINECTRL2 0x00000040
#define AUART_INTR 0x00000050
#define AUART_DATA 0x00000060
#define AUART_STAT 0x00000070
#define AUART_DEBUG 0x00000080
#define AUART_VERSION 0x00000090
#define AUART_AUTOBAUD 0x000000a0
#define AUART_CTRL0_SFTRST (1 << 31)
#define AUART_CTRL0_CLKGATE (1 << 30)
#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
#define AUART_CTRL2_DMAONERR (1 << 26)
#define AUART_CTRL2_TXDMAE (1 << 25)
#define AUART_CTRL2_RXDMAE (1 << 24)
#define AUART_CTRL2_CTSEN (1 << 15)
#define AUART_CTRL2_RTSEN (1 << 14)
#define AUART_CTRL2_RTS (1 << 11)
#define AUART_CTRL2_RXE (1 << 9)
#define AUART_CTRL2_TXE (1 << 8)
#define AUART_CTRL2_UARTEN (1 << 0)
#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0
#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec
#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
#define AUART_LINECTRL_SPS (1 << 7)
#define AUART_LINECTRL_WLEN_MASK 0x00000060
#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
#define AUART_LINECTRL_FEN (1 << 4)
#define AUART_LINECTRL_STP2 (1 << 3)
#define AUART_LINECTRL_EPS (1 << 2)
#define AUART_LINECTRL_PEN (1 << 1)
#define AUART_LINECTRL_BRK (1 << 0)
#define AUART_INTR_RTIEN (1 << 22)
#define AUART_INTR_TXIEN (1 << 21)
#define AUART_INTR_RXIEN (1 << 20)
#define AUART_INTR_CTSMIEN (1 << 17)
#define AUART_INTR_RTIS (1 << 6)
#define AUART_INTR_TXIS (1 << 5)
#define AUART_INTR_RXIS (1 << 4)
#define AUART_INTR_CTSMIS (1 << 1)
#define AUART_STAT_BUSY (1 << 29)
#define AUART_STAT_CTS (1 << 28)
#define AUART_STAT_TXFE (1 << 27)
#define AUART_STAT_TXFF (1 << 25)
#define AUART_STAT_RXFE (1 << 24)
#define AUART_STAT_OERR (1 << 19)
#define AUART_STAT_BERR (1 << 18)
#define AUART_STAT_PERR (1 << 17)
#define AUART_STAT_FERR (1 << 16)
#define AUART_STAT_RXCOUNT_MASK 0xffff
/*
* Start of Alphascale asm9260 defines
* This list contains only differences of existing bits
* between imx2x and asm9260
*/
#define ASM9260_HW_CTRL0 0x0000
/*
* RW. Tell the UART to execute the RX DMA Command. The
* UART will clear this bit at the end of receive execution.
*/
#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28)
/* RW. 0 use FIFO for status register; 1 use DMA */
#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25)
/*
* RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
* Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
* operation. If this bit is set to 1, a receive timeout will cause the receive
* DMA logic to terminate by filling the remaining DMA bytes with garbage data.
*/
#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24)
/*
* RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
* asserting timeout on the RX input. If the RXFIFO is not empty and the RX
* input is idle, then the watchdog counter will decrement each bit-time. Note
* 7-bit-time is added to the programmed value, so a value of zero will set
* the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
* note that the counter is reloaded at the end of each frame, so if the frame
* is 10 bits long and the timeout counter value is zero, then timeout will
* occur (when FIFO is not empty) even if the RX input is not idle. The default
* value is 0x3 (31 bit-time).
*/
#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16)
/* TIMEOUT = (100*7+1)*(1/BAUD) */
#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16)
/* TX ctrl register */
#define ASM9260_HW_CTRL1 0x0010
/*
* RW. Tell the UART to execute the TX DMA Command. The
* UART will clear this bit at the end of transmit execution.
*/
#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28)
#define ASM9260_HW_CTRL2 0x0020
/*
* RW. Receive Interrupt FIFO Level Select.
* The trigger points for the receive interrupt are as follows:
* ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
* ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
* ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
* THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
* SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
*/
#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20)
#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20)
/* RW. Same as RXIFLSEL */
#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16)
#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16)
/* RW. Set DTR. When this bit is 1, the output is 0. */
#define ASM9260_BM_CTRL2_DTR BIT(10)
/* RW. Loop Back Enable */
#define ASM9260_BM_CTRL2_LBE BIT(7)
#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0)
#define ASM9260_HW_LINECTRL 0x0030
/*
* RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
* parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
* and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
* bit is cleared stick parity is disabled.
*/
#define ASM9260_BM_LCTRL_SPS BIT(7)
/* RW. Word length */
#define ASM9260_BM_LCTRL_WLEN (3 << 5)
#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5)
#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5)
#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5)
#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5)
/*
* Interrupt register.
* contains the interrupt enables and the interrupt status bits
*/
#define ASM9260_HW_INTR 0x0040
/* Tx FIFO EMPTY Raw Interrupt enable */
#define ASM9260_BM_INTR_TFEIEN BIT(27)
/* Overrun Error Interrupt Enable. */
#define ASM9260_BM_INTR_OEIEN BIT(26)
/* Break Error Interrupt Enable. */
#define ASM9260_BM_INTR_BEIEN BIT(25)
/* Parity Error Interrupt Enable. */
#define ASM9260_BM_INTR_PEIEN BIT(24)
/* Framing Error Interrupt Enable. */
#define ASM9260_BM_INTR_FEIEN BIT(23)
/* nUARTDSR Modem Interrupt Enable. */
#define ASM9260_BM_INTR_DSRMIEN BIT(19)
/* nUARTDCD Modem Interrupt Enable. */
#define ASM9260_BM_INTR_DCDMIEN BIT(18)
/* nUARTRI Modem Interrupt Enable. */
#define ASM9260_BM_INTR_RIMIEN BIT(16)
/* Auto-Boud Timeout */
#define ASM9260_BM_INTR_ABTO BIT(13)
#define ASM9260_BM_INTR_ABEO BIT(12)
/* Tx FIFO EMPTY Raw Interrupt state */
#define ASM9260_BM_INTR_TFEIS BIT(11)
/* Overrun Error */
#define ASM9260_BM_INTR_OEIS BIT(10)
/* Break Error */
#define ASM9260_BM_INTR_BEIS BIT(9)
/* Parity Error */
#define ASM9260_BM_INTR_PEIS BIT(8)
/* Framing Error */
#define ASM9260_BM_INTR_FEIS BIT(7)
#define ASM9260_BM_INTR_DSRMIS BIT(3)
#define ASM9260_BM_INTR_DCDMIS BIT(2)
#define ASM9260_BM_INTR_RIMIS BIT(0)
/*
* RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
* time. In PIO mode, only one character can be accessed at a time. The status
* register contains the receive data flags and valid bits.
*/
#define ASM9260_HW_DATA 0x0050
#define ASM9260_HW_STAT 0x0060
/* RO. If 1, UARTAPP is present in this product. */
#define ASM9260_BM_STAT_PRESENT BIT(31)
/* RO. If 1, HISPEED is present in this product. */
#define ASM9260_BM_STAT_HISPEED BIT(30)
/* RO. Receive FIFO Full. */
#define ASM9260_BM_STAT_RXFULL BIT(26)
/* RO. The UART Debug Register contains the state of the DMA signals. */
#define ASM9260_HW_DEBUG 0x0070
/* DMA Command Run Status */
#define ASM9260_BM_DEBUG_TXDMARUN BIT(5)
#define ASM9260_BM_DEBUG_RXDMARUN BIT(4)
/* DMA Command End Status */
#define ASM9260_BM_DEBUG_TXCMDEND BIT(3)
#define ASM9260_BM_DEBUG_RXCMDEND BIT(2)
/* DMA Request Status */
#define ASM9260_BM_DEBUG_TXDMARQ BIT(1)
#define ASM9260_BM_DEBUG_RXDMARQ BIT(0)
#define ASM9260_HW_ILPR 0x0080
#define ASM9260_HW_RS485CTRL 0x0090
/*
* RW. This bit reverses the polarity of the direction control signal on the RTS
* (or DTR) pin.
* If 0, The direction control pin will be driven to logic ‘0’ when the
* transmitter has data to be sent. It will be driven to logic ‘1’ after the
* last bit of data has been transmitted.
*/
#define ASM9260_BM_RS485CTRL_ONIV BIT(5)
/* RW. Enable Auto Direction Control. */
#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4)
/*
* RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
* If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
*/
#define ASM9260_BM_RS485CTRL_PINSEL BIT(3)
/* RW. Enable Auto Address Detect (AAD). */
#define ASM9260_BM_RS485CTRL_AADEN BIT(2)
/* RW. Disable receiver. */
#define ASM9260_BM_RS485CTRL_RXDIS BIT(1)
/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
#define ASM9260_BM_RS485CTRL_RS485EN BIT(0)
#define ASM9260_HW_RS485ADRMATCH 0x00a0
/* Contains the address match value. */
#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0)
#define ASM9260_HW_RS485DLY 0x00b0
/*
* RW. Contains the direction control (RTS or DTR) delay value. This delay time
* is in periods of the baud clock.
*/
#define ASM9260_BM_RS485DLY_MASK (0xff << 0)
#define ASM9260_HW_AUTOBAUD 0x00c0
/* WO. Auto-baud time-out interrupt clear bit. */
#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9)
/* WO. End of auto-baud interrupt clear bit. */
#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8)
/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2)
/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
#define ASM9260_BM_AUTOBAUD_MODE BIT(1)
/*
* Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
* automatically cleared after auto-baud completion.
*/
#define ASM9260_BM_AUTOBAUD_START BIT(0)
#define ASM9260_HW_CTRL3 0x00d0
#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16)
/*
* RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
* pins 137 and 144.
*/
#define ASM9260_BM_CTRL3_MASTERMODE BIT(6)
/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
#define ASM9260_BM_CTRL3_SYNCMODE BIT(4)
/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
#define ASM9260_BM_CTRL3_MSBF BIT(2)
/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
#define ASM9260_BM_CTRL3_BAUD8 BIT(1)
/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
#define ASM9260_BM_CTRL3_9BIT BIT(0)
#define ASM9260_HW_ISO7816_CTRL 0x00e0
/* RW. Enable High Speed mode. */
#define ASM9260_BM_ISO7816CTRL_HS BIT(12)
/* Disable Successive Receive NACK */
#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8)
#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4)
/* Receive NACK Inhibit */
#define ASM9260_BM_ISO7816CTRL_INACK BIT(3)
#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2)
/* RW. 1 - ISO7816 mode; 0 - USART mode */
#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0)
#define ASM9260_HW_ISO7816_ERRCNT 0x00f0
/* Parity error counter. Will be cleared after reading */
#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0)
#define ASM9260_HW_ISO7816_STATUS 0x0100
/* Max number of Repetitions Reached */
#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0)
/* End of Alphascale asm9260 defines */
static struct uart_driver auart_driver;
enum mxs_auart_type {
IMX23_AUART,
IMX28_AUART,
ASM9260_AUART,
};
struct vendor_data {
const u16 *reg_offset;
};
enum {
REG_CTRL0,
REG_CTRL1,
REG_CTRL2,
REG_LINECTRL,
REG_LINECTRL2,
REG_INTR,
REG_DATA,
REG_STAT,
REG_DEBUG,
REG_VERSION,
REG_AUTOBAUD,
/* The size of the array - must be last */
REG_ARRAY_SIZE,
};
static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
[REG_CTRL0] = ASM9260_HW_CTRL0,
[REG_CTRL1] = ASM9260_HW_CTRL1,
[REG_CTRL2] = ASM9260_HW_CTRL2,
[REG_LINECTRL] = ASM9260_HW_LINECTRL,
[REG_INTR] = ASM9260_HW_INTR,
[REG_DATA] = ASM9260_HW_DATA,
[REG_STAT] = ASM9260_HW_STAT,
[REG_DEBUG] = ASM9260_HW_DEBUG,
[REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
};
static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
[REG_CTRL0] = AUART_CTRL0,
[REG_CTRL1] = AUART_CTRL1,
[REG_CTRL2] = AUART_CTRL2,
[REG_LINECTRL] = AUART_LINECTRL,
[REG_LINECTRL2] = AUART_LINECTRL2,
[REG_INTR] = AUART_INTR,
[REG_DATA] = AUART_DATA,
[REG_STAT] = AUART_STAT,
[REG_DEBUG] = AUART_DEBUG,
[REG_VERSION] = AUART_VERSION,
[REG_AUTOBAUD] = AUART_AUTOBAUD,
};
static const struct vendor_data vendor_alphascale_asm9260 = {
.reg_offset = mxs_asm9260_offsets,
};
static const struct vendor_data vendor_freescale_stmp37xx = {
.reg_offset = mxs_stmp37xx_offsets,
};
struct mxs_auart_port {
struct uart_port port;
#define MXS_AUART_DMA_ENABLED 0x2
#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
#define MXS_AUART_RTSCTS 4 /* bit 4 */
unsigned long flags;
unsigned int mctrl_prev;
enum mxs_auart_type devtype;
const struct vendor_data *vendor;
struct clk *clk;
struct clk *clk_ahb;
struct device *dev;
/* for DMA */
struct scatterlist tx_sgl;
struct dma_chan *tx_dma_chan;
void *tx_dma_buf;
struct scatterlist rx_sgl;
struct dma_chan *rx_dma_chan;
void *rx_dma_buf;
struct mctrl_gpios *gpios;
int gpio_irq[UART_GPIO_MAX];
bool ms_irq_enabled;
};
static const struct of_device_id mxs_auart_dt_ids[] = {
{
.compatible = "fsl,imx28-auart",
.data = (const void *)IMX28_AUART
}, {
.compatible = "fsl,imx23-auart",
.data = (const void *)IMX23_AUART
}, {
.compatible = "alphascale,asm9260-auart",
.data = (const void *)ASM9260_AUART
}, { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
static inline int is_imx28_auart(struct mxs_auart_port *s)
{
return s->devtype == IMX28_AUART;
}
static inline int is_asm9260_auart(struct mxs_auart_port *s)
{
return s->devtype == ASM9260_AUART;
}
static inline bool auart_dma_enabled(struct mxs_auart_port *s)
{
return s->flags & MXS_AUART_DMA_ENABLED;
}
static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
unsigned int reg)
{
return uap->vendor->reg_offset[reg];
}
static unsigned int mxs_read(const struct mxs_auart_port *uap,
unsigned int reg)
{
void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
return readl_relaxed(addr);
}
static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
unsigned int reg)
{
void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
writel_relaxed(val, addr);
}
static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
unsigned int reg)
{
void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
writel_relaxed(val, addr + SET_REG);
}
static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
unsigned int reg)
{
void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
writel_relaxed(val, addr + CLR_REG);
}
static void mxs_auart_stop_tx(struct uart_port *u);
#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
static void mxs_auart_tx_chars(struct mxs_auart_port *s);
static void dma_tx_callback(void *param)
{
struct mxs_auart_port *s = param;
struct circ_buf *xmit = &s->port.state->xmit;
dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
/* clear the bit used to serialize the DMA tx. */
clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
smp_mb__after_atomic();
/* wake up the possible processes. */
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&s->port);
mxs_auart_tx_chars(s);
}
static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
{
struct dma_async_tx_descriptor *desc;
struct scatterlist *sgl = &s->tx_sgl;
struct dma_chan *channel = s->tx_dma_chan;
u32 pio;
/* [1] : send PIO. Note, the first pio word is CTRL1. */
pio = AUART_CTRL1_XFER_COUNT(size);
desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
1, DMA_TRANS_NONE, 0);
if (!desc) {
dev_err(s->dev, "step 1 error\n");
return -EINVAL;
}
/* [2] : set DMA buffer. */
sg_init_one(sgl, s->tx_dma_buf, size);
dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
desc = dmaengine_prep_slave_sg(channel, sgl,
1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(s->dev, "step 2 error\n");
return -EINVAL;
}
/* [3] : submit the DMA */
desc->callback = dma_tx_callback;
desc->callback_param = s;
dmaengine_submit(desc);
dma_async_issue_pending(channel);
return 0;
}
static void mxs_auart_tx_chars(struct mxs_auart_port *s)
{
struct circ_buf *xmit = &s->port.state->xmit;
bool pending;
u8 ch;
if (auart_dma_enabled(s)) {
u32 i = 0;
int size;
void *buffer = s->tx_dma_buf;
if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
return;
while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
size = min_t(u32, UART_XMIT_SIZE - i,
CIRC_CNT_TO_END(xmit->head,
xmit->tail,
UART_XMIT_SIZE));
memcpy(buffer + i, xmit->buf + xmit->tail, size);
xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
i += size;
if (i >= UART_XMIT_SIZE)
break;
}
if (uart_tx_stopped(&s->port))
mxs_auart_stop_tx(&s->port);
if (i) {
mxs_auart_dma_tx(s, i);
} else {
clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
smp_mb__after_atomic();
}
return;
}
pending = uart_port_tx(&s->port, ch,
!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF),
mxs_write(ch, s, REG_DATA));
if (pending)
mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
else
mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
}
static void mxs_auart_rx_char(struct mxs_auart_port *s)
{
u32 stat;
u8 c, flag;
c = mxs_read(s, REG_DATA);
stat = mxs_read(s, REG_STAT);
flag = TTY_NORMAL;
s->port.icount.rx++;
if (stat & AUART_STAT_BERR) {
s->port.icount.brk++;
if (uart_handle_break(&s->port))
goto out;
} else if (stat & AUART_STAT_PERR) {
s->port.icount.parity++;
} else if (stat & AUART_STAT_FERR) {
s->port.icount.frame++;
}
/*
* Mask off conditions which should be ingored.
*/
stat &= s->port.read_status_mask;
if (stat & AUART_STAT_BERR) {
flag = TTY_BREAK;
} else if (stat & AUART_STAT_PERR)
flag = TTY_PARITY;
else if (stat & AUART_STAT_FERR)
flag = TTY_FRAME;
if (stat & AUART_STAT_OERR)
s->port.icount.overrun++;
if (uart_handle_sysrq_char(&s->port, c))
goto out;
uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
out:
mxs_write(stat, s, REG_STAT);
}
static void mxs_auart_rx_chars(struct mxs_auart_port *s)
{
u32 stat = 0;
for (;;) {
stat = mxs_read(s, REG_STAT);
if (stat & AUART_STAT_RXFE)
break;
mxs_auart_rx_char(s);
}
mxs_write(stat, s, REG_STAT);
tty_flip_buffer_push(&s->port.state->port);
}
static int mxs_auart_request_port(struct uart_port *u)
{
return 0;
}
static int mxs_auart_verify_port(struct uart_port *u,
struct serial_struct *ser)
{
if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
return -EINVAL;
return 0;
}
static void mxs_auart_config_port(struct uart_port *u, int flags)
{
}
static const char *mxs_auart_type(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
return dev_name(s->dev);
}
static void mxs_auart_release_port(struct uart_port *u)
{
}
static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
{
struct mxs_auart_port *s = to_auart_port(u);
u32 ctrl = mxs_read(s, REG_CTRL2);
ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
if (mctrl & TIOCM_RTS) {
if (uart_cts_enabled(u))
ctrl |= AUART_CTRL2_RTSEN;
else
ctrl |= AUART_CTRL2_RTS;
}
mxs_write(ctrl, s, REG_CTRL2);
mctrl_gpio_set(s->gpios, mctrl);
}
#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
{
u32 mctrl_diff;
mctrl_diff = mctrl ^ s->mctrl_prev;
s->mctrl_prev = mctrl;
if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
s->port.state != NULL) {
if (mctrl_diff & TIOCM_RI)
s->port.icount.rng++;
if (mctrl_diff & TIOCM_DSR)
s->port.icount.dsr++;
if (mctrl_diff & TIOCM_CD)
uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
if (mctrl_diff & TIOCM_CTS)
uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
wake_up_interruptible(&s->port.state->port.delta_msr_wait);
}
return mctrl;
}
static u32 mxs_auart_get_mctrl(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
u32 stat = mxs_read(s, REG_STAT);
u32 mctrl = 0;
if (stat & AUART_STAT_CTS)
mctrl |= TIOCM_CTS;
return mctrl_gpio_get(s->gpios, &mctrl);
}
/*
* Enable modem status interrupts
*/
static void mxs_auart_enable_ms(struct uart_port *port)
{
struct mxs_auart_port *s = to_auart_port(port);
/*
* Interrupt should not be enabled twice
*/
if (s->ms_irq_enabled)
return;
s->ms_irq_enabled = true;
if (s->gpio_irq[UART_GPIO_CTS] >= 0)
enable_irq(s->gpio_irq[UART_GPIO_CTS]);
/* TODO: enable AUART_INTR_CTSMIEN otherwise */
if (s->gpio_irq[UART_GPIO_DSR] >= 0)
enable_irq(s->gpio_irq[UART_GPIO_DSR]);
if (s->gpio_irq[UART_GPIO_RI] >= 0)
enable_irq(s->gpio_irq[UART_GPIO_RI]);
if (s->gpio_irq[UART_GPIO_DCD] >= 0)
enable_irq(s->gpio_irq[UART_GPIO_DCD]);
}
/*
* Disable modem status interrupts
*/
static void mxs_auart_disable_ms(struct uart_port *port)
{
struct mxs_auart_port *s = to_auart_port(port);
/*
* Interrupt should not be disabled twice
*/
if (!s->ms_irq_enabled)
return;
s->ms_irq_enabled = false;
if (s->gpio_irq[UART_GPIO_CTS] >= 0)
disable_irq(s->gpio_irq[UART_GPIO_CTS]);
/* TODO: disable AUART_INTR_CTSMIEN otherwise */
if (s->gpio_irq[UART_GPIO_DSR] >= 0)
disable_irq(s->gpio_irq[UART_GPIO_DSR]);
if (s->gpio_irq[UART_GPIO_RI] >= 0)
disable_irq(s->gpio_irq[UART_GPIO_RI]);
if (s->gpio_irq[UART_GPIO_DCD] >= 0)
disable_irq(s->gpio_irq[UART_GPIO_DCD]);
}
static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
static void dma_rx_callback(void *arg)
{
struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
struct tty_port *port = &s->port.state->port;
int count;
u32 stat;
dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
stat = mxs_read(s, REG_STAT);
stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
AUART_STAT_PERR | AUART_STAT_FERR);
count = stat & AUART_STAT_RXCOUNT_MASK;
tty_insert_flip_string(port, s->rx_dma_buf, count);
mxs_write(stat, s, REG_STAT);
tty_flip_buffer_push(port);
/* start the next DMA for RX. */
mxs_auart_dma_prep_rx(s);
}
static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
{
struct dma_async_tx_descriptor *desc;
struct scatterlist *sgl = &s->rx_sgl;
struct dma_chan *channel = s->rx_dma_chan;
u32 pio[1];
/* [1] : send PIO */
pio[0] = AUART_CTRL0_RXTO_ENABLE
| AUART_CTRL0_RXTIMEOUT(0x80)
| AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
1, DMA_TRANS_NONE, 0);
if (!desc) {
dev_err(s->dev, "step 1 error\n");
return -EINVAL;
}
/* [2] : send DMA request */
sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(s->dev, "step 2 error\n");
return -1;
}
/* [3] : submit the DMA, but do not issue it. */
desc->callback = dma_rx_callback;
desc->callback_param = s;
dmaengine_submit(desc);
dma_async_issue_pending(channel);
return 0;
}
static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
{
if (s->tx_dma_chan) {
dma_release_channel(s->tx_dma_chan);
s->tx_dma_chan = NULL;
}
if (s->rx_dma_chan) {
dma_release_channel(s->rx_dma_chan);
s->rx_dma_chan = NULL;
}
kfree(s->tx_dma_buf);
kfree(s->rx_dma_buf);
s->tx_dma_buf = NULL;
s->rx_dma_buf = NULL;
}
static void mxs_auart_dma_exit(struct mxs_auart_port *s)
{
mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
s, REG_CTRL2);
mxs_auart_dma_exit_channel(s);
s->flags &= ~MXS_AUART_DMA_ENABLED;
clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
}
static int mxs_auart_dma_init(struct mxs_auart_port *s)
{
if (auart_dma_enabled(s))
return 0;
/* init for RX */
s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
if (!s->rx_dma_chan)
goto err_out;
s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
if (!s->rx_dma_buf)
goto err_out;
/* init for TX */
s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
if (!s->tx_dma_chan)
goto err_out;
s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
if (!s->tx_dma_buf)
goto err_out;
/* set the flags */
s->flags |= MXS_AUART_DMA_ENABLED;
dev_dbg(s->dev, "enabled the DMA support.");
/* The DMA buffer is now the FIFO the TTY subsystem can use */
s->port.fifosize = UART_XMIT_SIZE;
return 0;
err_out:
mxs_auart_dma_exit_channel(s);
return -EINVAL;
}
#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
static void mxs_auart_settermios(struct uart_port *u,
struct ktermios *termios,
const struct ktermios *old)
{
struct mxs_auart_port *s = to_auart_port(u);
u32 ctrl, ctrl2, div;
unsigned int cflag, baud, baud_min, baud_max;
cflag = termios->c_cflag;
ctrl = AUART_LINECTRL_FEN;
ctrl2 = mxs_read(s, REG_CTRL2);
ctrl |= AUART_LINECTRL_WLEN(tty_get_char_size(cflag));
/* parity */
if (cflag & PARENB) {
ctrl |= AUART_LINECTRL_PEN;
if ((cflag & PARODD) == 0)
ctrl |= AUART_LINECTRL_EPS;
if (cflag & CMSPAR)
ctrl |= AUART_LINECTRL_SPS;
}
u->read_status_mask = AUART_STAT_OERR;
if (termios->c_iflag & INPCK)
u->read_status_mask |= AUART_STAT_PERR;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
u->read_status_mask |= AUART_STAT_BERR;
/*
* Characters to ignore
*/
u->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
u->ignore_status_mask |= AUART_STAT_PERR;
if (termios->c_iflag & IGNBRK) {
u->ignore_status_mask |= AUART_STAT_BERR;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
u->ignore_status_mask |= AUART_STAT_OERR;
}
/*
* ignore all characters if CREAD is not set
*/
if (cflag & CREAD)
ctrl2 |= AUART_CTRL2_RXE;
else
ctrl2 &= ~AUART_CTRL2_RXE;
/* figure out the stop bits requested */
if (cflag & CSTOPB)
ctrl |= AUART_LINECTRL_STP2;
/* figure out the hardware flow control settings */
ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
if (cflag & CRTSCTS) {
/*
* The DMA has a bug(see errata:2836) in mx23.
* So we can not implement the DMA for auart in mx23,
* we can only implement the DMA support for auart
* in mx28.
*/
if (is_imx28_auart(s)
&& test_bit(MXS_AUART_RTSCTS, &s->flags)) {
if (!mxs_auart_dma_init(s))
/* enable DMA tranfer */
ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
| AUART_CTRL2_DMAONERR;
}
/* Even if RTS is GPIO line RTSEN can be enabled because
* the pinctrl configuration decides about RTS pin function */
ctrl2 |= AUART_CTRL2_RTSEN;
if (CTS_AT_AUART())
ctrl2 |= AUART_CTRL2_CTSEN;
}
/* set baud rate */
if (is_asm9260_auart(s)) {
baud = uart_get_baud_rate(u, termios, old,
u->uartclk * 4 / 0x3FFFFF,
u->uartclk / 16);
div = u->uartclk * 4 / baud;
} else {
baud_min = DIV_ROUND_UP(u->uartclk * 32,
AUART_LINECTRL_BAUD_DIV_MAX);
baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
}
ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
mxs_write(ctrl, s, REG_LINECTRL);
mxs_write(ctrl2, s, REG_CTRL2);
uart_update_timeout(u, termios->c_cflag, baud);
/* prepare for the DMA RX. */
if (auart_dma_enabled(s) &&
!test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
if (!mxs_auart_dma_prep_rx(s)) {
/* Disable the normal RX interrupt. */
mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
s, REG_INTR);
} else {
mxs_auart_dma_exit(s);
dev_err(s->dev, "We can not start up the DMA.\n");
}
}
/* CTS flow-control and modem-status interrupts */
if (UART_ENABLE_MS(u, termios->c_cflag))
mxs_auart_enable_ms(u);
else
mxs_auart_disable_ms(u);
}
static void mxs_auart_set_ldisc(struct uart_port *port,
struct ktermios *termios)
{
if (termios->c_line == N_PPS) {
port->flags |= UPF_HARDPPS_CD;
mxs_auart_enable_ms(port);
} else {
port->flags &= ~UPF_HARDPPS_CD;
}
}
static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
{
u32 istat;
struct mxs_auart_port *s = context;
u32 mctrl_temp = s->mctrl_prev;
u32 stat = mxs_read(s, REG_STAT);
istat = mxs_read(s, REG_INTR);
/* ack irq */
mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
| AUART_INTR_CTSMIS), s, REG_INTR);
/*
* Dealing with GPIO interrupt
*/
if (irq == s->gpio_irq[UART_GPIO_CTS] ||
irq == s->gpio_irq[UART_GPIO_DCD] ||
irq == s->gpio_irq[UART_GPIO_DSR] ||
irq == s->gpio_irq[UART_GPIO_RI])
mxs_auart_modem_status(s,
mctrl_gpio_get(s->gpios, &mctrl_temp));
if (istat & AUART_INTR_CTSMIS) {
if (CTS_AT_AUART() && s->ms_irq_enabled)
uart_handle_cts_change(&s->port,
stat & AUART_STAT_CTS);
mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
istat &= ~AUART_INTR_CTSMIS;
}
if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
if (!auart_dma_enabled(s))
mxs_auart_rx_chars(s);
istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
}
if (istat & AUART_INTR_TXIS) {
mxs_auart_tx_chars(s);
istat &= ~AUART_INTR_TXIS;
}
return IRQ_HANDLED;
}
static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
{
int i;
unsigned int reg;
mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
for (i = 0; i < 10000; i++) {
reg = mxs_read(s, REG_CTRL0);
if (!(reg & AUART_CTRL0_SFTRST))
break;
udelay(3);
}
mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
}
static void mxs_auart_reset_assert(struct mxs_auart_port *s)
{
int i;
u32 reg;
reg = mxs_read(s, REG_CTRL0);
/* if already in reset state, keep it untouched */
if (reg & AUART_CTRL0_SFTRST)
return;
mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
for (i = 0; i < 1000; i++) {
reg = mxs_read(s, REG_CTRL0);
/* reset is finished when the clock is gated */
if (reg & AUART_CTRL0_CLKGATE)
return;
udelay(10);
}
dev_err(s->dev, "Failed to reset the unit.");
}
static int mxs_auart_startup(struct uart_port *u)
{
int ret;
struct mxs_auart_port *s = to_auart_port(u);
ret = clk_prepare_enable(s->clk);
if (ret)
return ret;
if (uart_console(u)) {
mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
} else {
/* reset the unit to a well known state */
mxs_auart_reset_assert(s);
mxs_auart_reset_deassert(s);
}
mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
s, REG_INTR);
/* Reset FIFO size (it could have changed if DMA was enabled) */
u->fifosize = MXS_AUART_FIFO_SIZE;
/*
* Enable fifo so all four bytes of a DMA word are written to
* output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
*/
mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
/* get initial status of modem lines */
mctrl_gpio_get(s->gpios, &s->mctrl_prev);
s->ms_irq_enabled = false;
return 0;
}
static void mxs_auart_shutdown(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
mxs_auart_disable_ms(u);
if (auart_dma_enabled(s))
mxs_auart_dma_exit(s);
if (uart_console(u)) {
mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
AUART_INTR_CTSMIEN, s, REG_INTR);
mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
} else {
mxs_auart_reset_assert(s);
}
clk_disable_unprepare(s->clk);
}
static unsigned int mxs_auart_tx_empty(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
if ((mxs_read(s, REG_STAT) &
(AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
return TIOCSER_TEMT;
return 0;
}
static void mxs_auart_start_tx(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
/* enable transmitter */
mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
mxs_auart_tx_chars(s);
}
static void mxs_auart_stop_tx(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
}
static void mxs_auart_stop_rx(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
}
static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
{
struct mxs_auart_port *s = to_auart_port(u);
if (ctl)
mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
else
mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
}
static const struct uart_ops mxs_auart_ops = {
.tx_empty = mxs_auart_tx_empty,
.start_tx = mxs_auart_start_tx,
.stop_tx = mxs_auart_stop_tx,
.stop_rx = mxs_auart_stop_rx,
.enable_ms = mxs_auart_enable_ms,
.break_ctl = mxs_auart_break_ctl,
.set_mctrl = mxs_auart_set_mctrl,
.get_mctrl = mxs_auart_get_mctrl,
.startup = mxs_auart_startup,
.shutdown = mxs_auart_shutdown,
.set_termios = mxs_auart_settermios,
.set_ldisc = mxs_auart_set_ldisc,
.type = mxs_auart_type,
.release_port = mxs_auart_release_port,
.request_port = mxs_auart_request_port,
.config_port = mxs_auart_config_port,
.verify_port = mxs_auart_verify_port,
};
static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch)
{
struct mxs_auart_port *s = to_auart_port(port);
unsigned int to = 1000;
while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
if (!to--)
break;
udelay(1);
}
mxs_write(ch, s, REG_DATA);
}
static void
auart_console_write(struct console *co, const char *str, unsigned int count)
{
struct mxs_auart_port *s;
struct uart_port *port;
unsigned int old_ctrl0, old_ctrl2;
unsigned int to = 20000;
if (co->index >= MXS_AUART_PORTS || co->index < 0)
return;
s = auart_port[co->index];
port = &s->port;
clk_enable(s->clk);
/* First save the CR then disable the interrupts */
old_ctrl2 = mxs_read(s, REG_CTRL2);
old_ctrl0 = mxs_read(s, REG_CTRL0);
mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
uart_console_write(port, str, count, mxs_auart_console_putchar);
/* Finally, wait for transmitter to become empty ... */
while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
udelay(1);
if (!to--)
break;
}
/*
* ... and restore the TCR if we waited long enough for the transmitter
* to be idle. This might keep the transmitter enabled although it is
* unused, but that is better than to disable it while it is still
* transmitting.
*/
if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
mxs_write(old_ctrl0, s, REG_CTRL0);
mxs_write(old_ctrl2, s, REG_CTRL2);
}
clk_disable(s->clk);
}
static void __init
auart_console_get_options(struct mxs_auart_port *s, int *baud,
int *parity, int *bits)
{
struct uart_port *port = &s->port;
unsigned int lcr_h, quot;
if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
return;
lcr_h = mxs_read(s, REG_LINECTRL);
*parity = 'n';
if (lcr_h & AUART_LINECTRL_PEN) {
if (lcr_h & AUART_LINECTRL_EPS)
*parity = 'e';
else
*parity = 'o';
}
if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(7))
*bits = 7;
else
*bits = 8;
quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
>> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
>> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
if (quot == 0)
quot = 1;
*baud = (port->uartclk << 2) / quot;
}
static int __init
auart_console_setup(struct console *co, char *options)
{
struct mxs_auart_port *s;
int baud = 9600;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
co->index = 0;
s = auart_port[co->index];
if (!s)
return -ENODEV;
ret = clk_prepare_enable(s->clk);
if (ret)
return ret;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
else
auart_console_get_options(s, &baud, &parity, &bits);
ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
clk_disable_unprepare(s->clk);
return ret;
}
static struct console auart_console = {
.name = "ttyAPP",
.write = auart_console_write,
.device = uart_console_device,
.setup = auart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &auart_driver,
};
#endif
static struct uart_driver auart_driver = {
.owner = THIS_MODULE,
.driver_name = "ttyAPP",
.dev_name = "ttyAPP",
.major = 0,
.minor = 0,
.nr = MXS_AUART_PORTS,
#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
.cons = &auart_console,
#endif
};
static void mxs_init_regs(struct mxs_auart_port *s)
{
if (is_asm9260_auart(s))
s->vendor = &vendor_alphascale_asm9260;
else
s->vendor = &vendor_freescale_stmp37xx;
}
static int mxs_get_clks(struct mxs_auart_port *s,
struct platform_device *pdev)
{
int err;
if (!is_asm9260_auart(s)) {
s->clk = devm_clk_get(&pdev->dev, NULL);
return PTR_ERR_OR_ZERO(s->clk);
}
s->clk = devm_clk_get(s->dev, "mod");
if (IS_ERR(s->clk)) {
dev_err(s->dev, "Failed to get \"mod\" clk\n");
return PTR_ERR(s->clk);
}
s->clk_ahb = devm_clk_get(s->dev, "ahb");
if (IS_ERR(s->clk_ahb)) {
dev_err(s->dev, "Failed to get \"ahb\" clk\n");
return PTR_ERR(s->clk_ahb);
}
err = clk_prepare_enable(s->clk_ahb);
if (err) {
dev_err(s->dev, "Failed to enable ahb_clk!\n");
return err;
}
err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
if (err) {
dev_err(s->dev, "Failed to set rate!\n");
goto disable_clk_ahb;
}
err = clk_prepare_enable(s->clk);
if (err) {
dev_err(s->dev, "Failed to enable clk!\n");
goto disable_clk_ahb;
}
return 0;
disable_clk_ahb:
clk_disable_unprepare(s->clk_ahb);
return err;
}
static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
{
enum mctrl_gpio_idx i;
struct gpio_desc *gpiod;
s->gpios = mctrl_gpio_init_noauto(dev, 0);
if (IS_ERR(s->gpios))
return PTR_ERR(s->gpios);
/* Block (enabled before) DMA option if RTS or CTS is GPIO line */
if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
if (test_bit(MXS_AUART_RTSCTS, &s->flags))
dev_warn(dev,
"DMA and flow control via gpio may cause some problems. DMA disabled!\n");
clear_bit(MXS_AUART_RTSCTS, &s->flags);
}
for (i = 0; i < UART_GPIO_MAX; i++) {
gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
if (gpiod && (gpiod_get_direction(gpiod) == 1))
s->gpio_irq[i] = gpiod_to_irq(gpiod);
else
s->gpio_irq[i] = -EINVAL;
}
return 0;
}
static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
{
enum mctrl_gpio_idx i;
for (i = 0; i < UART_GPIO_MAX; i++)
if (s->gpio_irq[i] >= 0)
free_irq(s->gpio_irq[i], s);
}
static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
{
int *irq = s->gpio_irq;
enum mctrl_gpio_idx i;
int err = 0;
for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
if (irq[i] < 0)
continue;
irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
err = request_irq(irq[i], mxs_auart_irq_handle,
IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
if (err)
dev_err(s->dev, "%s - Can't get %d irq\n",
__func__, irq[i]);
}
/*
* If something went wrong, rollback.
* Be careful: i may be unsigned.
*/
while (err && (i-- > 0))
if (irq[i] >= 0)
free_irq(irq[i], s);
return err;
}
static int mxs_auart_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct mxs_auart_port *s;
u32 version;
int ret, irq;
struct resource *r;
s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
if (!s)
return -ENOMEM;
s->port.dev = &pdev->dev;
s->dev = &pdev->dev;
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
return ret;
}
s->port.line = ret;
if (of_property_read_bool(np, "uart-has-rtscts") ||
of_property_read_bool(np, "fsl,uart-has-rtscts") /* deprecated */)
set_bit(MXS_AUART_RTSCTS, &s->flags);
if (s->port.line >= ARRAY_SIZE(auart_port)) {
dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
return -EINVAL;
}
s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev);
ret = mxs_get_clks(s, pdev);
if (ret)
return ret;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
ret = -ENXIO;
goto out_disable_clks;
}
s->port.mapbase = r->start;
s->port.membase = ioremap(r->start, resource_size(r));
if (!s->port.membase) {
ret = -ENOMEM;
goto out_disable_clks;
}
s->port.ops = &mxs_auart_ops;
s->port.iotype = UPIO_MEM;
s->port.fifosize = MXS_AUART_FIFO_SIZE;
s->port.uartclk = clk_get_rate(s->clk);
s->port.type = PORT_IMX;
s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
mxs_init_regs(s);
s->mctrl_prev = 0;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
goto out_iounmap;
}
s->port.irq = irq;
ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
dev_name(&pdev->dev), s);
if (ret)
goto out_iounmap;
platform_set_drvdata(pdev, s);
ret = mxs_auart_init_gpios(s, &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
goto out_iounmap;
}
/*
* Get the GPIO lines IRQ
*/
ret = mxs_auart_request_gpio_irq(s);
if (ret)
goto out_iounmap;
auart_port[s->port.line] = s;
mxs_auart_reset_deassert(s);
ret = uart_add_one_port(&auart_driver, &s->port);
if (ret)
goto out_free_qpio_irq;
/* ASM9260 don't have version reg */
if (is_asm9260_auart(s)) {
dev_info(&pdev->dev, "Found APPUART ASM9260\n");
} else {
version = mxs_read(s, REG_VERSION);
dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
(version >> 24) & 0xff,
(version >> 16) & 0xff, version & 0xffff);
}
return 0;
out_free_qpio_irq:
mxs_auart_free_gpio_irq(s);
auart_port[pdev->id] = NULL;
out_iounmap:
iounmap(s->port.membase);
out_disable_clks:
if (is_asm9260_auart(s)) {
clk_disable_unprepare(s->clk);
clk_disable_unprepare(s->clk_ahb);
}
return ret;
}
static int mxs_auart_remove(struct platform_device *pdev)
{
struct mxs_auart_port *s = platform_get_drvdata(pdev);
uart_remove_one_port(&auart_driver, &s->port);
auart_port[pdev->id] = NULL;
mxs_auart_free_gpio_irq(s);
iounmap(s->port.membase);
if (is_asm9260_auart(s)) {
clk_disable_unprepare(s->clk);
clk_disable_unprepare(s->clk_ahb);
}
return 0;
}
static struct platform_driver mxs_auart_driver = {
.probe = mxs_auart_probe,
.remove = mxs_auart_remove,
.driver = {
.name = "mxs-auart",
.of_match_table = mxs_auart_dt_ids,
},
};
static int __init mxs_auart_init(void)
{
int r;
r = uart_register_driver(&auart_driver);
if (r)
goto out;
r = platform_driver_register(&mxs_auart_driver);
if (r)
goto out_err;
return 0;
out_err:
uart_unregister_driver(&auart_driver);
out:
return r;
}
static void __exit mxs_auart_exit(void)
{
platform_driver_unregister(&mxs_auart_driver);
uart_unregister_driver(&auart_driver);
}
module_init(mxs_auart_init);
module_exit(mxs_auart_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Freescale MXS application uart driver");
MODULE_ALIAS("platform:mxs-auart");
| linux-master | drivers/tty/serial/mxs-auart.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for msm7k serial device and console
*
* Copyright (C) 2007 Google, Inc.
* Author: Robert Love <[email protected]>
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*/
#include <linux/kernel.h>
#include <linux/atomic.h>
#include <linux/dma/qcom_adm.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/wait.h>
#define MSM_UART_MR1 0x0000
#define MSM_UART_MR1_AUTO_RFR_LEVEL0 0x3F
#define MSM_UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
#define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
#define MSM_UART_MR1_RX_RDY_CTL BIT(7)
#define MSM_UART_MR1_CTS_CTL BIT(6)
#define MSM_UART_MR2 0x0004
#define MSM_UART_MR2_ERROR_MODE BIT(6)
#define MSM_UART_MR2_BITS_PER_CHAR 0x30
#define MSM_UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
#define MSM_UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
#define MSM_UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
#define MSM_UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
#define MSM_UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
#define MSM_UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
#define MSM_UART_MR2_PARITY_MODE_NONE 0x0
#define MSM_UART_MR2_PARITY_MODE_ODD 0x1
#define MSM_UART_MR2_PARITY_MODE_EVEN 0x2
#define MSM_UART_MR2_PARITY_MODE_SPACE 0x3
#define MSM_UART_MR2_PARITY_MODE 0x3
#define MSM_UART_CSR 0x0008
#define MSM_UART_TF 0x000C
#define UARTDM_TF 0x0070
#define MSM_UART_CR 0x0010
#define MSM_UART_CR_CMD_NULL (0 << 4)
#define MSM_UART_CR_CMD_RESET_RX (1 << 4)
#define MSM_UART_CR_CMD_RESET_TX (2 << 4)
#define MSM_UART_CR_CMD_RESET_ERR (3 << 4)
#define MSM_UART_CR_CMD_RESET_BREAK_INT (4 << 4)
#define MSM_UART_CR_CMD_START_BREAK (5 << 4)
#define MSM_UART_CR_CMD_STOP_BREAK (6 << 4)
#define MSM_UART_CR_CMD_RESET_CTS (7 << 4)
#define MSM_UART_CR_CMD_RESET_STALE_INT (8 << 4)
#define MSM_UART_CR_CMD_PACKET_MODE (9 << 4)
#define MSM_UART_CR_CMD_MODE_RESET (12 << 4)
#define MSM_UART_CR_CMD_SET_RFR (13 << 4)
#define MSM_UART_CR_CMD_RESET_RFR (14 << 4)
#define MSM_UART_CR_CMD_PROTECTION_EN (16 << 4)
#define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
#define MSM_UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
#define MSM_UART_CR_CMD_FORCE_STALE (4 << 8)
#define MSM_UART_CR_CMD_RESET_TX_READY (3 << 8)
#define MSM_UART_CR_TX_DISABLE BIT(3)
#define MSM_UART_CR_TX_ENABLE BIT(2)
#define MSM_UART_CR_RX_DISABLE BIT(1)
#define MSM_UART_CR_RX_ENABLE BIT(0)
#define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
#define MSM_UART_IMR 0x0014
#define MSM_UART_IMR_TXLEV BIT(0)
#define MSM_UART_IMR_RXSTALE BIT(3)
#define MSM_UART_IMR_RXLEV BIT(4)
#define MSM_UART_IMR_DELTA_CTS BIT(5)
#define MSM_UART_IMR_CURRENT_CTS BIT(6)
#define MSM_UART_IMR_RXBREAK_START BIT(10)
#define MSM_UART_IPR_RXSTALE_LAST 0x20
#define MSM_UART_IPR_STALE_LSB 0x1F
#define MSM_UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
#define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
#define MSM_UART_IPR 0x0018
#define MSM_UART_TFWR 0x001C
#define MSM_UART_RFWR 0x0020
#define MSM_UART_HCR 0x0024
#define MSM_UART_MREG 0x0028
#define MSM_UART_NREG 0x002C
#define MSM_UART_DREG 0x0030
#define MSM_UART_MNDREG 0x0034
#define MSM_UART_IRDA 0x0038
#define MSM_UART_MISR_MODE 0x0040
#define MSM_UART_MISR_RESET 0x0044
#define MSM_UART_MISR_EXPORT 0x0048
#define MSM_UART_MISR_VAL 0x004C
#define MSM_UART_TEST_CTRL 0x0050
#define MSM_UART_SR 0x0008
#define MSM_UART_SR_HUNT_CHAR BIT(7)
#define MSM_UART_SR_RX_BREAK BIT(6)
#define MSM_UART_SR_PAR_FRAME_ERR BIT(5)
#define MSM_UART_SR_OVERRUN BIT(4)
#define MSM_UART_SR_TX_EMPTY BIT(3)
#define MSM_UART_SR_TX_READY BIT(2)
#define MSM_UART_SR_RX_FULL BIT(1)
#define MSM_UART_SR_RX_READY BIT(0)
#define MSM_UART_RF 0x000C
#define UARTDM_RF 0x0070
#define MSM_UART_MISR 0x0010
#define MSM_UART_ISR 0x0014
#define MSM_UART_ISR_TX_READY BIT(7)
#define UARTDM_RXFS 0x50
#define UARTDM_RXFS_BUF_SHIFT 0x7
#define UARTDM_RXFS_BUF_MASK 0x7
#define UARTDM_DMEN 0x3C
#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
#define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
#define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
#define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
#define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
#define UARTDM_DMRX 0x34
#define UARTDM_NCF_TX 0x40
#define UARTDM_RX_TOTAL_SNAP 0x38
#define UARTDM_BURST_SIZE 16 /* in bytes */
#define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
#define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
#define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
enum {
UARTDM_1P1 = 1,
UARTDM_1P2,
UARTDM_1P3,
UARTDM_1P4,
};
struct msm_dma {
struct dma_chan *chan;
enum dma_data_direction dir;
dma_addr_t phys;
unsigned char *virt;
dma_cookie_t cookie;
u32 enable_bit;
unsigned int count;
struct dma_async_tx_descriptor *desc;
};
struct msm_port {
struct uart_port uart;
char name[16];
struct clk *clk;
struct clk *pclk;
unsigned int imr;
int is_uartdm;
unsigned int old_snap_state;
bool break_detected;
struct msm_dma tx_dma;
struct msm_dma rx_dma;
};
static inline struct msm_port *to_msm_port(struct uart_port *up)
{
return container_of(up, struct msm_port, uart);
}
static
void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
{
writel_relaxed(val, port->membase + off);
}
static
unsigned int msm_read(struct uart_port *port, unsigned int off)
{
return readl_relaxed(port->membase + off);
}
/*
* Setup the MND registers to use the TCXO clock.
*/
static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
{
msm_write(port, 0x06, MSM_UART_MREG);
msm_write(port, 0xF1, MSM_UART_NREG);
msm_write(port, 0x0F, MSM_UART_DREG);
msm_write(port, 0x1A, MSM_UART_MNDREG);
port->uartclk = 1843200;
}
/*
* Setup the MND registers to use the TCXO clock divided by 4.
*/
static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
{
msm_write(port, 0x18, MSM_UART_MREG);
msm_write(port, 0xF6, MSM_UART_NREG);
msm_write(port, 0x0F, MSM_UART_DREG);
msm_write(port, 0x0A, MSM_UART_MNDREG);
port->uartclk = 1843200;
}
static void msm_serial_set_mnd_regs(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
/*
* These registers don't exist so we change the clk input rate
* on uartdm hardware instead
*/
if (msm_port->is_uartdm)
return;
if (port->uartclk == 19200000)
msm_serial_set_mnd_regs_tcxo(port);
else if (port->uartclk == 4800000)
msm_serial_set_mnd_regs_tcxoby4(port);
}
static void msm_handle_tx(struct uart_port *port);
static void msm_start_rx_dma(struct msm_port *msm_port);
static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
{
struct device *dev = port->dev;
unsigned int mapped;
u32 val;
mapped = dma->count;
dma->count = 0;
dmaengine_terminate_all(dma->chan);
/*
* DMA Stall happens if enqueue and flush command happens concurrently.
* For example before changing the baud rate/protocol configuration and
* sending flush command to ADM, disable the channel of UARTDM.
* Note: should not reset the receiver here immediately as it is not
* suggested to do disable/reset or reset/disable at the same time.
*/
val = msm_read(port, UARTDM_DMEN);
val &= ~dma->enable_bit;
msm_write(port, val, UARTDM_DMEN);
if (mapped)
dma_unmap_single(dev, dma->phys, mapped, dma->dir);
}
static void msm_release_dma(struct msm_port *msm_port)
{
struct msm_dma *dma;
dma = &msm_port->tx_dma;
if (dma->chan) {
msm_stop_dma(&msm_port->uart, dma);
dma_release_channel(dma->chan);
}
memset(dma, 0, sizeof(*dma));
dma = &msm_port->rx_dma;
if (dma->chan) {
msm_stop_dma(&msm_port->uart, dma);
dma_release_channel(dma->chan);
kfree(dma->virt);
}
memset(dma, 0, sizeof(*dma));
}
static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
{
struct device *dev = msm_port->uart.dev;
struct dma_slave_config conf;
struct qcom_adm_peripheral_config periph_conf = {};
struct msm_dma *dma;
u32 crci = 0;
int ret;
dma = &msm_port->tx_dma;
/* allocate DMA resources, if available */
dma->chan = dma_request_chan(dev, "tx");
if (IS_ERR(dma->chan))
goto no_tx;
of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
memset(&conf, 0, sizeof(conf));
conf.direction = DMA_MEM_TO_DEV;
conf.device_fc = true;
conf.dst_addr = base + UARTDM_TF;
conf.dst_maxburst = UARTDM_BURST_SIZE;
if (crci) {
conf.peripheral_config = &periph_conf;
conf.peripheral_size = sizeof(periph_conf);
periph_conf.crci = crci;
}
ret = dmaengine_slave_config(dma->chan, &conf);
if (ret)
goto rel_tx;
dma->dir = DMA_TO_DEVICE;
if (msm_port->is_uartdm < UARTDM_1P4)
dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
else
dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
return;
rel_tx:
dma_release_channel(dma->chan);
no_tx:
memset(dma, 0, sizeof(*dma));
}
static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
{
struct device *dev = msm_port->uart.dev;
struct dma_slave_config conf;
struct qcom_adm_peripheral_config periph_conf = {};
struct msm_dma *dma;
u32 crci = 0;
int ret;
dma = &msm_port->rx_dma;
/* allocate DMA resources, if available */
dma->chan = dma_request_chan(dev, "rx");
if (IS_ERR(dma->chan))
goto no_rx;
of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
if (!dma->virt)
goto rel_rx;
memset(&conf, 0, sizeof(conf));
conf.direction = DMA_DEV_TO_MEM;
conf.device_fc = true;
conf.src_addr = base + UARTDM_RF;
conf.src_maxburst = UARTDM_BURST_SIZE;
if (crci) {
conf.peripheral_config = &periph_conf;
conf.peripheral_size = sizeof(periph_conf);
periph_conf.crci = crci;
}
ret = dmaengine_slave_config(dma->chan, &conf);
if (ret)
goto err;
dma->dir = DMA_FROM_DEVICE;
if (msm_port->is_uartdm < UARTDM_1P4)
dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
else
dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
return;
err:
kfree(dma->virt);
rel_rx:
dma_release_channel(dma->chan);
no_rx:
memset(dma, 0, sizeof(*dma));
}
static inline void msm_wait_for_xmitr(struct uart_port *port)
{
unsigned int timeout = 500000;
while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) {
if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY)
break;
udelay(1);
if (!timeout--)
break;
}
msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);
}
static void msm_stop_tx(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
msm_port->imr &= ~MSM_UART_IMR_TXLEV;
msm_write(port, msm_port->imr, MSM_UART_IMR);
}
static void msm_start_tx(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
struct msm_dma *dma = &msm_port->tx_dma;
/* Already started in DMA mode */
if (dma->count)
return;
msm_port->imr |= MSM_UART_IMR_TXLEV;
msm_write(port, msm_port->imr, MSM_UART_IMR);
}
static void msm_reset_dm_count(struct uart_port *port, int count)
{
msm_wait_for_xmitr(port);
msm_write(port, count, UARTDM_NCF_TX);
msm_read(port, UARTDM_NCF_TX);
}
static void msm_complete_tx_dma(void *args)
{
struct msm_port *msm_port = args;
struct uart_port *port = &msm_port->uart;
struct circ_buf *xmit = &port->state->xmit;
struct msm_dma *dma = &msm_port->tx_dma;
struct dma_tx_state state;
unsigned long flags;
unsigned int count;
u32 val;
spin_lock_irqsave(&port->lock, flags);
/* Already stopped */
if (!dma->count)
goto done;
dmaengine_tx_status(dma->chan, dma->cookie, &state);
dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
val = msm_read(port, UARTDM_DMEN);
val &= ~dma->enable_bit;
msm_write(port, val, UARTDM_DMEN);
if (msm_port->is_uartdm > UARTDM_1P3) {
msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);
}
count = dma->count - state.residue;
uart_xmit_advance(port, count);
dma->count = 0;
/* Restore "Tx FIFO below watermark" interrupt */
msm_port->imr |= MSM_UART_IMR_TXLEV;
msm_write(port, msm_port->imr, MSM_UART_IMR);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
msm_handle_tx(port);
done:
spin_unlock_irqrestore(&port->lock, flags);
}
static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
{
struct circ_buf *xmit = &msm_port->uart.state->xmit;
struct uart_port *port = &msm_port->uart;
struct msm_dma *dma = &msm_port->tx_dma;
void *cpu_addr;
int ret;
u32 val;
cpu_addr = &xmit->buf[xmit->tail];
dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
ret = dma_mapping_error(port->dev, dma->phys);
if (ret)
return ret;
dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
count, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT |
DMA_PREP_FENCE);
if (!dma->desc) {
ret = -EIO;
goto unmap;
}
dma->desc->callback = msm_complete_tx_dma;
dma->desc->callback_param = msm_port;
dma->cookie = dmaengine_submit(dma->desc);
ret = dma_submit_error(dma->cookie);
if (ret)
goto unmap;
/*
* Using DMA complete for Tx FIFO reload, no need for
* "Tx FIFO below watermark" one, disable it
*/
msm_port->imr &= ~MSM_UART_IMR_TXLEV;
msm_write(port, msm_port->imr, MSM_UART_IMR);
dma->count = count;
val = msm_read(port, UARTDM_DMEN);
val |= dma->enable_bit;
if (msm_port->is_uartdm < UARTDM_1P4)
msm_write(port, val, UARTDM_DMEN);
msm_reset_dm_count(port, count);
if (msm_port->is_uartdm > UARTDM_1P3)
msm_write(port, val, UARTDM_DMEN);
dma_async_issue_pending(dma->chan);
return 0;
unmap:
dma_unmap_single(port->dev, dma->phys, count, dma->dir);
return ret;
}
static void msm_complete_rx_dma(void *args)
{
struct msm_port *msm_port = args;
struct uart_port *port = &msm_port->uart;
struct tty_port *tport = &port->state->port;
struct msm_dma *dma = &msm_port->rx_dma;
int count = 0, i, sysrq;
unsigned long flags;
u32 val;
spin_lock_irqsave(&port->lock, flags);
/* Already stopped */
if (!dma->count)
goto done;
val = msm_read(port, UARTDM_DMEN);
val &= ~dma->enable_bit;
msm_write(port, val, UARTDM_DMEN);
if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) {
port->icount.overrun++;
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
}
count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
port->icount.rx += count;
dma->count = 0;
dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
for (i = 0; i < count; i++) {
char flag = TTY_NORMAL;
if (msm_port->break_detected && dma->virt[i] == 0) {
port->icount.brk++;
flag = TTY_BREAK;
msm_port->break_detected = false;
if (uart_handle_break(port))
continue;
}
if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
flag = TTY_NORMAL;
spin_unlock_irqrestore(&port->lock, flags);
sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
spin_lock_irqsave(&port->lock, flags);
if (!sysrq)
tty_insert_flip_char(tport, dma->virt[i], flag);
}
msm_start_rx_dma(msm_port);
done:
spin_unlock_irqrestore(&port->lock, flags);
if (count)
tty_flip_buffer_push(tport);
}
static void msm_start_rx_dma(struct msm_port *msm_port)
{
struct msm_dma *dma = &msm_port->rx_dma;
struct uart_port *uart = &msm_port->uart;
u32 val;
int ret;
if (IS_ENABLED(CONFIG_CONSOLE_POLL))
return;
if (!dma->chan)
return;
dma->phys = dma_map_single(uart->dev, dma->virt,
UARTDM_RX_SIZE, dma->dir);
ret = dma_mapping_error(uart->dev, dma->phys);
if (ret)
goto sw_mode;
dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT);
if (!dma->desc)
goto unmap;
dma->desc->callback = msm_complete_rx_dma;
dma->desc->callback_param = msm_port;
dma->cookie = dmaengine_submit(dma->desc);
ret = dma_submit_error(dma->cookie);
if (ret)
goto unmap;
/*
* Using DMA for FIFO off-load, no need for "Rx FIFO over
* watermark" or "stale" interrupts, disable them
*/
msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
/*
* Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
* we need RXSTALE to flush input DMA fifo to memory
*/
if (msm_port->is_uartdm < UARTDM_1P4)
msm_port->imr |= MSM_UART_IMR_RXSTALE;
msm_write(uart, msm_port->imr, MSM_UART_IMR);
dma->count = UARTDM_RX_SIZE;
dma_async_issue_pending(dma->chan);
msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
val = msm_read(uart, UARTDM_DMEN);
val |= dma->enable_bit;
if (msm_port->is_uartdm < UARTDM_1P4)
msm_write(uart, val, UARTDM_DMEN);
msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
if (msm_port->is_uartdm > UARTDM_1P3)
msm_write(uart, val, UARTDM_DMEN);
return;
unmap:
dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
sw_mode:
/*
* Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
* receiver must be reset.
*/
msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
/* Re-enable RX interrupts */
msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE;
msm_write(uart, msm_port->imr, MSM_UART_IMR);
}
static void msm_stop_rx(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
struct msm_dma *dma = &msm_port->rx_dma;
msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
msm_write(port, msm_port->imr, MSM_UART_IMR);
if (dma->chan)
msm_stop_dma(port, dma);
}
static void msm_enable_ms(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
msm_port->imr |= MSM_UART_IMR_DELTA_CTS;
msm_write(port, msm_port->imr, MSM_UART_IMR);
}
static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
__must_hold(&port->lock)
{
struct tty_port *tport = &port->state->port;
unsigned int sr;
int count = 0;
struct msm_port *msm_port = to_msm_port(port);
if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
port->icount.overrun++;
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
}
if (misr & MSM_UART_IMR_RXSTALE) {
count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
msm_port->old_snap_state;
msm_port->old_snap_state = 0;
} else {
count = 4 * (msm_read(port, MSM_UART_RFWR));
msm_port->old_snap_state += count;
}
/* TODO: Precise error reporting */
port->icount.rx += count;
while (count > 0) {
unsigned char buf[4];
int sysrq, r_count, i;
sr = msm_read(port, MSM_UART_SR);
if ((sr & MSM_UART_SR_RX_READY) == 0) {
msm_port->old_snap_state -= count;
break;
}
ioread32_rep(port->membase + UARTDM_RF, buf, 1);
r_count = min_t(int, count, sizeof(buf));
for (i = 0; i < r_count; i++) {
char flag = TTY_NORMAL;
if (msm_port->break_detected && buf[i] == 0) {
port->icount.brk++;
flag = TTY_BREAK;
msm_port->break_detected = false;
if (uart_handle_break(port))
continue;
}
if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
flag = TTY_NORMAL;
spin_unlock(&port->lock);
sysrq = uart_handle_sysrq_char(port, buf[i]);
spin_lock(&port->lock);
if (!sysrq)
tty_insert_flip_char(tport, buf[i], flag);
}
count -= r_count;
}
tty_flip_buffer_push(tport);
if (misr & (MSM_UART_IMR_RXSTALE))
msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
msm_write(port, 0xFFFFFF, UARTDM_DMRX);
msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
/* Try to use DMA */
msm_start_rx_dma(msm_port);
}
static void msm_handle_rx(struct uart_port *port)
__must_hold(&port->lock)
{
struct tty_port *tport = &port->state->port;
unsigned int sr;
/*
* Handle overrun. My understanding of the hardware is that overrun
* is not tied to the RX buffer, so we handle the case out of band.
*/
if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
port->icount.overrun++;
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
}
/* and now the main RX loop */
while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) {
unsigned int c;
char flag = TTY_NORMAL;
int sysrq;
c = msm_read(port, MSM_UART_RF);
if (sr & MSM_UART_SR_RX_BREAK) {
port->icount.brk++;
if (uart_handle_break(port))
continue;
} else if (sr & MSM_UART_SR_PAR_FRAME_ERR) {
port->icount.frame++;
} else {
port->icount.rx++;
}
/* Mask conditions we're ignoring. */
sr &= port->read_status_mask;
if (sr & MSM_UART_SR_RX_BREAK)
flag = TTY_BREAK;
else if (sr & MSM_UART_SR_PAR_FRAME_ERR)
flag = TTY_FRAME;
spin_unlock(&port->lock);
sysrq = uart_handle_sysrq_char(port, c);
spin_lock(&port->lock);
if (!sysrq)
tty_insert_flip_char(tport, c, flag);
}
tty_flip_buffer_push(tport);
}
static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
{
struct circ_buf *xmit = &port->state->xmit;
struct msm_port *msm_port = to_msm_port(port);
unsigned int num_chars;
unsigned int tf_pointer = 0;
void __iomem *tf;
if (msm_port->is_uartdm)
tf = port->membase + UARTDM_TF;
else
tf = port->membase + MSM_UART_TF;
if (tx_count && msm_port->is_uartdm)
msm_reset_dm_count(port, tx_count);
while (tf_pointer < tx_count) {
int i;
char buf[4] = { 0 };
if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
break;
if (msm_port->is_uartdm)
num_chars = min(tx_count - tf_pointer,
(unsigned int)sizeof(buf));
else
num_chars = 1;
for (i = 0; i < num_chars; i++)
buf[i] = xmit->buf[xmit->tail + i];
iowrite32_rep(tf, buf, 1);
uart_xmit_advance(port, num_chars);
tf_pointer += num_chars;
}
/* disable tx interrupts if nothing more to send */
if (uart_circ_empty(xmit))
msm_stop_tx(port);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static void msm_handle_tx(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
struct circ_buf *xmit = &msm_port->uart.state->xmit;
struct msm_dma *dma = &msm_port->tx_dma;
unsigned int pio_count, dma_count, dma_min;
char buf[4] = { 0 };
void __iomem *tf;
int err = 0;
if (port->x_char) {
if (msm_port->is_uartdm)
tf = port->membase + UARTDM_TF;
else
tf = port->membase + MSM_UART_TF;
buf[0] = port->x_char;
if (msm_port->is_uartdm)
msm_reset_dm_count(port, 1);
iowrite32_rep(tf, buf, 1);
port->icount.tx++;
port->x_char = 0;
return;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
msm_stop_tx(port);
return;
}
pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
dma_min = 1; /* Always DMA */
if (msm_port->is_uartdm > UARTDM_1P3) {
dma_count = UARTDM_TX_AIGN(dma_count);
dma_min = UARTDM_BURST_SIZE;
} else {
if (dma_count > UARTDM_TX_MAX)
dma_count = UARTDM_TX_MAX;
}
if (pio_count > port->fifosize)
pio_count = port->fifosize;
if (!dma->chan || dma_count < dma_min)
msm_handle_tx_pio(port, pio_count);
else
err = msm_handle_tx_dma(msm_port, dma_count);
if (err) /* fall back to PIO mode */
msm_handle_tx_pio(port, pio_count);
}
static void msm_handle_delta_cts(struct uart_port *port)
{
msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
port->icount.cts++;
wake_up_interruptible(&port->state->port.delta_msr_wait);
}
static irqreturn_t msm_uart_irq(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct msm_port *msm_port = to_msm_port(port);
struct msm_dma *dma = &msm_port->rx_dma;
unsigned long flags;
unsigned int misr;
u32 val;
spin_lock_irqsave(&port->lock, flags);
misr = msm_read(port, MSM_UART_MISR);
msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */
if (misr & MSM_UART_IMR_RXBREAK_START) {
msm_port->break_detected = true;
msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);
}
if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) {
if (dma->count) {
val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE;
msm_write(port, val, MSM_UART_CR);
val = MSM_UART_CR_CMD_RESET_STALE_INT;
msm_write(port, val, MSM_UART_CR);
/*
* Flush DMA input fifo to memory, this will also
* trigger DMA RX completion
*/
dmaengine_terminate_all(dma->chan);
} else if (msm_port->is_uartdm) {
msm_handle_rx_dm(port, misr);
} else {
msm_handle_rx(port);
}
}
if (misr & MSM_UART_IMR_TXLEV)
msm_handle_tx(port);
if (misr & MSM_UART_IMR_DELTA_CTS)
msm_handle_delta_cts(port);
msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
static unsigned int msm_tx_empty(struct uart_port *port)
{
return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
}
static unsigned int msm_get_mctrl(struct uart_port *port)
{
return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
}
static void msm_reset(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
unsigned int mr;
/* reset everything */
msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);
msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
mr = msm_read(port, MSM_UART_MR1);
mr &= ~MSM_UART_MR1_RX_RDY_CTL;
msm_write(port, mr, MSM_UART_MR1);
/* Disable DM modes */
if (msm_port->is_uartdm)
msm_write(port, 0, UARTDM_DMEN);
}
static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
unsigned int mr;
mr = msm_read(port, MSM_UART_MR1);
if (!(mctrl & TIOCM_RTS)) {
mr &= ~MSM_UART_MR1_RX_RDY_CTL;
msm_write(port, mr, MSM_UART_MR1);
msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
} else {
mr |= MSM_UART_MR1_RX_RDY_CTL;
msm_write(port, mr, MSM_UART_MR1);
}
}
static void msm_break_ctl(struct uart_port *port, int break_ctl)
{
if (break_ctl)
msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);
else
msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);
}
struct msm_baud_map {
u16 divisor;
u8 code;
u8 rxstale;
};
static const struct msm_baud_map *
msm_find_best_baud(struct uart_port *port, unsigned int baud,
unsigned long *rate)
{
struct msm_port *msm_port = to_msm_port(port);
unsigned int divisor, result;
unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
const struct msm_baud_map *entry, *end, *best;
static const struct msm_baud_map table[] = {
{ 1, 0xff, 31 },
{ 2, 0xee, 16 },
{ 3, 0xdd, 8 },
{ 4, 0xcc, 6 },
{ 6, 0xbb, 6 },
{ 8, 0xaa, 6 },
{ 12, 0x99, 6 },
{ 16, 0x88, 1 },
{ 24, 0x77, 1 },
{ 32, 0x66, 1 },
{ 48, 0x55, 1 },
{ 96, 0x44, 1 },
{ 192, 0x33, 1 },
{ 384, 0x22, 1 },
{ 768, 0x11, 1 },
{ 1536, 0x00, 1 },
};
best = table; /* Default to smallest divider */
target = clk_round_rate(msm_port->clk, 16 * baud);
divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
end = table + ARRAY_SIZE(table);
entry = table;
while (entry < end) {
if (entry->divisor <= divisor) {
result = target / entry->divisor / 16;
diff = abs(result - baud);
/* Keep track of best entry */
if (diff < best_diff) {
best_diff = diff;
best = entry;
best_rate = target;
}
if (result == baud)
break;
} else if (entry->divisor > divisor) {
old = target;
target = clk_round_rate(msm_port->clk, old + 1);
/*
* The rate didn't get any faster so we can't do
* better at dividing it down
*/
if (target == old)
break;
/* Start the divisor search over at this new rate */
entry = table;
divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
continue;
}
entry++;
}
*rate = best_rate;
return best;
}
static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
unsigned long *saved_flags)
__must_hold(&port->lock)
{
unsigned int rxstale, watermark, mask;
struct msm_port *msm_port = to_msm_port(port);
const struct msm_baud_map *entry;
unsigned long flags, rate;
flags = *saved_flags;
spin_unlock_irqrestore(&port->lock, flags);
entry = msm_find_best_baud(port, baud, &rate);
clk_set_rate(msm_port->clk, rate);
baud = rate / 16 / entry->divisor;
spin_lock_irqsave(&port->lock, flags);
*saved_flags = flags;
port->uartclk = rate;
msm_write(port, entry->code, MSM_UART_CSR);
/* RX stale watermark */
rxstale = entry->rxstale;
watermark = MSM_UART_IPR_STALE_LSB & rxstale;
if (msm_port->is_uartdm) {
mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB;
} else {
watermark |= MSM_UART_IPR_RXSTALE_LAST;
mask = MSM_UART_IPR_STALE_TIMEOUT_MSB;
}
watermark |= mask & (rxstale << 2);
msm_write(port, watermark, MSM_UART_IPR);
/* set RX watermark */
watermark = (port->fifosize * 3) / 4;
msm_write(port, watermark, MSM_UART_RFWR);
/* set TX watermark */
msm_write(port, 10, MSM_UART_TFWR);
msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);
msm_reset(port);
/* Enable RX and TX */
msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
/* turn on RX and CTS interrupts */
msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE |
MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START;
msm_write(port, msm_port->imr, MSM_UART_IMR);
if (msm_port->is_uartdm) {
msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
msm_write(port, 0xFFFFFF, UARTDM_DMRX);
msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
}
return baud;
}
static void msm_init_clock(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
clk_prepare_enable(msm_port->clk);
clk_prepare_enable(msm_port->pclk);
msm_serial_set_mnd_regs(port);
}
static int msm_startup(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
unsigned int data, rfr_level, mask;
int ret;
snprintf(msm_port->name, sizeof(msm_port->name),
"msm_serial%d", port->line);
msm_init_clock(port);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
/* set automatic RFR level */
data = msm_read(port, MSM_UART_MR1);
if (msm_port->is_uartdm)
mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1;
else
mask = MSM_UART_MR1_AUTO_RFR_LEVEL1;
data &= ~mask;
data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0;
data |= mask & (rfr_level << 2);
data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
msm_write(port, data, MSM_UART_MR1);
if (msm_port->is_uartdm) {
msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
}
ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
msm_port->name, port);
if (unlikely(ret))
goto err_irq;
return 0;
err_irq:
if (msm_port->is_uartdm)
msm_release_dma(msm_port);
clk_disable_unprepare(msm_port->pclk);
clk_disable_unprepare(msm_port->clk);
return ret;
}
static void msm_shutdown(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
msm_port->imr = 0;
msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */
if (msm_port->is_uartdm)
msm_release_dma(msm_port);
clk_disable_unprepare(msm_port->clk);
free_irq(port->irq, port);
}
static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct msm_port *msm_port = to_msm_port(port);
struct msm_dma *dma = &msm_port->rx_dma;
unsigned long flags;
unsigned int baud, mr;
spin_lock_irqsave(&port->lock, flags);
if (dma->chan) /* Terminate if any */
msm_stop_dma(port, dma);
/* calculate and set baud rate */
baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
baud = msm_set_baud_rate(port, baud, &flags);
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);
/* calculate parity */
mr = msm_read(port, MSM_UART_MR2);
mr &= ~MSM_UART_MR2_PARITY_MODE;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
mr |= MSM_UART_MR2_PARITY_MODE_ODD;
else if (termios->c_cflag & CMSPAR)
mr |= MSM_UART_MR2_PARITY_MODE_SPACE;
else
mr |= MSM_UART_MR2_PARITY_MODE_EVEN;
}
/* calculate bits per char */
mr &= ~MSM_UART_MR2_BITS_PER_CHAR;
switch (termios->c_cflag & CSIZE) {
case CS5:
mr |= MSM_UART_MR2_BITS_PER_CHAR_5;
break;
case CS6:
mr |= MSM_UART_MR2_BITS_PER_CHAR_6;
break;
case CS7:
mr |= MSM_UART_MR2_BITS_PER_CHAR_7;
break;
case CS8:
default:
mr |= MSM_UART_MR2_BITS_PER_CHAR_8;
break;
}
/* calculate stop bits */
mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO);
if (termios->c_cflag & CSTOPB)
mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO;
else
mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE;
/* set parity, bits per char, and stop bit */
msm_write(port, mr, MSM_UART_MR2);
/* calculate and set hardware flow control */
mr = msm_read(port, MSM_UART_MR1);
mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL);
if (termios->c_cflag & CRTSCTS) {
mr |= MSM_UART_MR1_CTS_CTL;
mr |= MSM_UART_MR1_RX_RDY_CTL;
}
msm_write(port, mr, MSM_UART_MR1);
/* Configure status bits to ignore based on termio flags. */
port->read_status_mask = 0;
if (termios->c_iflag & INPCK)
port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
port->read_status_mask |= MSM_UART_SR_RX_BREAK;
uart_update_timeout(port, termios->c_cflag, baud);
/* Try to use DMA */
msm_start_rx_dma(msm_port);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *msm_type(struct uart_port *port)
{
return "MSM";
}
static void msm_release_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *uart_resource;
resource_size_t size;
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource))
return;
size = resource_size(uart_resource);
release_mem_region(port->mapbase, size);
iounmap(port->membase);
port->membase = NULL;
}
static int msm_request_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *uart_resource;
resource_size_t size;
int ret;
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!uart_resource))
return -ENXIO;
size = resource_size(uart_resource);
if (!request_mem_region(port->mapbase, size, "msm_serial"))
return -EBUSY;
port->membase = ioremap(port->mapbase, size);
if (!port->membase) {
ret = -EBUSY;
goto fail_release_port;
}
return 0;
fail_release_port:
release_mem_region(port->mapbase, size);
return ret;
}
static void msm_config_port(struct uart_port *port, int flags)
{
int ret;
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_MSM;
ret = msm_request_port(port);
if (ret)
return;
}
}
static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
{
if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
return -EINVAL;
if (unlikely(port->irq != ser->irq))
return -EINVAL;
return 0;
}
static void msm_power(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
struct msm_port *msm_port = to_msm_port(port);
switch (state) {
case 0:
clk_prepare_enable(msm_port->clk);
clk_prepare_enable(msm_port->pclk);
break;
case 3:
clk_disable_unprepare(msm_port->clk);
clk_disable_unprepare(msm_port->pclk);
break;
default:
pr_err("msm_serial: Unknown PM state %d\n", state);
}
}
#ifdef CONFIG_CONSOLE_POLL
static int msm_poll_get_char_single(struct uart_port *port)
{
struct msm_port *msm_port = to_msm_port(port);
unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF;
if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY))
return NO_POLL_CHAR;
return msm_read(port, rf_reg) & 0xff;
}
static int msm_poll_get_char_dm(struct uart_port *port)
{
int c;
static u32 slop;
static int count;
unsigned char *sp = (unsigned char *)&slop;
/* Check if a previous read had more than one char */
if (count) {
c = sp[sizeof(slop) - count];
count--;
/* Or if FIFO is empty */
} else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) {
/*
* If RX packing buffer has less than a word, force stale to
* push contents into RX FIFO
*/
count = msm_read(port, UARTDM_RXFS);
count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
if (count) {
msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);
slop = msm_read(port, UARTDM_RF);
c = sp[0];
count--;
msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
msm_write(port, 0xFFFFFF, UARTDM_DMRX);
msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
} else {
c = NO_POLL_CHAR;
}
/* FIFO has a word */
} else {
slop = msm_read(port, UARTDM_RF);
c = sp[0];
count = sizeof(slop) - 1;
}
return c;
}
static int msm_poll_get_char(struct uart_port *port)
{
u32 imr;
int c;
struct msm_port *msm_port = to_msm_port(port);
/* Disable all interrupts */
imr = msm_read(port, MSM_UART_IMR);
msm_write(port, 0, MSM_UART_IMR);
if (msm_port->is_uartdm)
c = msm_poll_get_char_dm(port);
else
c = msm_poll_get_char_single(port);
/* Enable interrupts */
msm_write(port, imr, MSM_UART_IMR);
return c;
}
static void msm_poll_put_char(struct uart_port *port, unsigned char c)
{
u32 imr;
struct msm_port *msm_port = to_msm_port(port);
/* Disable all interrupts */
imr = msm_read(port, MSM_UART_IMR);
msm_write(port, 0, MSM_UART_IMR);
if (msm_port->is_uartdm)
msm_reset_dm_count(port, 1);
/* Wait until FIFO is empty */
while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
cpu_relax();
/* Write a character */
msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF);
/* Wait until FIFO is empty */
while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
cpu_relax();
/* Enable interrupts */
msm_write(port, imr, MSM_UART_IMR);
}
#endif
static const struct uart_ops msm_uart_pops = {
.tx_empty = msm_tx_empty,
.set_mctrl = msm_set_mctrl,
.get_mctrl = msm_get_mctrl,
.stop_tx = msm_stop_tx,
.start_tx = msm_start_tx,
.stop_rx = msm_stop_rx,
.enable_ms = msm_enable_ms,
.break_ctl = msm_break_ctl,
.startup = msm_startup,
.shutdown = msm_shutdown,
.set_termios = msm_set_termios,
.type = msm_type,
.release_port = msm_release_port,
.request_port = msm_request_port,
.config_port = msm_config_port,
.verify_port = msm_verify_port,
.pm = msm_power,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = msm_poll_get_char,
.poll_put_char = msm_poll_put_char,
#endif
};
static struct msm_port msm_uart_ports[] = {
{
.uart = {
.iotype = UPIO_MEM,
.ops = &msm_uart_pops,
.flags = UPF_BOOT_AUTOCONF,
.fifosize = 64,
.line = 0,
},
},
{
.uart = {
.iotype = UPIO_MEM,
.ops = &msm_uart_pops,
.flags = UPF_BOOT_AUTOCONF,
.fifosize = 64,
.line = 1,
},
},
{
.uart = {
.iotype = UPIO_MEM,
.ops = &msm_uart_pops,
.flags = UPF_BOOT_AUTOCONF,
.fifosize = 64,
.line = 2,
},
},
};
#define MSM_UART_NR ARRAY_SIZE(msm_uart_ports)
static inline struct uart_port *msm_get_port_from_line(unsigned int line)
{
return &msm_uart_ports[line].uart;
}
#ifdef CONFIG_SERIAL_MSM_CONSOLE
static void __msm_console_write(struct uart_port *port, const char *s,
unsigned int count, bool is_uartdm)
{
unsigned long flags;
int i;
int num_newlines = 0;
bool replaced = false;
void __iomem *tf;
int locked = 1;
if (is_uartdm)
tf = port->membase + UARTDM_TF;
else
tf = port->membase + MSM_UART_TF;
/* Account for newlines that will get a carriage return added */
for (i = 0; i < count; i++)
if (s[i] == '\n')
num_newlines++;
count += num_newlines;
local_irq_save(flags);
if (port->sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock(&port->lock);
else
spin_lock(&port->lock);
if (is_uartdm)
msm_reset_dm_count(port, count);
i = 0;
while (i < count) {
int j;
unsigned int num_chars;
char buf[4] = { 0 };
if (is_uartdm)
num_chars = min(count - i, (unsigned int)sizeof(buf));
else
num_chars = 1;
for (j = 0; j < num_chars; j++) {
char c = *s;
if (c == '\n' && !replaced) {
buf[j] = '\r';
j++;
replaced = true;
}
if (j < num_chars) {
buf[j] = c;
s++;
replaced = false;
}
}
while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
cpu_relax();
iowrite32_rep(tf, buf, 1);
i += num_chars;
}
if (locked)
spin_unlock(&port->lock);
local_irq_restore(flags);
}
static void msm_console_write(struct console *co, const char *s,
unsigned int count)
{
struct uart_port *port;
struct msm_port *msm_port;
BUG_ON(co->index < 0 || co->index >= MSM_UART_NR);
port = msm_get_port_from_line(co->index);
msm_port = to_msm_port(port);
__msm_console_write(port, s, count, msm_port->is_uartdm);
}
static int msm_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (unlikely(co->index >= MSM_UART_NR || co->index < 0))
return -ENXIO;
port = msm_get_port_from_line(co->index);
if (unlikely(!port->membase))
return -ENXIO;
msm_init_clock(port);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
pr_info("msm_serial: console setup on port #%d\n", port->line);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static void
msm_serial_early_write(struct console *con, const char *s, unsigned n)
{
struct earlycon_device *dev = con->data;
__msm_console_write(&dev->port, s, n, false);
}
static int __init
msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = msm_serial_early_write;
return 0;
}
OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
msm_serial_early_console_setup);
static void
msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
{
struct earlycon_device *dev = con->data;
__msm_console_write(&dev->port, s, n, true);
}
static int __init
msm_serial_early_console_setup_dm(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = msm_serial_early_write_dm;
return 0;
}
OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
msm_serial_early_console_setup_dm);
static struct uart_driver msm_uart_driver;
static struct console msm_console = {
.name = "ttyMSM",
.write = msm_console_write,
.device = uart_console_device,
.setup = msm_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &msm_uart_driver,
};
#define MSM_CONSOLE (&msm_console)
#else
#define MSM_CONSOLE NULL
#endif
static struct uart_driver msm_uart_driver = {
.owner = THIS_MODULE,
.driver_name = "msm_serial",
.dev_name = "ttyMSM",
.nr = MSM_UART_NR,
.cons = MSM_CONSOLE,
};
static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
static const struct of_device_id msm_uartdm_table[] = {
{ .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
{ .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
{ .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
{ .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
{ }
};
static int msm_serial_probe(struct platform_device *pdev)
{
struct msm_port *msm_port;
struct resource *resource;
struct uart_port *port;
const struct of_device_id *id;
int irq, line;
if (pdev->dev.of_node)
line = of_alias_get_id(pdev->dev.of_node, "serial");
else
line = pdev->id;
if (line < 0)
line = atomic_inc_return(&msm_uart_next_id) - 1;
if (unlikely(line < 0 || line >= MSM_UART_NR))
return -ENXIO;
dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
port = msm_get_port_from_line(line);
port->dev = &pdev->dev;
msm_port = to_msm_port(port);
id = of_match_device(msm_uartdm_table, &pdev->dev);
if (id)
msm_port->is_uartdm = (unsigned long)id->data;
else
msm_port->is_uartdm = 0;
msm_port->clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(msm_port->clk))
return PTR_ERR(msm_port->clk);
if (msm_port->is_uartdm) {
msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
if (IS_ERR(msm_port->pclk))
return PTR_ERR(msm_port->pclk);
}
port->uartclk = clk_get_rate(msm_port->clk);
dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!resource))
return -ENXIO;
port->mapbase = resource->start;
irq = platform_get_irq(pdev, 0);
if (unlikely(irq < 0))
return -ENXIO;
port->irq = irq;
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
platform_set_drvdata(pdev, port);
return uart_add_one_port(&msm_uart_driver, port);
}
static int msm_serial_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
uart_remove_one_port(&msm_uart_driver, port);
return 0;
}
static const struct of_device_id msm_match_table[] = {
{ .compatible = "qcom,msm-uart" },
{ .compatible = "qcom,msm-uartdm" },
{}
};
MODULE_DEVICE_TABLE(of, msm_match_table);
static int __maybe_unused msm_serial_suspend(struct device *dev)
{
struct msm_port *port = dev_get_drvdata(dev);
uart_suspend_port(&msm_uart_driver, &port->uart);
return 0;
}
static int __maybe_unused msm_serial_resume(struct device *dev)
{
struct msm_port *port = dev_get_drvdata(dev);
uart_resume_port(&msm_uart_driver, &port->uart);
return 0;
}
static const struct dev_pm_ops msm_serial_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
};
static struct platform_driver msm_platform_driver = {
.remove = msm_serial_remove,
.probe = msm_serial_probe,
.driver = {
.name = "msm_serial",
.pm = &msm_serial_dev_pm_ops,
.of_match_table = msm_match_table,
},
};
static int __init msm_serial_init(void)
{
int ret;
ret = uart_register_driver(&msm_uart_driver);
if (unlikely(ret))
return ret;
ret = platform_driver_register(&msm_platform_driver);
if (unlikely(ret))
uart_unregister_driver(&msm_uart_driver);
pr_info("msm_serial: driver initialized\n");
return ret;
}
static void __exit msm_serial_exit(void)
{
platform_driver_unregister(&msm_platform_driver);
uart_unregister_driver(&msm_uart_driver);
}
module_init(msm_serial_init);
module_exit(msm_serial_exit);
MODULE_AUTHOR("Robert Love <[email protected]>");
MODULE_DESCRIPTION("Driver for msm7x serial device");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/msm_serial.c |
// SPDX-License-Identifier: GPL-2.0
/*
* su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
*
* Copyright (C) 1997 Eddie C. Dost ([email protected])
* Copyright (C) 1998-1999 Pete Zaitcev ([email protected])
*
* This is mainly a variation of 8250.c, credits go to authors mentioned
* therein. In fact this driver should be merged into the generic 8250.c
* infrastructure perhaps using a 8250_sparc.c module.
*
* Fixed to use tty_get_baud_rate().
* Theodore Ts'o <[email protected]>, 2001-Oct-12
*
* Converted to new 2.5.x UART layer.
* David S. Miller ([email protected]), 2002-Jul-29
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/sysrq.h>
#include <linux/console.h>
#include <linux/slab.h>
#ifdef CONFIG_SERIO
#include <linux/serio.h>
#endif
#include <linux/serial_reg.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <linux/serial_core.h>
#include <linux/sunserialcore.h>
/* We are on a NS PC87303 clocked with 24.0 MHz, which results
* in a UART clock of 1.8462 MHz.
*/
#define SU_BASE_BAUD (1846200 / 16)
enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
struct serial_uart_config {
char *name;
int dfl_xmit_fifo_size;
int flags;
};
/*
* Here we define the default xmit fifo size used for each type of UART.
*/
static const struct serial_uart_config uart_config[] = {
{ "unknown", 1, 0 },
{ "8250", 1, 0 },
{ "16450", 1, 0 },
{ "16550", 1, 0 },
{ "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
{ "Cirrus", 1, 0 },
{ "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
{ "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
{ "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
{ "Startech", 1, 0 },
{ "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
{ "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
{ "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
{ "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
};
struct uart_sunsu_port {
struct uart_port port;
unsigned char acr;
unsigned char ier;
unsigned short rev;
unsigned char lcr;
unsigned int lsr_break_flag;
unsigned int cflag;
/* Probing information. */
enum su_type su_type;
unsigned int type_probed; /* XXX Stupid */
unsigned long reg_size;
#ifdef CONFIG_SERIO
struct serio serio;
int serio_open;
#endif
};
static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
{
offset <<= up->port.regshift;
switch (up->port.iotype) {
case UPIO_HUB6:
outb(up->port.hub6 - 1 + offset, up->port.iobase);
return inb(up->port.iobase + 1);
case UPIO_MEM:
return readb(up->port.membase + offset);
default:
return inb(up->port.iobase + offset);
}
}
static void serial_out(struct uart_sunsu_port *up, int offset, int value)
{
#ifndef CONFIG_SPARC64
/*
* MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
* connected with a gate then go to SlavIO. When IRQ4 goes tristated
* gate outputs a logical one. Since we use level triggered interrupts
* we have lockup and watchdog reset. We cannot mask IRQ because
* keyboard shares IRQ with us (Word has it as Bob Smelik's design).
* This problem is similar to what Alpha people suffer, see
* 8250_alpha.c.
*/
if (offset == UART_MCR)
value |= UART_MCR_OUT2;
#endif
offset <<= up->port.regshift;
switch (up->port.iotype) {
case UPIO_HUB6:
outb(up->port.hub6 - 1 + offset, up->port.iobase);
outb(value, up->port.iobase + 1);
break;
case UPIO_MEM:
writeb(value, up->port.membase + offset);
break;
default:
outb(value, up->port.iobase + offset);
}
}
/*
* We used to support using pause I/O for certain machines. We
* haven't supported this for a while, but just in case it's badly
* needed for certain old 386 machines, I've left these #define's
* in....
*/
#define serial_inp(up, offset) serial_in(up, offset)
#define serial_outp(up, offset, value) serial_out(up, offset, value)
/*
* For the 16C950
*/
static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
{
serial_out(up, UART_SCR, offset);
serial_out(up, UART_ICR, value);
}
#if 0 /* Unused currently */
static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
{
unsigned int value;
serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
serial_out(up, UART_SCR, offset);
value = serial_in(up, UART_ICR);
serial_icr_write(up, UART_ACR, up->acr);
return value;
}
#endif
#ifdef CONFIG_SERIAL_8250_RSA
/*
* Attempts to turn on the RSA FIFO. Returns zero on failure.
* We set the port uart clock rate if we succeed.
*/
static int __enable_rsa(struct uart_sunsu_port *up)
{
unsigned char mode;
int result;
mode = serial_inp(up, UART_RSA_MSR);
result = mode & UART_RSA_MSR_FIFO;
if (!result) {
serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
mode = serial_inp(up, UART_RSA_MSR);
result = mode & UART_RSA_MSR_FIFO;
}
if (result)
up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
return result;
}
static void enable_rsa(struct uart_sunsu_port *up)
{
if (up->port.type == PORT_RSA) {
if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
spin_lock_irq(&up->port.lock);
__enable_rsa(up);
spin_unlock_irq(&up->port.lock);
}
if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
serial_outp(up, UART_RSA_FRR, 0);
}
}
/*
* Attempts to turn off the RSA FIFO. Returns zero on failure.
* It is unknown why interrupts were disabled in here. However,
* the caller is expected to preserve this behaviour by grabbing
* the spinlock before calling this function.
*/
static void disable_rsa(struct uart_sunsu_port *up)
{
unsigned char mode;
int result;
if (up->port.type == PORT_RSA &&
up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
spin_lock_irq(&up->port.lock);
mode = serial_inp(up, UART_RSA_MSR);
result = !(mode & UART_RSA_MSR_FIFO);
if (!result) {
serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
mode = serial_inp(up, UART_RSA_MSR);
result = !(mode & UART_RSA_MSR_FIFO);
}
if (result)
up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
spin_unlock_irq(&up->port.lock);
}
}
#endif /* CONFIG_SERIAL_8250_RSA */
static inline void __stop_tx(struct uart_sunsu_port *p)
{
if (p->ier & UART_IER_THRI) {
p->ier &= ~UART_IER_THRI;
serial_out(p, UART_IER, p->ier);
}
}
static void sunsu_stop_tx(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
__stop_tx(up);
/*
* We really want to stop the transmitter from sending.
*/
if (up->port.type == PORT_16C950) {
up->acr |= UART_ACR_TXDIS;
serial_icr_write(up, UART_ACR, up->acr);
}
}
static void sunsu_start_tx(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
if (!(up->ier & UART_IER_THRI)) {
up->ier |= UART_IER_THRI;
serial_out(up, UART_IER, up->ier);
}
/*
* Re-enable the transmitter if we disabled it.
*/
if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
up->acr &= ~UART_ACR_TXDIS;
serial_icr_write(up, UART_ACR, up->acr);
}
}
static void sunsu_stop_rx(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
up->ier &= ~UART_IER_RLSI;
up->port.read_status_mask &= ~UART_LSR_DR;
serial_out(up, UART_IER, up->ier);
}
static void sunsu_enable_ms(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
up->ier |= UART_IER_MSI;
serial_out(up, UART_IER, up->ier);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static void
receive_chars(struct uart_sunsu_port *up, unsigned char *status)
{
struct tty_port *port = &up->port.state->port;
unsigned char ch, flag;
int max_count = 256;
int saw_console_brk = 0;
do {
ch = serial_inp(up, UART_RX);
flag = TTY_NORMAL;
up->port.icount.rx++;
if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
UART_LSR_FE | UART_LSR_OE))) {
/*
* For statistics only
*/
if (*status & UART_LSR_BI) {
*status &= ~(UART_LSR_FE | UART_LSR_PE);
up->port.icount.brk++;
if (up->port.cons != NULL &&
up->port.line == up->port.cons->index)
saw_console_brk = 1;
/*
* We do the SysRQ and SAK checking
* here because otherwise the break
* may get masked by ignore_status_mask
* or read_status_mask.
*/
if (uart_handle_break(&up->port))
goto ignore_char;
} else if (*status & UART_LSR_PE)
up->port.icount.parity++;
else if (*status & UART_LSR_FE)
up->port.icount.frame++;
if (*status & UART_LSR_OE)
up->port.icount.overrun++;
/*
* Mask off conditions which should be ingored.
*/
*status &= up->port.read_status_mask;
if (up->port.cons != NULL &&
up->port.line == up->port.cons->index) {
/* Recover the break flag from console xmit */
*status |= up->lsr_break_flag;
up->lsr_break_flag = 0;
}
if (*status & UART_LSR_BI) {
flag = TTY_BREAK;
} else if (*status & UART_LSR_PE)
flag = TTY_PARITY;
else if (*status & UART_LSR_FE)
flag = TTY_FRAME;
}
if (uart_handle_sysrq_char(&up->port, ch))
goto ignore_char;
if ((*status & up->port.ignore_status_mask) == 0)
tty_insert_flip_char(port, ch, flag);
if (*status & UART_LSR_OE)
/*
* Overrun is special, since it's reported
* immediately, and doesn't affect the current
* character.
*/
tty_insert_flip_char(port, 0, TTY_OVERRUN);
ignore_char:
*status = serial_inp(up, UART_LSR);
} while ((*status & UART_LSR_DR) && (max_count-- > 0));
if (saw_console_brk)
sun_do_break();
}
static void transmit_chars(struct uart_sunsu_port *up)
{
struct circ_buf *xmit = &up->port.state->xmit;
int count;
if (up->port.x_char) {
serial_outp(up, UART_TX, up->port.x_char);
up->port.icount.tx++;
up->port.x_char = 0;
return;
}
if (uart_tx_stopped(&up->port)) {
sunsu_stop_tx(&up->port);
return;
}
if (uart_circ_empty(xmit)) {
__stop_tx(up);
return;
}
count = up->port.fifosize;
do {
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
uart_xmit_advance(&up->port, 1);
if (uart_circ_empty(xmit))
break;
} while (--count > 0);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
if (uart_circ_empty(xmit))
__stop_tx(up);
}
static void check_modem_status(struct uart_sunsu_port *up)
{
int status;
status = serial_in(up, UART_MSR);
if ((status & UART_MSR_ANY_DELTA) == 0)
return;
if (status & UART_MSR_TERI)
up->port.icount.rng++;
if (status & UART_MSR_DDSR)
up->port.icount.dsr++;
if (status & UART_MSR_DDCD)
uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
if (status & UART_MSR_DCTS)
uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
}
static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id)
{
struct uart_sunsu_port *up = dev_id;
unsigned long flags;
unsigned char status;
spin_lock_irqsave(&up->port.lock, flags);
do {
status = serial_inp(up, UART_LSR);
if (status & UART_LSR_DR)
receive_chars(up, &status);
check_modem_status(up);
if (status & UART_LSR_THRE)
transmit_chars(up);
tty_flip_buffer_push(&up->port.state->port);
} while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
spin_unlock_irqrestore(&up->port.lock, flags);
return IRQ_HANDLED;
}
/* Separate interrupt handling path for keyboard/mouse ports. */
static void
sunsu_change_speed(struct uart_port *port, unsigned int cflag,
unsigned int iflag, unsigned int quot);
static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
{
unsigned int cur_cflag = up->cflag;
int quot, new_baud;
up->cflag &= ~CBAUD;
up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
quot = up->port.uartclk / (16 * new_baud);
sunsu_change_speed(&up->port, up->cflag, 0, quot);
}
static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break)
{
do {
unsigned char ch = serial_inp(up, UART_RX);
/* Stop-A is handled by drivers/char/keyboard.c now. */
if (up->su_type == SU_PORT_KBD) {
#ifdef CONFIG_SERIO
serio_interrupt(&up->serio, ch, 0);
#endif
} else if (up->su_type == SU_PORT_MS) {
int ret = suncore_mouse_baud_detection(ch, is_break);
switch (ret) {
case 2:
sunsu_change_mouse_baud(up);
fallthrough;
case 1:
break;
case 0:
#ifdef CONFIG_SERIO
serio_interrupt(&up->serio, ch, 0);
#endif
break;
}
}
} while (serial_in(up, UART_LSR) & UART_LSR_DR);
}
static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id)
{
struct uart_sunsu_port *up = dev_id;
if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
unsigned char status = serial_inp(up, UART_LSR);
if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0);
}
return IRQ_HANDLED;
}
static unsigned int sunsu_tx_empty(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned long flags;
unsigned int ret;
spin_lock_irqsave(&up->port.lock, flags);
ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
spin_unlock_irqrestore(&up->port.lock, flags);
return ret;
}
static unsigned int sunsu_get_mctrl(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned char status;
unsigned int ret;
status = serial_in(up, UART_MSR);
ret = 0;
if (status & UART_MSR_DCD)
ret |= TIOCM_CAR;
if (status & UART_MSR_RI)
ret |= TIOCM_RNG;
if (status & UART_MSR_DSR)
ret |= TIOCM_DSR;
if (status & UART_MSR_CTS)
ret |= TIOCM_CTS;
return ret;
}
static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned char mcr = 0;
if (mctrl & TIOCM_RTS)
mcr |= UART_MCR_RTS;
if (mctrl & TIOCM_DTR)
mcr |= UART_MCR_DTR;
if (mctrl & TIOCM_OUT1)
mcr |= UART_MCR_OUT1;
if (mctrl & TIOCM_OUT2)
mcr |= UART_MCR_OUT2;
if (mctrl & TIOCM_LOOP)
mcr |= UART_MCR_LOOP;
serial_out(up, UART_MCR, mcr);
}
static void sunsu_break_ctl(struct uart_port *port, int break_state)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
if (break_state == -1)
up->lcr |= UART_LCR_SBC;
else
up->lcr &= ~UART_LCR_SBC;
serial_out(up, UART_LCR, up->lcr);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static int sunsu_startup(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned long flags;
int retval;
if (up->port.type == PORT_16C950) {
/* Wake up and initialize UART */
up->acr = 0;
serial_outp(up, UART_LCR, 0xBF);
serial_outp(up, UART_EFR, UART_EFR_ECB);
serial_outp(up, UART_IER, 0);
serial_outp(up, UART_LCR, 0);
serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
serial_outp(up, UART_LCR, 0xBF);
serial_outp(up, UART_EFR, UART_EFR_ECB);
serial_outp(up, UART_LCR, 0);
}
#ifdef CONFIG_SERIAL_8250_RSA
/*
* If this is an RSA port, see if we can kick it up to the
* higher speed clock.
*/
enable_rsa(up);
#endif
/*
* Clear the FIFO buffers and disable them.
* (they will be reenabled in set_termios())
*/
if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_outp(up, UART_FCR, 0);
}
/*
* Clear the interrupt registers.
*/
(void) serial_inp(up, UART_LSR);
(void) serial_inp(up, UART_RX);
(void) serial_inp(up, UART_IIR);
(void) serial_inp(up, UART_MSR);
/*
* At this point, there's no way the LSR could still be 0xff;
* if it is, then bail out, because there's likely no UART
* here.
*/
if (!(up->port.flags & UPF_BUGGY_UART) &&
(serial_inp(up, UART_LSR) == 0xff)) {
printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
return -ENODEV;
}
if (up->su_type != SU_PORT_PORT) {
retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
IRQF_SHARED, su_typev[up->su_type], up);
} else {
retval = request_irq(up->port.irq, sunsu_serial_interrupt,
IRQF_SHARED, su_typev[up->su_type], up);
}
if (retval) {
printk("su: Cannot register IRQ %d\n", up->port.irq);
return retval;
}
/*
* Now, initialize the UART
*/
serial_outp(up, UART_LCR, UART_LCR_WLEN8);
spin_lock_irqsave(&up->port.lock, flags);
up->port.mctrl |= TIOCM_OUT2;
sunsu_set_mctrl(&up->port, up->port.mctrl);
spin_unlock_irqrestore(&up->port.lock, flags);
/*
* Finally, enable interrupts. Note: Modem status interrupts
* are set via set_termios(), which will be occurring imminently
* anyway, so we don't enable them here.
*/
up->ier = UART_IER_RLSI | UART_IER_RDI;
serial_outp(up, UART_IER, up->ier);
if (up->port.flags & UPF_FOURPORT) {
unsigned int icp;
/*
* Enable interrupts on the AST Fourport board
*/
icp = (up->port.iobase & 0xfe0) | 0x01f;
outb_p(0x80, icp);
(void) inb_p(icp);
}
/*
* And clear the interrupt registers again for luck.
*/
(void) serial_inp(up, UART_LSR);
(void) serial_inp(up, UART_RX);
(void) serial_inp(up, UART_IIR);
(void) serial_inp(up, UART_MSR);
return 0;
}
static void sunsu_shutdown(struct uart_port *port)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned long flags;
/*
* Disable interrupts from this port
*/
up->ier = 0;
serial_outp(up, UART_IER, 0);
spin_lock_irqsave(&up->port.lock, flags);
if (up->port.flags & UPF_FOURPORT) {
/* reset interrupts on the AST Fourport board */
inb((up->port.iobase & 0xfe0) | 0x1f);
up->port.mctrl |= TIOCM_OUT1;
} else
up->port.mctrl &= ~TIOCM_OUT2;
sunsu_set_mctrl(&up->port, up->port.mctrl);
spin_unlock_irqrestore(&up->port.lock, flags);
/*
* Disable break condition and FIFOs
*/
serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR |
UART_FCR_CLEAR_XMIT);
serial_outp(up, UART_FCR, 0);
#ifdef CONFIG_SERIAL_8250_RSA
/*
* Reset the RSA board back to 115kbps compat mode.
*/
disable_rsa(up);
#endif
/*
* Read data port to reset things.
*/
(void) serial_in(up, UART_RX);
free_irq(up->port.irq, up);
}
static void
sunsu_change_speed(struct uart_port *port, unsigned int cflag,
unsigned int iflag, unsigned int quot)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
unsigned char cval, fcr = 0;
unsigned long flags;
switch (cflag & CSIZE) {
case CS5:
cval = 0x00;
break;
case CS6:
cval = 0x01;
break;
case CS7:
cval = 0x02;
break;
default:
case CS8:
cval = 0x03;
break;
}
if (cflag & CSTOPB)
cval |= 0x04;
if (cflag & PARENB)
cval |= UART_LCR_PARITY;
if (!(cflag & PARODD))
cval |= UART_LCR_EPAR;
if (cflag & CMSPAR)
cval |= UART_LCR_SPAR;
/*
* Work around a bug in the Oxford Semiconductor 952 rev B
* chip which causes it to seriously miscalculate baud rates
* when DLL is 0.
*/
if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
up->rev == 0x5201)
quot ++;
if (uart_config[up->port.type].flags & UART_USE_FIFO) {
if ((up->port.uartclk / quot) < (2400 * 16))
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
#ifdef CONFIG_SERIAL_8250_RSA
else if (up->port.type == PORT_RSA)
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
#endif
else
fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
}
if (up->port.type == PORT_16750)
fcr |= UART_FCR7_64BYTE;
/*
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*/
spin_lock_irqsave(&up->port.lock, flags);
/*
* Update the per-port timeout.
*/
uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (iflag & INPCK)
up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
if (iflag & (IGNBRK | BRKINT | PARMRK))
up->port.read_status_mask |= UART_LSR_BI;
/*
* Characteres to ignore
*/
up->port.ignore_status_mask = 0;
if (iflag & IGNPAR)
up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
if (iflag & IGNBRK) {
up->port.ignore_status_mask |= UART_LSR_BI;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (iflag & IGNPAR)
up->port.ignore_status_mask |= UART_LSR_OE;
}
/*
* ignore all characters if CREAD is not set
*/
if ((cflag & CREAD) == 0)
up->port.ignore_status_mask |= UART_LSR_DR;
/*
* CTS flow control flag and modem status interrupts
*/
up->ier &= ~UART_IER_MSI;
if (UART_ENABLE_MS(&up->port, cflag))
up->ier |= UART_IER_MSI;
serial_out(up, UART_IER, up->ier);
if (uart_config[up->port.type].flags & UART_STARTECH) {
serial_outp(up, UART_LCR, 0xBF);
serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
}
serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
if (up->port.type == PORT_16750)
serial_outp(up, UART_FCR, fcr); /* set fcr */
serial_outp(up, UART_LCR, cval); /* reset DLAB */
up->lcr = cval; /* Save LCR */
if (up->port.type != PORT_16750) {
if (fcr & UART_FCR_ENABLE_FIFO) {
/* emulated UARTs (Lucent Venus 167x) need two steps */
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
}
serial_outp(up, UART_FCR, fcr); /* set fcr */
}
up->cflag = cflag;
spin_unlock_irqrestore(&up->port.lock, flags);
}
static void
sunsu_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
unsigned int baud, quot;
/*
* Ask the core to calculate the divisor for us.
*/
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
quot = uart_get_divisor(port, baud);
sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
}
static void sunsu_release_port(struct uart_port *port)
{
}
static int sunsu_request_port(struct uart_port *port)
{
return 0;
}
static void sunsu_config_port(struct uart_port *port, int flags)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
if (flags & UART_CONFIG_TYPE) {
/*
* We are supposed to call autoconfig here, but this requires
* splitting all the OBP probing crap from the UART probing.
* We'll do it when we kill sunsu.c altogether.
*/
port->type = up->type_probed; /* XXX */
}
}
static int
sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
{
return -EINVAL;
}
static const char *
sunsu_type(struct uart_port *port)
{
int type = port->type;
if (type >= ARRAY_SIZE(uart_config))
type = 0;
return uart_config[type].name;
}
static const struct uart_ops sunsu_pops = {
.tx_empty = sunsu_tx_empty,
.set_mctrl = sunsu_set_mctrl,
.get_mctrl = sunsu_get_mctrl,
.stop_tx = sunsu_stop_tx,
.start_tx = sunsu_start_tx,
.stop_rx = sunsu_stop_rx,
.enable_ms = sunsu_enable_ms,
.break_ctl = sunsu_break_ctl,
.startup = sunsu_startup,
.shutdown = sunsu_shutdown,
.set_termios = sunsu_set_termios,
.type = sunsu_type,
.release_port = sunsu_release_port,
.request_port = sunsu_request_port,
.config_port = sunsu_config_port,
.verify_port = sunsu_verify_port,
};
#define UART_NR 4
static struct uart_sunsu_port sunsu_ports[UART_NR];
static int nr_inst; /* Number of already registered ports */
#ifdef CONFIG_SERIO
static DEFINE_SPINLOCK(sunsu_serio_lock);
static int sunsu_serio_write(struct serio *serio, unsigned char ch)
{
struct uart_sunsu_port *up = serio->port_data;
unsigned long flags;
int lsr;
spin_lock_irqsave(&sunsu_serio_lock, flags);
do {
lsr = serial_in(up, UART_LSR);
} while (!(lsr & UART_LSR_THRE));
/* Send the character out. */
serial_out(up, UART_TX, ch);
spin_unlock_irqrestore(&sunsu_serio_lock, flags);
return 0;
}
static int sunsu_serio_open(struct serio *serio)
{
struct uart_sunsu_port *up = serio->port_data;
unsigned long flags;
int ret;
spin_lock_irqsave(&sunsu_serio_lock, flags);
if (!up->serio_open) {
up->serio_open = 1;
ret = 0;
} else
ret = -EBUSY;
spin_unlock_irqrestore(&sunsu_serio_lock, flags);
return ret;
}
static void sunsu_serio_close(struct serio *serio)
{
struct uart_sunsu_port *up = serio->port_data;
unsigned long flags;
spin_lock_irqsave(&sunsu_serio_lock, flags);
up->serio_open = 0;
spin_unlock_irqrestore(&sunsu_serio_lock, flags);
}
#endif /* CONFIG_SERIO */
static void sunsu_autoconfig(struct uart_sunsu_port *up)
{
unsigned char status1, status2, scratch, scratch2, scratch3;
unsigned char save_lcr, save_mcr;
unsigned long flags;
if (up->su_type == SU_PORT_NONE)
return;
up->type_probed = PORT_UNKNOWN;
up->port.iotype = UPIO_MEM;
spin_lock_irqsave(&up->port.lock, flags);
if (!(up->port.flags & UPF_BUGGY_UART)) {
/*
* Do a simple existence test first; if we fail this, there's
* no point trying anything else.
*
* 0x80 is used as a nonsense port to prevent against false
* positives due to ISA bus float. The assumption is that
* 0x80 is a non-existent port; which should be safe since
* include/asm/io.h also makes this assumption.
*/
scratch = serial_inp(up, UART_IER);
serial_outp(up, UART_IER, 0);
#ifdef __i386__
outb(0xff, 0x080);
#endif
scratch2 = serial_inp(up, UART_IER);
serial_outp(up, UART_IER, 0x0f);
#ifdef __i386__
outb(0, 0x080);
#endif
scratch3 = serial_inp(up, UART_IER);
serial_outp(up, UART_IER, scratch);
if (scratch2 != 0 || scratch3 != 0x0F)
goto out; /* We failed; there's nothing here */
}
save_mcr = serial_in(up, UART_MCR);
save_lcr = serial_in(up, UART_LCR);
/*
* Check to see if a UART is really there. Certain broken
* internal modems based on the Rockwell chipset fail this
* test, because they apparently don't implement the loopback
* test mode. So this test is skipped on the COM 1 through
* COM 4 ports. This *should* be safe, since no board
* manufacturer would be stupid enough to design a board
* that conflicts with COM 1-4 --- we hope!
*/
if (!(up->port.flags & UPF_SKIP_TEST)) {
serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
status1 = serial_inp(up, UART_MSR) & 0xF0;
serial_outp(up, UART_MCR, save_mcr);
if (status1 != 0x90)
goto out; /* We failed loopback test */
}
serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
serial_outp(up, UART_LCR, 0);
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
scratch = serial_in(up, UART_IIR) >> 6;
switch (scratch) {
case 0:
up->port.type = PORT_16450;
break;
case 1:
up->port.type = PORT_UNKNOWN;
break;
case 2:
up->port.type = PORT_16550;
break;
case 3:
up->port.type = PORT_16550A;
break;
}
if (up->port.type == PORT_16550A) {
/* Check for Startech UART's */
serial_outp(up, UART_LCR, UART_LCR_DLAB);
if (serial_in(up, UART_EFR) == 0) {
up->port.type = PORT_16650;
} else {
serial_outp(up, UART_LCR, 0xBF);
if (serial_in(up, UART_EFR) == 0)
up->port.type = PORT_16650V2;
}
}
if (up->port.type == PORT_16550A) {
/* Check for TI 16750 */
serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
serial_outp(up, UART_FCR,
UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
scratch = serial_in(up, UART_IIR) >> 5;
if (scratch == 7) {
/*
* If this is a 16750, and not a cheap UART
* clone, then it should only go into 64 byte
* mode if the UART_FCR7_64BYTE bit was set
* while UART_LCR_DLAB was latched.
*/
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_outp(up, UART_LCR, 0);
serial_outp(up, UART_FCR,
UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
scratch = serial_in(up, UART_IIR) >> 5;
if (scratch == 6)
up->port.type = PORT_16750;
}
serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
}
serial_outp(up, UART_LCR, save_lcr);
if (up->port.type == PORT_16450) {
scratch = serial_in(up, UART_SCR);
serial_outp(up, UART_SCR, 0xa5);
status1 = serial_in(up, UART_SCR);
serial_outp(up, UART_SCR, 0x5a);
status2 = serial_in(up, UART_SCR);
serial_outp(up, UART_SCR, scratch);
if ((status1 != 0xa5) || (status2 != 0x5a))
up->port.type = PORT_8250;
}
up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
if (up->port.type == PORT_UNKNOWN)
goto out;
up->type_probed = up->port.type; /* XXX */
/*
* Reset the UART.
*/
#ifdef CONFIG_SERIAL_8250_RSA
if (up->port.type == PORT_RSA)
serial_outp(up, UART_RSA_FRR, 0);
#endif
serial_outp(up, UART_MCR, save_mcr);
serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR |
UART_FCR_CLEAR_XMIT));
serial_outp(up, UART_FCR, 0);
(void)serial_in(up, UART_RX);
serial_outp(up, UART_IER, 0);
out:
spin_unlock_irqrestore(&up->port.lock, flags);
}
static struct uart_driver sunsu_reg = {
.owner = THIS_MODULE,
.driver_name = "sunsu",
.dev_name = "ttyS",
.major = TTY_MAJOR,
};
static int sunsu_kbd_ms_init(struct uart_sunsu_port *up)
{
int quot, baud;
#ifdef CONFIG_SERIO
struct serio *serio;
#endif
if (up->su_type == SU_PORT_KBD) {
up->cflag = B1200 | CS8 | CLOCAL | CREAD;
baud = 1200;
} else {
up->cflag = B4800 | CS8 | CLOCAL | CREAD;
baud = 4800;
}
quot = up->port.uartclk / (16 * baud);
sunsu_autoconfig(up);
if (up->port.type == PORT_UNKNOWN)
return -ENODEV;
printk("%pOF: %s port at %llx, irq %u\n",
up->port.dev->of_node,
(up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse",
(unsigned long long) up->port.mapbase,
up->port.irq);
#ifdef CONFIG_SERIO
serio = &up->serio;
serio->port_data = up;
serio->id.type = SERIO_RS232;
if (up->su_type == SU_PORT_KBD) {
serio->id.proto = SERIO_SUNKBD;
strscpy(serio->name, "sukbd", sizeof(serio->name));
} else {
serio->id.proto = SERIO_SUN;
serio->id.extra = 1;
strscpy(serio->name, "sums", sizeof(serio->name));
}
strscpy(serio->phys,
(!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
sizeof(serio->phys));
serio->write = sunsu_serio_write;
serio->open = sunsu_serio_open;
serio->close = sunsu_serio_close;
serio->dev.parent = up->port.dev;
serio_register_port(serio);
#endif
sunsu_change_speed(&up->port, up->cflag, 0, quot);
sunsu_startup(&up->port);
return 0;
}
/*
* ------------------------------------------------------------
* Serial console driver
* ------------------------------------------------------------
*/
#ifdef CONFIG_SERIAL_SUNSU_CONSOLE
/*
* Wait for transmitter & holding register to empty
*/
static void wait_for_xmitr(struct uart_sunsu_port *up)
{
unsigned int status, tmout = 10000;
/* Wait up to 10ms for the character(s) to be sent. */
do {
status = serial_in(up, UART_LSR);
if (status & UART_LSR_BI)
up->lsr_break_flag = UART_LSR_BI;
if (--tmout == 0)
break;
udelay(1);
} while (!uart_lsr_tx_empty(status));
/* Wait up to 1s for flow control if necessary */
if (up->port.flags & UPF_CONS_FLOW) {
tmout = 1000000;
while (--tmout &&
((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
udelay(1);
}
}
static void sunsu_console_putchar(struct uart_port *port, unsigned char ch)
{
struct uart_sunsu_port *up =
container_of(port, struct uart_sunsu_port, port);
wait_for_xmitr(up);
serial_out(up, UART_TX, ch);
}
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*/
static void sunsu_console_write(struct console *co, const char *s,
unsigned int count)
{
struct uart_sunsu_port *up = &sunsu_ports[co->index];
unsigned long flags;
unsigned int ier;
int locked = 1;
if (up->port.sysrq || oops_in_progress)
locked = spin_trylock_irqsave(&up->port.lock, flags);
else
spin_lock_irqsave(&up->port.lock, flags);
/*
* First save the UER then disable the interrupts
*/
ier = serial_in(up, UART_IER);
serial_out(up, UART_IER, 0);
uart_console_write(&up->port, s, count, sunsu_console_putchar);
/*
* Finally, wait for transmitter to become empty
* and restore the IER
*/
wait_for_xmitr(up);
serial_out(up, UART_IER, ier);
if (locked)
spin_unlock_irqrestore(&up->port.lock, flags);
}
/*
* Setup initial baud/bits/parity. We do two things here:
* - construct a cflag setting for the first su_open()
* - initialize the serial port
* Return non-zero if we didn't find a serial port.
*/
static int __init sunsu_console_setup(struct console *co, char *options)
{
static struct ktermios dummy;
struct ktermios termios;
struct uart_port *port;
printk("Console: ttyS%d (SU)\n",
(sunsu_reg.minor - 64) + co->index);
if (co->index > nr_inst)
return -ENODEV;
port = &sunsu_ports[co->index].port;
/*
* Temporary fix.
*/
spin_lock_init(&port->lock);
/* Get firmware console settings. */
sunserial_console_termios(co, port->dev->of_node);
memset(&termios, 0, sizeof(struct ktermios));
termios.c_cflag = co->cflag;
port->mctrl |= TIOCM_DTR;
port->ops->set_termios(port, &termios, &dummy);
return 0;
}
static struct console sunsu_console = {
.name = "ttyS",
.write = sunsu_console_write,
.device = uart_console_device,
.setup = sunsu_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &sunsu_reg,
};
/*
* Register console.
*/
static inline struct console *SUNSU_CONSOLE(void)
{
return &sunsu_console;
}
#else
#define SUNSU_CONSOLE() (NULL)
#define sunsu_serial_console_init() do { } while (0)
#endif
static enum su_type su_get_type(struct device_node *dp)
{
struct device_node *ap = of_find_node_by_path("/aliases");
enum su_type rc = SU_PORT_PORT;
if (ap) {
const char *keyb = of_get_property(ap, "keyboard", NULL);
const char *ms = of_get_property(ap, "mouse", NULL);
struct device_node *match;
if (keyb) {
match = of_find_node_by_path(keyb);
/*
* The pointer is used as an identifier not
* as a pointer, we can drop the refcount on
* the of__node immediately after getting it.
*/
of_node_put(match);
if (dp == match) {
rc = SU_PORT_KBD;
goto out;
}
}
if (ms) {
match = of_find_node_by_path(ms);
of_node_put(match);
if (dp == match) {
rc = SU_PORT_MS;
goto out;
}
}
}
out:
of_node_put(ap);
return rc;
}
static int su_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct uart_sunsu_port *up;
struct resource *rp;
enum su_type type;
bool ignore_line;
int err;
type = su_get_type(dp);
if (type == SU_PORT_PORT) {
if (nr_inst >= UART_NR)
return -EINVAL;
up = &sunsu_ports[nr_inst];
} else {
up = kzalloc(sizeof(*up), GFP_KERNEL);
if (!up)
return -ENOMEM;
}
up->port.line = nr_inst;
spin_lock_init(&up->port.lock);
up->su_type = type;
rp = &op->resource[0];
up->port.mapbase = rp->start;
up->reg_size = resource_size(rp);
up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
if (!up->port.membase) {
if (type != SU_PORT_PORT)
kfree(up);
return -ENOMEM;
}
up->port.irq = op->archdata.irqs[0];
up->port.dev = &op->dev;
up->port.type = PORT_UNKNOWN;
up->port.uartclk = (SU_BASE_BAUD * 16);
up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSU_CONSOLE);
err = 0;
if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
err = sunsu_kbd_ms_init(up);
if (err) {
of_iounmap(&op->resource[0],
up->port.membase, up->reg_size);
kfree(up);
return err;
}
platform_set_drvdata(op, up);
nr_inst++;
return 0;
}
up->port.flags |= UPF_BOOT_AUTOCONF;
sunsu_autoconfig(up);
err = -ENODEV;
if (up->port.type == PORT_UNKNOWN)
goto out_unmap;
up->port.ops = &sunsu_pops;
ignore_line = false;
if (of_node_name_eq(dp, "rsc-console") ||
of_node_name_eq(dp, "lom-console"))
ignore_line = true;
sunserial_console_match(SUNSU_CONSOLE(), dp,
&sunsu_reg, up->port.line,
ignore_line);
err = uart_add_one_port(&sunsu_reg, &up->port);
if (err)
goto out_unmap;
platform_set_drvdata(op, up);
nr_inst++;
return 0;
out_unmap:
of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
kfree(up);
return err;
}
static int su_remove(struct platform_device *op)
{
struct uart_sunsu_port *up = platform_get_drvdata(op);
bool kbdms = false;
if (up->su_type == SU_PORT_MS ||
up->su_type == SU_PORT_KBD)
kbdms = true;
if (kbdms) {
#ifdef CONFIG_SERIO
serio_unregister_port(&up->serio);
#endif
} else if (up->port.type != PORT_UNKNOWN)
uart_remove_one_port(&sunsu_reg, &up->port);
if (up->port.membase)
of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
if (kbdms)
kfree(up);
return 0;
}
static const struct of_device_id su_match[] = {
{
.name = "su",
},
{
.name = "su_pnp",
},
{
.name = "serial",
.compatible = "su",
},
{
.type = "serial",
.compatible = "su",
},
{},
};
MODULE_DEVICE_TABLE(of, su_match);
static struct platform_driver su_driver = {
.driver = {
.name = "su",
.of_match_table = su_match,
},
.probe = su_probe,
.remove = su_remove,
};
static int __init sunsu_init(void)
{
struct device_node *dp;
int err;
int num_uart = 0;
for_each_node_by_name(dp, "su") {
if (su_get_type(dp) == SU_PORT_PORT)
num_uart++;
}
for_each_node_by_name(dp, "su_pnp") {
if (su_get_type(dp) == SU_PORT_PORT)
num_uart++;
}
for_each_node_by_name(dp, "serial") {
if (of_device_is_compatible(dp, "su")) {
if (su_get_type(dp) == SU_PORT_PORT)
num_uart++;
}
}
for_each_node_by_type(dp, "serial") {
if (of_device_is_compatible(dp, "su")) {
if (su_get_type(dp) == SU_PORT_PORT)
num_uart++;
}
}
if (num_uart) {
err = sunserial_register_minors(&sunsu_reg, num_uart);
if (err)
return err;
}
err = platform_driver_register(&su_driver);
if (err && num_uart)
sunserial_unregister_minors(&sunsu_reg, num_uart);
return err;
}
static void __exit sunsu_exit(void)
{
platform_driver_unregister(&su_driver);
if (sunsu_reg.nr)
sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr);
}
module_init(sunsu_init);
module_exit(sunsu_exit);
MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller");
MODULE_DESCRIPTION("Sun SU serial port driver");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/sunsu.c |
// SPDX-License-Identifier: GPL-2.0
/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
*
* Copyright (C) 1997 Eddie C. Dost ([email protected])
* Copyright (C) 2002, 2006 David S. Miller ([email protected])
*
* Rewrote buffer handling to use CIRC(Circular Buffer) macros.
* Maxim Krasnyanskiy <[email protected]>
*
* Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
* rates to be programmed into the UART. Also eliminated a lot of
* duplicated code in the console setup.
* Theodore Ts'o <[email protected]>, 2001-Oct-12
*
* Ported to new 2.5.x UART layer.
* David S. Miller <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/sysrq.h>
#include <linux/console.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/setup.h>
#include <linux/serial_core.h>
#include <linux/sunserialcore.h>
#include "sunsab.h"
struct uart_sunsab_port {
struct uart_port port; /* Generic UART port */
union sab82532_async_regs __iomem *regs; /* Chip registers */
unsigned long irqflags; /* IRQ state flags */
int dsr; /* Current DSR state */
unsigned int cec_timeout; /* Chip poll timeout... */
unsigned int tec_timeout; /* likewise */
unsigned char interrupt_mask0;/* ISR0 masking */
unsigned char interrupt_mask1;/* ISR1 masking */
unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
unsigned int gis_shift;
int type; /* SAB82532 version */
/* Setting configuration bits while the transmitter is active
* can cause garbage characters to get emitted by the chip.
* Therefore, we cache such writes here and do the real register
* write the next time the transmitter becomes idle.
*/
unsigned int cached_ebrg;
unsigned char cached_mode;
unsigned char cached_pvr;
unsigned char cached_dafo;
};
/*
* This assumes you have a 29.4912 MHz clock for your UART.
*/
#define SAB_BASE_BAUD ( 29491200 / 16 )
static char *sab82532_version[16] = {
"V1.0", "V2.0", "V3.2", "V(0x03)",
"V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
"V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
"V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
};
#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
#define SAB82532_XMIT_FIFO_SIZE 32
static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
{
int timeout = up->tec_timeout;
while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
udelay(1);
}
static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
{
int timeout = up->cec_timeout;
while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
udelay(1);
}
static struct tty_port *
receive_chars(struct uart_sunsab_port *up,
union sab82532_irq_status *stat)
{
struct tty_port *port = NULL;
unsigned char buf[32];
int saw_console_brk = 0;
int free_fifo = 0;
int count = 0;
int i;
if (up->port.state != NULL) /* Unopened serial console */
port = &up->port.state->port;
/* Read number of BYTES (Character + Status) available. */
if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
count = SAB82532_RECV_FIFO_SIZE;
free_fifo++;
}
if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
free_fifo++;
}
/* Issue a FIFO read command in case we where idle. */
if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
sunsab_cec_wait(up);
writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
return port;
}
if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
free_fifo++;
/* Read the FIFO. */
for (i = 0; i < count; i++)
buf[i] = readb(&up->regs->r.rfifo[i]);
/* Issue Receive Message Complete command. */
if (free_fifo) {
sunsab_cec_wait(up);
writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
}
/* Count may be zero for BRK, so we check for it here */
if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
(up->port.line == up->port.cons->index))
saw_console_brk = 1;
if (count == 0) {
if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
SAB82532_ISR0_FERR);
up->port.icount.brk++;
uart_handle_break(&up->port);
}
}
for (i = 0; i < count; i++) {
unsigned char ch = buf[i], flag;
flag = TTY_NORMAL;
up->port.icount.rx++;
if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
SAB82532_ISR0_FERR |
SAB82532_ISR0_RFO)) ||
unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
/*
* For statistics only
*/
if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
SAB82532_ISR0_FERR);
up->port.icount.brk++;
/*
* We do the SysRQ and SAK checking
* here because otherwise the break
* may get masked by ignore_status_mask
* or read_status_mask.
*/
if (uart_handle_break(&up->port))
continue;
} else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
up->port.icount.parity++;
else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
up->port.icount.frame++;
if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
up->port.icount.overrun++;
/*
* Mask off conditions which should be ingored.
*/
stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
flag = TTY_BREAK;
} else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
flag = TTY_PARITY;
else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
flag = TTY_FRAME;
}
if (uart_handle_sysrq_char(&up->port, ch) || !port)
continue;
if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
(stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
tty_insert_flip_char(port, ch, flag);
if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
tty_insert_flip_char(port, 0, TTY_OVERRUN);
}
if (saw_console_brk)
sun_do_break();
return port;
}
static void sunsab_stop_tx(struct uart_port *);
static void sunsab_tx_idle(struct uart_sunsab_port *);
static void transmit_chars(struct uart_sunsab_port *up,
union sab82532_irq_status *stat)
{
struct circ_buf *xmit = &up->port.state->xmit;
int i;
if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
writeb(up->interrupt_mask1, &up->regs->w.imr1);
set_bit(SAB82532_ALLS, &up->irqflags);
}
#if 0 /* [email protected] says this check causes problems */
if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
return;
#endif
if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
return;
set_bit(SAB82532_XPR, &up->irqflags);
sunsab_tx_idle(up);
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
up->interrupt_mask1 |= SAB82532_IMR1_XPR;
writeb(up->interrupt_mask1, &up->regs->w.imr1);
return;
}
up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
writeb(up->interrupt_mask1, &up->regs->w.imr1);
clear_bit(SAB82532_ALLS, &up->irqflags);
/* Stuff 32 bytes into Transmit FIFO. */
clear_bit(SAB82532_XPR, &up->irqflags);
for (i = 0; i < up->port.fifosize; i++) {
writeb(xmit->buf[xmit->tail],
&up->regs->w.xfifo[i]);
uart_xmit_advance(&up->port, 1);
if (uart_circ_empty(xmit))
break;
}
/* Issue a Transmit Frame command. */
sunsab_cec_wait(up);
writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&up->port);
if (uart_circ_empty(xmit))
sunsab_stop_tx(&up->port);
}
static void check_status(struct uart_sunsab_port *up,
union sab82532_irq_status *stat)
{
if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
uart_handle_dcd_change(&up->port,
!(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
uart_handle_cts_change(&up->port,
(readb(&up->regs->r.star) & SAB82532_STAR_CTS));
if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
up->port.icount.dsr++;
}
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
}
static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
{
struct uart_sunsab_port *up = dev_id;
struct tty_port *port = NULL;
union sab82532_irq_status status;
unsigned long flags;
unsigned char gis;
spin_lock_irqsave(&up->port.lock, flags);
status.stat = 0;
gis = readb(&up->regs->r.gis) >> up->gis_shift;
if (gis & 1)
status.sreg.isr0 = readb(&up->regs->r.isr0);
if (gis & 2)
status.sreg.isr1 = readb(&up->regs->r.isr1);
if (status.stat) {
if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
(status.sreg.isr1 & SAB82532_ISR1_BRK))
port = receive_chars(up, &status);
if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
(status.sreg.isr1 & SAB82532_ISR1_CSC))
check_status(up, &status);
if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
transmit_chars(up, &status);
}
spin_unlock_irqrestore(&up->port.lock, flags);
if (port)
tty_flip_buffer_push(port);
return IRQ_HANDLED;
}
/* port->lock is not held. */
static unsigned int sunsab_tx_empty(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
int ret;
/* Do not need a lock for a state test like this. */
if (test_bit(SAB82532_ALLS, &up->irqflags))
ret = TIOCSER_TEMT;
else
ret = 0;
return ret;
}
/* port->lock held by caller. */
static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
if (mctrl & TIOCM_RTS) {
up->cached_mode &= ~SAB82532_MODE_FRTS;
up->cached_mode |= SAB82532_MODE_RTS;
} else {
up->cached_mode |= (SAB82532_MODE_FRTS |
SAB82532_MODE_RTS);
}
if (mctrl & TIOCM_DTR) {
up->cached_pvr &= ~(up->pvr_dtr_bit);
} else {
up->cached_pvr |= up->pvr_dtr_bit;
}
set_bit(SAB82532_REGS_PENDING, &up->irqflags);
if (test_bit(SAB82532_XPR, &up->irqflags))
sunsab_tx_idle(up);
}
/* port->lock is held by caller and interrupts are disabled. */
static unsigned int sunsab_get_mctrl(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
unsigned char val;
unsigned int result;
result = 0;
val = readb(&up->regs->r.pvr);
result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
val = readb(&up->regs->r.vstr);
result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
val = readb(&up->regs->r.star);
result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
return result;
}
/* port->lock held by caller. */
static void sunsab_stop_tx(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
up->interrupt_mask1 |= SAB82532_IMR1_XPR;
writeb(up->interrupt_mask1, &up->regs->w.imr1);
}
/* port->lock held by caller. */
static void sunsab_tx_idle(struct uart_sunsab_port *up)
{
if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
u8 tmp;
clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
writeb(up->cached_mode, &up->regs->rw.mode);
writeb(up->cached_pvr, &up->regs->rw.pvr);
writeb(up->cached_dafo, &up->regs->w.dafo);
writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
tmp = readb(&up->regs->rw.ccr2);
tmp &= ~0xc0;
tmp |= (up->cached_ebrg >> 2) & 0xc0;
writeb(tmp, &up->regs->rw.ccr2);
}
}
/* port->lock held by caller. */
static void sunsab_start_tx(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
struct circ_buf *xmit = &up->port.state->xmit;
int i;
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
return;
up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
writeb(up->interrupt_mask1, &up->regs->w.imr1);
if (!test_bit(SAB82532_XPR, &up->irqflags))
return;
clear_bit(SAB82532_ALLS, &up->irqflags);
clear_bit(SAB82532_XPR, &up->irqflags);
for (i = 0; i < up->port.fifosize; i++) {
writeb(xmit->buf[xmit->tail],
&up->regs->w.xfifo[i]);
uart_xmit_advance(&up->port, 1);
if (uart_circ_empty(xmit))
break;
}
/* Issue a Transmit Frame command. */
sunsab_cec_wait(up);
writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
}
/* port->lock is not held. */
static void sunsab_send_xchar(struct uart_port *port, char ch)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
unsigned long flags;
if (ch == __DISABLED_CHAR)
return;
spin_lock_irqsave(&up->port.lock, flags);
sunsab_tec_wait(up);
writeb(ch, &up->regs->w.tic);
spin_unlock_irqrestore(&up->port.lock, flags);
}
/* port->lock held by caller. */
static void sunsab_stop_rx(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
up->interrupt_mask0 |= SAB82532_IMR0_TCD;
writeb(up->interrupt_mask1, &up->regs->w.imr0);
}
/* port->lock is not held. */
static void sunsab_break_ctl(struct uart_port *port, int break_state)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
unsigned long flags;
unsigned char val;
spin_lock_irqsave(&up->port.lock, flags);
val = up->cached_dafo;
if (break_state)
val |= SAB82532_DAFO_XBRK;
else
val &= ~SAB82532_DAFO_XBRK;
up->cached_dafo = val;
set_bit(SAB82532_REGS_PENDING, &up->irqflags);
if (test_bit(SAB82532_XPR, &up->irqflags))
sunsab_tx_idle(up);
spin_unlock_irqrestore(&up->port.lock, flags);
}
/* port->lock is not held. */
static int sunsab_startup(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
unsigned long flags;
unsigned char tmp;
int err = request_irq(up->port.irq, sunsab_interrupt,
IRQF_SHARED, "sab", up);
if (err)
return err;
spin_lock_irqsave(&up->port.lock, flags);
/*
* Wait for any commands or immediate characters
*/
sunsab_cec_wait(up);
sunsab_tec_wait(up);
/*
* Clear the FIFO buffers.
*/
writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
sunsab_cec_wait(up);
writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
/*
* Clear the interrupt registers.
*/
(void) readb(&up->regs->r.isr0);
(void) readb(&up->regs->r.isr1);
/*
* Now, initialize the UART
*/
writeb(0, &up->regs->w.ccr0); /* power-down */
writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
SAB82532_CCR2_TOE, &up->regs->w.ccr2);
writeb(0, &up->regs->w.ccr3);
writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
SAB82532_MODE_RAC);
writeb(up->cached_mode, &up->regs->w.mode);
writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
tmp = readb(&up->regs->rw.ccr0);
tmp |= SAB82532_CCR0_PU; /* power-up */
writeb(tmp, &up->regs->rw.ccr0);
/*
* Finally, enable interrupts
*/
up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
SAB82532_IMR0_PLLA);
writeb(up->interrupt_mask0, &up->regs->w.imr0);
up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
SAB82532_IMR1_XPR);
writeb(up->interrupt_mask1, &up->regs->w.imr1);
set_bit(SAB82532_ALLS, &up->irqflags);
set_bit(SAB82532_XPR, &up->irqflags);
spin_unlock_irqrestore(&up->port.lock, flags);
return 0;
}
/* port->lock is not held. */
static void sunsab_shutdown(struct uart_port *port)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
/* Disable Interrupts */
up->interrupt_mask0 = 0xff;
writeb(up->interrupt_mask0, &up->regs->w.imr0);
up->interrupt_mask1 = 0xff;
writeb(up->interrupt_mask1, &up->regs->w.imr1);
/* Disable break condition */
up->cached_dafo = readb(&up->regs->rw.dafo);
up->cached_dafo &= ~SAB82532_DAFO_XBRK;
writeb(up->cached_dafo, &up->regs->rw.dafo);
/* Disable Receiver */
up->cached_mode &= ~SAB82532_MODE_RAC;
writeb(up->cached_mode, &up->regs->rw.mode);
/*
* XXX FIXME
*
* If the chip is powered down here the system hangs/crashes during
* reboot or shutdown. This needs to be investigated further,
* similar behaviour occurs in 2.4 when the driver is configured
* as a module only. One hint may be that data is sometimes
* transmitted at 9600 baud during shutdown (regardless of the
* speed the chip was configured for when the port was open).
*/
#if 0
/* Power Down */
tmp = readb(&up->regs->rw.ccr0);
tmp &= ~SAB82532_CCR0_PU;
writeb(tmp, &up->regs->rw.ccr0);
#endif
spin_unlock_irqrestore(&up->port.lock, flags);
free_irq(up->port.irq, up);
}
/*
* This is used to figure out the divisor speeds.
*
* The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
*
* with 0 <= N < 64 and 0 <= M < 16
*/
static void calc_ebrg(int baud, int *n_ret, int *m_ret)
{
int n, m;
if (baud == 0) {
*n_ret = 0;
*m_ret = 0;
return;
}
/*
* We scale numbers by 10 so that we get better accuracy
* without having to use floating point. Here we increment m
* until n is within the valid range.
*/
n = (SAB_BASE_BAUD * 10) / baud;
m = 0;
while (n >= 640) {
n = n / 2;
m++;
}
n = (n+5) / 10;
/*
* We try very hard to avoid speeds with M == 0 since they may
* not work correctly for XTAL frequences above 10 MHz.
*/
if ((m == 0) && ((n & 1) == 0)) {
n = n / 2;
m++;
}
*n_ret = n - 1;
*m_ret = m;
}
/* Internal routine, port->lock is held and local interrupts are disabled. */
static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
unsigned int iflag, unsigned int baud,
unsigned int quot)
{
unsigned char dafo;
int n, m;
/* Byte size and parity */
switch (cflag & CSIZE) {
case CS5: dafo = SAB82532_DAFO_CHL5; break;
case CS6: dafo = SAB82532_DAFO_CHL6; break;
case CS7: dafo = SAB82532_DAFO_CHL7; break;
case CS8: dafo = SAB82532_DAFO_CHL8; break;
/* Never happens, but GCC is too dumb to figure it out */
default: dafo = SAB82532_DAFO_CHL5; break;
}
if (cflag & CSTOPB)
dafo |= SAB82532_DAFO_STOP;
if (cflag & PARENB)
dafo |= SAB82532_DAFO_PARE;
if (cflag & PARODD) {
dafo |= SAB82532_DAFO_PAR_ODD;
} else {
dafo |= SAB82532_DAFO_PAR_EVEN;
}
up->cached_dafo = dafo;
calc_ebrg(baud, &n, &m);
up->cached_ebrg = n | (m << 6);
up->tec_timeout = (10 * 1000000) / baud;
up->cec_timeout = up->tec_timeout >> 2;
/* CTS flow control flags */
/* We encode read_status_mask and ignore_status_mask like so:
*
* ---------------------
* | ... | ISR1 | ISR0 |
* ---------------------
* .. 15 8 7 0
*/
up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
SAB82532_ISR0_CDSC);
up->port.read_status_mask |= (SAB82532_ISR1_CSC |
SAB82532_ISR1_ALLS |
SAB82532_ISR1_XPR) << 8;
if (iflag & INPCK)
up->port.read_status_mask |= (SAB82532_ISR0_PERR |
SAB82532_ISR0_FERR);
if (iflag & (IGNBRK | BRKINT | PARMRK))
up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
/*
* Characteres to ignore
*/
up->port.ignore_status_mask = 0;
if (iflag & IGNPAR)
up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
SAB82532_ISR0_FERR);
if (iflag & IGNBRK) {
up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (iflag & IGNPAR)
up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
}
/*
* ignore all characters if CREAD is not set
*/
if ((cflag & CREAD) == 0)
up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
SAB82532_ISR0_TCD);
uart_update_timeout(&up->port, cflag,
(up->port.uartclk / (16 * quot)));
/* Now schedule a register update when the chip's
* transmitter is idle.
*/
up->cached_mode |= SAB82532_MODE_RAC;
set_bit(SAB82532_REGS_PENDING, &up->irqflags);
if (test_bit(SAB82532_XPR, &up->irqflags))
sunsab_tx_idle(up);
}
/* port->lock is not held. */
static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
unsigned long flags;
unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
unsigned int quot = uart_get_divisor(port, baud);
spin_lock_irqsave(&up->port.lock, flags);
sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static const char *sunsab_type(struct uart_port *port)
{
struct uart_sunsab_port *up = (void *)port;
static char buf[36];
sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
return buf;
}
static void sunsab_release_port(struct uart_port *port)
{
}
static int sunsab_request_port(struct uart_port *port)
{
return 0;
}
static void sunsab_config_port(struct uart_port *port, int flags)
{
}
static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
{
return -EINVAL;
}
static const struct uart_ops sunsab_pops = {
.tx_empty = sunsab_tx_empty,
.set_mctrl = sunsab_set_mctrl,
.get_mctrl = sunsab_get_mctrl,
.stop_tx = sunsab_stop_tx,
.start_tx = sunsab_start_tx,
.send_xchar = sunsab_send_xchar,
.stop_rx = sunsab_stop_rx,
.break_ctl = sunsab_break_ctl,
.startup = sunsab_startup,
.shutdown = sunsab_shutdown,
.set_termios = sunsab_set_termios,
.type = sunsab_type,
.release_port = sunsab_release_port,
.request_port = sunsab_request_port,
.config_port = sunsab_config_port,
.verify_port = sunsab_verify_port,
};
static struct uart_driver sunsab_reg = {
.owner = THIS_MODULE,
.driver_name = "sunsab",
.dev_name = "ttyS",
.major = TTY_MAJOR,
};
static struct uart_sunsab_port *sunsab_ports;
#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
static void sunsab_console_putchar(struct uart_port *port, unsigned char c)
{
struct uart_sunsab_port *up =
container_of(port, struct uart_sunsab_port, port);
sunsab_tec_wait(up);
writeb(c, &up->regs->w.tic);
}
static void sunsab_console_write(struct console *con, const char *s, unsigned n)
{
struct uart_sunsab_port *up = &sunsab_ports[con->index];
unsigned long flags;
int locked = 1;
if (up->port.sysrq || oops_in_progress)
locked = spin_trylock_irqsave(&up->port.lock, flags);
else
spin_lock_irqsave(&up->port.lock, flags);
uart_console_write(&up->port, s, n, sunsab_console_putchar);
sunsab_tec_wait(up);
if (locked)
spin_unlock_irqrestore(&up->port.lock, flags);
}
static int sunsab_console_setup(struct console *con, char *options)
{
struct uart_sunsab_port *up = &sunsab_ports[con->index];
unsigned long flags;
unsigned int baud, quot;
/*
* The console framework calls us for each and every port
* registered. Defer the console setup until the requested
* port has been properly discovered. A bit of a hack,
* though...
*/
if (up->port.type != PORT_SUNSAB)
return -EINVAL;
printk("Console: ttyS%d (SAB82532)\n",
(sunsab_reg.minor - 64) + con->index);
sunserial_console_termios(con, up->port.dev->of_node);
switch (con->cflag & CBAUD) {
case B150: baud = 150; break;
case B300: baud = 300; break;
case B600: baud = 600; break;
case B1200: baud = 1200; break;
case B2400: baud = 2400; break;
case B4800: baud = 4800; break;
default: case B9600: baud = 9600; break;
case B19200: baud = 19200; break;
case B38400: baud = 38400; break;
case B57600: baud = 57600; break;
case B115200: baud = 115200; break;
case B230400: baud = 230400; break;
case B460800: baud = 460800; break;
}
/*
* Temporary fix.
*/
spin_lock_init(&up->port.lock);
/*
* Initialize the hardware
*/
sunsab_startup(&up->port);
spin_lock_irqsave(&up->port.lock, flags);
/*
* Finally, enable interrupts
*/
up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
writeb(up->interrupt_mask0, &up->regs->w.imr0);
up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
SAB82532_IMR1_XPR;
writeb(up->interrupt_mask1, &up->regs->w.imr1);
quot = uart_get_divisor(&up->port, baud);
sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
spin_unlock_irqrestore(&up->port.lock, flags);
return 0;
}
static struct console sunsab_console = {
.name = "ttyS",
.write = sunsab_console_write,
.device = uart_console_device,
.setup = sunsab_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &sunsab_reg,
};
static inline struct console *SUNSAB_CONSOLE(void)
{
return &sunsab_console;
}
#else
#define SUNSAB_CONSOLE() (NULL)
#define sunsab_console_init() do { } while (0)
#endif
static int sunsab_init_one(struct uart_sunsab_port *up,
struct platform_device *op,
unsigned long offset,
int line)
{
up->port.line = line;
up->port.dev = &op->dev;
up->port.mapbase = op->resource[0].start + offset;
up->port.membase = of_ioremap(&op->resource[0], offset,
sizeof(union sab82532_async_regs),
"sab");
if (!up->port.membase)
return -ENOMEM;
up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
up->port.irq = op->archdata.irqs[0];
up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
up->port.iotype = UPIO_MEM;
up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);
writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
up->port.ops = &sunsab_pops;
up->port.type = PORT_SUNSAB;
up->port.uartclk = SAB_BASE_BAUD;
up->type = readb(&up->regs->r.vstr) & 0x0f;
writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
writeb(0xff, &up->regs->w.pim);
if ((up->port.line & 0x1) == 0) {
up->pvr_dsr_bit = (1 << 0);
up->pvr_dtr_bit = (1 << 1);
up->gis_shift = 2;
} else {
up->pvr_dsr_bit = (1 << 3);
up->pvr_dtr_bit = (1 << 2);
up->gis_shift = 0;
}
up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
writeb(up->cached_pvr, &up->regs->w.pvr);
up->cached_mode = readb(&up->regs->rw.mode);
up->cached_mode |= SAB82532_MODE_FRTS;
writeb(up->cached_mode, &up->regs->rw.mode);
up->cached_mode |= SAB82532_MODE_RTS;
writeb(up->cached_mode, &up->regs->rw.mode);
up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
return 0;
}
static int sab_probe(struct platform_device *op)
{
static int inst;
struct uart_sunsab_port *up;
int err;
up = &sunsab_ports[inst * 2];
err = sunsab_init_one(&up[0], op,
0,
(inst * 2) + 0);
if (err)
goto out;
err = sunsab_init_one(&up[1], op,
sizeof(union sab82532_async_regs),
(inst * 2) + 1);
if (err)
goto out1;
sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
&sunsab_reg, up[0].port.line,
false);
sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
&sunsab_reg, up[1].port.line,
false);
err = uart_add_one_port(&sunsab_reg, &up[0].port);
if (err)
goto out2;
err = uart_add_one_port(&sunsab_reg, &up[1].port);
if (err)
goto out3;
platform_set_drvdata(op, &up[0]);
inst++;
return 0;
out3:
uart_remove_one_port(&sunsab_reg, &up[0].port);
out2:
of_iounmap(&op->resource[0],
up[1].port.membase,
sizeof(union sab82532_async_regs));
out1:
of_iounmap(&op->resource[0],
up[0].port.membase,
sizeof(union sab82532_async_regs));
out:
return err;
}
static int sab_remove(struct platform_device *op)
{
struct uart_sunsab_port *up = platform_get_drvdata(op);
uart_remove_one_port(&sunsab_reg, &up[1].port);
uart_remove_one_port(&sunsab_reg, &up[0].port);
of_iounmap(&op->resource[0],
up[1].port.membase,
sizeof(union sab82532_async_regs));
of_iounmap(&op->resource[0],
up[0].port.membase,
sizeof(union sab82532_async_regs));
return 0;
}
static const struct of_device_id sab_match[] = {
{
.name = "se",
},
{
.name = "serial",
.compatible = "sab82532",
},
{},
};
MODULE_DEVICE_TABLE(of, sab_match);
static struct platform_driver sab_driver = {
.driver = {
.name = "sab",
.of_match_table = sab_match,
},
.probe = sab_probe,
.remove = sab_remove,
};
static int __init sunsab_init(void)
{
struct device_node *dp;
int err;
int num_channels = 0;
for_each_node_by_name(dp, "se")
num_channels += 2;
for_each_node_by_name(dp, "serial") {
if (of_device_is_compatible(dp, "sab82532"))
num_channels += 2;
}
if (num_channels) {
sunsab_ports = kcalloc(num_channels,
sizeof(struct uart_sunsab_port),
GFP_KERNEL);
if (!sunsab_ports)
return -ENOMEM;
err = sunserial_register_minors(&sunsab_reg, num_channels);
if (err) {
kfree(sunsab_ports);
sunsab_ports = NULL;
return err;
}
}
err = platform_driver_register(&sab_driver);
if (err) {
kfree(sunsab_ports);
sunsab_ports = NULL;
}
return err;
}
static void __exit sunsab_exit(void)
{
platform_driver_unregister(&sab_driver);
if (sunsab_reg.nr) {
sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
}
kfree(sunsab_ports);
sunsab_ports = NULL;
}
module_init(sunsab_init);
module_exit(sunsab_exit);
MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/sunsab.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for Atmel AT91 Serial ports
* Copyright (C) 2003 Rick Bronson
*
* Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* DMA support added by Chip Coldwell.
*/
#include <linux/circ_buf.h>
#include <linux/tty.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/tty_flip.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/atmel_pdc.h>
#include <linux/uaccess.h>
#include <linux/platform_data/atmel.h>
#include <linux/timer.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/suspend.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/div64.h>
#include <asm/ioctls.h>
#define PDC_BUFFER_SIZE 512
/* Revisit: We should calculate this based on the actual port settings */
#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
/* The minium number of data FIFOs should be able to contain */
#define ATMEL_MIN_FIFO_SIZE 8
/*
* These two offsets are substracted from the RX FIFO size to define the RTS
* high and low thresholds
*/
#define ATMEL_RTS_HIGH_OFFSET 16
#define ATMEL_RTS_LOW_OFFSET 20
#include <linux/serial_core.h>
#include "serial_mctrl_gpio.h"
#include "atmel_serial.h"
static void atmel_start_rx(struct uart_port *port);
static void atmel_stop_rx(struct uart_port *port);
#ifdef CONFIG_SERIAL_ATMEL_TTYAT
/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
* should coexist with the 8250 driver, such as if we have an external 16C550
* UART. */
#define SERIAL_ATMEL_MAJOR 204
#define MINOR_START 154
#define ATMEL_DEVICENAME "ttyAT"
#else
/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
* name, but it is legally reserved for the 8250 driver. */
#define SERIAL_ATMEL_MAJOR TTY_MAJOR
#define MINOR_START 64
#define ATMEL_DEVICENAME "ttyS"
#endif
#define ATMEL_ISR_PASS_LIMIT 256
struct atmel_dma_buffer {
unsigned char *buf;
dma_addr_t dma_addr;
unsigned int dma_size;
unsigned int ofs;
};
struct atmel_uart_char {
u16 status;
u16 ch;
};
/*
* Be careful, the real size of the ring buffer is
* sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
* can contain up to 1024 characters in PIO mode and up to 4096 characters in
* DMA mode.
*/
#define ATMEL_SERIAL_RINGSIZE 1024
/*
* at91: 6 USARTs and one DBGU port (SAM9260)
* samx7: 3 USARTs and 5 UARTs
*/
#define ATMEL_MAX_UART 8
/*
* We wrap our port structure around the generic uart_port.
*/
struct atmel_uart_port {
struct uart_port uart; /* uart */
struct clk *clk; /* uart clock */
struct clk *gclk; /* uart generic clock */
int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
u32 backup_imr; /* IMR saved during suspend */
int break_active; /* break being received */
bool use_dma_rx; /* enable DMA receiver */
bool use_pdc_rx; /* enable PDC receiver */
short pdc_rx_idx; /* current PDC RX buffer */
struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
bool use_dma_tx; /* enable DMA transmitter */
bool use_pdc_tx; /* enable PDC transmitter */
struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
spinlock_t lock_tx; /* port lock */
spinlock_t lock_rx; /* port lock */
struct dma_chan *chan_tx;
struct dma_chan *chan_rx;
struct dma_async_tx_descriptor *desc_tx;
struct dma_async_tx_descriptor *desc_rx;
dma_cookie_t cookie_tx;
dma_cookie_t cookie_rx;
struct scatterlist sg_tx;
struct scatterlist sg_rx;
struct tasklet_struct tasklet_rx;
struct tasklet_struct tasklet_tx;
atomic_t tasklet_shutdown;
unsigned int irq_status_prev;
unsigned int tx_len;
struct circ_buf rx_ring;
struct mctrl_gpios *gpios;
u32 backup_mode; /* MR saved during iso7816 operations */
u32 backup_brgr; /* BRGR saved during iso7816 operations */
unsigned int tx_done_mask;
u32 fifo_size;
u32 rts_high;
u32 rts_low;
bool ms_irq_enabled;
u32 rtor; /* address of receiver timeout register if it exists */
bool is_usart;
bool has_frac_baudrate;
bool has_hw_timer;
struct timer_list uart_timer;
bool tx_stopped;
bool suspended;
unsigned int pending;
unsigned int pending_status;
spinlock_t lock_suspended;
bool hd_start_rx; /* can start RX during half-duplex operation */
/* ISO7816 */
unsigned int fidi_min;
unsigned int fidi_max;
struct {
u32 cr;
u32 mr;
u32 imr;
u32 brgr;
u32 rtor;
u32 ttgr;
u32 fmr;
u32 fimr;
} cache;
int (*prepare_rx)(struct uart_port *port);
int (*prepare_tx)(struct uart_port *port);
void (*schedule_rx)(struct uart_port *port);
void (*schedule_tx)(struct uart_port *port);
void (*release_rx)(struct uart_port *port);
void (*release_tx)(struct uart_port *port);
};
static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
#if defined(CONFIG_OF)
static const struct of_device_id atmel_serial_dt_ids[] = {
{ .compatible = "atmel,at91rm9200-usart-serial" },
{ /* sentinel */ }
};
#endif
static inline struct atmel_uart_port *
to_atmel_uart_port(struct uart_port *uart)
{
return container_of(uart, struct atmel_uart_port, uart);
}
static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
{
return __raw_readl(port->membase + reg);
}
static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
{
__raw_writel(value, port->membase + reg);
}
static inline u8 atmel_uart_read_char(struct uart_port *port)
{
return __raw_readb(port->membase + ATMEL_US_RHR);
}
static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
{
__raw_writeb(value, port->membase + ATMEL_US_THR);
}
static inline int atmel_uart_is_half_duplex(struct uart_port *port)
{
return ((port->rs485.flags & SER_RS485_ENABLED) &&
!(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
(port->iso7816.flags & SER_ISO7816_ENABLED);
}
static inline int atmel_error_rate(int desired_value, int actual_value)
{
return 100 - (desired_value * 100) / actual_value;
}
#ifdef CONFIG_SERIAL_ATMEL_PDC
static bool atmel_use_pdc_rx(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
return atmel_port->use_pdc_rx;
}
static bool atmel_use_pdc_tx(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
return atmel_port->use_pdc_tx;
}
#else
static bool atmel_use_pdc_rx(struct uart_port *port)
{
return false;
}
static bool atmel_use_pdc_tx(struct uart_port *port)
{
return false;
}
#endif
static bool atmel_use_dma_tx(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
return atmel_port->use_dma_tx;
}
static bool atmel_use_dma_rx(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
return atmel_port->use_dma_rx;
}
static bool atmel_use_fifo(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
return atmel_port->fifo_size;
}
static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
struct tasklet_struct *t)
{
if (!atomic_read(&atmel_port->tasklet_shutdown))
tasklet_schedule(t);
}
/* Enable or disable the rs485 support */
static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485conf)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int mode;
/* Disable interrupts */
atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
mode = atmel_uart_readl(port, ATMEL_US_MR);
if (rs485conf->flags & SER_RS485_ENABLED) {
dev_dbg(port->dev, "Setting UART to RS485\n");
if (rs485conf->flags & SER_RS485_RX_DURING_TX)
atmel_port->tx_done_mask = ATMEL_US_TXRDY;
else
atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
atmel_uart_writel(port, ATMEL_US_TTGR,
rs485conf->delay_rts_after_send);
mode &= ~ATMEL_US_USMODE;
mode |= ATMEL_US_USMODE_RS485;
} else {
dev_dbg(port->dev, "Setting UART to RS232\n");
if (atmel_use_pdc_tx(port))
atmel_port->tx_done_mask = ATMEL_US_ENDTX |
ATMEL_US_TXBUFE;
else
atmel_port->tx_done_mask = ATMEL_US_TXRDY;
}
atmel_uart_writel(port, ATMEL_US_MR, mode);
/* Enable interrupts */
atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
return 0;
}
static unsigned int atmel_calc_cd(struct uart_port *port,
struct serial_iso7816 *iso7816conf)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int cd;
u64 mck_rate;
mck_rate = (u64)clk_get_rate(atmel_port->clk);
do_div(mck_rate, iso7816conf->clk);
cd = mck_rate;
return cd;
}
static unsigned int atmel_calc_fidi(struct uart_port *port,
struct serial_iso7816 *iso7816conf)
{
u64 fidi = 0;
if (iso7816conf->sc_fi && iso7816conf->sc_di) {
fidi = (u64)iso7816conf->sc_fi;
do_div(fidi, iso7816conf->sc_di);
}
return (u32)fidi;
}
/* Enable or disable the iso7816 support */
/* Called with interrupts disabled */
static int atmel_config_iso7816(struct uart_port *port,
struct serial_iso7816 *iso7816conf)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int mode;
unsigned int cd, fidi;
int ret = 0;
/* Disable interrupts */
atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
mode = atmel_uart_readl(port, ATMEL_US_MR);
if (iso7816conf->flags & SER_ISO7816_ENABLED) {
mode &= ~ATMEL_US_USMODE;
if (iso7816conf->tg > 255) {
dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
memset(iso7816conf, 0, sizeof(struct serial_iso7816));
ret = -EINVAL;
goto err_out;
}
if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
== SER_ISO7816_T(0)) {
mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
} else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
== SER_ISO7816_T(1)) {
mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
} else {
dev_err(port->dev, "ISO7816: Type not supported\n");
memset(iso7816conf, 0, sizeof(struct serial_iso7816));
ret = -EINVAL;
goto err_out;
}
mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
/* select mck clock, and output */
mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
/* set parity for normal/inverse mode + max iterations */
mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
cd = atmel_calc_cd(port, iso7816conf);
fidi = atmel_calc_fidi(port, iso7816conf);
if (fidi == 0) {
dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
} else if (fidi < atmel_port->fidi_min
|| fidi > atmel_port->fidi_max) {
dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
memset(iso7816conf, 0, sizeof(struct serial_iso7816));
ret = -EINVAL;
goto err_out;
}
if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
/* port not yet in iso7816 mode: store configuration */
atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
}
atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
atmel_uart_writel(port, ATMEL_US_BRGR, cd);
atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
} else {
dev_dbg(port->dev, "Setting UART back to RS232\n");
/* back to last RS232 settings */
mode = atmel_port->backup_mode;
memset(iso7816conf, 0, sizeof(struct serial_iso7816));
atmel_uart_writel(port, ATMEL_US_TTGR, 0);
atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
if (atmel_use_pdc_tx(port))
atmel_port->tx_done_mask = ATMEL_US_ENDTX |
ATMEL_US_TXBUFE;
else
atmel_port->tx_done_mask = ATMEL_US_TXRDY;
}
port->iso7816 = *iso7816conf;
atmel_uart_writel(port, ATMEL_US_MR, mode);
err_out:
/* Enable interrupts */
atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
return ret;
}
/*
* Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
*/
static u_int atmel_tx_empty(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (atmel_port->tx_stopped)
return TIOCSER_TEMT;
return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
TIOCSER_TEMT :
0;
}
/*
* Set state of the modem control output lines
*/
static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
{
unsigned int control = 0;
unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
unsigned int rts_paused, rts_ready;
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
/* override mode to RS485 if needed, otherwise keep the current mode */
if (port->rs485.flags & SER_RS485_ENABLED) {
atmel_uart_writel(port, ATMEL_US_TTGR,
port->rs485.delay_rts_after_send);
mode &= ~ATMEL_US_USMODE;
mode |= ATMEL_US_USMODE_RS485;
}
/* set the RTS line state according to the mode */
if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
/* force RTS line to high level */
rts_paused = ATMEL_US_RTSEN;
/* give the control of the RTS line back to the hardware */
rts_ready = ATMEL_US_RTSDIS;
} else {
/* force RTS line to high level */
rts_paused = ATMEL_US_RTSDIS;
/* force RTS line to low level */
rts_ready = ATMEL_US_RTSEN;
}
if (mctrl & TIOCM_RTS)
control |= rts_ready;
else
control |= rts_paused;
if (mctrl & TIOCM_DTR)
control |= ATMEL_US_DTREN;
else
control |= ATMEL_US_DTRDIS;
atmel_uart_writel(port, ATMEL_US_CR, control);
mctrl_gpio_set(atmel_port->gpios, mctrl);
/* Local loopback mode? */
mode &= ~ATMEL_US_CHMODE;
if (mctrl & TIOCM_LOOP)
mode |= ATMEL_US_CHMODE_LOC_LOOP;
else
mode |= ATMEL_US_CHMODE_NORMAL;
atmel_uart_writel(port, ATMEL_US_MR, mode);
}
/*
* Get state of the modem control input lines
*/
static u_int atmel_get_mctrl(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int ret = 0, status;
status = atmel_uart_readl(port, ATMEL_US_CSR);
/*
* The control signals are active low.
*/
if (!(status & ATMEL_US_DCD))
ret |= TIOCM_CD;
if (!(status & ATMEL_US_CTS))
ret |= TIOCM_CTS;
if (!(status & ATMEL_US_DSR))
ret |= TIOCM_DSR;
if (!(status & ATMEL_US_RI))
ret |= TIOCM_RI;
return mctrl_gpio_get(atmel_port->gpios, &ret);
}
/*
* Stop transmitting.
*/
static void atmel_stop_tx(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
bool is_pdc = atmel_use_pdc_tx(port);
bool is_dma = is_pdc || atmel_use_dma_tx(port);
if (is_pdc) {
/* disable PDC transmit */
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
}
if (is_dma) {
/*
* Disable the transmitter.
* This is mandatory when DMA is used, otherwise the DMA buffer
* is fully transmitted.
*/
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
atmel_port->tx_stopped = true;
}
/* Disable interrupts */
atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
if (atmel_uart_is_half_duplex(port))
if (!atomic_read(&atmel_port->tasklet_shutdown))
atmel_start_rx(port);
}
/*
* Start transmitting.
*/
static void atmel_start_tx(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
bool is_pdc = atmel_use_pdc_tx(port);
bool is_dma = is_pdc || atmel_use_dma_tx(port);
if (is_pdc && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
& ATMEL_PDC_TXTEN))
/* The transmitter is already running. Yes, we
really need this.*/
return;
if (is_dma && atmel_uart_is_half_duplex(port))
atmel_stop_rx(port);
if (is_pdc) {
/* re-enable PDC transmit */
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
}
/* Enable interrupts */
atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
if (is_dma) {
/* re-enable the transmitter */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
atmel_port->tx_stopped = false;
}
}
/*
* start receiving - port is in process of being opened.
*/
static void atmel_start_rx(struct uart_port *port)
{
/* reset status and receiver */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
if (atmel_use_pdc_rx(port)) {
/* enable PDC controller */
atmel_uart_writel(port, ATMEL_US_IER,
ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
port->read_status_mask);
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
} else {
atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
}
}
/*
* Stop receiving - port is in process of being closed.
*/
static void atmel_stop_rx(struct uart_port *port)
{
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
if (atmel_use_pdc_rx(port)) {
/* disable PDC receive */
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
atmel_uart_writel(port, ATMEL_US_IDR,
ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
port->read_status_mask);
} else {
atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
}
}
/*
* Enable modem status interrupts
*/
static void atmel_enable_ms(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
uint32_t ier = 0;
/*
* Interrupt should not be enabled twice
*/
if (atmel_port->ms_irq_enabled)
return;
atmel_port->ms_irq_enabled = true;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ier |= ATMEL_US_CTSIC;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ier |= ATMEL_US_DSRIC;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ier |= ATMEL_US_RIIC;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ier |= ATMEL_US_DCDIC;
atmel_uart_writel(port, ATMEL_US_IER, ier);
mctrl_gpio_enable_ms(atmel_port->gpios);
}
/*
* Disable modem status interrupts
*/
static void atmel_disable_ms(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
uint32_t idr = 0;
/*
* Interrupt should not be disabled twice
*/
if (!atmel_port->ms_irq_enabled)
return;
atmel_port->ms_irq_enabled = false;
mctrl_gpio_disable_ms(atmel_port->gpios);
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
idr |= ATMEL_US_CTSIC;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
idr |= ATMEL_US_DSRIC;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
idr |= ATMEL_US_RIIC;
if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
idr |= ATMEL_US_DCDIC;
atmel_uart_writel(port, ATMEL_US_IDR, idr);
}
/*
* Control the transmission of a break signal
*/
static void atmel_break_ctl(struct uart_port *port, int break_state)
{
if (break_state != 0)
/* start break */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
else
/* stop break */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
}
/*
* Stores the incoming character in the ring buffer
*/
static void
atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
unsigned int ch)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct circ_buf *ring = &atmel_port->rx_ring;
struct atmel_uart_char *c;
if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
/* Buffer overflow, ignore char */
return;
c = &((struct atmel_uart_char *)ring->buf)[ring->head];
c->status = status;
c->ch = ch;
/* Make sure the character is stored before we update head. */
smp_wmb();
ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
}
/*
* Deal with parity, framing and overrun errors.
*/
static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
{
/* clear error */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
if (status & ATMEL_US_RXBRK) {
/* ignore side-effect */
status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
port->icount.brk++;
}
if (status & ATMEL_US_PARE)
port->icount.parity++;
if (status & ATMEL_US_FRAME)
port->icount.frame++;
if (status & ATMEL_US_OVRE)
port->icount.overrun++;
}
/*
* Characters received (called from interrupt handler)
*/
static void atmel_rx_chars(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int status, ch;
status = atmel_uart_readl(port, ATMEL_US_CSR);
while (status & ATMEL_US_RXRDY) {
ch = atmel_uart_read_char(port);
/*
* note that the error handling code is
* out of the main execution path
*/
if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
| ATMEL_US_OVRE | ATMEL_US_RXBRK)
|| atmel_port->break_active)) {
/* clear error */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
if (status & ATMEL_US_RXBRK
&& !atmel_port->break_active) {
atmel_port->break_active = 1;
atmel_uart_writel(port, ATMEL_US_IER,
ATMEL_US_RXBRK);
} else {
/*
* This is either the end-of-break
* condition or we've received at
* least one character without RXBRK
* being set. In both cases, the next
* RXBRK will indicate start-of-break.
*/
atmel_uart_writel(port, ATMEL_US_IDR,
ATMEL_US_RXBRK);
status &= ~ATMEL_US_RXBRK;
atmel_port->break_active = 0;
}
}
atmel_buffer_rx_char(port, status, ch);
status = atmel_uart_readl(port, ATMEL_US_CSR);
}
atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
}
/*
* Transmit characters (called from tasklet with TXRDY interrupt
* disabled)
*/
static void atmel_tx_chars(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
bool pending;
u8 ch;
pending = uart_port_tx(port, ch,
atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY,
atmel_uart_write_char(port, ch));
if (pending) {
/* we still have characters to transmit, so we should continue
* transmitting them when TX is ready, regardless of
* mode or duplexity
*/
atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
/* Enable interrupts */
atmel_uart_writel(port, ATMEL_US_IER,
atmel_port->tx_done_mask);
} else {
if (atmel_uart_is_half_duplex(port))
atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
}
}
static void atmel_complete_tx_dma(void *arg)
{
struct atmel_uart_port *atmel_port = arg;
struct uart_port *port = &atmel_port->uart;
struct circ_buf *xmit = &port->state->xmit;
struct dma_chan *chan = atmel_port->chan_tx;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
if (chan)
dmaengine_terminate_all(chan);
uart_xmit_advance(port, atmel_port->tx_len);
spin_lock(&atmel_port->lock_tx);
async_tx_ack(atmel_port->desc_tx);
atmel_port->cookie_tx = -EINVAL;
atmel_port->desc_tx = NULL;
spin_unlock(&atmel_port->lock_tx);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
/*
* xmit is a circular buffer so, if we have just send data from
* xmit->tail to the end of xmit->buf, now we have to transmit the
* remaining data from the beginning of xmit->buf to xmit->head.
*/
if (!uart_circ_empty(xmit))
atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
else if (atmel_uart_is_half_duplex(port)) {
/*
* DMA done, re-enable TXEMPTY and signal that we can stop
* TX and start RX for RS485
*/
atmel_port->hd_start_rx = true;
atmel_uart_writel(port, ATMEL_US_IER,
atmel_port->tx_done_mask);
}
spin_unlock_irqrestore(&port->lock, flags);
}
static void atmel_release_tx_dma(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct dma_chan *chan = atmel_port->chan_tx;
if (chan) {
dmaengine_terminate_all(chan);
dma_release_channel(chan);
dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
DMA_TO_DEVICE);
}
atmel_port->desc_tx = NULL;
atmel_port->chan_tx = NULL;
atmel_port->cookie_tx = -EINVAL;
}
/*
* Called from tasklet with TXRDY interrupt is disabled.
*/
static void atmel_tx_dma(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct circ_buf *xmit = &port->state->xmit;
struct dma_chan *chan = atmel_port->chan_tx;
struct dma_async_tx_descriptor *desc;
struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
unsigned int tx_len, part1_len, part2_len, sg_len;
dma_addr_t phys_addr;
/* Make sure we have an idle channel */
if (atmel_port->desc_tx != NULL)
return;
if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
/*
* DMA is idle now.
* Port xmit buffer is already mapped,
* and it is one page... Just adjust
* offsets and lengths. Since it is a circular buffer,
* we have to transmit till the end, and then the rest.
* Take the port lock to get a
* consistent xmit buffer state.
*/
tx_len = CIRC_CNT_TO_END(xmit->head,
xmit->tail,
UART_XMIT_SIZE);
if (atmel_port->fifo_size) {
/* multi data mode */
part1_len = (tx_len & ~0x3); /* DWORD access */
part2_len = (tx_len & 0x3); /* BYTE access */
} else {
/* single data (legacy) mode */
part1_len = 0;
part2_len = tx_len; /* BYTE access only */
}
sg_init_table(sgl, 2);
sg_len = 0;
phys_addr = sg_dma_address(sg_tx) + xmit->tail;
if (part1_len) {
sg = &sgl[sg_len++];
sg_dma_address(sg) = phys_addr;
sg_dma_len(sg) = part1_len;
phys_addr += part1_len;
}
if (part2_len) {
sg = &sgl[sg_len++];
sg_dma_address(sg) = phys_addr;
sg_dma_len(sg) = part2_len;
}
/*
* save tx_len so atmel_complete_tx_dma() will increase
* xmit->tail correctly
*/
atmel_port->tx_len = tx_len;
desc = dmaengine_prep_slave_sg(chan,
sgl,
sg_len,
DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT |
DMA_CTRL_ACK);
if (!desc) {
dev_err(port->dev, "Failed to send via dma!\n");
return;
}
dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
atmel_port->desc_tx = desc;
desc->callback = atmel_complete_tx_dma;
desc->callback_param = atmel_port;
atmel_port->cookie_tx = dmaengine_submit(desc);
if (dma_submit_error(atmel_port->cookie_tx)) {
dev_err(port->dev, "dma_submit_error %d\n",
atmel_port->cookie_tx);
return;
}
dma_async_issue_pending(chan);
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static int atmel_prepare_tx_dma(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct device *mfd_dev = port->dev->parent;
dma_cap_mask_t mask;
struct dma_slave_config config;
int ret, nent;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
if (atmel_port->chan_tx == NULL)
goto chan_err;
dev_info(port->dev, "using %s for tx DMA transfers\n",
dma_chan_name(atmel_port->chan_tx));
spin_lock_init(&atmel_port->lock_tx);
sg_init_table(&atmel_port->sg_tx, 1);
/* UART circular tx buffer is an aligned page. */
BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
sg_set_page(&atmel_port->sg_tx,
virt_to_page(port->state->xmit.buf),
UART_XMIT_SIZE,
offset_in_page(port->state->xmit.buf));
nent = dma_map_sg(port->dev,
&atmel_port->sg_tx,
1,
DMA_TO_DEVICE);
if (!nent) {
dev_dbg(port->dev, "need to release resource of dma\n");
goto chan_err;
} else {
dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
sg_dma_len(&atmel_port->sg_tx),
port->state->xmit.buf,
&sg_dma_address(&atmel_port->sg_tx));
}
/* Configure the slave DMA */
memset(&config, 0, sizeof(config));
config.direction = DMA_MEM_TO_DEV;
config.dst_addr_width = (atmel_port->fifo_size) ?
DMA_SLAVE_BUSWIDTH_4_BYTES :
DMA_SLAVE_BUSWIDTH_1_BYTE;
config.dst_addr = port->mapbase + ATMEL_US_THR;
config.dst_maxburst = 1;
ret = dmaengine_slave_config(atmel_port->chan_tx,
&config);
if (ret) {
dev_err(port->dev, "DMA tx slave configuration failed\n");
goto chan_err;
}
return 0;
chan_err:
dev_err(port->dev, "TX channel not available, switch to pio\n");
atmel_port->use_dma_tx = false;
if (atmel_port->chan_tx)
atmel_release_tx_dma(port);
return -EINVAL;
}
static void atmel_complete_rx_dma(void *arg)
{
struct uart_port *port = arg;
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
}
static void atmel_release_rx_dma(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct dma_chan *chan = atmel_port->chan_rx;
if (chan) {
dmaengine_terminate_all(chan);
dma_release_channel(chan);
dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
DMA_FROM_DEVICE);
}
atmel_port->desc_rx = NULL;
atmel_port->chan_rx = NULL;
atmel_port->cookie_rx = -EINVAL;
}
static void atmel_rx_from_dma(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct tty_port *tport = &port->state->port;
struct circ_buf *ring = &atmel_port->rx_ring;
struct dma_chan *chan = atmel_port->chan_rx;
struct dma_tx_state state;
enum dma_status dmastat;
size_t count;
/* Reset the UART timeout early so that we don't miss one */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
dmastat = dmaengine_tx_status(chan,
atmel_port->cookie_rx,
&state);
/* Restart a new tasklet if DMA status is error */
if (dmastat == DMA_ERROR) {
dev_dbg(port->dev, "Get residue error, restart tasklet\n");
atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
return;
}
/* CPU claims ownership of RX DMA buffer */
dma_sync_sg_for_cpu(port->dev,
&atmel_port->sg_rx,
1,
DMA_FROM_DEVICE);
/*
* ring->head points to the end of data already written by the DMA.
* ring->tail points to the beginning of data to be read by the
* framework.
* The current transfer size should not be larger than the dma buffer
* length.
*/
ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
/*
* At this point ring->head may point to the first byte right after the
* last byte of the dma buffer:
* 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
*
* However ring->tail must always points inside the dma buffer:
* 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
*
* Since we use a ring buffer, we have to handle the case
* where head is lower than tail. In such a case, we first read from
* tail to the end of the buffer then reset tail.
*/
if (ring->head < ring->tail) {
count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
tty_insert_flip_string(tport, ring->buf + ring->tail, count);
ring->tail = 0;
port->icount.rx += count;
}
/* Finally we read data from tail to head */
if (ring->tail < ring->head) {
count = ring->head - ring->tail;
tty_insert_flip_string(tport, ring->buf + ring->tail, count);
/* Wrap ring->head if needed */
if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
ring->head = 0;
ring->tail = ring->head;
port->icount.rx += count;
}
/* USART retreives ownership of RX DMA buffer */
dma_sync_sg_for_device(port->dev,
&atmel_port->sg_rx,
1,
DMA_FROM_DEVICE);
tty_flip_buffer_push(tport);
atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
}
static int atmel_prepare_rx_dma(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct device *mfd_dev = port->dev->parent;
struct dma_async_tx_descriptor *desc;
dma_cap_mask_t mask;
struct dma_slave_config config;
struct circ_buf *ring;
int ret, nent;
ring = &atmel_port->rx_ring;
dma_cap_zero(mask);
dma_cap_set(DMA_CYCLIC, mask);
atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
if (atmel_port->chan_rx == NULL)
goto chan_err;
dev_info(port->dev, "using %s for rx DMA transfers\n",
dma_chan_name(atmel_port->chan_rx));
spin_lock_init(&atmel_port->lock_rx);
sg_init_table(&atmel_port->sg_rx, 1);
/* UART circular rx buffer is an aligned page. */
BUG_ON(!PAGE_ALIGNED(ring->buf));
sg_set_page(&atmel_port->sg_rx,
virt_to_page(ring->buf),
sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
offset_in_page(ring->buf));
nent = dma_map_sg(port->dev,
&atmel_port->sg_rx,
1,
DMA_FROM_DEVICE);
if (!nent) {
dev_dbg(port->dev, "need to release resource of dma\n");
goto chan_err;
} else {
dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
sg_dma_len(&atmel_port->sg_rx),
ring->buf,
&sg_dma_address(&atmel_port->sg_rx));
}
/* Configure the slave DMA */
memset(&config, 0, sizeof(config));
config.direction = DMA_DEV_TO_MEM;
config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
config.src_addr = port->mapbase + ATMEL_US_RHR;
config.src_maxburst = 1;
ret = dmaengine_slave_config(atmel_port->chan_rx,
&config);
if (ret) {
dev_err(port->dev, "DMA rx slave configuration failed\n");
goto chan_err;
}
/*
* Prepare a cyclic dma transfer, assign 2 descriptors,
* each one is half ring buffer size
*/
desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
sg_dma_address(&atmel_port->sg_rx),
sg_dma_len(&atmel_port->sg_rx),
sg_dma_len(&atmel_port->sg_rx)/2,
DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT);
if (!desc) {
dev_err(port->dev, "Preparing DMA cyclic failed\n");
goto chan_err;
}
desc->callback = atmel_complete_rx_dma;
desc->callback_param = port;
atmel_port->desc_rx = desc;
atmel_port->cookie_rx = dmaengine_submit(desc);
if (dma_submit_error(atmel_port->cookie_rx)) {
dev_err(port->dev, "dma_submit_error %d\n",
atmel_port->cookie_rx);
goto chan_err;
}
dma_async_issue_pending(atmel_port->chan_rx);
return 0;
chan_err:
dev_err(port->dev, "RX channel not available, switch to pio\n");
atmel_port->use_dma_rx = false;
if (atmel_port->chan_rx)
atmel_release_rx_dma(port);
return -EINVAL;
}
static void atmel_uart_timer_callback(struct timer_list *t)
{
struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
uart_timer);
struct uart_port *port = &atmel_port->uart;
if (!atomic_read(&atmel_port->tasklet_shutdown)) {
tasklet_schedule(&atmel_port->tasklet_rx);
mod_timer(&atmel_port->uart_timer,
jiffies + uart_poll_timeout(port));
}
}
/*
* receive interrupt handler.
*/
static void
atmel_handle_receive(struct uart_port *port, unsigned int pending)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (atmel_use_pdc_rx(port)) {
/*
* PDC receive. Just schedule the tasklet and let it
* figure out the details.
*
* TODO: We're not handling error flags correctly at
* the moment.
*/
if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
atmel_uart_writel(port, ATMEL_US_IDR,
(ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
atmel_tasklet_schedule(atmel_port,
&atmel_port->tasklet_rx);
}
if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
ATMEL_US_FRAME | ATMEL_US_PARE))
atmel_pdc_rxerr(port, pending);
}
if (atmel_use_dma_rx(port)) {
if (pending & ATMEL_US_TIMEOUT) {
atmel_uart_writel(port, ATMEL_US_IDR,
ATMEL_US_TIMEOUT);
atmel_tasklet_schedule(atmel_port,
&atmel_port->tasklet_rx);
}
}
/* Interrupt receive */
if (pending & ATMEL_US_RXRDY)
atmel_rx_chars(port);
else if (pending & ATMEL_US_RXBRK) {
/*
* End of break detected. If it came along with a
* character, atmel_rx_chars will handle it.
*/
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
atmel_port->break_active = 0;
}
}
/*
* transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
*/
static void
atmel_handle_transmit(struct uart_port *port, unsigned int pending)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (pending & atmel_port->tx_done_mask) {
atmel_uart_writel(port, ATMEL_US_IDR,
atmel_port->tx_done_mask);
/* Start RX if flag was set and FIFO is empty */
if (atmel_port->hd_start_rx) {
if (!(atmel_uart_readl(port, ATMEL_US_CSR)
& ATMEL_US_TXEMPTY))
dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
atmel_port->hd_start_rx = false;
atmel_start_rx(port);
}
atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
}
}
/*
* status flags interrupt handler.
*/
static void
atmel_handle_status(struct uart_port *port, unsigned int pending,
unsigned int status)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int status_change;
if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
| ATMEL_US_CTSIC)) {
status_change = status ^ atmel_port->irq_status_prev;
atmel_port->irq_status_prev = status;
if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
| ATMEL_US_DCD | ATMEL_US_CTS)) {
/* TODO: All reads to CSR will clear these interrupts! */
if (status_change & ATMEL_US_RI)
port->icount.rng++;
if (status_change & ATMEL_US_DSR)
port->icount.dsr++;
if (status_change & ATMEL_US_DCD)
uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
if (status_change & ATMEL_US_CTS)
uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
wake_up_interruptible(&port->state->port.delta_msr_wait);
}
}
if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
}
/*
* Interrupt handler
*/
static irqreturn_t atmel_interrupt(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int status, pending, mask, pass_counter = 0;
spin_lock(&atmel_port->lock_suspended);
do {
status = atmel_uart_readl(port, ATMEL_US_CSR);
mask = atmel_uart_readl(port, ATMEL_US_IMR);
pending = status & mask;
if (!pending)
break;
if (atmel_port->suspended) {
atmel_port->pending |= pending;
atmel_port->pending_status = status;
atmel_uart_writel(port, ATMEL_US_IDR, mask);
pm_system_wakeup();
break;
}
atmel_handle_receive(port, pending);
atmel_handle_status(port, pending, status);
atmel_handle_transmit(port, pending);
} while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
spin_unlock(&atmel_port->lock_suspended);
return pass_counter ? IRQ_HANDLED : IRQ_NONE;
}
static void atmel_release_tx_pdc(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
dma_unmap_single(port->dev,
pdc->dma_addr,
pdc->dma_size,
DMA_TO_DEVICE);
}
/*
* Called from tasklet with ENDTX and TXBUFE interrupts disabled.
*/
static void atmel_tx_pdc(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct circ_buf *xmit = &port->state->xmit;
struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
int count;
/* nothing left to transmit? */
if (atmel_uart_readl(port, ATMEL_PDC_TCR))
return;
uart_xmit_advance(port, pdc->ofs);
pdc->ofs = 0;
/* more to transmit - setup next transfer */
/* disable PDC transmit */
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
dma_sync_single_for_device(port->dev,
pdc->dma_addr,
pdc->dma_size,
DMA_TO_DEVICE);
count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
pdc->ofs = count;
atmel_uart_writel(port, ATMEL_PDC_TPR,
pdc->dma_addr + xmit->tail);
atmel_uart_writel(port, ATMEL_PDC_TCR, count);
/* re-enable PDC transmit */
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
/* Enable interrupts */
atmel_uart_writel(port, ATMEL_US_IER,
atmel_port->tx_done_mask);
} else {
if (atmel_uart_is_half_duplex(port)) {
/* DMA done, stop TX, start RX for RS485 */
atmel_start_rx(port);
}
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static int atmel_prepare_tx_pdc(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
struct circ_buf *xmit = &port->state->xmit;
pdc->buf = xmit->buf;
pdc->dma_addr = dma_map_single(port->dev,
pdc->buf,
UART_XMIT_SIZE,
DMA_TO_DEVICE);
pdc->dma_size = UART_XMIT_SIZE;
pdc->ofs = 0;
return 0;
}
static void atmel_rx_from_ring(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct circ_buf *ring = &atmel_port->rx_ring;
unsigned int status;
u8 flg;
while (ring->head != ring->tail) {
struct atmel_uart_char c;
/* Make sure c is loaded after head. */
smp_rmb();
c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
port->icount.rx++;
status = c.status;
flg = TTY_NORMAL;
/*
* note that the error handling code is
* out of the main execution path
*/
if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
| ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
if (status & ATMEL_US_RXBRK) {
/* ignore side-effect */
status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
port->icount.brk++;
if (uart_handle_break(port))
continue;
}
if (status & ATMEL_US_PARE)
port->icount.parity++;
if (status & ATMEL_US_FRAME)
port->icount.frame++;
if (status & ATMEL_US_OVRE)
port->icount.overrun++;
status &= port->read_status_mask;
if (status & ATMEL_US_RXBRK)
flg = TTY_BREAK;
else if (status & ATMEL_US_PARE)
flg = TTY_PARITY;
else if (status & ATMEL_US_FRAME)
flg = TTY_FRAME;
}
if (uart_handle_sysrq_char(port, c.ch))
continue;
uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
}
tty_flip_buffer_push(&port->state->port);
}
static void atmel_release_rx_pdc(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
int i;
for (i = 0; i < 2; i++) {
struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
dma_unmap_single(port->dev,
pdc->dma_addr,
pdc->dma_size,
DMA_FROM_DEVICE);
kfree(pdc->buf);
}
}
static void atmel_rx_from_pdc(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
struct tty_port *tport = &port->state->port;
struct atmel_dma_buffer *pdc;
int rx_idx = atmel_port->pdc_rx_idx;
unsigned int head;
unsigned int tail;
unsigned int count;
do {
/* Reset the UART timeout early so that we don't miss one */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
pdc = &atmel_port->pdc_rx[rx_idx];
head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
tail = pdc->ofs;
/* If the PDC has switched buffers, RPR won't contain
* any address within the current buffer. Since head
* is unsigned, we just need a one-way comparison to
* find out.
*
* In this case, we just need to consume the entire
* buffer and resubmit it for DMA. This will clear the
* ENDRX bit as well, so that we can safely re-enable
* all interrupts below.
*/
head = min(head, pdc->dma_size);
if (likely(head != tail)) {
dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
pdc->dma_size, DMA_FROM_DEVICE);
/*
* head will only wrap around when we recycle
* the DMA buffer, and when that happens, we
* explicitly set tail to 0. So head will
* always be greater than tail.
*/
count = head - tail;
tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
count);
dma_sync_single_for_device(port->dev, pdc->dma_addr,
pdc->dma_size, DMA_FROM_DEVICE);
port->icount.rx += count;
pdc->ofs = head;
}
/*
* If the current buffer is full, we need to check if
* the next one contains any additional data.
*/
if (head >= pdc->dma_size) {
pdc->ofs = 0;
atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
rx_idx = !rx_idx;
atmel_port->pdc_rx_idx = rx_idx;
}
} while (head >= pdc->dma_size);
tty_flip_buffer_push(tport);
atmel_uart_writel(port, ATMEL_US_IER,
ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
}
static int atmel_prepare_rx_pdc(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
int i;
for (i = 0; i < 2; i++) {
struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
if (pdc->buf == NULL) {
if (i != 0) {
dma_unmap_single(port->dev,
atmel_port->pdc_rx[0].dma_addr,
PDC_BUFFER_SIZE,
DMA_FROM_DEVICE);
kfree(atmel_port->pdc_rx[0].buf);
}
atmel_port->use_pdc_rx = false;
return -ENOMEM;
}
pdc->dma_addr = dma_map_single(port->dev,
pdc->buf,
PDC_BUFFER_SIZE,
DMA_FROM_DEVICE);
pdc->dma_size = PDC_BUFFER_SIZE;
pdc->ofs = 0;
}
atmel_port->pdc_rx_idx = 0;
atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
atmel_uart_writel(port, ATMEL_PDC_RNPR,
atmel_port->pdc_rx[1].dma_addr);
atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
return 0;
}
/*
* tasklet handling tty stuff outside the interrupt handler.
*/
static void atmel_tasklet_rx_func(struct tasklet_struct *t)
{
struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
tasklet_rx);
struct uart_port *port = &atmel_port->uart;
/* The interrupt handler does not take the lock */
spin_lock(&port->lock);
atmel_port->schedule_rx(port);
spin_unlock(&port->lock);
}
static void atmel_tasklet_tx_func(struct tasklet_struct *t)
{
struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
tasklet_tx);
struct uart_port *port = &atmel_port->uart;
/* The interrupt handler does not take the lock */
spin_lock(&port->lock);
atmel_port->schedule_tx(port);
spin_unlock(&port->lock);
}
static void atmel_init_property(struct atmel_uart_port *atmel_port,
struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
/* DMA/PDC usage specification */
if (of_property_read_bool(np, "atmel,use-dma-rx")) {
if (of_property_read_bool(np, "dmas")) {
atmel_port->use_dma_rx = true;
atmel_port->use_pdc_rx = false;
} else {
atmel_port->use_dma_rx = false;
atmel_port->use_pdc_rx = true;
}
} else {
atmel_port->use_dma_rx = false;
atmel_port->use_pdc_rx = false;
}
if (of_property_read_bool(np, "atmel,use-dma-tx")) {
if (of_property_read_bool(np, "dmas")) {
atmel_port->use_dma_tx = true;
atmel_port->use_pdc_tx = false;
} else {
atmel_port->use_dma_tx = false;
atmel_port->use_pdc_tx = true;
}
} else {
atmel_port->use_dma_tx = false;
atmel_port->use_pdc_tx = false;
}
}
static void atmel_set_ops(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (atmel_use_dma_rx(port)) {
atmel_port->prepare_rx = &atmel_prepare_rx_dma;
atmel_port->schedule_rx = &atmel_rx_from_dma;
atmel_port->release_rx = &atmel_release_rx_dma;
} else if (atmel_use_pdc_rx(port)) {
atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
atmel_port->schedule_rx = &atmel_rx_from_pdc;
atmel_port->release_rx = &atmel_release_rx_pdc;
} else {
atmel_port->prepare_rx = NULL;
atmel_port->schedule_rx = &atmel_rx_from_ring;
atmel_port->release_rx = NULL;
}
if (atmel_use_dma_tx(port)) {
atmel_port->prepare_tx = &atmel_prepare_tx_dma;
atmel_port->schedule_tx = &atmel_tx_dma;
atmel_port->release_tx = &atmel_release_tx_dma;
} else if (atmel_use_pdc_tx(port)) {
atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
atmel_port->schedule_tx = &atmel_tx_pdc;
atmel_port->release_tx = &atmel_release_tx_pdc;
} else {
atmel_port->prepare_tx = NULL;
atmel_port->schedule_tx = &atmel_tx_chars;
atmel_port->release_tx = NULL;
}
}
/*
* Get ip name usart or uart
*/
static void atmel_get_ip_name(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
int name = atmel_uart_readl(port, ATMEL_US_NAME);
u32 version;
u32 usart, dbgu_uart, new_uart;
/* ASCII decoding for IP version */
usart = 0x55534152; /* USAR(T) */
dbgu_uart = 0x44424755; /* DBGU */
new_uart = 0x55415254; /* UART */
/*
* Only USART devices from at91sam9260 SOC implement fractional
* baudrate. It is available for all asynchronous modes, with the
* following restriction: the sampling clock's duty cycle is not
* constant.
*/
atmel_port->has_frac_baudrate = false;
atmel_port->has_hw_timer = false;
atmel_port->is_usart = false;
if (name == new_uart) {
dev_dbg(port->dev, "Uart with hw timer");
atmel_port->has_hw_timer = true;
atmel_port->rtor = ATMEL_UA_RTOR;
} else if (name == usart) {
dev_dbg(port->dev, "Usart\n");
atmel_port->has_frac_baudrate = true;
atmel_port->has_hw_timer = true;
atmel_port->is_usart = true;
atmel_port->rtor = ATMEL_US_RTOR;
version = atmel_uart_readl(port, ATMEL_US_VERSION);
switch (version) {
case 0x814: /* sama5d2 */
fallthrough;
case 0x701: /* sama5d4 */
atmel_port->fidi_min = 3;
atmel_port->fidi_max = 65535;
break;
case 0x502: /* sam9x5, sama5d3 */
atmel_port->fidi_min = 3;
atmel_port->fidi_max = 2047;
break;
default:
atmel_port->fidi_min = 1;
atmel_port->fidi_max = 2047;
}
} else if (name == dbgu_uart) {
dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
} else {
/* fallback for older SoCs: use version field */
version = atmel_uart_readl(port, ATMEL_US_VERSION);
switch (version) {
case 0x302:
case 0x10213:
case 0x10302:
dev_dbg(port->dev, "This version is usart\n");
atmel_port->has_frac_baudrate = true;
atmel_port->has_hw_timer = true;
atmel_port->is_usart = true;
atmel_port->rtor = ATMEL_US_RTOR;
break;
case 0x203:
case 0x10202:
dev_dbg(port->dev, "This version is uart\n");
break;
default:
dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
}
}
}
/*
* Perform initialization and enable port for reception
*/
static int atmel_startup(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
int retval;
/*
* Ensure that no interrupts are enabled otherwise when
* request_irq() is called we could get stuck trying to
* handle an unexpected interrupt
*/
atmel_uart_writel(port, ATMEL_US_IDR, -1);
atmel_port->ms_irq_enabled = false;
/*
* Allocate the IRQ
*/
retval = request_irq(port->irq, atmel_interrupt,
IRQF_SHARED | IRQF_COND_SUSPEND,
dev_name(&pdev->dev), port);
if (retval) {
dev_err(port->dev, "atmel_startup - Can't get irq\n");
return retval;
}
atomic_set(&atmel_port->tasklet_shutdown, 0);
tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
/*
* Initialize DMA (if necessary)
*/
atmel_init_property(atmel_port, pdev);
atmel_set_ops(port);
if (atmel_port->prepare_rx) {
retval = atmel_port->prepare_rx(port);
if (retval < 0)
atmel_set_ops(port);
}
if (atmel_port->prepare_tx) {
retval = atmel_port->prepare_tx(port);
if (retval < 0)
atmel_set_ops(port);
}
/*
* Enable FIFO when available
*/
if (atmel_port->fifo_size) {
unsigned int txrdym = ATMEL_US_ONE_DATA;
unsigned int rxrdym = ATMEL_US_ONE_DATA;
unsigned int fmr;
atmel_uart_writel(port, ATMEL_US_CR,
ATMEL_US_FIFOEN |
ATMEL_US_RXFCLR |
ATMEL_US_TXFLCLR);
if (atmel_use_dma_tx(port))
txrdym = ATMEL_US_FOUR_DATA;
fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
if (atmel_port->rts_high &&
atmel_port->rts_low)
fmr |= ATMEL_US_FRTSC |
ATMEL_US_RXFTHRES(atmel_port->rts_high) |
ATMEL_US_RXFTHRES2(atmel_port->rts_low);
atmel_uart_writel(port, ATMEL_US_FMR, fmr);
}
/* Save current CSR for comparison in atmel_tasklet_func() */
atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
/*
* Finally, enable the serial port
*/
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
/* enable xmit & rcvr */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
atmel_port->tx_stopped = false;
timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
if (atmel_use_pdc_rx(port)) {
/* set UART timeout */
if (!atmel_port->has_hw_timer) {
mod_timer(&atmel_port->uart_timer,
jiffies + uart_poll_timeout(port));
/* set USART timeout */
} else {
atmel_uart_writel(port, atmel_port->rtor,
PDC_RX_TIMEOUT);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
atmel_uart_writel(port, ATMEL_US_IER,
ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
}
/* enable PDC controller */
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
} else if (atmel_use_dma_rx(port)) {
/* set UART timeout */
if (!atmel_port->has_hw_timer) {
mod_timer(&atmel_port->uart_timer,
jiffies + uart_poll_timeout(port));
/* set USART timeout */
} else {
atmel_uart_writel(port, atmel_port->rtor,
PDC_RX_TIMEOUT);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
atmel_uart_writel(port, ATMEL_US_IER,
ATMEL_US_TIMEOUT);
}
} else {
/* enable receive only */
atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
}
return 0;
}
/*
* Flush any TX data submitted for DMA. Called when the TX circular
* buffer is reset.
*/
static void atmel_flush_buffer(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (atmel_use_pdc_tx(port)) {
atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
atmel_port->pdc_tx.ofs = 0;
}
/*
* in uart_flush_buffer(), the xmit circular buffer has just
* been cleared, so we have to reset tx_len accordingly.
*/
atmel_port->tx_len = 0;
}
/*
* Disable the port
*/
static void atmel_shutdown(struct uart_port *port)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
/* Disable modem control lines interrupts */
atmel_disable_ms(port);
/* Disable interrupts at device level */
atmel_uart_writel(port, ATMEL_US_IDR, -1);
/* Prevent spurious interrupts from scheduling the tasklet */
atomic_inc(&atmel_port->tasklet_shutdown);
/*
* Prevent any tasklets being scheduled during
* cleanup
*/
del_timer_sync(&atmel_port->uart_timer);
/* Make sure that no interrupt is on the fly */
synchronize_irq(port->irq);
/*
* Clear out any scheduled tasklets before
* we destroy the buffers
*/
tasklet_kill(&atmel_port->tasklet_rx);
tasklet_kill(&atmel_port->tasklet_tx);
/*
* Ensure everything is stopped and
* disable port and break condition.
*/
atmel_stop_rx(port);
atmel_stop_tx(port);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
/*
* Shut-down the DMA.
*/
if (atmel_port->release_rx)
atmel_port->release_rx(port);
if (atmel_port->release_tx)
atmel_port->release_tx(port);
/*
* Reset ring buffer pointers
*/
atmel_port->rx_ring.head = 0;
atmel_port->rx_ring.tail = 0;
/*
* Free the interrupts
*/
free_irq(port->irq, port);
atmel_flush_buffer(port);
}
/*
* Power / Clock management.
*/
static void atmel_serial_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
switch (state) {
case UART_PM_STATE_ON:
/*
* Enable the peripheral clock for this serial port.
* This is called on uart_open() or a resume event.
*/
clk_prepare_enable(atmel_port->clk);
/* re-enable interrupts if we disabled some on suspend */
atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
break;
case UART_PM_STATE_OFF:
/* Back up the interrupt mask and disable all interrupts */
atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
atmel_uart_writel(port, ATMEL_US_IDR, -1);
/*
* Disable the peripheral clock for this serial port.
* This is called on uart_close() or a suspend event.
*/
clk_disable_unprepare(atmel_port->clk);
if (__clk_is_enabled(atmel_port->gclk))
clk_disable_unprepare(atmel_port->gclk);
break;
default:
dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
}
}
/*
* Change the port parameters
*/
static void atmel_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned long flags;
unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
unsigned int baud, actual_baud, gclk_rate;
int ret;
/* save the current mode register */
mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
/* reset the mode, clock divisor, parity, stop bits and data size */
if (atmel_port->is_usart)
mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
ATMEL_US_USCLKS | ATMEL_US_USMODE);
else
mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
/* byte size */
switch (termios->c_cflag & CSIZE) {
case CS5:
mode |= ATMEL_US_CHRL_5;
break;
case CS6:
mode |= ATMEL_US_CHRL_6;
break;
case CS7:
mode |= ATMEL_US_CHRL_7;
break;
default:
mode |= ATMEL_US_CHRL_8;
break;
}
/* stop bits */
if (termios->c_cflag & CSTOPB)
mode |= ATMEL_US_NBSTOP_2;
/* parity */
if (termios->c_cflag & PARENB) {
/* Mark or Space parity */
if (termios->c_cflag & CMSPAR) {
if (termios->c_cflag & PARODD)
mode |= ATMEL_US_PAR_MARK;
else
mode |= ATMEL_US_PAR_SPACE;
} else if (termios->c_cflag & PARODD)
mode |= ATMEL_US_PAR_ODD;
else
mode |= ATMEL_US_PAR_EVEN;
} else
mode |= ATMEL_US_PAR_NONE;
spin_lock_irqsave(&port->lock, flags);
port->read_status_mask = ATMEL_US_OVRE;
if (termios->c_iflag & INPCK)
port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
port->read_status_mask |= ATMEL_US_RXBRK;
if (atmel_use_pdc_rx(port))
/* need to enable error interrupts */
atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= ATMEL_US_RXBRK;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= ATMEL_US_OVRE;
}
/* TODO: Ignore all characters if CREAD is set.*/
/* update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, baud);
/*
* save/disable interrupts. The tty layer will ensure that the
* transmitter is empty if requested by the caller, so there's
* no need to wait for it here.
*/
imr = atmel_uart_readl(port, ATMEL_US_IMR);
atmel_uart_writel(port, ATMEL_US_IDR, -1);
/* disable receiver and transmitter */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
atmel_port->tx_stopped = true;
/* mode */
if (port->rs485.flags & SER_RS485_ENABLED) {
atmel_uart_writel(port, ATMEL_US_TTGR,
port->rs485.delay_rts_after_send);
mode |= ATMEL_US_USMODE_RS485;
} else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
/* select mck clock, and output */
mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
/* set max iterations */
mode |= ATMEL_US_MAX_ITER(3);
if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
== SER_ISO7816_T(0))
mode |= ATMEL_US_USMODE_ISO7816_T0;
else
mode |= ATMEL_US_USMODE_ISO7816_T1;
} else if (termios->c_cflag & CRTSCTS) {
/* RS232 with hardware handshake (RTS/CTS) */
if (atmel_use_fifo(port) &&
!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
/*
* with ATMEL_US_USMODE_HWHS set, the controller will
* be able to drive the RTS pin high/low when the RX
* FIFO is above RXFTHRES/below RXFTHRES2.
* It will also disable the transmitter when the CTS
* pin is high.
* This mode is not activated if CTS pin is a GPIO
* because in this case, the transmitter is always
* disabled (there must be an internal pull-up
* responsible for this behaviour).
* If the RTS pin is a GPIO, the controller won't be
* able to drive it according to the FIFO thresholds,
* but it will be handled by the driver.
*/
mode |= ATMEL_US_USMODE_HWHS;
} else {
/*
* For platforms without FIFO, the flow control is
* handled by the driver.
*/
mode |= ATMEL_US_USMODE_NORMAL;
}
} else {
/* RS232 without hadware handshake */
mode |= ATMEL_US_USMODE_NORMAL;
}
/*
* Set the baud rate:
* Fractional baudrate allows to setup output frequency more
* accurately. This feature is enabled only when using normal mode.
* baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
* Currently, OVER is always set to 0 so we get
* baudrate = selected clock / (16 * (CD + FP / 8))
* then
* 8 CD + FP = selected clock / (2 * baudrate)
*/
if (atmel_port->has_frac_baudrate) {
div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
cd = div >> 3;
fp = div & ATMEL_US_FP_MASK;
} else {
cd = uart_get_divisor(port, baud);
}
/*
* If the current value of the Clock Divisor surpasses the 16 bit
* ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
* Clock implicitly divided by 8.
* If the IP is UART however, keep the highest possible value for
* the CD and avoid needless division of CD, since UART IP's do not
* support implicit division of the Peripheral Clock.
*/
if (atmel_port->is_usart && cd > ATMEL_US_CD) {
cd /= 8;
mode |= ATMEL_US_USCLKS_MCK_DIV8;
} else {
cd = min_t(unsigned int, cd, ATMEL_US_CD);
}
/*
* If there is no Fractional Part, there is a high chance that
* we may be able to generate a baudrate closer to the desired one
* if we use the GCLK as the clock source driving the baudrate
* generator.
*/
if (!atmel_port->has_frac_baudrate) {
if (__clk_is_enabled(atmel_port->gclk))
clk_disable_unprepare(atmel_port->gclk);
gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
abs(atmel_error_rate(baud, gclk_rate / 16))) {
clk_set_rate(atmel_port->gclk, 16 * baud);
ret = clk_prepare_enable(atmel_port->gclk);
if (ret)
goto gclk_fail;
if (atmel_port->is_usart) {
mode &= ~ATMEL_US_USCLKS;
mode |= ATMEL_US_USCLKS_GCLK;
} else {
mode |= ATMEL_UA_BRSRCCK;
}
/*
* Set the Clock Divisor for GCLK to 1.
* Since we were able to generate the smallest
* multiple of the desired baudrate times 16,
* then we surely can generate a bigger multiple
* with the exact error rate for an equally increased
* CD. Thus no need to take into account
* a higher value for CD.
*/
cd = 1;
}
}
gclk_fail:
quot = cd | fp << ATMEL_US_FP_OFFSET;
if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
atmel_uart_writel(port, ATMEL_US_BRGR, quot);
/* set the mode, clock divisor, parity, stop bits and data size */
atmel_uart_writel(port, ATMEL_US_MR, mode);
/*
* when switching the mode, set the RTS line state according to the
* new mode, otherwise keep the former state
*/
if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
unsigned int rts_state;
if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
/* let the hardware control the RTS line */
rts_state = ATMEL_US_RTSDIS;
} else {
/* force RTS line to low level */
rts_state = ATMEL_US_RTSEN;
}
atmel_uart_writel(port, ATMEL_US_CR, rts_state);
}
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
atmel_port->tx_stopped = false;
/* restore interrupts */
atmel_uart_writel(port, ATMEL_US_IER, imr);
/* CTS flow-control and modem-status interrupts */
if (UART_ENABLE_MS(port, termios->c_cflag))
atmel_enable_ms(port);
else
atmel_disable_ms(port);
spin_unlock_irqrestore(&port->lock, flags);
}
static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
{
if (termios->c_line == N_PPS) {
port->flags |= UPF_HARDPPS_CD;
spin_lock_irq(&port->lock);
atmel_enable_ms(port);
spin_unlock_irq(&port->lock);
} else {
port->flags &= ~UPF_HARDPPS_CD;
if (!UART_ENABLE_MS(port, termios->c_cflag)) {
spin_lock_irq(&port->lock);
atmel_disable_ms(port);
spin_unlock_irq(&port->lock);
}
}
}
/*
* Return string describing the specified port
*/
static const char *atmel_type(struct uart_port *port)
{
return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
}
/*
* Release the memory region(s) being used by 'port'.
*/
static void atmel_release_port(struct uart_port *port)
{
struct platform_device *mpdev = to_platform_device(port->dev->parent);
int size = resource_size(mpdev->resource);
release_mem_region(port->mapbase, size);
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
port->membase = NULL;
}
}
/*
* Request the memory region(s) being used by 'port'.
*/
static int atmel_request_port(struct uart_port *port)
{
struct platform_device *mpdev = to_platform_device(port->dev->parent);
int size = resource_size(mpdev->resource);
if (!request_mem_region(port->mapbase, size, "atmel_serial"))
return -EBUSY;
if (port->flags & UPF_IOREMAP) {
port->membase = ioremap(port->mapbase, size);
if (port->membase == NULL) {
release_mem_region(port->mapbase, size);
return -ENOMEM;
}
}
return 0;
}
/*
* Configure/autoconfigure the port.
*/
static void atmel_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_ATMEL;
atmel_request_port(port);
}
}
/*
* Verify the new serial_struct (for TIOCSSERIAL).
*/
static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
ret = -EINVAL;
if (port->irq != ser->irq)
ret = -EINVAL;
if (ser->io_type != SERIAL_IO_MEM)
ret = -EINVAL;
if (port->uartclk / 16 != ser->baud_base)
ret = -EINVAL;
if (port->mapbase != (unsigned long)ser->iomem_base)
ret = -EINVAL;
if (port->iobase != ser->port)
ret = -EINVAL;
if (ser->hub6 != 0)
ret = -EINVAL;
return ret;
}
#ifdef CONFIG_CONSOLE_POLL
static int atmel_poll_get_char(struct uart_port *port)
{
while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
cpu_relax();
return atmel_uart_read_char(port);
}
static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
{
while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
cpu_relax();
atmel_uart_write_char(port, ch);
}
#endif
static const struct uart_ops atmel_pops = {
.tx_empty = atmel_tx_empty,
.set_mctrl = atmel_set_mctrl,
.get_mctrl = atmel_get_mctrl,
.stop_tx = atmel_stop_tx,
.start_tx = atmel_start_tx,
.stop_rx = atmel_stop_rx,
.enable_ms = atmel_enable_ms,
.break_ctl = atmel_break_ctl,
.startup = atmel_startup,
.shutdown = atmel_shutdown,
.flush_buffer = atmel_flush_buffer,
.set_termios = atmel_set_termios,
.set_ldisc = atmel_set_ldisc,
.type = atmel_type,
.release_port = atmel_release_port,
.request_port = atmel_request_port,
.config_port = atmel_config_port,
.verify_port = atmel_verify_port,
.pm = atmel_serial_pm,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = atmel_poll_get_char,
.poll_put_char = atmel_poll_put_char,
#endif
};
static const struct serial_rs485 atmel_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
.delay_rts_before_send = 1,
.delay_rts_after_send = 1,
};
/*
* Configure the port from the platform device resource info.
*/
static int atmel_init_port(struct atmel_uart_port *atmel_port,
struct platform_device *pdev)
{
int ret;
struct uart_port *port = &atmel_port->uart;
struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
atmel_init_property(atmel_port, pdev);
atmel_set_ops(port);
port->iotype = UPIO_MEM;
port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
port->ops = &atmel_pops;
port->fifosize = 1;
port->dev = &pdev->dev;
port->mapbase = mpdev->resource[0].start;
port->irq = platform_get_irq(mpdev, 0);
port->rs485_config = atmel_config_rs485;
port->rs485_supported = atmel_rs485_supported;
port->iso7816_config = atmel_config_iso7816;
port->membase = NULL;
memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
ret = uart_get_rs485_mode(port);
if (ret)
return ret;
port->uartclk = clk_get_rate(atmel_port->clk);
/*
* Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
* ENDTX|TXBUFE
*/
if (atmel_uart_is_half_duplex(port))
atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
else if (atmel_use_pdc_tx(port)) {
port->fifosize = PDC_BUFFER_SIZE;
atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
} else {
atmel_port->tx_done_mask = ATMEL_US_TXRDY;
}
return 0;
}
#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
{
while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
cpu_relax();
atmel_uart_write_char(port, ch);
}
/*
* Interrupts are disabled on entering
*/
static void atmel_console_write(struct console *co, const char *s, u_int count)
{
struct uart_port *port = &atmel_ports[co->index].uart;
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned int status, imr;
unsigned int pdc_tx;
/*
* First, save IMR and then disable interrupts
*/
imr = atmel_uart_readl(port, ATMEL_US_IMR);
atmel_uart_writel(port, ATMEL_US_IDR,
ATMEL_US_RXRDY | atmel_port->tx_done_mask);
/* Store PDC transmit status and disable it */
pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
/* Make sure that tx path is actually able to send characters */
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
atmel_port->tx_stopped = false;
uart_console_write(port, s, count, atmel_console_putchar);
/*
* Finally, wait for transmitter to become empty
* and restore IMR
*/
do {
status = atmel_uart_readl(port, ATMEL_US_CSR);
} while (!(status & ATMEL_US_TXRDY));
/* Restore PDC transmit status */
if (pdc_tx)
atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
/* set interrupts back the way they were */
atmel_uart_writel(port, ATMEL_US_IER, imr);
}
/*
* If the port was already initialised (eg, by a boot loader),
* try to determine the current setup.
*/
static void __init atmel_console_get_options(struct uart_port *port, int *baud,
int *parity, int *bits)
{
unsigned int mr, quot;
/*
* If the baud rate generator isn't running, the port wasn't
* initialized by the boot loader.
*/
quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
if (!quot)
return;
mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
if (mr == ATMEL_US_CHRL_8)
*bits = 8;
else
*bits = 7;
mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
if (mr == ATMEL_US_PAR_EVEN)
*parity = 'e';
else if (mr == ATMEL_US_PAR_ODD)
*parity = 'o';
*baud = port->uartclk / (16 * quot);
}
static int __init atmel_console_setup(struct console *co, char *options)
{
struct uart_port *port = &atmel_ports[co->index].uart;
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (port->membase == NULL) {
/* Port not initialized yet - delay setup */
return -ENODEV;
}
atmel_uart_writel(port, ATMEL_US_IDR, -1);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
atmel_port->tx_stopped = false;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
else
atmel_console_get_options(port, &baud, &parity, &bits);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver atmel_uart;
static struct console atmel_console = {
.name = ATMEL_DEVICENAME,
.write = atmel_console_write,
.device = uart_console_device,
.setup = atmel_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &atmel_uart,
};
static void atmel_serial_early_write(struct console *con, const char *s,
unsigned int n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, atmel_console_putchar);
}
static int __init atmel_early_console_setup(struct earlycon_device *device,
const char *options)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = atmel_serial_early_write;
return 0;
}
OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
atmel_early_console_setup);
OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
atmel_early_console_setup);
#define ATMEL_CONSOLE_DEVICE (&atmel_console)
#else
#define ATMEL_CONSOLE_DEVICE NULL
#endif
static struct uart_driver atmel_uart = {
.owner = THIS_MODULE,
.driver_name = "atmel_serial",
.dev_name = ATMEL_DEVICENAME,
.major = SERIAL_ATMEL_MAJOR,
.minor = MINOR_START,
.nr = ATMEL_MAX_UART,
.cons = ATMEL_CONSOLE_DEVICE,
};
static bool atmel_serial_clk_will_stop(void)
{
#ifdef CONFIG_ARCH_AT91
return at91_suspend_entering_slow_clock();
#else
return false;
#endif
}
static int __maybe_unused atmel_serial_suspend(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (uart_console(port) && console_suspend_enabled) {
/* Drain the TX shifter */
while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
ATMEL_US_TXEMPTY))
cpu_relax();
}
if (uart_console(port) && !console_suspend_enabled) {
/* Cache register values as we won't get a full shutdown/startup
* cycle
*/
atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
atmel_port->cache.rtor = atmel_uart_readl(port,
atmel_port->rtor);
atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
}
/* we can not wake up if we're running on slow clock */
atmel_port->may_wakeup = device_may_wakeup(dev);
if (atmel_serial_clk_will_stop()) {
unsigned long flags;
spin_lock_irqsave(&atmel_port->lock_suspended, flags);
atmel_port->suspended = true;
spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
device_set_wakeup_enable(dev, 0);
}
uart_suspend_port(&atmel_uart, port);
return 0;
}
static int __maybe_unused atmel_serial_resume(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
unsigned long flags;
if (uart_console(port) && !console_suspend_enabled) {
atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
atmel_uart_writel(port, atmel_port->rtor,
atmel_port->cache.rtor);
atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
if (atmel_port->fifo_size) {
atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
atmel_uart_writel(port, ATMEL_US_FMR,
atmel_port->cache.fmr);
atmel_uart_writel(port, ATMEL_US_FIER,
atmel_port->cache.fimr);
}
atmel_start_rx(port);
}
spin_lock_irqsave(&atmel_port->lock_suspended, flags);
if (atmel_port->pending) {
atmel_handle_receive(port, atmel_port->pending);
atmel_handle_status(port, atmel_port->pending,
atmel_port->pending_status);
atmel_handle_transmit(port, atmel_port->pending);
atmel_port->pending = 0;
}
atmel_port->suspended = false;
spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
uart_resume_port(&atmel_uart, port);
device_set_wakeup_enable(dev, atmel_port->may_wakeup);
return 0;
}
static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
struct platform_device *pdev)
{
atmel_port->fifo_size = 0;
atmel_port->rts_low = 0;
atmel_port->rts_high = 0;
if (of_property_read_u32(pdev->dev.of_node,
"atmel,fifo-size",
&atmel_port->fifo_size))
return;
if (!atmel_port->fifo_size)
return;
if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
atmel_port->fifo_size = 0;
dev_err(&pdev->dev, "Invalid FIFO size\n");
return;
}
/*
* 0 <= rts_low <= rts_high <= fifo_size
* Once their CTS line asserted by the remote peer, some x86 UARTs tend
* to flush their internal TX FIFO, commonly up to 16 data, before
* actually stopping to send new data. So we try to set the RTS High
* Threshold to a reasonably high value respecting this 16 data
* empirical rule when possible.
*/
atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
dev_info(&pdev->dev, "Using FIFO (%u data)\n",
atmel_port->fifo_size);
dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
atmel_port->rts_high);
dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
atmel_port->rts_low);
}
static int atmel_serial_probe(struct platform_device *pdev)
{
struct atmel_uart_port *atmel_port;
struct device_node *np = pdev->dev.parent->of_node;
void *data;
int ret;
bool rs485_enabled;
BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
/*
* In device tree there is no node with "atmel,at91rm9200-usart-serial"
* as compatible string. This driver is probed by at91-usart mfd driver
* which is just a wrapper over the atmel_serial driver and
* spi-at91-usart driver. All attributes needed by this driver are
* found in of_node of parent.
*/
pdev->dev.of_node = np;
ret = of_alias_get_id(np, "serial");
if (ret < 0)
/* port id not found in platform data nor device-tree aliases:
* auto-enumerate it */
ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
if (ret >= ATMEL_MAX_UART) {
ret = -ENODEV;
goto err;
}
if (test_and_set_bit(ret, atmel_ports_in_use)) {
/* port already in use */
ret = -EBUSY;
goto err;
}
atmel_port = &atmel_ports[ret];
atmel_port->backup_imr = 0;
atmel_port->uart.line = ret;
atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
atmel_serial_probe_fifos(atmel_port, pdev);
atomic_set(&atmel_port->tasklet_shutdown, 0);
spin_lock_init(&atmel_port->lock_suspended);
atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
if (IS_ERR(atmel_port->clk)) {
ret = PTR_ERR(atmel_port->clk);
goto err;
}
ret = clk_prepare_enable(atmel_port->clk);
if (ret)
goto err;
atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
if (IS_ERR(atmel_port->gclk)) {
ret = PTR_ERR(atmel_port->gclk);
goto err_clk_disable_unprepare;
}
ret = atmel_init_port(atmel_port, pdev);
if (ret)
goto err_clk_disable_unprepare;
atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
if (IS_ERR(atmel_port->gpios)) {
ret = PTR_ERR(atmel_port->gpios);
goto err_clk_disable_unprepare;
}
if (!atmel_use_pdc_rx(&atmel_port->uart)) {
ret = -ENOMEM;
data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
sizeof(struct atmel_uart_char),
GFP_KERNEL);
if (!data)
goto err_clk_disable_unprepare;
atmel_port->rx_ring.buf = data;
}
rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
if (ret)
goto err_add_port;
device_init_wakeup(&pdev->dev, 1);
platform_set_drvdata(pdev, atmel_port);
if (rs485_enabled) {
atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
ATMEL_US_USMODE_NORMAL);
atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
ATMEL_US_RTSEN);
}
/*
* Get port name of usart or uart
*/
atmel_get_ip_name(&atmel_port->uart);
/*
* The peripheral clock can now safely be disabled till the port
* is used
*/
clk_disable_unprepare(atmel_port->clk);
return 0;
err_add_port:
kfree(atmel_port->rx_ring.buf);
atmel_port->rx_ring.buf = NULL;
err_clk_disable_unprepare:
clk_disable_unprepare(atmel_port->clk);
clear_bit(atmel_port->uart.line, atmel_ports_in_use);
err:
return ret;
}
/*
* Even if the driver is not modular, it makes sense to be able to
* unbind a device: there can be many bound devices, and there are
* situations where dynamic binding and unbinding can be useful.
*
* For example, a connected device can require a specific firmware update
* protocol that needs bitbanging on IO lines, but use the regular serial
* port in the normal case.
*/
static int atmel_serial_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
tasklet_kill(&atmel_port->tasklet_rx);
tasklet_kill(&atmel_port->tasklet_tx);
device_init_wakeup(&pdev->dev, 0);
uart_remove_one_port(&atmel_uart, port);
kfree(atmel_port->rx_ring.buf);
/* "port" is allocated statically, so we shouldn't free it */
clear_bit(port->line, atmel_ports_in_use);
pdev->dev.of_node = NULL;
return 0;
}
static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
atmel_serial_resume);
static struct platform_driver atmel_serial_driver = {
.probe = atmel_serial_probe,
.remove = atmel_serial_remove,
.driver = {
.name = "atmel_usart_serial",
.of_match_table = of_match_ptr(atmel_serial_dt_ids),
.pm = pm_ptr(&atmel_serial_pm_ops),
},
};
static int __init atmel_serial_init(void)
{
int ret;
ret = uart_register_driver(&atmel_uart);
if (ret)
return ret;
ret = platform_driver_register(&atmel_serial_driver);
if (ret)
uart_unregister_driver(&atmel_uart);
return ret;
}
device_initcall(atmel_serial_init);
| linux-master | drivers/tty/serial/atmel_serial.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/io.h>
#define URTX0 0x40 /* Transmitter Register */
#define UTS_TXFULL (1<<4) /* TxFIFO full */
#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
static void imx_uart_console_early_putchar(struct uart_port *port, unsigned char ch)
{
while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
cpu_relax();
writel_relaxed(ch, port->membase + URTX0);
}
static void imx_uart_console_early_write(struct console *con, const char *s,
unsigned count)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
}
static int __init
imx_console_early_setup(struct earlycon_device *dev, const char *opt)
{
if (!dev->port.membase)
return -ENODEV;
dev->con->write = imx_uart_console_early_write;
return 0;
}
OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
MODULE_AUTHOR("NXP");
MODULE_DESCRIPTION("IMX earlycon driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/imx_earlycon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for GRLIB serial ports (APBUART)
*
* Based on linux/drivers/serial/amba.c
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
* Copyright (C) 2003 Konrad Eisele <[email protected]>
* Copyright (C) 2006 Daniel Hellstrom <[email protected]>, Aeroflex Gaisler AB
* Copyright (C) 2008 Gilead Kutnick <[email protected]>
* Copyright (C) 2009 Kristoffer Glembo <[email protected]>, Aeroflex Gaisler AB
*/
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/kthread.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/serial_core.h>
#include <asm/irq.h>
#include "apbuart.h"
#define SERIAL_APBUART_MAJOR TTY_MAJOR
#define SERIAL_APBUART_MINOR 64
#define UART_DUMMY_RSR_RX 0x8000 /* for ignore all read */
static void apbuart_tx_chars(struct uart_port *port);
static void apbuart_stop_tx(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CTRL(port);
cr &= ~UART_CTRL_TI;
UART_PUT_CTRL(port, cr);
}
static void apbuart_start_tx(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CTRL(port);
cr |= UART_CTRL_TI;
UART_PUT_CTRL(port, cr);
if (UART_GET_STATUS(port) & UART_STATUS_THE)
apbuart_tx_chars(port);
}
static void apbuart_stop_rx(struct uart_port *port)
{
unsigned int cr;
cr = UART_GET_CTRL(port);
cr &= ~(UART_CTRL_RI);
UART_PUT_CTRL(port, cr);
}
static void apbuart_rx_chars(struct uart_port *port)
{
unsigned int status, rsr;
unsigned int max_chars = port->fifosize;
u8 ch, flag;
status = UART_GET_STATUS(port);
while (UART_RX_DATA(status) && (max_chars--)) {
ch = UART_GET_CHAR(port);
flag = TTY_NORMAL;
port->icount.rx++;
rsr = UART_GET_STATUS(port) | UART_DUMMY_RSR_RX;
UART_PUT_STATUS(port, 0);
if (rsr & UART_STATUS_ERR) {
if (rsr & UART_STATUS_BR) {
rsr &= ~(UART_STATUS_FE | UART_STATUS_PE);
port->icount.brk++;
if (uart_handle_break(port))
goto ignore_char;
} else if (rsr & UART_STATUS_PE) {
port->icount.parity++;
} else if (rsr & UART_STATUS_FE) {
port->icount.frame++;
}
if (rsr & UART_STATUS_OE)
port->icount.overrun++;
rsr &= port->read_status_mask;
if (rsr & UART_STATUS_PE)
flag = TTY_PARITY;
else if (rsr & UART_STATUS_FE)
flag = TTY_FRAME;
}
if (uart_handle_sysrq_char(port, ch))
goto ignore_char;
uart_insert_char(port, rsr, UART_STATUS_OE, ch, flag);
ignore_char:
status = UART_GET_STATUS(port);
}
tty_flip_buffer_push(&port->state->port);
}
static void apbuart_tx_chars(struct uart_port *port)
{
u8 ch;
uart_port_tx_limited(port, ch, port->fifosize >> 1,
true,
UART_PUT_CHAR(port, ch),
({}));
}
static irqreturn_t apbuart_int(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
unsigned int status;
spin_lock(&port->lock);
status = UART_GET_STATUS(port);
if (status & UART_STATUS_DR)
apbuart_rx_chars(port);
if (status & UART_STATUS_THE)
apbuart_tx_chars(port);
spin_unlock(&port->lock);
return IRQ_HANDLED;
}
static unsigned int apbuart_tx_empty(struct uart_port *port)
{
unsigned int status = UART_GET_STATUS(port);
return status & UART_STATUS_THE ? TIOCSER_TEMT : 0;
}
static unsigned int apbuart_get_mctrl(struct uart_port *port)
{
/* The GRLIB APBUART handles flow control in hardware */
return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
}
static void apbuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
/* The GRLIB APBUART handles flow control in hardware */
}
static void apbuart_break_ctl(struct uart_port *port, int break_state)
{
/* We don't support sending break */
}
static int apbuart_startup(struct uart_port *port)
{
int retval;
unsigned int cr;
/* Allocate the IRQ */
retval = request_irq(port->irq, apbuart_int, 0, "apbuart", port);
if (retval)
return retval;
/* Finally, enable interrupts */
cr = UART_GET_CTRL(port);
UART_PUT_CTRL(port,
cr | UART_CTRL_RE | UART_CTRL_TE |
UART_CTRL_RI | UART_CTRL_TI);
return 0;
}
static void apbuart_shutdown(struct uart_port *port)
{
unsigned int cr;
/* disable all interrupts, disable the port */
cr = UART_GET_CTRL(port);
UART_PUT_CTRL(port,
cr & ~(UART_CTRL_RE | UART_CTRL_TE |
UART_CTRL_RI | UART_CTRL_TI));
/* Free the interrupt */
free_irq(port->irq, port);
}
static void apbuart_set_termios(struct uart_port *port,
struct ktermios *termios, const struct ktermios *old)
{
unsigned int cr;
unsigned long flags;
unsigned int baud, quot;
/* Ask the core to calculate the divisor for us. */
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
if (baud == 0)
panic("invalid baudrate %i\n", port->uartclk / 16);
/* uart_get_divisor calc a *16 uart freq, apbuart is *8 */
quot = (uart_get_divisor(port, baud)) * 2;
cr = UART_GET_CTRL(port);
cr &= ~(UART_CTRL_PE | UART_CTRL_PS);
if (termios->c_cflag & PARENB) {
cr |= UART_CTRL_PE;
if ((termios->c_cflag & PARODD))
cr |= UART_CTRL_PS;
}
/* Enable flow control. */
if (termios->c_cflag & CRTSCTS)
cr |= UART_CTRL_FL;
spin_lock_irqsave(&port->lock, flags);
/* Update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);
port->read_status_mask = UART_STATUS_OE;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UART_STATUS_FE | UART_STATUS_PE;
/* Characters to ignore */
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= UART_STATUS_FE | UART_STATUS_PE;
/* Ignore all characters if CREAD is not set. */
if ((termios->c_cflag & CREAD) == 0)
port->ignore_status_mask |= UART_DUMMY_RSR_RX;
/* Set baud rate */
quot -= 1;
UART_PUT_SCAL(port, quot);
UART_PUT_CTRL(port, cr);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *apbuart_type(struct uart_port *port)
{
return port->type == PORT_APBUART ? "GRLIB/APBUART" : NULL;
}
static void apbuart_release_port(struct uart_port *port)
{
release_mem_region(port->mapbase, 0x100);
}
static int apbuart_request_port(struct uart_port *port)
{
return request_mem_region(port->mapbase, 0x100, "grlib-apbuart")
!= NULL ? 0 : -EBUSY;
return 0;
}
/* Configure/autoconfigure the port */
static void apbuart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_APBUART;
apbuart_request_port(port);
}
}
/* Verify the new serial_struct (for TIOCSSERIAL) */
static int apbuart_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_APBUART)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
return ret;
}
static const struct uart_ops grlib_apbuart_ops = {
.tx_empty = apbuart_tx_empty,
.set_mctrl = apbuart_set_mctrl,
.get_mctrl = apbuart_get_mctrl,
.stop_tx = apbuart_stop_tx,
.start_tx = apbuart_start_tx,
.stop_rx = apbuart_stop_rx,
.break_ctl = apbuart_break_ctl,
.startup = apbuart_startup,
.shutdown = apbuart_shutdown,
.set_termios = apbuart_set_termios,
.type = apbuart_type,
.release_port = apbuart_release_port,
.request_port = apbuart_request_port,
.config_port = apbuart_config_port,
.verify_port = apbuart_verify_port,
};
static struct uart_port grlib_apbuart_ports[UART_NR];
static struct device_node *grlib_apbuart_nodes[UART_NR];
static int apbuart_scan_fifo_size(struct uart_port *port, int portnumber)
{
int ctrl, loop = 0;
int status;
int fifosize;
unsigned long flags;
ctrl = UART_GET_CTRL(port);
/*
* Enable the transceiver and wait for it to be ready to send data.
* Clear interrupts so that this process will not be externally
* interrupted in the middle (which can cause the transceiver to
* drain prematurely).
*/
local_irq_save(flags);
UART_PUT_CTRL(port, ctrl | UART_CTRL_TE);
while (!UART_TX_READY(UART_GET_STATUS(port)))
loop++;
/*
* Disable the transceiver so data isn't actually sent during the
* actual test.
*/
UART_PUT_CTRL(port, ctrl & ~(UART_CTRL_TE));
fifosize = 1;
UART_PUT_CHAR(port, 0);
/*
* So long as transmitting a character increments the tranceivier FIFO
* length the FIFO must be at least that big. These bytes will
* automatically drain off of the FIFO.
*/
status = UART_GET_STATUS(port);
while (((status >> 20) & 0x3F) == fifosize) {
fifosize++;
UART_PUT_CHAR(port, 0);
status = UART_GET_STATUS(port);
}
fifosize--;
UART_PUT_CTRL(port, ctrl);
local_irq_restore(flags);
if (fifosize == 0)
fifosize = 1;
return fifosize;
}
static void apbuart_flush_fifo(struct uart_port *port)
{
int i;
for (i = 0; i < port->fifosize; i++)
UART_GET_CHAR(port);
}
/* ======================================================================== */
/* Console driver, if enabled */
/* ======================================================================== */
#ifdef CONFIG_SERIAL_GRLIB_GAISLER_APBUART_CONSOLE
static void apbuart_console_putchar(struct uart_port *port, unsigned char ch)
{
unsigned int status;
do {
status = UART_GET_STATUS(port);
} while (!UART_TX_READY(status));
UART_PUT_CHAR(port, ch);
}
static void
apbuart_console_write(struct console *co, const char *s, unsigned int count)
{
struct uart_port *port = &grlib_apbuart_ports[co->index];
unsigned int status, old_cr, new_cr;
/* First save the CR then disable the interrupts */
old_cr = UART_GET_CTRL(port);
new_cr = old_cr & ~(UART_CTRL_RI | UART_CTRL_TI);
UART_PUT_CTRL(port, new_cr);
uart_console_write(port, s, count, apbuart_console_putchar);
/*
* Finally, wait for transmitter to become empty
* and restore the TCR
*/
do {
status = UART_GET_STATUS(port);
} while (!UART_TX_READY(status));
UART_PUT_CTRL(port, old_cr);
}
static void __init
apbuart_console_get_options(struct uart_port *port, int *baud,
int *parity, int *bits)
{
if (UART_GET_CTRL(port) & (UART_CTRL_RE | UART_CTRL_TE)) {
unsigned int quot, status;
status = UART_GET_STATUS(port);
*parity = 'n';
if (status & UART_CTRL_PE) {
if ((status & UART_CTRL_PS) == 0)
*parity = 'e';
else
*parity = 'o';
}
*bits = 8;
quot = UART_GET_SCAL(port) / 8;
*baud = port->uartclk / (16 * (quot + 1));
}
}
static int __init apbuart_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud = 38400;
int bits = 8;
int parity = 'n';
int flow = 'n';
pr_debug("apbuart_console_setup co=%p, co->index=%i, options=%s\n",
co, co->index, options);
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= grlib_apbuart_port_nr)
co->index = 0;
port = &grlib_apbuart_ports[co->index];
spin_lock_init(&port->lock);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
else
apbuart_console_get_options(port, &baud, &parity, &bits);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver grlib_apbuart_driver;
static struct console grlib_apbuart_console = {
.name = "ttyS",
.write = apbuart_console_write,
.device = uart_console_device,
.setup = apbuart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &grlib_apbuart_driver,
};
static int grlib_apbuart_configure(void);
static int __init apbuart_console_init(void)
{
if (grlib_apbuart_configure())
return -ENODEV;
register_console(&grlib_apbuart_console);
return 0;
}
console_initcall(apbuart_console_init);
#define APBUART_CONSOLE (&grlib_apbuart_console)
#else
#define APBUART_CONSOLE NULL
#endif
static struct uart_driver grlib_apbuart_driver = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = SERIAL_APBUART_MAJOR,
.minor = SERIAL_APBUART_MINOR,
.nr = UART_NR,
.cons = APBUART_CONSOLE,
};
/* ======================================================================== */
/* OF Platform Driver */
/* ======================================================================== */
static int apbuart_probe(struct platform_device *op)
{
int i;
struct uart_port *port = NULL;
for (i = 0; i < grlib_apbuart_port_nr; i++) {
if (op->dev.of_node == grlib_apbuart_nodes[i])
break;
}
port = &grlib_apbuart_ports[i];
port->dev = &op->dev;
port->irq = op->archdata.irqs[0];
uart_add_one_port(&grlib_apbuart_driver, (struct uart_port *) port);
apbuart_flush_fifo((struct uart_port *) port);
printk(KERN_INFO "grlib-apbuart at 0x%llx, irq %d\n",
(unsigned long long) port->mapbase, port->irq);
return 0;
}
static const struct of_device_id apbuart_match[] = {
{
.name = "GAISLER_APBUART",
},
{
.name = "01_00c",
},
{},
};
MODULE_DEVICE_TABLE(of, apbuart_match);
static struct platform_driver grlib_apbuart_of_driver = {
.probe = apbuart_probe,
.driver = {
.name = "grlib-apbuart",
.of_match_table = apbuart_match,
},
};
static int __init grlib_apbuart_configure(void)
{
struct device_node *np;
int line = 0;
for_each_matching_node(np, apbuart_match) {
const int *ampopts;
const u32 *freq_hz;
const struct amba_prom_registers *regs;
struct uart_port *port;
unsigned long addr;
ampopts = of_get_property(np, "ampopts", NULL);
if (ampopts && (*ampopts == 0))
continue; /* Ignore if used by another OS instance */
regs = of_get_property(np, "reg", NULL);
/* Frequency of APB Bus is frequency of UART */
freq_hz = of_get_property(np, "freq", NULL);
if (!regs || !freq_hz || (*freq_hz == 0))
continue;
grlib_apbuart_nodes[line] = np;
addr = regs->phys_addr;
port = &grlib_apbuart_ports[line];
port->mapbase = addr;
port->membase = ioremap(addr, sizeof(struct grlib_apbuart_regs_map));
port->irq = 0;
port->iotype = UPIO_MEM;
port->ops = &grlib_apbuart_ops;
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_GRLIB_GAISLER_APBUART_CONSOLE);
port->flags = UPF_BOOT_AUTOCONF;
port->line = line;
port->uartclk = *freq_hz;
port->fifosize = apbuart_scan_fifo_size((struct uart_port *) port, line);
line++;
/* We support maximum UART_NR uarts ... */
if (line == UART_NR)
break;
}
grlib_apbuart_driver.nr = grlib_apbuart_port_nr = line;
return line ? 0 : -ENODEV;
}
static int __init grlib_apbuart_init(void)
{
int ret;
/* Find all APBUARTS in device the tree and initialize their ports */
ret = grlib_apbuart_configure();
if (ret)
return ret;
printk(KERN_INFO "Serial: GRLIB APBUART driver\n");
ret = uart_register_driver(&grlib_apbuart_driver);
if (ret) {
printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
__FILE__, ret);
return ret;
}
ret = platform_driver_register(&grlib_apbuart_of_driver);
if (ret) {
printk(KERN_ERR
"%s: platform_driver_register failed (%i)\n",
__FILE__, ret);
uart_unregister_driver(&grlib_apbuart_driver);
return ret;
}
return ret;
}
static void __exit grlib_apbuart_exit(void)
{
int i;
for (i = 0; i < grlib_apbuart_port_nr; i++)
uart_remove_one_port(&grlib_apbuart_driver,
&grlib_apbuart_ports[i]);
uart_unregister_driver(&grlib_apbuart_driver);
platform_driver_unregister(&grlib_apbuart_of_driver);
}
module_init(grlib_apbuart_init);
module_exit(grlib_apbuart_exit);
MODULE_AUTHOR("Aeroflex Gaisler AB");
MODULE_DESCRIPTION("GRLIB APBUART serial driver");
MODULE_VERSION("2.1");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/apbuart.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Comtrol RocketPort EXPRESS/INFINITY cards
*
* Copyright (C) 2012 Kevin Cernekee <[email protected]>
*
* Inspired by, and loosely based on:
*
* ar933x_uart.c
* Copyright (C) 2011 Gabor Juhos <[email protected]>
*
* rocketport_infinity_express-linux-1.20.tar.gz
* Copyright (C) 2004-2011 Comtrol, Inc.
*/
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/completion.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/sysrq.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/types.h>
#define DRV_NAME "rp2"
#define RP2_FW_NAME "rp2.fw"
#define RP2_UCODE_BYTES 0x3f
#define PORTS_PER_ASIC 16
#define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
#define UART_CLOCK 44236800
#define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
#define FIFO_SIZE 512
/* BAR0 registers */
#define RP2_FPGA_CTL0 0x110
#define RP2_FPGA_CTL1 0x11c
#define RP2_IRQ_MASK 0x1ec
#define RP2_IRQ_MASK_EN_m BIT(0)
#define RP2_IRQ_STATUS 0x1f0
/* BAR1 registers */
#define RP2_ASIC_SPACING 0x1000
#define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
#define RP2_PORT_BASE 0x000
#define RP2_PORT_SPACING 0x040
#define RP2_UCODE_BASE 0x400
#define RP2_UCODE_SPACING 0x80
#define RP2_CLK_PRESCALER 0xc00
#define RP2_CH_IRQ_STAT 0xc04
#define RP2_CH_IRQ_MASK 0xc08
#define RP2_ASIC_IRQ 0xd00
#define RP2_ASIC_IRQ_EN_m BIT(20)
#define RP2_GLOBAL_CMD 0xd0c
#define RP2_ASIC_CFG 0xd04
/* port registers */
#define RP2_DATA_DWORD 0x000
#define RP2_DATA_BYTE 0x008
#define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
#define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
#define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
#define RP2_DATA_BYTE_BREAK_m BIT(11)
/* This lets uart_insert_char() drop bytes received on a !CREAD port */
#define RP2_DUMMY_READ BIT(16)
#define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
RP2_DATA_BYTE_ERR_OVERRUN_m | \
RP2_DATA_BYTE_ERR_FRAMING_m | \
RP2_DATA_BYTE_BREAK_m)
#define RP2_RX_FIFO_COUNT 0x00c
#define RP2_TX_FIFO_COUNT 0x00e
#define RP2_CHAN_STAT 0x010
#define RP2_CHAN_STAT_RXDATA_m BIT(0)
#define RP2_CHAN_STAT_DCD_m BIT(3)
#define RP2_CHAN_STAT_DSR_m BIT(4)
#define RP2_CHAN_STAT_CTS_m BIT(5)
#define RP2_CHAN_STAT_RI_m BIT(6)
#define RP2_CHAN_STAT_OVERRUN_m BIT(13)
#define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
#define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
#define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
#define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
#define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
#define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
RP2_CHAN_STAT_CTS_CHANGED_m | \
RP2_CHAN_STAT_CD_CHANGED_m | \
RP2_CHAN_STAT_RI_CHANGED_m)
#define RP2_TXRX_CTL 0x014
#define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
#define RP2_TXRX_CTL_RXIRQ_m BIT(2)
#define RP2_TXRX_CTL_RX_TRIG_s 3
#define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_RX_EN_m BIT(5)
#define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
#define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
#define RP2_TXRX_CTL_TX_TRIG_s 16
#define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
#define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
#define RP2_TXRX_CTL_TXIRQ_m BIT(19)
#define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
#define RP2_TXRX_CTL_TX_EN_m BIT(24)
#define RP2_TXRX_CTL_RTS_m BIT(25)
#define RP2_TXRX_CTL_DTR_m BIT(26)
#define RP2_TXRX_CTL_LOOP_m BIT(27)
#define RP2_TXRX_CTL_BREAK_m BIT(28)
#define RP2_TXRX_CTL_CMSPAR_m BIT(29)
#define RP2_TXRX_CTL_nPARODD_m BIT(30)
#define RP2_TXRX_CTL_PARENB_m BIT(31)
#define RP2_UART_CTL 0x018
#define RP2_UART_CTL_MODE_s 0
#define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
#define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
#define RP2_UART_CTL_FLUSH_RX_m BIT(3)
#define RP2_UART_CTL_FLUSH_TX_m BIT(4)
#define RP2_UART_CTL_RESET_CH_m BIT(5)
#define RP2_UART_CTL_XMIT_EN_m BIT(6)
#define RP2_UART_CTL_DATABITS_s 8
#define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
#define RP2_UART_CTL_STOPBITS_m BIT(10)
#define RP2_BAUD 0x01c
/* ucode registers */
#define RP2_TX_SWFLOW 0x02
#define RP2_TX_SWFLOW_ena 0x81
#define RP2_TX_SWFLOW_dis 0x9d
#define RP2_RX_SWFLOW 0x0c
#define RP2_RX_SWFLOW_ena 0x81
#define RP2_RX_SWFLOW_dis 0x8d
#define RP2_RX_FIFO 0x37
#define RP2_RX_FIFO_ena 0x08
#define RP2_RX_FIFO_dis 0x81
static struct uart_driver rp2_uart_driver = {
.owner = THIS_MODULE,
.driver_name = DRV_NAME,
.dev_name = "ttyRP",
.nr = CONFIG_SERIAL_RP2_NR_UARTS,
};
struct rp2_card;
struct rp2_uart_port {
struct uart_port port;
int idx;
int ignore_rx;
struct rp2_card *card;
void __iomem *asic_base;
void __iomem *base;
void __iomem *ucode;
};
struct rp2_card {
struct pci_dev *pdev;
struct rp2_uart_port *ports;
int n_ports;
int initialized_ports;
int minor_start;
int smpte;
void __iomem *bar0;
void __iomem *bar1;
spinlock_t card_lock;
};
#define RP_ID(prod) PCI_VDEVICE(RP, (prod))
#define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
static inline void rp2_decode_cap(const struct pci_device_id *id,
int *ports, int *smpte)
{
*ports = id->driver_data >> 8;
*smpte = id->driver_data & 0xff;
}
static DEFINE_SPINLOCK(rp2_minor_lock);
static int rp2_minor_next;
static int rp2_alloc_ports(int n_ports)
{
int ret = -ENOSPC;
spin_lock(&rp2_minor_lock);
if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
/* sorry, no support for hot unplugging individual cards */
ret = rp2_minor_next;
rp2_minor_next += n_ports;
}
spin_unlock(&rp2_minor_lock);
return ret;
}
static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
{
return container_of(port, struct rp2_uart_port, port);
}
static void rp2_rmw(struct rp2_uart_port *up, int reg,
u32 clr_bits, u32 set_bits)
{
u32 tmp = readl(up->base + reg);
tmp &= ~clr_bits;
tmp |= set_bits;
writel(tmp, up->base + reg);
}
static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
{
rp2_rmw(up, reg, val, 0);
}
static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
{
rp2_rmw(up, reg, 0, val);
}
static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
int is_enabled)
{
unsigned long flags, irq_mask;
spin_lock_irqsave(&up->card->card_lock, flags);
irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
if (is_enabled)
irq_mask &= ~BIT(ch_num);
else
irq_mask |= BIT(ch_num);
writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
spin_unlock_irqrestore(&up->card->card_lock, flags);
}
static unsigned int rp2_uart_tx_empty(struct uart_port *port)
{
struct rp2_uart_port *up = port_to_up(port);
unsigned long tx_fifo_bytes, flags;
/*
* This should probably check the transmitter, not the FIFO.
* But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
* enabled.
*/
spin_lock_irqsave(&up->port.lock, flags);
tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
spin_unlock_irqrestore(&up->port.lock, flags);
return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
}
static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
{
struct rp2_uart_port *up = port_to_up(port);
u32 status;
status = readl(up->base + RP2_CHAN_STAT);
return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
}
static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
}
static void rp2_uart_start_tx(struct uart_port *port)
{
rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
}
static void rp2_uart_stop_tx(struct uart_port *port)
{
rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
}
static void rp2_uart_stop_rx(struct uart_port *port)
{
rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
}
static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
break_state ? RP2_TXRX_CTL_BREAK_m : 0);
spin_unlock_irqrestore(&port->lock, flags);
}
static void rp2_uart_enable_ms(struct uart_port *port)
{
rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
}
static void __rp2_uart_set_termios(struct rp2_uart_port *up,
unsigned long cfl,
unsigned long ifl,
unsigned int baud_div)
{
/* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
writew(baud_div - 1, up->base + RP2_BAUD);
/* data bits and stop bits */
rp2_rmw(up, RP2_UART_CTL,
RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
(((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
(((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
(((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
(((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
/* parity and hardware flow control */
rp2_rmw(up, RP2_TXRX_CTL,
RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
RP2_TXRX_CTL_CTSFLOW_m,
((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
RP2_TXRX_CTL_CTSFLOW_m) : 0));
/* XON/XOFF software flow control */
writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
up->ucode + RP2_TX_SWFLOW);
writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
up->ucode + RP2_RX_SWFLOW);
}
static void rp2_uart_set_termios(struct uart_port *port, struct ktermios *new,
const struct ktermios *old)
{
struct rp2_uart_port *up = port_to_up(port);
unsigned long flags;
unsigned int baud, baud_div;
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
baud_div = uart_get_divisor(port, baud);
if (tty_termios_baud_rate(new))
tty_termios_encode_baud_rate(new, baud, baud);
spin_lock_irqsave(&port->lock, flags);
/* ignore all characters if CREAD is not set */
port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
__rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
uart_update_timeout(port, new->c_cflag, baud);
spin_unlock_irqrestore(&port->lock, flags);
}
static void rp2_rx_chars(struct rp2_uart_port *up)
{
u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
struct tty_port *port = &up->port.state->port;
for (; bytes != 0; bytes--) {
u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
u8 ch = byte & 0xff;
if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
if (!uart_handle_sysrq_char(&up->port, ch))
uart_insert_char(&up->port, byte, 0, ch,
TTY_NORMAL);
} else {
u8 flag = TTY_NORMAL;
if (byte & RP2_DATA_BYTE_BREAK_m)
flag = TTY_BREAK;
else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
flag = TTY_FRAME;
else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
flag = TTY_PARITY;
uart_insert_char(&up->port, byte,
RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
}
up->port.icount.rx++;
}
tty_flip_buffer_push(port);
}
static void rp2_tx_chars(struct rp2_uart_port *up)
{
u8 ch;
uart_port_tx_limited(&up->port, ch,
FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT),
true,
writeb(ch, up->base + RP2_DATA_BYTE),
({}));
}
static void rp2_ch_interrupt(struct rp2_uart_port *up)
{
u32 status;
spin_lock(&up->port.lock);
/*
* The IRQ status bits are clear-on-write. Other status bits in
* this register aren't, so it's harmless to write to them.
*/
status = readl(up->base + RP2_CHAN_STAT);
writel(status, up->base + RP2_CHAN_STAT);
if (status & RP2_CHAN_STAT_RXDATA_m)
rp2_rx_chars(up);
if (status & RP2_CHAN_STAT_TXEMPTY_m)
rp2_tx_chars(up);
if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
spin_unlock(&up->port.lock);
}
static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
{
void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
int ch, handled = 0;
unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
~readl(base + RP2_CH_IRQ_MASK);
for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
rp2_ch_interrupt(&card->ports[ch]);
handled++;
}
return handled;
}
static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
{
struct rp2_card *card = dev_id;
int handled;
handled = rp2_asic_interrupt(card, 0);
if (card->n_ports >= PORTS_PER_ASIC)
handled += rp2_asic_interrupt(card, 1);
return handled ? IRQ_HANDLED : IRQ_NONE;
}
static inline void rp2_flush_fifos(struct rp2_uart_port *up)
{
rp2_rmw_set(up, RP2_UART_CTL,
RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
readl(up->base + RP2_UART_CTL);
udelay(10);
rp2_rmw_clr(up, RP2_UART_CTL,
RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
}
static int rp2_uart_startup(struct uart_port *port)
{
struct rp2_uart_port *up = port_to_up(port);
rp2_flush_fifos(up);
rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
RP2_TXRX_CTL_RX_TRIG_1);
rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
rp2_mask_ch_irq(up, up->idx, 1);
return 0;
}
static void rp2_uart_shutdown(struct uart_port *port)
{
struct rp2_uart_port *up = port_to_up(port);
unsigned long flags;
rp2_uart_break_ctl(port, 0);
spin_lock_irqsave(&port->lock, flags);
rp2_mask_ch_irq(up, up->idx, 0);
rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *rp2_uart_type(struct uart_port *port)
{
return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
}
static void rp2_uart_release_port(struct uart_port *port)
{
/* Nothing to release ... */
}
static int rp2_uart_request_port(struct uart_port *port)
{
/* UARTs always present */
return 0;
}
static void rp2_uart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_RP2;
}
static int rp2_uart_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
return -EINVAL;
return 0;
}
static const struct uart_ops rp2_uart_ops = {
.tx_empty = rp2_uart_tx_empty,
.set_mctrl = rp2_uart_set_mctrl,
.get_mctrl = rp2_uart_get_mctrl,
.stop_tx = rp2_uart_stop_tx,
.start_tx = rp2_uart_start_tx,
.stop_rx = rp2_uart_stop_rx,
.enable_ms = rp2_uart_enable_ms,
.break_ctl = rp2_uart_break_ctl,
.startup = rp2_uart_startup,
.shutdown = rp2_uart_shutdown,
.set_termios = rp2_uart_set_termios,
.type = rp2_uart_type,
.release_port = rp2_uart_release_port,
.request_port = rp2_uart_request_port,
.config_port = rp2_uart_config_port,
.verify_port = rp2_uart_verify_port,
};
static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
{
void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
u32 clk_cfg;
writew(1, base + RP2_GLOBAL_CMD);
readw(base + RP2_GLOBAL_CMD);
msleep(100);
writel(0, base + RP2_CLK_PRESCALER);
/* TDM clock configuration */
clk_cfg = readw(base + RP2_ASIC_CFG);
clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
writew(clk_cfg, base + RP2_ASIC_CFG);
/* IRQ routing */
writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
}
static void rp2_init_card(struct rp2_card *card)
{
writel(4, card->bar0 + RP2_FPGA_CTL0);
writel(0, card->bar0 + RP2_FPGA_CTL1);
rp2_reset_asic(card, 0);
if (card->n_ports >= PORTS_PER_ASIC)
rp2_reset_asic(card, 1);
writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
}
static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
{
int i;
writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
readl(up->base + RP2_UART_CTL);
udelay(1);
writel(0, up->base + RP2_TXRX_CTL);
writel(0, up->base + RP2_UART_CTL);
readl(up->base + RP2_UART_CTL);
udelay(1);
rp2_flush_fifos(up);
for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
writeb(fw->data[i], up->ucode + i);
__rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
rp2_uart_set_mctrl(&up->port, 0);
writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
rp2_rmw_set(up, RP2_TXRX_CTL,
RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
}
static void rp2_remove_ports(struct rp2_card *card)
{
int i;
for (i = 0; i < card->initialized_ports; i++)
uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
card->initialized_ports = 0;
}
static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
{
resource_size_t phys_base;
int i, rc = 0;
phys_base = pci_resource_start(card->pdev, 1);
for (i = 0; i < card->n_ports; i++) {
struct rp2_uart_port *rp = &card->ports[i];
struct uart_port *p;
int j = (unsigned)i % PORTS_PER_ASIC;
rp->asic_base = card->bar1;
rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
rp->card = card;
rp->idx = j;
p = &rp->port;
p->line = card->minor_start + i;
p->dev = &card->pdev->dev;
p->type = PORT_RP2;
p->iotype = UPIO_MEM32;
p->uartclk = UART_CLOCK;
p->regshift = 2;
p->fifosize = FIFO_SIZE;
p->ops = &rp2_uart_ops;
p->irq = card->pdev->irq;
p->membase = rp->base;
p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
if (i >= PORTS_PER_ASIC) {
rp->asic_base += RP2_ASIC_SPACING;
rp->base += RP2_ASIC_SPACING;
rp->ucode += RP2_ASIC_SPACING;
p->mapbase += RP2_ASIC_SPACING;
}
rp2_init_port(rp, fw);
rc = uart_add_one_port(&rp2_uart_driver, p);
if (rc) {
dev_err(&card->pdev->dev,
"error registering port %d: %d\n", i, rc);
rp2_remove_ports(card);
break;
}
card->initialized_ports++;
}
return rc;
}
static int rp2_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
const struct firmware *fw;
struct rp2_card *card;
struct rp2_uart_port *ports;
void __iomem * const *bars;
int rc;
card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
pci_set_drvdata(pdev, card);
spin_lock_init(&card->card_lock);
rc = pcim_enable_device(pdev);
if (rc)
return rc;
rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
if (rc)
return rc;
bars = pcim_iomap_table(pdev);
card->bar0 = bars[0];
card->bar1 = bars[1];
card->pdev = pdev;
rp2_decode_cap(id, &card->n_ports, &card->smpte);
dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
card->minor_start = rp2_alloc_ports(card->n_ports);
if (card->minor_start < 0) {
dev_err(&pdev->dev,
"too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
return -EINVAL;
}
rp2_init_card(card);
ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
GFP_KERNEL);
if (!ports)
return -ENOMEM;
card->ports = ports;
rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);
if (rc < 0) {
dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
RP2_FW_NAME);
return rc;
}
rc = rp2_load_firmware(card, fw);
release_firmware(fw);
if (rc < 0)
return rc;
rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
IRQF_SHARED, DRV_NAME, card);
if (rc)
return rc;
return 0;
}
static void rp2_remove(struct pci_dev *pdev)
{
struct rp2_card *card = pci_get_drvdata(pdev);
rp2_remove_ports(card);
}
static const struct pci_device_id rp2_pci_tbl[] = {
/* RocketPort INFINITY cards */
{ RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
{ RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
{ RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
{ RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
{ RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
{ RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
{ RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
{ RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
{ RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
{ RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
{ RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
{ RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
{ RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
{ RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
{ RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
{ RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
{ RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
/* RocketPort EXPRESS cards */
{ RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
{ RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
{ RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
{ RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
{ RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
{ RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
{ RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
{ RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
{ RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
{ RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
{ }
};
MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
static struct pci_driver rp2_pci_driver = {
.name = DRV_NAME,
.id_table = rp2_pci_tbl,
.probe = rp2_probe,
.remove = rp2_remove,
};
static int __init rp2_uart_init(void)
{
int rc;
rc = uart_register_driver(&rp2_uart_driver);
if (rc)
return rc;
rc = pci_register_driver(&rp2_pci_driver);
if (rc) {
uart_unregister_driver(&rp2_uart_driver);
return rc;
}
return 0;
}
static void __exit rp2_uart_exit(void)
{
pci_unregister_driver(&rp2_pci_driver);
uart_unregister_driver(&rp2_uart_driver);
}
module_init(rp2_uart_init);
module_exit(rp2_uart_exit);
MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
MODULE_AUTHOR("Kevin Cernekee <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_FIRMWARE(RP2_FW_NAME);
| linux-master | drivers/tty/serial/rp2.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale lpuart serial port driver
*
* Copyright 2012-2014 Freescale Semiconductor, Inc.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/dmapool.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_dma.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/tty_flip.h>
/* All registers are 8-bit width */
#define UARTBDH 0x00
#define UARTBDL 0x01
#define UARTCR1 0x02
#define UARTCR2 0x03
#define UARTSR1 0x04
#define UARTCR3 0x06
#define UARTDR 0x07
#define UARTCR4 0x0a
#define UARTCR5 0x0b
#define UARTMODEM 0x0d
#define UARTPFIFO 0x10
#define UARTCFIFO 0x11
#define UARTSFIFO 0x12
#define UARTTWFIFO 0x13
#define UARTTCFIFO 0x14
#define UARTRWFIFO 0x15
#define UARTBDH_LBKDIE 0x80
#define UARTBDH_RXEDGIE 0x40
#define UARTBDH_SBR_MASK 0x1f
#define UARTCR1_LOOPS 0x80
#define UARTCR1_RSRC 0x20
#define UARTCR1_M 0x10
#define UARTCR1_WAKE 0x08
#define UARTCR1_ILT 0x04
#define UARTCR1_PE 0x02
#define UARTCR1_PT 0x01
#define UARTCR2_TIE 0x80
#define UARTCR2_TCIE 0x40
#define UARTCR2_RIE 0x20
#define UARTCR2_ILIE 0x10
#define UARTCR2_TE 0x08
#define UARTCR2_RE 0x04
#define UARTCR2_RWU 0x02
#define UARTCR2_SBK 0x01
#define UARTSR1_TDRE 0x80
#define UARTSR1_TC 0x40
#define UARTSR1_RDRF 0x20
#define UARTSR1_IDLE 0x10
#define UARTSR1_OR 0x08
#define UARTSR1_NF 0x04
#define UARTSR1_FE 0x02
#define UARTSR1_PE 0x01
#define UARTCR3_R8 0x80
#define UARTCR3_T8 0x40
#define UARTCR3_TXDIR 0x20
#define UARTCR3_TXINV 0x10
#define UARTCR3_ORIE 0x08
#define UARTCR3_NEIE 0x04
#define UARTCR3_FEIE 0x02
#define UARTCR3_PEIE 0x01
#define UARTCR4_MAEN1 0x80
#define UARTCR4_MAEN2 0x40
#define UARTCR4_M10 0x20
#define UARTCR4_BRFA_MASK 0x1f
#define UARTCR4_BRFA_OFF 0
#define UARTCR5_TDMAS 0x80
#define UARTCR5_RDMAS 0x20
#define UARTMODEM_RXRTSE 0x08
#define UARTMODEM_TXRTSPOL 0x04
#define UARTMODEM_TXRTSE 0x02
#define UARTMODEM_TXCTSE 0x01
#define UARTPFIFO_TXFE 0x80
#define UARTPFIFO_FIFOSIZE_MASK 0x7
#define UARTPFIFO_TXSIZE_OFF 4
#define UARTPFIFO_RXFE 0x08
#define UARTPFIFO_RXSIZE_OFF 0
#define UARTCFIFO_TXFLUSH 0x80
#define UARTCFIFO_RXFLUSH 0x40
#define UARTCFIFO_RXOFE 0x04
#define UARTCFIFO_TXOFE 0x02
#define UARTCFIFO_RXUFE 0x01
#define UARTSFIFO_TXEMPT 0x80
#define UARTSFIFO_RXEMPT 0x40
#define UARTSFIFO_RXOF 0x04
#define UARTSFIFO_TXOF 0x02
#define UARTSFIFO_RXUF 0x01
/* 32-bit global registers only for i.MX7ULP/i.MX8x
* Used to reset all internal logic and registers, except the Global Register.
*/
#define UART_GLOBAL 0x8
/* 32-bit register definition */
#define UARTBAUD 0x00
#define UARTSTAT 0x04
#define UARTCTRL 0x08
#define UARTDATA 0x0C
#define UARTMATCH 0x10
#define UARTMODIR 0x14
#define UARTFIFO 0x18
#define UARTWATER 0x1c
#define UARTBAUD_MAEN1 0x80000000
#define UARTBAUD_MAEN2 0x40000000
#define UARTBAUD_M10 0x20000000
#define UARTBAUD_TDMAE 0x00800000
#define UARTBAUD_RDMAE 0x00200000
#define UARTBAUD_MATCFG 0x00400000
#define UARTBAUD_BOTHEDGE 0x00020000
#define UARTBAUD_RESYNCDIS 0x00010000
#define UARTBAUD_LBKDIE 0x00008000
#define UARTBAUD_RXEDGIE 0x00004000
#define UARTBAUD_SBNS 0x00002000
#define UARTBAUD_SBR 0x00000000
#define UARTBAUD_SBR_MASK 0x1fff
#define UARTBAUD_OSR_MASK 0x1f
#define UARTBAUD_OSR_SHIFT 24
#define UARTSTAT_LBKDIF 0x80000000
#define UARTSTAT_RXEDGIF 0x40000000
#define UARTSTAT_MSBF 0x20000000
#define UARTSTAT_RXINV 0x10000000
#define UARTSTAT_RWUID 0x08000000
#define UARTSTAT_BRK13 0x04000000
#define UARTSTAT_LBKDE 0x02000000
#define UARTSTAT_RAF 0x01000000
#define UARTSTAT_TDRE 0x00800000
#define UARTSTAT_TC 0x00400000
#define UARTSTAT_RDRF 0x00200000
#define UARTSTAT_IDLE 0x00100000
#define UARTSTAT_OR 0x00080000
#define UARTSTAT_NF 0x00040000
#define UARTSTAT_FE 0x00020000
#define UARTSTAT_PE 0x00010000
#define UARTSTAT_MA1F 0x00008000
#define UARTSTAT_M21F 0x00004000
#define UARTCTRL_R8T9 0x80000000
#define UARTCTRL_R9T8 0x40000000
#define UARTCTRL_TXDIR 0x20000000
#define UARTCTRL_TXINV 0x10000000
#define UARTCTRL_ORIE 0x08000000
#define UARTCTRL_NEIE 0x04000000
#define UARTCTRL_FEIE 0x02000000
#define UARTCTRL_PEIE 0x01000000
#define UARTCTRL_TIE 0x00800000
#define UARTCTRL_TCIE 0x00400000
#define UARTCTRL_RIE 0x00200000
#define UARTCTRL_ILIE 0x00100000
#define UARTCTRL_TE 0x00080000
#define UARTCTRL_RE 0x00040000
#define UARTCTRL_RWU 0x00020000
#define UARTCTRL_SBK 0x00010000
#define UARTCTRL_MA1IE 0x00008000
#define UARTCTRL_MA2IE 0x00004000
#define UARTCTRL_IDLECFG GENMASK(10, 8)
#define UARTCTRL_LOOPS 0x00000080
#define UARTCTRL_DOZEEN 0x00000040
#define UARTCTRL_RSRC 0x00000020
#define UARTCTRL_M 0x00000010
#define UARTCTRL_WAKE 0x00000008
#define UARTCTRL_ILT 0x00000004
#define UARTCTRL_PE 0x00000002
#define UARTCTRL_PT 0x00000001
#define UARTDATA_NOISY 0x00008000
#define UARTDATA_PARITYE 0x00004000
#define UARTDATA_FRETSC 0x00002000
#define UARTDATA_RXEMPT 0x00001000
#define UARTDATA_IDLINE 0x00000800
#define UARTDATA_MASK 0x3ff
#define UARTMODIR_IREN 0x00020000
#define UARTMODIR_RTSWATER GENMASK(10, 8)
#define UARTMODIR_TXCTSSRC 0x00000020
#define UARTMODIR_TXCTSC 0x00000010
#define UARTMODIR_RXRTSE 0x00000008
#define UARTMODIR_TXRTSPOL 0x00000004
#define UARTMODIR_TXRTSE 0x00000002
#define UARTMODIR_TXCTSE 0x00000001
#define UARTFIFO_TXEMPT 0x00800000
#define UARTFIFO_RXEMPT 0x00400000
#define UARTFIFO_TXOF 0x00020000
#define UARTFIFO_RXUF 0x00010000
#define UARTFIFO_TXFLUSH 0x00008000
#define UARTFIFO_RXFLUSH 0x00004000
#define UARTFIFO_RXIDEN GENMASK(12, 10)
#define UARTFIFO_TXOFE 0x00000200
#define UARTFIFO_RXUFE 0x00000100
#define UARTFIFO_TXFE 0x00000080
#define UARTFIFO_FIFOSIZE_MASK 0x7
#define UARTFIFO_TXSIZE_OFF 4
#define UARTFIFO_RXFE 0x00000008
#define UARTFIFO_RXSIZE_OFF 0
#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
#define UARTWATER_COUNT_MASK 0xff
#define UARTWATER_TXCNT_OFF 8
#define UARTWATER_RXCNT_OFF 24
#define UARTWATER_WATER_MASK 0xff
#define UARTWATER_TXWATER_OFF 0
#define UARTWATER_RXWATER_OFF 16
#define UART_GLOBAL_RST 0x2
#define GLOBAL_RST_MIN_US 20
#define GLOBAL_RST_MAX_US 40
/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
#define DMA_RX_TIMEOUT (10)
#define DMA_RX_IDLE_CHARS 8
#define UART_AUTOSUSPEND_TIMEOUT 3000
#define DRIVER_NAME "fsl-lpuart"
#define DEV_NAME "ttyLP"
#define UART_NR 8
/* IMX lpuart has four extra unused regs located at the beginning */
#define IMX_REG_OFF 0x10
enum lpuart_type {
VF610_LPUART,
LS1021A_LPUART,
LS1028A_LPUART,
IMX7ULP_LPUART,
IMX8ULP_LPUART,
IMX8QXP_LPUART,
IMXRT1050_LPUART,
};
struct lpuart_port {
struct uart_port port;
enum lpuart_type devtype;
struct clk *ipg_clk;
struct clk *baud_clk;
unsigned int txfifo_size;
unsigned int rxfifo_size;
u8 rx_watermark;
bool lpuart_dma_tx_use;
bool lpuart_dma_rx_use;
struct dma_chan *dma_tx_chan;
struct dma_chan *dma_rx_chan;
struct dma_async_tx_descriptor *dma_tx_desc;
struct dma_async_tx_descriptor *dma_rx_desc;
dma_cookie_t dma_tx_cookie;
dma_cookie_t dma_rx_cookie;
unsigned int dma_tx_bytes;
unsigned int dma_rx_bytes;
bool dma_tx_in_progress;
unsigned int dma_rx_timeout;
struct timer_list lpuart_timer;
struct scatterlist rx_sgl, tx_sgl[2];
struct circ_buf rx_ring;
int rx_dma_rng_buf_len;
int last_residue;
unsigned int dma_tx_nents;
wait_queue_head_t dma_wait;
bool is_cs7; /* Set to true when character size is 7 */
/* and the parity is enabled */
bool dma_idle_int;
};
struct lpuart_soc_data {
enum lpuart_type devtype;
char iotype;
u8 reg_off;
u8 rx_watermark;
};
static const struct lpuart_soc_data vf_data = {
.devtype = VF610_LPUART,
.iotype = UPIO_MEM,
.rx_watermark = 1,
};
static const struct lpuart_soc_data ls1021a_data = {
.devtype = LS1021A_LPUART,
.iotype = UPIO_MEM32BE,
.rx_watermark = 1,
};
static const struct lpuart_soc_data ls1028a_data = {
.devtype = LS1028A_LPUART,
.iotype = UPIO_MEM32,
.rx_watermark = 0,
};
static struct lpuart_soc_data imx7ulp_data = {
.devtype = IMX7ULP_LPUART,
.iotype = UPIO_MEM32,
.reg_off = IMX_REG_OFF,
.rx_watermark = 1,
};
static struct lpuart_soc_data imx8ulp_data = {
.devtype = IMX8ULP_LPUART,
.iotype = UPIO_MEM32,
.reg_off = IMX_REG_OFF,
.rx_watermark = 3,
};
static struct lpuart_soc_data imx8qxp_data = {
.devtype = IMX8QXP_LPUART,
.iotype = UPIO_MEM32,
.reg_off = IMX_REG_OFF,
.rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
};
static struct lpuart_soc_data imxrt1050_data = {
.devtype = IMXRT1050_LPUART,
.iotype = UPIO_MEM32,
.reg_off = IMX_REG_OFF,
.rx_watermark = 1,
};
static const struct of_device_id lpuart_dt_ids[] = {
{ .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
{ .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
{ .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
{ .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
{ .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, },
{ .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
{ .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
/* Forward declare this for the dma callbacks*/
static void lpuart_dma_tx_complete(void *arg);
static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
{
return (sport->devtype == LS1021A_LPUART ||
sport->devtype == LS1028A_LPUART);
}
static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
{
return sport->devtype == IMX7ULP_LPUART;
}
static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
{
return sport->devtype == IMX8ULP_LPUART;
}
static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
{
return sport->devtype == IMX8QXP_LPUART;
}
static inline u32 lpuart32_read(struct uart_port *port, u32 off)
{
switch (port->iotype) {
case UPIO_MEM32:
return readl(port->membase + off);
case UPIO_MEM32BE:
return ioread32be(port->membase + off);
default:
return 0;
}
}
static inline void lpuart32_write(struct uart_port *port, u32 val,
u32 off)
{
switch (port->iotype) {
case UPIO_MEM32:
writel(val, port->membase + off);
break;
case UPIO_MEM32BE:
iowrite32be(val, port->membase + off);
break;
}
}
static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
{
int ret = 0;
if (is_en) {
ret = clk_prepare_enable(sport->ipg_clk);
if (ret)
return ret;
ret = clk_prepare_enable(sport->baud_clk);
if (ret) {
clk_disable_unprepare(sport->ipg_clk);
return ret;
}
} else {
clk_disable_unprepare(sport->baud_clk);
clk_disable_unprepare(sport->ipg_clk);
}
return 0;
}
static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
{
if (is_imx8qxp_lpuart(sport))
return clk_get_rate(sport->baud_clk);
return clk_get_rate(sport->ipg_clk);
}
#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
static void lpuart_stop_tx(struct uart_port *port)
{
unsigned char temp;
temp = readb(port->membase + UARTCR2);
temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
writeb(temp, port->membase + UARTCR2);
}
static void lpuart32_stop_tx(struct uart_port *port)
{
unsigned long temp;
temp = lpuart32_read(port, UARTCTRL);
temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
lpuart32_write(port, temp, UARTCTRL);
}
static void lpuart_stop_rx(struct uart_port *port)
{
unsigned char temp;
temp = readb(port->membase + UARTCR2);
writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
}
static void lpuart32_stop_rx(struct uart_port *port)
{
unsigned long temp;
temp = lpuart32_read(port, UARTCTRL);
lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
}
static void lpuart_dma_tx(struct lpuart_port *sport)
{
struct circ_buf *xmit = &sport->port.state->xmit;
struct scatterlist *sgl = sport->tx_sgl;
struct device *dev = sport->port.dev;
struct dma_chan *chan = sport->dma_tx_chan;
int ret;
if (sport->dma_tx_in_progress)
return;
sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
if (xmit->tail < xmit->head || xmit->head == 0) {
sport->dma_tx_nents = 1;
sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
} else {
sport->dma_tx_nents = 2;
sg_init_table(sgl, 2);
sg_set_buf(sgl, xmit->buf + xmit->tail,
UART_XMIT_SIZE - xmit->tail);
sg_set_buf(sgl + 1, xmit->buf, xmit->head);
}
ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
DMA_TO_DEVICE);
if (!ret) {
dev_err(dev, "DMA mapping error for TX.\n");
return;
}
sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
ret, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT);
if (!sport->dma_tx_desc) {
dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
DMA_TO_DEVICE);
dev_err(dev, "Cannot prepare TX slave DMA!\n");
return;
}
sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
sport->dma_tx_desc->callback_param = sport;
sport->dma_tx_in_progress = true;
sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
dma_async_issue_pending(chan);
}
static bool lpuart_stopped_or_empty(struct uart_port *port)
{
return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
}
static void lpuart_dma_tx_complete(void *arg)
{
struct lpuart_port *sport = arg;
struct scatterlist *sgl = &sport->tx_sgl[0];
struct circ_buf *xmit = &sport->port.state->xmit;
struct dma_chan *chan = sport->dma_tx_chan;
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
if (!sport->dma_tx_in_progress) {
spin_unlock_irqrestore(&sport->port.lock, flags);
return;
}
dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
DMA_TO_DEVICE);
uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
sport->dma_tx_in_progress = false;
spin_unlock_irqrestore(&sport->port.lock, flags);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&sport->port);
if (waitqueue_active(&sport->dma_wait)) {
wake_up(&sport->dma_wait);
return;
}
spin_lock_irqsave(&sport->port.lock, flags);
if (!lpuart_stopped_or_empty(&sport->port))
lpuart_dma_tx(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
}
static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
{
switch (sport->port.iotype) {
case UPIO_MEM32:
return sport->port.mapbase + UARTDATA;
case UPIO_MEM32BE:
return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
}
return sport->port.mapbase + UARTDR;
}
static int lpuart_dma_tx_request(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
struct dma_slave_config dma_tx_sconfig = {};
int ret;
dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dma_tx_sconfig.dst_maxburst = 1;
dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
if (ret) {
dev_err(sport->port.dev,
"DMA slave config failed, err = %d\n", ret);
return ret;
}
return 0;
}
static bool lpuart_is_32(struct lpuart_port *sport)
{
return sport->port.iotype == UPIO_MEM32 ||
sport->port.iotype == UPIO_MEM32BE;
}
static void lpuart_flush_buffer(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
struct dma_chan *chan = sport->dma_tx_chan;
u32 val;
if (sport->lpuart_dma_tx_use) {
if (sport->dma_tx_in_progress) {
dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
sport->dma_tx_nents, DMA_TO_DEVICE);
sport->dma_tx_in_progress = false;
}
dmaengine_terminate_async(chan);
}
if (lpuart_is_32(sport)) {
val = lpuart32_read(&sport->port, UARTFIFO);
val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
lpuart32_write(&sport->port, val, UARTFIFO);
} else {
val = readb(sport->port.membase + UARTCFIFO);
val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
writeb(val, sport->port.membase + UARTCFIFO);
}
}
static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
u8 bit)
{
while (!(readb(port->membase + offset) & bit))
cpu_relax();
}
static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
u32 bit)
{
while (!(lpuart32_read(port, offset) & bit))
cpu_relax();
}
#if defined(CONFIG_CONSOLE_POLL)
static int lpuart_poll_init(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
unsigned long flags;
unsigned char temp;
sport->port.fifosize = 0;
spin_lock_irqsave(&sport->port.lock, flags);
/* Disable Rx & Tx */
writeb(0, sport->port.membase + UARTCR2);
temp = readb(sport->port.membase + UARTPFIFO);
/* Enable Rx and Tx FIFO */
writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
sport->port.membase + UARTPFIFO);
/* flush Tx and Rx FIFO */
writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
sport->port.membase + UARTCFIFO);
/* explicitly clear RDRF */
if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
readb(sport->port.membase + UARTDR);
writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
}
writeb(0, sport->port.membase + UARTTWFIFO);
writeb(1, sport->port.membase + UARTRWFIFO);
/* Enable Rx and Tx */
writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
spin_unlock_irqrestore(&sport->port.lock, flags);
return 0;
}
static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
{
/* drain */
lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
writeb(c, port->membase + UARTDR);
}
static int lpuart_poll_get_char(struct uart_port *port)
{
if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
return NO_POLL_CHAR;
return readb(port->membase + UARTDR);
}
static int lpuart32_poll_init(struct uart_port *port)
{
unsigned long flags;
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
u32 temp;
sport->port.fifosize = 0;
spin_lock_irqsave(&sport->port.lock, flags);
/* Disable Rx & Tx */
lpuart32_write(&sport->port, 0, UARTCTRL);
temp = lpuart32_read(&sport->port, UARTFIFO);
/* Enable Rx and Tx FIFO */
lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
/* flush Tx and Rx FIFO */
lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
/* explicitly clear RDRF */
if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
lpuart32_read(&sport->port, UARTDATA);
lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
}
/* Enable Rx and Tx */
lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
spin_unlock_irqrestore(&sport->port.lock, flags);
return 0;
}
static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
{
lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
lpuart32_write(port, c, UARTDATA);
}
static int lpuart32_poll_get_char(struct uart_port *port)
{
if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
return NO_POLL_CHAR;
return lpuart32_read(port, UARTDATA);
}
#endif
static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
{
struct uart_port *port = &sport->port;
u8 ch;
uart_port_tx(port, ch,
readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
writeb(ch, port->membase + UARTDR));
}
static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
{
struct circ_buf *xmit = &sport->port.state->xmit;
unsigned long txcnt;
if (sport->port.x_char) {
lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
sport->port.icount.tx++;
sport->port.x_char = 0;
return;
}
if (lpuart_stopped_or_empty(&sport->port)) {
lpuart32_stop_tx(&sport->port);
return;
}
txcnt = lpuart32_read(&sport->port, UARTWATER);
txcnt = txcnt >> UARTWATER_TXCNT_OFF;
txcnt &= UARTWATER_COUNT_MASK;
while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
uart_xmit_advance(&sport->port, 1);
txcnt = lpuart32_read(&sport->port, UARTWATER);
txcnt = txcnt >> UARTWATER_TXCNT_OFF;
txcnt &= UARTWATER_COUNT_MASK;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&sport->port);
if (uart_circ_empty(xmit))
lpuart32_stop_tx(&sport->port);
}
static void lpuart_start_tx(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
unsigned char temp;
temp = readb(port->membase + UARTCR2);
writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
if (sport->lpuart_dma_tx_use) {
if (!lpuart_stopped_or_empty(port))
lpuart_dma_tx(sport);
} else {
if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
lpuart_transmit_buffer(sport);
}
}
static void lpuart32_start_tx(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned long temp;
if (sport->lpuart_dma_tx_use) {
if (!lpuart_stopped_or_empty(port))
lpuart_dma_tx(sport);
} else {
temp = lpuart32_read(port, UARTCTRL);
lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
lpuart32_transmit_buffer(sport);
}
}
static void
lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
{
switch (state) {
case UART_PM_STATE_OFF:
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
break;
default:
pm_runtime_get_sync(port->dev);
break;
}
}
/* return TIOCSER_TEMT when transmitter is not busy */
static unsigned int lpuart_tx_empty(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
unsigned char sr1 = readb(port->membase + UARTSR1);
unsigned char sfifo = readb(port->membase + UARTSFIFO);
if (sport->dma_tx_in_progress)
return 0;
if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
return TIOCSER_TEMT;
return 0;
}
static unsigned int lpuart32_tx_empty(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
unsigned long stat = lpuart32_read(port, UARTSTAT);
unsigned long sfifo = lpuart32_read(port, UARTFIFO);
unsigned long ctrl = lpuart32_read(port, UARTCTRL);
if (sport->dma_tx_in_progress)
return 0;
/*
* LPUART Transmission Complete Flag may never be set while queuing a break
* character, so avoid checking for transmission complete when UARTCTRL_SBK
* is asserted.
*/
if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
return TIOCSER_TEMT;
return 0;
}
static void lpuart_txint(struct lpuart_port *sport)
{
spin_lock(&sport->port.lock);
lpuart_transmit_buffer(sport);
spin_unlock(&sport->port.lock);
}
static void lpuart_rxint(struct lpuart_port *sport)
{
unsigned int flg, ignored = 0, overrun = 0;
struct tty_port *port = &sport->port.state->port;
unsigned char rx, sr;
spin_lock(&sport->port.lock);
while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
flg = TTY_NORMAL;
sport->port.icount.rx++;
/*
* to clear the FE, OR, NF, FE, PE flags,
* read SR1 then read DR
*/
sr = readb(sport->port.membase + UARTSR1);
rx = readb(sport->port.membase + UARTDR);
if (uart_prepare_sysrq_char(&sport->port, rx))
continue;
if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
if (sr & UARTSR1_PE)
sport->port.icount.parity++;
else if (sr & UARTSR1_FE)
sport->port.icount.frame++;
if (sr & UARTSR1_OR)
overrun++;
if (sr & sport->port.ignore_status_mask) {
if (++ignored > 100)
goto out;
continue;
}
sr &= sport->port.read_status_mask;
if (sr & UARTSR1_PE)
flg = TTY_PARITY;
else if (sr & UARTSR1_FE)
flg = TTY_FRAME;
if (sr & UARTSR1_OR)
flg = TTY_OVERRUN;
sport->port.sysrq = 0;
}
if (tty_insert_flip_char(port, rx, flg) == 0)
sport->port.icount.buf_overrun++;
}
out:
if (overrun) {
sport->port.icount.overrun += overrun;
/*
* Overruns cause FIFO pointers to become missaligned.
* Flushing the receive FIFO reinitializes the pointers.
*/
writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
}
uart_unlock_and_check_sysrq(&sport->port);
tty_flip_buffer_push(port);
}
static void lpuart32_txint(struct lpuart_port *sport)
{
spin_lock(&sport->port.lock);
lpuart32_transmit_buffer(sport);
spin_unlock(&sport->port.lock);
}
static void lpuart32_rxint(struct lpuart_port *sport)
{
unsigned int flg, ignored = 0;
struct tty_port *port = &sport->port.state->port;
unsigned long rx, sr;
bool is_break;
spin_lock(&sport->port.lock);
while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
flg = TTY_NORMAL;
sport->port.icount.rx++;
/*
* to clear the FE, OR, NF, FE, PE flags,
* read STAT then read DATA reg
*/
sr = lpuart32_read(&sport->port, UARTSTAT);
rx = lpuart32_read(&sport->port, UARTDATA);
rx &= UARTDATA_MASK;
/*
* The LPUART can't distinguish between a break and a framing error,
* thus we assume it is a break if the received data is zero.
*/
is_break = (sr & UARTSTAT_FE) && !rx;
if (is_break && uart_handle_break(&sport->port))
continue;
if (uart_prepare_sysrq_char(&sport->port, rx))
continue;
if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
if (sr & UARTSTAT_PE) {
sport->port.icount.parity++;
} else if (sr & UARTSTAT_FE) {
if (is_break)
sport->port.icount.brk++;
else
sport->port.icount.frame++;
}
if (sr & UARTSTAT_OR)
sport->port.icount.overrun++;
if (sr & sport->port.ignore_status_mask) {
if (++ignored > 100)
goto out;
continue;
}
sr &= sport->port.read_status_mask;
if (sr & UARTSTAT_PE) {
flg = TTY_PARITY;
} else if (sr & UARTSTAT_FE) {
if (is_break)
flg = TTY_BREAK;
else
flg = TTY_FRAME;
}
if (sr & UARTSTAT_OR)
flg = TTY_OVERRUN;
}
if (sport->is_cs7)
rx &= 0x7F;
if (tty_insert_flip_char(port, rx, flg) == 0)
sport->port.icount.buf_overrun++;
}
out:
uart_unlock_and_check_sysrq(&sport->port);
tty_flip_buffer_push(port);
}
static irqreturn_t lpuart_int(int irq, void *dev_id)
{
struct lpuart_port *sport = dev_id;
unsigned char sts;
sts = readb(sport->port.membase + UARTSR1);
/* SysRq, using dma, check for linebreak by framing err. */
if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
readb(sport->port.membase + UARTDR);
uart_handle_break(&sport->port);
/* linebreak produces some garbage, removing it */
writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
return IRQ_HANDLED;
}
if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
lpuart_rxint(sport);
if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
lpuart_txint(sport);
return IRQ_HANDLED;
}
static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
unsigned char *p, int count)
{
while (count--) {
if (*p && uart_handle_sysrq_char(port, *p))
return;
p++;
}
}
static void lpuart_handle_sysrq(struct lpuart_port *sport)
{
struct circ_buf *ring = &sport->rx_ring;
int count;
if (ring->head < ring->tail) {
count = sport->rx_sgl.length - ring->tail;
lpuart_handle_sysrq_chars(&sport->port,
ring->buf + ring->tail, count);
ring->tail = 0;
}
if (ring->head > ring->tail) {
count = ring->head - ring->tail;
lpuart_handle_sysrq_chars(&sport->port,
ring->buf + ring->tail, count);
ring->tail = ring->head;
}
}
static int lpuart_tty_insert_flip_string(struct tty_port *port,
unsigned char *chars, size_t size, bool is_cs7)
{
int i;
if (is_cs7)
for (i = 0; i < size; i++)
chars[i] &= 0x7F;
return tty_insert_flip_string(port, chars, size);
}
static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
{
struct tty_port *port = &sport->port.state->port;
struct dma_tx_state state;
enum dma_status dmastat;
struct dma_chan *chan = sport->dma_rx_chan;
struct circ_buf *ring = &sport->rx_ring;
unsigned long flags;
int count, copied;
if (lpuart_is_32(sport)) {
unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
/* Clear the error flags */
lpuart32_write(&sport->port, sr, UARTSTAT);
if (sr & UARTSTAT_PE)
sport->port.icount.parity++;
else if (sr & UARTSTAT_FE)
sport->port.icount.frame++;
}
} else {
unsigned char sr = readb(sport->port.membase + UARTSR1);
if (sr & (UARTSR1_PE | UARTSR1_FE)) {
unsigned char cr2;
/* Disable receiver during this operation... */
cr2 = readb(sport->port.membase + UARTCR2);
cr2 &= ~UARTCR2_RE;
writeb(cr2, sport->port.membase + UARTCR2);
/* Read DR to clear the error flags */
readb(sport->port.membase + UARTDR);
if (sr & UARTSR1_PE)
sport->port.icount.parity++;
else if (sr & UARTSR1_FE)
sport->port.icount.frame++;
/*
* At this point parity/framing error is
* cleared However, since the DMA already read
* the data register and we had to read it
* again after reading the status register to
* properly clear the flags, the FIFO actually
* underflowed... This requires a clearing of
* the FIFO...
*/
if (readb(sport->port.membase + UARTSFIFO) &
UARTSFIFO_RXUF) {
writeb(UARTSFIFO_RXUF,
sport->port.membase + UARTSFIFO);
writeb(UARTCFIFO_RXFLUSH,
sport->port.membase + UARTCFIFO);
}
cr2 |= UARTCR2_RE;
writeb(cr2, sport->port.membase + UARTCR2);
}
}
async_tx_ack(sport->dma_rx_desc);
spin_lock_irqsave(&sport->port.lock, flags);
dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
if (dmastat == DMA_ERROR) {
dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
spin_unlock_irqrestore(&sport->port.lock, flags);
return;
}
/* CPU claims ownership of RX DMA buffer */
dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
DMA_FROM_DEVICE);
/*
* ring->head points to the end of data already written by the DMA.
* ring->tail points to the beginning of data to be read by the
* framework.
* The current transfer size should not be larger than the dma buffer
* length.
*/
ring->head = sport->rx_sgl.length - state.residue;
BUG_ON(ring->head > sport->rx_sgl.length);
/*
* Silent handling of keys pressed in the sysrq timeframe
*/
if (sport->port.sysrq) {
lpuart_handle_sysrq(sport);
goto exit;
}
/*
* At this point ring->head may point to the first byte right after the
* last byte of the dma buffer:
* 0 <= ring->head <= sport->rx_sgl.length
*
* However ring->tail must always points inside the dma buffer:
* 0 <= ring->tail <= sport->rx_sgl.length - 1
*
* Since we use a ring buffer, we have to handle the case
* where head is lower than tail. In such a case, we first read from
* tail to the end of the buffer then reset tail.
*/
if (ring->head < ring->tail) {
count = sport->rx_sgl.length - ring->tail;
copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
count, sport->is_cs7);
if (copied != count)
sport->port.icount.buf_overrun++;
ring->tail = 0;
sport->port.icount.rx += copied;
}
/* Finally we read data from tail to head */
if (ring->tail < ring->head) {
count = ring->head - ring->tail;
copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
count, sport->is_cs7);
if (copied != count)
sport->port.icount.buf_overrun++;
/* Wrap ring->head if needed */
if (ring->head >= sport->rx_sgl.length)
ring->head = 0;
ring->tail = ring->head;
sport->port.icount.rx += copied;
}
sport->last_residue = state.residue;
exit:
dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
DMA_FROM_DEVICE);
spin_unlock_irqrestore(&sport->port.lock, flags);
tty_flip_buffer_push(port);
if (!sport->dma_idle_int)
mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
}
static void lpuart_dma_rx_complete(void *arg)
{
struct lpuart_port *sport = arg;
lpuart_copy_rx_to_tty(sport);
}
static void lpuart32_dma_idleint(struct lpuart_port *sport)
{
enum dma_status dmastat;
struct dma_chan *chan = sport->dma_rx_chan;
struct circ_buf *ring = &sport->rx_ring;
struct dma_tx_state state;
int count = 0;
dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
if (dmastat == DMA_ERROR) {
dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
return;
}
ring->head = sport->rx_sgl.length - state.residue;
count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
/* Check if new data received before copying */
if (count)
lpuart_copy_rx_to_tty(sport);
}
static irqreturn_t lpuart32_int(int irq, void *dev_id)
{
struct lpuart_port *sport = dev_id;
unsigned long sts, rxcount;
sts = lpuart32_read(&sport->port, UARTSTAT);
rxcount = lpuart32_read(&sport->port, UARTWATER);
rxcount = rxcount >> UARTWATER_RXCNT_OFF;
if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
lpuart32_rxint(sport);
if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
lpuart32_txint(sport);
if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int)
lpuart32_dma_idleint(sport);
lpuart32_write(&sport->port, sts, UARTSTAT);
return IRQ_HANDLED;
}
/*
* Timer function to simulate the hardware EOP (End Of Package) event.
* The timer callback is to check for new RX data and copy to TTY buffer.
* If no new data are received since last interval, the EOP condition is
* met, complete the DMA transfer by copying the data. Otherwise, just
* restart timer.
*/
static void lpuart_timer_func(struct timer_list *t)
{
struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
enum dma_status dmastat;
struct dma_chan *chan = sport->dma_rx_chan;
struct circ_buf *ring = &sport->rx_ring;
struct dma_tx_state state;
unsigned long flags;
int count;
dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
if (dmastat == DMA_ERROR) {
dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
return;
}
ring->head = sport->rx_sgl.length - state.residue;
count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
/* Check if new data received before copying */
if ((count != 0) && (sport->last_residue == state.residue))
lpuart_copy_rx_to_tty(sport);
else
mod_timer(&sport->lpuart_timer,
jiffies + sport->dma_rx_timeout);
if (spin_trylock_irqsave(&sport->port.lock, flags)) {
sport->last_residue = state.residue;
spin_unlock_irqrestore(&sport->port.lock, flags);
}
}
static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
{
struct dma_slave_config dma_rx_sconfig = {};
struct circ_buf *ring = &sport->rx_ring;
int ret, nent;
struct tty_port *port = &sport->port.state->port;
struct tty_struct *tty = port->tty;
struct ktermios *termios = &tty->termios;
struct dma_chan *chan = sport->dma_rx_chan;
unsigned int bits = tty_get_frame_size(termios->c_cflag);
unsigned int baud = tty_get_baud_rate(tty);
/*
* Calculate length of one DMA buffer size to keep latency below
* 10ms at any baud rate.
*/
sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
sport->rx_dma_rng_buf_len = max_t(int,
sport->rxfifo_size * 2,
sport->rx_dma_rng_buf_len);
/*
* Keep this condition check in case rxfifo_size is unavailable
* for some SoCs.
*/
if (sport->rx_dma_rng_buf_len < 16)
sport->rx_dma_rng_buf_len = 16;
sport->last_residue = 0;
sport->dma_rx_timeout = max(nsecs_to_jiffies(
sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);
ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
if (!ring->buf)
return -ENOMEM;
sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
DMA_FROM_DEVICE);
if (!nent) {
dev_err(sport->port.dev, "DMA Rx mapping error\n");
return -EINVAL;
}
dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dma_rx_sconfig.src_maxburst = 1;
dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
if (ret < 0) {
dev_err(sport->port.dev,
"DMA Rx slave config failed, err = %d\n", ret);
return ret;
}
sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
sg_dma_address(&sport->rx_sgl),
sport->rx_sgl.length,
sport->rx_sgl.length / 2,
DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT);
if (!sport->dma_rx_desc) {
dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
return -EFAULT;
}
sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
sport->dma_rx_desc->callback_param = sport;
sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
dma_async_issue_pending(chan);
if (lpuart_is_32(sport)) {
unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
if (sport->dma_idle_int) {
unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL);
lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL);
}
} else {
writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
sport->port.membase + UARTCR5);
}
return 0;
}
static void lpuart_dma_rx_free(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
struct dma_chan *chan = sport->dma_rx_chan;
dmaengine_terminate_sync(chan);
if (!sport->dma_idle_int)
del_timer_sync(&sport->lpuart_timer);
dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
kfree(sport->rx_ring.buf);
sport->rx_ring.tail = 0;
sport->rx_ring.head = 0;
sport->dma_rx_desc = NULL;
sport->dma_rx_cookie = -EINVAL;
}
static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
u8 modem = readb(sport->port.membase + UARTMODEM) &
~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
writeb(modem, sport->port.membase + UARTMODEM);
if (rs485->flags & SER_RS485_ENABLED) {
/* Enable auto RS-485 RTS mode */
modem |= UARTMODEM_TXRTSE;
/*
* The hardware defaults to RTS logic HIGH while transfer.
* Switch polarity in case RTS shall be logic HIGH
* after transfer.
* Note: UART is assumed to be active high.
*/
if (rs485->flags & SER_RS485_RTS_ON_SEND)
modem |= UARTMODEM_TXRTSPOL;
else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
modem &= ~UARTMODEM_TXRTSPOL;
}
writeb(modem, sport->port.membase + UARTMODEM);
return 0;
}
static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct lpuart_port *sport = container_of(port,
struct lpuart_port, port);
unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
& ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
lpuart32_write(&sport->port, modem, UARTMODIR);
if (rs485->flags & SER_RS485_ENABLED) {
/* Enable auto RS-485 RTS mode */
modem |= UARTMODIR_TXRTSE;
/*
* The hardware defaults to RTS logic HIGH while transfer.
* Switch polarity in case RTS shall be logic HIGH
* after transfer.
* Note: UART is assumed to be active high.
*/
if (rs485->flags & SER_RS485_RTS_ON_SEND)
modem |= UARTMODIR_TXRTSPOL;
else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
modem &= ~UARTMODIR_TXRTSPOL;
}
lpuart32_write(&sport->port, modem, UARTMODIR);
return 0;
}
static unsigned int lpuart_get_mctrl(struct uart_port *port)
{
unsigned int mctrl = 0;
u8 reg;
reg = readb(port->membase + UARTCR1);
if (reg & UARTCR1_LOOPS)
mctrl |= TIOCM_LOOP;
return mctrl;
}
static unsigned int lpuart32_get_mctrl(struct uart_port *port)
{
unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
u32 reg;
reg = lpuart32_read(port, UARTCTRL);
if (reg & UARTCTRL_LOOPS)
mctrl |= TIOCM_LOOP;
return mctrl;
}
static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
u8 reg;
reg = readb(port->membase + UARTCR1);
/* for internal loopback we need LOOPS=1 and RSRC=0 */
reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
if (mctrl & TIOCM_LOOP)
reg |= UARTCR1_LOOPS;
writeb(reg, port->membase + UARTCR1);
}
static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
u32 reg;
reg = lpuart32_read(port, UARTCTRL);
/* for internal loopback we need LOOPS=1 and RSRC=0 */
reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
if (mctrl & TIOCM_LOOP)
reg |= UARTCTRL_LOOPS;
lpuart32_write(port, reg, UARTCTRL);
}
static void lpuart_break_ctl(struct uart_port *port, int break_state)
{
unsigned char temp;
temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
if (break_state != 0)
temp |= UARTCR2_SBK;
writeb(temp, port->membase + UARTCR2);
}
static void lpuart32_break_ctl(struct uart_port *port, int break_state)
{
unsigned long temp;
temp = lpuart32_read(port, UARTCTRL);
/*
* LPUART IP now has two known bugs, one is CTS has higher priority than the
* break signal, which causes the break signal sending through UARTCTRL_SBK
* may impacted by the CTS input if the HW flow control is enabled. It
* exists on all platforms we support in this driver.
* Another bug is i.MX8QM LPUART may have an additional break character
* being sent after SBK was cleared.
* To avoid above two bugs, we use Transmit Data Inversion function to send
* the break signal instead of UARTCTRL_SBK.
*/
if (break_state != 0) {
/*
* Disable the transmitter to prevent any data from being sent out
* during break, then invert the TX line to send break.
*/
temp &= ~UARTCTRL_TE;
lpuart32_write(port, temp, UARTCTRL);
temp |= UARTCTRL_TXINV;
lpuart32_write(port, temp, UARTCTRL);
} else {
/* Disable the TXINV to turn off break and re-enable transmitter. */
temp &= ~UARTCTRL_TXINV;
lpuart32_write(port, temp, UARTCTRL);
temp |= UARTCTRL_TE;
lpuart32_write(port, temp, UARTCTRL);
}
}
static void lpuart_setup_watermark(struct lpuart_port *sport)
{
unsigned char val, cr2;
unsigned char cr2_saved;
cr2 = readb(sport->port.membase + UARTCR2);
cr2_saved = cr2;
cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
UARTCR2_RIE | UARTCR2_RE);
writeb(cr2, sport->port.membase + UARTCR2);
val = readb(sport->port.membase + UARTPFIFO);
writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
sport->port.membase + UARTPFIFO);
/* flush Tx and Rx FIFO */
writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
sport->port.membase + UARTCFIFO);
/* explicitly clear RDRF */
if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
readb(sport->port.membase + UARTDR);
writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
}
if (uart_console(&sport->port))
sport->rx_watermark = 1;
writeb(0, sport->port.membase + UARTTWFIFO);
writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
/* Restore cr2 */
writeb(cr2_saved, sport->port.membase + UARTCR2);
}
static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
{
unsigned char cr2;
lpuart_setup_watermark(sport);
cr2 = readb(sport->port.membase + UARTCR2);
cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
writeb(cr2, sport->port.membase + UARTCR2);
}
static void lpuart32_setup_watermark(struct lpuart_port *sport)
{
unsigned long val, ctrl;
unsigned long ctrl_saved;
ctrl = lpuart32_read(&sport->port, UARTCTRL);
ctrl_saved = ctrl;
ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);
lpuart32_write(&sport->port, ctrl, UARTCTRL);
/* enable FIFO mode */
val = lpuart32_read(&sport->port, UARTFIFO);
val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);
lpuart32_write(&sport->port, val, UARTFIFO);
/* set the watermark */
if (uart_console(&sport->port))
sport->rx_watermark = 1;
val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
(0x0 << UARTWATER_TXWATER_OFF);
lpuart32_write(&sport->port, val, UARTWATER);
/* set RTS watermark */
if (!uart_console(&sport->port)) {
val = lpuart32_read(&sport->port, UARTMODIR);
val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
lpuart32_write(&sport->port, val, UARTMODIR);
}
/* Restore cr2 */
lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
}
static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
{
u32 temp;
lpuart32_setup_watermark(sport);
temp = lpuart32_read(&sport->port, UARTCTRL);
temp |= UARTCTRL_RE | UARTCTRL_TE;
temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
lpuart32_write(&sport->port, temp, UARTCTRL);
}
static void rx_dma_timer_init(struct lpuart_port *sport)
{
if (sport->dma_idle_int)
return;
timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
add_timer(&sport->lpuart_timer);
}
static void lpuart_request_dma(struct lpuart_port *sport)
{
sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
if (IS_ERR(sport->dma_tx_chan)) {
dev_dbg_once(sport->port.dev,
"DMA tx channel request failed, operating without tx DMA (%ld)\n",
PTR_ERR(sport->dma_tx_chan));
sport->dma_tx_chan = NULL;
}
sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
if (IS_ERR(sport->dma_rx_chan)) {
dev_dbg_once(sport->port.dev,
"DMA rx channel request failed, operating without rx DMA (%ld)\n",
PTR_ERR(sport->dma_rx_chan));
sport->dma_rx_chan = NULL;
}
}
static void lpuart_tx_dma_startup(struct lpuart_port *sport)
{
u32 uartbaud;
int ret;
if (uart_console(&sport->port))
goto err;
if (!sport->dma_tx_chan)
goto err;
ret = lpuart_dma_tx_request(&sport->port);
if (ret)
goto err;
init_waitqueue_head(&sport->dma_wait);
sport->lpuart_dma_tx_use = true;
if (lpuart_is_32(sport)) {
uartbaud = lpuart32_read(&sport->port, UARTBAUD);
lpuart32_write(&sport->port,
uartbaud | UARTBAUD_TDMAE, UARTBAUD);
} else {
writeb(readb(sport->port.membase + UARTCR5) |
UARTCR5_TDMAS, sport->port.membase + UARTCR5);
}
return;
err:
sport->lpuart_dma_tx_use = false;
}
static void lpuart_rx_dma_startup(struct lpuart_port *sport)
{
int ret;
unsigned char cr3;
if (uart_console(&sport->port))
goto err;
if (!sport->dma_rx_chan)
goto err;
/* set default Rx DMA timeout */
sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
ret = lpuart_start_rx_dma(sport);
if (ret)
goto err;
if (!sport->dma_rx_timeout)
sport->dma_rx_timeout = 1;
sport->lpuart_dma_rx_use = true;
rx_dma_timer_init(sport);
if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
cr3 = readb(sport->port.membase + UARTCR3);
cr3 |= UARTCR3_FEIE;
writeb(cr3, sport->port.membase + UARTCR3);
}
return;
err:
sport->lpuart_dma_rx_use = false;
}
static void lpuart_hw_setup(struct lpuart_port *sport)
{
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
lpuart_setup_watermark_enable(sport);
lpuart_rx_dma_startup(sport);
lpuart_tx_dma_startup(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
}
static int lpuart_startup(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned char temp;
/* determine FIFO size and enable FIFO mode */
temp = readb(sport->port.membase + UARTPFIFO);
sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
UARTPFIFO_FIFOSIZE_MASK);
sport->port.fifosize = sport->txfifo_size;
sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
UARTPFIFO_FIFOSIZE_MASK);
lpuart_request_dma(sport);
lpuart_hw_setup(sport);
return 0;
}
static void lpuart32_hw_disable(struct lpuart_port *sport)
{
unsigned long temp;
temp = lpuart32_read(&sport->port, UARTCTRL);
temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
UARTCTRL_TIE | UARTCTRL_TE);
lpuart32_write(&sport->port, temp, UARTCTRL);
}
static void lpuart32_configure(struct lpuart_port *sport)
{
unsigned long temp;
temp = lpuart32_read(&sport->port, UARTCTRL);
if (!sport->lpuart_dma_rx_use)
temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
if (!sport->lpuart_dma_tx_use)
temp |= UARTCTRL_TIE;
lpuart32_write(&sport->port, temp, UARTCTRL);
}
static void lpuart32_hw_setup(struct lpuart_port *sport)
{
unsigned long flags;
spin_lock_irqsave(&sport->port.lock, flags);
lpuart32_hw_disable(sport);
lpuart_rx_dma_startup(sport);
lpuart_tx_dma_startup(sport);
lpuart32_setup_watermark_enable(sport);
lpuart32_configure(sport);
spin_unlock_irqrestore(&sport->port.lock, flags);
}
static int lpuart32_startup(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned long temp;
/* determine FIFO size */
temp = lpuart32_read(&sport->port, UARTFIFO);
sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
UARTFIFO_FIFOSIZE_MASK);
sport->port.fifosize = sport->txfifo_size;
sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
UARTFIFO_FIFOSIZE_MASK);
/*
* The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
* Although they support the RX/TXSIZE fields, their encoding is
* different. Eg the reference manual states 0b101 is 16 words.
*/
if (is_layerscape_lpuart(sport)) {
sport->rxfifo_size = 16;
sport->txfifo_size = 16;
sport->port.fifosize = sport->txfifo_size;
}
lpuart_request_dma(sport);
lpuart32_hw_setup(sport);
return 0;
}
static void lpuart_dma_shutdown(struct lpuart_port *sport)
{
if (sport->lpuart_dma_rx_use) {
lpuart_dma_rx_free(&sport->port);
sport->lpuart_dma_rx_use = false;
}
if (sport->lpuart_dma_tx_use) {
if (wait_event_interruptible_timeout(sport->dma_wait,
!sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
sport->dma_tx_in_progress = false;
dmaengine_terminate_sync(sport->dma_tx_chan);
}
sport->lpuart_dma_tx_use = false;
}
if (sport->dma_tx_chan)
dma_release_channel(sport->dma_tx_chan);
if (sport->dma_rx_chan)
dma_release_channel(sport->dma_rx_chan);
}
static void lpuart_shutdown(struct uart_port *port)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned char temp;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
/* disable Rx/Tx and interrupts */
temp = readb(port->membase + UARTCR2);
temp &= ~(UARTCR2_TE | UARTCR2_RE |
UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
writeb(temp, port->membase + UARTCR2);
spin_unlock_irqrestore(&port->lock, flags);
lpuart_dma_shutdown(sport);
}
static void lpuart32_shutdown(struct uart_port *port)
{
struct lpuart_port *sport =
container_of(port, struct lpuart_port, port);
unsigned long temp;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
/* clear status */
temp = lpuart32_read(&sport->port, UARTSTAT);
lpuart32_write(&sport->port, temp, UARTSTAT);
/* disable Rx/Tx DMA */
temp = lpuart32_read(port, UARTBAUD);
temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
lpuart32_write(port, temp, UARTBAUD);
/* disable Rx/Tx and interrupts and break condition */
temp = lpuart32_read(port, UARTCTRL);
temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |
UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
lpuart32_write(port, temp, UARTCTRL);
spin_unlock_irqrestore(&port->lock, flags);
lpuart_dma_shutdown(sport);
}
static void
lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned long flags;
unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
unsigned int baud;
unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
unsigned int sbr, brfa;
cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
old_cr2 = readb(sport->port.membase + UARTCR2);
cr3 = readb(sport->port.membase + UARTCR3);
cr4 = readb(sport->port.membase + UARTCR4);
bdh = readb(sport->port.membase + UARTBDH);
modem = readb(sport->port.membase + UARTMODEM);
/*
* only support CS8 and CS7, and for CS7 must enable PE.
* supported mode:
* - (7,e/o,1)
* - (8,n,1)
* - (8,m/s,1)
* - (8,e/o,1)
*/
while ((termios->c_cflag & CSIZE) != CS8 &&
(termios->c_cflag & CSIZE) != CS7) {
termios->c_cflag &= ~CSIZE;
termios->c_cflag |= old_csize;
old_csize = CS8;
}
if ((termios->c_cflag & CSIZE) == CS8 ||
(termios->c_cflag & CSIZE) == CS7)
cr1 = old_cr1 & ~UARTCR1_M;
if (termios->c_cflag & CMSPAR) {
if ((termios->c_cflag & CSIZE) != CS8) {
termios->c_cflag &= ~CSIZE;
termios->c_cflag |= CS8;
}
cr1 |= UARTCR1_M;
}
/*
* When auto RS-485 RTS mode is enabled,
* hardware flow control need to be disabled.
*/
if (sport->port.rs485.flags & SER_RS485_ENABLED)
termios->c_cflag &= ~CRTSCTS;
if (termios->c_cflag & CRTSCTS)
modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
else
modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
termios->c_cflag &= ~CSTOPB;
/* parity must be enabled when CS7 to match 8-bits format */
if ((termios->c_cflag & CSIZE) == CS7)
termios->c_cflag |= PARENB;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & CMSPAR) {
cr1 &= ~UARTCR1_PE;
if (termios->c_cflag & PARODD)
cr3 |= UARTCR3_T8;
else
cr3 &= ~UARTCR3_T8;
} else {
cr1 |= UARTCR1_PE;
if ((termios->c_cflag & CSIZE) == CS8)
cr1 |= UARTCR1_M;
if (termios->c_cflag & PARODD)
cr1 |= UARTCR1_PT;
else
cr1 &= ~UARTCR1_PT;
}
} else {
cr1 &= ~UARTCR1_PE;
}
/* ask the core to calculate the divisor */
baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
/*
* Need to update the Ring buffer length according to the selected
* baud rate and restart Rx DMA path.
*
* Since timer function acqures sport->port.lock, need to stop before
* acquring same lock because otherwise del_timer_sync() can deadlock.
*/
if (old && sport->lpuart_dma_rx_use)
lpuart_dma_rx_free(&sport->port);
spin_lock_irqsave(&sport->port.lock, flags);
sport->port.read_status_mask = 0;
if (termios->c_iflag & INPCK)
sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
sport->port.read_status_mask |= UARTSR1_FE;
/* characters to ignore */
sport->port.ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
sport->port.ignore_status_mask |= UARTSR1_PE;
if (termios->c_iflag & IGNBRK) {
sport->port.ignore_status_mask |= UARTSR1_FE;
/*
* if we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
sport->port.ignore_status_mask |= UARTSR1_OR;
}
/* update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, baud);
/* wait transmit engin complete */
lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
/* disable transmit and receive */
writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
sport->port.membase + UARTCR2);
sbr = sport->port.uartclk / (16 * baud);
brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
bdh &= ~UARTBDH_SBR_MASK;
bdh |= (sbr >> 8) & 0x1F;
cr4 &= ~UARTCR4_BRFA_MASK;
brfa &= UARTCR4_BRFA_MASK;
writeb(cr4 | brfa, sport->port.membase + UARTCR4);
writeb(bdh, sport->port.membase + UARTBDH);
writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
writeb(cr3, sport->port.membase + UARTCR3);
writeb(cr1, sport->port.membase + UARTCR1);
writeb(modem, sport->port.membase + UARTMODEM);
/* restore control register */
writeb(old_cr2, sport->port.membase + UARTCR2);
if (old && sport->lpuart_dma_rx_use) {
if (!lpuart_start_rx_dma(sport))
rx_dma_timer_init(sport);
else
sport->lpuart_dma_rx_use = false;
}
spin_unlock_irqrestore(&sport->port.lock, flags);
}
static void __lpuart32_serial_setbrg(struct uart_port *port,
unsigned int baudrate, bool use_rx_dma,
bool use_tx_dma)
{
u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
u32 clk = port->uartclk;
/*
* The idea is to use the best OSR (over-sampling rate) possible.
* Note, OSR is typically hard-set to 16 in other LPUART instantiations.
* Loop to find the best OSR value possible, one that generates minimum
* baud_diff iterate through the rest of the supported values of OSR.
*
* Calculation Formula:
* Baud Rate = baud clock / ((OSR+1) × SBR)
*/
baud_diff = baudrate;
osr = 0;
sbr = 0;
for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
/* calculate the temporary sbr value */
tmp_sbr = (clk / (baudrate * tmp_osr));
if (tmp_sbr == 0)
tmp_sbr = 1;
/*
* calculate the baud rate difference based on the temporary
* osr and sbr values
*/
tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
/* select best values between sbr and sbr+1 */
tmp = clk / (tmp_osr * (tmp_sbr + 1));
if (tmp_diff > (baudrate - tmp)) {
tmp_diff = baudrate - tmp;
tmp_sbr++;
}
if (tmp_sbr > UARTBAUD_SBR_MASK)
continue;
if (tmp_diff <= baud_diff) {
baud_diff = tmp_diff;
osr = tmp_osr;
sbr = tmp_sbr;
if (!baud_diff)
break;
}
}
/* handle buadrate outside acceptable rate */
if (baud_diff > ((baudrate / 100) * 3))
dev_warn(port->dev,
"unacceptable baud rate difference of more than 3%%\n");
tmp = lpuart32_read(port, UARTBAUD);
if ((osr > 3) && (osr < 8))
tmp |= UARTBAUD_BOTHEDGE;
tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
tmp &= ~UARTBAUD_SBR_MASK;
tmp |= sbr & UARTBAUD_SBR_MASK;
if (!use_rx_dma)
tmp &= ~UARTBAUD_RDMAE;
if (!use_tx_dma)
tmp &= ~UARTBAUD_TDMAE;
lpuart32_write(port, tmp, UARTBAUD);
}
static void lpuart32_serial_setbrg(struct lpuart_port *sport,
unsigned int baudrate)
{
__lpuart32_serial_setbrg(&sport->port, baudrate,
sport->lpuart_dma_rx_use,
sport->lpuart_dma_tx_use);
}
static void
lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned long flags;
unsigned long ctrl, old_ctrl, bd, modem;
unsigned int baud;
unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
bd = lpuart32_read(&sport->port, UARTBAUD);
modem = lpuart32_read(&sport->port, UARTMODIR);
sport->is_cs7 = false;
/*
* only support CS8 and CS7, and for CS7 must enable PE.
* supported mode:
* - (7,e/o,1)
* - (8,n,1)
* - (8,m/s,1)
* - (8,e/o,1)
*/
while ((termios->c_cflag & CSIZE) != CS8 &&
(termios->c_cflag & CSIZE) != CS7) {
termios->c_cflag &= ~CSIZE;
termios->c_cflag |= old_csize;
old_csize = CS8;
}
if ((termios->c_cflag & CSIZE) == CS8 ||
(termios->c_cflag & CSIZE) == CS7)
ctrl = old_ctrl & ~UARTCTRL_M;
if (termios->c_cflag & CMSPAR) {
if ((termios->c_cflag & CSIZE) != CS8) {
termios->c_cflag &= ~CSIZE;
termios->c_cflag |= CS8;
}
ctrl |= UARTCTRL_M;
}
/*
* When auto RS-485 RTS mode is enabled,
* hardware flow control need to be disabled.
*/
if (sport->port.rs485.flags & SER_RS485_ENABLED)
termios->c_cflag &= ~CRTSCTS;
if (termios->c_cflag & CRTSCTS)
modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
else
modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
if (termios->c_cflag & CSTOPB)
bd |= UARTBAUD_SBNS;
else
bd &= ~UARTBAUD_SBNS;
/* parity must be enabled when CS7 to match 8-bits format */
if ((termios->c_cflag & CSIZE) == CS7)
termios->c_cflag |= PARENB;
if ((termios->c_cflag & PARENB)) {
if (termios->c_cflag & CMSPAR) {
ctrl &= ~UARTCTRL_PE;
ctrl |= UARTCTRL_M;
} else {
ctrl |= UARTCTRL_PE;
if ((termios->c_cflag & CSIZE) == CS8)
ctrl |= UARTCTRL_M;
if (termios->c_cflag & PARODD)
ctrl |= UARTCTRL_PT;
else
ctrl &= ~UARTCTRL_PT;
}
} else {
ctrl &= ~UARTCTRL_PE;
}
/* ask the core to calculate the divisor */
baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
/*
* Need to update the Ring buffer length according to the selected
* baud rate and restart Rx DMA path.
*
* Since timer function acqures sport->port.lock, need to stop before
* acquring same lock because otherwise del_timer_sync() can deadlock.
*/
if (old && sport->lpuart_dma_rx_use)
lpuart_dma_rx_free(&sport->port);
spin_lock_irqsave(&sport->port.lock, flags);
sport->port.read_status_mask = 0;
if (termios->c_iflag & INPCK)
sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
sport->port.read_status_mask |= UARTSTAT_FE;
/* characters to ignore */
sport->port.ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
sport->port.ignore_status_mask |= UARTSTAT_PE;
if (termios->c_iflag & IGNBRK) {
sport->port.ignore_status_mask |= UARTSTAT_FE;
/*
* if we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
sport->port.ignore_status_mask |= UARTSTAT_OR;
}
/* update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, baud);
/*
* LPUART Transmission Complete Flag may never be set while queuing a break
* character, so skip waiting for transmission complete when UARTCTRL_SBK is
* asserted.
*/
if (!(old_ctrl & UARTCTRL_SBK)) {
lpuart32_write(&sport->port, 0, UARTMODIR);
lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
}
/* disable transmit and receive */
lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
UARTCTRL);
lpuart32_write(&sport->port, bd, UARTBAUD);
lpuart32_serial_setbrg(sport, baud);
lpuart32_write(&sport->port, modem, UARTMODIR);
lpuart32_write(&sport->port, ctrl, UARTCTRL);
/* restore control register */
if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
sport->is_cs7 = true;
if (old && sport->lpuart_dma_rx_use) {
if (!lpuart_start_rx_dma(sport))
rx_dma_timer_init(sport);
else
sport->lpuart_dma_rx_use = false;
}
spin_unlock_irqrestore(&sport->port.lock, flags);
}
static const char *lpuart_type(struct uart_port *port)
{
return "FSL_LPUART";
}
static void lpuart_release_port(struct uart_port *port)
{
/* nothing to do */
}
static int lpuart_request_port(struct uart_port *port)
{
return 0;
}
/* configure/autoconfigure the port */
static void lpuart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_LPUART;
}
static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
ret = -EINVAL;
if (port->irq != ser->irq)
ret = -EINVAL;
if (ser->io_type != UPIO_MEM)
ret = -EINVAL;
if (port->uartclk / 16 != ser->baud_base)
ret = -EINVAL;
if (port->iobase != ser->port)
ret = -EINVAL;
if (ser->hub6 != 0)
ret = -EINVAL;
return ret;
}
static const struct uart_ops lpuart_pops = {
.tx_empty = lpuart_tx_empty,
.set_mctrl = lpuart_set_mctrl,
.get_mctrl = lpuart_get_mctrl,
.stop_tx = lpuart_stop_tx,
.start_tx = lpuart_start_tx,
.stop_rx = lpuart_stop_rx,
.break_ctl = lpuart_break_ctl,
.startup = lpuart_startup,
.shutdown = lpuart_shutdown,
.set_termios = lpuart_set_termios,
.pm = lpuart_uart_pm,
.type = lpuart_type,
.request_port = lpuart_request_port,
.release_port = lpuart_release_port,
.config_port = lpuart_config_port,
.verify_port = lpuart_verify_port,
.flush_buffer = lpuart_flush_buffer,
#if defined(CONFIG_CONSOLE_POLL)
.poll_init = lpuart_poll_init,
.poll_get_char = lpuart_poll_get_char,
.poll_put_char = lpuart_poll_put_char,
#endif
};
static const struct uart_ops lpuart32_pops = {
.tx_empty = lpuart32_tx_empty,
.set_mctrl = lpuart32_set_mctrl,
.get_mctrl = lpuart32_get_mctrl,
.stop_tx = lpuart32_stop_tx,
.start_tx = lpuart32_start_tx,
.stop_rx = lpuart32_stop_rx,
.break_ctl = lpuart32_break_ctl,
.startup = lpuart32_startup,
.shutdown = lpuart32_shutdown,
.set_termios = lpuart32_set_termios,
.pm = lpuart_uart_pm,
.type = lpuart_type,
.request_port = lpuart_request_port,
.release_port = lpuart_release_port,
.config_port = lpuart_config_port,
.verify_port = lpuart_verify_port,
.flush_buffer = lpuart_flush_buffer,
#if defined(CONFIG_CONSOLE_POLL)
.poll_init = lpuart32_poll_init,
.poll_get_char = lpuart32_poll_get_char,
.poll_put_char = lpuart32_poll_put_char,
#endif
};
static struct lpuart_port *lpuart_ports[UART_NR];
#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
{
lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
writeb(ch, port->membase + UARTDR);
}
static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
{
lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
lpuart32_write(port, ch, UARTDATA);
}
static void
lpuart_console_write(struct console *co, const char *s, unsigned int count)
{
struct lpuart_port *sport = lpuart_ports[co->index];
unsigned char old_cr2, cr2;
unsigned long flags;
int locked = 1;
if (oops_in_progress)
locked = spin_trylock_irqsave(&sport->port.lock, flags);
else
spin_lock_irqsave(&sport->port.lock, flags);
/* first save CR2 and then disable interrupts */
cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
cr2 |= UARTCR2_TE | UARTCR2_RE;
cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
writeb(cr2, sport->port.membase + UARTCR2);
uart_console_write(&sport->port, s, count, lpuart_console_putchar);
/* wait for transmitter finish complete and restore CR2 */
lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
writeb(old_cr2, sport->port.membase + UARTCR2);
if (locked)
spin_unlock_irqrestore(&sport->port.lock, flags);
}
static void
lpuart32_console_write(struct console *co, const char *s, unsigned int count)
{
struct lpuart_port *sport = lpuart_ports[co->index];
unsigned long old_cr, cr;
unsigned long flags;
int locked = 1;
if (oops_in_progress)
locked = spin_trylock_irqsave(&sport->port.lock, flags);
else
spin_lock_irqsave(&sport->port.lock, flags);
/* first save CR2 and then disable interrupts */
cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
cr |= UARTCTRL_TE | UARTCTRL_RE;
cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
lpuart32_write(&sport->port, cr, UARTCTRL);
uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
/* wait for transmitter finish complete and restore CR2 */
lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
lpuart32_write(&sport->port, old_cr, UARTCTRL);
if (locked)
spin_unlock_irqrestore(&sport->port.lock, flags);
}
/*
* if the port was already initialised (eg, by a boot loader),
* try to determine the current setup.
*/
static void __init
lpuart_console_get_options(struct lpuart_port *sport, int *baud,
int *parity, int *bits)
{
unsigned char cr, bdh, bdl, brfa;
unsigned int sbr, uartclk, baud_raw;
cr = readb(sport->port.membase + UARTCR2);
cr &= UARTCR2_TE | UARTCR2_RE;
if (!cr)
return;
/* ok, the port was enabled */
cr = readb(sport->port.membase + UARTCR1);
*parity = 'n';
if (cr & UARTCR1_PE) {
if (cr & UARTCR1_PT)
*parity = 'o';
else
*parity = 'e';
}
if (cr & UARTCR1_M)
*bits = 9;
else
*bits = 8;
bdh = readb(sport->port.membase + UARTBDH);
bdh &= UARTBDH_SBR_MASK;
bdl = readb(sport->port.membase + UARTBDL);
sbr = bdh;
sbr <<= 8;
sbr |= bdl;
brfa = readb(sport->port.membase + UARTCR4);
brfa &= UARTCR4_BRFA_MASK;
uartclk = lpuart_get_baud_clk_rate(sport);
/*
* baud = mod_clk/(16*(sbr[13]+(brfa)/32)
*/
baud_raw = uartclk / (16 * (sbr + brfa / 32));
if (*baud != baud_raw)
dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
"from %d to %d\n", baud_raw, *baud);
}
static void __init
lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
int *parity, int *bits)
{
unsigned long cr, bd;
unsigned int sbr, uartclk, baud_raw;
cr = lpuart32_read(&sport->port, UARTCTRL);
cr &= UARTCTRL_TE | UARTCTRL_RE;
if (!cr)
return;
/* ok, the port was enabled */
cr = lpuart32_read(&sport->port, UARTCTRL);
*parity = 'n';
if (cr & UARTCTRL_PE) {
if (cr & UARTCTRL_PT)
*parity = 'o';
else
*parity = 'e';
}
if (cr & UARTCTRL_M)
*bits = 9;
else
*bits = 8;
bd = lpuart32_read(&sport->port, UARTBAUD);
bd &= UARTBAUD_SBR_MASK;
if (!bd)
return;
sbr = bd;
uartclk = lpuart_get_baud_clk_rate(sport);
/*
* baud = mod_clk/(16*(sbr[13]+(brfa)/32)
*/
baud_raw = uartclk / (16 * sbr);
if (*baud != baud_raw)
dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
"from %d to %d\n", baud_raw, *baud);
}
static int __init lpuart_console_setup(struct console *co, char *options)
{
struct lpuart_port *sport;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
/*
* check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
co->index = 0;
sport = lpuart_ports[co->index];
if (sport == NULL)
return -ENODEV;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
else
if (lpuart_is_32(sport))
lpuart32_console_get_options(sport, &baud, &parity, &bits);
else
lpuart_console_get_options(sport, &baud, &parity, &bits);
if (lpuart_is_32(sport))
lpuart32_setup_watermark(sport);
else
lpuart_setup_watermark(sport);
return uart_set_options(&sport->port, co, baud, parity, bits, flow);
}
static struct uart_driver lpuart_reg;
static struct console lpuart_console = {
.name = DEV_NAME,
.write = lpuart_console_write,
.device = uart_console_device,
.setup = lpuart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &lpuart_reg,
};
static struct console lpuart32_console = {
.name = DEV_NAME,
.write = lpuart32_console_write,
.device = uart_console_device,
.setup = lpuart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &lpuart_reg,
};
static void lpuart_early_write(struct console *con, const char *s, unsigned n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, lpuart_console_putchar);
}
static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
}
static int __init lpuart_early_console_setup(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = lpuart_early_write;
return 0;
}
static int __init lpuart32_early_console_setup(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
if (device->port.iotype != UPIO_MEM32)
device->port.iotype = UPIO_MEM32BE;
device->con->write = lpuart32_early_write;
return 0;
}
static int __init ls1028a_early_console_setup(struct earlycon_device *device,
const char *opt)
{
u32 cr;
if (!device->port.membase)
return -ENODEV;
device->port.iotype = UPIO_MEM32;
device->con->write = lpuart32_early_write;
/* set the baudrate */
if (device->port.uartclk && device->baud)
__lpuart32_serial_setbrg(&device->port, device->baud,
false, false);
/* enable transmitter */
cr = lpuart32_read(&device->port, UARTCTRL);
cr |= UARTCTRL_TE;
lpuart32_write(&device->port, cr, UARTCTRL);
return 0;
}
static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->port.iotype = UPIO_MEM32;
device->port.membase += IMX_REG_OFF;
device->con->write = lpuart32_early_write;
return 0;
}
OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
#define LPUART_CONSOLE (&lpuart_console)
#define LPUART32_CONSOLE (&lpuart32_console)
#else
#define LPUART_CONSOLE NULL
#define LPUART32_CONSOLE NULL
#endif
static struct uart_driver lpuart_reg = {
.owner = THIS_MODULE,
.driver_name = DRIVER_NAME,
.dev_name = DEV_NAME,
.nr = ARRAY_SIZE(lpuart_ports),
.cons = LPUART_CONSOLE,
};
static const struct serial_rs485 lpuart_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
/* delay_rts_* and RX_DURING_TX are not supported */
};
static int lpuart_global_reset(struct lpuart_port *sport)
{
struct uart_port *port = &sport->port;
void __iomem *global_addr;
unsigned long ctrl, bd;
unsigned int val = 0;
int ret;
ret = clk_prepare_enable(sport->ipg_clk);
if (ret) {
dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
return ret;
}
if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
/*
* If the transmitter is used by earlycon, wait for transmit engine to
* complete and then reset.
*/
ctrl = lpuart32_read(port, UARTCTRL);
if (ctrl & UARTCTRL_TE) {
bd = lpuart32_read(&sport->port, UARTBAUD);
if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
port)) {
dev_warn(sport->port.dev,
"timeout waiting for transmit engine to complete\n");
clk_disable_unprepare(sport->ipg_clk);
return 0;
}
}
global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
writel(UART_GLOBAL_RST, global_addr);
usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
writel(0, global_addr);
usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
/* Recover the transmitter for earlycon. */
if (ctrl & UARTCTRL_TE) {
lpuart32_write(port, bd, UARTBAUD);
lpuart32_write(port, ctrl, UARTCTRL);
}
}
clk_disable_unprepare(sport->ipg_clk);
return 0;
}
static int lpuart_probe(struct platform_device *pdev)
{
const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
struct device_node *np = pdev->dev.of_node;
struct lpuart_port *sport;
struct resource *res;
irq_handler_t handler;
int ret;
sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
if (!sport)
return -ENOMEM;
sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(sport->port.membase))
return PTR_ERR(sport->port.membase);
sport->port.membase += sdata->reg_off;
sport->port.mapbase = res->start + sdata->reg_off;
sport->port.dev = &pdev->dev;
sport->port.type = PORT_LPUART;
sport->devtype = sdata->devtype;
sport->rx_watermark = sdata->rx_watermark;
sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) ||
is_imx8qxp_lpuart(sport);
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
sport->port.irq = ret;
sport->port.iotype = sdata->iotype;
if (lpuart_is_32(sport))
sport->port.ops = &lpuart32_pops;
else
sport->port.ops = &lpuart_pops;
sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
sport->port.flags = UPF_BOOT_AUTOCONF;
if (lpuart_is_32(sport))
sport->port.rs485_config = lpuart32_config_rs485;
else
sport->port.rs485_config = lpuart_config_rs485;
sport->port.rs485_supported = lpuart_rs485_supported;
sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(sport->ipg_clk)) {
ret = PTR_ERR(sport->ipg_clk);
dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
return ret;
}
sport->baud_clk = NULL;
if (is_imx8qxp_lpuart(sport)) {
sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
if (IS_ERR(sport->baud_clk)) {
ret = PTR_ERR(sport->baud_clk);
dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
return ret;
}
}
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
return ret;
}
if (ret >= ARRAY_SIZE(lpuart_ports)) {
dev_err(&pdev->dev, "serial%d out of range\n", ret);
return -EINVAL;
}
sport->port.line = ret;
ret = lpuart_enable_clks(sport);
if (ret)
return ret;
sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
lpuart_ports[sport->port.line] = sport;
platform_set_drvdata(pdev, &sport->port);
if (lpuart_is_32(sport)) {
lpuart_reg.cons = LPUART32_CONSOLE;
handler = lpuart32_int;
} else {
lpuart_reg.cons = LPUART_CONSOLE;
handler = lpuart_int;
}
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
ret = lpuart_global_reset(sport);
if (ret)
goto failed_reset;
ret = uart_get_rs485_mode(&sport->port);
if (ret)
goto failed_get_rs485;
ret = uart_add_one_port(&lpuart_reg, &sport->port);
if (ret)
goto failed_attach_port;
ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
DRIVER_NAME, sport);
if (ret)
goto failed_irq_request;
return 0;
failed_irq_request:
uart_remove_one_port(&lpuart_reg, &sport->port);
failed_attach_port:
failed_get_rs485:
failed_reset:
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);
lpuart_disable_clks(sport);
return ret;
}
static int lpuart_remove(struct platform_device *pdev)
{
struct lpuart_port *sport = platform_get_drvdata(pdev);
uart_remove_one_port(&lpuart_reg, &sport->port);
lpuart_disable_clks(sport);
if (sport->dma_tx_chan)
dma_release_channel(sport->dma_tx_chan);
if (sport->dma_rx_chan)
dma_release_channel(sport->dma_rx_chan);
pm_runtime_disable(&pdev->dev);
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_dont_use_autosuspend(&pdev->dev);
return 0;
}
static int lpuart_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct lpuart_port *sport = platform_get_drvdata(pdev);
lpuart_disable_clks(sport);
return 0;
};
static int lpuart_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct lpuart_port *sport = platform_get_drvdata(pdev);
return lpuart_enable_clks(sport);
};
static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
{
unsigned int val, baud;
if (lpuart_is_32(sport)) {
val = lpuart32_read(&sport->port, UARTCTRL);
baud = lpuart32_read(&sport->port, UARTBAUD);
if (on) {
/* set rx_watermark to 0 in wakeup source mode */
lpuart32_write(&sport->port, 0, UARTWATER);
val |= UARTCTRL_RIE;
/* clear RXEDGIF flag before enable RXEDGIE interrupt */
lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
baud |= UARTBAUD_RXEDGIE;
} else {
val &= ~UARTCTRL_RIE;
baud &= ~UARTBAUD_RXEDGIE;
}
lpuart32_write(&sport->port, val, UARTCTRL);
lpuart32_write(&sport->port, baud, UARTBAUD);
} else {
val = readb(sport->port.membase + UARTCR2);
if (on)
val |= UARTCR2_RIE;
else
val &= ~UARTCR2_RIE;
writeb(val, sport->port.membase + UARTCR2);
}
}
static bool lpuart_uport_is_active(struct lpuart_port *sport)
{
struct tty_port *port = &sport->port.state->port;
struct tty_struct *tty;
struct device *tty_dev;
int may_wake = 0;
tty = tty_port_tty_get(port);
if (tty) {
tty_dev = tty->dev;
may_wake = tty_dev && device_may_wakeup(tty_dev);
tty_kref_put(tty);
}
if ((tty_port_initialized(port) && may_wake) ||
(!console_suspend_enabled && uart_console(&sport->port)))
return true;
return false;
}
static int lpuart_suspend_noirq(struct device *dev)
{
struct lpuart_port *sport = dev_get_drvdata(dev);
bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
if (lpuart_uport_is_active(sport))
serial_lpuart_enable_wakeup(sport, !!irq_wake);
pinctrl_pm_select_sleep_state(dev);
return 0;
}
static int lpuart_resume_noirq(struct device *dev)
{
struct lpuart_port *sport = dev_get_drvdata(dev);
unsigned int val;
pinctrl_pm_select_default_state(dev);
if (lpuart_uport_is_active(sport)) {
serial_lpuart_enable_wakeup(sport, false);
/* clear the wakeup flags */
if (lpuart_is_32(sport)) {
val = lpuart32_read(&sport->port, UARTSTAT);
lpuart32_write(&sport->port, val, UARTSTAT);
}
}
return 0;
}
static int lpuart_suspend(struct device *dev)
{
struct lpuart_port *sport = dev_get_drvdata(dev);
unsigned long temp, flags;
uart_suspend_port(&lpuart_reg, &sport->port);
if (lpuart_uport_is_active(sport)) {
spin_lock_irqsave(&sport->port.lock, flags);
if (lpuart_is_32(sport)) {
/* disable Rx/Tx and interrupts */
temp = lpuart32_read(&sport->port, UARTCTRL);
temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
lpuart32_write(&sport->port, temp, UARTCTRL);
} else {
/* disable Rx/Tx and interrupts */
temp = readb(sport->port.membase + UARTCR2);
temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
writeb(temp, sport->port.membase + UARTCR2);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
if (sport->lpuart_dma_rx_use) {
/*
* EDMA driver during suspend will forcefully release any
* non-idle DMA channels. If port wakeup is enabled or if port
* is console port or 'no_console_suspend' is set the Rx DMA
* cannot resume as expected, hence gracefully release the
* Rx DMA path before suspend and start Rx DMA path on resume.
*/
lpuart_dma_rx_free(&sport->port);
/* Disable Rx DMA to use UART port as wakeup source */
spin_lock_irqsave(&sport->port.lock, flags);
if (lpuart_is_32(sport)) {
temp = lpuart32_read(&sport->port, UARTBAUD);
lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
UARTBAUD);
} else {
writeb(readb(sport->port.membase + UARTCR5) &
~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
}
if (sport->lpuart_dma_tx_use) {
spin_lock_irqsave(&sport->port.lock, flags);
if (lpuart_is_32(sport)) {
temp = lpuart32_read(&sport->port, UARTBAUD);
temp &= ~UARTBAUD_TDMAE;
lpuart32_write(&sport->port, temp, UARTBAUD);
} else {
temp = readb(sport->port.membase + UARTCR5);
temp &= ~UARTCR5_TDMAS;
writeb(temp, sport->port.membase + UARTCR5);
}
spin_unlock_irqrestore(&sport->port.lock, flags);
sport->dma_tx_in_progress = false;
dmaengine_terminate_sync(sport->dma_tx_chan);
}
} else if (pm_runtime_active(sport->port.dev)) {
lpuart_disable_clks(sport);
pm_runtime_disable(sport->port.dev);
pm_runtime_set_suspended(sport->port.dev);
}
return 0;
}
static void lpuart_console_fixup(struct lpuart_port *sport)
{
struct tty_port *port = &sport->port.state->port;
struct uart_port *uport = &sport->port;
struct ktermios termios;
/* i.MX7ULP enter VLLS mode that lpuart module power off and registers
* all lost no matter the port is wakeup source.
* For console port, console baud rate setting lost and print messy
* log when enable the console port as wakeup source. To avoid the
* issue happen, user should not enable uart port as wakeup source
* in VLLS mode, or restore console setting here.
*/
if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
console_suspend_enabled && uart_console(&sport->port)) {
mutex_lock(&port->mutex);
memset(&termios, 0, sizeof(struct ktermios));
termios.c_cflag = uport->cons->cflag;
if (port->tty && termios.c_cflag == 0)
termios = port->tty->termios;
uport->ops->set_termios(uport, &termios, NULL);
mutex_unlock(&port->mutex);
}
}
static int lpuart_resume(struct device *dev)
{
struct lpuart_port *sport = dev_get_drvdata(dev);
int ret;
if (lpuart_uport_is_active(sport)) {
if (lpuart_is_32(sport))
lpuart32_hw_setup(sport);
else
lpuart_hw_setup(sport);
} else if (pm_runtime_active(sport->port.dev)) {
ret = lpuart_enable_clks(sport);
if (ret)
return ret;
pm_runtime_set_active(sport->port.dev);
pm_runtime_enable(sport->port.dev);
}
lpuart_console_fixup(sport);
uart_resume_port(&lpuart_reg, &sport->port);
return 0;
}
static const struct dev_pm_ops lpuart_pm_ops = {
RUNTIME_PM_OPS(lpuart_runtime_suspend,
lpuart_runtime_resume, NULL)
NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
lpuart_resume_noirq)
SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
};
static struct platform_driver lpuart_driver = {
.probe = lpuart_probe,
.remove = lpuart_remove,
.driver = {
.name = "fsl-lpuart",
.of_match_table = lpuart_dt_ids,
.pm = pm_ptr(&lpuart_pm_ops),
},
};
static int __init lpuart_serial_init(void)
{
int ret = uart_register_driver(&lpuart_reg);
if (ret)
return ret;
ret = platform_driver_register(&lpuart_driver);
if (ret)
uart_unregister_driver(&lpuart_reg);
return ret;
}
static void __exit lpuart_serial_exit(void)
{
platform_driver_unregister(&lpuart_driver);
uart_unregister_driver(&lpuart_reg);
}
module_init(lpuart_serial_init);
module_exit(lpuart_serial_exit);
MODULE_DESCRIPTION("Freescale lpuart serial port driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/fsl_lpuart.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
* Copyright (C) 2002 - 2011 Paul Mundt
* Copyright (C) 2015 Glider bvba
* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
*
* based off of the old drivers/char/sh-sci.c by:
*
* Copyright (C) 1999, 2000 Niibe Yutaka
* Copyright (C) 2000 Sugioka Toshinobu
* Modified to support multiple serial ports. Stuart Menefy (May 2000).
* Modified to support SecureEdge. David McCullough (2002)
* Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
* Removed SH7300 support (Jul 2007).
*/
#undef DEBUG
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/ctype.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/ktime.h>
#include <linux/major.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/scatterlist.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sysrq.h>
#include <linux/timer.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#ifdef CONFIG_SUPERH
#include <asm/sh_bios.h>
#include <asm/platform_early.h>
#endif
#include "serial_mctrl_gpio.h"
#include "sh-sci.h"
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
SCIx_RXI_IRQ,
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
SCIx_DRI_IRQ,
SCIx_TEI_IRQ,
SCIx_NR_IRQS,
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
};
#define SCIx_IRQ_IS_MUXED(port) \
((port)->irqs[SCIx_ERI_IRQ] == \
(port)->irqs[SCIx_RXI_IRQ]) || \
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
enum SCI_CLKS {
SCI_FCK, /* Functional Clock */
SCI_SCK, /* Optional External Clock */
SCI_BRG_INT, /* Optional BRG Internal Clock Source */
SCI_SCIF_CLK, /* Optional BRG External Clock Source */
SCI_NUM_CLKS
};
/* Bit x set means sampling rate x + 1 is supported */
#define SCI_SR(x) BIT((x) - 1)
#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
SCI_SR(19) | SCI_SR(27)
#define min_sr(_port) ffs((_port)->sampling_rate_mask)
#define max_sr(_port) fls((_port)->sampling_rate_mask)
/* Iterate over all supported sampling rates, from high to low */
#define for_each_sr(_sr, _port) \
for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
struct plat_sci_reg {
u8 offset, size;
};
struct sci_port_params {
const struct plat_sci_reg regs[SCIx_NR_REGS];
unsigned int fifosize;
unsigned int overrun_reg;
unsigned int overrun_mask;
unsigned int sampling_rate_mask;
unsigned int error_mask;
unsigned int error_clear;
};
struct sci_port {
struct uart_port port;
/* Platform configuration */
const struct sci_port_params *params;
const struct plat_sci_port *cfg;
unsigned int sampling_rate_mask;
resource_size_t reg_size;
struct mctrl_gpios *gpios;
/* Clocks */
struct clk *clks[SCI_NUM_CLKS];
unsigned long clk_rates[SCI_NUM_CLKS];
int irqs[SCIx_NR_IRQS];
char *irqstr[SCIx_NR_IRQS];
struct dma_chan *chan_tx;
struct dma_chan *chan_rx;
#ifdef CONFIG_SERIAL_SH_SCI_DMA
struct dma_chan *chan_tx_saved;
struct dma_chan *chan_rx_saved;
dma_cookie_t cookie_tx;
dma_cookie_t cookie_rx[2];
dma_cookie_t active_rx;
dma_addr_t tx_dma_addr;
unsigned int tx_dma_len;
struct scatterlist sg_rx[2];
void *rx_buf[2];
size_t buf_len_rx;
struct work_struct work_tx;
struct hrtimer rx_timer;
unsigned int rx_timeout; /* microseconds */
#endif
unsigned int rx_frame;
int rx_trigger;
struct timer_list rx_fifo_timer;
int rx_fifo_timeout;
u16 hscif_tot;
bool has_rtscts;
bool autorts;
};
#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
static struct sci_port sci_ports[SCI_NPORTS];
static unsigned long sci_ports_in_use;
static struct uart_driver sci_uart_driver;
static inline struct sci_port *
to_sci_port(struct uart_port *uart)
{
return container_of(uart, struct sci_port, port);
}
static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
/*
* Common SCI definitions, dependent on the port's regshift
* value.
*/
[SCIx_SCI_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 8 },
[SCBRR] = { 0x01, 8 },
[SCSCR] = { 0x02, 8 },
[SCxTDR] = { 0x03, 8 },
[SCxSR] = { 0x04, 8 },
[SCxRDR] = { 0x05, 8 },
},
.fifosize = 1,
.overrun_reg = SCxSR,
.overrun_mask = SCI_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
},
/*
* Common definitions for legacy IrDA ports.
*/
[SCIx_IRDA_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 8 },
[SCBRR] = { 0x02, 8 },
[SCSCR] = { 0x04, 8 },
[SCxTDR] = { 0x06, 8 },
[SCxSR] = { 0x08, 16 },
[SCxRDR] = { 0x0a, 8 },
[SCFCR] = { 0x0c, 8 },
[SCFDR] = { 0x0e, 16 },
},
.fifosize = 1,
.overrun_reg = SCxSR,
.overrun_mask = SCI_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
},
/*
* Common SCIFA definitions.
*/
[SCIx_SCIFA_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x20, 8 },
[SCxSR] = { 0x14, 16 },
[SCxRDR] = { 0x24, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCPCR] = { 0x30, 16 },
[SCPDR] = { 0x34, 16 },
},
.fifosize = 64,
.overrun_reg = SCxSR,
.overrun_mask = SCIFA_ORER,
.sampling_rate_mask = SCI_SR_SCIFAB,
.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
},
/*
* Common SCIFB definitions.
*/
[SCIx_SCIFB_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x40, 8 },
[SCxSR] = { 0x14, 16 },
[SCxRDR] = { 0x60, 8 },
[SCFCR] = { 0x18, 16 },
[SCTFDR] = { 0x38, 16 },
[SCRFDR] = { 0x3c, 16 },
[SCPCR] = { 0x30, 16 },
[SCPDR] = { 0x34, 16 },
},
.fifosize = 256,
.overrun_reg = SCxSR,
.overrun_mask = SCIFA_ORER,
.sampling_rate_mask = SCI_SR_SCIFAB,
.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
},
/*
* Common SH-2(A) SCIF definitions for ports with FIFO data
* count registers.
*/
[SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x0c, 8 },
[SCxSR] = { 0x10, 16 },
[SCxRDR] = { 0x14, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
* It looks like a normal SCIF with FIFO data, but with a
* compressed address space. Also, the break out of interrupts
* are different: ERI/BRI, RXI, TXI, TEI, DRI.
*/
[SCIx_RZ_SCIFA_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x02, 8 },
[SCSCR] = { 0x04, 16 },
[SCxTDR] = { 0x06, 8 },
[SCxSR] = { 0x08, 16 },
[SCxRDR] = { 0x0A, 8 },
[SCFCR] = { 0x0C, 16 },
[SCFDR] = { 0x0E, 16 },
[SCSPTR] = { 0x10, 16 },
[SCLSR] = { 0x12, 16 },
[SEMR] = { 0x14, 8 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* Common SH-3 SCIF definitions.
*/
[SCIx_SH3_SCIF_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 8 },
[SCBRR] = { 0x02, 8 },
[SCSCR] = { 0x04, 8 },
[SCxTDR] = { 0x06, 8 },
[SCxSR] = { 0x08, 16 },
[SCxRDR] = { 0x0a, 8 },
[SCFCR] = { 0x0c, 8 },
[SCFDR] = { 0x0e, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* Common SH-4(A) SCIF(B) definitions.
*/
[SCIx_SH4_SCIF_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x0c, 8 },
[SCxSR] = { 0x10, 16 },
[SCxRDR] = { 0x14, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* Common SCIF definitions for ports with a Baud Rate Generator for
* External Clock (BRG).
*/
[SCIx_SH4_SCIF_BRG_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x0c, 8 },
[SCxSR] = { 0x10, 16 },
[SCxRDR] = { 0x14, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
[SCDL] = { 0x30, 16 },
[SCCKS] = { 0x34, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* Common HSCIF definitions.
*/
[SCIx_HSCIF_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x0c, 8 },
[SCxSR] = { 0x10, 16 },
[SCxRDR] = { 0x14, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
[HSSRR] = { 0x40, 16 },
[SCDL] = { 0x30, 16 },
[SCCKS] = { 0x34, 16 },
[HSRTRGR] = { 0x54, 16 },
[HSTTRGR] = { 0x58, 16 },
},
.fifosize = 128,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR_RANGE(8, 32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
* register.
*/
[SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x0c, 8 },
[SCxSR] = { 0x10, 16 },
[SCxRDR] = { 0x14, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCLSR] = { 0x24, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* Common SH-4(A) SCIF(B) definitions for ports with FIFO data
* count registers.
*/
[SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x0c, 8 },
[SCxSR] = { 0x10, 16 },
[SCxRDR] = { 0x14, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
[SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
[SCRFDR] = { 0x20, 16 },
[SCSPTR] = { 0x24, 16 },
[SCLSR] = { 0x28, 16 },
},
.fifosize = 16,
.overrun_reg = SCLSR,
.overrun_mask = SCLSR_ORER,
.sampling_rate_mask = SCI_SR(32),
.error_mask = SCIF_DEFAULT_ERROR_MASK,
.error_clear = SCIF_ERROR_CLEAR,
},
/*
* SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
* registers.
*/
[SCIx_SH7705_SCIF_REGTYPE] = {
.regs = {
[SCSMR] = { 0x00, 16 },
[SCBRR] = { 0x04, 8 },
[SCSCR] = { 0x08, 16 },
[SCxTDR] = { 0x20, 8 },
[SCxSR] = { 0x14, 16 },
[SCxRDR] = { 0x24, 8 },
[SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
},
.fifosize = 64,
.overrun_reg = SCxSR,
.overrun_mask = SCIFA_ORER,
.sampling_rate_mask = SCI_SR(16),
.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
},
};
#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
/*
* The "offset" here is rather misleading, in that it refers to an enum
* value relative to the port mapping rather than the fixed offset
* itself, which needs to be manually retrieved from the platform's
* register map for the given port.
*/
static unsigned int sci_serial_in(struct uart_port *p, int offset)
{
const struct plat_sci_reg *reg = sci_getreg(p, offset);
if (reg->size == 8)
return ioread8(p->membase + (reg->offset << p->regshift));
else if (reg->size == 16)
return ioread16(p->membase + (reg->offset << p->regshift));
else
WARN(1, "Invalid register access\n");
return 0;
}
static void sci_serial_out(struct uart_port *p, int offset, int value)
{
const struct plat_sci_reg *reg = sci_getreg(p, offset);
if (reg->size == 8)
iowrite8(value, p->membase + (reg->offset << p->regshift));
else if (reg->size == 16)
iowrite16(value, p->membase + (reg->offset << p->regshift));
else
WARN(1, "Invalid register access\n");
}
static void sci_port_enable(struct sci_port *sci_port)
{
unsigned int i;
if (!sci_port->port.dev)
return;
pm_runtime_get_sync(sci_port->port.dev);
for (i = 0; i < SCI_NUM_CLKS; i++) {
clk_prepare_enable(sci_port->clks[i]);
sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
}
sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
}
static void sci_port_disable(struct sci_port *sci_port)
{
unsigned int i;
if (!sci_port->port.dev)
return;
for (i = SCI_NUM_CLKS; i-- > 0; )
clk_disable_unprepare(sci_port->clks[i]);
pm_runtime_put_sync(sci_port->port.dev);
}
static inline unsigned long port_rx_irq_mask(struct uart_port *port)
{
/*
* Not all ports (such as SCIFA) will support REIE. Rather than
* special-casing the port type, we check the port initialization
* IRQ enable mask to see whether the IRQ is desired at all. If
* it's unset, it's logically inferred that there's no point in
* testing for it.
*/
return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
}
static void sci_start_tx(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
unsigned short ctrl;
#ifdef CONFIG_SERIAL_SH_SCI_DMA
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
u16 new, scr = serial_port_in(port, SCSCR);
if (s->chan_tx)
new = scr | SCSCR_TDRQE;
else
new = scr & ~SCSCR_TDRQE;
if (new != scr)
serial_port_out(port, SCSCR, new);
}
if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
dma_submit_error(s->cookie_tx)) {
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
/* Switch irq from SCIF to DMA */
disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
s->cookie_tx = 0;
schedule_work(&s->work_tx);
}
#endif
if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
ctrl = serial_port_in(port, SCSCR);
/*
* For SCI, TE (transmit enable) must be set after setting TIE
* (transmit interrupt enable) or in the same instruction to start
* the transmit process.
*/
if (port->type == PORT_SCI)
ctrl |= SCSCR_TE;
serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
}
}
static void sci_stop_tx(struct uart_port *port)
{
unsigned short ctrl;
/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
ctrl = serial_port_in(port, SCSCR);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
ctrl &= ~SCSCR_TDRQE;
ctrl &= ~SCSCR_TIE;
serial_port_out(port, SCSCR, ctrl);
#ifdef CONFIG_SERIAL_SH_SCI_DMA
if (to_sci_port(port)->chan_tx &&
!dma_submit_error(to_sci_port(port)->cookie_tx)) {
dmaengine_terminate_async(to_sci_port(port)->chan_tx);
to_sci_port(port)->cookie_tx = -EINVAL;
}
#endif
}
static void sci_start_rx(struct uart_port *port)
{
unsigned short ctrl;
ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
ctrl &= ~SCSCR_RDRQE;
serial_port_out(port, SCSCR, ctrl);
}
static void sci_stop_rx(struct uart_port *port)
{
unsigned short ctrl;
ctrl = serial_port_in(port, SCSCR);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
ctrl &= ~SCSCR_RDRQE;
ctrl &= ~port_rx_irq_mask(port);
serial_port_out(port, SCSCR, ctrl);
}
static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
{
if (port->type == PORT_SCI) {
/* Just store the mask */
serial_port_out(port, SCxSR, mask);
} else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
/* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
/* Only clear the status bits we want to clear */
serial_port_out(port, SCxSR,
serial_port_in(port, SCxSR) & mask);
} else {
/* Store the mask, clear parity/framing errors */
serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
}
}
#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
#ifdef CONFIG_CONSOLE_POLL
static int sci_poll_get_char(struct uart_port *port)
{
unsigned short status;
int c;
do {
status = serial_port_in(port, SCxSR);
if (status & SCxSR_ERRORS(port)) {
sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
continue;
}
break;
} while (1);
if (!(status & SCxSR_RDxF(port)))
return NO_POLL_CHAR;
c = serial_port_in(port, SCxRDR);
/* Dummy read */
serial_port_in(port, SCxSR);
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
return c;
}
#endif
static void sci_poll_put_char(struct uart_port *port, unsigned char c)
{
unsigned short status;
do {
status = serial_port_in(port, SCxSR);
} while (!(status & SCxSR_TDxE(port)));
serial_port_out(port, SCxTDR, c);
sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
}
#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
CONFIG_SERIAL_SH_SCI_EARLYCON */
static void sci_init_pins(struct uart_port *port, unsigned int cflag)
{
struct sci_port *s = to_sci_port(port);
/*
* Use port-specific handler if provided.
*/
if (s->cfg->ops && s->cfg->ops->init_pins) {
s->cfg->ops->init_pins(port, cflag);
return;
}
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
u16 data = serial_port_in(port, SCPDR);
u16 ctrl = serial_port_in(port, SCPCR);
/* Enable RXD and TXD pin functions */
ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
if (to_sci_port(port)->has_rtscts) {
/* RTS# is output, active low, unless autorts */
if (!(port->mctrl & TIOCM_RTS)) {
ctrl |= SCPCR_RTSC;
data |= SCPDR_RTSD;
} else if (!s->autorts) {
ctrl |= SCPCR_RTSC;
data &= ~SCPDR_RTSD;
} else {
/* Enable RTS# pin function */
ctrl &= ~SCPCR_RTSC;
}
/* Enable CTS# pin function */
ctrl &= ~SCPCR_CTSC;
}
serial_port_out(port, SCPDR, data);
serial_port_out(port, SCPCR, ctrl);
} else if (sci_getreg(port, SCSPTR)->size) {
u16 status = serial_port_in(port, SCSPTR);
/* RTS# is always output; and active low, unless autorts */
status |= SCSPTR_RTSIO;
if (!(port->mctrl & TIOCM_RTS))
status |= SCSPTR_RTSDT;
else if (!s->autorts)
status &= ~SCSPTR_RTSDT;
/* CTS# and SCK are inputs */
status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
serial_port_out(port, SCSPTR, status);
}
}
static int sci_txfill(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
const struct plat_sci_reg *reg;
reg = sci_getreg(port, SCTFDR);
if (reg->size)
return serial_port_in(port, SCTFDR) & fifo_mask;
reg = sci_getreg(port, SCFDR);
if (reg->size)
return serial_port_in(port, SCFDR) >> 8;
return !(serial_port_in(port, SCxSR) & SCI_TDRE);
}
static int sci_txroom(struct uart_port *port)
{
return port->fifosize - sci_txfill(port);
}
static int sci_rxfill(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
const struct plat_sci_reg *reg;
reg = sci_getreg(port, SCRFDR);
if (reg->size)
return serial_port_in(port, SCRFDR) & fifo_mask;
reg = sci_getreg(port, SCFDR);
if (reg->size)
return serial_port_in(port, SCFDR) & fifo_mask;
return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
}
/* ********************************************************************** *
* the interrupt related routines *
* ********************************************************************** */
static void sci_transmit_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->state->xmit;
unsigned int stopped = uart_tx_stopped(port);
unsigned short status;
unsigned short ctrl;
int count;
status = serial_port_in(port, SCxSR);
if (!(status & SCxSR_TDxE(port))) {
ctrl = serial_port_in(port, SCSCR);
if (uart_circ_empty(xmit))
ctrl &= ~SCSCR_TIE;
else
ctrl |= SCSCR_TIE;
serial_port_out(port, SCSCR, ctrl);
return;
}
count = sci_txroom(port);
do {
unsigned char c;
if (port->x_char) {
c = port->x_char;
port->x_char = 0;
} else if (!uart_circ_empty(xmit) && !stopped) {
c = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
} else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
ctrl = serial_port_in(port, SCSCR);
ctrl &= ~SCSCR_TE;
serial_port_out(port, SCSCR, ctrl);
return;
} else {
break;
}
serial_port_out(port, SCxTDR, c);
port->icount.tx++;
} while (--count > 0);
sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
if (port->type == PORT_SCI) {
ctrl = serial_port_in(port, SCSCR);
ctrl &= ~SCSCR_TIE;
ctrl |= SCSCR_TEIE;
serial_port_out(port, SCSCR, ctrl);
}
sci_stop_tx(port);
}
}
static void sci_receive_chars(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
int i, count, copied = 0;
unsigned short status;
unsigned char flag;
status = serial_port_in(port, SCxSR);
if (!(status & SCxSR_RDxF(port)))
return;
while (1) {
/* Don't copy more bytes than there is room for in the buffer */
count = tty_buffer_request_room(tport, sci_rxfill(port));
/* If for any reason we can't copy more data, we're done! */
if (count == 0)
break;
if (port->type == PORT_SCI) {
char c = serial_port_in(port, SCxRDR);
if (uart_handle_sysrq_char(port, c))
count = 0;
else
tty_insert_flip_char(tport, c, TTY_NORMAL);
} else {
for (i = 0; i < count; i++) {
char c;
if (port->type == PORT_SCIF ||
port->type == PORT_HSCIF) {
status = serial_port_in(port, SCxSR);
c = serial_port_in(port, SCxRDR);
} else {
c = serial_port_in(port, SCxRDR);
status = serial_port_in(port, SCxSR);
}
if (uart_handle_sysrq_char(port, c)) {
count--; i--;
continue;
}
/* Store data and status */
if (status & SCxSR_FER(port)) {
flag = TTY_FRAME;
port->icount.frame++;
} else if (status & SCxSR_PER(port)) {
flag = TTY_PARITY;
port->icount.parity++;
} else
flag = TTY_NORMAL;
tty_insert_flip_char(tport, c, flag);
}
}
serial_port_in(port, SCxSR); /* dummy read */
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
copied += count;
port->icount.rx += count;
}
if (copied) {
/* Tell the rest of the system the news. New characters! */
tty_flip_buffer_push(tport);
} else {
/* TTY buffers full; read from RX reg to prevent lockup */
serial_port_in(port, SCxRDR);
serial_port_in(port, SCxSR); /* dummy read */
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
}
}
static int sci_handle_errors(struct uart_port *port)
{
int copied = 0;
unsigned short status = serial_port_in(port, SCxSR);
struct tty_port *tport = &port->state->port;
struct sci_port *s = to_sci_port(port);
/* Handle overruns */
if (status & s->params->overrun_mask) {
port->icount.overrun++;
/* overrun error */
if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
copied++;
}
if (status & SCxSR_FER(port)) {
/* frame error */
port->icount.frame++;
if (tty_insert_flip_char(tport, 0, TTY_FRAME))
copied++;
}
if (status & SCxSR_PER(port)) {
/* parity error */
port->icount.parity++;
if (tty_insert_flip_char(tport, 0, TTY_PARITY))
copied++;
}
if (copied)
tty_flip_buffer_push(tport);
return copied;
}
static int sci_handle_fifo_overrun(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
struct sci_port *s = to_sci_port(port);
const struct plat_sci_reg *reg;
int copied = 0;
u16 status;
reg = sci_getreg(port, s->params->overrun_reg);
if (!reg->size)
return 0;
status = serial_port_in(port, s->params->overrun_reg);
if (status & s->params->overrun_mask) {
status &= ~s->params->overrun_mask;
serial_port_out(port, s->params->overrun_reg, status);
port->icount.overrun++;
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
tty_flip_buffer_push(tport);
copied++;
}
return copied;
}
static int sci_handle_breaks(struct uart_port *port)
{
int copied = 0;
unsigned short status = serial_port_in(port, SCxSR);
struct tty_port *tport = &port->state->port;
if (uart_handle_break(port))
return 0;
if (status & SCxSR_BRK(port)) {
port->icount.brk++;
/* Notify of BREAK */
if (tty_insert_flip_char(tport, 0, TTY_BREAK))
copied++;
}
if (copied)
tty_flip_buffer_push(tport);
copied += sci_handle_fifo_overrun(port);
return copied;
}
static int scif_set_rtrg(struct uart_port *port, int rx_trig)
{
unsigned int bits;
if (rx_trig >= port->fifosize)
rx_trig = port->fifosize - 1;
if (rx_trig < 1)
rx_trig = 1;
/* HSCIF can be set to an arbitrary level. */
if (sci_getreg(port, HSRTRGR)->size) {
serial_port_out(port, HSRTRGR, rx_trig);
return rx_trig;
}
switch (port->type) {
case PORT_SCIF:
if (rx_trig < 4) {
bits = 0;
rx_trig = 1;
} else if (rx_trig < 8) {
bits = SCFCR_RTRG0;
rx_trig = 4;
} else if (rx_trig < 14) {
bits = SCFCR_RTRG1;
rx_trig = 8;
} else {
bits = SCFCR_RTRG0 | SCFCR_RTRG1;
rx_trig = 14;
}
break;
case PORT_SCIFA:
case PORT_SCIFB:
if (rx_trig < 16) {
bits = 0;
rx_trig = 1;
} else if (rx_trig < 32) {
bits = SCFCR_RTRG0;
rx_trig = 16;
} else if (rx_trig < 48) {
bits = SCFCR_RTRG1;
rx_trig = 32;
} else {
bits = SCFCR_RTRG0 | SCFCR_RTRG1;
rx_trig = 48;
}
break;
default:
WARN(1, "unknown FIFO configuration");
return 1;
}
serial_port_out(port, SCFCR,
(serial_port_in(port, SCFCR) &
~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
return rx_trig;
}
static int scif_rtrg_enabled(struct uart_port *port)
{
if (sci_getreg(port, HSRTRGR)->size)
return serial_port_in(port, HSRTRGR) != 0;
else
return (serial_port_in(port, SCFCR) &
(SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
}
static void rx_fifo_timer_fn(struct timer_list *t)
{
struct sci_port *s = from_timer(s, t, rx_fifo_timer);
struct uart_port *port = &s->port;
dev_dbg(port->dev, "Rx timed out\n");
scif_set_rtrg(port, 1);
}
static ssize_t rx_fifo_trigger_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct uart_port *port = dev_get_drvdata(dev);
struct sci_port *sci = to_sci_port(port);
return sprintf(buf, "%d\n", sci->rx_trigger);
}
static ssize_t rx_fifo_trigger_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct uart_port *port = dev_get_drvdata(dev);
struct sci_port *sci = to_sci_port(port);
int ret;
long r;
ret = kstrtol(buf, 0, &r);
if (ret)
return ret;
sci->rx_trigger = scif_set_rtrg(port, r);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
scif_set_rtrg(port, 1);
return count;
}
static DEVICE_ATTR_RW(rx_fifo_trigger);
static ssize_t rx_fifo_timeout_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct uart_port *port = dev_get_drvdata(dev);
struct sci_port *sci = to_sci_port(port);
int v;
if (port->type == PORT_HSCIF)
v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
else
v = sci->rx_fifo_timeout;
return sprintf(buf, "%d\n", v);
}
static ssize_t rx_fifo_timeout_store(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t count)
{
struct uart_port *port = dev_get_drvdata(dev);
struct sci_port *sci = to_sci_port(port);
int ret;
long r;
ret = kstrtol(buf, 0, &r);
if (ret)
return ret;
if (port->type == PORT_HSCIF) {
if (r < 0 || r > 3)
return -EINVAL;
sci->hscif_tot = r << HSSCR_TOT_SHIFT;
} else {
sci->rx_fifo_timeout = r;
scif_set_rtrg(port, 1);
if (r > 0)
timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
}
return count;
}
static DEVICE_ATTR_RW(rx_fifo_timeout);
#ifdef CONFIG_SERIAL_SH_SCI_DMA
static void sci_dma_tx_complete(void *arg)
{
struct sci_port *s = arg;
struct uart_port *port = &s->port;
struct circ_buf *xmit = &port->state->xmit;
unsigned long flags;
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
spin_lock_irqsave(&port->lock, flags);
uart_xmit_advance(port, s->tx_dma_len);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (!uart_circ_empty(xmit)) {
s->cookie_tx = 0;
schedule_work(&s->work_tx);
} else {
s->cookie_tx = -EINVAL;
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
u16 ctrl = serial_port_in(port, SCSCR);
serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
/* Switch irq from DMA to SCIF */
dmaengine_pause(s->chan_tx_saved);
enable_irq(s->irqs[SCIx_TXI_IRQ]);
}
}
}
spin_unlock_irqrestore(&port->lock, flags);
}
/* Locking: called with port lock held */
static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
{
struct uart_port *port = &s->port;
struct tty_port *tport = &port->state->port;
int copied;
copied = tty_insert_flip_string(tport, buf, count);
if (copied < count)
port->icount.buf_overrun++;
port->icount.rx += copied;
return copied;
}
static int sci_dma_rx_find_active(struct sci_port *s)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
if (s->active_rx == s->cookie_rx[i])
return i;
return -1;
}
static void sci_dma_rx_chan_invalidate(struct sci_port *s)
{
unsigned int i;
s->chan_rx = NULL;
for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
s->cookie_rx[i] = -EINVAL;
s->active_rx = 0;
}
static void sci_dma_rx_release(struct sci_port *s)
{
struct dma_chan *chan = s->chan_rx_saved;
s->chan_rx_saved = NULL;
sci_dma_rx_chan_invalidate(s);
dmaengine_terminate_sync(chan);
dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
sg_dma_address(&s->sg_rx[0]));
dma_release_channel(chan);
}
static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
{
long sec = usec / 1000000;
long nsec = (usec % 1000000) * 1000;
ktime_t t = ktime_set(sec, nsec);
hrtimer_start(hrt, t, HRTIMER_MODE_REL);
}
static void sci_dma_rx_reenable_irq(struct sci_port *s)
{
struct uart_port *port = &s->port;
u16 scr;
/* Direct new serial port interrupts back to CPU */
scr = serial_port_in(port, SCSCR);
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
enable_irq(s->irqs[SCIx_RXI_IRQ]);
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
scif_set_rtrg(port, s->rx_trigger);
else
scr &= ~SCSCR_RDRQE;
}
serial_port_out(port, SCSCR, scr | SCSCR_RIE);
}
static void sci_dma_rx_complete(void *arg)
{
struct sci_port *s = arg;
struct dma_chan *chan = s->chan_rx;
struct uart_port *port = &s->port;
struct dma_async_tx_descriptor *desc;
unsigned long flags;
int active, count = 0;
dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
s->active_rx);
spin_lock_irqsave(&port->lock, flags);
active = sci_dma_rx_find_active(s);
if (active >= 0)
count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
start_hrtimer_us(&s->rx_timer, s->rx_timeout);
if (count)
tty_flip_buffer_push(&port->state->port);
desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc)
goto fail;
desc->callback = sci_dma_rx_complete;
desc->callback_param = s;
s->cookie_rx[active] = dmaengine_submit(desc);
if (dma_submit_error(s->cookie_rx[active]))
goto fail;
s->active_rx = s->cookie_rx[!active];
dma_async_issue_pending(chan);
spin_unlock_irqrestore(&port->lock, flags);
dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
__func__, s->cookie_rx[active], active, s->active_rx);
return;
fail:
spin_unlock_irqrestore(&port->lock, flags);
dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
/* Switch to PIO */
spin_lock_irqsave(&port->lock, flags);
dmaengine_terminate_async(chan);
sci_dma_rx_chan_invalidate(s);
sci_dma_rx_reenable_irq(s);
spin_unlock_irqrestore(&port->lock, flags);
}
static void sci_dma_tx_release(struct sci_port *s)
{
struct dma_chan *chan = s->chan_tx_saved;
cancel_work_sync(&s->work_tx);
s->chan_tx_saved = s->chan_tx = NULL;
s->cookie_tx = -EINVAL;
dmaengine_terminate_sync(chan);
dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
DMA_TO_DEVICE);
dma_release_channel(chan);
}
static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
{
struct dma_chan *chan = s->chan_rx;
struct uart_port *port = &s->port;
unsigned long flags;
int i;
for (i = 0; i < 2; i++) {
struct scatterlist *sg = &s->sg_rx[i];
struct dma_async_tx_descriptor *desc;
desc = dmaengine_prep_slave_sg(chan,
sg, 1, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc)
goto fail;
desc->callback = sci_dma_rx_complete;
desc->callback_param = s;
s->cookie_rx[i] = dmaengine_submit(desc);
if (dma_submit_error(s->cookie_rx[i]))
goto fail;
}
s->active_rx = s->cookie_rx[0];
dma_async_issue_pending(chan);
return 0;
fail:
/* Switch to PIO */
if (!port_lock_held)
spin_lock_irqsave(&port->lock, flags);
if (i)
dmaengine_terminate_async(chan);
sci_dma_rx_chan_invalidate(s);
sci_start_rx(port);
if (!port_lock_held)
spin_unlock_irqrestore(&port->lock, flags);
return -EAGAIN;
}
static void sci_dma_tx_work_fn(struct work_struct *work)
{
struct sci_port *s = container_of(work, struct sci_port, work_tx);
struct dma_async_tx_descriptor *desc;
struct dma_chan *chan = s->chan_tx;
struct uart_port *port = &s->port;
struct circ_buf *xmit = &port->state->xmit;
unsigned long flags;
dma_addr_t buf;
int head, tail;
/*
* DMA is idle now.
* Port xmit buffer is already mapped, and it is one page... Just adjust
* offsets and lengths. Since it is a circular buffer, we have to
* transmit till the end, and then the rest. Take the port lock to get a
* consistent xmit buffer state.
*/
spin_lock_irq(&port->lock);
head = xmit->head;
tail = xmit->tail;
buf = s->tx_dma_addr + tail;
s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
if (!s->tx_dma_len) {
/* Transmit buffer has been flushed */
spin_unlock_irq(&port->lock);
return;
}
desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
spin_unlock_irq(&port->lock);
dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
goto switch_to_pio;
}
dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
DMA_TO_DEVICE);
desc->callback = sci_dma_tx_complete;
desc->callback_param = s;
s->cookie_tx = dmaengine_submit(desc);
if (dma_submit_error(s->cookie_tx)) {
spin_unlock_irq(&port->lock);
dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
goto switch_to_pio;
}
spin_unlock_irq(&port->lock);
dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
__func__, xmit->buf, tail, head, s->cookie_tx);
dma_async_issue_pending(chan);
return;
switch_to_pio:
spin_lock_irqsave(&port->lock, flags);
s->chan_tx = NULL;
sci_start_tx(port);
spin_unlock_irqrestore(&port->lock, flags);
return;
}
static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
{
struct sci_port *s = container_of(t, struct sci_port, rx_timer);
struct dma_chan *chan = s->chan_rx;
struct uart_port *port = &s->port;
struct dma_tx_state state;
enum dma_status status;
unsigned long flags;
unsigned int read;
int active, count;
dev_dbg(port->dev, "DMA Rx timed out\n");
spin_lock_irqsave(&port->lock, flags);
active = sci_dma_rx_find_active(s);
if (active < 0) {
spin_unlock_irqrestore(&port->lock, flags);
return HRTIMER_NORESTART;
}
status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
if (status == DMA_COMPLETE) {
spin_unlock_irqrestore(&port->lock, flags);
dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
s->active_rx, active);
/* Let packet complete handler take care of the packet */
return HRTIMER_NORESTART;
}
dmaengine_pause(chan);
/*
* sometimes DMA transfer doesn't stop even if it is stopped and
* data keeps on coming until transaction is complete so check
* for DMA_COMPLETE again
* Let packet complete handler take care of the packet
*/
status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
if (status == DMA_COMPLETE) {
spin_unlock_irqrestore(&port->lock, flags);
dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
return HRTIMER_NORESTART;
}
/* Handle incomplete DMA receive */
dmaengine_terminate_async(s->chan_rx);
read = sg_dma_len(&s->sg_rx[active]) - state.residue;
if (read) {
count = sci_dma_rx_push(s, s->rx_buf[active], read);
if (count)
tty_flip_buffer_push(&port->state->port);
}
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
sci_dma_rx_submit(s, true);
sci_dma_rx_reenable_irq(s);
spin_unlock_irqrestore(&port->lock, flags);
return HRTIMER_NORESTART;
}
static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
enum dma_transfer_direction dir)
{
struct dma_chan *chan;
struct dma_slave_config cfg;
int ret;
chan = dma_request_slave_channel(port->dev,
dir == DMA_MEM_TO_DEV ? "tx" : "rx");
if (!chan) {
dev_dbg(port->dev, "dma_request_slave_channel failed\n");
return NULL;
}
memset(&cfg, 0, sizeof(cfg));
cfg.direction = dir;
cfg.dst_addr = port->mapbase +
(sci_getreg(port, SCxTDR)->offset << port->regshift);
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
cfg.src_addr = port->mapbase +
(sci_getreg(port, SCxRDR)->offset << port->regshift);
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
ret = dmaengine_slave_config(chan, &cfg);
if (ret) {
dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
dma_release_channel(chan);
return NULL;
}
return chan;
}
static void sci_request_dma(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
struct dma_chan *chan;
dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
/*
* DMA on console may interfere with Kernel log messages which use
* plain putchar(). So, simply don't use it with a console.
*/
if (uart_console(port))
return;
if (!port->dev->of_node)
return;
s->cookie_tx = -EINVAL;
/*
* Don't request a dma channel if no channel was specified
* in the device tree.
*/
if (!of_property_present(port->dev->of_node, "dmas"))
return;
chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
if (chan) {
/* UART circular tx buffer is an aligned page. */
s->tx_dma_addr = dma_map_single(chan->device->dev,
port->state->xmit.buf,
UART_XMIT_SIZE,
DMA_TO_DEVICE);
if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
dma_release_channel(chan);
} else {
dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
__func__, UART_XMIT_SIZE,
port->state->xmit.buf, &s->tx_dma_addr);
INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
s->chan_tx_saved = s->chan_tx = chan;
}
}
chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
if (chan) {
unsigned int i;
dma_addr_t dma;
void *buf;
s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
&dma, GFP_KERNEL);
if (!buf) {
dev_warn(port->dev,
"Failed to allocate Rx dma buffer, using PIO\n");
dma_release_channel(chan);
return;
}
for (i = 0; i < 2; i++) {
struct scatterlist *sg = &s->sg_rx[i];
sg_init_table(sg, 1);
s->rx_buf[i] = buf;
sg_dma_address(sg) = dma;
sg_dma_len(sg) = s->buf_len_rx;
buf += s->buf_len_rx;
dma += s->buf_len_rx;
}
hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
s->rx_timer.function = sci_dma_rx_timer_fn;
s->chan_rx_saved = s->chan_rx = chan;
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
sci_dma_rx_submit(s, false);
}
}
static void sci_free_dma(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
if (s->chan_tx_saved)
sci_dma_tx_release(s);
if (s->chan_rx_saved)
sci_dma_rx_release(s);
}
static void sci_flush_buffer(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
/*
* In uart_flush_buffer(), the xmit circular buffer has just been
* cleared, so we have to reset tx_dma_len accordingly, and stop any
* pending transfers
*/
s->tx_dma_len = 0;
if (s->chan_tx) {
dmaengine_terminate_async(s->chan_tx);
s->cookie_tx = -EINVAL;
}
}
#else /* !CONFIG_SERIAL_SH_SCI_DMA */
static inline void sci_request_dma(struct uart_port *port)
{
}
static inline void sci_free_dma(struct uart_port *port)
{
}
#define sci_flush_buffer NULL
#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
{
struct uart_port *port = ptr;
struct sci_port *s = to_sci_port(port);
#ifdef CONFIG_SERIAL_SH_SCI_DMA
if (s->chan_rx) {
u16 scr = serial_port_in(port, SCSCR);
u16 ssr = serial_port_in(port, SCxSR);
/* Disable future Rx interrupts */
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
scif_set_rtrg(port, 1);
scr |= SCSCR_RIE;
} else {
scr |= SCSCR_RDRQE;
}
} else {
if (sci_dma_rx_submit(s, false) < 0)
goto handle_pio;
scr &= ~SCSCR_RIE;
}
serial_port_out(port, SCSCR, scr);
/* Clear current interrupt */
serial_port_out(port, SCxSR,
ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
jiffies, s->rx_timeout);
start_hrtimer_us(&s->rx_timer, s->rx_timeout);
return IRQ_HANDLED;
}
handle_pio:
#endif
if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
if (!scif_rtrg_enabled(port))
scif_set_rtrg(port, s->rx_trigger);
mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
}
/* I think sci_receive_chars has to be called irrespective
* of whether the I_IXOFF is set, otherwise, how is the interrupt
* to be disabled?
*/
sci_receive_chars(port);
return IRQ_HANDLED;
}
static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
{
struct uart_port *port = ptr;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
sci_transmit_chars(port);
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
{
struct uart_port *port = ptr;
unsigned long flags;
unsigned short ctrl;
if (port->type != PORT_SCI)
return sci_tx_interrupt(irq, ptr);
spin_lock_irqsave(&port->lock, flags);
ctrl = serial_port_in(port, SCSCR);
ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
serial_port_out(port, SCSCR, ctrl);
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t sci_br_interrupt(int irq, void *ptr)
{
struct uart_port *port = ptr;
/* Handle BREAKs */
sci_handle_breaks(port);
/* drop invalid character received before break was detected */
serial_port_in(port, SCxRDR);
sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
return IRQ_HANDLED;
}
static irqreturn_t sci_er_interrupt(int irq, void *ptr)
{
struct uart_port *port = ptr;
struct sci_port *s = to_sci_port(port);
if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
/* Break and Error interrupts are muxed */
unsigned short ssr_status = serial_port_in(port, SCxSR);
/* Break Interrupt */
if (ssr_status & SCxSR_BRK(port))
sci_br_interrupt(irq, ptr);
/* Break only? */
if (!(ssr_status & SCxSR_ERRORS(port)))
return IRQ_HANDLED;
}
/* Handle errors */
if (port->type == PORT_SCI) {
if (sci_handle_errors(port)) {
/* discard character in rx buffer */
serial_port_in(port, SCxSR);
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
}
} else {
sci_handle_fifo_overrun(port);
if (!s->chan_rx)
sci_receive_chars(port);
}
sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
/* Kick the transmission */
if (!s->chan_tx)
sci_tx_interrupt(irq, ptr);
return IRQ_HANDLED;
}
static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
{
unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
struct uart_port *port = ptr;
struct sci_port *s = to_sci_port(port);
irqreturn_t ret = IRQ_NONE;
ssr_status = serial_port_in(port, SCxSR);
scr_status = serial_port_in(port, SCSCR);
if (s->params->overrun_reg == SCxSR)
orer_status = ssr_status;
else if (sci_getreg(port, s->params->overrun_reg)->size)
orer_status = serial_port_in(port, s->params->overrun_reg);
err_enabled = scr_status & port_rx_irq_mask(port);
/* Tx Interrupt */
if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
!s->chan_tx)
ret = sci_tx_interrupt(irq, ptr);
/*
* Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
* DR flags
*/
if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
(scr_status & SCSCR_RIE))
ret = sci_rx_interrupt(irq, ptr);
/* Error Interrupt */
if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
ret = sci_er_interrupt(irq, ptr);
/* Break Interrupt */
if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
(ssr_status & SCxSR_BRK(port)) && err_enabled)
ret = sci_br_interrupt(irq, ptr);
/* Overrun Interrupt */
if (orer_status & s->params->overrun_mask) {
sci_handle_fifo_overrun(port);
ret = IRQ_HANDLED;
}
return ret;
}
static const struct sci_irq_desc {
const char *desc;
irq_handler_t handler;
} sci_irq_desc[] = {
/*
* Split out handlers, the default case.
*/
[SCIx_ERI_IRQ] = {
.desc = "rx err",
.handler = sci_er_interrupt,
},
[SCIx_RXI_IRQ] = {
.desc = "rx full",
.handler = sci_rx_interrupt,
},
[SCIx_TXI_IRQ] = {
.desc = "tx empty",
.handler = sci_tx_interrupt,
},
[SCIx_BRI_IRQ] = {
.desc = "break",
.handler = sci_br_interrupt,
},
[SCIx_DRI_IRQ] = {
.desc = "rx ready",
.handler = sci_rx_interrupt,
},
[SCIx_TEI_IRQ] = {
.desc = "tx end",
.handler = sci_tx_end_interrupt,
},
/*
* Special muxed handler.
*/
[SCIx_MUX_IRQ] = {
.desc = "mux",
.handler = sci_mpxed_interrupt,
},
};
static int sci_request_irq(struct sci_port *port)
{
struct uart_port *up = &port->port;
int i, j, w, ret = 0;
for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
const struct sci_irq_desc *desc;
int irq;
/* Check if already registered (muxed) */
for (w = 0; w < i; w++)
if (port->irqs[w] == port->irqs[i])
w = i + 1;
if (w > i)
continue;
if (SCIx_IRQ_IS_MUXED(port)) {
i = SCIx_MUX_IRQ;
irq = up->irq;
} else {
irq = port->irqs[i];
/*
* Certain port types won't support all of the
* available interrupt sources.
*/
if (unlikely(irq < 0))
continue;
}
desc = sci_irq_desc + i;
port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
dev_name(up->dev), desc->desc);
if (!port->irqstr[j]) {
ret = -ENOMEM;
goto out_nomem;
}
ret = request_irq(irq, desc->handler, up->irqflags,
port->irqstr[j], port);
if (unlikely(ret)) {
dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
goto out_noirq;
}
}
return 0;
out_noirq:
while (--i >= 0)
free_irq(port->irqs[i], port);
out_nomem:
while (--j >= 0)
kfree(port->irqstr[j]);
return ret;
}
static void sci_free_irq(struct sci_port *port)
{
int i, j;
/*
* Intentionally in reverse order so we iterate over the muxed
* IRQ first.
*/
for (i = 0; i < SCIx_NR_IRQS; i++) {
int irq = port->irqs[i];
/*
* Certain port types won't support all of the available
* interrupt sources.
*/
if (unlikely(irq < 0))
continue;
/* Check if already freed (irq was muxed) */
for (j = 0; j < i; j++)
if (port->irqs[j] == irq)
j = i + 1;
if (j > i)
continue;
free_irq(port->irqs[i], port);
kfree(port->irqstr[i]);
if (SCIx_IRQ_IS_MUXED(port)) {
/* If there's only one IRQ, we're done. */
return;
}
}
}
static unsigned int sci_tx_empty(struct uart_port *port)
{
unsigned short status = serial_port_in(port, SCxSR);
unsigned short in_tx_fifo = sci_txfill(port);
return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
}
static void sci_set_rts(struct uart_port *port, bool state)
{
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
u16 data = serial_port_in(port, SCPDR);
/* Active low */
if (state)
data &= ~SCPDR_RTSD;
else
data |= SCPDR_RTSD;
serial_port_out(port, SCPDR, data);
/* RTS# is output */
serial_port_out(port, SCPCR,
serial_port_in(port, SCPCR) | SCPCR_RTSC);
} else if (sci_getreg(port, SCSPTR)->size) {
u16 ctrl = serial_port_in(port, SCSPTR);
/* Active low */
if (state)
ctrl &= ~SCSPTR_RTSDT;
else
ctrl |= SCSPTR_RTSDT;
serial_port_out(port, SCSPTR, ctrl);
}
}
static bool sci_get_cts(struct uart_port *port)
{
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
/* Active low */
return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
} else if (sci_getreg(port, SCSPTR)->size) {
/* Active low */
return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
}
return true;
}
/*
* Modem control is a bit of a mixed bag for SCI(F) ports. Generally
* CTS/RTS is supported in hardware by at least one port and controlled
* via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
* handled via the ->init_pins() op, which is a bit of a one-way street,
* lacking any ability to defer pin control -- this will later be
* converted over to the GPIO framework).
*
* Other modes (such as loopback) are supported generically on certain
* port types, but not others. For these it's sufficient to test for the
* existence of the support register and simply ignore the port type.
*/
static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct sci_port *s = to_sci_port(port);
if (mctrl & TIOCM_LOOP) {
const struct plat_sci_reg *reg;
/*
* Standard loopback mode for SCFCR ports.
*/
reg = sci_getreg(port, SCFCR);
if (reg->size)
serial_port_out(port, SCFCR,
serial_port_in(port, SCFCR) |
SCFCR_LOOP);
}
mctrl_gpio_set(s->gpios, mctrl);
if (!s->has_rtscts)
return;
if (!(mctrl & TIOCM_RTS)) {
/* Disable Auto RTS */
serial_port_out(port, SCFCR,
serial_port_in(port, SCFCR) & ~SCFCR_MCE);
/* Clear RTS */
sci_set_rts(port, 0);
} else if (s->autorts) {
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
/* Enable RTS# pin function */
serial_port_out(port, SCPCR,
serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
}
/* Enable Auto RTS */
serial_port_out(port, SCFCR,
serial_port_in(port, SCFCR) | SCFCR_MCE);
} else {
/* Set RTS */
sci_set_rts(port, 1);
}
}
static unsigned int sci_get_mctrl(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
struct mctrl_gpios *gpios = s->gpios;
unsigned int mctrl = 0;
mctrl_gpio_get(gpios, &mctrl);
/*
* CTS/RTS is handled in hardware when supported, while nothing
* else is wired up.
*/
if (s->autorts) {
if (sci_get_cts(port))
mctrl |= TIOCM_CTS;
} else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
mctrl |= TIOCM_CTS;
}
if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
mctrl |= TIOCM_DSR;
if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
mctrl |= TIOCM_CAR;
return mctrl;
}
static void sci_enable_ms(struct uart_port *port)
{
mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
}
static void sci_break_ctl(struct uart_port *port, int break_state)
{
unsigned short scscr, scsptr;
unsigned long flags;
/* check whether the port has SCSPTR */
if (!sci_getreg(port, SCSPTR)->size) {
/*
* Not supported by hardware. Most parts couple break and rx
* interrupts together, with break detection always enabled.
*/
return;
}
spin_lock_irqsave(&port->lock, flags);
scsptr = serial_port_in(port, SCSPTR);
scscr = serial_port_in(port, SCSCR);
if (break_state == -1) {
scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
scscr &= ~SCSCR_TE;
} else {
scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
scscr |= SCSCR_TE;
}
serial_port_out(port, SCSPTR, scsptr);
serial_port_out(port, SCSCR, scscr);
spin_unlock_irqrestore(&port->lock, flags);
}
static int sci_startup(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
int ret;
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
sci_request_dma(port);
ret = sci_request_irq(s);
if (unlikely(ret < 0)) {
sci_free_dma(port);
return ret;
}
return 0;
}
static void sci_shutdown(struct uart_port *port)
{
struct sci_port *s = to_sci_port(port);
unsigned long flags;
u16 scr;
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
s->autorts = false;
mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
spin_lock_irqsave(&port->lock, flags);
sci_stop_rx(port);
sci_stop_tx(port);
/*
* Stop RX and TX, disable related interrupts, keep clock source
* and HSCIF TOT bits
*/
scr = serial_port_in(port, SCSCR);
serial_port_out(port, SCSCR, scr &
(SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
spin_unlock_irqrestore(&port->lock, flags);
#ifdef CONFIG_SERIAL_SH_SCI_DMA
if (s->chan_rx_saved) {
dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
port->line);
hrtimer_cancel(&s->rx_timer);
}
#endif
if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
del_timer_sync(&s->rx_fifo_timer);
sci_free_irq(s);
sci_free_dma(port);
}
static int sci_sck_calc(struct sci_port *s, unsigned int bps,
unsigned int *srr)
{
unsigned long freq = s->clk_rates[SCI_SCK];
int err, min_err = INT_MAX;
unsigned int sr;
if (s->port.type != PORT_HSCIF)
freq *= 2;
for_each_sr(sr, s) {
err = DIV_ROUND_CLOSEST(freq, sr) - bps;
if (abs(err) >= abs(min_err))
continue;
min_err = err;
*srr = sr - 1;
if (!err)
break;
}
dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
*srr + 1);
return min_err;
}
static int sci_brg_calc(struct sci_port *s, unsigned int bps,
unsigned long freq, unsigned int *dlr,
unsigned int *srr)
{
int err, min_err = INT_MAX;
unsigned int sr, dl;
if (s->port.type != PORT_HSCIF)
freq *= 2;
for_each_sr(sr, s) {
dl = DIV_ROUND_CLOSEST(freq, sr * bps);
dl = clamp(dl, 1U, 65535U);
err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
if (abs(err) >= abs(min_err))
continue;
min_err = err;
*dlr = dl;
*srr = sr - 1;
if (!err)
break;
}
dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
min_err, *dlr, *srr + 1);
return min_err;
}
/* calculate sample rate, BRR, and clock select */
static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
unsigned int *brr, unsigned int *srr,
unsigned int *cks)
{
unsigned long freq = s->clk_rates[SCI_FCK];
unsigned int sr, br, prediv, scrate, c;
int err, min_err = INT_MAX;
if (s->port.type != PORT_HSCIF)
freq *= 2;
/*
* Find the combination of sample rate and clock select with the
* smallest deviation from the desired baud rate.
* Prefer high sample rates to maximise the receive margin.
*
* M: Receive margin (%)
* N: Ratio of bit rate to clock (N = sampling rate)
* D: Clock duty (D = 0 to 1.0)
* L: Frame length (L = 9 to 12)
* F: Absolute value of clock frequency deviation
*
* M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
* (|D - 0.5| / N * (1 + F))|
* NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
*/
for_each_sr(sr, s) {
for (c = 0; c <= 3; c++) {
/* integerized formulas from HSCIF documentation */
prediv = sr << (2 * c + 1);
/*
* We need to calculate:
*
* br = freq / (prediv * bps) clamped to [1..256]
* err = freq / (br * prediv) - bps
*
* Watch out for overflow when calculating the desired
* sampling clock rate!
*/
if (bps > UINT_MAX / prediv)
break;
scrate = prediv * bps;
br = DIV_ROUND_CLOSEST(freq, scrate);
br = clamp(br, 1U, 256U);
err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
if (abs(err) >= abs(min_err))
continue;
min_err = err;
*brr = br - 1;
*srr = sr - 1;
*cks = c;
if (!err)
goto found;
}
}
found:
dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
min_err, *brr, *srr + 1, *cks);
return min_err;
}
static void sci_reset(struct uart_port *port)
{
const struct plat_sci_reg *reg;
unsigned int status;
struct sci_port *s = to_sci_port(port);
serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
reg = sci_getreg(port, SCFCR);
if (reg->size)
serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
sci_clear_SCxSR(port,
SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
SCxSR_BREAK_CLEAR(port));
if (sci_getreg(port, SCLSR)->size) {
status = serial_port_in(port, SCLSR);
status &= ~(SCLSR_TO | SCLSR_ORER);
serial_port_out(port, SCLSR, status);
}
if (s->rx_trigger > 1) {
if (s->rx_fifo_timeout) {
scif_set_rtrg(port, 1);
timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
} else {
if (port->type == PORT_SCIFA ||
port->type == PORT_SCIFB)
scif_set_rtrg(port, 1);
else
scif_set_rtrg(port, s->rx_trigger);
}
}
}
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
struct sci_port *s = to_sci_port(port);
const struct plat_sci_reg *reg;
int min_err = INT_MAX, err;
unsigned long max_freq = 0;
int best_clk = -1;
unsigned long flags;
if ((termios->c_cflag & CSIZE) == CS7) {
smr_val |= SCSMR_CHR;
} else {
termios->c_cflag &= ~CSIZE;
termios->c_cflag |= CS8;
}
if (termios->c_cflag & PARENB)
smr_val |= SCSMR_PE;
if (termios->c_cflag & PARODD)
smr_val |= SCSMR_PE | SCSMR_ODD;
if (termios->c_cflag & CSTOPB)
smr_val |= SCSMR_STOP;
/*
* earlyprintk comes here early on with port->uartclk set to zero.
* the clock framework is not up and running at this point so here
* we assume that 115200 is the maximum baud rate. please note that
* the baud rate is not programmed during earlyprintk - it is assumed
* that the previous boot loader has enabled required clocks and
* setup the baud rate generator hardware for us already.
*/
if (!port->uartclk) {
baud = uart_get_baud_rate(port, termios, old, 0, 115200);
goto done;
}
for (i = 0; i < SCI_NUM_CLKS; i++)
max_freq = max(max_freq, s->clk_rates[i]);
baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
if (!baud)
goto done;
/*
* There can be multiple sources for the sampling clock. Find the one
* that gives us the smallest deviation from the desired baud rate.
*/
/* Optional Undivided External Clock */
if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
port->type != PORT_SCIFB) {
err = sci_sck_calc(s, baud, &srr1);
if (abs(err) < abs(min_err)) {
best_clk = SCI_SCK;
scr_val = SCSCR_CKE1;
sccks = SCCKS_CKS;
min_err = err;
srr = srr1;
if (!err)
goto done;
}
}
/* Optional BRG Frequency Divided External Clock */
if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
&srr1);
if (abs(err) < abs(min_err)) {
best_clk = SCI_SCIF_CLK;
scr_val = SCSCR_CKE1;
sccks = 0;
min_err = err;
dl = dl1;
srr = srr1;
if (!err)
goto done;
}
}
/* Optional BRG Frequency Divided Internal Clock */
if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
&srr1);
if (abs(err) < abs(min_err)) {
best_clk = SCI_BRG_INT;
scr_val = SCSCR_CKE1;
sccks = SCCKS_XIN;
min_err = err;
dl = dl1;
srr = srr1;
if (!min_err)
goto done;
}
}
/* Divided Functional Clock using standard Bit Rate Register */
err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
if (abs(err) < abs(min_err)) {
best_clk = SCI_FCK;
scr_val = 0;
min_err = err;
brr = brr1;
srr = srr1;
cks = cks1;
}
done:
if (best_clk >= 0)
dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
s->clks[best_clk], baud, min_err);
sci_port_enable(s);
/*
* Program the optional External Baud Rate Generator (BRG) first.
* It controls the mux to select (H)SCK or frequency divided clock.
*/
if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
serial_port_out(port, SCDL, dl);
serial_port_out(port, SCCKS, sccks);
}
spin_lock_irqsave(&port->lock, flags);
sci_reset(port);
uart_update_timeout(port, termios->c_cflag, baud);
/* byte size and parity */
bits = tty_get_frame_size(termios->c_cflag);
if (sci_getreg(port, SEMR)->size)
serial_port_out(port, SEMR, 0);
if (best_clk >= 0) {
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
switch (srr + 1) {
case 5: smr_val |= SCSMR_SRC_5; break;
case 7: smr_val |= SCSMR_SRC_7; break;
case 11: smr_val |= SCSMR_SRC_11; break;
case 13: smr_val |= SCSMR_SRC_13; break;
case 16: smr_val |= SCSMR_SRC_16; break;
case 17: smr_val |= SCSMR_SRC_17; break;
case 19: smr_val |= SCSMR_SRC_19; break;
case 27: smr_val |= SCSMR_SRC_27; break;
}
smr_val |= cks;
serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
serial_port_out(port, SCSMR, smr_val);
serial_port_out(port, SCBRR, brr);
if (sci_getreg(port, HSSRR)->size) {
unsigned int hssrr = srr | HSCIF_SRE;
/* Calculate deviation from intended rate at the
* center of the last stop bit in sampling clocks.
*/
int last_stop = bits * 2 - 1;
int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
(int)(srr + 1),
2 * (int)baud);
if (abs(deviation) >= 2) {
/* At least two sampling clocks off at the
* last stop bit; we can increase the error
* margin by shifting the sampling point.
*/
int shift = clamp(deviation / 2, -8, 7);
hssrr |= (shift << HSCIF_SRHP_SHIFT) &
HSCIF_SRHP_MASK;
hssrr |= HSCIF_SRDE;
}
serial_port_out(port, HSSRR, hssrr);
}
/* Wait one bit interval */
udelay((1000000 + (baud - 1)) / baud);
} else {
/* Don't touch the bit rate configuration */
scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
smr_val |= serial_port_in(port, SCSMR) &
(SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
serial_port_out(port, SCSMR, smr_val);
}
sci_init_pins(port, termios->c_cflag);
port->status &= ~UPSTAT_AUTOCTS;
s->autorts = false;
reg = sci_getreg(port, SCFCR);
if (reg->size) {
unsigned short ctrl = serial_port_in(port, SCFCR);
if ((port->flags & UPF_HARD_FLOW) &&
(termios->c_cflag & CRTSCTS)) {
/* There is no CTS interrupt to restart the hardware */
port->status |= UPSTAT_AUTOCTS;
/* MCE is enabled when RTS is raised */
s->autorts = true;
}
/*
* As we've done a sci_reset() above, ensure we don't
* interfere with the FIFOs while toggling MCE. As the
* reset values could still be set, simply mask them out.
*/
ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
serial_port_out(port, SCFCR, ctrl);
}
if (port->flags & UPF_HARD_FLOW) {
/* Refresh (Auto) RTS */
sci_set_mctrl(port, port->mctrl);
}
/*
* For SCI, TE (transmit enable) must be set after setting TIE
* (transmit interrupt enable) or in the same instruction to
* start the transmitting process. So skip setting TE here for SCI.
*/
if (port->type != PORT_SCI)
scr_val |= SCSCR_TE;
scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
if ((srr + 1 == 5) &&
(port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
/*
* In asynchronous mode, when the sampling rate is 1/5, first
* received data may become invalid on some SCIFA and SCIFB.
* To avoid this problem wait more than 1 serial data time (1
* bit time x serial data number) after setting SCSCR.RE = 1.
*/
udelay(DIV_ROUND_UP(10 * 1000000, baud));
}
/* Calculate delay for 2 DMA buffers (4 FIFO). */
s->rx_frame = (10000 * bits) / (baud / 100);
#ifdef CONFIG_SERIAL_SH_SCI_DMA
s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
#endif
if ((termios->c_cflag & CREAD) != 0)
sci_start_rx(port);
spin_unlock_irqrestore(&port->lock, flags);
sci_port_disable(s);
if (UART_ENABLE_MS(port, termios->c_cflag))
sci_enable_ms(port);
}
static void sci_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
struct sci_port *sci_port = to_sci_port(port);
switch (state) {
case UART_PM_STATE_OFF:
sci_port_disable(sci_port);
break;
default:
sci_port_enable(sci_port);
break;
}
}
static const char *sci_type(struct uart_port *port)
{
switch (port->type) {
case PORT_IRDA:
return "irda";
case PORT_SCI:
return "sci";
case PORT_SCIF:
return "scif";
case PORT_SCIFA:
return "scifa";
case PORT_SCIFB:
return "scifb";
case PORT_HSCIF:
return "hscif";
}
return NULL;
}
static int sci_remap_port(struct uart_port *port)
{
struct sci_port *sport = to_sci_port(port);
/*
* Nothing to do if there's already an established membase.
*/
if (port->membase)
return 0;
if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
return -ENXIO;
}
} else {
/*
* For the simple (and majority of) cases where we don't
* need to do any remapping, just cast the cookie
* directly.
*/
port->membase = (void __iomem *)(uintptr_t)port->mapbase;
}
return 0;
}
static void sci_release_port(struct uart_port *port)
{
struct sci_port *sport = to_sci_port(port);
if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
iounmap(port->membase);
port->membase = NULL;
}
release_mem_region(port->mapbase, sport->reg_size);
}
static int sci_request_port(struct uart_port *port)
{
struct resource *res;
struct sci_port *sport = to_sci_port(port);
int ret;
res = request_mem_region(port->mapbase, sport->reg_size,
dev_name(port->dev));
if (unlikely(res == NULL)) {
dev_err(port->dev, "request_mem_region failed.");
return -EBUSY;
}
ret = sci_remap_port(port);
if (unlikely(ret != 0)) {
release_resource(res);
return ret;
}
return 0;
}
static void sci_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
struct sci_port *sport = to_sci_port(port);
port->type = sport->cfg->type;
sci_request_port(port);
}
}
static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
{
if (ser->baud_base < 2400)
/* No paper tape reader for Mitch.. */
return -EINVAL;
return 0;
}
static const struct uart_ops sci_uart_ops = {
.tx_empty = sci_tx_empty,
.set_mctrl = sci_set_mctrl,
.get_mctrl = sci_get_mctrl,
.start_tx = sci_start_tx,
.stop_tx = sci_stop_tx,
.stop_rx = sci_stop_rx,
.enable_ms = sci_enable_ms,
.break_ctl = sci_break_ctl,
.startup = sci_startup,
.shutdown = sci_shutdown,
.flush_buffer = sci_flush_buffer,
.set_termios = sci_set_termios,
.pm = sci_pm,
.type = sci_type,
.release_port = sci_release_port,
.request_port = sci_request_port,
.config_port = sci_config_port,
.verify_port = sci_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = sci_poll_get_char,
.poll_put_char = sci_poll_put_char,
#endif
};
static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
{
const char *clk_names[] = {
[SCI_FCK] = "fck",
[SCI_SCK] = "sck",
[SCI_BRG_INT] = "brg_int",
[SCI_SCIF_CLK] = "scif_clk",
};
struct clk *clk;
unsigned int i;
if (sci_port->cfg->type == PORT_HSCIF)
clk_names[SCI_SCK] = "hsck";
for (i = 0; i < SCI_NUM_CLKS; i++) {
clk = devm_clk_get_optional(dev, clk_names[i]);
if (IS_ERR(clk))
return PTR_ERR(clk);
if (!clk && i == SCI_FCK) {
/*
* Not all SH platforms declare a clock lookup entry
* for SCI devices, in which case we need to get the
* global "peripheral_clk" clock.
*/
clk = devm_clk_get(dev, "peripheral_clk");
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk),
"failed to get %s\n",
clk_names[i]);
}
if (!clk)
dev_dbg(dev, "failed to get %s\n", clk_names[i]);
else
dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
clk, clk_get_rate(clk));
sci_port->clks[i] = clk;
}
return 0;
}
static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port *cfg)
{
unsigned int regtype;
if (cfg->regtype != SCIx_PROBE_REGTYPE)
return &sci_port_params[cfg->regtype];
switch (cfg->type) {
case PORT_SCI:
regtype = SCIx_SCI_REGTYPE;
break;
case PORT_IRDA:
regtype = SCIx_IRDA_REGTYPE;
break;
case PORT_SCIFA:
regtype = SCIx_SCIFA_REGTYPE;
break;
case PORT_SCIFB:
regtype = SCIx_SCIFB_REGTYPE;
break;
case PORT_SCIF:
/*
* The SH-4 is a bit of a misnomer here, although that's
* where this particular port layout originated. This
* configuration (or some slight variation thereof)
* remains the dominant model for all SCIFs.
*/
regtype = SCIx_SH4_SCIF_REGTYPE;
break;
case PORT_HSCIF:
regtype = SCIx_HSCIF_REGTYPE;
break;
default:
pr_err("Can't probe register map for given port\n");
return NULL;
}
return &sci_port_params[regtype];
}
static int sci_init_single(struct platform_device *dev,
struct sci_port *sci_port, unsigned int index,
const struct plat_sci_port *p, bool early)
{
struct uart_port *port = &sci_port->port;
const struct resource *res;
unsigned int i;
int ret;
sci_port->cfg = p;
port->ops = &sci_uart_ops;
port->iotype = UPIO_MEM;
port->line = index;
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (res == NULL)
return -ENOMEM;
port->mapbase = res->start;
sci_port->reg_size = resource_size(res);
for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
if (i)
sci_port->irqs[i] = platform_get_irq_optional(dev, i);
else
sci_port->irqs[i] = platform_get_irq(dev, i);
}
/*
* The fourth interrupt on SCI port is transmit end interrupt, so
* shuffle the interrupts.
*/
if (p->type == PORT_SCI)
swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
/* The SCI generates several interrupts. They can be muxed together or
* connected to different interrupt lines. In the muxed case only one
* interrupt resource is specified as there is only one interrupt ID.
* In the non-muxed case, up to 6 interrupt signals might be generated
* from the SCI, however those signals might have their own individual
* interrupt ID numbers, or muxed together with another interrupt.
*/
if (sci_port->irqs[0] < 0)
return -ENXIO;
if (sci_port->irqs[1] < 0)
for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
sci_port->irqs[i] = sci_port->irqs[0];
sci_port->params = sci_probe_regmap(p);
if (unlikely(sci_port->params == NULL))
return -EINVAL;
switch (p->type) {
case PORT_SCIFB:
sci_port->rx_trigger = 48;
break;
case PORT_HSCIF:
sci_port->rx_trigger = 64;
break;
case PORT_SCIFA:
sci_port->rx_trigger = 32;
break;
case PORT_SCIF:
if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
/* RX triggering not implemented for this IP */
sci_port->rx_trigger = 1;
else
sci_port->rx_trigger = 8;
break;
default:
sci_port->rx_trigger = 1;
break;
}
sci_port->rx_fifo_timeout = 0;
sci_port->hscif_tot = 0;
/* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
* match the SoC datasheet, this should be investigated. Let platform
* data override the sampling rate for now.
*/
sci_port->sampling_rate_mask = p->sampling_rate
? SCI_SR(p->sampling_rate)
: sci_port->params->sampling_rate_mask;
if (!early) {
ret = sci_init_clocks(sci_port, &dev->dev);
if (ret < 0)
return ret;
port->dev = &dev->dev;
pm_runtime_enable(&dev->dev);
}
port->type = p->type;
port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
port->fifosize = sci_port->params->fifosize;
if (port->type == PORT_SCI && !dev->dev.of_node) {
if (sci_port->reg_size >= 0x20)
port->regshift = 2;
else
port->regshift = 1;
}
/*
* The UART port needs an IRQ value, so we peg this to the RX IRQ
* for the multi-IRQ ports, which is where we are primarily
* concerned with the shutdown path synchronization.
*
* For the muxed case there's nothing more to do.
*/
port->irq = sci_port->irqs[SCIx_RXI_IRQ];
port->irqflags = 0;
port->serial_in = sci_serial_in;
port->serial_out = sci_serial_out;
return 0;
}
static void sci_cleanup_single(struct sci_port *port)
{
pm_runtime_disable(port->port.dev);
}
#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
static void serial_console_putchar(struct uart_port *port, unsigned char ch)
{
sci_poll_put_char(port, ch);
}
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*/
static void serial_console_write(struct console *co, const char *s,
unsigned count)
{
struct sci_port *sci_port = &sci_ports[co->index];
struct uart_port *port = &sci_port->port;
unsigned short bits, ctrl, ctrl_temp;
unsigned long flags;
int locked = 1;
if (port->sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
else
spin_lock_irqsave(&port->lock, flags);
/* first save SCSCR then disable interrupts, keep clock source */
ctrl = serial_port_in(port, SCSCR);
ctrl_temp = SCSCR_RE | SCSCR_TE |
(sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
(ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
uart_console_write(port, s, count, serial_console_putchar);
/* wait until fifo is empty and last bit has been transmitted */
bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
while ((serial_port_in(port, SCxSR) & bits) != bits)
cpu_relax();
/* restore the SCSCR */
serial_port_out(port, SCSCR, ctrl);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
}
static int serial_console_setup(struct console *co, char *options)
{
struct sci_port *sci_port;
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
/*
* Refuse to handle any bogus ports.
*/
if (co->index < 0 || co->index >= SCI_NPORTS)
return -ENODEV;
sci_port = &sci_ports[co->index];
port = &sci_port->port;
/*
* Refuse to handle uninitialized ports.
*/
if (!port->ops)
return -ENODEV;
ret = sci_remap_port(port);
if (unlikely(ret != 0))
return ret;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct console serial_console = {
.name = "ttySC",
.device = uart_console_device,
.write = serial_console_write,
.setup = serial_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &sci_uart_driver,
};
#ifdef CONFIG_SUPERH
static char early_serial_buf[32];
static int early_serial_console_setup(struct console *co, char *options)
{
/*
* This early console is always registered using the earlyprintk=
* parameter, which does not call add_preferred_console(). Thus
* @options is always NULL and the options for this early console
* are passed using a custom buffer.
*/
WARN_ON(options);
return serial_console_setup(co, early_serial_buf);
}
static struct console early_serial_console = {
.name = "early_ttySC",
.write = serial_console_write,
.setup = early_serial_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
};
static int sci_probe_earlyprintk(struct platform_device *pdev)
{
const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
if (early_serial_console.data)
return -EEXIST;
early_serial_console.index = pdev->id;
sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
if (!strstr(early_serial_buf, "keep"))
early_serial_console.flags |= CON_BOOT;
register_console(&early_serial_console);
return 0;
}
#endif
#define SCI_CONSOLE (&serial_console)
#else
static inline int sci_probe_earlyprintk(struct platform_device *pdev)
{
return -EINVAL;
}
#define SCI_CONSOLE NULL
#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
static DEFINE_MUTEX(sci_uart_registration_lock);
static struct uart_driver sci_uart_driver = {
.owner = THIS_MODULE,
.driver_name = "sci",
.dev_name = "ttySC",
.major = SCI_MAJOR,
.minor = SCI_MINOR_START,
.nr = SCI_NPORTS,
.cons = SCI_CONSOLE,
};
static int sci_remove(struct platform_device *dev)
{
struct sci_port *port = platform_get_drvdata(dev);
unsigned int type = port->port.type; /* uart_remove_... clears it */
sci_ports_in_use &= ~BIT(port->port.line);
uart_remove_one_port(&sci_uart_driver, &port->port);
sci_cleanup_single(port);
if (port->port.fifosize > 1)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
return 0;
}
#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
static const struct of_device_id of_sci_match[] __maybe_unused = {
/* SoC-specific types */
{
.compatible = "renesas,scif-r7s72100",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
},
{
.compatible = "renesas,scif-r7s9210",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
},
{
.compatible = "renesas,scif-r9a07g044",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
},
/* Family-specific types */
{
.compatible = "renesas,rcar-gen1-scif",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
}, {
.compatible = "renesas,rcar-gen2-scif",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
}, {
.compatible = "renesas,rcar-gen3-scif",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
}, {
.compatible = "renesas,rcar-gen4-scif",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
},
/* Generic types */
{
.compatible = "renesas,scif",
.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
}, {
.compatible = "renesas,scifa",
.data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
}, {
.compatible = "renesas,scifb",
.data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
}, {
.compatible = "renesas,hscif",
.data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
}, {
.compatible = "renesas,sci",
.data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
}, {
/* Terminator */
},
};
MODULE_DEVICE_TABLE(of, of_sci_match);
static void sci_reset_control_assert(void *data)
{
reset_control_assert(data);
}
static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
unsigned int *dev_id)
{
struct device_node *np = pdev->dev.of_node;
struct reset_control *rstc;
struct plat_sci_port *p;
struct sci_port *sp;
const void *data;
int id, ret;
if (!IS_ENABLED(CONFIG_OF) || !np)
return ERR_PTR(-EINVAL);
data = of_device_get_match_data(&pdev->dev);
rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc))
return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
"failed to get reset ctrl\n"));
ret = reset_control_deassert(rstc);
if (ret) {
dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
return ERR_PTR(ret);
}
ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
if (ret) {
dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
ret);
return ERR_PTR(ret);
}
p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
if (!p)
return ERR_PTR(-ENOMEM);
/* Get the line number from the aliases node. */
id = of_alias_get_id(np, "serial");
if (id < 0 && ~sci_ports_in_use)
id = ffz(sci_ports_in_use);
if (id < 0) {
dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
return ERR_PTR(-EINVAL);
}
if (id >= ARRAY_SIZE(sci_ports)) {
dev_err(&pdev->dev, "serial%d out of range\n", id);
return ERR_PTR(-EINVAL);
}
sp = &sci_ports[id];
*dev_id = id;
p->type = SCI_OF_TYPE(data);
p->regtype = SCI_OF_REGTYPE(data);
sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
return p;
}
static int sci_probe_single(struct platform_device *dev,
unsigned int index,
struct plat_sci_port *p,
struct sci_port *sciport)
{
int ret;
/* Sanity check */
if (unlikely(index >= SCI_NPORTS)) {
dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
index+1, SCI_NPORTS);
dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
return -EINVAL;
}
BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
if (sci_ports_in_use & BIT(index))
return -EBUSY;
mutex_lock(&sci_uart_registration_lock);
if (!sci_uart_driver.state) {
ret = uart_register_driver(&sci_uart_driver);
if (ret) {
mutex_unlock(&sci_uart_registration_lock);
return ret;
}
}
mutex_unlock(&sci_uart_registration_lock);
ret = sci_init_single(dev, sciport, index, p, false);
if (ret)
return ret;
sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
if (IS_ERR(sciport->gpios))
return PTR_ERR(sciport->gpios);
if (sciport->has_rtscts) {
if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
return -EINVAL;
}
sciport->port.flags |= UPF_HARD_FLOW;
}
ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
if (ret) {
sci_cleanup_single(sciport);
return ret;
}
return 0;
}
static int sci_probe(struct platform_device *dev)
{
struct plat_sci_port *p;
struct sci_port *sp;
unsigned int dev_id;
int ret;
/*
* If we've come here via earlyprintk initialization, head off to
* the special early probe. We don't have sufficient device state
* to make it beyond this yet.
*/
#ifdef CONFIG_SUPERH
if (is_sh_early_platform_device(dev))
return sci_probe_earlyprintk(dev);
#endif
if (dev->dev.of_node) {
p = sci_parse_dt(dev, &dev_id);
if (IS_ERR(p))
return PTR_ERR(p);
} else {
p = dev->dev.platform_data;
if (p == NULL) {
dev_err(&dev->dev, "no platform data supplied\n");
return -EINVAL;
}
dev_id = dev->id;
}
sp = &sci_ports[dev_id];
platform_set_drvdata(dev, sp);
ret = sci_probe_single(dev, dev_id, p, sp);
if (ret)
return ret;
if (sp->port.fifosize > 1) {
ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
if (ret)
return ret;
}
if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
sp->port.type == PORT_HSCIF) {
ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
if (ret) {
if (sp->port.fifosize > 1) {
device_remove_file(&dev->dev,
&dev_attr_rx_fifo_trigger);
}
return ret;
}
}
#ifdef CONFIG_SH_STANDARD_BIOS
sh_bios_gdb_detach();
#endif
sci_ports_in_use |= BIT(dev_id);
return 0;
}
static __maybe_unused int sci_suspend(struct device *dev)
{
struct sci_port *sport = dev_get_drvdata(dev);
if (sport)
uart_suspend_port(&sci_uart_driver, &sport->port);
return 0;
}
static __maybe_unused int sci_resume(struct device *dev)
{
struct sci_port *sport = dev_get_drvdata(dev);
if (sport)
uart_resume_port(&sci_uart_driver, &sport->port);
return 0;
}
static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
static struct platform_driver sci_driver = {
.probe = sci_probe,
.remove = sci_remove,
.driver = {
.name = "sh-sci",
.pm = &sci_dev_pm_ops,
.of_match_table = of_match_ptr(of_sci_match),
},
};
static int __init sci_init(void)
{
pr_info("%s\n", banner);
return platform_driver_register(&sci_driver);
}
static void __exit sci_exit(void)
{
platform_driver_unregister(&sci_driver);
if (sci_uart_driver.state)
uart_unregister_driver(&sci_uart_driver);
}
#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
sh_early_platform_init_buffer("earlyprintk", &sci_driver,
early_serial_buf, ARRAY_SIZE(early_serial_buf));
#endif
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
static struct plat_sci_port port_cfg __initdata;
static int __init early_console_setup(struct earlycon_device *device,
int type)
{
if (!device->port.membase)
return -ENODEV;
device->port.serial_in = sci_serial_in;
device->port.serial_out = sci_serial_out;
device->port.type = type;
memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
port_cfg.type = type;
sci_ports[0].cfg = &port_cfg;
sci_ports[0].params = sci_probe_regmap(&port_cfg);
port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
sci_serial_out(&sci_ports[0].port, SCSCR,
SCSCR_RE | SCSCR_TE | port_cfg.scscr);
device->con->write = serial_console_write;
return 0;
}
static int __init sci_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return early_console_setup(device, PORT_SCI);
}
static int __init scif_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return early_console_setup(device, PORT_SCIF);
}
static int __init rzscifa_early_console_setup(struct earlycon_device *device,
const char *opt)
{
port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
return early_console_setup(device, PORT_SCIF);
}
static int __init scifa_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return early_console_setup(device, PORT_SCIFA);
}
static int __init scifb_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return early_console_setup(device, PORT_SCIFB);
}
static int __init hscif_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return early_console_setup(device, PORT_HSCIF);
}
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
module_init(sci_init);
module_exit(sci_exit);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sh-sci");
MODULE_AUTHOR("Paul Mundt");
MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
| linux-master | drivers/tty/serial/sh-sci.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014 Linaro Ltd.
* Author: Rob Herring <[email protected]>
*
* Based on 8250 earlycon:
* (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
* Bjorn Helgaas <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/console.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/serial_core.h>
#include <linux/sizes.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/acpi.h>
#ifdef CONFIG_FIX_EARLYCON_MEM
#include <asm/fixmap.h>
#endif
#include <asm/serial.h>
static struct console early_con = {
.name = "uart", /* fixed up at earlycon registration */
.flags = CON_PRINTBUFFER | CON_BOOT,
.index = 0,
};
static struct earlycon_device early_console_dev = {
.con = &early_con,
};
static void __iomem * __init earlycon_map(resource_size_t paddr, size_t size)
{
void __iomem *base;
#ifdef CONFIG_FIX_EARLYCON_MEM
set_fixmap_io(FIX_EARLYCON_MEM_BASE, paddr & PAGE_MASK);
base = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
base += paddr & ~PAGE_MASK;
#else
base = ioremap(paddr, size);
#endif
if (!base)
pr_err("%s: Couldn't map %pa\n", __func__, &paddr);
return base;
}
static void __init earlycon_init(struct earlycon_device *device,
const char *name)
{
struct console *earlycon = device->con;
const char *s;
size_t len;
/* scan backwards from end of string for first non-numeral */
for (s = name + strlen(name);
s > name && s[-1] >= '0' && s[-1] <= '9';
s--)
;
if (*s)
earlycon->index = simple_strtoul(s, NULL, 10);
len = s - name;
strscpy(earlycon->name, name, min(len + 1, sizeof(earlycon->name)));
earlycon->data = &early_console_dev;
}
static void __init earlycon_print_info(struct earlycon_device *device)
{
struct console *earlycon = device->con;
struct uart_port *port = &device->port;
if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM16 ||
port->iotype == UPIO_MEM32 || port->iotype == UPIO_MEM32BE)
pr_info("%s%d at MMIO%s %pa (options '%s')\n",
earlycon->name, earlycon->index,
(port->iotype == UPIO_MEM) ? "" :
(port->iotype == UPIO_MEM16) ? "16" :
(port->iotype == UPIO_MEM32) ? "32" : "32be",
&port->mapbase, device->options);
else
pr_info("%s%d at I/O port 0x%lx (options '%s')\n",
earlycon->name, earlycon->index,
port->iobase, device->options);
}
static int __init parse_options(struct earlycon_device *device, char *options)
{
struct uart_port *port = &device->port;
int length;
resource_size_t addr;
if (uart_parse_earlycon(options, &port->iotype, &addr, &options))
return -EINVAL;
switch (port->iotype) {
case UPIO_MEM:
port->mapbase = addr;
break;
case UPIO_MEM16:
port->regshift = 1;
port->mapbase = addr;
break;
case UPIO_MEM32:
case UPIO_MEM32BE:
port->regshift = 2;
port->mapbase = addr;
break;
case UPIO_PORT:
port->iobase = addr;
break;
default:
return -EINVAL;
}
if (options) {
char *uartclk;
device->baud = simple_strtoul(options, NULL, 0);
uartclk = strchr(options, ',');
if (uartclk && kstrtouint(uartclk + 1, 0, &port->uartclk) < 0)
pr_warn("[%s] unsupported earlycon uart clkrate option\n",
options);
length = min(strcspn(options, " ") + 1,
(size_t)(sizeof(device->options)));
strscpy(device->options, options, length);
}
return 0;
}
static int __init register_earlycon(char *buf, const struct earlycon_id *match)
{
int err;
struct uart_port *port = &early_console_dev.port;
/* On parsing error, pass the options buf to the setup function */
if (buf && !parse_options(&early_console_dev, buf))
buf = NULL;
spin_lock_init(&port->lock);
if (!port->uartclk)
port->uartclk = BASE_BAUD * 16;
if (port->mapbase)
port->membase = earlycon_map(port->mapbase, 64);
earlycon_init(&early_console_dev, match->name);
err = match->setup(&early_console_dev, buf);
earlycon_print_info(&early_console_dev);
if (err < 0)
return err;
if (!early_console_dev.con->write)
return -ENODEV;
register_console(early_console_dev.con);
return 0;
}
/**
* setup_earlycon - match and register earlycon console
* @buf: earlycon param string
*
* Registers the earlycon console matching the earlycon specified
* in the param string @buf. Acceptable param strings are of the form
* <name>,io|mmio|mmio32|mmio32be,<addr>,<options>
* <name>,0x<addr>,<options>
* <name>,<options>
* <name>
*
* Only for the third form does the earlycon setup() method receive the
* <options> string in the 'options' parameter; all other forms set
* the parameter to NULL.
*
* Returns 0 if an attempt to register the earlycon was made,
* otherwise negative error code
*/
int __init setup_earlycon(char *buf)
{
const struct earlycon_id *match;
bool empty_compatible = true;
if (!buf || !buf[0])
return -EINVAL;
if (console_is_registered(&early_con))
return -EALREADY;
again:
for (match = __earlycon_table; match < __earlycon_table_end; match++) {
size_t len = strlen(match->name);
if (strncmp(buf, match->name, len))
continue;
/* prefer entries with empty compatible */
if (empty_compatible && *match->compatible)
continue;
if (buf[len]) {
if (buf[len] != ',')
continue;
buf += len + 1;
} else
buf = NULL;
return register_earlycon(buf, match);
}
if (empty_compatible) {
empty_compatible = false;
goto again;
}
return -ENOENT;
}
/*
* This defers the initialization of the early console until after ACPI has
* been initialized.
*/
bool earlycon_acpi_spcr_enable __initdata;
/* early_param wrapper for setup_earlycon() */
static int __init param_setup_earlycon(char *buf)
{
int err;
/* Just 'earlycon' is a valid param for devicetree and ACPI SPCR. */
if (!buf || !buf[0]) {
if (IS_ENABLED(CONFIG_ACPI_SPCR_TABLE)) {
earlycon_acpi_spcr_enable = true;
return 0;
} else if (!buf) {
return early_init_dt_scan_chosen_stdout();
}
}
err = setup_earlycon(buf);
if (err == -ENOENT || err == -EALREADY)
return 0;
return err;
}
early_param("earlycon", param_setup_earlycon);
#ifdef CONFIG_OF_EARLY_FLATTREE
int __init of_setup_earlycon(const struct earlycon_id *match,
unsigned long node,
const char *options)
{
int err;
struct uart_port *port = &early_console_dev.port;
const __be32 *val;
bool big_endian;
u64 addr;
if (console_is_registered(&early_con))
return -EALREADY;
spin_lock_init(&port->lock);
port->iotype = UPIO_MEM;
addr = of_flat_dt_translate_address(node);
if (addr == OF_BAD_ADDR) {
pr_warn("[%s] bad address\n", match->name);
return -ENXIO;
}
port->mapbase = addr;
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
port->membase = earlycon_map(port->mapbase, SZ_4K);
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
big_endian = of_get_flat_dt_prop(node, "big-endian", NULL) != NULL ||
(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) &&
of_get_flat_dt_prop(node, "native-endian", NULL) != NULL);
val = of_get_flat_dt_prop(node, "reg-io-width", NULL);
if (val) {
switch (be32_to_cpu(*val)) {
case 1:
port->iotype = UPIO_MEM;
break;
case 2:
port->iotype = UPIO_MEM16;
break;
case 4:
port->iotype = (big_endian) ? UPIO_MEM32BE : UPIO_MEM32;
break;
default:
pr_warn("[%s] unsupported reg-io-width\n", match->name);
return -EINVAL;
}
}
val = of_get_flat_dt_prop(node, "current-speed", NULL);
if (val)
early_console_dev.baud = be32_to_cpu(*val);
val = of_get_flat_dt_prop(node, "clock-frequency", NULL);
if (val)
port->uartclk = be32_to_cpu(*val);
if (options) {
early_console_dev.baud = simple_strtoul(options, NULL, 0);
strscpy(early_console_dev.options, options,
sizeof(early_console_dev.options));
}
earlycon_init(&early_console_dev, match->name);
err = match->setup(&early_console_dev, options);
earlycon_print_info(&early_console_dev);
if (err < 0)
return err;
if (!early_console_dev.con->write)
return -ENODEV;
register_console(early_console_dev.con);
return 0;
}
#endif /* CONFIG_OF_EARLY_FLATTREE */
| linux-master | drivers/tty/serial/earlycon.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for CPM (SCC/SMC) serial ports; core driver
*
* Based on arch/ppc/cpm2_io/uart.c by Dan Malek
* Based on ppc8xx.c by Thomas Gleixner
* Based on drivers/serial/amba.c by Russell King
*
* Maintainer: Kumar Gala ([email protected]) (CPM2)
* Pantelis Antoniou ([email protected]) (CPM1)
*
* Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
* (C) 2004 Intracom, S.A.
* (C) 2005-2006 MontaVista Software, Inc.
* Vitaly Bordug <[email protected]>
*/
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/device.h>
#include <linux/memblock.h>
#include <linux/dma-mapping.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/gpio/consumer.h>
#include <linux/clk.h>
#include <sysdev/fsl_soc.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/delay.h>
#include <asm/udbg.h>
#include <linux/serial_core.h>
#include <linux/kernel.h>
#include "cpm_uart.h"
/**************************************************************/
static int cpm_uart_tx_pump(struct uart_port *port);
static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
/**************************************************************/
#define HW_BUF_SPD_THRESHOLD 2400
static void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
cpm_command(port->command, cmd);
}
/*
* Check, if transmit buffers are processed
*/
static unsigned int cpm_uart_tx_empty(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
cbd_t __iomem *bdp = pinfo->tx_bd_base;
int ret = 0;
while (1) {
if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
break;
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
ret = TIOCSER_TEMT;
break;
}
bdp++;
}
pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
return ret;
}
static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
if (pinfo->gpios[GPIO_RTS])
gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
if (pinfo->gpios[GPIO_DTR])
gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
}
static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
if (pinfo->gpios[GPIO_CTS]) {
if (gpiod_get_value(pinfo->gpios[GPIO_CTS]))
mctrl &= ~TIOCM_CTS;
}
if (pinfo->gpios[GPIO_DSR]) {
if (gpiod_get_value(pinfo->gpios[GPIO_DSR]))
mctrl &= ~TIOCM_DSR;
}
if (pinfo->gpios[GPIO_DCD]) {
if (gpiod_get_value(pinfo->gpios[GPIO_DCD]))
mctrl &= ~TIOCM_CAR;
}
if (pinfo->gpios[GPIO_RI]) {
if (!gpiod_get_value(pinfo->gpios[GPIO_RI]))
mctrl |= TIOCM_RNG;
}
return mctrl;
}
/*
* Stop transmitter
*/
static void cpm_uart_stop_tx(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
smc_t __iomem *smcp = pinfo->smcp;
scc_t __iomem *sccp = pinfo->sccp;
pr_debug("CPM uart[%d]:stop tx\n", port->line);
if (IS_SMC(pinfo))
clrbits8(&smcp->smc_smcm, SMCM_TX);
else
clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
}
/*
* Start transmitter
*/
static void cpm_uart_start_tx(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
smc_t __iomem *smcp = pinfo->smcp;
scc_t __iomem *sccp = pinfo->sccp;
pr_debug("CPM uart[%d]:start tx\n", port->line);
if (IS_SMC(pinfo)) {
if (in_8(&smcp->smc_smcm) & SMCM_TX)
return;
} else {
if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
return;
}
if (cpm_uart_tx_pump(port) != 0) {
if (IS_SMC(pinfo)) {
setbits8(&smcp->smc_smcm, SMCM_TX);
} else {
setbits16(&sccp->scc_sccm, UART_SCCM_TX);
}
}
}
/*
* Stop receiver
*/
static void cpm_uart_stop_rx(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
smc_t __iomem *smcp = pinfo->smcp;
scc_t __iomem *sccp = pinfo->sccp;
pr_debug("CPM uart[%d]:stop rx\n", port->line);
if (IS_SMC(pinfo))
clrbits8(&smcp->smc_smcm, SMCM_RX);
else
clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
}
/*
* Generate a break.
*/
static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
break_state);
if (break_state)
cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
else
cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
}
/*
* Transmit characters, refill buffer descriptor, if possible
*/
static void cpm_uart_int_tx(struct uart_port *port)
{
pr_debug("CPM uart[%d]:TX INT\n", port->line);
cpm_uart_tx_pump(port);
}
#ifdef CONFIG_CONSOLE_POLL
static int serial_polled;
#endif
/*
* Receive characters
*/
static void cpm_uart_int_rx(struct uart_port *port)
{
int i;
unsigned char ch;
u8 *cp;
struct tty_port *tport = &port->state->port;
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
cbd_t __iomem *bdp;
u16 status;
unsigned int flg;
pr_debug("CPM uart[%d]:RX INT\n", port->line);
/* Just loop through the closed BDs and copy the characters into
* the buffer.
*/
bdp = pinfo->rx_cur;
for (;;) {
#ifdef CONFIG_CONSOLE_POLL
if (unlikely(serial_polled)) {
serial_polled = 0;
return;
}
#endif
/* get status */
status = in_be16(&bdp->cbd_sc);
/* If this one is empty, return happy */
if (status & BD_SC_EMPTY)
break;
/* get number of characters, and check spce in flip-buffer */
i = in_be16(&bdp->cbd_datlen);
/* If we have not enough room in tty flip buffer, then we try
* later, which will be the next rx-interrupt or a timeout
*/
if (tty_buffer_request_room(tport, i) < i) {
printk(KERN_WARNING "No room in flip buffer\n");
return;
}
/* get pointer */
cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
/* loop through the buffer */
while (i-- > 0) {
ch = *cp++;
port->icount.rx++;
flg = TTY_NORMAL;
if (status &
(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
goto handle_error;
if (uart_handle_sysrq_char(port, ch))
continue;
#ifdef CONFIG_CONSOLE_POLL
if (unlikely(serial_polled)) {
serial_polled = 0;
return;
}
#endif
error_return:
tty_insert_flip_char(tport, ch, flg);
} /* End while (i--) */
/* This BD is ready to be used again. Clear status. get next */
clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
BD_SC_OV | BD_SC_ID);
setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->rx_bd_base;
else
bdp++;
} /* End for (;;) */
/* Write back buffer pointer */
pinfo->rx_cur = bdp;
/* activate BH processing */
tty_flip_buffer_push(tport);
return;
/* Error processing */
handle_error:
/* Statistics */
if (status & BD_SC_BR)
port->icount.brk++;
if (status & BD_SC_PR)
port->icount.parity++;
if (status & BD_SC_FR)
port->icount.frame++;
if (status & BD_SC_OV)
port->icount.overrun++;
/* Mask out ignored conditions */
status &= port->read_status_mask;
/* Handle the remaining ones */
if (status & BD_SC_BR)
flg = TTY_BREAK;
else if (status & BD_SC_PR)
flg = TTY_PARITY;
else if (status & BD_SC_FR)
flg = TTY_FRAME;
/* overrun does not affect the current character ! */
if (status & BD_SC_OV) {
ch = 0;
flg = TTY_OVERRUN;
/* We skip this buffer */
/* CHECK: Is really nothing senseful there */
/* ASSUMPTION: it contains nothing valid */
i = 0;
}
port->sysrq = 0;
goto error_return;
}
/*
* Asynchron mode interrupt handler
*/
static irqreturn_t cpm_uart_int(int irq, void *data)
{
u8 events;
struct uart_port *port = data;
struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
smc_t __iomem *smcp = pinfo->smcp;
scc_t __iomem *sccp = pinfo->sccp;
pr_debug("CPM uart[%d]:IRQ\n", port->line);
if (IS_SMC(pinfo)) {
events = in_8(&smcp->smc_smce);
out_8(&smcp->smc_smce, events);
if (events & SMCM_BRKE)
uart_handle_break(port);
if (events & SMCM_RX)
cpm_uart_int_rx(port);
if (events & SMCM_TX)
cpm_uart_int_tx(port);
} else {
events = in_be16(&sccp->scc_scce);
out_be16(&sccp->scc_scce, events);
if (events & UART_SCCM_BRKE)
uart_handle_break(port);
if (events & UART_SCCM_RX)
cpm_uart_int_rx(port);
if (events & UART_SCCM_TX)
cpm_uart_int_tx(port);
}
return (events) ? IRQ_HANDLED : IRQ_NONE;
}
static int cpm_uart_startup(struct uart_port *port)
{
int retval;
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
pr_debug("CPM uart[%d]:startup\n", port->line);
/* If the port is not the console, make sure rx is disabled. */
if (!(pinfo->flags & FLAG_CONSOLE)) {
/* Disable UART rx */
if (IS_SMC(pinfo)) {
clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
} else {
clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
}
cpm_uart_initbd(pinfo);
if (IS_SMC(pinfo)) {
out_be32(&pinfo->smcup->smc_rstate, 0);
out_be32(&pinfo->smcup->smc_tstate, 0);
out_be16(&pinfo->smcup->smc_rbptr,
in_be16(&pinfo->smcup->smc_rbase));
out_be16(&pinfo->smcup->smc_tbptr,
in_be16(&pinfo->smcup->smc_tbase));
} else {
cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
}
}
/* Install interrupt handler. */
retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
if (retval)
return retval;
/* Startup rx-int */
if (IS_SMC(pinfo)) {
setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
} else {
setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
}
return 0;
}
inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
{
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(pinfo->wait_closing);
}
/*
* Shutdown the uart
*/
static void cpm_uart_shutdown(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
pr_debug("CPM uart[%d]:shutdown\n", port->line);
/* free interrupt handler */
free_irq(port->irq, port);
/* If the port is not the console, disable Rx and Tx. */
if (!(pinfo->flags & FLAG_CONSOLE)) {
/* Wait for all the BDs marked sent */
while(!cpm_uart_tx_empty(port)) {
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(2);
}
if (pinfo->wait_closing)
cpm_uart_wait_until_send(pinfo);
/* Stop uarts */
if (IS_SMC(pinfo)) {
smc_t __iomem *smcp = pinfo->smcp;
clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
} else {
scc_t __iomem *sccp = pinfo->sccp;
clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
}
/* Shut them really down and reinit buffer descriptors */
if (IS_SMC(pinfo)) {
out_be16(&pinfo->smcup->smc_brkcr, 0);
cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
} else {
out_be16(&pinfo->sccup->scc_brkcr, 0);
cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
}
cpm_uart_initbd(pinfo);
}
}
static void cpm_uart_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
int baud;
unsigned long flags;
u16 cval, scval, prev_mode;
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
smc_t __iomem *smcp = pinfo->smcp;
scc_t __iomem *sccp = pinfo->sccp;
int maxidl;
pr_debug("CPM uart[%d]:set_termios\n", port->line);
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY)
pinfo->rx_fifosize = 1;
else
pinfo->rx_fifosize = RX_BUF_SIZE;
/* MAXIDL is the timeout after which a receive buffer is closed
* when not full if no more characters are received.
* We calculate it from the baudrate so that the duration is
* always the same at standard rates: about 4ms.
*/
maxidl = baud / 2400;
if (maxidl < 1)
maxidl = 1;
if (maxidl > 0x10)
maxidl = 0x10;
cval = 0;
scval = 0;
if (termios->c_cflag & CSTOPB) {
cval |= SMCMR_SL; /* Two stops */
scval |= SCU_PSMR_SL;
}
if (termios->c_cflag & PARENB) {
cval |= SMCMR_PEN;
scval |= SCU_PSMR_PEN;
if (!(termios->c_cflag & PARODD)) {
cval |= SMCMR_PM_EVEN;
scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
}
}
/*
* Update the timeout
*/
uart_update_timeout(port, termios->c_cflag, baud);
/*
* Set up parity check flag
*/
port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
if (termios->c_iflag & INPCK)
port->read_status_mask |= BD_SC_FR | BD_SC_PR;
if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
port->read_status_mask |= BD_SC_BR;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= BD_SC_BR;
/*
* If we're ignore parity and break indicators, ignore
* overruns too. (For real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= BD_SC_OV;
}
/*
* !!! ignore all characters if CREAD is not set
*/
if ((termios->c_cflag & CREAD) == 0)
port->read_status_mask &= ~BD_SC_EMPTY;
spin_lock_irqsave(&port->lock, flags);
if (IS_SMC(pinfo)) {
unsigned int bits = tty_get_frame_size(termios->c_cflag);
/*
* MRBLR can be changed while an SMC/SCC is operating only
* if it is done in a single bus cycle with one 16-bit move
* (not two 8-bit bus cycles back-to-back). This occurs when
* the cp shifts control to the next RxBD, so the change does
* not take effect immediately. To guarantee the exact RxBD
* on which the change occurs, change MRBLR only while the
* SMC/SCC receiver is disabled.
*/
out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
out_be16(&pinfo->smcup->smc_maxidl, maxidl);
/* Set the mode register. We want to keep a copy of the
* enables, because we want to put them back if they were
* present.
*/
prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
/* Output in *one* operation, so we don't interrupt RX/TX if they
* were already enabled.
* Character length programmed into the register is frame bits minus 1.
*/
out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits - 1) | cval |
SMCMR_SM_UART | prev_mode);
} else {
unsigned int bits = tty_get_char_size(termios->c_cflag);
out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
out_be16(&pinfo->sccup->scc_maxidl, maxidl);
out_be16(&sccp->scc_psmr, (UART_LCR_WLEN(bits) << 12) | scval);
}
if (pinfo->clk)
clk_set_rate(pinfo->clk, baud);
else
cpm_setbrg(pinfo->brg - 1, baud);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *cpm_uart_type(struct uart_port *port)
{
pr_debug("CPM uart[%d]:uart_type\n", port->line);
return port->type == PORT_CPM ? "CPM UART" : NULL;
}
/*
* verify the new serial_struct (for TIOCSSERIAL).
*/
static int cpm_uart_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
int ret = 0;
pr_debug("CPM uart[%d]:verify_port\n", port->line);
if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= nr_irqs)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
return ret;
}
/*
* Transmit characters, refill buffer descriptor, if possible
*/
static int cpm_uart_tx_pump(struct uart_port *port)
{
cbd_t __iomem *bdp;
u8 *p;
int count;
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
struct circ_buf *xmit = &port->state->xmit;
/* Handle xon/xoff */
if (port->x_char) {
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
*p++ = port->x_char;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
/* Get next BD. */
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
pinfo->tx_cur = bdp;
port->icount.tx++;
port->x_char = 0;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
cpm_uart_stop_tx(port);
return 0;
}
/* Pick next descriptor and fill from buffer */
bdp = pinfo->tx_cur;
while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && !uart_circ_empty(xmit)) {
count = 0;
p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
while (count < pinfo->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
uart_xmit_advance(port, 1);
count++;
if (uart_circ_empty(xmit))
break;
}
out_be16(&bdp->cbd_datlen, count);
setbits16(&bdp->cbd_sc, BD_SC_READY);
/* Get next BD. */
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = pinfo->tx_bd_base;
else
bdp++;
}
pinfo->tx_cur = bdp;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
cpm_uart_stop_tx(port);
return 0;
}
return 1;
}
/*
* init buffer descriptors
*/
static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
{
int i;
u8 *mem_addr;
cbd_t __iomem *bdp;
pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
* virtual address for us to work with.
*/
mem_addr = pinfo->mem_addr;
bdp = pinfo->rx_cur = pinfo->rx_bd_base;
for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
mem_addr += pinfo->rx_fifosize;
}
out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
* virtual address for us to work with.
*/
mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
bdp = pinfo->tx_cur = pinfo->tx_bd_base;
for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
mem_addr += pinfo->tx_fifosize;
}
out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
}
static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
{
scc_t __iomem *scp;
scc_uart_t __iomem *sup;
pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
scp = pinfo->sccp;
sup = pinfo->sccup;
/* Store address */
out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
(u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
(u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
/* Set up the uart parameters in the
* parameter ram.
*/
out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB);
out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB);
out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
out_be16(&sup->scc_maxidl, 0x10);
out_be16(&sup->scc_brkcr, 1);
out_be16(&sup->scc_parec, 0);
out_be16(&sup->scc_frmec, 0);
out_be16(&sup->scc_nosec, 0);
out_be16(&sup->scc_brkec, 0);
out_be16(&sup->scc_uaddr1, 0);
out_be16(&sup->scc_uaddr2, 0);
out_be16(&sup->scc_toseq, 0);
out_be16(&sup->scc_char1, 0x8000);
out_be16(&sup->scc_char2, 0x8000);
out_be16(&sup->scc_char3, 0x8000);
out_be16(&sup->scc_char4, 0x8000);
out_be16(&sup->scc_char5, 0x8000);
out_be16(&sup->scc_char6, 0x8000);
out_be16(&sup->scc_char7, 0x8000);
out_be16(&sup->scc_char8, 0x8000);
out_be16(&sup->scc_rccm, 0xc0ff);
/* Send the CPM an initialize command.
*/
cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
out_be32(&scp->scc_gsmrh, 0);
out_be32(&scp->scc_gsmrl,
SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
/* Enable rx interrupts and clear all pending events. */
out_be16(&scp->scc_sccm, 0);
out_be16(&scp->scc_scce, 0xffff);
out_be16(&scp->scc_dsr, 0x7e7e);
out_be16(&scp->scc_psmr, 0x3000);
setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
{
smc_t __iomem *sp;
smc_uart_t __iomem *up;
pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
sp = pinfo->smcp;
up = pinfo->smcup;
/* Store address */
out_be16(&pinfo->smcup->smc_rbase,
(u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
out_be16(&pinfo->smcup->smc_tbase,
(u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
/*
* In case SMC is being relocated...
*/
out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
out_be32(&up->smc_rstate, 0);
out_be32(&up->smc_tstate, 0);
out_be16(&up->smc_brkcr, 1); /* number of break chars */
out_be16(&up->smc_brkec, 0);
/* Set up the uart parameters in the
* parameter ram.
*/
out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB);
out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB);
/* Using idle character time requires some additional tuning. */
out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
out_be16(&up->smc_maxidl, 0x10);
out_be16(&up->smc_brklen, 0);
out_be16(&up->smc_brkec, 0);
out_be16(&up->smc_brkcr, 1);
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
/* Enable only rx interrupts clear all pending events. */
out_8(&sp->smc_smcm, 0);
out_8(&sp->smc_smce, 0xff);
setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
}
/*
* Allocate DP-Ram and memory buffers. We need to allocate a transmit and
* receive buffer descriptors from dual port ram, and a character
* buffer area from host mem. If we are allocating for the console we need
* to do it from bootmem
*/
static int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
{
int dpmemsz, memsz;
u8 __iomem *dp_mem;
unsigned long dp_offset;
u8 *mem_addr;
dma_addr_t dma_addr = 0;
pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
dp_offset = cpm_muram_alloc(dpmemsz, 8);
if (IS_ERR_VALUE(dp_offset)) {
pr_err("%s: could not allocate buffer descriptors\n", __func__);
return -ENOMEM;
}
dp_mem = cpm_muram_addr(dp_offset);
memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
if (IS_ENABLED(CONFIG_CPM1) && is_con) {
/* was hostalloc but changed cause it blows away the */
/* large tlb mapping when pinning the kernel area */
mem_addr = (u8 __force *)cpm_muram_addr(cpm_muram_alloc(memsz, 8));
dma_addr = cpm_muram_dma((void __iomem *)mem_addr);
} else if (is_con) {
mem_addr = kzalloc(memsz, GFP_NOWAIT);
dma_addr = virt_to_bus(mem_addr);
} else {
mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr,
GFP_KERNEL);
}
if (!mem_addr) {
cpm_muram_free(dp_offset);
pr_err("%s: could not allocate coherent memory\n", __func__);
return -ENOMEM;
}
pinfo->dp_addr = dp_offset;
pinfo->mem_addr = mem_addr;
pinfo->dma_addr = dma_addr;
pinfo->mem_size = memsz;
pinfo->rx_buf = mem_addr;
pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
* pinfo->rx_fifosize);
pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem;
pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
return 0;
}
static void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
{
dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
pinfo->rx_fifosize) +
L1_CACHE_ALIGN(pinfo->tx_nrfifos *
pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
pinfo->dma_addr);
cpm_muram_free(pinfo->dp_addr);
}
/*
* Initialize port. This is called from early_console stuff
* so we have to be careful here !
*/
static int cpm_uart_request_port(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
int ret;
pr_debug("CPM uart[%d]:request port\n", port->line);
if (pinfo->flags & FLAG_CONSOLE)
return 0;
if (IS_SMC(pinfo)) {
clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
} else {
clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
ret = cpm_uart_allocbuf(pinfo, 0);
if (ret)
return ret;
cpm_uart_initbd(pinfo);
if (IS_SMC(pinfo))
cpm_uart_init_smc(pinfo);
else
cpm_uart_init_scc(pinfo);
return 0;
}
static void cpm_uart_release_port(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
if (!(pinfo->flags & FLAG_CONSOLE))
cpm_uart_freebuf(pinfo);
}
/*
* Configure/autoconfigure the port.
*/
static void cpm_uart_config_port(struct uart_port *port, int flags)
{
pr_debug("CPM uart[%d]:config_port\n", port->line);
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_CPM;
cpm_uart_request_port(port);
}
}
#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
/*
* Write a string to the serial port
* Note that this is called with interrupts already disabled
*/
static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
const char *string, u_int count, bool handle_linefeed)
{
unsigned int i;
cbd_t __iomem *bdp, *bdbase;
unsigned char *cpm_outp_addr;
/* Get the address of the host memory buffer.
*/
bdp = pinfo->tx_cur;
bdbase = pinfo->tx_bd_base;
/*
* Now, do each character. This is not as bad as it looks
* since this is a holding FIFO and not a transmitting FIFO.
* We could add the complexity of filling the entire transmit
* buffer, but we would just wait longer between accesses......
*/
for (i = 0; i < count; i++, string++) {
/* Wait for transmitter fifo to empty.
* Ready indicates output is ready, and xmt is doing
* that, not that it is ready for us to send.
*/
while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
;
/* Send the character out.
* If the buffer address is in the CPM DPRAM, don't
* convert it.
*/
cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
pinfo);
*cpm_outp_addr = *string;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = bdbase;
else
bdp++;
/* if a LF, also do CR... */
if (handle_linefeed && *string == 10) {
while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
;
cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
pinfo);
*cpm_outp_addr = 13;
out_be16(&bdp->cbd_datlen, 1);
setbits16(&bdp->cbd_sc, BD_SC_READY);
if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
bdp = bdbase;
else
bdp++;
}
}
/*
* Finally, Wait for transmitter & holding register to empty
* and restore the IER
*/
while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
;
pinfo->tx_cur = bdp;
}
#endif
#ifdef CONFIG_CONSOLE_POLL
/* Serial polling routines for writing and reading from the uart while
* in an interrupt or debug context.
*/
#define GDB_BUF_SIZE 512 /* power of 2, please */
static char poll_buf[GDB_BUF_SIZE];
static char *pollp;
static int poll_chars;
static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
{
u_char c, *cp;
volatile cbd_t *bdp;
int i;
/* Get the address of the host memory buffer.
*/
bdp = pinfo->rx_cur;
if (bdp->cbd_sc & BD_SC_EMPTY)
return NO_POLL_CHAR;
/* If the buffer address is in the CPM DPRAM, don't
* convert it.
*/
cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
if (obuf) {
i = c = bdp->cbd_datlen;
while (i-- > 0)
*obuf++ = *cp++;
} else
c = *cp;
bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
bdp->cbd_sc |= BD_SC_EMPTY;
if (bdp->cbd_sc & BD_SC_WRAP)
bdp = pinfo->rx_bd_base;
else
bdp++;
pinfo->rx_cur = (cbd_t *)bdp;
return (int)c;
}
static int cpm_get_poll_char(struct uart_port *port)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
if (!serial_polled) {
serial_polled = 1;
poll_chars = 0;
}
if (poll_chars <= 0) {
int ret = poll_wait_key(poll_buf, pinfo);
if (ret == NO_POLL_CHAR)
return ret;
poll_chars = ret;
pollp = poll_buf;
}
poll_chars--;
return *pollp++;
}
static void cpm_put_poll_char(struct uart_port *port,
unsigned char c)
{
struct uart_cpm_port *pinfo =
container_of(port, struct uart_cpm_port, port);
static char ch[2];
ch[0] = (char)c;
cpm_uart_early_write(pinfo, ch, 1, false);
}
#ifdef CONFIG_SERIAL_CPM_CONSOLE
static struct uart_port *udbg_port;
static void udbg_cpm_putc(char c)
{
if (c == '\n')
cpm_put_poll_char(udbg_port, '\r');
cpm_put_poll_char(udbg_port, c);
}
static int udbg_cpm_getc_poll(void)
{
int c = cpm_get_poll_char(udbg_port);
return c == NO_POLL_CHAR ? -1 : c;
}
static int udbg_cpm_getc(void)
{
int c;
while ((c = udbg_cpm_getc_poll()) == -1)
cpu_relax();
return c;
}
#endif /* CONFIG_SERIAL_CPM_CONSOLE */
#endif /* CONFIG_CONSOLE_POLL */
static const struct uart_ops cpm_uart_pops = {
.tx_empty = cpm_uart_tx_empty,
.set_mctrl = cpm_uart_set_mctrl,
.get_mctrl = cpm_uart_get_mctrl,
.stop_tx = cpm_uart_stop_tx,
.start_tx = cpm_uart_start_tx,
.stop_rx = cpm_uart_stop_rx,
.break_ctl = cpm_uart_break_ctl,
.startup = cpm_uart_startup,
.shutdown = cpm_uart_shutdown,
.set_termios = cpm_uart_set_termios,
.type = cpm_uart_type,
.release_port = cpm_uart_release_port,
.request_port = cpm_uart_request_port,
.config_port = cpm_uart_config_port,
.verify_port = cpm_uart_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = cpm_get_poll_char,
.poll_put_char = cpm_put_poll_char,
#endif
};
static struct uart_cpm_port cpm_uart_ports[UART_NR];
static void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
struct device_node *np)
{
void __iomem *pram;
unsigned long offset;
struct resource res;
resource_size_t len;
/* Don't remap parameter RAM if it has already been initialized
* during console setup.
*/
if (IS_SMC(port) && port->smcup)
return port->smcup;
else if (!IS_SMC(port) && port->sccup)
return port->sccup;
if (of_address_to_resource(np, 1, &res))
return NULL;
len = resource_size(&res);
pram = ioremap(res.start, len);
if (!pram)
return NULL;
if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port))
return pram;
if (len != 2) {
pr_warn("cpm_uart[%d]: device tree references "
"SMC pram, using boot loader/wrapper pram mapping. "
"Please fix your device tree to reference the pram "
"base register instead.\n",
port->port.line);
return pram;
}
offset = cpm_muram_alloc(64, 64);
out_be16(pram, offset);
iounmap(pram);
return cpm_muram_addr(offset);
}
static void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
{
if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port))
iounmap(pram);
}
static int cpm_uart_init_port(struct device_node *np,
struct uart_cpm_port *pinfo)
{
const u32 *data;
void __iomem *mem, *pram;
struct device *dev = pinfo->port.dev;
int len;
int ret;
int i;
data = of_get_property(np, "clock", NULL);
if (data) {
struct clk *clk = clk_get(NULL, (const char*)data);
if (!IS_ERR(clk))
pinfo->clk = clk;
}
if (!pinfo->clk) {
data = of_get_property(np, "fsl,cpm-brg", &len);
if (!data || len != 4) {
printk(KERN_ERR "CPM UART %pOFn has no/invalid "
"fsl,cpm-brg property.\n", np);
return -EINVAL;
}
pinfo->brg = *data;
}
data = of_get_property(np, "fsl,cpm-command", &len);
if (!data || len != 4) {
printk(KERN_ERR "CPM UART %pOFn has no/invalid "
"fsl,cpm-command property.\n", np);
return -EINVAL;
}
pinfo->command = *data;
mem = of_iomap(np, 0);
if (!mem)
return -ENOMEM;
if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
pinfo->sccp = mem;
pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
} else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
pinfo->flags |= FLAG_SMC;
pinfo->smcp = mem;
pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
} else {
ret = -ENODEV;
goto out_mem;
}
if (!pram) {
ret = -ENOMEM;
goto out_mem;
}
pinfo->tx_nrfifos = TX_NUM_FIFO;
pinfo->tx_fifosize = TX_BUF_SIZE;
pinfo->rx_nrfifos = RX_NUM_FIFO;
pinfo->rx_fifosize = RX_BUF_SIZE;
pinfo->port.uartclk = ppc_proc_freq;
pinfo->port.mapbase = (unsigned long)mem;
pinfo->port.type = PORT_CPM;
pinfo->port.ops = &cpm_uart_pops;
pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE);
pinfo->port.iotype = UPIO_MEM;
pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
spin_lock_init(&pinfo->port.lock);
for (i = 0; i < NUM_GPIOS; i++) {
struct gpio_desc *gpiod;
pinfo->gpios[i] = NULL;
gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS);
if (IS_ERR(gpiod)) {
ret = PTR_ERR(gpiod);
goto out_pram;
}
if (gpiod) {
if (i == GPIO_RTS || i == GPIO_DTR)
ret = gpiod_direction_output(gpiod, 0);
else
ret = gpiod_direction_input(gpiod);
if (ret) {
pr_err("can't set direction for gpio #%d: %d\n",
i, ret);
continue;
}
pinfo->gpios[i] = gpiod;
}
}
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE)
if (!udbg_port)
#endif
udbg_putc = NULL;
#endif
return cpm_uart_request_port(&pinfo->port);
out_pram:
cpm_uart_unmap_pram(pinfo, pram);
out_mem:
iounmap(mem);
return ret;
}
#ifdef CONFIG_SERIAL_CPM_CONSOLE
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*
* Note that this is called with interrupts already disabled
*/
static void cpm_uart_console_write(struct console *co, const char *s,
u_int count)
{
struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
unsigned long flags;
if (unlikely(oops_in_progress)) {
local_irq_save(flags);
cpm_uart_early_write(pinfo, s, count, true);
local_irq_restore(flags);
} else {
spin_lock_irqsave(&pinfo->port.lock, flags);
cpm_uart_early_write(pinfo, s, count, true);
spin_unlock_irqrestore(&pinfo->port.lock, flags);
}
}
static int __init cpm_uart_console_setup(struct console *co, char *options)
{
int baud = 38400;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
struct uart_cpm_port *pinfo;
struct uart_port *port;
struct device_node *np;
int i = 0;
if (co->index >= UART_NR) {
printk(KERN_ERR "cpm_uart: console index %d too high\n",
co->index);
return -ENODEV;
}
for_each_node_by_type(np, "serial") {
if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
!of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
!of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
!of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
continue;
if (i++ == co->index)
break;
}
if (!np)
return -ENODEV;
pinfo = &cpm_uart_ports[co->index];
pinfo->flags |= FLAG_CONSOLE;
port = &pinfo->port;
ret = cpm_uart_init_port(np, pinfo);
of_node_put(np);
if (ret)
return ret;
if (options) {
uart_parse_options(options, &baud, &parity, &bits, &flow);
} else {
baud = get_baudrate();
if (baud == -1)
baud = 9600;
}
if (IS_SMC(pinfo)) {
out_be16(&pinfo->smcup->smc_brkcr, 0);
cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
} else {
out_be16(&pinfo->sccup->scc_brkcr, 0);
cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
ret = cpm_uart_allocbuf(pinfo, 1);
if (ret)
return ret;
cpm_uart_initbd(pinfo);
if (IS_SMC(pinfo))
cpm_uart_init_smc(pinfo);
else
cpm_uart_init_scc(pinfo);
uart_set_options(port, co, baud, parity, bits, flow);
cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
#ifdef CONFIG_CONSOLE_POLL
if (!udbg_port) {
udbg_port = &pinfo->port;
udbg_putc = udbg_cpm_putc;
udbg_getc = udbg_cpm_getc;
udbg_getc_poll = udbg_cpm_getc_poll;
}
#endif
return 0;
}
static struct uart_driver cpm_reg;
static struct console cpm_scc_uart_console = {
.name = "ttyCPM",
.write = cpm_uart_console_write,
.device = uart_console_device,
.setup = cpm_uart_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &cpm_reg,
};
static int __init cpm_uart_console_init(void)
{
cpm_muram_init();
register_console(&cpm_scc_uart_console);
return 0;
}
console_initcall(cpm_uart_console_init);
#define CPM_UART_CONSOLE &cpm_scc_uart_console
#else
#define CPM_UART_CONSOLE NULL
#endif
static struct uart_driver cpm_reg = {
.owner = THIS_MODULE,
.driver_name = "ttyCPM",
.dev_name = "ttyCPM",
.major = SERIAL_CPM_MAJOR,
.minor = SERIAL_CPM_MINOR,
.cons = CPM_UART_CONSOLE,
.nr = UART_NR,
};
static int probe_index;
static int cpm_uart_probe(struct platform_device *ofdev)
{
int index = probe_index++;
struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
int ret;
pinfo->port.line = index;
if (index >= UART_NR)
return -ENODEV;
platform_set_drvdata(ofdev, pinfo);
/* initialize the device pointer for the port */
pinfo->port.dev = &ofdev->dev;
pinfo->port.irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
if (!pinfo->port.irq)
return -EINVAL;
ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
if (!ret)
return uart_add_one_port(&cpm_reg, &pinfo->port);
irq_dispose_mapping(pinfo->port.irq);
return ret;
}
static int cpm_uart_remove(struct platform_device *ofdev)
{
struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev);
uart_remove_one_port(&cpm_reg, &pinfo->port);
return 0;
}
static const struct of_device_id cpm_uart_match[] = {
{
.compatible = "fsl,cpm1-smc-uart",
},
{
.compatible = "fsl,cpm1-scc-uart",
},
{
.compatible = "fsl,cpm2-smc-uart",
},
{
.compatible = "fsl,cpm2-scc-uart",
},
{}
};
MODULE_DEVICE_TABLE(of, cpm_uart_match);
static struct platform_driver cpm_uart_driver = {
.driver = {
.name = "cpm_uart",
.of_match_table = cpm_uart_match,
},
.probe = cpm_uart_probe,
.remove = cpm_uart_remove,
};
static int __init cpm_uart_init(void)
{
int ret = uart_register_driver(&cpm_reg);
if (ret)
return ret;
ret = platform_driver_register(&cpm_uart_driver);
if (ret)
uart_unregister_driver(&cpm_reg);
return ret;
}
static void __exit cpm_uart_exit(void)
{
platform_driver_unregister(&cpm_uart_driver);
uart_unregister_driver(&cpm_reg);
}
module_init(cpm_uart_init);
module_exit(cpm_uart_exit);
MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
MODULE_LICENSE("GPL");
MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
| linux-master | drivers/tty/serial/cpm_uart.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright (C) 2004 Infineon IFAP DC COM CPE
* Copyright (C) 2007 Felix Fietkau <[email protected]>
* Copyright (C) 2007 John Crispin <[email protected]>
* Copyright (C) 2010 Thomas Langer, <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/lantiq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/sysrq.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#define PORT_LTQ_ASC 111
#define MAXPORTS 2
#define UART_DUMMY_UER_RX 1
#define DRVNAME "lantiq,asc"
#ifdef __BIG_ENDIAN
#define LTQ_ASC_TBUF (0x0020 + 3)
#define LTQ_ASC_RBUF (0x0024 + 3)
#else
#define LTQ_ASC_TBUF 0x0020
#define LTQ_ASC_RBUF 0x0024
#endif
#define LTQ_ASC_FSTAT 0x0048
#define LTQ_ASC_WHBSTATE 0x0018
#define LTQ_ASC_STATE 0x0014
#define LTQ_ASC_IRNCR 0x00F8
#define LTQ_ASC_CLC 0x0000
#define LTQ_ASC_ID 0x0008
#define LTQ_ASC_PISEL 0x0004
#define LTQ_ASC_TXFCON 0x0044
#define LTQ_ASC_RXFCON 0x0040
#define LTQ_ASC_CON 0x0010
#define LTQ_ASC_BG 0x0050
#define LTQ_ASC_IRNREN 0x00F4
#define ASC_IRNREN_TX 0x1
#define ASC_IRNREN_RX 0x2
#define ASC_IRNREN_ERR 0x4
#define ASC_IRNREN_TX_BUF 0x8
#define ASC_IRNCR_TIR 0x1
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
#define ASC_IRNCR_MASK GENMASK(2, 0)
#define ASCOPT_CSIZE 0x3
#define TXFIFO_FL 1
#define RXFIFO_FL 1
#define ASCCLC_DISS 0x2
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_ODD 0x00000020
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_R 0x00008000
#define ASCCON_FEN 0x00020000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFREEMASK 0x3F000000
static struct ltq_uart_port *lqasc_port[MAXPORTS];
static struct uart_driver lqasc_reg;
struct ltq_soc_data {
int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
int (*request_irq)(struct uart_port *port);
void (*free_irq)(struct uart_port *port);
};
struct ltq_uart_port {
struct uart_port port;
/* clock used to derive divider */
struct clk *freqclk;
/* clock gating of the ASC core */
struct clk *clk;
unsigned int tx_irq;
unsigned int rx_irq;
unsigned int err_irq;
unsigned int common_irq;
spinlock_t lock; /* exclusive access for multi core */
const struct ltq_soc_data *soc;
};
static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
{
u32 tmp = __raw_readl(reg);
__raw_writel((tmp & ~clear) | set, reg);
}
static inline struct
ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
{
return container_of(port, struct ltq_uart_port, port);
}
static void
lqasc_stop_tx(struct uart_port *port)
{
return;
}
static bool lqasc_tx_ready(struct uart_port *port)
{
u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT);
return FIELD_GET(ASCFSTAT_TXFREEMASK, fstat);
}
static void
lqasc_start_tx(struct uart_port *port)
{
unsigned long flags;
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
u8 ch;
spin_lock_irqsave(<q_port->lock, flags);
uart_port_tx(port, ch,
lqasc_tx_ready(port),
writeb(ch, port->membase + LTQ_ASC_TBUF));
spin_unlock_irqrestore(<q_port->lock, flags);
return;
}
static void
lqasc_stop_rx(struct uart_port *port)
{
__raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
}
static int
lqasc_rx_chars(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
unsigned int ch = 0, rsr = 0, fifocnt;
fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
ASCFSTAT_RXFFLMASK;
while (fifocnt--) {
u8 flag = TTY_NORMAL;
ch = readb(port->membase + LTQ_ASC_RBUF);
rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
& ASCSTATE_ANY) | UART_DUMMY_UER_RX;
tty_flip_buffer_push(tport);
port->icount.rx++;
/*
* Note that the error handling code is
* out of the main execution path
*/
if (rsr & ASCSTATE_ANY) {
if (rsr & ASCSTATE_PE) {
port->icount.parity++;
asc_update_bits(0, ASCWHBSTATE_CLRPE,
port->membase + LTQ_ASC_WHBSTATE);
} else if (rsr & ASCSTATE_FE) {
port->icount.frame++;
asc_update_bits(0, ASCWHBSTATE_CLRFE,
port->membase + LTQ_ASC_WHBSTATE);
}
if (rsr & ASCSTATE_ROE) {
port->icount.overrun++;
asc_update_bits(0, ASCWHBSTATE_CLRROE,
port->membase + LTQ_ASC_WHBSTATE);
}
rsr &= port->read_status_mask;
if (rsr & ASCSTATE_PE)
flag = TTY_PARITY;
else if (rsr & ASCSTATE_FE)
flag = TTY_FRAME;
}
if ((rsr & port->ignore_status_mask) == 0)
tty_insert_flip_char(tport, ch, flag);
if (rsr & ASCSTATE_ROE)
/*
* Overrun is special, since it's reported
* immediately, and doesn't affect the current
* character
*/
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
}
if (ch != 0)
tty_flip_buffer_push(tport);
return 0;
}
static irqreturn_t
lqasc_tx_int(int irq, void *_port)
{
unsigned long flags;
struct uart_port *port = (struct uart_port *)_port;
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
spin_lock_irqsave(<q_port->lock, flags);
__raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
spin_unlock_irqrestore(<q_port->lock, flags);
lqasc_start_tx(port);
return IRQ_HANDLED;
}
static irqreturn_t
lqasc_err_int(int irq, void *_port)
{
unsigned long flags;
struct uart_port *port = (struct uart_port *)_port;
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
spin_lock_irqsave(<q_port->lock, flags);
__raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR);
/* clear any pending interrupts */
asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
spin_unlock_irqrestore(<q_port->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t
lqasc_rx_int(int irq, void *_port)
{
unsigned long flags;
struct uart_port *port = (struct uart_port *)_port;
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
spin_lock_irqsave(<q_port->lock, flags);
__raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
lqasc_rx_chars(port);
spin_unlock_irqrestore(<q_port->lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t lqasc_irq(int irq, void *p)
{
unsigned long flags;
u32 stat;
struct uart_port *port = p;
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
spin_lock_irqsave(<q_port->lock, flags);
stat = readl(port->membase + LTQ_ASC_IRNCR);
spin_unlock_irqrestore(<q_port->lock, flags);
if (!(stat & ASC_IRNCR_MASK))
return IRQ_NONE;
if (stat & ASC_IRNCR_TIR)
lqasc_tx_int(irq, p);
if (stat & ASC_IRNCR_RIR)
lqasc_rx_int(irq, p);
if (stat & ASC_IRNCR_EIR)
lqasc_err_int(irq, p);
return IRQ_HANDLED;
}
static unsigned int
lqasc_tx_empty(struct uart_port *port)
{
int status;
status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
ASCFSTAT_TXFFLMASK;
return status ? 0 : TIOCSER_TEMT;
}
static unsigned int
lqasc_get_mctrl(struct uart_port *port)
{
return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
}
static void
lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
{
}
static void
lqasc_break_ctl(struct uart_port *port, int break_state)
{
}
static int
lqasc_startup(struct uart_port *port)
{
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
int retval;
unsigned long flags;
if (!IS_ERR(ltq_port->clk))
clk_prepare_enable(ltq_port->clk);
port->uartclk = clk_get_rate(ltq_port->freqclk);
spin_lock_irqsave(<q_port->lock, flags);
asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
port->membase + LTQ_ASC_CLC);
__raw_writel(0, port->membase + LTQ_ASC_PISEL);
__raw_writel(
((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
port->membase + LTQ_ASC_TXFCON);
__raw_writel(
((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
| ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
port->membase + LTQ_ASC_RXFCON);
/* make sure other settings are written to hardware before
* setting enable bits
*/
wmb();
asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
ASCCON_ROEN, port->membase + LTQ_ASC_CON);
spin_unlock_irqrestore(<q_port->lock, flags);
retval = ltq_port->soc->request_irq(port);
if (retval)
return retval;
__raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
port->membase + LTQ_ASC_IRNREN);
return retval;
}
static void
lqasc_shutdown(struct uart_port *port)
{
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
unsigned long flags;
ltq_port->soc->free_irq(port);
spin_lock_irqsave(<q_port->lock, flags);
__raw_writel(0, port->membase + LTQ_ASC_CON);
asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
port->membase + LTQ_ASC_RXFCON);
asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
port->membase + LTQ_ASC_TXFCON);
spin_unlock_irqrestore(<q_port->lock, flags);
if (!IS_ERR(ltq_port->clk))
clk_disable_unprepare(ltq_port->clk);
}
static void
lqasc_set_termios(struct uart_port *port, struct ktermios *new,
const struct ktermios *old)
{
unsigned int cflag;
unsigned int iflag;
unsigned int divisor;
unsigned int baud;
unsigned int con = 0;
unsigned long flags;
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
cflag = new->c_cflag;
iflag = new->c_iflag;
switch (cflag & CSIZE) {
case CS7:
con = ASCCON_M_7ASYNC;
break;
case CS5:
case CS6:
default:
new->c_cflag &= ~ CSIZE;
new->c_cflag |= CS8;
con = ASCCON_M_8ASYNC;
break;
}
cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
if (cflag & CSTOPB)
con |= ASCCON_STP;
if (cflag & PARENB) {
if (!(cflag & PARODD))
con &= ~ASCCON_ODD;
else
con |= ASCCON_ODD;
}
port->read_status_mask = ASCSTATE_ROE;
if (iflag & INPCK)
port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
port->ignore_status_mask = 0;
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
if (iflag & IGNBRK) {
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (iflag & IGNPAR)
port->ignore_status_mask |= ASCSTATE_ROE;
}
if ((cflag & CREAD) == 0)
port->ignore_status_mask |= UART_DUMMY_UER_RX;
/* set error signals - framing, parity and overrun, enable receiver */
con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
spin_lock_irqsave(<q_port->lock, flags);
/* set up CON */
asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
/* Set baud rate - take a divider of 2 into account */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
divisor = uart_get_divisor(port, baud);
divisor = divisor / 2 - 1;
/* disable the baudrate generator */
asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
/* make sure the fractional divider is off */
asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
/* set up to use divisor of 2 */
asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
/* now we can write the new baudrate into the register */
__raw_writel(divisor, port->membase + LTQ_ASC_BG);
/* turn the baudrate generator back on */
asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
/* enable rx */
__raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
spin_unlock_irqrestore(<q_port->lock, flags);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(new))
tty_termios_encode_baud_rate(new, baud, baud);
uart_update_timeout(port, cflag, baud);
}
static const char*
lqasc_type(struct uart_port *port)
{
if (port->type == PORT_LTQ_ASC)
return DRVNAME;
else
return NULL;
}
static void
lqasc_release_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
if (port->flags & UPF_IOREMAP) {
devm_iounmap(&pdev->dev, port->membase);
port->membase = NULL;
}
}
static int
lqasc_request_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *res;
int size;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "cannot obtain I/O memory region");
return -ENODEV;
}
size = resource_size(res);
res = devm_request_mem_region(&pdev->dev, res->start,
size, dev_name(&pdev->dev));
if (!res) {
dev_err(&pdev->dev, "cannot request I/O memory region");
return -EBUSY;
}
if (port->flags & UPF_IOREMAP) {
port->membase = devm_ioremap(&pdev->dev,
port->mapbase, size);
if (port->membase == NULL)
return -ENOMEM;
}
return 0;
}
static void
lqasc_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_LTQ_ASC;
lqasc_request_port(port);
}
}
static int
lqasc_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= NR_IRQS)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
return ret;
}
static const struct uart_ops lqasc_pops = {
.tx_empty = lqasc_tx_empty,
.set_mctrl = lqasc_set_mctrl,
.get_mctrl = lqasc_get_mctrl,
.stop_tx = lqasc_stop_tx,
.start_tx = lqasc_start_tx,
.stop_rx = lqasc_stop_rx,
.break_ctl = lqasc_break_ctl,
.startup = lqasc_startup,
.shutdown = lqasc_shutdown,
.set_termios = lqasc_set_termios,
.type = lqasc_type,
.release_port = lqasc_release_port,
.request_port = lqasc_request_port,
.config_port = lqasc_config_port,
.verify_port = lqasc_verify_port,
};
#ifdef CONFIG_SERIAL_LANTIQ_CONSOLE
static void
lqasc_console_putchar(struct uart_port *port, unsigned char ch)
{
if (!port->membase)
return;
while (!lqasc_tx_ready(port))
;
writeb(ch, port->membase + LTQ_ASC_TBUF);
}
static void lqasc_serial_port_write(struct uart_port *port, const char *s,
u_int count)
{
uart_console_write(port, s, count, lqasc_console_putchar);
}
static void
lqasc_console_write(struct console *co, const char *s, u_int count)
{
struct ltq_uart_port *ltq_port;
unsigned long flags;
if (co->index >= MAXPORTS)
return;
ltq_port = lqasc_port[co->index];
if (!ltq_port)
return;
spin_lock_irqsave(<q_port->lock, flags);
lqasc_serial_port_write(<q_port->port, s, count);
spin_unlock_irqrestore(<q_port->lock, flags);
}
static int __init
lqasc_console_setup(struct console *co, char *options)
{
struct ltq_uart_port *ltq_port;
struct uart_port *port;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (co->index >= MAXPORTS)
return -ENODEV;
ltq_port = lqasc_port[co->index];
if (!ltq_port)
return -ENODEV;
port = <q_port->port;
if (!IS_ERR(ltq_port->clk))
clk_prepare_enable(ltq_port->clk);
port->uartclk = clk_get_rate(ltq_port->freqclk);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct console lqasc_console = {
.name = "ttyLTQ",
.write = lqasc_console_write,
.device = uart_console_device,
.setup = lqasc_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &lqasc_reg,
};
static int __init
lqasc_console_init(void)
{
register_console(&lqasc_console);
return 0;
}
console_initcall(lqasc_console_init);
static void lqasc_serial_early_console_write(struct console *co,
const char *s,
u_int count)
{
struct earlycon_device *dev = co->data;
lqasc_serial_port_write(&dev->port, s, count);
}
static int __init
lqasc_serial_early_console_setup(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = lqasc_serial_early_console_write;
return 0;
}
OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
#define LANTIQ_SERIAL_CONSOLE (&lqasc_console)
#else
#define LANTIQ_SERIAL_CONSOLE NULL
#endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */
static struct uart_driver lqasc_reg = {
.owner = THIS_MODULE,
.driver_name = DRVNAME,
.dev_name = "ttyLTQ",
.major = 0,
.minor = 0,
.nr = MAXPORTS,
.cons = LANTIQ_SERIAL_CONSOLE,
};
static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
{
struct uart_port *port = <q_port->port;
struct platform_device *pdev = to_platform_device(dev);
int irq;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ltq_port->tx_irq = irq;
irq = platform_get_irq(pdev, 1);
if (irq < 0)
return irq;
ltq_port->rx_irq = irq;
irq = platform_get_irq(pdev, 2);
if (irq < 0)
return irq;
ltq_port->err_irq = irq;
port->irq = ltq_port->tx_irq;
return 0;
}
static int request_irq_lantiq(struct uart_port *port)
{
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
int retval;
retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
0, "asc_tx", port);
if (retval) {
dev_err(port->dev, "failed to request asc_tx\n");
return retval;
}
retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
0, "asc_rx", port);
if (retval) {
dev_err(port->dev, "failed to request asc_rx\n");
goto err1;
}
retval = request_irq(ltq_port->err_irq, lqasc_err_int,
0, "asc_err", port);
if (retval) {
dev_err(port->dev, "failed to request asc_err\n");
goto err2;
}
return 0;
err2:
free_irq(ltq_port->rx_irq, port);
err1:
free_irq(ltq_port->tx_irq, port);
return retval;
}
static void free_irq_lantiq(struct uart_port *port)
{
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
free_irq(ltq_port->tx_irq, port);
free_irq(ltq_port->rx_irq, port);
free_irq(ltq_port->err_irq, port);
}
static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
{
struct uart_port *port = <q_port->port;
int ret;
ret = platform_get_irq(to_platform_device(dev), 0);
if (ret < 0) {
dev_err(dev, "failed to fetch IRQ for serial port\n");
return ret;
}
ltq_port->common_irq = ret;
port->irq = ret;
return 0;
}
static int request_irq_intel(struct uart_port *port)
{
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
int retval;
retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
"asc_irq", port);
if (retval)
dev_err(port->dev, "failed to request asc_irq\n");
return retval;
}
static void free_irq_intel(struct uart_port *port)
{
struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
free_irq(ltq_port->common_irq, port);
}
static int lqasc_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct ltq_uart_port *ltq_port;
struct uart_port *port;
struct resource *mmres;
int line;
int ret;
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mmres) {
dev_err(&pdev->dev,
"failed to get memory for serial port\n");
return -ENODEV;
}
ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
GFP_KERNEL);
if (!ltq_port)
return -ENOMEM;
port = <q_port->port;
ltq_port->soc = of_device_get_match_data(&pdev->dev);
ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
if (ret)
return ret;
/* get serial id */
line = of_alias_get_id(node, "serial");
if (line < 0) {
if (IS_ENABLED(CONFIG_LANTIQ)) {
if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
line = 0;
else
line = 1;
} else {
dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
line);
return line;
}
}
if (lqasc_port[line]) {
dev_err(&pdev->dev, "port %d already allocated\n", line);
return -EBUSY;
}
port->iotype = SERIAL_IO_MEM;
port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
port->ops = &lqasc_pops;
port->fifosize = 16;
port->type = PORT_LTQ_ASC;
port->line = line;
port->dev = &pdev->dev;
/* unused, just to be backward-compatible */
port->mapbase = mmres->start;
if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
ltq_port->freqclk = clk_get_fpi();
else
ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
if (IS_ERR(ltq_port->freqclk)) {
pr_err("failed to get fpi clk\n");
return -ENOENT;
}
/* not all asc ports have clock gates, lets ignore the return code */
if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
ltq_port->clk = clk_get(&pdev->dev, NULL);
else
ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
spin_lock_init(<q_port->lock);
lqasc_port[line] = ltq_port;
platform_set_drvdata(pdev, ltq_port);
ret = uart_add_one_port(&lqasc_reg, port);
return ret;
}
static int lqasc_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
uart_remove_one_port(&lqasc_reg, port);
return 0;
}
static const struct ltq_soc_data soc_data_lantiq = {
.fetch_irq = fetch_irq_lantiq,
.request_irq = request_irq_lantiq,
.free_irq = free_irq_lantiq,
};
static const struct ltq_soc_data soc_data_intel = {
.fetch_irq = fetch_irq_intel,
.request_irq = request_irq_intel,
.free_irq = free_irq_intel,
};
static const struct of_device_id ltq_asc_match[] = {
{ .compatible = "lantiq,asc", .data = &soc_data_lantiq },
{ .compatible = "intel,lgm-asc", .data = &soc_data_intel },
{},
};
MODULE_DEVICE_TABLE(of, ltq_asc_match);
static struct platform_driver lqasc_driver = {
.probe = lqasc_probe,
.remove = lqasc_remove,
.driver = {
.name = DRVNAME,
.of_match_table = ltq_asc_match,
},
};
static int __init
init_lqasc(void)
{
int ret;
ret = uart_register_driver(&lqasc_reg);
if (ret != 0)
return ret;
ret = platform_driver_register(&lqasc_driver);
if (ret != 0)
uart_unregister_driver(&lqasc_reg);
return ret;
}
static void __exit exit_lqasc(void)
{
platform_driver_unregister(&lqasc_driver);
uart_unregister_driver(&lqasc_reg);
}
module_init(init_lqasc);
module_exit(exit_lqasc);
MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/lantiq.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Freescale QUICC Engine UART device driver
*
* Author: Timur Tabi <[email protected]>
*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This driver adds support for UART devices via Freescale's QUICC Engine
* found on some Freescale SOCs.
*
* If Soft-UART support is needed but not already present, then this driver
* will request and upload the "Soft-UART" microcode upon probe. The
* filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
* is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
* (e.g. "11" for 1.1).
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/dma-mapping.h>
#include <soc/fsl/qe/ucc_slow.h>
#include <linux/firmware.h>
#include <soc/fsl/cpm.h>
#ifdef CONFIG_PPC32
#include <asm/reg.h> /* mfspr, SPRN_SVR */
#endif
/*
* The GUMR flag for Soft UART. This would normally be defined in qe.h,
* but Soft-UART is a hack and we want to keep everything related to it in
* this file.
*/
#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
/*
* soft_uart is 1 if we need to use Soft-UART mode
*/
static int soft_uart;
/*
* firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
*/
static int firmware_loaded;
/* Enable this macro to configure all serial ports in internal loopback
mode */
/* #define LOOPBACK */
/* The major and minor device numbers are defined in
* Documentation/admin-guide/devices.txt. For the QE
* UART, we have major number 204 and minor numbers 46 - 49, which are the
* same as for the CPM2. This decision was made because no Freescale part
* has both a CPM and a QE.
*/
#define SERIAL_QE_MAJOR 204
#define SERIAL_QE_MINOR 46
/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
#define UCC_MAX_UART 4
/* The number of buffer descriptors for receiving characters. */
#define RX_NUM_FIFO 4
/* The number of buffer descriptors for transmitting characters. */
#define TX_NUM_FIFO 4
/* The maximum size of the character buffer for a single RX BD. */
#define RX_BUF_SIZE 32
/* The maximum size of the character buffer for a single TX BD. */
#define TX_BUF_SIZE 32
/*
* The number of jiffies to wait after receiving a close command before the
* device is actually closed. This allows the last few characters to be
* sent over the wire.
*/
#define UCC_WAIT_CLOSING 100
struct ucc_uart_pram {
struct ucc_slow_pram common;
u8 res1[8]; /* reserved */
__be16 maxidl; /* Maximum idle chars */
__be16 idlc; /* temp idle counter */
__be16 brkcr; /* Break count register */
__be16 parec; /* receive parity error counter */
__be16 frmec; /* receive framing error counter */
__be16 nosec; /* receive noise counter */
__be16 brkec; /* receive break condition counter */
__be16 brkln; /* last received break length */
__be16 uaddr[2]; /* UART address character 1 & 2 */
__be16 rtemp; /* Temp storage */
__be16 toseq; /* Transmit out of sequence char */
__be16 cchars[8]; /* control characters 1-8 */
__be16 rccm; /* receive control character mask */
__be16 rccr; /* receive control character register */
__be16 rlbc; /* receive last break character */
__be16 res2; /* reserved */
__be32 res3; /* reserved, should be cleared */
u8 res4; /* reserved, should be cleared */
u8 res5[3]; /* reserved, should be cleared */
__be32 res6; /* reserved, should be cleared */
__be32 res7; /* reserved, should be cleared */
__be32 res8; /* reserved, should be cleared */
__be32 res9; /* reserved, should be cleared */
__be32 res10; /* reserved, should be cleared */
__be32 res11; /* reserved, should be cleared */
__be32 res12; /* reserved, should be cleared */
__be32 res13; /* reserved, should be cleared */
/* The rest is for Soft-UART only */
__be16 supsmr; /* 0x90, Shadow UPSMR */
__be16 res92; /* 0x92, reserved, initialize to 0 */
__be32 rx_state; /* 0x94, RX state, initialize to 0 */
__be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
u8 res14[0xBC - 0x9F]; /* reserved */
__be32 dump_ptr; /* 0xBC, Dump pointer */
__be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
__be16 tx_state; /* 0xC6, TX state */
u8 res15[0xD0 - 0xC8]; /* reserved */
__be32 resD0; /* 0xD0, reserved, initialize to 0 */
u8 resD4; /* 0xD4, reserved, initialize to 0 */
__be16 resD5; /* 0xD5, reserved, initialize to 0 */
} __attribute__ ((packed));
/* SUPSMR definitions, for Soft-UART only */
#define UCC_UART_SUPSMR_SL 0x8000
#define UCC_UART_SUPSMR_RPM_MASK 0x6000
#define UCC_UART_SUPSMR_RPM_ODD 0x0000
#define UCC_UART_SUPSMR_RPM_LOW 0x2000
#define UCC_UART_SUPSMR_RPM_EVEN 0x4000
#define UCC_UART_SUPSMR_RPM_HIGH 0x6000
#define UCC_UART_SUPSMR_PEN 0x1000
#define UCC_UART_SUPSMR_TPM_MASK 0x0C00
#define UCC_UART_SUPSMR_TPM_ODD 0x0000
#define UCC_UART_SUPSMR_TPM_LOW 0x0400
#define UCC_UART_SUPSMR_TPM_EVEN 0x0800
#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
#define UCC_UART_SUPSMR_FRZ 0x0100
#define UCC_UART_SUPSMR_UM_MASK 0x00c0
#define UCC_UART_SUPSMR_UM_NORMAL 0x0000
#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
#define UCC_UART_SUPSMR_CL_MASK 0x0030
#define UCC_UART_SUPSMR_CL_8 0x0030
#define UCC_UART_SUPSMR_CL_7 0x0020
#define UCC_UART_SUPSMR_CL_6 0x0010
#define UCC_UART_SUPSMR_CL_5 0x0000
#define UCC_UART_TX_STATE_AHDLC 0x00
#define UCC_UART_TX_STATE_UART 0x01
#define UCC_UART_TX_STATE_X1 0x00
#define UCC_UART_TX_STATE_X16 0x80
#define UCC_UART_PRAM_ALIGNMENT 0x100
#define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
#define NUM_CONTROL_CHARS 8
/* Private per-port data structure */
struct uart_qe_port {
struct uart_port port;
struct ucc_slow __iomem *uccp;
struct ucc_uart_pram __iomem *uccup;
struct ucc_slow_info us_info;
struct ucc_slow_private *us_private;
struct device_node *np;
unsigned int ucc_num; /* First ucc is 0, not 1 */
u16 rx_nrfifos;
u16 rx_fifosize;
u16 tx_nrfifos;
u16 tx_fifosize;
int wait_closing;
u32 flags;
struct qe_bd *rx_bd_base;
struct qe_bd *rx_cur;
struct qe_bd *tx_bd_base;
struct qe_bd *tx_cur;
unsigned char *tx_buf;
unsigned char *rx_buf;
void *bd_virt; /* virtual address of the BD buffers */
dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
unsigned int bd_size; /* size of BD buffer space */
};
static struct uart_driver ucc_uart_driver = {
.owner = THIS_MODULE,
.driver_name = "ucc_uart",
.dev_name = "ttyQE",
.major = SERIAL_QE_MAJOR,
.minor = SERIAL_QE_MINOR,
.nr = UCC_MAX_UART,
};
/*
* Virtual to physical address translation.
*
* Given the virtual address for a character buffer, this function returns
* the physical (DMA) equivalent.
*/
static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
{
if (likely((addr >= qe_port->bd_virt)) &&
(addr < (qe_port->bd_virt + qe_port->bd_size)))
return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
/* something nasty happened */
printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
BUG();
return 0;
}
/*
* Physical to virtual address translation.
*
* Given the physical (DMA) address for a character buffer, this function
* returns the virtual equivalent.
*/
static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
{
/* sanity check */
if (likely((addr >= qe_port->bd_dma_addr) &&
(addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
/* something nasty happened */
printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
BUG();
return NULL;
}
/*
* Return 1 if the QE is done transmitting all buffers for this port
*
* This function scans each BD in sequence. If we find a BD that is not
* ready (READY=1), then we return 0 indicating that the QE is still sending
* data. If we reach the last BD (WRAP=1), then we know we've scanned
* the entire list, and all BDs are done.
*/
static unsigned int qe_uart_tx_empty(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
struct qe_bd *bdp = qe_port->tx_bd_base;
while (1) {
if (ioread16be(&bdp->status) & BD_SC_READY)
/* This BD is not done, so return "not done" */
return 0;
if (ioread16be(&bdp->status) & BD_SC_WRAP)
/*
* This BD is done and it's the last one, so return
* "done"
*/
return 1;
bdp++;
}
}
/*
* Set the modem control lines
*
* Although the QE can control the modem control lines (e.g. CTS), we
* don't need that support. This function must exist, however, otherwise
* the kernel will panic.
*/
static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}
/*
* Get the current modem control line status
*
* Although the QE can control the modem control lines (e.g. CTS), this
* driver currently doesn't support that, so we always return Carrier
* Detect, Data Set Ready, and Clear To Send.
*/
static unsigned int qe_uart_get_mctrl(struct uart_port *port)
{
return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
}
/*
* Disable the transmit interrupt.
*
* Although this function is called "stop_tx", it does not actually stop
* transmission of data. Instead, it tells the QE to not generate an
* interrupt when the UCC is finished sending characters.
*/
static void qe_uart_stop_tx(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
}
/*
* Transmit as many characters to the HW as possible.
*
* This function will attempt to stuff of all the characters from the
* kernel's transmit buffer into TX BDs.
*
* A return value of non-zero indicates that it successfully stuffed all
* characters from the kernel buffer.
*
* A return value of zero indicates that there are still characters in the
* kernel's buffer that have not been transmitted, but there are no more BDs
* available. This function should be called again after a BD has been made
* available.
*/
static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
{
struct qe_bd *bdp;
unsigned char *p;
unsigned int count;
struct uart_port *port = &qe_port->port;
struct circ_buf *xmit = &port->state->xmit;
/* Handle xon/xoff */
if (port->x_char) {
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;
p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
*p++ = port->x_char;
iowrite16be(1, &bdp->length);
qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
if (ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
qe_port->tx_cur = bdp;
port->icount.tx++;
port->x_char = 0;
return 1;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
qe_uart_stop_tx(port);
return 0;
}
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;
while (!(ioread16be(&bdp->status) & BD_SC_READY) && !uart_circ_empty(xmit)) {
count = 0;
p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
while (count < qe_port->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
uart_xmit_advance(port, 1);
count++;
if (uart_circ_empty(xmit))
break;
}
iowrite16be(count, &bdp->length);
qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
if (ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
}
qe_port->tx_cur = bdp;
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit)) {
/* The kernel buffer is empty, so turn off TX interrupts. We
don't need to be told when the QE is finished transmitting
the data. */
qe_uart_stop_tx(port);
return 0;
}
return 1;
}
/*
* Start transmitting data
*
* This function will start transmitting any available data, if the port
* isn't already transmitting data.
*/
static void qe_uart_start_tx(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
/* If we currently are transmitting, then just return */
if (ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
return;
/* Otherwise, pump the port and start transmission */
if (qe_uart_tx_pump(qe_port))
qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
}
/*
* Stop transmitting data
*/
static void qe_uart_stop_rx(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
}
/* Start or stop sending break signal
*
* This function controls the sending of a break signal. If break_state=1,
* then we start sending a break signal. If break_state=0, then we stop
* sending the break signal.
*/
static void qe_uart_break_ctl(struct uart_port *port, int break_state)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
if (break_state)
ucc_slow_stop_tx(qe_port->us_private);
else
ucc_slow_restart_tx(qe_port->us_private);
}
/* ISR helper function for receiving character.
*
* This function is called by the ISR to handling receiving characters
*/
static void qe_uart_int_rx(struct uart_qe_port *qe_port)
{
int i;
unsigned char ch, *cp;
struct uart_port *port = &qe_port->port;
struct tty_port *tport = &port->state->port;
struct qe_bd *bdp;
u16 status;
unsigned int flg;
/* Just loop through the closed BDs and copy the characters into
* the buffer.
*/
bdp = qe_port->rx_cur;
while (1) {
status = ioread16be(&bdp->status);
/* If this one is empty, then we assume we've read them all */
if (status & BD_SC_EMPTY)
break;
/* get number of characters, and check space in RX buffer */
i = ioread16be(&bdp->length);
/* If we don't have enough room in RX buffer for the entire BD,
* then we try later, which will be the next RX interrupt.
*/
if (tty_buffer_request_room(tport, i) < i) {
dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
return;
}
/* get pointer */
cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
/* loop through the buffer */
while (i-- > 0) {
ch = *cp++;
port->icount.rx++;
flg = TTY_NORMAL;
if (!i && status &
(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
goto handle_error;
if (uart_handle_sysrq_char(port, ch))
continue;
error_return:
tty_insert_flip_char(tport, ch, flg);
}
/* This BD is ready to be used again. Clear status. get next */
qe_clrsetbits_be16(&bdp->status,
BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
BD_SC_EMPTY);
if (ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->rx_bd_base;
else
bdp++;
}
/* Write back buffer pointer */
qe_port->rx_cur = bdp;
/* Activate BH processing */
tty_flip_buffer_push(tport);
return;
/* Error processing */
handle_error:
/* Statistics */
if (status & BD_SC_BR)
port->icount.brk++;
if (status & BD_SC_PR)
port->icount.parity++;
if (status & BD_SC_FR)
port->icount.frame++;
if (status & BD_SC_OV)
port->icount.overrun++;
/* Mask out ignored conditions */
status &= port->read_status_mask;
/* Handle the remaining ones */
if (status & BD_SC_BR)
flg = TTY_BREAK;
else if (status & BD_SC_PR)
flg = TTY_PARITY;
else if (status & BD_SC_FR)
flg = TTY_FRAME;
/* Overrun does not affect the current character ! */
if (status & BD_SC_OV)
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
port->sysrq = 0;
goto error_return;
}
/* Interrupt handler
*
* This interrupt handler is called after a BD is processed.
*/
static irqreturn_t qe_uart_int(int irq, void *data)
{
struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
struct ucc_slow __iomem *uccp = qe_port->uccp;
u16 events;
/* Clear the interrupts */
events = ioread16be(&uccp->ucce);
iowrite16be(events, &uccp->ucce);
if (events & UCC_UART_UCCE_BRKE)
uart_handle_break(&qe_port->port);
if (events & UCC_UART_UCCE_RX)
qe_uart_int_rx(qe_port);
if (events & UCC_UART_UCCE_TX)
qe_uart_tx_pump(qe_port);
return events ? IRQ_HANDLED : IRQ_NONE;
}
/* Initialize buffer descriptors
*
* This function initializes all of the RX and TX buffer descriptors.
*/
static void qe_uart_initbd(struct uart_qe_port *qe_port)
{
int i;
void *bd_virt;
struct qe_bd *bdp;
/* Set the physical address of the host memory buffers in the buffer
* descriptors, and the virtual address for us to work with.
*/
bd_virt = qe_port->bd_virt;
bdp = qe_port->rx_bd_base;
qe_port->rx_cur = qe_port->rx_bd_base;
for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
iowrite16be(0, &bdp->length);
bd_virt += qe_port->rx_fifosize;
bdp++;
}
/* */
iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
iowrite16be(0, &bdp->length);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
* virtual address for us to work with.
*/
bd_virt = qe_port->bd_virt +
L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
qe_port->tx_cur = qe_port->tx_bd_base;
bdp = qe_port->tx_bd_base;
for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
iowrite16be(BD_SC_INTRPT, &bdp->status);
iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
iowrite16be(0, &bdp->length);
bd_virt += qe_port->tx_fifosize;
bdp++;
}
/* Loopback requires the preamble bit to be set on the first TX BD */
#ifdef LOOPBACK
qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
#endif
iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
iowrite16be(0, &bdp->length);
}
/*
* Initialize a UCC for UART.
*
* This function configures a given UCC to be used as a UART device. Basic
* UCC initialization is handled in qe_uart_request_port(). This function
* does all the UART-specific stuff.
*/
static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
{
u32 cecr_subblock;
struct ucc_slow __iomem *uccp = qe_port->uccp;
struct ucc_uart_pram *uccup = qe_port->uccup;
unsigned int i;
/* First, disable TX and RX in the UCC */
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
/* Program the UCC UART parameter RAM */
iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
iowrite16be(0x10, &uccup->maxidl);
iowrite16be(1, &uccup->brkcr);
iowrite16be(0, &uccup->parec);
iowrite16be(0, &uccup->frmec);
iowrite16be(0, &uccup->nosec);
iowrite16be(0, &uccup->brkec);
iowrite16be(0, &uccup->uaddr[0]);
iowrite16be(0, &uccup->uaddr[1]);
iowrite16be(0, &uccup->toseq);
for (i = 0; i < 8; i++)
iowrite16be(0xC000, &uccup->cchars[i]);
iowrite16be(0xc0ff, &uccup->rccm);
/* Configure the GUMR registers for UART */
if (soft_uart) {
/* Soft-UART requires a 1X multiplier for TX */
qe_clrsetbits_be32(&uccp->gumr_l,
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
} else {
qe_clrsetbits_be32(&uccp->gumr_l,
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
qe_clrsetbits_be32(&uccp->gumr_h,
UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
UCC_SLOW_GUMR_H_RFW);
}
#ifdef LOOPBACK
qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
UCC_SLOW_GUMR_L_DIAG_LOOP);
qe_clrsetbits_be32(&uccp->gumr_h,
UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
UCC_SLOW_GUMR_H_CDS);
#endif
/* Disable rx interrupts and clear all pending events. */
iowrite16be(0, &uccp->uccm);
iowrite16be(0xffff, &uccp->ucce);
iowrite16be(0x7e7e, &uccp->udsr);
/* Initialize UPSMR */
iowrite16be(0, &uccp->upsmr);
if (soft_uart) {
iowrite16be(0x30, &uccup->supsmr);
iowrite16be(0, &uccup->res92);
iowrite32be(0, &uccup->rx_state);
iowrite32be(0, &uccup->rx_cnt);
iowrite8(0, &uccup->rx_bitmark);
iowrite8(10, &uccup->rx_length);
iowrite32be(0x4000, &uccup->dump_ptr);
iowrite8(0, &uccup->rx_temp_dlst_qe);
iowrite32be(0, &uccup->rx_frame_rem);
iowrite8(0, &uccup->rx_frame_rem_size);
/* Soft-UART requires TX to be 1X */
iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
&uccup->tx_mode);
iowrite16be(0, &uccup->tx_state);
iowrite8(0, &uccup->resD4);
iowrite16be(0, &uccup->resD5);
/* Set UART mode.
* Enable receive and transmit.
*/
/* From the microcode errata:
* 1.GUMR_L register, set mode=0010 (QMC).
* 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
* 3.Set GUMR_H[19:20] (Transparent mode)
* 4.Clear GUMR_H[26] (RFW)
* ...
* 6.Receiver must use 16x over sampling
*/
qe_clrsetbits_be32(&uccp->gumr_l,
UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
qe_clrsetbits_be32(&uccp->gumr_h,
UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
#ifdef LOOPBACK
qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
UCC_SLOW_GUMR_L_DIAG_LOOP);
qe_clrbits_be32(&uccp->gumr_h,
UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
#endif
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
QE_CR_PROTOCOL_UNSPECIFIED, 0);
} else {
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
QE_CR_PROTOCOL_UART, 0);
}
}
/*
* Initialize the port.
*/
static int qe_uart_startup(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
int ret;
/*
* If we're using Soft-UART mode, then we need to make sure the
* firmware has been uploaded first.
*/
if (soft_uart && !firmware_loaded) {
dev_err(port->dev, "Soft-UART firmware not uploaded\n");
return -ENODEV;
}
qe_uart_initbd(qe_port);
qe_uart_init_ucc(qe_port);
/* Install interrupt handler. */
ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
qe_port);
if (ret) {
dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
return ret;
}
/* Startup rx-int */
qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
return 0;
}
/*
* Shutdown the port.
*/
static void qe_uart_shutdown(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
struct ucc_slow __iomem *uccp = qe_port->uccp;
unsigned int timeout = 20;
/* Disable RX and TX */
/* Wait for all the BDs marked sent */
while (!qe_uart_tx_empty(port)) {
if (!--timeout) {
dev_warn(port->dev, "shutdown timeout\n");
break;
}
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(2);
}
if (qe_port->wait_closing) {
/* Wait a bit longer */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(qe_port->wait_closing);
}
/* Stop uarts */
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
/* Shut them really down and reinit buffer descriptors */
ucc_slow_graceful_stop_tx(qe_port->us_private);
qe_uart_initbd(qe_port);
free_irq(port->irq, qe_port);
}
/*
* Set the serial port parameters.
*/
static void qe_uart_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
struct ucc_slow __iomem *uccp = qe_port->uccp;
unsigned int baud;
unsigned long flags;
u16 upsmr = ioread16be(&uccp->upsmr);
struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
u16 supsmr = ioread16be(&uccup->supsmr);
/* byte size */
upsmr &= UCC_UART_UPSMR_CL_MASK;
supsmr &= UCC_UART_SUPSMR_CL_MASK;
switch (termios->c_cflag & CSIZE) {
case CS5:
upsmr |= UCC_UART_UPSMR_CL_5;
supsmr |= UCC_UART_SUPSMR_CL_5;
break;
case CS6:
upsmr |= UCC_UART_UPSMR_CL_6;
supsmr |= UCC_UART_SUPSMR_CL_6;
break;
case CS7:
upsmr |= UCC_UART_UPSMR_CL_7;
supsmr |= UCC_UART_SUPSMR_CL_7;
break;
default: /* case CS8 */
upsmr |= UCC_UART_UPSMR_CL_8;
supsmr |= UCC_UART_SUPSMR_CL_8;
break;
}
/* If CSTOPB is set, we want two stop bits */
if (termios->c_cflag & CSTOPB) {
upsmr |= UCC_UART_UPSMR_SL;
supsmr |= UCC_UART_SUPSMR_SL;
}
if (termios->c_cflag & PARENB) {
upsmr |= UCC_UART_UPSMR_PEN;
supsmr |= UCC_UART_SUPSMR_PEN;
if (!(termios->c_cflag & PARODD)) {
upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
UCC_UART_UPSMR_TPM_MASK);
upsmr |= UCC_UART_UPSMR_RPM_EVEN |
UCC_UART_UPSMR_TPM_EVEN;
supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
UCC_UART_SUPSMR_TPM_MASK);
supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
UCC_UART_SUPSMR_TPM_EVEN;
}
}
/*
* Set up parity check flag
*/
port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
if (termios->c_iflag & INPCK)
port->read_status_mask |= BD_SC_FR | BD_SC_PR;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
port->read_status_mask |= BD_SC_BR;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= BD_SC_BR;
/*
* If we're ignore parity and break indicators, ignore
* overruns too. (For real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= BD_SC_OV;
}
/*
* !!! ignore all characters if CREAD is not set
*/
if ((termios->c_cflag & CREAD) == 0)
port->read_status_mask &= ~BD_SC_EMPTY;
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
/* Do we really need a spinlock here? */
spin_lock_irqsave(&port->lock, flags);
/* Update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);
iowrite16be(upsmr, &uccp->upsmr);
if (soft_uart) {
iowrite16be(supsmr, &uccup->supsmr);
iowrite8(tty_get_frame_size(termios->c_cflag), &uccup->rx_length);
/* Soft-UART requires a 1X multiplier for TX */
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
} else {
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
}
spin_unlock_irqrestore(&port->lock, flags);
}
/*
* Return a pointer to a string that describes what kind of port this is.
*/
static const char *qe_uart_type(struct uart_port *port)
{
return "QE";
}
/*
* Allocate any memory and I/O resources required by the port.
*/
static int qe_uart_request_port(struct uart_port *port)
{
int ret;
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
struct ucc_slow_info *us_info = &qe_port->us_info;
struct ucc_slow_private *uccs;
unsigned int rx_size, tx_size;
void *bd_virt;
dma_addr_t bd_dma_addr = 0;
ret = ucc_slow_init(us_info, &uccs);
if (ret) {
dev_err(port->dev, "could not initialize UCC%u\n",
qe_port->ucc_num);
return ret;
}
qe_port->us_private = uccs;
qe_port->uccp = uccs->us_regs;
qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
qe_port->rx_bd_base = uccs->rx_bd;
qe_port->tx_bd_base = uccs->tx_bd;
/*
* Allocate the transmit and receive data buffers.
*/
rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
GFP_KERNEL);
if (!bd_virt) {
dev_err(port->dev, "could not allocate buffer descriptors\n");
return -ENOMEM;
}
qe_port->bd_virt = bd_virt;
qe_port->bd_dma_addr = bd_dma_addr;
qe_port->bd_size = rx_size + tx_size;
qe_port->rx_buf = bd_virt;
qe_port->tx_buf = qe_port->rx_buf + rx_size;
return 0;
}
/*
* Configure the port.
*
* We say we're a CPM-type port because that's mostly true. Once the device
* is configured, this driver operates almost identically to the CPM serial
* driver.
*/
static void qe_uart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
port->type = PORT_CPM;
qe_uart_request_port(port);
}
}
/*
* Release any memory and I/O resources that were allocated in
* qe_uart_request_port().
*/
static void qe_uart_release_port(struct uart_port *port)
{
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
struct ucc_slow_private *uccs = qe_port->us_private;
dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
qe_port->bd_dma_addr);
ucc_slow_free(uccs);
}
/*
* Verify that the data in serial_struct is suitable for this device.
*/
static int qe_uart_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
return -EINVAL;
if (ser->irq < 0 || ser->irq >= nr_irqs)
return -EINVAL;
if (ser->baud_base < 9600)
return -EINVAL;
return 0;
}
/* UART operations
*
* Details on these functions can be found in Documentation/driver-api/serial/driver.rst
*/
static const struct uart_ops qe_uart_pops = {
.tx_empty = qe_uart_tx_empty,
.set_mctrl = qe_uart_set_mctrl,
.get_mctrl = qe_uart_get_mctrl,
.stop_tx = qe_uart_stop_tx,
.start_tx = qe_uart_start_tx,
.stop_rx = qe_uart_stop_rx,
.break_ctl = qe_uart_break_ctl,
.startup = qe_uart_startup,
.shutdown = qe_uart_shutdown,
.set_termios = qe_uart_set_termios,
.type = qe_uart_type,
.release_port = qe_uart_release_port,
.request_port = qe_uart_request_port,
.config_port = qe_uart_config_port,
.verify_port = qe_uart_verify_port,
};
#ifdef CONFIG_PPC32
/*
* Obtain the SOC model number and revision level
*
* This function parses the device tree to obtain the SOC model. It then
* reads the SVR register to the revision.
*
* The device tree stores the SOC model two different ways.
*
* The new way is:
*
* cpu@0 {
* compatible = "PowerPC,8323";
* device_type = "cpu";
* ...
*
*
* The old way is:
* PowerPC,8323@0 {
* device_type = "cpu";
* ...
*
* This code first checks the new way, and then the old way.
*/
static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
{
struct device_node *np;
const char *soc_string;
unsigned int svr;
unsigned int soc;
/* Find the CPU node */
np = of_find_node_by_type(NULL, "cpu");
if (!np)
return 0;
/* Find the compatible property */
soc_string = of_get_property(np, "compatible", NULL);
if (!soc_string)
/* No compatible property, so try the name. */
soc_string = np->name;
of_node_put(np);
/* Extract the SOC number from the "PowerPC," string */
if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
return 0;
/* Get the revision from the SVR */
svr = mfspr(SPRN_SVR);
*rev_h = (svr >> 4) & 0xf;
*rev_l = svr & 0xf;
return soc;
}
/*
* requst_firmware_nowait() callback function
*
* This function is called by the kernel when a firmware is made available,
* or if it times out waiting for the firmware.
*/
static void uart_firmware_cont(const struct firmware *fw, void *context)
{
struct qe_firmware *firmware;
struct device *dev = context;
int ret;
if (!fw) {
dev_err(dev, "firmware not found\n");
return;
}
firmware = (struct qe_firmware *) fw->data;
if (firmware->header.length != fw->size) {
dev_err(dev, "invalid firmware\n");
goto out;
}
ret = qe_upload_firmware(firmware);
if (ret) {
dev_err(dev, "could not load firmware\n");
goto out;
}
firmware_loaded = 1;
out:
release_firmware(fw);
}
static int soft_uart_init(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
struct qe_firmware_info *qe_fw_info;
int ret;
if (of_property_read_bool(np, "soft-uart")) {
dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
soft_uart = 1;
} else {
return 0;
}
qe_fw_info = qe_get_firmware_info();
/* Check if the firmware has been uploaded. */
if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
firmware_loaded = 1;
} else {
char filename[32];
unsigned int soc;
unsigned int rev_h;
unsigned int rev_l;
soc = soc_info(&rev_h, &rev_l);
if (!soc) {
dev_err(&ofdev->dev, "unknown CPU model\n");
return -ENXIO;
}
sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
soc, rev_h, rev_l);
dev_info(&ofdev->dev, "waiting for firmware %s\n",
filename);
/*
* We call request_firmware_nowait instead of
* request_firmware so that the driver can load and
* initialize the ports without holding up the rest of
* the kernel. If hotplug support is enabled in the
* kernel, then we use it.
*/
ret = request_firmware_nowait(THIS_MODULE,
FW_ACTION_UEVENT, filename, &ofdev->dev,
GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
if (ret) {
dev_err(&ofdev->dev,
"could not load firmware %s\n",
filename);
return ret;
}
}
return 0;
}
#else /* !CONFIG_PPC32 */
static int soft_uart_init(struct platform_device *ofdev)
{
return 0;
}
#endif
static int ucc_uart_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
const char *sprop; /* String OF properties */
struct uart_qe_port *qe_port = NULL;
struct resource res;
u32 val;
int ret;
/*
* Determine if we need Soft-UART mode
*/
ret = soft_uart_init(ofdev);
if (ret)
return ret;
qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
if (!qe_port) {
dev_err(&ofdev->dev, "can't allocate QE port structure\n");
return -ENOMEM;
}
/* Search for IRQ and mapbase */
ret = of_address_to_resource(np, 0, &res);
if (ret) {
dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
goto out_free;
}
if (!res.start) {
dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
ret = -EINVAL;
goto out_free;
}
qe_port->port.mapbase = res.start;
/* Get the UCC number (device ID) */
/* UCCs are numbered 1-7 */
if (of_property_read_u32(np, "cell-index", &val)) {
if (of_property_read_u32(np, "device-id", &val)) {
dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
ret = -EINVAL;
goto out_free;
}
}
if (val < 1 || val > UCC_MAX_NUM) {
dev_err(&ofdev->dev, "no support for UCC%u\n", val);
ret = -ENODEV;
goto out_free;
}
qe_port->ucc_num = val - 1;
/*
* In the future, we should not require the BRG to be specified in the
* device tree. If no clock-source is specified, then just pick a BRG
* to use. This requires a new QE library function that manages BRG
* assignments.
*/
sprop = of_get_property(np, "rx-clock-name", NULL);
if (!sprop) {
dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
ret = -ENODEV;
goto out_free;
}
qe_port->us_info.rx_clock = qe_clock_source(sprop);
if ((qe_port->us_info.rx_clock < QE_BRG1) ||
(qe_port->us_info.rx_clock > QE_BRG16)) {
dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
ret = -ENODEV;
goto out_free;
}
#ifdef LOOPBACK
/* In internal loopback mode, TX and RX must use the same clock */
qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
#else
sprop = of_get_property(np, "tx-clock-name", NULL);
if (!sprop) {
dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
ret = -ENODEV;
goto out_free;
}
qe_port->us_info.tx_clock = qe_clock_source(sprop);
#endif
if ((qe_port->us_info.tx_clock < QE_BRG1) ||
(qe_port->us_info.tx_clock > QE_BRG16)) {
dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
ret = -ENODEV;
goto out_free;
}
/* Get the port number, numbered 0-3 */
if (of_property_read_u32(np, "port-number", &val)) {
dev_err(&ofdev->dev, "missing port-number in device tree\n");
ret = -EINVAL;
goto out_free;
}
qe_port->port.line = val;
if (qe_port->port.line >= UCC_MAX_UART) {
dev_err(&ofdev->dev, "port-number must be 0-%u\n",
UCC_MAX_UART - 1);
ret = -EINVAL;
goto out_free;
}
qe_port->port.irq = irq_of_parse_and_map(np, 0);
if (qe_port->port.irq == 0) {
dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
qe_port->ucc_num + 1);
ret = -EINVAL;
goto out_free;
}
/*
* Newer device trees have an "fsl,qe" compatible property for the QE
* node, but we still need to support older device trees.
*/
np = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!np) {
np = of_find_node_by_type(NULL, "qe");
if (!np) {
dev_err(&ofdev->dev, "could not find 'qe' node\n");
ret = -EINVAL;
goto out_free;
}
}
if (of_property_read_u32(np, "brg-frequency", &val)) {
dev_err(&ofdev->dev,
"missing brg-frequency in device tree\n");
ret = -EINVAL;
goto out_np;
}
if (val)
qe_port->port.uartclk = val;
else {
if (!IS_ENABLED(CONFIG_PPC32)) {
dev_err(&ofdev->dev,
"invalid brg-frequency in device tree\n");
ret = -EINVAL;
goto out_np;
}
/*
* Older versions of U-Boot do not initialize the brg-frequency
* property, so in this case we assume the BRG frequency is
* half the QE bus frequency.
*/
if (of_property_read_u32(np, "bus-frequency", &val)) {
dev_err(&ofdev->dev,
"missing QE bus-frequency in device tree\n");
ret = -EINVAL;
goto out_np;
}
if (val)
qe_port->port.uartclk = val / 2;
else {
dev_err(&ofdev->dev,
"invalid QE bus-frequency in device tree\n");
ret = -EINVAL;
goto out_np;
}
}
spin_lock_init(&qe_port->port.lock);
qe_port->np = np;
qe_port->port.dev = &ofdev->dev;
qe_port->port.ops = &qe_uart_pops;
qe_port->port.iotype = UPIO_MEM;
qe_port->tx_nrfifos = TX_NUM_FIFO;
qe_port->tx_fifosize = TX_BUF_SIZE;
qe_port->rx_nrfifos = RX_NUM_FIFO;
qe_port->rx_fifosize = RX_BUF_SIZE;
qe_port->wait_closing = UCC_WAIT_CLOSING;
qe_port->port.fifosize = 512;
qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
qe_port->us_info.ucc_num = qe_port->ucc_num;
qe_port->us_info.regs = (phys_addr_t) res.start;
qe_port->us_info.irq = qe_port->port.irq;
qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
/* Make sure ucc_slow_init() initializes both TX and RX */
qe_port->us_info.init_tx = 1;
qe_port->us_info.init_rx = 1;
/* Add the port to the uart sub-system. This will cause
* qe_uart_config_port() to be called, so the us_info structure must
* be initialized.
*/
ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
if (ret) {
dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
qe_port->port.line);
goto out_np;
}
platform_set_drvdata(ofdev, qe_port);
dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
qe_port->ucc_num + 1, qe_port->port.line);
/* Display the mknod command for this device */
dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
qe_port->port.line, SERIAL_QE_MAJOR,
SERIAL_QE_MINOR + qe_port->port.line);
return 0;
out_np:
of_node_put(np);
out_free:
kfree(qe_port);
return ret;
}
static int ucc_uart_remove(struct platform_device *ofdev)
{
struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
of_node_put(qe_port->np);
kfree(qe_port);
return 0;
}
static const struct of_device_id ucc_uart_match[] = {
{
.type = "serial",
.compatible = "ucc_uart",
},
{
.compatible = "fsl,t1040-ucc-uart",
},
{},
};
MODULE_DEVICE_TABLE(of, ucc_uart_match);
static struct platform_driver ucc_uart_of_driver = {
.driver = {
.name = "ucc_uart",
.of_match_table = ucc_uart_match,
},
.probe = ucc_uart_probe,
.remove = ucc_uart_remove,
};
static int __init ucc_uart_init(void)
{
int ret;
printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
#ifdef LOOPBACK
printk(KERN_INFO "ucc-uart: Using loopback mode\n");
#endif
ret = uart_register_driver(&ucc_uart_driver);
if (ret) {
printk(KERN_ERR "ucc-uart: could not register UART driver\n");
return ret;
}
ret = platform_driver_register(&ucc_uart_of_driver);
if (ret) {
printk(KERN_ERR
"ucc-uart: could not register platform driver\n");
uart_unregister_driver(&ucc_uart_driver);
}
return ret;
}
static void __exit ucc_uart_exit(void)
{
printk(KERN_INFO
"Freescale QUICC Engine UART device driver unloading\n");
platform_driver_unregister(&ucc_uart_of_driver);
uart_unregister_driver(&ucc_uart_driver);
}
module_init(ucc_uart_init);
module_exit(ucc_uart_exit);
MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
MODULE_AUTHOR("Timur Tabi <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
| linux-master | drivers/tty/serial/ucc_uart.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Helpers for controlling modem lines via GPIO
*
* Copyright (C) 2014 Paratronic S.A.
*/
#include <linux/err.h>
#include <linux/device.h>
#include <linux/irq.h>
#include <linux/gpio/consumer.h>
#include <linux/termios.h>
#include <linux/serial_core.h>
#include <linux/module.h>
#include <linux/property.h>
#include "serial_mctrl_gpio.h"
struct mctrl_gpios {
struct uart_port *port;
struct gpio_desc *gpio[UART_GPIO_MAX];
int irq[UART_GPIO_MAX];
unsigned int mctrl_prev;
bool mctrl_on;
};
static const struct {
const char *name;
unsigned int mctrl;
enum gpiod_flags flags;
} mctrl_gpios_desc[UART_GPIO_MAX] = {
{ "cts", TIOCM_CTS, GPIOD_IN, },
{ "dsr", TIOCM_DSR, GPIOD_IN, },
{ "dcd", TIOCM_CD, GPIOD_IN, },
{ "rng", TIOCM_RNG, GPIOD_IN, },
{ "rts", TIOCM_RTS, GPIOD_OUT_LOW, },
{ "dtr", TIOCM_DTR, GPIOD_OUT_LOW, },
};
static bool mctrl_gpio_flags_is_dir_out(unsigned int idx)
{
return mctrl_gpios_desc[idx].flags & GPIOD_FLAGS_BIT_DIR_OUT;
}
/**
* mctrl_gpio_set - set gpios according to mctrl state
* @gpios: gpios to set
* @mctrl: state to set
*
* Set the gpios according to the mctrl state.
*/
void mctrl_gpio_set(struct mctrl_gpios *gpios, unsigned int mctrl)
{
enum mctrl_gpio_idx i;
struct gpio_desc *desc_array[UART_GPIO_MAX];
DECLARE_BITMAP(values, UART_GPIO_MAX);
unsigned int count = 0;
if (gpios == NULL)
return;
for (i = 0; i < UART_GPIO_MAX; i++)
if (gpios->gpio[i] && mctrl_gpio_flags_is_dir_out(i)) {
desc_array[count] = gpios->gpio[i];
__assign_bit(count, values,
mctrl & mctrl_gpios_desc[i].mctrl);
count++;
}
gpiod_set_array_value(count, desc_array, NULL, values);
}
EXPORT_SYMBOL_GPL(mctrl_gpio_set);
/**
* mctrl_gpio_to_gpiod - obtain gpio_desc of modem line index
* @gpios: gpios to look into
* @gidx: index of the modem line
* Returns: the gpio_desc structure associated to the modem line index
*/
struct gpio_desc *mctrl_gpio_to_gpiod(struct mctrl_gpios *gpios,
enum mctrl_gpio_idx gidx)
{
if (gpios == NULL)
return NULL;
return gpios->gpio[gidx];
}
EXPORT_SYMBOL_GPL(mctrl_gpio_to_gpiod);
/**
* mctrl_gpio_get - update mctrl with the gpios values.
* @gpios: gpios to get the info from
* @mctrl: mctrl to set
* Returns: modified mctrl (the same value as in @mctrl)
*
* Update mctrl with the gpios values.
*/
unsigned int mctrl_gpio_get(struct mctrl_gpios *gpios, unsigned int *mctrl)
{
enum mctrl_gpio_idx i;
if (gpios == NULL)
return *mctrl;
for (i = 0; i < UART_GPIO_MAX; i++) {
if (gpios->gpio[i] && !mctrl_gpio_flags_is_dir_out(i)) {
if (gpiod_get_value(gpios->gpio[i]))
*mctrl |= mctrl_gpios_desc[i].mctrl;
else
*mctrl &= ~mctrl_gpios_desc[i].mctrl;
}
}
return *mctrl;
}
EXPORT_SYMBOL_GPL(mctrl_gpio_get);
unsigned int
mctrl_gpio_get_outputs(struct mctrl_gpios *gpios, unsigned int *mctrl)
{
enum mctrl_gpio_idx i;
if (gpios == NULL)
return *mctrl;
for (i = 0; i < UART_GPIO_MAX; i++) {
if (gpios->gpio[i] && mctrl_gpio_flags_is_dir_out(i)) {
if (gpiod_get_value(gpios->gpio[i]))
*mctrl |= mctrl_gpios_desc[i].mctrl;
else
*mctrl &= ~mctrl_gpios_desc[i].mctrl;
}
}
return *mctrl;
}
EXPORT_SYMBOL_GPL(mctrl_gpio_get_outputs);
struct mctrl_gpios *mctrl_gpio_init_noauto(struct device *dev, unsigned int idx)
{
struct mctrl_gpios *gpios;
enum mctrl_gpio_idx i;
gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
if (!gpios)
return ERR_PTR(-ENOMEM);
for (i = 0; i < UART_GPIO_MAX; i++) {
char *gpio_str;
bool present;
/* Check if GPIO property exists and continue if not */
gpio_str = kasprintf(GFP_KERNEL, "%s-gpios",
mctrl_gpios_desc[i].name);
if (!gpio_str)
continue;
present = device_property_present(dev, gpio_str);
kfree(gpio_str);
if (!present)
continue;
gpios->gpio[i] =
devm_gpiod_get_index_optional(dev,
mctrl_gpios_desc[i].name,
idx,
mctrl_gpios_desc[i].flags);
if (IS_ERR(gpios->gpio[i]))
return ERR_CAST(gpios->gpio[i]);
}
return gpios;
}
EXPORT_SYMBOL_GPL(mctrl_gpio_init_noauto);
#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
static irqreturn_t mctrl_gpio_irq_handle(int irq, void *context)
{
struct mctrl_gpios *gpios = context;
struct uart_port *port = gpios->port;
u32 mctrl = gpios->mctrl_prev;
u32 mctrl_diff;
unsigned long flags;
mctrl_gpio_get(gpios, &mctrl);
spin_lock_irqsave(&port->lock, flags);
mctrl_diff = mctrl ^ gpios->mctrl_prev;
gpios->mctrl_prev = mctrl;
if (mctrl_diff & MCTRL_ANY_DELTA && port->state != NULL) {
if ((mctrl_diff & mctrl) & TIOCM_RI)
port->icount.rng++;
if ((mctrl_diff & mctrl) & TIOCM_DSR)
port->icount.dsr++;
if (mctrl_diff & TIOCM_CD)
uart_handle_dcd_change(port, mctrl & TIOCM_CD);
if (mctrl_diff & TIOCM_CTS)
uart_handle_cts_change(port, mctrl & TIOCM_CTS);
wake_up_interruptible(&port->state->port.delta_msr_wait);
}
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
/**
* mctrl_gpio_init - initialize uart gpios
* @port: port to initialize gpios for
* @idx: index of the gpio in the @port's device
*
* This will get the {cts,rts,...}-gpios from device tree if they are present
* and request them, set direction etc, and return an allocated structure.
* `devm_*` functions are used, so there's no need to call mctrl_gpio_free().
* As this sets up the irq handling, make sure to not handle changes to the
* gpio input lines in your driver, too.
*/
struct mctrl_gpios *mctrl_gpio_init(struct uart_port *port, unsigned int idx)
{
struct mctrl_gpios *gpios;
enum mctrl_gpio_idx i;
gpios = mctrl_gpio_init_noauto(port->dev, idx);
if (IS_ERR(gpios))
return gpios;
gpios->port = port;
for (i = 0; i < UART_GPIO_MAX; ++i) {
int ret;
if (!gpios->gpio[i] || mctrl_gpio_flags_is_dir_out(i))
continue;
ret = gpiod_to_irq(gpios->gpio[i]);
if (ret < 0) {
dev_err(port->dev,
"failed to find corresponding irq for %s (idx=%d, err=%d)\n",
mctrl_gpios_desc[i].name, idx, ret);
return ERR_PTR(ret);
}
gpios->irq[i] = ret;
/* irqs should only be enabled in .enable_ms */
irq_set_status_flags(gpios->irq[i], IRQ_NOAUTOEN);
ret = devm_request_irq(port->dev, gpios->irq[i],
mctrl_gpio_irq_handle,
IRQ_TYPE_EDGE_BOTH, dev_name(port->dev),
gpios);
if (ret) {
/* alternatively implement polling */
dev_err(port->dev,
"failed to request irq for %s (idx=%d, err=%d)\n",
mctrl_gpios_desc[i].name, idx, ret);
return ERR_PTR(ret);
}
}
return gpios;
}
EXPORT_SYMBOL_GPL(mctrl_gpio_init);
/**
* mctrl_gpio_free - explicitly free uart gpios
* @dev: uart port's device
* @gpios: gpios structure to be freed
*
* This will free the requested gpios in mctrl_gpio_init(). As `devm_*`
* functions are used, there's generally no need to call this function.
*/
void mctrl_gpio_free(struct device *dev, struct mctrl_gpios *gpios)
{
enum mctrl_gpio_idx i;
if (gpios == NULL)
return;
for (i = 0; i < UART_GPIO_MAX; i++) {
if (gpios->irq[i])
devm_free_irq(gpios->port->dev, gpios->irq[i], gpios);
if (gpios->gpio[i])
devm_gpiod_put(dev, gpios->gpio[i]);
}
devm_kfree(dev, gpios);
}
EXPORT_SYMBOL_GPL(mctrl_gpio_free);
/**
* mctrl_gpio_enable_ms - enable irqs and handling of changes to the ms lines
* @gpios: gpios to enable
*/
void mctrl_gpio_enable_ms(struct mctrl_gpios *gpios)
{
enum mctrl_gpio_idx i;
if (gpios == NULL)
return;
/* .enable_ms may be called multiple times */
if (gpios->mctrl_on)
return;
gpios->mctrl_on = true;
/* get initial status of modem lines GPIOs */
mctrl_gpio_get(gpios, &gpios->mctrl_prev);
for (i = 0; i < UART_GPIO_MAX; ++i) {
if (!gpios->irq[i])
continue;
enable_irq(gpios->irq[i]);
}
}
EXPORT_SYMBOL_GPL(mctrl_gpio_enable_ms);
/**
* mctrl_gpio_disable_ms - disable irqs and handling of changes to the ms lines
* @gpios: gpios to disable
*/
void mctrl_gpio_disable_ms(struct mctrl_gpios *gpios)
{
enum mctrl_gpio_idx i;
if (gpios == NULL)
return;
if (!gpios->mctrl_on)
return;
gpios->mctrl_on = false;
for (i = 0; i < UART_GPIO_MAX; ++i) {
if (!gpios->irq[i])
continue;
disable_irq(gpios->irq[i]);
}
}
EXPORT_SYMBOL_GPL(mctrl_gpio_disable_ms);
void mctrl_gpio_enable_irq_wake(struct mctrl_gpios *gpios)
{
enum mctrl_gpio_idx i;
if (!gpios)
return;
if (!gpios->mctrl_on)
return;
for (i = 0; i < UART_GPIO_MAX; ++i) {
if (!gpios->irq[i])
continue;
enable_irq_wake(gpios->irq[i]);
}
}
EXPORT_SYMBOL_GPL(mctrl_gpio_enable_irq_wake);
void mctrl_gpio_disable_irq_wake(struct mctrl_gpios *gpios)
{
enum mctrl_gpio_idx i;
if (!gpios)
return;
if (!gpios->mctrl_on)
return;
for (i = 0; i < UART_GPIO_MAX; ++i) {
if (!gpios->irq[i])
continue;
disable_irq_wake(gpios->irq[i]);
}
}
EXPORT_SYMBOL_GPL(mctrl_gpio_disable_irq_wake);
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/serial_mctrl_gpio.c |
// SPDX-License-Identifier: GPL-2.0
/*
* dz.c: Serial port driver for DECstations equipped
* with the DZ chipset.
*
* Copyright (C) 1998 Olivier A. D. Lebaillif
*
* Email: [email protected]
*
* Copyright (C) 2004, 2006, 2007 Maciej W. Rozycki
*
* [31-AUG-98] triemer
* Changed IRQ to use Harald's dec internals interrupts.h
* removed base_addr code - moving address assignment to setup.c
* Changed name of dz_init to rs_init to be consistent with tc code
* [13-NOV-98] triemer fixed code to receive characters
* after patches by harald to irq code.
* [09-JAN-99] triemer minor fix for schedule - due to removal of timeout
* field from "current" - somewhere between 2.1.121 and 2.1.131
Qua Jun 27 15:02:26 BRT 2001
* [27-JUN-2001] Arnaldo Carvalho de Melo <[email protected]> - cleanups
*
* Parts (C) 1999 David Airlie, [email protected]
* [07-SEP-99] Bugfixes
*
* [06-Jan-2002] Russell King <[email protected]>
* Converted to new serial core
*/
#undef DEBUG_DZ
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/major.h>
#include <linux/module.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/sysrq.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/atomic.h>
#include <linux/io.h>
#include <asm/bootinfo.h>
#include <asm/dec/interrupts.h>
#include <asm/dec/kn01.h>
#include <asm/dec/kn02.h>
#include <asm/dec/machtype.h>
#include <asm/dec/prom.h>
#include <asm/dec/system.h>
#include "dz.h"
MODULE_DESCRIPTION("DECstation DZ serial driver");
MODULE_LICENSE("GPL");
static char dz_name[] __initdata = "DECstation DZ serial driver version ";
static char dz_version[] __initdata = "1.04";
struct dz_port {
struct dz_mux *mux;
struct uart_port port;
unsigned int cflag;
};
struct dz_mux {
struct dz_port dport[DZ_NB_PORT];
atomic_t map_guard;
atomic_t irq_guard;
int initialised;
};
static struct dz_mux dz_mux;
static inline struct dz_port *to_dport(struct uart_port *uport)
{
return container_of(uport, struct dz_port, port);
}
/*
* ------------------------------------------------------------
* dz_in () and dz_out ()
*
* These routines are used to access the registers of the DZ
* chip, hiding relocation differences between implementation.
* ------------------------------------------------------------
*/
static u16 dz_in(struct dz_port *dport, unsigned offset)
{
void __iomem *addr = dport->port.membase + offset;
return readw(addr);
}
static void dz_out(struct dz_port *dport, unsigned offset, u16 value)
{
void __iomem *addr = dport->port.membase + offset;
writew(value, addr);
}
/*
* ------------------------------------------------------------
* rs_stop () and rs_start ()
*
* These routines are called before setting or resetting
* tty->flow.stopped. They enable or disable transmitter interrupts,
* as necessary.
* ------------------------------------------------------------
*/
static void dz_stop_tx(struct uart_port *uport)
{
struct dz_port *dport = to_dport(uport);
u16 tmp, mask = 1 << dport->port.line;
tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
tmp &= ~mask; /* clear the TX flag */
dz_out(dport, DZ_TCR, tmp);
}
static void dz_start_tx(struct uart_port *uport)
{
struct dz_port *dport = to_dport(uport);
u16 tmp, mask = 1 << dport->port.line;
tmp = dz_in(dport, DZ_TCR); /* read the TX flag */
tmp |= mask; /* set the TX flag */
dz_out(dport, DZ_TCR, tmp);
}
static void dz_stop_rx(struct uart_port *uport)
{
struct dz_port *dport = to_dport(uport);
dport->cflag &= ~DZ_RXENAB;
dz_out(dport, DZ_LPR, dport->cflag);
}
/*
* ------------------------------------------------------------
*
* Here start the interrupt handling routines. All of the following
* subroutines are declared as inline and are folded into
* dz_interrupt. They were separated out for readability's sake.
*
* Note: dz_interrupt() is a "fast" interrupt, which means that it
* runs with interrupts turned off. People who may want to modify
* dz_interrupt() should try to keep the interrupt handler as fast as
* possible. After you are done making modifications, it is not a bad
* idea to do:
*
* make drivers/serial/dz.s
*
* and look at the resulting assemble code in dz.s.
*
* ------------------------------------------------------------
*/
/*
* ------------------------------------------------------------
* receive_char ()
*
* This routine deals with inputs from any lines.
* ------------------------------------------------------------
*/
static inline void dz_receive_chars(struct dz_mux *mux)
{
struct uart_port *uport;
struct dz_port *dport = &mux->dport[0];
struct uart_icount *icount;
int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 };
u16 status;
u8 ch, flag;
int i;
while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) {
dport = &mux->dport[LINE(status)];
uport = &dport->port;
ch = UCHAR(status); /* grab the char */
flag = TTY_NORMAL;
icount = &uport->icount;
icount->rx++;
if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) {
/*
* There is no separate BREAK status bit, so treat
* null characters with framing errors as BREAKs;
* normally, otherwise. For this move the Framing
* Error bit to a simulated BREAK bit.
*/
if (!ch) {
status |= (status & DZ_FERR) >>
(ffs(DZ_FERR) - ffs(DZ_BREAK));
status &= ~DZ_FERR;
}
/* Handle SysRq/SAK & keep track of the statistics. */
if (status & DZ_BREAK) {
icount->brk++;
if (uart_handle_break(uport))
continue;
} else if (status & DZ_FERR)
icount->frame++;
else if (status & DZ_PERR)
icount->parity++;
if (status & DZ_OERR)
icount->overrun++;
status &= uport->read_status_mask;
if (status & DZ_BREAK)
flag = TTY_BREAK;
else if (status & DZ_FERR)
flag = TTY_FRAME;
else if (status & DZ_PERR)
flag = TTY_PARITY;
}
if (uart_handle_sysrq_char(uport, ch))
continue;
uart_insert_char(uport, status, DZ_OERR, ch, flag);
lines_rx[LINE(status)] = 1;
}
for (i = 0; i < DZ_NB_PORT; i++)
if (lines_rx[i])
tty_flip_buffer_push(&mux->dport[i].port.state->port);
}
/*
* ------------------------------------------------------------
* transmit_char ()
*
* This routine deals with outputs to any lines.
* ------------------------------------------------------------
*/
static inline void dz_transmit_chars(struct dz_mux *mux)
{
struct dz_port *dport = &mux->dport[0];
struct circ_buf *xmit;
unsigned char tmp;
u16 status;
status = dz_in(dport, DZ_CSR);
dport = &mux->dport[LINE(status)];
xmit = &dport->port.state->xmit;
if (dport->port.x_char) { /* XON/XOFF chars */
dz_out(dport, DZ_TDR, dport->port.x_char);
dport->port.icount.tx++;
dport->port.x_char = 0;
return;
}
/* If nothing to do or stopped or hardware stopped. */
if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
spin_lock(&dport->port.lock);
dz_stop_tx(&dport->port);
spin_unlock(&dport->port.lock);
return;
}
/*
* If something to do... (remember the dz has no output fifo,
* so we go one char at a time) :-<
*/
tmp = xmit->buf[xmit->tail];
dz_out(dport, DZ_TDR, tmp);
uart_xmit_advance(&dport->port, 1);
if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS)
uart_write_wakeup(&dport->port);
/* Are we are done. */
if (uart_circ_empty(xmit)) {
spin_lock(&dport->port.lock);
dz_stop_tx(&dport->port);
spin_unlock(&dport->port.lock);
}
}
/*
* ------------------------------------------------------------
* check_modem_status()
*
* DS 3100 & 5100: Only valid for the MODEM line, duh!
* DS 5000/200: Valid for the MODEM and PRINTER line.
* ------------------------------------------------------------
*/
static inline void check_modem_status(struct dz_port *dport)
{
/*
* FIXME:
* 1. No status change interrupt; use a timer.
* 2. Handle the 3100/5000 as appropriate. --macro
*/
u16 status;
/* If not the modem line just return. */
if (dport->port.line != DZ_MODEM)
return;
status = dz_in(dport, DZ_MSR);
/* it's easy, since DSR2 is the only bit in the register */
if (status)
dport->port.icount.dsr++;
}
/*
* ------------------------------------------------------------
* dz_interrupt ()
*
* this is the main interrupt routine for the DZ chip.
* It deals with the multiple ports.
* ------------------------------------------------------------
*/
static irqreturn_t dz_interrupt(int irq, void *dev_id)
{
struct dz_mux *mux = dev_id;
struct dz_port *dport = &mux->dport[0];
u16 status;
/* get the reason why we just got an irq */
status = dz_in(dport, DZ_CSR);
if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE))
dz_receive_chars(mux);
if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE))
dz_transmit_chars(mux);
return IRQ_HANDLED;
}
/*
* -------------------------------------------------------------------
* Here ends the DZ interrupt routines.
* -------------------------------------------------------------------
*/
static unsigned int dz_get_mctrl(struct uart_port *uport)
{
/*
* FIXME: Handle the 3100/5000 as appropriate. --macro
*/
struct dz_port *dport = to_dport(uport);
unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
if (dport->port.line == DZ_MODEM) {
if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR)
mctrl &= ~TIOCM_DSR;
}
return mctrl;
}
static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl)
{
/*
* FIXME: Handle the 3100/5000 as appropriate. --macro
*/
struct dz_port *dport = to_dport(uport);
u16 tmp;
if (dport->port.line == DZ_MODEM) {
tmp = dz_in(dport, DZ_TCR);
if (mctrl & TIOCM_DTR)
tmp &= ~DZ_MODEM_DTR;
else
tmp |= DZ_MODEM_DTR;
dz_out(dport, DZ_TCR, tmp);
}
}
/*
* -------------------------------------------------------------------
* startup ()
*
* various initialization tasks
* -------------------------------------------------------------------
*/
static int dz_startup(struct uart_port *uport)
{
struct dz_port *dport = to_dport(uport);
struct dz_mux *mux = dport->mux;
unsigned long flags;
int irq_guard;
int ret;
u16 tmp;
irq_guard = atomic_add_return(1, &mux->irq_guard);
if (irq_guard != 1)
return 0;
ret = request_irq(dport->port.irq, dz_interrupt,
IRQF_SHARED, "dz", mux);
if (ret) {
atomic_add(-1, &mux->irq_guard);
printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq);
return ret;
}
spin_lock_irqsave(&dport->port.lock, flags);
/* Enable interrupts. */
tmp = dz_in(dport, DZ_CSR);
tmp |= DZ_RIE | DZ_TIE;
dz_out(dport, DZ_CSR, tmp);
spin_unlock_irqrestore(&dport->port.lock, flags);
return 0;
}
/*
* -------------------------------------------------------------------
* shutdown ()
*
* This routine will shutdown a serial port; interrupts are disabled, and
* DTR is dropped if the hangup on close termio flag is on.
* -------------------------------------------------------------------
*/
static void dz_shutdown(struct uart_port *uport)
{
struct dz_port *dport = to_dport(uport);
struct dz_mux *mux = dport->mux;
unsigned long flags;
int irq_guard;
u16 tmp;
spin_lock_irqsave(&dport->port.lock, flags);
dz_stop_tx(&dport->port);
spin_unlock_irqrestore(&dport->port.lock, flags);
irq_guard = atomic_add_return(-1, &mux->irq_guard);
if (!irq_guard) {
/* Disable interrupts. */
tmp = dz_in(dport, DZ_CSR);
tmp &= ~(DZ_RIE | DZ_TIE);
dz_out(dport, DZ_CSR, tmp);
free_irq(dport->port.irq, mux);
}
}
/*
* -------------------------------------------------------------------
* dz_tx_empty() -- get the transmitter empty status
*
* Purpose: Let user call ioctl() to get info when the UART physically
* is emptied. On bus types like RS485, the transmitter must
* release the bus after transmitting. This must be done when
* the transmit shift register is empty, not be done when the
* transmit holding register is empty. This functionality
* allows an RS485 driver to be written in user space.
* -------------------------------------------------------------------
*/
static unsigned int dz_tx_empty(struct uart_port *uport)
{
struct dz_port *dport = to_dport(uport);
unsigned short tmp, mask = 1 << dport->port.line;
tmp = dz_in(dport, DZ_TCR);
tmp &= mask;
return tmp ? 0 : TIOCSER_TEMT;
}
static void dz_break_ctl(struct uart_port *uport, int break_state)
{
/*
* FIXME: Can't access BREAK bits in TDR easily;
* reuse the code for polled TX. --macro
*/
struct dz_port *dport = to_dport(uport);
unsigned long flags;
unsigned short tmp, mask = 1 << dport->port.line;
spin_lock_irqsave(&uport->lock, flags);
tmp = dz_in(dport, DZ_TCR);
if (break_state)
tmp |= mask;
else
tmp &= ~mask;
dz_out(dport, DZ_TCR, tmp);
spin_unlock_irqrestore(&uport->lock, flags);
}
static int dz_encode_baud_rate(unsigned int baud)
{
switch (baud) {
case 50:
return DZ_B50;
case 75:
return DZ_B75;
case 110:
return DZ_B110;
case 134:
return DZ_B134;
case 150:
return DZ_B150;
case 300:
return DZ_B300;
case 600:
return DZ_B600;
case 1200:
return DZ_B1200;
case 1800:
return DZ_B1800;
case 2000:
return DZ_B2000;
case 2400:
return DZ_B2400;
case 3600:
return DZ_B3600;
case 4800:
return DZ_B4800;
case 7200:
return DZ_B7200;
case 9600:
return DZ_B9600;
default:
return -1;
}
}
static void dz_reset(struct dz_port *dport)
{
struct dz_mux *mux = dport->mux;
if (mux->initialised)
return;
dz_out(dport, DZ_CSR, DZ_CLR);
while (dz_in(dport, DZ_CSR) & DZ_CLR);
iob();
/* Enable scanning. */
dz_out(dport, DZ_CSR, DZ_MSE);
mux->initialised = 1;
}
static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
const struct ktermios *old_termios)
{
struct dz_port *dport = to_dport(uport);
unsigned long flags;
unsigned int cflag, baud;
int bflag;
cflag = dport->port.line;
switch (termios->c_cflag & CSIZE) {
case CS5:
cflag |= DZ_CS5;
break;
case CS6:
cflag |= DZ_CS6;
break;
case CS7:
cflag |= DZ_CS7;
break;
case CS8:
default:
cflag |= DZ_CS8;
}
if (termios->c_cflag & CSTOPB)
cflag |= DZ_CSTOPB;
if (termios->c_cflag & PARENB)
cflag |= DZ_PARENB;
if (termios->c_cflag & PARODD)
cflag |= DZ_PARODD;
baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600);
bflag = dz_encode_baud_rate(baud);
if (bflag < 0) {
if (old_termios) {
/* Keep unchanged. */
baud = tty_termios_baud_rate(old_termios);
bflag = dz_encode_baud_rate(baud);
}
if (bflag < 0) { /* Resort to 9600. */
baud = 9600;
bflag = DZ_B9600;
}
tty_termios_encode_baud_rate(termios, baud, baud);
}
cflag |= bflag;
if (termios->c_cflag & CREAD)
cflag |= DZ_RXENAB;
spin_lock_irqsave(&dport->port.lock, flags);
uart_update_timeout(uport, termios->c_cflag, baud);
dz_out(dport, DZ_LPR, cflag);
dport->cflag = cflag;
/* setup accept flag */
dport->port.read_status_mask = DZ_OERR;
if (termios->c_iflag & INPCK)
dport->port.read_status_mask |= DZ_FERR | DZ_PERR;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
dport->port.read_status_mask |= DZ_BREAK;
/* characters to ignore */
uport->ignore_status_mask = 0;
if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
dport->port.ignore_status_mask |= DZ_OERR;
if (termios->c_iflag & IGNPAR)
dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR;
if (termios->c_iflag & IGNBRK)
dport->port.ignore_status_mask |= DZ_BREAK;
spin_unlock_irqrestore(&dport->port.lock, flags);
}
/*
* Hack alert!
* Required solely so that the initial PROM-based console
* works undisturbed in parallel with this one.
*/
static void dz_pm(struct uart_port *uport, unsigned int state,
unsigned int oldstate)
{
struct dz_port *dport = to_dport(uport);
unsigned long flags;
spin_lock_irqsave(&dport->port.lock, flags);
if (state < 3)
dz_start_tx(&dport->port);
else
dz_stop_tx(&dport->port);
spin_unlock_irqrestore(&dport->port.lock, flags);
}
static const char *dz_type(struct uart_port *uport)
{
return "DZ";
}
static void dz_release_port(struct uart_port *uport)
{
struct dz_mux *mux = to_dport(uport)->mux;
int map_guard;
iounmap(uport->membase);
uport->membase = NULL;
map_guard = atomic_add_return(-1, &mux->map_guard);
if (!map_guard)
release_mem_region(uport->mapbase, dec_kn_slot_size);
}
static int dz_map_port(struct uart_port *uport)
{
if (!uport->membase)
uport->membase = ioremap(uport->mapbase,
dec_kn_slot_size);
if (!uport->membase) {
printk(KERN_ERR "dz: Cannot map MMIO\n");
return -ENOMEM;
}
return 0;
}
static int dz_request_port(struct uart_port *uport)
{
struct dz_mux *mux = to_dport(uport)->mux;
int map_guard;
int ret;
map_guard = atomic_add_return(1, &mux->map_guard);
if (map_guard == 1) {
if (!request_mem_region(uport->mapbase, dec_kn_slot_size,
"dz")) {
atomic_add(-1, &mux->map_guard);
printk(KERN_ERR
"dz: Unable to reserve MMIO resource\n");
return -EBUSY;
}
}
ret = dz_map_port(uport);
if (ret) {
map_guard = atomic_add_return(-1, &mux->map_guard);
if (!map_guard)
release_mem_region(uport->mapbase, dec_kn_slot_size);
return ret;
}
return 0;
}
static void dz_config_port(struct uart_port *uport, int flags)
{
struct dz_port *dport = to_dport(uport);
if (flags & UART_CONFIG_TYPE) {
if (dz_request_port(uport))
return;
uport->type = PORT_DZ;
dz_reset(dport);
}
}
/*
* Verify the new serial_struct (for TIOCSSERIAL).
*/
static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ)
ret = -EINVAL;
if (ser->irq != uport->irq)
ret = -EINVAL;
return ret;
}
static const struct uart_ops dz_ops = {
.tx_empty = dz_tx_empty,
.get_mctrl = dz_get_mctrl,
.set_mctrl = dz_set_mctrl,
.stop_tx = dz_stop_tx,
.start_tx = dz_start_tx,
.stop_rx = dz_stop_rx,
.break_ctl = dz_break_ctl,
.startup = dz_startup,
.shutdown = dz_shutdown,
.set_termios = dz_set_termios,
.pm = dz_pm,
.type = dz_type,
.release_port = dz_release_port,
.request_port = dz_request_port,
.config_port = dz_config_port,
.verify_port = dz_verify_port,
};
static void __init dz_init_ports(void)
{
static int first = 1;
unsigned long base;
int line;
if (!first)
return;
first = 0;
if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100)
base = dec_kn_slot_base + KN01_DZ11;
else
base = dec_kn_slot_base + KN02_DZ11;
for (line = 0; line < DZ_NB_PORT; line++) {
struct dz_port *dport = &dz_mux.dport[line];
struct uart_port *uport = &dport->port;
dport->mux = &dz_mux;
uport->irq = dec_interrupt[DEC_IRQ_DZ11];
uport->fifosize = 1;
uport->iotype = UPIO_MEM;
uport->flags = UPF_BOOT_AUTOCONF;
uport->ops = &dz_ops;
uport->line = line;
uport->mapbase = base;
uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_DZ_CONSOLE);
}
}
#ifdef CONFIG_SERIAL_DZ_CONSOLE
/*
* -------------------------------------------------------------------
* dz_console_putchar() -- transmit a character
*
* Polled transmission. This is tricky. We need to mask transmit
* interrupts so that they do not interfere, enable the transmitter
* for the line requested and then wait till the transmit scanner
* requests data for this line. But it may request data for another
* line first, in which case we have to disable its transmitter and
* repeat waiting till our line pops up. Only then the character may
* be transmitted. Finally, the state of the transmitter mask is
* restored. Welcome to the world of PDP-11!
* -------------------------------------------------------------------
*/
static void dz_console_putchar(struct uart_port *uport, unsigned char ch)
{
struct dz_port *dport = to_dport(uport);
unsigned long flags;
unsigned short csr, tcr, trdy, mask;
int loops = 10000;
spin_lock_irqsave(&dport->port.lock, flags);
csr = dz_in(dport, DZ_CSR);
dz_out(dport, DZ_CSR, csr & ~DZ_TIE);
tcr = dz_in(dport, DZ_TCR);
tcr |= 1 << dport->port.line;
mask = tcr;
dz_out(dport, DZ_TCR, mask);
iob();
spin_unlock_irqrestore(&dport->port.lock, flags);
do {
trdy = dz_in(dport, DZ_CSR);
if (!(trdy & DZ_TRDY))
continue;
trdy = (trdy & DZ_TLINE) >> 8;
if (trdy == dport->port.line)
break;
mask &= ~(1 << trdy);
dz_out(dport, DZ_TCR, mask);
iob();
udelay(2);
} while (--loops);
if (loops) /* Cannot send otherwise. */
dz_out(dport, DZ_TDR, ch);
dz_out(dport, DZ_TCR, tcr);
dz_out(dport, DZ_CSR, csr);
}
/*
* -------------------------------------------------------------------
* dz_console_print ()
*
* dz_console_print is registered for printk.
* The console must be locked when we get here.
* -------------------------------------------------------------------
*/
static void dz_console_print(struct console *co,
const char *str,
unsigned int count)
{
struct dz_port *dport = &dz_mux.dport[co->index];
#ifdef DEBUG_DZ
prom_printf((char *) str);
#endif
uart_console_write(&dport->port, str, count, dz_console_putchar);
}
static int __init dz_console_setup(struct console *co, char *options)
{
struct dz_port *dport = &dz_mux.dport[co->index];
struct uart_port *uport = &dport->port;
int baud = 9600;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
ret = dz_map_port(uport);
if (ret)
return ret;
spin_lock_init(&dport->port.lock); /* For dz_pm(). */
dz_reset(dport);
dz_pm(uport, 0, -1);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(&dport->port, co, baud, parity, bits, flow);
}
static struct uart_driver dz_reg;
static struct console dz_console = {
.name = "ttyS",
.write = dz_console_print,
.device = uart_console_device,
.setup = dz_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &dz_reg,
};
static int __init dz_serial_console_init(void)
{
if (!IOASIC) {
dz_init_ports();
register_console(&dz_console);
return 0;
} else
return -ENXIO;
}
console_initcall(dz_serial_console_init);
#define SERIAL_DZ_CONSOLE &dz_console
#else
#define SERIAL_DZ_CONSOLE NULL
#endif /* CONFIG_SERIAL_DZ_CONSOLE */
static struct uart_driver dz_reg = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
.nr = DZ_NB_PORT,
.cons = SERIAL_DZ_CONSOLE,
};
static int __init dz_init(void)
{
int ret, i;
if (IOASIC)
return -ENXIO;
printk("%s%s\n", dz_name, dz_version);
dz_init_ports();
ret = uart_register_driver(&dz_reg);
if (ret)
return ret;
for (i = 0; i < DZ_NB_PORT; i++)
uart_add_one_port(&dz_reg, &dz_mux.dport[i].port);
return 0;
}
module_init(dz_init);
| linux-master | drivers/tty/serial/dz.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* SiFive UART driver
* Copyright (C) 2018 Paul Walmsley <[email protected]>
* Copyright (C) 2018-2019 SiFive
*
* Based partially on:
* - drivers/tty/serial/pxa.c
* - drivers/tty/serial/amba-pl011.c
* - drivers/tty/serial/uartlite.c
* - drivers/tty/serial/omap-serial.c
* - drivers/pwm/pwm-sifive.c
*
* See the following sources for further documentation:
* - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
* SiFive FE310-G000 v2p3
* - The tree/master/src/main/scala/devices/uart directory of
* https://github.com/sifive/sifive-blocks/
*
* The SiFive UART design is not 8250-compatible. The following common
* features are not supported:
* - Word lengths other than 8 bits
* - Break handling
* - Parity
* - Flow control
* - Modem signals (DSR, RI, etc.)
* On the other hand, the design is free from the baggage of the 8250
* programming model.
*/
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
/*
* Register offsets
*/
/* TXDATA */
#define SIFIVE_SERIAL_TXDATA_OFFS 0x0
#define SIFIVE_SERIAL_TXDATA_FULL_SHIFT 31
#define SIFIVE_SERIAL_TXDATA_FULL_MASK (1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT)
#define SIFIVE_SERIAL_TXDATA_DATA_SHIFT 0
#define SIFIVE_SERIAL_TXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT)
/* RXDATA */
#define SIFIVE_SERIAL_RXDATA_OFFS 0x4
#define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT 31
#define SIFIVE_SERIAL_RXDATA_EMPTY_MASK (1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT)
#define SIFIVE_SERIAL_RXDATA_DATA_SHIFT 0
#define SIFIVE_SERIAL_RXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT)
/* TXCTRL */
#define SIFIVE_SERIAL_TXCTRL_OFFS 0x8
#define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT 16
#define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
#define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT 1
#define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK (1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT)
#define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT 0
#define SIFIVE_SERIAL_TXCTRL_TXEN_MASK (1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT)
/* RXCTRL */
#define SIFIVE_SERIAL_RXCTRL_OFFS 0xC
#define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT 16
#define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
#define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT 0
#define SIFIVE_SERIAL_RXCTRL_RXEN_MASK (1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT)
/* IE */
#define SIFIVE_SERIAL_IE_OFFS 0x10
#define SIFIVE_SERIAL_IE_RXWM_SHIFT 1
#define SIFIVE_SERIAL_IE_RXWM_MASK (1 << SIFIVE_SERIAL_IE_RXWM_SHIFT)
#define SIFIVE_SERIAL_IE_TXWM_SHIFT 0
#define SIFIVE_SERIAL_IE_TXWM_MASK (1 << SIFIVE_SERIAL_IE_TXWM_SHIFT)
/* IP */
#define SIFIVE_SERIAL_IP_OFFS 0x14
#define SIFIVE_SERIAL_IP_RXWM_SHIFT 1
#define SIFIVE_SERIAL_IP_RXWM_MASK (1 << SIFIVE_SERIAL_IP_RXWM_SHIFT)
#define SIFIVE_SERIAL_IP_TXWM_SHIFT 0
#define SIFIVE_SERIAL_IP_TXWM_MASK (1 << SIFIVE_SERIAL_IP_TXWM_SHIFT)
/* DIV */
#define SIFIVE_SERIAL_DIV_OFFS 0x18
#define SIFIVE_SERIAL_DIV_DIV_SHIFT 0
#define SIFIVE_SERIAL_DIV_DIV_MASK (0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT)
/*
* Config macros
*/
/*
* SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can
* host a serial console
*/
#define SIFIVE_SERIAL_MAX_PORTS 8
/*
* SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should
* configure itself to use
*/
#define SIFIVE_DEFAULT_BAUD_RATE 115200
/* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */
#define SIFIVE_SERIAL_NAME "sifive-serial"
/* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
#define SIFIVE_TTY_PREFIX "ttySIF"
/* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
#define SIFIVE_TX_FIFO_DEPTH 8
/* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
#define SIFIVE_RX_FIFO_DEPTH 8
#if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH)
#error Driver does not support configurations with different TX, RX FIFO sizes
#endif
/*
*
*/
/**
* struct sifive_serial_port - driver-specific data extension to struct uart_port
* @port: struct uart_port embedded in this struct
* @dev: struct device *
* @ier: shadowed copy of the interrupt enable register
* @baud_rate: UART serial line rate (e.g., 115200 baud)
* @clk: reference to this device's clock
* @clk_notifier: clock rate change notifier for upstream clock changes
*
* Configuration data specific to this SiFive UART.
*/
struct sifive_serial_port {
struct uart_port port;
struct device *dev;
unsigned char ier;
unsigned long baud_rate;
struct clk *clk;
struct notifier_block clk_notifier;
};
/*
* Structure container-of macros
*/
#define port_to_sifive_serial_port(p) (container_of((p), \
struct sifive_serial_port, \
port))
#define notifier_to_sifive_serial_port(nb) (container_of((nb), \
struct sifive_serial_port, \
clk_notifier))
/*
* Forward declarations
*/
static void sifive_serial_stop_tx(struct uart_port *port);
/*
* Internal functions
*/
/**
* __ssp_early_writel() - write to a SiFive serial port register (early)
* @port: pointer to a struct uart_port record
* @offs: register address offset from the IP block base address
* @v: value to write to the register
*
* Given a pointer @port to a struct uart_port record, write the value
* @v to the IP block register address offset @offs. This function is
* intended for early console use.
*
* Context: Intended to be used only by the earlyconsole code.
*/
static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
{
writel_relaxed(v, port->membase + offs);
}
/**
* __ssp_early_readl() - read from a SiFive serial port register (early)
* @port: pointer to a struct uart_port record
* @offs: register address offset from the IP block base address
*
* Given a pointer @port to a struct uart_port record, read the
* contents of the IP block register located at offset @offs from the
* IP block base and return it. This function is intended for early
* console use.
*
* Context: Intended to be called only by the earlyconsole code or by
* __ssp_readl() or __ssp_writel() (in this driver)
*
* Returns: the register value read from the UART.
*/
static u32 __ssp_early_readl(struct uart_port *port, u16 offs)
{
return readl_relaxed(port->membase + offs);
}
/**
* __ssp_writel() - write to a SiFive serial port register
* @v: value to write to the register
* @offs: register address offset from the IP block base address
* @ssp: pointer to a struct sifive_serial_port record
*
* Write the value @v to the IP block register located at offset @offs from the
* IP block base, given a pointer @ssp to a struct sifive_serial_port record.
*
* Context: Any context.
*/
static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
{
__ssp_early_writel(v, offs, &ssp->port);
}
/**
* __ssp_readl() - read from a SiFive serial port register
* @ssp: pointer to a struct sifive_serial_port record
* @offs: register address offset from the IP block base address
*
* Read the contents of the IP block register located at offset @offs from the
* IP block base, given a pointer @ssp to a struct sifive_serial_port record.
*
* Context: Any context.
*
* Returns: the value of the UART register
*/
static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
{
return __ssp_early_readl(&ssp->port, offs);
}
/**
* sifive_serial_is_txfifo_full() - is the TXFIFO full?
* @ssp: pointer to a struct sifive_serial_port
*
* Read the transmit FIFO "full" bit, returning a non-zero value if the
* TX FIFO is full, or zero if space remains. Intended to be used to prevent
* writes to the TX FIFO when it's full.
*
* Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
* is full, or 0 if space remains.
*/
static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
{
return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
SIFIVE_SERIAL_TXDATA_FULL_MASK;
}
/**
* __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
* @ssp: pointer to a struct sifive_serial_port
* @ch: character to transmit
*
* Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
* struct sifive_serial_port * to transmit on. Caller should first check to
* ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full().
*
* Context: Any context.
*/
static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
{
__ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
}
/**
* __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
* @ssp: pointer to a struct sifive_serial_port
*
* Transfer up to a TX FIFO size's worth of characters from the Linux serial
* transmit buffer to the SiFive UART TX FIFO.
*
* Context: Any context. Expects @ssp->port.lock to be held by caller.
*/
static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
{
u8 ch;
uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH,
true,
__ssp_transmit_char(ssp, ch),
({}));
}
/**
* __ssp_enable_txwm() - enable transmit watermark interrupts
* @ssp: pointer to a struct sifive_serial_port
*
* Enable interrupt generation when the transmit FIFO watermark is reached
* on the SiFive UART referred to by @ssp.
*/
static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
{
if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
return;
ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
}
/**
* __ssp_enable_rxwm() - enable receive watermark interrupts
* @ssp: pointer to a struct sifive_serial_port
*
* Enable interrupt generation when the receive FIFO watermark is reached
* on the SiFive UART referred to by @ssp.
*/
static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
{
if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
return;
ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
}
/**
* __ssp_disable_txwm() - disable transmit watermark interrupts
* @ssp: pointer to a struct sifive_serial_port
*
* Disable interrupt generation when the transmit FIFO watermark is reached
* on the UART referred to by @ssp.
*/
static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
{
if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
return;
ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
}
/**
* __ssp_disable_rxwm() - disable receive watermark interrupts
* @ssp: pointer to a struct sifive_serial_port
*
* Disable interrupt generation when the receive FIFO watermark is reached
* on the UART referred to by @ssp.
*/
static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
{
if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
return;
ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
}
/**
* __ssp_receive_char() - receive a byte from the UART
* @ssp: pointer to a struct sifive_serial_port
* @is_empty: char pointer to return whether the RX FIFO is empty
*
* Try to read a byte from the SiFive UART RX FIFO, referenced by
* @ssp, and to return it. Also returns the RX FIFO empty bit in
* the char pointed to by @ch. The caller must pass the byte back to the
* Linux serial layer if needed.
*
* Returns: the byte read from the UART RX FIFO.
*/
static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
{
u32 v;
u8 ch;
v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
if (!is_empty)
WARN_ON(1);
else
*is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT;
ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
SIFIVE_SERIAL_RXDATA_DATA_SHIFT;
return ch;
}
/**
* __ssp_receive_chars() - receive multiple bytes from the UART
* @ssp: pointer to a struct sifive_serial_port
*
* Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
* to by @ssp and pass them up to the Linux serial layer.
*
* Context: Expects ssp->port.lock to be held by caller.
*/
static void __ssp_receive_chars(struct sifive_serial_port *ssp)
{
char is_empty;
int c;
u8 ch;
for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
ch = __ssp_receive_char(ssp, &is_empty);
if (is_empty)
break;
ssp->port.icount.rx++;
uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
}
tty_flip_buffer_push(&ssp->port.state->port);
}
/**
* __ssp_update_div() - calculate the divisor setting by the line rate
* @ssp: pointer to a struct sifive_serial_port
*
* Calculate the appropriate value of the clock divisor for the UART
* and target line rate referred to by @ssp and write it into the
* hardware.
*/
static void __ssp_update_div(struct sifive_serial_port *ssp)
{
u16 div;
div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
__ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
}
/**
* __ssp_update_baud_rate() - set the UART "baud rate"
* @ssp: pointer to a struct sifive_serial_port
* @rate: new target bit rate
*
* Calculate the UART divisor value for the target bit rate @rate for the
* SiFive UART described by @ssp and program it into the UART. There may
* be some error between the target bit rate and the actual bit rate implemented
* by the UART due to clock ratio granularity.
*/
static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
unsigned int rate)
{
if (ssp->baud_rate == rate)
return;
ssp->baud_rate = rate;
__ssp_update_div(ssp);
}
/**
* __ssp_set_stop_bits() - set the number of stop bits
* @ssp: pointer to a struct sifive_serial_port
* @nstop: 1 or 2 (stop bits)
*
* Program the SiFive UART referred to by @ssp to use @nstop stop bits.
*/
static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
{
u32 v;
if (nstop < 1 || nstop > 2) {
WARN_ON(1);
return;
}
v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
__ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
}
/**
* __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
* @ssp: pointer to a struct sifive_serial_port
*
* Delay while the UART TX FIFO referred to by @ssp is marked as full.
*
* Context: Any context.
*/
static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
{
while (sifive_serial_is_txfifo_full(ssp))
udelay(1); /* XXX Could probably be more intelligent here */
}
/*
* Linux serial API functions
*/
static void sifive_serial_stop_tx(struct uart_port *port)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_disable_txwm(ssp);
}
static void sifive_serial_stop_rx(struct uart_port *port)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_disable_rxwm(ssp);
}
static void sifive_serial_start_tx(struct uart_port *port)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_enable_txwm(ssp);
}
static irqreturn_t sifive_serial_irq(int irq, void *dev_id)
{
struct sifive_serial_port *ssp = dev_id;
u32 ip;
spin_lock(&ssp->port.lock);
ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
if (!ip) {
spin_unlock(&ssp->port.lock);
return IRQ_NONE;
}
if (ip & SIFIVE_SERIAL_IP_RXWM_MASK)
__ssp_receive_chars(ssp);
if (ip & SIFIVE_SERIAL_IP_TXWM_MASK)
__ssp_transmit_chars(ssp);
spin_unlock(&ssp->port.lock);
return IRQ_HANDLED;
}
static unsigned int sifive_serial_tx_empty(struct uart_port *port)
{
return TIOCSER_TEMT;
}
static unsigned int sifive_serial_get_mctrl(struct uart_port *port)
{
return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
}
static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
/* IP block does not support these signals */
}
static void sifive_serial_break_ctl(struct uart_port *port, int break_state)
{
/* IP block does not support sending a break */
}
static int sifive_serial_startup(struct uart_port *port)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_enable_rxwm(ssp);
return 0;
}
static void sifive_serial_shutdown(struct uart_port *port)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_disable_rxwm(ssp);
__ssp_disable_txwm(ssp);
}
/**
* sifive_serial_clk_notifier() - clock post-rate-change notifier
* @nb: pointer to the struct notifier_block, from the notifier code
* @event: event mask from the notifier code
* @data: pointer to the struct clk_notifier_data from the notifier code
*
* On the V0 SoC, the UART IP block is derived from the CPU clock source
* after a synchronous divide-by-two divider, so any CPU clock rate change
* requires the UART baud rate to be updated. This presumably corrupts any
* serial word currently being transmitted or received. In order to avoid
* corrupting the output data stream, we drain the transmit queue before
* allowing the clock's rate to be changed.
*/
static int sifive_serial_clk_notifier(struct notifier_block *nb,
unsigned long event, void *data)
{
struct clk_notifier_data *cnd = data;
struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
if (event == PRE_RATE_CHANGE) {
/*
* The TX watermark is always set to 1 by this driver, which
* means that the TX busy bit will lower when there are 0 bytes
* left in the TX queue -- in other words, when the TX FIFO is
* empty.
*/
__ssp_wait_for_xmitr(ssp);
/*
* On the cycle the TX FIFO goes empty there is still a full
* UART frame left to be transmitted in the shift register.
* The UART provides no way for software to directly determine
* when that last frame has been transmitted, so we just sleep
* here instead. As we're not tracking the number of stop bits
* they're just worst cased here. The rest of the serial
* framing parameters aren't configurable by software.
*/
udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
}
if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
ssp->port.uartclk = cnd->new_rate;
__ssp_update_div(ssp);
}
return NOTIFY_OK;
}
static void sifive_serial_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
unsigned long flags;
u32 v, old_v;
int rate;
char nstop;
if ((termios->c_cflag & CSIZE) != CS8) {
dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
termios->c_cflag &= ~CSIZE;
termios->c_cflag |= CS8;
}
if (termios->c_iflag & (INPCK | PARMRK))
dev_err_once(ssp->port.dev, "parity checking not supported\n");
if (termios->c_iflag & BRKINT)
dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);
/* Set number of stop bits */
nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
__ssp_set_stop_bits(ssp, nstop);
/* Set line rate */
rate = uart_get_baud_rate(port, termios, old, 0,
ssp->port.uartclk / 16);
__ssp_update_baud_rate(ssp, rate);
spin_lock_irqsave(&ssp->port.lock, flags);
/* Update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, rate);
ssp->port.read_status_mask = 0;
/* Ignore all characters if CREAD is not set */
v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
old_v = v;
if ((termios->c_cflag & CREAD) == 0)
v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
else
v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
if (v != old_v)
__ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
spin_unlock_irqrestore(&ssp->port.lock, flags);
}
static void sifive_serial_release_port(struct uart_port *port)
{
}
static int sifive_serial_request_port(struct uart_port *port)
{
return 0;
}
static void sifive_serial_config_port(struct uart_port *port, int flags)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
ssp->port.type = PORT_SIFIVE_V0;
}
static int sifive_serial_verify_port(struct uart_port *port,
struct serial_struct *ser)
{
return -EINVAL;
}
static const char *sifive_serial_type(struct uart_port *port)
{
return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;
}
#ifdef CONFIG_CONSOLE_POLL
static int sifive_serial_poll_get_char(struct uart_port *port)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
char is_empty, ch;
ch = __ssp_receive_char(ssp, &is_empty);
if (is_empty)
return NO_POLL_CHAR;
return ch;
}
static void sifive_serial_poll_put_char(struct uart_port *port,
unsigned char c)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_wait_for_xmitr(ssp);
__ssp_transmit_char(ssp, c);
}
#endif /* CONFIG_CONSOLE_POLL */
/*
* Early console support
*/
#ifdef CONFIG_SERIAL_EARLYCON
static void early_sifive_serial_putc(struct uart_port *port, unsigned char c)
{
while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) &
SIFIVE_SERIAL_TXDATA_FULL_MASK)
cpu_relax();
__ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port);
}
static void early_sifive_serial_write(struct console *con, const char *s,
unsigned int n)
{
struct earlycon_device *dev = con->data;
struct uart_port *port = &dev->port;
uart_console_write(port, s, n, early_sifive_serial_putc);
}
static int __init early_sifive_serial_setup(struct earlycon_device *dev,
const char *options)
{
struct uart_port *port = &dev->port;
if (!port->membase)
return -ENODEV;
dev->con->write = early_sifive_serial_write;
return 0;
}
OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
early_sifive_serial_setup);
#endif /* CONFIG_SERIAL_EARLYCON */
/*
* Linux console interface
*/
#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS];
static void sifive_serial_console_putchar(struct uart_port *port, unsigned char ch)
{
struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
__ssp_wait_for_xmitr(ssp);
__ssp_transmit_char(ssp, ch);
}
static void sifive_serial_console_write(struct console *co, const char *s,
unsigned int count)
{
struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
unsigned long flags;
unsigned int ier;
int locked = 1;
if (!ssp)
return;
local_irq_save(flags);
if (ssp->port.sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock(&ssp->port.lock);
else
spin_lock(&ssp->port.lock);
ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
__ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);
__ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
if (locked)
spin_unlock(&ssp->port.lock);
local_irq_restore(flags);
}
static int sifive_serial_console_setup(struct console *co, char *options)
{
struct sifive_serial_port *ssp;
int baud = SIFIVE_DEFAULT_BAUD_RATE;
int bits = 8;
int parity = 'n';
int flow = 'n';
if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)
return -ENODEV;
ssp = sifive_serial_console_ports[co->index];
if (!ssp)
return -ENODEV;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
}
static struct uart_driver sifive_serial_uart_driver;
static struct console sifive_serial_console = {
.name = SIFIVE_TTY_PREFIX,
.write = sifive_serial_console_write,
.device = uart_console_device,
.setup = sifive_serial_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &sifive_serial_uart_driver,
};
static int __init sifive_console_init(void)
{
register_console(&sifive_serial_console);
return 0;
}
console_initcall(sifive_console_init);
static void __ssp_add_console_port(struct sifive_serial_port *ssp)
{
sifive_serial_console_ports[ssp->port.line] = ssp;
}
static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
{
sifive_serial_console_ports[ssp->port.line] = NULL;
}
#define SIFIVE_SERIAL_CONSOLE (&sifive_serial_console)
#else
#define SIFIVE_SERIAL_CONSOLE NULL
static void __ssp_add_console_port(struct sifive_serial_port *ssp)
{}
static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
{}
#endif
static const struct uart_ops sifive_serial_uops = {
.tx_empty = sifive_serial_tx_empty,
.set_mctrl = sifive_serial_set_mctrl,
.get_mctrl = sifive_serial_get_mctrl,
.stop_tx = sifive_serial_stop_tx,
.start_tx = sifive_serial_start_tx,
.stop_rx = sifive_serial_stop_rx,
.break_ctl = sifive_serial_break_ctl,
.startup = sifive_serial_startup,
.shutdown = sifive_serial_shutdown,
.set_termios = sifive_serial_set_termios,
.type = sifive_serial_type,
.release_port = sifive_serial_release_port,
.request_port = sifive_serial_request_port,
.config_port = sifive_serial_config_port,
.verify_port = sifive_serial_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = sifive_serial_poll_get_char,
.poll_put_char = sifive_serial_poll_put_char,
#endif
};
static struct uart_driver sifive_serial_uart_driver = {
.owner = THIS_MODULE,
.driver_name = SIFIVE_SERIAL_NAME,
.dev_name = SIFIVE_TTY_PREFIX,
.nr = SIFIVE_SERIAL_MAX_PORTS,
.cons = SIFIVE_SERIAL_CONSOLE,
};
static int sifive_serial_probe(struct platform_device *pdev)
{
struct sifive_serial_port *ssp;
struct resource *mem;
struct clk *clk;
void __iomem *base;
int irq, id, r;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -EPROBE_DEFER;
base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
if (IS_ERR(base))
return PTR_ERR(base);
clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "unable to find controller clock\n");
return PTR_ERR(clk);
}
id = of_alias_get_id(pdev->dev.of_node, "serial");
if (id < 0) {
dev_err(&pdev->dev, "missing aliases entry\n");
return id;
}
#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
if (id > SIFIVE_SERIAL_MAX_PORTS) {
dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
return -EINVAL;
}
#endif
ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
if (!ssp)
return -ENOMEM;
ssp->port.dev = &pdev->dev;
ssp->port.type = PORT_SIFIVE_V0;
ssp->port.iotype = UPIO_MEM;
ssp->port.irq = irq;
ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
ssp->port.ops = &sifive_serial_uops;
ssp->port.line = id;
ssp->port.mapbase = mem->start;
ssp->port.membase = base;
ssp->dev = &pdev->dev;
ssp->clk = clk;
ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
if (r) {
dev_err(&pdev->dev, "could not register clock notifier: %d\n",
r);
goto probe_out1;
}
/* Set up clock divider */
ssp->port.uartclk = clk_get_rate(ssp->clk);
ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
__ssp_update_div(ssp);
platform_set_drvdata(pdev, ssp);
/* Enable transmits and set the watermark level to 1 */
__ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) |
SIFIVE_SERIAL_TXCTRL_TXEN_MASK,
SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
/* Enable receives and set the watermark level to 0 */
__ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) |
SIFIVE_SERIAL_RXCTRL_RXEN_MASK,
SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
dev_name(&pdev->dev), ssp);
if (r) {
dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);
goto probe_out2;
}
__ssp_add_console_port(ssp);
r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
if (r != 0) {
dev_err(&pdev->dev, "could not add uart: %d\n", r);
goto probe_out3;
}
return 0;
probe_out3:
__ssp_remove_console_port(ssp);
free_irq(ssp->port.irq, ssp);
probe_out2:
clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
probe_out1:
return r;
}
static int sifive_serial_remove(struct platform_device *dev)
{
struct sifive_serial_port *ssp = platform_get_drvdata(dev);
__ssp_remove_console_port(ssp);
uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
free_irq(ssp->port.irq, ssp);
clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
return 0;
}
static int sifive_serial_suspend(struct device *dev)
{
struct sifive_serial_port *ssp = dev_get_drvdata(dev);
return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port);
}
static int sifive_serial_resume(struct device *dev)
{
struct sifive_serial_port *ssp = dev_get_drvdata(dev);
return uart_resume_port(&sifive_serial_uart_driver, &ssp->port);
}
DEFINE_SIMPLE_DEV_PM_OPS(sifive_uart_pm_ops, sifive_serial_suspend,
sifive_serial_resume);
static const struct of_device_id sifive_serial_of_match[] = {
{ .compatible = "sifive,fu540-c000-uart0" },
{ .compatible = "sifive,uart0" },
{},
};
MODULE_DEVICE_TABLE(of, sifive_serial_of_match);
static struct platform_driver sifive_serial_platform_driver = {
.probe = sifive_serial_probe,
.remove = sifive_serial_remove,
.driver = {
.name = SIFIVE_SERIAL_NAME,
.pm = pm_sleep_ptr(&sifive_uart_pm_ops),
.of_match_table = sifive_serial_of_match,
},
};
static int __init sifive_serial_init(void)
{
int r;
r = uart_register_driver(&sifive_serial_uart_driver);
if (r)
goto init_out1;
r = platform_driver_register(&sifive_serial_platform_driver);
if (r)
goto init_out2;
return 0;
init_out2:
uart_unregister_driver(&sifive_serial_uart_driver);
init_out1:
return r;
}
static void __exit sifive_serial_exit(void)
{
platform_driver_unregister(&sifive_serial_platform_driver);
uart_unregister_driver(&sifive_serial_uart_driver);
}
module_init(sifive_serial_init);
module_exit(sifive_serial_exit);
MODULE_DESCRIPTION("SiFive UART serial driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Paul Walmsley <[email protected]>");
| linux-master | drivers/tty/serial/sifive.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* PIC32 Integrated Serial Driver.
*
* Copyright (C) 2015 Microchip Technology, Inc.
*
* Authors:
* Sorin-Andrei Pistirica <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/console.h>
#include <linux/clk.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/delay.h>
#include <asm/mach-pic32/pic32.h>
/* UART name and device definitions */
#define PIC32_DEV_NAME "pic32-uart"
#define PIC32_MAX_UARTS 6
#define PIC32_SDEV_NAME "ttyPIC"
#define PIC32_UART_DFLT_BRATE 9600
#define PIC32_UART_TX_FIFO_DEPTH 8
#define PIC32_UART_RX_FIFO_DEPTH 8
#define PIC32_UART_MODE 0x00
#define PIC32_UART_STA 0x10
#define PIC32_UART_TX 0x20
#define PIC32_UART_RX 0x30
#define PIC32_UART_BRG 0x40
/* struct pic32_sport - pic32 serial port descriptor
* @port: uart port descriptor
* @idx: port index
* @irq_fault: virtual fault interrupt number
* @irq_fault_name: irq fault name
* @irq_rx: virtual rx interrupt number
* @irq_rx_name: irq rx name
* @irq_tx: virtual tx interrupt number
* @irq_tx_name: irq tx name
* @cts_gpiod: clear to send GPIO
* @dev: device descriptor
**/
struct pic32_sport {
struct uart_port port;
int idx;
int irq_fault;
const char *irq_fault_name;
int irq_rx;
const char *irq_rx_name;
int irq_tx;
const char *irq_tx_name;
bool enable_tx_irq;
struct gpio_desc *cts_gpiod;
struct clk *clk;
struct device *dev;
};
static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
{
return container_of(port, struct pic32_sport, port);
}
static inline void pic32_uart_writel(struct pic32_sport *sport,
u32 reg, u32 val)
{
__raw_writel(val, sport->port.membase + reg);
}
static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
{
return __raw_readl(sport->port.membase + reg);
}
/* pic32 uart mode register bits */
#define PIC32_UART_MODE_ON BIT(15)
#define PIC32_UART_MODE_FRZ BIT(14)
#define PIC32_UART_MODE_SIDL BIT(13)
#define PIC32_UART_MODE_IREN BIT(12)
#define PIC32_UART_MODE_RTSMD BIT(11)
#define PIC32_UART_MODE_RESV1 BIT(10)
#define PIC32_UART_MODE_UEN1 BIT(9)
#define PIC32_UART_MODE_UEN0 BIT(8)
#define PIC32_UART_MODE_WAKE BIT(7)
#define PIC32_UART_MODE_LPBK BIT(6)
#define PIC32_UART_MODE_ABAUD BIT(5)
#define PIC32_UART_MODE_RXINV BIT(4)
#define PIC32_UART_MODE_BRGH BIT(3)
#define PIC32_UART_MODE_PDSEL1 BIT(2)
#define PIC32_UART_MODE_PDSEL0 BIT(1)
#define PIC32_UART_MODE_STSEL BIT(0)
/* pic32 uart status register bits */
#define PIC32_UART_STA_UTXISEL1 BIT(15)
#define PIC32_UART_STA_UTXISEL0 BIT(14)
#define PIC32_UART_STA_UTXINV BIT(13)
#define PIC32_UART_STA_URXEN BIT(12)
#define PIC32_UART_STA_UTXBRK BIT(11)
#define PIC32_UART_STA_UTXEN BIT(10)
#define PIC32_UART_STA_UTXBF BIT(9)
#define PIC32_UART_STA_TRMT BIT(8)
#define PIC32_UART_STA_URXISEL1 BIT(7)
#define PIC32_UART_STA_URXISEL0 BIT(6)
#define PIC32_UART_STA_ADDEN BIT(5)
#define PIC32_UART_STA_RIDLE BIT(4)
#define PIC32_UART_STA_PERR BIT(3)
#define PIC32_UART_STA_FERR BIT(2)
#define PIC32_UART_STA_OERR BIT(1)
#define PIC32_UART_STA_URXDA BIT(0)
/* pic32_sport pointer for console use */
static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
{
/* wait for tx empty, otherwise chars will be lost or corrupted */
while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
udelay(1);
}
/* serial core request to check if uart tx buffer is empty */
static unsigned int pic32_uart_tx_empty(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
}
/* serial core request to set UART outputs */
static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct pic32_sport *sport = to_pic32_sport(port);
/* set loopback mode */
if (mctrl & TIOCM_LOOP)
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
PIC32_UART_MODE_LPBK);
else
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_LPBK);
}
/* serial core request to return the state of misc UART input pins */
static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
unsigned int mctrl = 0;
/* get the state of CTS input pin for this port */
if (!sport->cts_gpiod)
mctrl |= TIOCM_CTS;
else if (gpiod_get_value(sport->cts_gpiod))
mctrl |= TIOCM_CTS;
/* DSR and CD are not supported in PIC32, so return 1
* RI is not supported in PIC32, so return 0
*/
mctrl |= TIOCM_CD;
mctrl |= TIOCM_DSR;
return mctrl;
}
/* stop tx and start tx are not called in pairs, therefore a flag indicates
* the status of irq to control the irq-depth.
*/
static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
{
if (en && !sport->enable_tx_irq) {
enable_irq(sport->irq_tx);
sport->enable_tx_irq = true;
} else if (!en && sport->enable_tx_irq) {
/* use disable_irq_nosync() and not disable_irq() to avoid self
* imposed deadlock by not waiting for irq handler to end,
* since this callback is called from interrupt context.
*/
disable_irq_nosync(sport->irq_tx);
sport->enable_tx_irq = false;
}
}
/* serial core request to disable tx ASAP (used for flow control) */
static void pic32_uart_stop_tx(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
return;
if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
return;
/* wait for tx empty */
pic32_wait_deplete_txbuf(sport);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_UTXEN);
pic32_uart_irqtxen(sport, 0);
}
/* serial core request to (re)enable tx */
static void pic32_uart_start_tx(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
pic32_uart_irqtxen(sport, 1);
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
PIC32_UART_STA_UTXEN);
}
/* serial core request to stop rx, called before port shutdown */
static void pic32_uart_stop_rx(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
/* disable rx interrupts */
disable_irq(sport->irq_rx);
/* receiver Enable bit OFF */
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_URXEN);
}
/* serial core request to start/stop emitting break char */
static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
{
struct pic32_sport *sport = to_pic32_sport(port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
if (ctl)
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
PIC32_UART_STA_UTXBRK);
else
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_UTXBRK);
spin_unlock_irqrestore(&port->lock, flags);
}
/* get port type in string format */
static const char *pic32_uart_type(struct uart_port *port)
{
return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
}
/* read all chars in rx fifo and send them to core */
static void pic32_uart_do_rx(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
struct tty_port *tty;
unsigned int max_count;
/* limit number of char read in interrupt, should not be
* higher than fifo size anyway since we're much faster than
* serial port
*/
max_count = PIC32_UART_RX_FIFO_DEPTH;
spin_lock(&port->lock);
tty = &port->state->port;
do {
u32 sta_reg, c;
char flag;
/* get overrun/fifo empty information from status register */
sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
/* fifo reset is required to clear interrupt */
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_OERR);
port->icount.overrun++;
tty_insert_flip_char(tty, 0, TTY_OVERRUN);
}
/* Can at least one more character can be read? */
if (!(sta_reg & PIC32_UART_STA_URXDA))
break;
/* read the character and increment the rx counter */
c = pic32_uart_readl(sport, PIC32_UART_RX);
port->icount.rx++;
flag = TTY_NORMAL;
c &= 0xff;
if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
(sta_reg & PIC32_UART_STA_FERR))) {
/* do stats first */
if (sta_reg & PIC32_UART_STA_PERR)
port->icount.parity++;
if (sta_reg & PIC32_UART_STA_FERR)
port->icount.frame++;
/* update flag wrt read_status_mask */
sta_reg &= port->read_status_mask;
if (sta_reg & PIC32_UART_STA_FERR)
flag = TTY_FRAME;
if (sta_reg & PIC32_UART_STA_PERR)
flag = TTY_PARITY;
}
if (uart_handle_sysrq_char(port, c))
continue;
if ((sta_reg & port->ignore_status_mask) == 0)
tty_insert_flip_char(tty, c, flag);
} while (--max_count);
spin_unlock(&port->lock);
tty_flip_buffer_push(tty);
}
/* fill tx fifo with chars to send, stop when fifo is about to be full
* or when all chars have been sent.
*/
static void pic32_uart_do_tx(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
struct circ_buf *xmit = &port->state->xmit;
unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
if (port->x_char) {
pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
port->icount.tx++;
port->x_char = 0;
return;
}
if (uart_tx_stopped(port)) {
pic32_uart_stop_tx(port);
return;
}
if (uart_circ_empty(xmit))
goto txq_empty;
/* keep stuffing chars into uart tx buffer
* 1) until uart fifo is full
* or
* 2) until the circ buffer is empty
* (all chars have been sent)
* or
* 3) until the max count is reached
* (prevents lingering here for too long in certain cases)
*/
while (!(PIC32_UART_STA_UTXBF &
pic32_uart_readl(sport, PIC32_UART_STA))) {
unsigned int c = xmit->buf[xmit->tail];
pic32_uart_writel(sport, PIC32_UART_TX, c);
uart_xmit_advance(port, 1);
if (uart_circ_empty(xmit))
break;
if (--max_count == 0)
break;
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
if (uart_circ_empty(xmit))
goto txq_empty;
return;
txq_empty:
pic32_uart_irqtxen(sport, 0);
}
/* RX interrupt handler */
static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
pic32_uart_do_rx(port);
return IRQ_HANDLED;
}
/* TX interrupt handler */
static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
pic32_uart_do_tx(port);
spin_unlock_irqrestore(&port->lock, flags);
return IRQ_HANDLED;
}
/* FAULT interrupt handler */
static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
{
/* do nothing: pic32_uart_do_rx() handles faults. */
return IRQ_HANDLED;
}
/* enable rx & tx operation on uart */
static void pic32_uart_en_and_unmask(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
PIC32_UART_MODE_ON);
}
/* disable rx & tx operation on uart */
static void pic32_uart_dsbl_and_mask(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
/* wait for tx empty, otherwise chars will be lost or corrupted */
pic32_wait_deplete_txbuf(sport);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_ON);
}
/* serial core request to initialize uart and start rx operation */
static int pic32_uart_startup(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
unsigned long flags;
int ret;
local_irq_save(flags);
ret = clk_prepare_enable(sport->clk);
if (ret) {
local_irq_restore(flags);
goto out_done;
}
/* clear status and mode registers */
pic32_uart_writel(sport, PIC32_UART_MODE, 0);
pic32_uart_writel(sport, PIC32_UART_STA, 0);
/* disable uart and mask all interrupts */
pic32_uart_dsbl_and_mask(port);
/* set default baud */
pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
local_irq_restore(flags);
/* Each UART of a PIC32 has three interrupts therefore,
* we setup driver to register the 3 irqs for the device.
*
* For each irq request_irq() is called with interrupt disabled.
* And the irq is enabled as soon as we are ready to handle them.
*/
sport->enable_tx_irq = false;
sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
pic32_uart_type(port),
sport->idx);
if (!sport->irq_fault_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
ret = -ENOMEM;
goto out_disable_clk;
}
irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
IRQF_NO_THREAD, sport->irq_fault_name, port);
if (ret) {
dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
__func__, sport->irq_fault, ret,
pic32_uart_type(port));
goto out_f;
}
sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
pic32_uart_type(port),
sport->idx);
if (!sport->irq_rx_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
ret = -ENOMEM;
goto out_f;
}
irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
IRQF_NO_THREAD, sport->irq_rx_name, port);
if (ret) {
dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
__func__, sport->irq_rx, ret,
pic32_uart_type(port));
goto out_r;
}
sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
pic32_uart_type(port),
sport->idx);
if (!sport->irq_tx_name) {
dev_err(port->dev, "%s: kasprintf err!", __func__);
ret = -ENOMEM;
goto out_r;
}
irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
IRQF_NO_THREAD, sport->irq_tx_name, port);
if (ret) {
dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
__func__, sport->irq_tx, ret,
pic32_uart_type(port));
goto out_t;
}
local_irq_save(flags);
/* set rx interrupt on first receive */
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
/* set interrupt on empty */
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
PIC32_UART_STA_UTXISEL1);
/* enable all interrupts and eanable uart */
pic32_uart_en_and_unmask(port);
local_irq_restore(flags);
enable_irq(sport->irq_rx);
return 0;
out_t:
free_irq(sport->irq_tx, port);
kfree(sport->irq_tx_name);
out_r:
free_irq(sport->irq_rx, port);
kfree(sport->irq_rx_name);
out_f:
free_irq(sport->irq_fault, port);
kfree(sport->irq_fault_name);
out_disable_clk:
clk_disable_unprepare(sport->clk);
out_done:
return ret;
}
/* serial core request to flush & disable uart */
static void pic32_uart_shutdown(struct uart_port *port)
{
struct pic32_sport *sport = to_pic32_sport(port);
unsigned long flags;
/* disable uart */
spin_lock_irqsave(&port->lock, flags);
pic32_uart_dsbl_and_mask(port);
spin_unlock_irqrestore(&port->lock, flags);
clk_disable_unprepare(sport->clk);
/* free all 3 interrupts for this UART */
free_irq(sport->irq_fault, port);
kfree(sport->irq_fault_name);
free_irq(sport->irq_tx, port);
kfree(sport->irq_tx_name);
free_irq(sport->irq_rx, port);
kfree(sport->irq_rx_name);
}
/* serial core request to change current uart setting */
static void pic32_uart_set_termios(struct uart_port *port,
struct ktermios *new,
const struct ktermios *old)
{
struct pic32_sport *sport = to_pic32_sport(port);
unsigned int baud;
unsigned int quot;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
/* disable uart and mask all interrupts while changing speed */
pic32_uart_dsbl_and_mask(port);
/* stop bit options */
if (new->c_cflag & CSTOPB)
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
PIC32_UART_MODE_STSEL);
else
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_STSEL);
/* parity options */
if (new->c_cflag & PARENB) {
if (new->c_cflag & PARODD) {
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
PIC32_UART_MODE_PDSEL1);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_PDSEL0);
} else {
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
PIC32_UART_MODE_PDSEL0);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_PDSEL1);
}
} else {
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_PDSEL1 |
PIC32_UART_MODE_PDSEL0);
}
/* if hw flow ctrl, then the pins must be specified in device tree */
if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
/* enable hardware flow control */
pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
PIC32_UART_MODE_UEN1);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_UEN0);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_RTSMD);
} else {
/* disable hardware flow control */
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_UEN1);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_UEN0);
pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
PIC32_UART_MODE_RTSMD);
}
/* Always 8-bit */
new->c_cflag |= CS8;
/* Mark/Space parity is not supported */
new->c_cflag &= ~CMSPAR;
/* update baud */
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
quot = uart_get_divisor(port, baud) - 1;
pic32_uart_writel(sport, PIC32_UART_BRG, quot);
uart_update_timeout(port, new->c_cflag, baud);
if (tty_termios_baud_rate(new))
tty_termios_encode_baud_rate(new, baud, baud);
/* enable uart */
pic32_uart_en_and_unmask(port);
spin_unlock_irqrestore(&port->lock, flags);
}
/* serial core request to claim uart iomem */
static int pic32_uart_request_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *res_mem;
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!res_mem))
return -EINVAL;
if (!request_mem_region(port->mapbase, resource_size(res_mem),
"pic32_uart_mem"))
return -EBUSY;
port->membase = devm_ioremap(port->dev, port->mapbase,
resource_size(res_mem));
if (!port->membase) {
dev_err(port->dev, "Unable to map registers\n");
release_mem_region(port->mapbase, resource_size(res_mem));
return -ENOMEM;
}
return 0;
}
/* serial core request to release uart iomem */
static void pic32_uart_release_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct resource *res_mem;
unsigned int res_size;
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!res_mem))
return;
res_size = resource_size(res_mem);
release_mem_region(port->mapbase, res_size);
}
/* serial core request to do any port required auto-configuration */
static void pic32_uart_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE) {
if (pic32_uart_request_port(port))
return;
port->type = PORT_PIC32;
}
}
/* serial core request to check that port information in serinfo are suitable */
static int pic32_uart_verify_port(struct uart_port *port,
struct serial_struct *serinfo)
{
if (port->type != PORT_PIC32)
return -EINVAL;
if (port->irq != serinfo->irq)
return -EINVAL;
if (port->iotype != serinfo->io_type)
return -EINVAL;
if (port->mapbase != (unsigned long)serinfo->iomem_base)
return -EINVAL;
return 0;
}
/* serial core callbacks */
static const struct uart_ops pic32_uart_ops = {
.tx_empty = pic32_uart_tx_empty,
.get_mctrl = pic32_uart_get_mctrl,
.set_mctrl = pic32_uart_set_mctrl,
.start_tx = pic32_uart_start_tx,
.stop_tx = pic32_uart_stop_tx,
.stop_rx = pic32_uart_stop_rx,
.break_ctl = pic32_uart_break_ctl,
.startup = pic32_uart_startup,
.shutdown = pic32_uart_shutdown,
.set_termios = pic32_uart_set_termios,
.type = pic32_uart_type,
.release_port = pic32_uart_release_port,
.request_port = pic32_uart_request_port,
.config_port = pic32_uart_config_port,
.verify_port = pic32_uart_verify_port,
};
#ifdef CONFIG_SERIAL_PIC32_CONSOLE
/* output given char */
static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
{
struct pic32_sport *sport = to_pic32_sport(port);
if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
return;
if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
return;
/* wait for tx empty */
pic32_wait_deplete_txbuf(sport);
pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
}
/* console core request to output given string */
static void pic32_console_write(struct console *co, const char *s,
unsigned int count)
{
struct pic32_sport *sport = pic32_sports[co->index];
/* call uart helper to deal with \r\n */
uart_console_write(&sport->port, s, count, pic32_console_putchar);
}
/* console core request to setup given console, find matching uart
* port and setup it.
*/
static int pic32_console_setup(struct console *co, char *options)
{
struct pic32_sport *sport;
int baud = 115200;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret = 0;
if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
return -ENODEV;
sport = pic32_sports[co->index];
if (!sport)
return -ENODEV;
ret = clk_prepare_enable(sport->clk);
if (ret)
return ret;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(&sport->port, co, baud, parity, bits, flow);
}
static struct uart_driver pic32_uart_driver;
static struct console pic32_console = {
.name = PIC32_SDEV_NAME,
.write = pic32_console_write,
.device = uart_console_device,
.setup = pic32_console_setup,
.flags = CON_PRINTBUFFER,
.index = -1,
.data = &pic32_uart_driver,
};
#define PIC32_SCONSOLE (&pic32_console)
static int __init pic32_console_init(void)
{
register_console(&pic32_console);
return 0;
}
console_initcall(pic32_console_init);
/*
* Late console initialization.
*/
static int __init pic32_late_console_init(void)
{
if (!console_is_registered(&pic32_console))
register_console(&pic32_console);
return 0;
}
core_initcall(pic32_late_console_init);
#else
#define PIC32_SCONSOLE NULL
#endif
static struct uart_driver pic32_uart_driver = {
.owner = THIS_MODULE,
.driver_name = PIC32_DEV_NAME,
.dev_name = PIC32_SDEV_NAME,
.nr = PIC32_MAX_UARTS,
.cons = PIC32_SCONSOLE,
};
static int pic32_uart_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct pic32_sport *sport;
int uart_idx = 0;
struct resource *res_mem;
struct uart_port *port;
int ret;
uart_idx = of_alias_get_id(np, "serial");
if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
return -EINVAL;
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res_mem)
return -EINVAL;
sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
if (!sport)
return -ENOMEM;
sport->idx = uart_idx;
sport->irq_fault = irq_of_parse_and_map(np, 0);
sport->irq_rx = irq_of_parse_and_map(np, 1);
sport->irq_tx = irq_of_parse_and_map(np, 2);
sport->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(sport->clk))
return PTR_ERR(sport->clk);
sport->dev = &pdev->dev;
/* Hardware flow control: gpios
* !Note: Basically, CTS is needed for reading the status.
*/
sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
if (IS_ERR(sport->cts_gpiod))
return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
pic32_sports[uart_idx] = sport;
port = &sport->port;
port->iotype = UPIO_MEM;
port->mapbase = res_mem->start;
port->ops = &pic32_uart_ops;
port->flags = UPF_BOOT_AUTOCONF;
port->dev = &pdev->dev;
port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
port->uartclk = clk_get_rate(sport->clk);
port->line = uart_idx;
ret = uart_add_one_port(&pic32_uart_driver, port);
if (ret) {
port->membase = NULL;
dev_err(port->dev, "%s: uart add port error!\n", __func__);
goto err;
}
#ifdef CONFIG_SERIAL_PIC32_CONSOLE
if (uart_console_registered(port)) {
/* The peripheral clock has been enabled by console_setup,
* so disable it till the port is used.
*/
clk_disable_unprepare(sport->clk);
}
#endif
platform_set_drvdata(pdev, port);
dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
__func__, uart_idx);
return 0;
err:
/* automatic unroll of sport and gpios */
return ret;
}
static int pic32_uart_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
struct pic32_sport *sport = to_pic32_sport(port);
uart_remove_one_port(&pic32_uart_driver, port);
clk_disable_unprepare(sport->clk);
platform_set_drvdata(pdev, NULL);
pic32_sports[sport->idx] = NULL;
/* automatic unroll of sport and gpios */
return 0;
}
static const struct of_device_id pic32_serial_dt_ids[] = {
{ .compatible = "microchip,pic32mzda-uart" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
static struct platform_driver pic32_uart_platform_driver = {
.probe = pic32_uart_probe,
.remove = pic32_uart_remove,
.driver = {
.name = PIC32_DEV_NAME,
.of_match_table = of_match_ptr(pic32_serial_dt_ids),
.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
},
};
static int __init pic32_uart_init(void)
{
int ret;
ret = uart_register_driver(&pic32_uart_driver);
if (ret) {
pr_err("failed to register %s:%d\n",
pic32_uart_driver.driver_name, ret);
return ret;
}
ret = platform_driver_register(&pic32_uart_platform_driver);
if (ret) {
pr_err("fail to register pic32 uart\n");
uart_unregister_driver(&pic32_uart_driver);
}
return ret;
}
arch_initcall(pic32_uart_init);
static void __exit pic32_uart_exit(void)
{
#ifdef CONFIG_SERIAL_PIC32_CONSOLE
unregister_console(&pic32_console);
#endif
platform_driver_unregister(&pic32_uart_platform_driver);
uart_unregister_driver(&pic32_uart_driver);
}
module_exit(pic32_uart_exit);
MODULE_AUTHOR("Sorin-Andrei Pistirica <[email protected]>");
MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/pic32_uart.c |
// SPDX-License-Identifier: GPL-2.0
/*
*Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
*/
#include <linux/kernel.h>
#include <linux/serial.h>
#include <linux/serial_reg.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/console.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/dmi.h>
#include <linux/nmi.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/debugfs.h>
#include <linux/dmaengine.h>
#include <linux/pch_dma.h>
enum {
PCH_UART_HANDLED_RX_INT_SHIFT,
PCH_UART_HANDLED_TX_INT_SHIFT,
PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
PCH_UART_HANDLED_MS_INT_SHIFT,
PCH_UART_HANDLED_LS_INT_SHIFT,
};
#define PCH_UART_DRIVER_DEVICE "ttyPCH"
/* Set the max number of UART port
* Intel EG20T PCH: 4 port
* LAPIS Semiconductor ML7213 IOH: 3 port
* LAPIS Semiconductor ML7223 IOH: 2 port
*/
#define PCH_UART_NR 4
#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
#define PCH_UART_RBR 0x00
#define PCH_UART_THR 0x00
#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
#define PCH_UART_IER_ERBFI 0x00000001
#define PCH_UART_IER_ETBEI 0x00000002
#define PCH_UART_IER_ELSI 0x00000004
#define PCH_UART_IER_EDSSI 0x00000008
#define PCH_UART_IIR_IP 0x00000001
#define PCH_UART_IIR_IID 0x00000006
#define PCH_UART_IIR_MSI 0x00000000
#define PCH_UART_IIR_TRI 0x00000002
#define PCH_UART_IIR_RRI 0x00000004
#define PCH_UART_IIR_REI 0x00000006
#define PCH_UART_IIR_TOI 0x00000008
#define PCH_UART_IIR_FIFO256 0x00000020
#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
#define PCH_UART_IIR_FE 0x000000C0
#define PCH_UART_FCR_FIFOE 0x00000001
#define PCH_UART_FCR_RFR 0x00000002
#define PCH_UART_FCR_TFR 0x00000004
#define PCH_UART_FCR_DMS 0x00000008
#define PCH_UART_FCR_FIFO256 0x00000020
#define PCH_UART_FCR_RFTL 0x000000C0
#define PCH_UART_FCR_RFTL1 0x00000000
#define PCH_UART_FCR_RFTL64 0x00000040
#define PCH_UART_FCR_RFTL128 0x00000080
#define PCH_UART_FCR_RFTL224 0x000000C0
#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
#define PCH_UART_FCR_RFTL_SHIFT 6
#define PCH_UART_LCR_WLS 0x00000003
#define PCH_UART_LCR_STB 0x00000004
#define PCH_UART_LCR_PEN 0x00000008
#define PCH_UART_LCR_EPS 0x00000010
#define PCH_UART_LCR_SP 0x00000020
#define PCH_UART_LCR_SB 0x00000040
#define PCH_UART_LCR_DLAB 0x00000080
#define PCH_UART_LCR_NP 0x00000000
#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
PCH_UART_LCR_SP)
#define PCH_UART_LCR_5BIT 0x00000000
#define PCH_UART_LCR_6BIT 0x00000001
#define PCH_UART_LCR_7BIT 0x00000002
#define PCH_UART_LCR_8BIT 0x00000003
#define PCH_UART_MCR_DTR 0x00000001
#define PCH_UART_MCR_RTS 0x00000002
#define PCH_UART_MCR_OUT 0x0000000C
#define PCH_UART_MCR_LOOP 0x00000010
#define PCH_UART_MCR_AFE 0x00000020
#define PCH_UART_LSR_DR 0x00000001
#define PCH_UART_LSR_ERR (1<<7)
#define PCH_UART_MSR_DCTS 0x00000001
#define PCH_UART_MSR_DDSR 0x00000002
#define PCH_UART_MSR_TERI 0x00000004
#define PCH_UART_MSR_DDCD 0x00000008
#define PCH_UART_MSR_CTS 0x00000010
#define PCH_UART_MSR_DSR 0x00000020
#define PCH_UART_MSR_RI 0x00000040
#define PCH_UART_MSR_DCD 0x00000080
#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
#define PCH_UART_DLL 0x00
#define PCH_UART_DLM 0x01
#define PCH_UART_BRCSR 0x0E
#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
#define PCH_UART_HAL_STB1 0
#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
PCH_UART_HAL_CLR_RX_FIFO)
#define PCH_UART_HAL_DMA_MODE0 0
#define PCH_UART_HAL_FIFO_DIS 0
#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
PCH_UART_FCR_FIFO256)
#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
#define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
#define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
#define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
#define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
#define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
#define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
struct pch_uart_buffer {
unsigned char *buf;
int size;
};
struct eg20t_port {
struct uart_port port;
int port_type;
void __iomem *membase;
resource_size_t mapbase;
unsigned int iobase;
struct pci_dev *pdev;
int fifo_size;
unsigned int uartclk;
int start_tx;
int start_rx;
int tx_empty;
int trigger;
int trigger_level;
struct pch_uart_buffer rxbuf;
unsigned int dmsr;
unsigned int fcr;
unsigned int mcr;
unsigned int use_dma;
struct dma_async_tx_descriptor *desc_tx;
struct dma_async_tx_descriptor *desc_rx;
struct pch_dma_slave param_tx;
struct pch_dma_slave param_rx;
struct dma_chan *chan_tx;
struct dma_chan *chan_rx;
struct scatterlist *sg_tx_p;
int nent;
int orig_nent;
struct scatterlist sg_rx;
int tx_dma_use;
void *rx_buf_virt;
dma_addr_t rx_buf_dma;
#define IRQ_NAME_SIZE 17
char irq_name[IRQ_NAME_SIZE];
/* protect the eg20t_port private structure and io access to membase */
spinlock_t lock;
};
/**
* struct pch_uart_driver_data - private data structure for UART-DMA
* @port_type: The type of UART port
* @line_no: UART port line number (0, 1, 2...)
*/
struct pch_uart_driver_data {
int port_type;
int line_no;
};
enum pch_uart_num_t {
pch_et20t_uart0 = 0,
pch_et20t_uart1,
pch_et20t_uart2,
pch_et20t_uart3,
pch_ml7213_uart0,
pch_ml7213_uart1,
pch_ml7213_uart2,
pch_ml7223_uart0,
pch_ml7223_uart1,
pch_ml7831_uart0,
pch_ml7831_uart1,
};
static struct pch_uart_driver_data drv_dat[] = {
[pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
[pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
[pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
[pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
[pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
[pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
[pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
[pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
[pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
[pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
[pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
};
#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
#endif
static unsigned int default_baud = 9600;
static unsigned int user_uartclk = 0;
static const int trigger_level_256[4] = { 1, 64, 128, 224 };
static const int trigger_level_64[4] = { 1, 16, 32, 56 };
static const int trigger_level_16[4] = { 1, 4, 8, 14 };
static const int trigger_level_1[4] = { 1, 1, 1, 1 };
#define PCH_REGS_BUFSIZE 1024
static ssize_t port_show_regs(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct eg20t_port *priv = file->private_data;
char *buf;
u32 len = 0;
ssize_t ret;
unsigned char lcr;
buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
if (!buf)
return 0;
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"PCH EG20T port[%d] regs:\n", priv->port.line);
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"=================================\n");
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"BRCSR: \t0x%02x\n",
ioread8(priv->membase + PCH_UART_BRCSR));
lcr = ioread8(priv->membase + UART_LCR);
iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
"DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
iowrite8(lcr, priv->membase + UART_LCR);
if (len > PCH_REGS_BUFSIZE)
len = PCH_REGS_BUFSIZE;
ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
kfree(buf);
return ret;
}
static const struct file_operations port_regs_ops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = port_show_regs,
.llseek = default_llseek,
};
static const struct dmi_system_id pch_uart_dmi_table[] = {
{
.ident = "CM-iTC",
{
DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
},
(void *)CMITC_UARTCLK,
},
{
.ident = "FRI2",
{
DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
},
(void *)FRI2_64_UARTCLK,
},
{
.ident = "Fish River Island II",
{
DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
},
(void *)FRI2_48_UARTCLK,
},
{
.ident = "COMe-mTT",
{
DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
},
(void *)NTC1_UARTCLK,
},
{
.ident = "nanoETXexpress-TT",
{
DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
},
(void *)NTC1_UARTCLK,
},
{
.ident = "MinnowBoard",
{
DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
},
(void *)MINNOW_UARTCLK,
},
{ }
};
/* Return UART clock, checking for board specific clocks. */
static unsigned int pch_uart_get_uartclk(void)
{
const struct dmi_system_id *d;
if (user_uartclk)
return user_uartclk;
d = dmi_first_match(pch_uart_dmi_table);
if (d)
return (unsigned long)d->driver_data;
return DEFAULT_UARTCLK;
}
static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
unsigned int flag)
{
u8 ier = ioread8(priv->membase + UART_IER);
ier |= flag & PCH_UART_IER_MASK;
iowrite8(ier, priv->membase + UART_IER);
}
static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
unsigned int flag)
{
u8 ier = ioread8(priv->membase + UART_IER);
ier &= ~(flag & PCH_UART_IER_MASK);
iowrite8(ier, priv->membase + UART_IER);
}
static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
unsigned int parity, unsigned int bits,
unsigned int stb)
{
unsigned int dll, dlm, lcr;
int div;
div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
if (div < 0 || USHRT_MAX <= div) {
dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
return -EINVAL;
}
dll = (unsigned int)div & 0x00FFU;
dlm = ((unsigned int)div >> 8) & 0x00FFU;
if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
return -EINVAL;
}
if (bits & ~PCH_UART_LCR_WLS) {
dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
return -EINVAL;
}
if (stb & ~PCH_UART_LCR_STB) {
dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
return -EINVAL;
}
lcr = parity;
lcr |= bits;
lcr |= stb;
dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
__func__, baud, div, lcr, jiffies);
iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
iowrite8(dll, priv->membase + PCH_UART_DLL);
iowrite8(dlm, priv->membase + PCH_UART_DLM);
iowrite8(lcr, priv->membase + UART_LCR);
return 0;
}
static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
unsigned int flag)
{
if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
__func__, flag);
return -EINVAL;
}
iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
priv->membase + UART_FCR);
iowrite8(priv->fcr, priv->membase + UART_FCR);
return 0;
}
static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
unsigned int dmamode,
unsigned int fifo_size, unsigned int trigger)
{
u8 fcr;
if (dmamode & ~PCH_UART_FCR_DMS) {
dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
__func__, dmamode);
return -EINVAL;
}
if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
__func__, fifo_size);
return -EINVAL;
}
if (trigger & ~PCH_UART_FCR_RFTL) {
dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
__func__, trigger);
return -EINVAL;
}
switch (priv->fifo_size) {
case 256:
priv->trigger_level =
trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
break;
case 64:
priv->trigger_level =
trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
break;
case 16:
priv->trigger_level =
trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
break;
default:
priv->trigger_level =
trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
break;
}
fcr =
dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
priv->membase + UART_FCR);
iowrite8(fcr, priv->membase + UART_FCR);
priv->fcr = fcr;
return 0;
}
static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
{
unsigned int msr = ioread8(priv->membase + UART_MSR);
priv->dmsr = msr & PCH_UART_MSR_DELTA;
return (u8)msr;
}
static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
int rx_size)
{
int i;
u8 rbr, lsr;
struct uart_port *port = &priv->port;
lsr = ioread8(priv->membase + UART_LSR);
for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
lsr = ioread8(priv->membase + UART_LSR)) {
rbr = ioread8(priv->membase + PCH_UART_RBR);
if (lsr & UART_LSR_BI) {
port->icount.brk++;
if (uart_handle_break(port))
continue;
}
if (uart_handle_sysrq_char(port, rbr))
continue;
buf[i++] = rbr;
}
return i;
}
static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
{
return ioread8(priv->membase + UART_IIR) &\
(PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
}
static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
{
return ioread8(priv->membase + UART_LSR);
}
static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
{
unsigned int lcr;
lcr = ioread8(priv->membase + UART_LCR);
if (on)
lcr |= PCH_UART_LCR_SB;
else
lcr &= ~PCH_UART_LCR_SB;
iowrite8(lcr, priv->membase + UART_LCR);
}
static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
int size)
{
struct uart_port *port = &priv->port;
struct tty_port *tport = &port->state->port;
tty_insert_flip_string(tport, buf, size);
tty_flip_buffer_push(tport);
return 0;
}
static int dma_push_rx(struct eg20t_port *priv, int size)
{
int room;
struct uart_port *port = &priv->port;
struct tty_port *tport = &port->state->port;
room = tty_buffer_request_room(tport, size);
if (room < size)
dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
size - room);
if (!room)
return 0;
tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
port->icount.rx += room;
return room;
}
static void pch_free_dma(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
if (priv->chan_tx) {
dma_release_channel(priv->chan_tx);
priv->chan_tx = NULL;
}
if (priv->chan_rx) {
dma_release_channel(priv->chan_rx);
priv->chan_rx = NULL;
}
if (priv->rx_buf_dma) {
dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
priv->rx_buf_dma);
priv->rx_buf_virt = NULL;
priv->rx_buf_dma = 0;
}
return;
}
static bool filter(struct dma_chan *chan, void *slave)
{
struct pch_dma_slave *param = slave;
if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
chan->device->dev)) {
chan->private = param;
return true;
} else {
return false;
}
}
static void pch_request_dma(struct uart_port *port)
{
dma_cap_mask_t mask;
struct dma_chan *chan;
struct pci_dev *dma_dev;
struct pch_dma_slave *param;
struct eg20t_port *priv =
container_of(port, struct eg20t_port, port);
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
/* Get DMA's dev information */
dma_dev = pci_get_slot(priv->pdev->bus,
PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
/* Set Tx DMA */
param = &priv->param_tx;
param->dma_dev = &dma_dev->dev;
param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
param->tx_reg = port->mapbase + UART_TX;
chan = dma_request_channel(mask, filter, param);
if (!chan) {
dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
__func__);
pci_dev_put(dma_dev);
return;
}
priv->chan_tx = chan;
/* Set Rx DMA */
param = &priv->param_rx;
param->dma_dev = &dma_dev->dev;
param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
param->rx_reg = port->mapbase + UART_RX;
chan = dma_request_channel(mask, filter, param);
if (!chan) {
dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
__func__);
dma_release_channel(priv->chan_tx);
priv->chan_tx = NULL;
pci_dev_put(dma_dev);
return;
}
/* Get Consistent memory for DMA */
priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
&priv->rx_buf_dma, GFP_KERNEL);
priv->chan_rx = chan;
pci_dev_put(dma_dev);
}
static void pch_dma_rx_complete(void *arg)
{
struct eg20t_port *priv = arg;
struct uart_port *port = &priv->port;
int count;
dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
count = dma_push_rx(priv, priv->trigger_level);
if (count)
tty_flip_buffer_push(&port->state->port);
async_tx_ack(priv->desc_rx);
pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
PCH_UART_HAL_RX_ERR_INT);
}
static void pch_dma_tx_complete(void *arg)
{
struct eg20t_port *priv = arg;
struct uart_port *port = &priv->port;
struct scatterlist *sg = priv->sg_tx_p;
int i;
for (i = 0; i < priv->nent; i++, sg++)
uart_xmit_advance(port, sg_dma_len(sg));
async_tx_ack(priv->desc_tx);
dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE);
priv->tx_dma_use = 0;
priv->nent = 0;
priv->orig_nent = 0;
kfree(priv->sg_tx_p);
pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
}
static int handle_rx_to(struct eg20t_port *priv)
{
struct pch_uart_buffer *buf;
int rx_size;
int ret;
if (!priv->start_rx) {
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
PCH_UART_HAL_RX_ERR_INT);
return 0;
}
buf = &priv->rxbuf;
do {
rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
ret = push_rx(priv, buf->buf, rx_size);
if (ret)
return 0;
} while (rx_size == buf->size);
return PCH_UART_HANDLED_RX_INT;
}
static int handle_rx(struct eg20t_port *priv)
{
return handle_rx_to(priv);
}
static int dma_handle_rx(struct eg20t_port *priv)
{
struct uart_port *port = &priv->port;
struct dma_async_tx_descriptor *desc;
struct scatterlist *sg;
priv = container_of(port, struct eg20t_port, port);
sg = &priv->sg_rx;
sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
sg_dma_len(sg) = priv->trigger_level;
sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
sg_dma_address(sg) = priv->rx_buf_dma;
desc = dmaengine_prep_slave_sg(priv->chan_rx,
sg, 1, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc)
return 0;
priv->desc_rx = desc;
desc->callback = pch_dma_rx_complete;
desc->callback_param = priv;
desc->tx_submit(desc);
dma_async_issue_pending(priv->chan_rx);
return PCH_UART_HANDLED_RX_INT;
}
static unsigned int handle_tx(struct eg20t_port *priv)
{
struct uart_port *port = &priv->port;
struct circ_buf *xmit = &port->state->xmit;
int fifo_size;
int tx_empty;
if (!priv->start_tx) {
dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
__func__, jiffies);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
priv->tx_empty = 1;
return 0;
}
fifo_size = max(priv->fifo_size, 1);
tx_empty = 1;
if (port->x_char) {
iowrite8(port->x_char, priv->membase + PCH_UART_THR);
port->icount.tx++;
port->x_char = 0;
tx_empty = 0;
fifo_size--;
}
while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
uart_xmit_advance(port, 1);
fifo_size--;
tx_empty = 0;
}
priv->tx_empty = tx_empty;
if (tx_empty) {
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
uart_write_wakeup(port);
}
return PCH_UART_HANDLED_TX_INT;
}
static unsigned int dma_handle_tx(struct eg20t_port *priv)
{
struct uart_port *port = &priv->port;
struct circ_buf *xmit = &port->state->xmit;
struct scatterlist *sg;
int nent;
int fifo_size;
struct dma_async_tx_descriptor *desc;
int num;
int i;
int bytes;
int size;
int rem;
if (!priv->start_tx) {
dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
__func__, jiffies);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
priv->tx_empty = 1;
return 0;
}
if (priv->tx_dma_use) {
dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
__func__, jiffies);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
priv->tx_empty = 1;
return 0;
}
fifo_size = max(priv->fifo_size, 1);
if (port->x_char) {
iowrite8(port->x_char, priv->membase + PCH_UART_THR);
port->icount.tx++;
port->x_char = 0;
fifo_size--;
}
bytes = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
if (!bytes) {
dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
uart_write_wakeup(port);
return 0;
}
if (bytes > fifo_size) {
num = bytes / fifo_size + 1;
size = fifo_size;
rem = bytes % fifo_size;
} else {
num = 1;
size = bytes;
rem = bytes;
}
dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
__func__, num, size, rem);
priv->tx_dma_use = 1;
priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
if (!priv->sg_tx_p) {
dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
return 0;
}
sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
sg = priv->sg_tx_p;
for (i = 0; i < num; i++, sg++) {
if (i == (num - 1))
sg_set_page(sg, virt_to_page(xmit->buf),
rem, fifo_size * i);
else
sg_set_page(sg, virt_to_page(xmit->buf),
size, fifo_size * i);
}
sg = priv->sg_tx_p;
nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
if (!nent) {
dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
return 0;
}
priv->orig_nent = num;
priv->nent = nent;
for (i = 0; i < nent; i++, sg++) {
sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
fifo_size * i;
sg_dma_address(sg) = (sg_dma_address(sg) &
~(UART_XMIT_SIZE - 1)) + sg->offset;
if (i == (nent - 1))
sg_dma_len(sg) = rem;
else
sg_dma_len(sg) = size;
}
desc = dmaengine_prep_slave_sg(priv->chan_tx,
priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
__func__);
return 0;
}
dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
priv->desc_tx = desc;
desc->callback = pch_dma_tx_complete;
desc->callback_param = priv;
desc->tx_submit(desc);
dma_async_issue_pending(priv->chan_tx);
return PCH_UART_HANDLED_TX_INT;
}
static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
{
struct uart_port *port = &priv->port;
struct tty_struct *tty = tty_port_tty_get(&port->state->port);
char *error_msg[5] = {};
int i = 0;
if (lsr & PCH_UART_LSR_ERR)
error_msg[i++] = "Error data in FIFO\n";
if (lsr & UART_LSR_FE) {
port->icount.frame++;
error_msg[i++] = " Framing Error\n";
}
if (lsr & UART_LSR_PE) {
port->icount.parity++;
error_msg[i++] = " Parity Error\n";
}
if (lsr & UART_LSR_OE) {
port->icount.overrun++;
error_msg[i++] = " Overrun Error\n";
}
if (tty == NULL) {
for (i = 0; error_msg[i] != NULL; i++)
dev_err(&priv->pdev->dev, error_msg[i]);
} else {
tty_kref_put(tty);
}
}
static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
{
struct eg20t_port *priv = dev_id;
unsigned int handled;
u8 lsr;
int ret = 0;
unsigned char iid;
unsigned long flags;
int next = 1;
u8 msr;
spin_lock_irqsave(&priv->lock, flags);
handled = 0;
while (next) {
iid = pch_uart_hal_get_iid(priv);
if (iid & PCH_UART_IIR_IP) /* No Interrupt */
break;
switch (iid) {
case PCH_UART_IID_RLS: /* Receiver Line Status */
lsr = pch_uart_hal_get_line_status(priv);
if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
UART_LSR_PE | UART_LSR_OE)) {
pch_uart_err_ir(priv, lsr);
ret = PCH_UART_HANDLED_RX_ERR_INT;
} else {
ret = PCH_UART_HANDLED_LS_INT;
}
break;
case PCH_UART_IID_RDR: /* Received Data Ready */
if (priv->use_dma) {
pch_uart_hal_disable_interrupt(priv,
PCH_UART_HAL_RX_INT |
PCH_UART_HAL_RX_ERR_INT);
ret = dma_handle_rx(priv);
if (!ret)
pch_uart_hal_enable_interrupt(priv,
PCH_UART_HAL_RX_INT |
PCH_UART_HAL_RX_ERR_INT);
} else {
ret = handle_rx(priv);
}
break;
case PCH_UART_IID_RDR_TO: /* Received Data Ready
(FIFO Timeout) */
ret = handle_rx_to(priv);
break;
case PCH_UART_IID_THRE: /* Transmitter Holding Register
Empty */
if (priv->use_dma)
ret = dma_handle_tx(priv);
else
ret = handle_tx(priv);
break;
case PCH_UART_IID_MS: /* Modem Status */
msr = pch_uart_hal_get_modem(priv);
next = 0; /* MS ir prioirty is the lowest. So, MS ir
means final interrupt */
if ((msr & UART_MSR_ANY_DELTA) == 0)
break;
ret |= PCH_UART_HANDLED_MS_INT;
break;
default: /* Never junp to this label */
dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
iid, jiffies);
ret = -1;
next = 0;
break;
}
handled |= (unsigned int)ret;
}
spin_unlock_irqrestore(&priv->lock, flags);
return IRQ_RETVAL(handled);
}
/* This function tests whether the transmitter fifo and shifter for the port
described by 'port' is empty. */
static unsigned int pch_uart_tx_empty(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
if (priv->tx_empty)
return TIOCSER_TEMT;
else
return 0;
}
/* Returns the current state of modem control inputs. */
static unsigned int pch_uart_get_mctrl(struct uart_port *port)
{
struct eg20t_port *priv;
u8 modem;
unsigned int ret = 0;
priv = container_of(port, struct eg20t_port, port);
modem = pch_uart_hal_get_modem(priv);
if (modem & UART_MSR_DCD)
ret |= TIOCM_CAR;
if (modem & UART_MSR_RI)
ret |= TIOCM_RNG;
if (modem & UART_MSR_DSR)
ret |= TIOCM_DSR;
if (modem & UART_MSR_CTS)
ret |= TIOCM_CTS;
return ret;
}
static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
u32 mcr = 0;
struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
if (mctrl & TIOCM_DTR)
mcr |= UART_MCR_DTR;
if (mctrl & TIOCM_RTS)
mcr |= UART_MCR_RTS;
if (mctrl & TIOCM_LOOP)
mcr |= UART_MCR_LOOP;
if (priv->mcr & UART_MCR_AFE)
mcr |= UART_MCR_AFE;
if (mctrl)
iowrite8(mcr, priv->membase + UART_MCR);
}
static void pch_uart_stop_tx(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
priv->start_tx = 0;
priv->tx_dma_use = 0;
}
static void pch_uart_start_tx(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
if (priv->use_dma) {
if (priv->tx_dma_use) {
dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
__func__);
return;
}
}
priv->start_tx = 1;
pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
}
static void pch_uart_stop_rx(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
priv->start_rx = 0;
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
PCH_UART_HAL_RX_ERR_INT);
}
/* Enable the modem status interrupts. */
static void pch_uart_enable_ms(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
}
/* Control the transmission of a break signal. */
static void pch_uart_break_ctl(struct uart_port *port, int ctl)
{
struct eg20t_port *priv;
unsigned long flags;
priv = container_of(port, struct eg20t_port, port);
spin_lock_irqsave(&priv->lock, flags);
pch_uart_hal_set_break(priv, ctl);
spin_unlock_irqrestore(&priv->lock, flags);
}
/* Grab any interrupt resources and initialise any low level driver state. */
static int pch_uart_startup(struct uart_port *port)
{
struct eg20t_port *priv;
int ret;
int fifo_size;
int trigger_level;
priv = container_of(port, struct eg20t_port, port);
priv->tx_empty = 1;
if (port->uartclk)
priv->uartclk = port->uartclk;
else
port->uartclk = priv->uartclk;
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
ret = pch_uart_hal_set_line(priv, default_baud,
PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
PCH_UART_HAL_STB1);
if (ret)
return ret;
switch (priv->fifo_size) {
case 256:
fifo_size = PCH_UART_HAL_FIFO256;
break;
case 64:
fifo_size = PCH_UART_HAL_FIFO64;
break;
case 16:
fifo_size = PCH_UART_HAL_FIFO16;
break;
case 1:
default:
fifo_size = PCH_UART_HAL_FIFO_DIS;
break;
}
switch (priv->trigger) {
case PCH_UART_HAL_TRIGGER1:
trigger_level = 1;
break;
case PCH_UART_HAL_TRIGGER_L:
trigger_level = priv->fifo_size / 4;
break;
case PCH_UART_HAL_TRIGGER_M:
trigger_level = priv->fifo_size / 2;
break;
case PCH_UART_HAL_TRIGGER_H:
default:
trigger_level = priv->fifo_size - (priv->fifo_size / 8);
break;
}
priv->trigger_level = trigger_level;
ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
fifo_size, priv->trigger);
if (ret < 0)
return ret;
ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
priv->irq_name, priv);
if (ret < 0)
return ret;
if (priv->use_dma)
pch_request_dma(port);
priv->start_rx = 1;
pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
PCH_UART_HAL_RX_ERR_INT);
uart_update_timeout(port, CS8, default_baud);
return 0;
}
static void pch_uart_shutdown(struct uart_port *port)
{
struct eg20t_port *priv;
int ret;
priv = container_of(port, struct eg20t_port, port);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
if (ret)
dev_err(priv->port.dev,
"pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
pch_free_dma(port);
free_irq(priv->port.irq, priv);
}
/* Change the port parameters, including word length, parity, stop
*bits. Update read_status_mask and ignore_status_mask to indicate
*the types of events we are interested in receiving. */
static void pch_uart_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
int rtn;
unsigned int baud, parity, bits, stb;
struct eg20t_port *priv;
unsigned long flags;
priv = container_of(port, struct eg20t_port, port);
switch (termios->c_cflag & CSIZE) {
case CS5:
bits = PCH_UART_HAL_5BIT;
break;
case CS6:
bits = PCH_UART_HAL_6BIT;
break;
case CS7:
bits = PCH_UART_HAL_7BIT;
break;
default: /* CS8 */
bits = PCH_UART_HAL_8BIT;
break;
}
if (termios->c_cflag & CSTOPB)
stb = PCH_UART_HAL_STB2;
else
stb = PCH_UART_HAL_STB1;
if (termios->c_cflag & PARENB) {
if (termios->c_cflag & PARODD)
parity = PCH_UART_HAL_PARITY_ODD;
else
parity = PCH_UART_HAL_PARITY_EVEN;
} else
parity = PCH_UART_HAL_PARITY_NONE;
/* Only UART0 has auto hardware flow function */
if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
priv->mcr |= UART_MCR_AFE;
else
priv->mcr &= ~UART_MCR_AFE;
termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
spin_lock_irqsave(&priv->lock, flags);
spin_lock(&port->lock);
uart_update_timeout(port, termios->c_cflag, baud);
rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
if (rtn)
goto out;
pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);
out:
spin_unlock(&port->lock);
spin_unlock_irqrestore(&priv->lock, flags);
}
static const char *pch_uart_type(struct uart_port *port)
{
return KBUILD_MODNAME;
}
static void pch_uart_release_port(struct uart_port *port)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
pci_iounmap(priv->pdev, priv->membase);
pci_release_regions(priv->pdev);
}
static int pch_uart_request_port(struct uart_port *port)
{
struct eg20t_port *priv;
int ret;
void __iomem *membase;
priv = container_of(port, struct eg20t_port, port);
ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
if (ret < 0)
return -EBUSY;
membase = pci_iomap(priv->pdev, 1, 0);
if (!membase) {
pci_release_regions(priv->pdev);
return -EBUSY;
}
priv->membase = port->membase = membase;
return 0;
}
static void pch_uart_config_port(struct uart_port *port, int type)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
if (type & UART_CONFIG_TYPE) {
port->type = priv->port_type;
pch_uart_request_port(port);
}
}
static int pch_uart_verify_port(struct uart_port *port,
struct serial_struct *serinfo)
{
struct eg20t_port *priv;
priv = container_of(port, struct eg20t_port, port);
if (serinfo->flags & UPF_LOW_LATENCY) {
dev_info(priv->port.dev,
"PCH UART : Use PIO Mode (without DMA)\n");
priv->use_dma = 0;
serinfo->flags &= ~UPF_LOW_LATENCY;
} else {
#ifndef CONFIG_PCH_DMA
dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
__func__);
return -EOPNOTSUPP;
#endif
if (!priv->use_dma) {
pch_request_dma(port);
if (priv->chan_rx)
priv->use_dma = 1;
}
dev_info(priv->port.dev, "PCH UART: %s\n",
priv->use_dma ?
"Use DMA Mode" : "No DMA");
}
return 0;
}
#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
/*
* Wait for transmitter & holding register to empty
*/
static void wait_for_xmitr(struct eg20t_port *up, int bits)
{
unsigned int status, tmout = 10000;
/* Wait up to 10ms for the character(s) to be sent. */
for (;;) {
status = ioread8(up->membase + UART_LSR);
if ((status & bits) == bits)
break;
if (--tmout == 0)
break;
udelay(1);
}
/* Wait up to 1s for flow control if necessary */
if (up->port.flags & UPF_CONS_FLOW) {
unsigned int tmout;
for (tmout = 1000000; tmout; tmout--) {
unsigned int msr = ioread8(up->membase + UART_MSR);
if (msr & UART_MSR_CTS)
break;
udelay(1);
touch_nmi_watchdog();
}
}
}
#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
#ifdef CONFIG_CONSOLE_POLL
/*
* Console polling routines for communicate via uart while
* in an interrupt or debug context.
*/
static int pch_uart_get_poll_char(struct uart_port *port)
{
struct eg20t_port *priv =
container_of(port, struct eg20t_port, port);
u8 lsr = ioread8(priv->membase + UART_LSR);
if (!(lsr & UART_LSR_DR))
return NO_POLL_CHAR;
return ioread8(priv->membase + PCH_UART_RBR);
}
static void pch_uart_put_poll_char(struct uart_port *port,
unsigned char c)
{
unsigned int ier;
struct eg20t_port *priv =
container_of(port, struct eg20t_port, port);
/*
* First save the IER then disable the interrupts
*/
ier = ioread8(priv->membase + UART_IER);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
wait_for_xmitr(priv, UART_LSR_THRE);
/*
* Send the character out.
*/
iowrite8(c, priv->membase + PCH_UART_THR);
/*
* Finally, wait for transmitter to become empty
* and restore the IER
*/
wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
iowrite8(ier, priv->membase + UART_IER);
}
#endif /* CONFIG_CONSOLE_POLL */
static const struct uart_ops pch_uart_ops = {
.tx_empty = pch_uart_tx_empty,
.set_mctrl = pch_uart_set_mctrl,
.get_mctrl = pch_uart_get_mctrl,
.stop_tx = pch_uart_stop_tx,
.start_tx = pch_uart_start_tx,
.stop_rx = pch_uart_stop_rx,
.enable_ms = pch_uart_enable_ms,
.break_ctl = pch_uart_break_ctl,
.startup = pch_uart_startup,
.shutdown = pch_uart_shutdown,
.set_termios = pch_uart_set_termios,
/* .pm = pch_uart_pm, Not supported yet */
.type = pch_uart_type,
.release_port = pch_uart_release_port,
.request_port = pch_uart_request_port,
.config_port = pch_uart_config_port,
.verify_port = pch_uart_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = pch_uart_get_poll_char,
.poll_put_char = pch_uart_put_poll_char,
#endif
};
#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
static void pch_console_putchar(struct uart_port *port, unsigned char ch)
{
struct eg20t_port *priv =
container_of(port, struct eg20t_port, port);
wait_for_xmitr(priv, UART_LSR_THRE);
iowrite8(ch, priv->membase + PCH_UART_THR);
}
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*
* The console_lock must be held when we get here.
*/
static void
pch_console_write(struct console *co, const char *s, unsigned int count)
{
struct eg20t_port *priv;
unsigned long flags;
int priv_locked = 1;
int port_locked = 1;
u8 ier;
priv = pch_uart_ports[co->index];
touch_nmi_watchdog();
local_irq_save(flags);
if (priv->port.sysrq) {
/* call to uart_handle_sysrq_char already took the priv lock */
priv_locked = 0;
/* serial8250_handle_port() already took the port lock */
port_locked = 0;
} else if (oops_in_progress) {
priv_locked = spin_trylock(&priv->lock);
port_locked = spin_trylock(&priv->port.lock);
} else {
spin_lock(&priv->lock);
spin_lock(&priv->port.lock);
}
/*
* First save the IER then disable the interrupts
*/
ier = ioread8(priv->membase + UART_IER);
pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
uart_console_write(&priv->port, s, count, pch_console_putchar);
/*
* Finally, wait for transmitter to become empty
* and restore the IER
*/
wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
iowrite8(ier, priv->membase + UART_IER);
if (port_locked)
spin_unlock(&priv->port.lock);
if (priv_locked)
spin_unlock(&priv->lock);
local_irq_restore(flags);
}
static int __init pch_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud = default_baud;
int bits = 8;
int parity = 'n';
int flow = 'n';
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= PCH_UART_NR)
co->index = 0;
port = &pch_uart_ports[co->index]->port;
if (!port || (!port->iobase && !port->membase))
return -ENODEV;
port->uartclk = pch_uart_get_uartclk();
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
return uart_set_options(port, co, baud, parity, bits, flow);
}
static struct uart_driver pch_uart_driver;
static struct console pch_console = {
.name = PCH_UART_DRIVER_DEVICE,
.write = pch_console_write,
.device = uart_console_device,
.setup = pch_console_setup,
.flags = CON_PRINTBUFFER | CON_ANYTIME,
.index = -1,
.data = &pch_uart_driver,
};
#define PCH_CONSOLE (&pch_console)
#else
#define PCH_CONSOLE NULL
#endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
static struct uart_driver pch_uart_driver = {
.owner = THIS_MODULE,
.driver_name = KBUILD_MODNAME,
.dev_name = PCH_UART_DRIVER_DEVICE,
.major = 0,
.minor = 0,
.nr = PCH_UART_NR,
.cons = PCH_CONSOLE,
};
static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct eg20t_port *priv;
int ret;
unsigned int iobase;
unsigned int mapbase;
unsigned char *rxbuf;
int fifosize;
int port_type;
struct pch_uart_driver_data *board;
char name[32];
board = &drv_dat[id->driver_data];
port_type = board->port_type;
priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
if (priv == NULL)
goto init_port_alloc_err;
rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
if (!rxbuf)
goto init_port_free_txbuf;
switch (port_type) {
case PORT_PCH_8LINE:
fifosize = 256; /* EG20T/ML7213: UART0 */
break;
case PORT_PCH_2LINE:
fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
break;
default:
dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
goto init_port_hal_free;
}
pci_enable_msi(pdev);
pci_set_master(pdev);
spin_lock_init(&priv->lock);
iobase = pci_resource_start(pdev, 0);
mapbase = pci_resource_start(pdev, 1);
priv->mapbase = mapbase;
priv->iobase = iobase;
priv->pdev = pdev;
priv->tx_empty = 1;
priv->rxbuf.buf = rxbuf;
priv->rxbuf.size = PAGE_SIZE;
priv->fifo_size = fifosize;
priv->uartclk = pch_uart_get_uartclk();
priv->port_type = port_type;
priv->port.dev = &pdev->dev;
priv->port.iobase = iobase;
priv->port.membase = NULL;
priv->port.mapbase = mapbase;
priv->port.irq = pdev->irq;
priv->port.iotype = UPIO_PORT;
priv->port.ops = &pch_uart_ops;
priv->port.flags = UPF_BOOT_AUTOCONF;
priv->port.fifosize = fifosize;
priv->port.line = board->line_no;
priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
priv->trigger = PCH_UART_HAL_TRIGGER_M;
snprintf(priv->irq_name, IRQ_NAME_SIZE,
KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
priv->port.line);
spin_lock_init(&priv->port.lock);
pci_set_drvdata(pdev, priv);
priv->trigger_level = 1;
priv->fcr = 0;
if (pdev->dev.of_node)
of_property_read_u32(pdev->dev.of_node, "clock-frequency"
, &user_uartclk);
#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
pch_uart_ports[board->line_no] = priv;
#endif
ret = uart_add_one_port(&pch_uart_driver, &priv->port);
if (ret < 0)
goto init_port_hal_free;
snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv,
&port_regs_ops);
return priv;
init_port_hal_free:
#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
pch_uart_ports[board->line_no] = NULL;
#endif
free_page((unsigned long)rxbuf);
init_port_free_txbuf:
kfree(priv);
init_port_alloc_err:
return NULL;
}
static void pch_uart_exit_port(struct eg20t_port *priv)
{
char name[32];
snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
debugfs_lookup_and_remove(name, NULL);
uart_remove_one_port(&pch_uart_driver, &priv->port);
free_page((unsigned long)priv->rxbuf.buf);
}
static void pch_uart_pci_remove(struct pci_dev *pdev)
{
struct eg20t_port *priv = pci_get_drvdata(pdev);
pci_disable_msi(pdev);
#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
pch_uart_ports[priv->port.line] = NULL;
#endif
pch_uart_exit_port(priv);
pci_disable_device(pdev);
kfree(priv);
return;
}
static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
{
struct eg20t_port *priv = dev_get_drvdata(dev);
uart_suspend_port(&pch_uart_driver, &priv->port);
return 0;
}
static int __maybe_unused pch_uart_pci_resume(struct device *dev)
{
struct eg20t_port *priv = dev_get_drvdata(dev);
uart_resume_port(&pch_uart_driver, &priv->port);
return 0;
}
static const struct pci_device_id pch_uart_pci_id[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
.driver_data = pch_et20t_uart0},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
.driver_data = pch_et20t_uart1},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
.driver_data = pch_et20t_uart2},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
.driver_data = pch_et20t_uart3},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
.driver_data = pch_ml7213_uart0},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
.driver_data = pch_ml7213_uart1},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
.driver_data = pch_ml7213_uart2},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
.driver_data = pch_ml7223_uart0},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
.driver_data = pch_ml7223_uart1},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
.driver_data = pch_ml7831_uart0},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
.driver_data = pch_ml7831_uart1},
{0,},
};
static int pch_uart_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
int ret;
struct eg20t_port *priv;
ret = pci_enable_device(pdev);
if (ret < 0)
goto probe_error;
priv = pch_uart_init_port(pdev, id);
if (!priv) {
ret = -EBUSY;
goto probe_disable_device;
}
pci_set_drvdata(pdev, priv);
return ret;
probe_disable_device:
pci_disable_msi(pdev);
pci_disable_device(pdev);
probe_error:
return ret;
}
static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
pch_uart_pci_suspend,
pch_uart_pci_resume);
static struct pci_driver pch_uart_pci_driver = {
.name = "pch_uart",
.id_table = pch_uart_pci_id,
.probe = pch_uart_pci_probe,
.remove = pch_uart_pci_remove,
.driver.pm = &pch_uart_pci_pm_ops,
};
static int __init pch_uart_module_init(void)
{
int ret;
/* register as UART driver */
ret = uart_register_driver(&pch_uart_driver);
if (ret < 0)
return ret;
/* register as PCI driver */
ret = pci_register_driver(&pch_uart_pci_driver);
if (ret < 0)
uart_unregister_driver(&pch_uart_driver);
return ret;
}
module_init(pch_uart_module_init);
static void __exit pch_uart_module_exit(void)
{
pci_unregister_driver(&pch_uart_pci_driver);
uart_unregister_driver(&pch_uart_driver);
}
module_exit(pch_uart_module_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
module_param(default_baud, uint, S_IRUGO);
MODULE_PARM_DESC(default_baud,
"Default BAUD for initial driver state and console (default 9600)");
module_param(user_uartclk, uint, S_IRUGO);
MODULE_PARM_DESC(user_uartclk,
"Override UART default or board specific UART clock");
| linux-master | drivers/tty/serial/pch_uart.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for AMBA serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
* Copyright (C) 2010 ST-Ericsson SA
*
* This is a generic driver for ARM AMBA-type serial ports. They
* have a lot of 16550-like features, but are not register compatible.
* Note that although they do have CTS, DCD and DSR inputs, they do
* not have an RI input, nor do they have DTR or RTS outputs. If
* required, these have to be supplied via some other means (eg, GPIO)
* and hooked into this driver.
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/sysrq.h>
#include <linux/device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/scatterlist.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/sizes.h>
#include <linux/io.h>
#include <linux/acpi.h>
#define UART_NR 14
#define SERIAL_AMBA_MAJOR 204
#define SERIAL_AMBA_MINOR 64
#define SERIAL_AMBA_NR UART_NR
#define AMBA_ISR_PASS_LIMIT 256
#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
#define UART_DUMMY_DR_RX (1 << 16)
enum {
REG_DR,
REG_ST_DMAWM,
REG_ST_TIMEOUT,
REG_FR,
REG_LCRH_RX,
REG_LCRH_TX,
REG_IBRD,
REG_FBRD,
REG_CR,
REG_IFLS,
REG_IMSC,
REG_RIS,
REG_MIS,
REG_ICR,
REG_DMACR,
REG_ST_XFCR,
REG_ST_XON1,
REG_ST_XON2,
REG_ST_XOFF1,
REG_ST_XOFF2,
REG_ST_ITCR,
REG_ST_ITIP,
REG_ST_ABCR,
REG_ST_ABIMSC,
/* The size of the array - must be last */
REG_ARRAY_SIZE,
};
static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
[REG_DR] = UART01x_DR,
[REG_FR] = UART01x_FR,
[REG_LCRH_RX] = UART011_LCRH,
[REG_LCRH_TX] = UART011_LCRH,
[REG_IBRD] = UART011_IBRD,
[REG_FBRD] = UART011_FBRD,
[REG_CR] = UART011_CR,
[REG_IFLS] = UART011_IFLS,
[REG_IMSC] = UART011_IMSC,
[REG_RIS] = UART011_RIS,
[REG_MIS] = UART011_MIS,
[REG_ICR] = UART011_ICR,
[REG_DMACR] = UART011_DMACR,
};
/* There is by now at least one vendor with differing details, so handle it */
struct vendor_data {
const u16 *reg_offset;
unsigned int ifls;
unsigned int fr_busy;
unsigned int fr_dsr;
unsigned int fr_cts;
unsigned int fr_ri;
unsigned int inv_fr;
bool access_32b;
bool oversampling;
bool dma_threshold;
bool cts_event_workaround;
bool always_enabled;
bool fixed_options;
unsigned int (*get_fifosize)(struct amba_device *dev);
};
static unsigned int get_fifosize_arm(struct amba_device *dev)
{
return amba_rev(dev) < 3 ? 16 : 32;
}
static struct vendor_data vendor_arm = {
.reg_offset = pl011_std_offsets,
.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
.fr_busy = UART01x_FR_BUSY,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
.always_enabled = false,
.fixed_options = false,
.get_fifosize = get_fifosize_arm,
};
static const struct vendor_data vendor_sbsa = {
.reg_offset = pl011_std_offsets,
.fr_busy = UART01x_FR_BUSY,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.access_32b = true,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
.always_enabled = true,
.fixed_options = true,
};
#ifdef CONFIG_ACPI_SPCR_TABLE
static const struct vendor_data vendor_qdt_qdf2400_e44 = {
.reg_offset = pl011_std_offsets,
.fr_busy = UART011_FR_TXFE,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.inv_fr = UART011_FR_TXFE,
.access_32b = true,
.oversampling = false,
.dma_threshold = false,
.cts_event_workaround = false,
.always_enabled = true,
.fixed_options = true,
};
#endif
static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
[REG_DR] = UART01x_DR,
[REG_ST_DMAWM] = ST_UART011_DMAWM,
[REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
[REG_FR] = UART01x_FR,
[REG_LCRH_RX] = ST_UART011_LCRH_RX,
[REG_LCRH_TX] = ST_UART011_LCRH_TX,
[REG_IBRD] = UART011_IBRD,
[REG_FBRD] = UART011_FBRD,
[REG_CR] = UART011_CR,
[REG_IFLS] = UART011_IFLS,
[REG_IMSC] = UART011_IMSC,
[REG_RIS] = UART011_RIS,
[REG_MIS] = UART011_MIS,
[REG_ICR] = UART011_ICR,
[REG_DMACR] = UART011_DMACR,
[REG_ST_XFCR] = ST_UART011_XFCR,
[REG_ST_XON1] = ST_UART011_XON1,
[REG_ST_XON2] = ST_UART011_XON2,
[REG_ST_XOFF1] = ST_UART011_XOFF1,
[REG_ST_XOFF2] = ST_UART011_XOFF2,
[REG_ST_ITCR] = ST_UART011_ITCR,
[REG_ST_ITIP] = ST_UART011_ITIP,
[REG_ST_ABCR] = ST_UART011_ABCR,
[REG_ST_ABIMSC] = ST_UART011_ABIMSC,
};
static unsigned int get_fifosize_st(struct amba_device *dev)
{
return 64;
}
static struct vendor_data vendor_st = {
.reg_offset = pl011_st_offsets,
.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
.fr_busy = UART01x_FR_BUSY,
.fr_dsr = UART01x_FR_DSR,
.fr_cts = UART01x_FR_CTS,
.fr_ri = UART011_FR_RI,
.oversampling = true,
.dma_threshold = true,
.cts_event_workaround = true,
.always_enabled = false,
.fixed_options = false,
.get_fifosize = get_fifosize_st,
};
/* Deals with DMA transactions */
struct pl011_sgbuf {
struct scatterlist sg;
char *buf;
};
struct pl011_dmarx_data {
struct dma_chan *chan;
struct completion complete;
bool use_buf_b;
struct pl011_sgbuf sgbuf_a;
struct pl011_sgbuf sgbuf_b;
dma_cookie_t cookie;
bool running;
struct timer_list timer;
unsigned int last_residue;
unsigned long last_jiffies;
bool auto_poll_rate;
unsigned int poll_rate;
unsigned int poll_timeout;
};
struct pl011_dmatx_data {
struct dma_chan *chan;
struct scatterlist sg;
char *buf;
bool queued;
};
/*
* We wrap our port structure around the generic uart_port.
*/
struct uart_amba_port {
struct uart_port port;
const u16 *reg_offset;
struct clk *clk;
const struct vendor_data *vendor;
unsigned int dmacr; /* dma control reg */
unsigned int im; /* interrupt mask */
unsigned int old_status;
unsigned int fifosize; /* vendor-specific */
unsigned int fixed_baud; /* vendor-set fixed baud rate */
char type[12];
bool rs485_tx_started;
unsigned int rs485_tx_drain_interval; /* usecs */
#ifdef CONFIG_DMA_ENGINE
/* DMA stuff */
bool using_tx_dma;
bool using_rx_dma;
struct pl011_dmarx_data dmarx;
struct pl011_dmatx_data dmatx;
bool dma_probed;
#endif
};
static unsigned int pl011_tx_empty(struct uart_port *port);
static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
unsigned int reg)
{
return uap->reg_offset[reg];
}
static unsigned int pl011_read(const struct uart_amba_port *uap,
unsigned int reg)
{
void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
return (uap->port.iotype == UPIO_MEM32) ?
readl_relaxed(addr) : readw_relaxed(addr);
}
static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
unsigned int reg)
{
void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
if (uap->port.iotype == UPIO_MEM32)
writel_relaxed(val, addr);
else
writew_relaxed(val, addr);
}
/*
* Reads up to 256 characters from the FIFO or until it's empty and
* inserts them into the TTY layer. Returns the number of characters
* read from the FIFO.
*/
static int pl011_fifo_to_tty(struct uart_amba_port *uap)
{
unsigned int ch, fifotaken;
int sysrq;
u16 status;
u8 flag;
for (fifotaken = 0; fifotaken != 256; fifotaken++) {
status = pl011_read(uap, REG_FR);
if (status & UART01x_FR_RXFE)
break;
/* Take chars from the FIFO and update status */
ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
flag = TTY_NORMAL;
uap->port.icount.rx++;
if (unlikely(ch & UART_DR_ERROR)) {
if (ch & UART011_DR_BE) {
ch &= ~(UART011_DR_FE | UART011_DR_PE);
uap->port.icount.brk++;
if (uart_handle_break(&uap->port))
continue;
} else if (ch & UART011_DR_PE)
uap->port.icount.parity++;
else if (ch & UART011_DR_FE)
uap->port.icount.frame++;
if (ch & UART011_DR_OE)
uap->port.icount.overrun++;
ch &= uap->port.read_status_mask;
if (ch & UART011_DR_BE)
flag = TTY_BREAK;
else if (ch & UART011_DR_PE)
flag = TTY_PARITY;
else if (ch & UART011_DR_FE)
flag = TTY_FRAME;
}
spin_unlock(&uap->port.lock);
sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
spin_lock(&uap->port.lock);
if (!sysrq)
uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
}
return fifotaken;
}
/*
* All the DMA operation mode stuff goes inside this ifdef.
* This assumes that you have a generic DMA device interface,
* no custom DMA interfaces are supported.
*/
#ifdef CONFIG_DMA_ENGINE
#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
enum dma_data_direction dir)
{
dma_addr_t dma_addr;
sg->buf = dma_alloc_coherent(chan->device->dev,
PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
if (!sg->buf)
return -ENOMEM;
sg_init_table(&sg->sg, 1);
sg_set_page(&sg->sg, phys_to_page(dma_addr),
PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
sg_dma_address(&sg->sg) = dma_addr;
sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
return 0;
}
static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
enum dma_data_direction dir)
{
if (sg->buf) {
dma_free_coherent(chan->device->dev,
PL011_DMA_BUFFER_SIZE, sg->buf,
sg_dma_address(&sg->sg));
}
}
static void pl011_dma_probe(struct uart_amba_port *uap)
{
/* DMA is the sole user of the platform data right now */
struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
struct device *dev = uap->port.dev;
struct dma_slave_config tx_conf = {
.dst_addr = uap->port.mapbase +
pl011_reg_to_offset(uap, REG_DR),
.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.direction = DMA_MEM_TO_DEV,
.dst_maxburst = uap->fifosize >> 1,
.device_fc = false,
};
struct dma_chan *chan;
dma_cap_mask_t mask;
uap->dma_probed = true;
chan = dma_request_chan(dev, "tx");
if (IS_ERR(chan)) {
if (PTR_ERR(chan) == -EPROBE_DEFER) {
uap->dma_probed = false;
return;
}
/* We need platform data */
if (!plat || !plat->dma_filter) {
dev_info(uap->port.dev, "no DMA platform data\n");
return;
}
/* Try to acquire a generic DMA engine slave TX channel */
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
chan = dma_request_channel(mask, plat->dma_filter,
plat->dma_tx_param);
if (!chan) {
dev_err(uap->port.dev, "no TX DMA channel!\n");
return;
}
}
dmaengine_slave_config(chan, &tx_conf);
uap->dmatx.chan = chan;
dev_info(uap->port.dev, "DMA channel TX %s\n",
dma_chan_name(uap->dmatx.chan));
/* Optionally make use of an RX channel as well */
chan = dma_request_slave_channel(dev, "rx");
if (!chan && plat && plat->dma_rx_param) {
chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
if (!chan) {
dev_err(uap->port.dev, "no RX DMA channel!\n");
return;
}
}
if (chan) {
struct dma_slave_config rx_conf = {
.src_addr = uap->port.mapbase +
pl011_reg_to_offset(uap, REG_DR),
.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.direction = DMA_DEV_TO_MEM,
.src_maxburst = uap->fifosize >> 2,
.device_fc = false,
};
struct dma_slave_caps caps;
/*
* Some DMA controllers provide information on their capabilities.
* If the controller does, check for suitable residue processing
* otherwise assime all is well.
*/
if (0 == dma_get_slave_caps(chan, &caps)) {
if (caps.residue_granularity ==
DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
dma_release_channel(chan);
dev_info(uap->port.dev,
"RX DMA disabled - no residue processing\n");
return;
}
}
dmaengine_slave_config(chan, &rx_conf);
uap->dmarx.chan = chan;
uap->dmarx.auto_poll_rate = false;
if (plat && plat->dma_rx_poll_enable) {
/* Set poll rate if specified. */
if (plat->dma_rx_poll_rate) {
uap->dmarx.auto_poll_rate = false;
uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
} else {
/*
* 100 ms defaults to poll rate if not
* specified. This will be adjusted with
* the baud rate at set_termios.
*/
uap->dmarx.auto_poll_rate = true;
uap->dmarx.poll_rate = 100;
}
/* 3 secs defaults poll_timeout if not specified. */
if (plat->dma_rx_poll_timeout)
uap->dmarx.poll_timeout =
plat->dma_rx_poll_timeout;
else
uap->dmarx.poll_timeout = 3000;
} else if (!plat && dev->of_node) {
uap->dmarx.auto_poll_rate = of_property_read_bool(
dev->of_node, "auto-poll");
if (uap->dmarx.auto_poll_rate) {
u32 x;
if (0 == of_property_read_u32(dev->of_node,
"poll-rate-ms", &x))
uap->dmarx.poll_rate = x;
else
uap->dmarx.poll_rate = 100;
if (0 == of_property_read_u32(dev->of_node,
"poll-timeout-ms", &x))
uap->dmarx.poll_timeout = x;
else
uap->dmarx.poll_timeout = 3000;
}
}
dev_info(uap->port.dev, "DMA channel RX %s\n",
dma_chan_name(uap->dmarx.chan));
}
}
static void pl011_dma_remove(struct uart_amba_port *uap)
{
if (uap->dmatx.chan)
dma_release_channel(uap->dmatx.chan);
if (uap->dmarx.chan)
dma_release_channel(uap->dmarx.chan);
}
/* Forward declare these for the refill routine */
static int pl011_dma_tx_refill(struct uart_amba_port *uap);
static void pl011_start_tx_pio(struct uart_amba_port *uap);
/*
* The current DMA TX buffer has been sent.
* Try to queue up another DMA buffer.
*/
static void pl011_dma_tx_callback(void *data)
{
struct uart_amba_port *uap = data;
struct pl011_dmatx_data *dmatx = &uap->dmatx;
unsigned long flags;
u16 dmacr;
spin_lock_irqsave(&uap->port.lock, flags);
if (uap->dmatx.queued)
dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
DMA_TO_DEVICE);
dmacr = uap->dmacr;
uap->dmacr = dmacr & ~UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
/*
* If TX DMA was disabled, it means that we've stopped the DMA for
* some reason (eg, XOFF received, or we want to send an X-char.)
*
* Note: we need to be careful here of a potential race between DMA
* and the rest of the driver - if the driver disables TX DMA while
* a TX buffer completing, we must update the tx queued status to
* get further refills (hence we check dmacr).
*/
if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
uart_circ_empty(&uap->port.state->xmit)) {
uap->dmatx.queued = false;
spin_unlock_irqrestore(&uap->port.lock, flags);
return;
}
if (pl011_dma_tx_refill(uap) <= 0)
/*
* We didn't queue a DMA buffer for some reason, but we
* have data pending to be sent. Re-enable the TX IRQ.
*/
pl011_start_tx_pio(uap);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
/*
* Try to refill the TX DMA buffer.
* Locking: called with port lock held and IRQs disabled.
* Returns:
* 1 if we queued up a TX DMA buffer.
* 0 if we didn't want to handle this by DMA
* <0 on error
*/
static int pl011_dma_tx_refill(struct uart_amba_port *uap)
{
struct pl011_dmatx_data *dmatx = &uap->dmatx;
struct dma_chan *chan = dmatx->chan;
struct dma_device *dma_dev = chan->device;
struct dma_async_tx_descriptor *desc;
struct circ_buf *xmit = &uap->port.state->xmit;
unsigned int count;
/*
* Try to avoid the overhead involved in using DMA if the
* transaction fits in the first half of the FIFO, by using
* the standard interrupt handling. This ensures that we
* issue a uart_write_wakeup() at the appropriate time.
*/
count = uart_circ_chars_pending(xmit);
if (count < (uap->fifosize >> 1)) {
uap->dmatx.queued = false;
return 0;
}
/*
* Bodge: don't send the last character by DMA, as this
* will prevent XON from notifying us to restart DMA.
*/
count -= 1;
/* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
if (count > PL011_DMA_BUFFER_SIZE)
count = PL011_DMA_BUFFER_SIZE;
if (xmit->tail < xmit->head)
memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
else {
size_t first = UART_XMIT_SIZE - xmit->tail;
size_t second;
if (first > count)
first = count;
second = count - first;
memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
if (second)
memcpy(&dmatx->buf[first], &xmit->buf[0], second);
}
dmatx->sg.length = count;
if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
uap->dmatx.queued = false;
dev_dbg(uap->port.dev, "unable to map TX DMA\n");
return -EBUSY;
}
desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
uap->dmatx.queued = false;
/*
* If DMA cannot be used right now, we complete this
* transaction via IRQ and let the TTY layer retry.
*/
dev_dbg(uap->port.dev, "TX DMA busy\n");
return -EBUSY;
}
/* Some data to go along to the callback */
desc->callback = pl011_dma_tx_callback;
desc->callback_param = uap;
/* All errors should happen at prepare time */
dmaengine_submit(desc);
/* Fire the DMA transaction */
dma_dev->device_issue_pending(chan);
uap->dmacr |= UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
uap->dmatx.queued = true;
/*
* Now we know that DMA will fire, so advance the ring buffer
* with the stuff we just dispatched.
*/
uart_xmit_advance(&uap->port, count);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
return 1;
}
/*
* We received a transmit interrupt without a pending X-char but with
* pending characters.
* Locking: called with port lock held and IRQs disabled.
* Returns:
* false if we want to use PIO to transmit
* true if we queued a DMA buffer
*/
static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
{
if (!uap->using_tx_dma)
return false;
/*
* If we already have a TX buffer queued, but received a
* TX interrupt, it will be because we've just sent an X-char.
* Ensure the TX DMA is enabled and the TX IRQ is disabled.
*/
if (uap->dmatx.queued) {
uap->dmacr |= UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
uap->im &= ~UART011_TXIM;
pl011_write(uap->im, uap, REG_IMSC);
return true;
}
/*
* We don't have a TX buffer queued, so try to queue one.
* If we successfully queued a buffer, mask the TX IRQ.
*/
if (pl011_dma_tx_refill(uap) > 0) {
uap->im &= ~UART011_TXIM;
pl011_write(uap->im, uap, REG_IMSC);
return true;
}
return false;
}
/*
* Stop the DMA transmit (eg, due to received XOFF).
* Locking: called with port lock held and IRQs disabled.
*/
static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
{
if (uap->dmatx.queued) {
uap->dmacr &= ~UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
}
}
/*
* Try to start a DMA transmit, or in the case of an XON/OFF
* character queued for send, try to get that character out ASAP.
* Locking: called with port lock held and IRQs disabled.
* Returns:
* false if we want the TX IRQ to be enabled
* true if we have a buffer queued
*/
static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
{
u16 dmacr;
if (!uap->using_tx_dma)
return false;
if (!uap->port.x_char) {
/* no X-char, try to push chars out in DMA mode */
bool ret = true;
if (!uap->dmatx.queued) {
if (pl011_dma_tx_refill(uap) > 0) {
uap->im &= ~UART011_TXIM;
pl011_write(uap->im, uap, REG_IMSC);
} else
ret = false;
} else if (!(uap->dmacr & UART011_TXDMAE)) {
uap->dmacr |= UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
}
return ret;
}
/*
* We have an X-char to send. Disable DMA to prevent it loading
* the TX fifo, and then see if we can stuff it into the FIFO.
*/
dmacr = uap->dmacr;
uap->dmacr &= ~UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
/*
* No space in the FIFO, so enable the transmit interrupt
* so we know when there is space. Note that once we've
* loaded the character, we should just re-enable DMA.
*/
return false;
}
pl011_write(uap->port.x_char, uap, REG_DR);
uap->port.icount.tx++;
uap->port.x_char = 0;
/* Success - restore the DMA state */
uap->dmacr = dmacr;
pl011_write(dmacr, uap, REG_DMACR);
return true;
}
/*
* Flush the transmit buffer.
* Locking: called with port lock held and IRQs disabled.
*/
static void pl011_dma_flush_buffer(struct uart_port *port)
__releases(&uap->port.lock)
__acquires(&uap->port.lock)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
if (!uap->using_tx_dma)
return;
dmaengine_terminate_async(uap->dmatx.chan);
if (uap->dmatx.queued) {
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
DMA_TO_DEVICE);
uap->dmatx.queued = false;
uap->dmacr &= ~UART011_TXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
}
}
static void pl011_dma_rx_callback(void *data);
static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
{
struct dma_chan *rxchan = uap->dmarx.chan;
struct pl011_dmarx_data *dmarx = &uap->dmarx;
struct dma_async_tx_descriptor *desc;
struct pl011_sgbuf *sgbuf;
if (!rxchan)
return -EIO;
/* Start the RX DMA job */
sgbuf = uap->dmarx.use_buf_b ?
&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
/*
* If the DMA engine is busy and cannot prepare a
* channel, no big deal, the driver will fall back
* to interrupt mode as a result of this error code.
*/
if (!desc) {
uap->dmarx.running = false;
dmaengine_terminate_all(rxchan);
return -EBUSY;
}
/* Some data to go along to the callback */
desc->callback = pl011_dma_rx_callback;
desc->callback_param = uap;
dmarx->cookie = dmaengine_submit(desc);
dma_async_issue_pending(rxchan);
uap->dmacr |= UART011_RXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
uap->dmarx.running = true;
uap->im &= ~UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
return 0;
}
/*
* This is called when either the DMA job is complete, or
* the FIFO timeout interrupt occurred. This must be called
* with the port spinlock uap->port.lock held.
*/
static void pl011_dma_rx_chars(struct uart_amba_port *uap,
u32 pending, bool use_buf_b,
bool readfifo)
{
struct tty_port *port = &uap->port.state->port;
struct pl011_sgbuf *sgbuf = use_buf_b ?
&uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
int dma_count = 0;
u32 fifotaken = 0; /* only used for vdbg() */
struct pl011_dmarx_data *dmarx = &uap->dmarx;
int dmataken = 0;
if (uap->dmarx.poll_rate) {
/* The data can be taken by polling */
dmataken = sgbuf->sg.length - dmarx->last_residue;
/* Recalculate the pending size */
if (pending >= dmataken)
pending -= dmataken;
}
/* Pick the remain data from the DMA */
if (pending) {
/*
* First take all chars in the DMA pipe, then look in the FIFO.
* Note that tty_insert_flip_buf() tries to take as many chars
* as it can.
*/
dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
pending);
uap->port.icount.rx += dma_count;
if (dma_count < pending)
dev_warn(uap->port.dev,
"couldn't insert all characters (TTY is full?)\n");
}
/* Reset the last_residue for Rx DMA poll */
if (uap->dmarx.poll_rate)
dmarx->last_residue = sgbuf->sg.length;
/*
* Only continue with trying to read the FIFO if all DMA chars have
* been taken first.
*/
if (dma_count == pending && readfifo) {
/* Clear any error flags */
pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
UART011_FEIS, uap, REG_ICR);
/*
* If we read all the DMA'd characters, and we had an
* incomplete buffer, that could be due to an rx error, or
* maybe we just timed out. Read any pending chars and check
* the error status.
*
* Error conditions will only occur in the FIFO, these will
* trigger an immediate interrupt and stop the DMA job, so we
* will always find the error in the FIFO, never in the DMA
* buffer.
*/
fifotaken = pl011_fifo_to_tty(uap);
}
dev_vdbg(uap->port.dev,
"Took %d chars from DMA buffer and %d chars from the FIFO\n",
dma_count, fifotaken);
tty_flip_buffer_push(port);
}
static void pl011_dma_rx_irq(struct uart_amba_port *uap)
{
struct pl011_dmarx_data *dmarx = &uap->dmarx;
struct dma_chan *rxchan = dmarx->chan;
struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
&dmarx->sgbuf_b : &dmarx->sgbuf_a;
size_t pending;
struct dma_tx_state state;
enum dma_status dmastat;
/*
* Pause the transfer so we can trust the current counter,
* do this before we pause the PL011 block, else we may
* overflow the FIFO.
*/
if (dmaengine_pause(rxchan))
dev_err(uap->port.dev, "unable to pause DMA transfer\n");
dmastat = rxchan->device->device_tx_status(rxchan,
dmarx->cookie, &state);
if (dmastat != DMA_PAUSED)
dev_err(uap->port.dev, "unable to pause DMA transfer\n");
/* Disable RX DMA - incoming data will wait in the FIFO */
uap->dmacr &= ~UART011_RXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
uap->dmarx.running = false;
pending = sgbuf->sg.length - state.residue;
BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
/* Then we terminate the transfer - we now know our residue */
dmaengine_terminate_all(rxchan);
/*
* This will take the chars we have so far and insert
* into the framework.
*/
pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
/* Switch buffer & re-trigger DMA job */
dmarx->use_buf_b = !dmarx->use_buf_b;
if (pl011_dma_rx_trigger_dma(uap)) {
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
"fall back to interrupt mode\n");
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
}
}
static void pl011_dma_rx_callback(void *data)
{
struct uart_amba_port *uap = data;
struct pl011_dmarx_data *dmarx = &uap->dmarx;
struct dma_chan *rxchan = dmarx->chan;
bool lastbuf = dmarx->use_buf_b;
struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
&dmarx->sgbuf_b : &dmarx->sgbuf_a;
size_t pending;
struct dma_tx_state state;
int ret;
/*
* This completion interrupt occurs typically when the
* RX buffer is totally stuffed but no timeout has yet
* occurred. When that happens, we just want the RX
* routine to flush out the secondary DMA buffer while
* we immediately trigger the next DMA job.
*/
spin_lock_irq(&uap->port.lock);
/*
* Rx data can be taken by the UART interrupts during
* the DMA irq handler. So we check the residue here.
*/
rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
pending = sgbuf->sg.length - state.residue;
BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
/* Then we terminate the transfer - we now know our residue */
dmaengine_terminate_all(rxchan);
uap->dmarx.running = false;
dmarx->use_buf_b = !lastbuf;
ret = pl011_dma_rx_trigger_dma(uap);
pl011_dma_rx_chars(uap, pending, lastbuf, false);
spin_unlock_irq(&uap->port.lock);
/*
* Do this check after we picked the DMA chars so we don't
* get some IRQ immediately from RX.
*/
if (ret) {
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
"fall back to interrupt mode\n");
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
}
}
/*
* Stop accepting received characters, when we're shutting down or
* suspending this port.
* Locking: called with port lock held and IRQs disabled.
*/
static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
{
if (!uap->using_rx_dma)
return;
/* FIXME. Just disable the DMA enable */
uap->dmacr &= ~UART011_RXDMAE;
pl011_write(uap->dmacr, uap, REG_DMACR);
}
/*
* Timer handler for Rx DMA polling.
* Every polling, It checks the residue in the dma buffer and transfer
* data to the tty. Also, last_residue is updated for the next polling.
*/
static void pl011_dma_rx_poll(struct timer_list *t)
{
struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
struct tty_port *port = &uap->port.state->port;
struct pl011_dmarx_data *dmarx = &uap->dmarx;
struct dma_chan *rxchan = uap->dmarx.chan;
unsigned long flags;
unsigned int dmataken = 0;
unsigned int size = 0;
struct pl011_sgbuf *sgbuf;
int dma_count;
struct dma_tx_state state;
sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
if (likely(state.residue < dmarx->last_residue)) {
dmataken = sgbuf->sg.length - dmarx->last_residue;
size = dmarx->last_residue - state.residue;
dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
size);
if (dma_count == size)
dmarx->last_residue = state.residue;
dmarx->last_jiffies = jiffies;
}
tty_flip_buffer_push(port);
/*
* If no data is received in poll_timeout, the driver will fall back
* to interrupt mode. We will retrigger DMA at the first interrupt.
*/
if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
> uap->dmarx.poll_timeout) {
spin_lock_irqsave(&uap->port.lock, flags);
pl011_dma_rx_stop(uap);
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
uap->dmarx.running = false;
dmaengine_terminate_all(rxchan);
del_timer(&uap->dmarx.timer);
} else {
mod_timer(&uap->dmarx.timer,
jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
}
}
static void pl011_dma_startup(struct uart_amba_port *uap)
{
int ret;
if (!uap->dma_probed)
pl011_dma_probe(uap);
if (!uap->dmatx.chan)
return;
uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
if (!uap->dmatx.buf) {
dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
uap->port.fifosize = uap->fifosize;
return;
}
sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
/* The DMA buffer is now the FIFO the TTY subsystem can use */
uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
uap->using_tx_dma = true;
if (!uap->dmarx.chan)
goto skip_rx;
/* Allocate and map DMA RX buffers */
ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
DMA_FROM_DEVICE);
if (ret) {
dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
"RX buffer A", ret);
goto skip_rx;
}
ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
DMA_FROM_DEVICE);
if (ret) {
dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
"RX buffer B", ret);
pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
DMA_FROM_DEVICE);
goto skip_rx;
}
uap->using_rx_dma = true;
skip_rx:
/* Turn on DMA error (RX/TX will be enabled on demand) */
uap->dmacr |= UART011_DMAONERR;
pl011_write(uap->dmacr, uap, REG_DMACR);
/*
* ST Micro variants has some specific dma burst threshold
* compensation. Set this to 16 bytes, so burst will only
* be issued above/below 16 bytes.
*/
if (uap->vendor->dma_threshold)
pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
uap, REG_ST_DMAWM);
if (uap->using_rx_dma) {
if (pl011_dma_rx_trigger_dma(uap))
dev_dbg(uap->port.dev, "could not trigger initial "
"RX DMA job, fall back to interrupt mode\n");
if (uap->dmarx.poll_rate) {
timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
mod_timer(&uap->dmarx.timer,
jiffies +
msecs_to_jiffies(uap->dmarx.poll_rate));
uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
uap->dmarx.last_jiffies = jiffies;
}
}
}
static void pl011_dma_shutdown(struct uart_amba_port *uap)
{
if (!(uap->using_tx_dma || uap->using_rx_dma))
return;
/* Disable RX and TX DMA */
while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
cpu_relax();
spin_lock_irq(&uap->port.lock);
uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
pl011_write(uap->dmacr, uap, REG_DMACR);
spin_unlock_irq(&uap->port.lock);
if (uap->using_tx_dma) {
/* In theory, this should already be done by pl011_dma_flush_buffer */
dmaengine_terminate_all(uap->dmatx.chan);
if (uap->dmatx.queued) {
dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
DMA_TO_DEVICE);
uap->dmatx.queued = false;
}
kfree(uap->dmatx.buf);
uap->using_tx_dma = false;
}
if (uap->using_rx_dma) {
dmaengine_terminate_all(uap->dmarx.chan);
/* Clean up the RX DMA */
pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
if (uap->dmarx.poll_rate)
del_timer_sync(&uap->dmarx.timer);
uap->using_rx_dma = false;
}
}
static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
{
return uap->using_rx_dma;
}
static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
{
return uap->using_rx_dma && uap->dmarx.running;
}
#else
/* Blank functions if the DMA engine is not available */
static inline void pl011_dma_remove(struct uart_amba_port *uap)
{
}
static inline void pl011_dma_startup(struct uart_amba_port *uap)
{
}
static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
{
}
static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
{
return false;
}
static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
{
}
static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
{
return false;
}
static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
{
}
static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
{
}
static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
{
return -EIO;
}
static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
{
return false;
}
static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
{
return false;
}
#define pl011_dma_flush_buffer NULL
#endif
static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
{
/*
* To be on the safe side only time out after twice as many iterations
* as fifo size.
*/
const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
struct uart_port *port = &uap->port;
int i = 0;
u32 cr;
/* Wait until hardware tx queue is empty */
while (!pl011_tx_empty(port)) {
if (i > MAX_TX_DRAIN_ITERS) {
dev_warn(port->dev,
"timeout while draining hardware tx queue\n");
break;
}
udelay(uap->rs485_tx_drain_interval);
i++;
}
if (port->rs485.delay_rts_after_send)
mdelay(port->rs485.delay_rts_after_send);
cr = pl011_read(uap, REG_CR);
if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
cr &= ~UART011_CR_RTS;
else
cr |= UART011_CR_RTS;
/* Disable the transmitter and reenable the transceiver */
cr &= ~UART011_CR_TXE;
cr |= UART011_CR_RXE;
pl011_write(cr, uap, REG_CR);
uap->rs485_tx_started = false;
}
static void pl011_stop_tx(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
uap->im &= ~UART011_TXIM;
pl011_write(uap->im, uap, REG_IMSC);
pl011_dma_tx_stop(uap);
if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
pl011_rs485_tx_stop(uap);
}
static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
/* Start TX with programmed I/O only (no DMA) */
static void pl011_start_tx_pio(struct uart_amba_port *uap)
{
if (pl011_tx_chars(uap, false)) {
uap->im |= UART011_TXIM;
pl011_write(uap->im, uap, REG_IMSC);
}
}
static void pl011_start_tx(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
if (!pl011_dma_tx_start(uap))
pl011_start_tx_pio(uap);
}
static void pl011_stop_rx(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
UART011_PEIM|UART011_BEIM|UART011_OEIM);
pl011_write(uap->im, uap, REG_IMSC);
pl011_dma_rx_stop(uap);
}
static void pl011_throttle_rx(struct uart_port *port)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
pl011_stop_rx(port);
spin_unlock_irqrestore(&port->lock, flags);
}
static void pl011_enable_ms(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
pl011_write(uap->im, uap, REG_IMSC);
}
static void pl011_rx_chars(struct uart_amba_port *uap)
__releases(&uap->port.lock)
__acquires(&uap->port.lock)
{
pl011_fifo_to_tty(uap);
spin_unlock(&uap->port.lock);
tty_flip_buffer_push(&uap->port.state->port);
/*
* If we were temporarily out of DMA mode for a while,
* attempt to switch back to DMA mode again.
*/
if (pl011_dma_rx_available(uap)) {
if (pl011_dma_rx_trigger_dma(uap)) {
dev_dbg(uap->port.dev, "could not trigger RX DMA job "
"fall back to interrupt mode again\n");
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
} else {
#ifdef CONFIG_DMA_ENGINE
/* Start Rx DMA poll */
if (uap->dmarx.poll_rate) {
uap->dmarx.last_jiffies = jiffies;
uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
mod_timer(&uap->dmarx.timer,
jiffies +
msecs_to_jiffies(uap->dmarx.poll_rate));
}
#endif
}
}
spin_lock(&uap->port.lock);
}
static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
bool from_irq)
{
if (unlikely(!from_irq) &&
pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
return false; /* unable to transmit character */
pl011_write(c, uap, REG_DR);
uap->port.icount.tx++;
return true;
}
static void pl011_rs485_tx_start(struct uart_amba_port *uap)
{
struct uart_port *port = &uap->port;
u32 cr;
/* Enable transmitter */
cr = pl011_read(uap, REG_CR);
cr |= UART011_CR_TXE;
/* Disable receiver if half-duplex */
if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
cr &= ~UART011_CR_RXE;
if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
cr &= ~UART011_CR_RTS;
else
cr |= UART011_CR_RTS;
pl011_write(cr, uap, REG_CR);
if (port->rs485.delay_rts_before_send)
mdelay(port->rs485.delay_rts_before_send);
uap->rs485_tx_started = true;
}
/* Returns true if tx interrupts have to be (kept) enabled */
static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
{
struct circ_buf *xmit = &uap->port.state->xmit;
int count = uap->fifosize >> 1;
if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
!uap->rs485_tx_started)
pl011_rs485_tx_start(uap);
if (uap->port.x_char) {
if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
return true;
uap->port.x_char = 0;
--count;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
pl011_stop_tx(&uap->port);
return false;
}
/* If we are using DMA mode, try to send some characters. */
if (pl011_dma_tx_irq(uap))
return true;
do {
if (likely(from_irq) && count-- == 0)
break;
if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
break;
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
} while (!uart_circ_empty(xmit));
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&uap->port);
if (uart_circ_empty(xmit)) {
pl011_stop_tx(&uap->port);
return false;
}
return true;
}
static void pl011_modem_status(struct uart_amba_port *uap)
{
unsigned int status, delta;
status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
delta = status ^ uap->old_status;
uap->old_status = status;
if (!delta)
return;
if (delta & UART01x_FR_DCD)
uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
if (delta & uap->vendor->fr_dsr)
uap->port.icount.dsr++;
if (delta & uap->vendor->fr_cts)
uart_handle_cts_change(&uap->port,
status & uap->vendor->fr_cts);
wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
}
static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
{
if (!uap->vendor->cts_event_workaround)
return;
/* workaround to make sure that all bits are unlocked.. */
pl011_write(0x00, uap, REG_ICR);
/*
* WA: introduce 26ns(1 uart clk) delay before W1C;
* single apb access will incur 2 pclk(133.12Mhz) delay,
* so add 2 dummy reads
*/
pl011_read(uap, REG_ICR);
pl011_read(uap, REG_ICR);
}
static irqreturn_t pl011_int(int irq, void *dev_id)
{
struct uart_amba_port *uap = dev_id;
unsigned long flags;
unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
int handled = 0;
spin_lock_irqsave(&uap->port.lock, flags);
status = pl011_read(uap, REG_RIS) & uap->im;
if (status) {
do {
check_apply_cts_event_workaround(uap);
pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
UART011_RXIS),
uap, REG_ICR);
if (status & (UART011_RTIS|UART011_RXIS)) {
if (pl011_dma_rx_running(uap))
pl011_dma_rx_irq(uap);
else
pl011_rx_chars(uap);
}
if (status & (UART011_DSRMIS|UART011_DCDMIS|
UART011_CTSMIS|UART011_RIMIS))
pl011_modem_status(uap);
if (status & UART011_TXIS)
pl011_tx_chars(uap, true);
if (pass_counter-- == 0)
break;
status = pl011_read(uap, REG_RIS) & uap->im;
} while (status != 0);
handled = 1;
}
spin_unlock_irqrestore(&uap->port.lock, flags);
return IRQ_RETVAL(handled);
}
static unsigned int pl011_tx_empty(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
/* Allow feature register bits to be inverted to work around errata */
unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
0 : TIOCSER_TEMT;
}
static unsigned int pl011_get_mctrl(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int result = 0;
unsigned int status = pl011_read(uap, REG_FR);
#define TIOCMBIT(uartbit, tiocmbit) \
if (status & uartbit) \
result |= tiocmbit
TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
#undef TIOCMBIT
return result;
}
static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int cr;
cr = pl011_read(uap, REG_CR);
#define TIOCMBIT(tiocmbit, uartbit) \
if (mctrl & tiocmbit) \
cr |= uartbit; \
else \
cr &= ~uartbit
TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
if (port->status & UPSTAT_AUTORTS) {
/* We need to disable auto-RTS if we want to turn RTS off */
TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
}
#undef TIOCMBIT
pl011_write(cr, uap, REG_CR);
}
static void pl011_break_ctl(struct uart_port *port, int break_state)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned long flags;
unsigned int lcr_h;
spin_lock_irqsave(&uap->port.lock, flags);
lcr_h = pl011_read(uap, REG_LCRH_TX);
if (break_state == -1)
lcr_h |= UART01x_LCRH_BRK;
else
lcr_h &= ~UART01x_LCRH_BRK;
pl011_write(lcr_h, uap, REG_LCRH_TX);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
#ifdef CONFIG_CONSOLE_POLL
static void pl011_quiesce_irqs(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
/*
* There is no way to clear TXIM as this is "ready to transmit IRQ", so
* we simply mask it. start_tx() will unmask it.
*
* Note we can race with start_tx(), and if the race happens, the
* polling user might get another interrupt just after we clear it.
* But it should be OK and can happen even w/o the race, e.g.
* controller immediately got some new data and raised the IRQ.
*
* And whoever uses polling routines assumes that it manages the device
* (including tx queue), so we're also fine with start_tx()'s caller
* side.
*/
pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
REG_IMSC);
}
static int pl011_get_poll_char(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int status;
/*
* The caller might need IRQs lowered, e.g. if used with KDB NMI
* debugger.
*/
pl011_quiesce_irqs(port);
status = pl011_read(uap, REG_FR);
if (status & UART01x_FR_RXFE)
return NO_POLL_CHAR;
return pl011_read(uap, REG_DR);
}
static void pl011_put_poll_char(struct uart_port *port,
unsigned char ch)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
cpu_relax();
pl011_write(ch, uap, REG_DR);
}
#endif /* CONFIG_CONSOLE_POLL */
static int pl011_hwinit(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
int retval;
/* Optionaly enable pins to be muxed in and configured */
pinctrl_pm_select_default_state(port->dev);
/*
* Try to enable the clock producer.
*/
retval = clk_prepare_enable(uap->clk);
if (retval)
return retval;
uap->port.uartclk = clk_get_rate(uap->clk);
/* Clear pending error and receive interrupts */
pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
UART011_FEIS | UART011_RTIS | UART011_RXIS,
uap, REG_ICR);
/*
* Save interrupts enable mask, and enable RX interrupts in case if
* the interrupt is used for NMI entry.
*/
uap->im = pl011_read(uap, REG_IMSC);
pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
if (dev_get_platdata(uap->port.dev)) {
struct amba_pl011_data *plat;
plat = dev_get_platdata(uap->port.dev);
if (plat->init)
plat->init();
}
return 0;
}
static bool pl011_split_lcrh(const struct uart_amba_port *uap)
{
return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
pl011_reg_to_offset(uap, REG_LCRH_TX);
}
static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
{
pl011_write(lcr_h, uap, REG_LCRH_RX);
if (pl011_split_lcrh(uap)) {
int i;
/*
* Wait 10 PCLKs before writing LCRH_TX register,
* to get this delay write read only register 10 times
*/
for (i = 0; i < 10; ++i)
pl011_write(0xff, uap, REG_MIS);
pl011_write(lcr_h, uap, REG_LCRH_TX);
}
}
static int pl011_allocate_irq(struct uart_amba_port *uap)
{
pl011_write(uap->im, uap, REG_IMSC);
return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
}
/*
* Enable interrupts, only timeouts when using DMA
* if initial RX DMA job failed, start in interrupt mode
* as well.
*/
static void pl011_enable_interrupts(struct uart_amba_port *uap)
{
unsigned long flags;
unsigned int i;
spin_lock_irqsave(&uap->port.lock, flags);
/* Clear out any spuriously appearing RX interrupts */
pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
/*
* RXIS is asserted only when the RX FIFO transitions from below
* to above the trigger threshold. If the RX FIFO is already
* full to the threshold this can't happen and RXIS will now be
* stuck off. Drain the RX FIFO explicitly to fix this:
*/
for (i = 0; i < uap->fifosize * 2; ++i) {
if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
break;
pl011_read(uap, REG_DR);
}
uap->im = UART011_RTIM;
if (!pl011_dma_rx_running(uap))
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
static void pl011_unthrottle_rx(struct uart_port *port)
{
struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
unsigned long flags;
spin_lock_irqsave(&uap->port.lock, flags);
uap->im = UART011_RTIM;
if (!pl011_dma_rx_running(uap))
uap->im |= UART011_RXIM;
pl011_write(uap->im, uap, REG_IMSC);
spin_unlock_irqrestore(&uap->port.lock, flags);
}
static int pl011_startup(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int cr;
int retval;
retval = pl011_hwinit(port);
if (retval)
goto clk_dis;
retval = pl011_allocate_irq(uap);
if (retval)
goto clk_dis;
pl011_write(uap->vendor->ifls, uap, REG_IFLS);
spin_lock_irq(&uap->port.lock);
cr = pl011_read(uap, REG_CR);
cr &= UART011_CR_RTS | UART011_CR_DTR;
cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
if (!(port->rs485.flags & SER_RS485_ENABLED))
cr |= UART011_CR_TXE;
pl011_write(cr, uap, REG_CR);
spin_unlock_irq(&uap->port.lock);
/*
* initialise the old status of the modem signals
*/
uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
/* Startup DMA */
pl011_dma_startup(uap);
pl011_enable_interrupts(uap);
return 0;
clk_dis:
clk_disable_unprepare(uap->clk);
return retval;
}
static int sbsa_uart_startup(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
int retval;
retval = pl011_hwinit(port);
if (retval)
return retval;
retval = pl011_allocate_irq(uap);
if (retval)
return retval;
/* The SBSA UART does not support any modem status lines. */
uap->old_status = 0;
pl011_enable_interrupts(uap);
return 0;
}
static void pl011_shutdown_channel(struct uart_amba_port *uap,
unsigned int lcrh)
{
unsigned long val;
val = pl011_read(uap, lcrh);
val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
pl011_write(val, uap, lcrh);
}
/*
* disable the port. It should not disable RTS and DTR.
* Also RTS and DTR state should be preserved to restore
* it during startup().
*/
static void pl011_disable_uart(struct uart_amba_port *uap)
{
unsigned int cr;
uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
spin_lock_irq(&uap->port.lock);
cr = pl011_read(uap, REG_CR);
cr &= UART011_CR_RTS | UART011_CR_DTR;
cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
pl011_write(cr, uap, REG_CR);
spin_unlock_irq(&uap->port.lock);
/*
* disable break condition and fifos
*/
pl011_shutdown_channel(uap, REG_LCRH_RX);
if (pl011_split_lcrh(uap))
pl011_shutdown_channel(uap, REG_LCRH_TX);
}
static void pl011_disable_interrupts(struct uart_amba_port *uap)
{
spin_lock_irq(&uap->port.lock);
/* mask all interrupts and clear all pending ones */
uap->im = 0;
pl011_write(uap->im, uap, REG_IMSC);
pl011_write(0xffff, uap, REG_ICR);
spin_unlock_irq(&uap->port.lock);
}
static void pl011_shutdown(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
pl011_disable_interrupts(uap);
pl011_dma_shutdown(uap);
if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
pl011_rs485_tx_stop(uap);
free_irq(uap->port.irq, uap);
pl011_disable_uart(uap);
/*
* Shut down the clock producer
*/
clk_disable_unprepare(uap->clk);
/* Optionally let pins go into sleep states */
pinctrl_pm_select_sleep_state(port->dev);
if (dev_get_platdata(uap->port.dev)) {
struct amba_pl011_data *plat;
plat = dev_get_platdata(uap->port.dev);
if (plat->exit)
plat->exit();
}
if (uap->port.ops->flush_buffer)
uap->port.ops->flush_buffer(port);
}
static void sbsa_uart_shutdown(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
pl011_disable_interrupts(uap);
free_irq(uap->port.irq, uap);
if (uap->port.ops->flush_buffer)
uap->port.ops->flush_buffer(port);
}
static void
pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
{
port->read_status_mask = UART011_DR_OE | 255;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
port->read_status_mask |= UART011_DR_BE;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= UART011_DR_BE;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= UART011_DR_OE;
}
/*
* Ignore all characters if CREAD is not set.
*/
if ((termios->c_cflag & CREAD) == 0)
port->ignore_status_mask |= UART_DUMMY_DR_RX;
}
static void
pl011_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned int lcr_h, old_cr;
unsigned long flags;
unsigned int baud, quot, clkdiv;
unsigned int bits;
if (uap->vendor->oversampling)
clkdiv = 8;
else
clkdiv = 16;
/*
* Ask the core to calculate the divisor for us.
*/
baud = uart_get_baud_rate(port, termios, old, 0,
port->uartclk / clkdiv);
#ifdef CONFIG_DMA_ENGINE
/*
* Adjust RX DMA polling rate with baud rate if not specified.
*/
if (uap->dmarx.auto_poll_rate)
uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
#endif
if (baud > port->uartclk/16)
quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
else
quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
switch (termios->c_cflag & CSIZE) {
case CS5:
lcr_h = UART01x_LCRH_WLEN_5;
break;
case CS6:
lcr_h = UART01x_LCRH_WLEN_6;
break;
case CS7:
lcr_h = UART01x_LCRH_WLEN_7;
break;
default: // CS8
lcr_h = UART01x_LCRH_WLEN_8;
break;
}
if (termios->c_cflag & CSTOPB)
lcr_h |= UART01x_LCRH_STP2;
if (termios->c_cflag & PARENB) {
lcr_h |= UART01x_LCRH_PEN;
if (!(termios->c_cflag & PARODD))
lcr_h |= UART01x_LCRH_EPS;
if (termios->c_cflag & CMSPAR)
lcr_h |= UART011_LCRH_SPS;
}
if (uap->fifosize > 1)
lcr_h |= UART01x_LCRH_FEN;
bits = tty_get_frame_size(termios->c_cflag);
spin_lock_irqsave(&port->lock, flags);
/*
* Update the per-port timeout.
*/
uart_update_timeout(port, termios->c_cflag, baud);
/*
* Calculate the approximated time it takes to transmit one character
* with the given baud rate. We use this as the poll interval when we
* wait for the tx queue to empty.
*/
uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
pl011_setup_status_masks(port, termios);
if (UART_ENABLE_MS(port, termios->c_cflag))
pl011_enable_ms(port);
if (port->rs485.flags & SER_RS485_ENABLED)
termios->c_cflag &= ~CRTSCTS;
old_cr = pl011_read(uap, REG_CR);
if (termios->c_cflag & CRTSCTS) {
if (old_cr & UART011_CR_RTS)
old_cr |= UART011_CR_RTSEN;
old_cr |= UART011_CR_CTSEN;
port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
} else {
old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
}
if (uap->vendor->oversampling) {
if (baud > port->uartclk / 16)
old_cr |= ST_UART011_CR_OVSFACT;
else
old_cr &= ~ST_UART011_CR_OVSFACT;
}
/*
* Workaround for the ST Micro oversampling variants to
* increase the bitrate slightly, by lowering the divisor,
* to avoid delayed sampling of start bit at high speeds,
* else we see data corruption.
*/
if (uap->vendor->oversampling) {
if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
quot -= 1;
else if ((baud > 3250000) && (quot > 2))
quot -= 2;
}
/* Set baud rate */
pl011_write(quot & 0x3f, uap, REG_FBRD);
pl011_write(quot >> 6, uap, REG_IBRD);
/*
* ----------v----------v----------v----------v-----
* NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
* REG_FBRD & REG_IBRD.
* ----------^----------^----------^----------^-----
*/
pl011_write_lcr_h(uap, lcr_h);
/*
* Receive was disabled by pl011_disable_uart during shutdown.
* Need to reenable receive if you need to use a tty_driver
* returns from tty_find_polling_driver() after a port shutdown.
*/
old_cr |= UART011_CR_RXE;
pl011_write(old_cr, uap, REG_CR);
spin_unlock_irqrestore(&port->lock, flags);
}
static void
sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
unsigned long flags;
tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
/* The SBSA UART only supports 8n1 without hardware flow control. */
termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
termios->c_cflag &= ~(CMSPAR | CRTSCTS);
termios->c_cflag |= CS8 | CLOCAL;
spin_lock_irqsave(&port->lock, flags);
uart_update_timeout(port, CS8, uap->fixed_baud);
pl011_setup_status_masks(port, termios);
spin_unlock_irqrestore(&port->lock, flags);
}
static const char *pl011_type(struct uart_port *port)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
return uap->port.type == PORT_AMBA ? uap->type : NULL;
}
/*
* Configure/autoconfigure the port.
*/
static void pl011_config_port(struct uart_port *port, int flags)
{
if (flags & UART_CONFIG_TYPE)
port->type = PORT_AMBA;
}
/*
* verify the new serial_struct (for TIOCSSERIAL).
*/
static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
{
int ret = 0;
if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
ret = -EINVAL;
if (ser->irq < 0 || ser->irq >= nr_irqs)
ret = -EINVAL;
if (ser->baud_base < 9600)
ret = -EINVAL;
if (port->mapbase != (unsigned long) ser->iomem_base)
ret = -EINVAL;
return ret;
}
static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
if (port->rs485.flags & SER_RS485_ENABLED)
pl011_rs485_tx_stop(uap);
/* Make sure auto RTS is disabled */
if (rs485->flags & SER_RS485_ENABLED) {
u32 cr = pl011_read(uap, REG_CR);
cr &= ~UART011_CR_RTSEN;
pl011_write(cr, uap, REG_CR);
port->status &= ~UPSTAT_AUTORTS;
}
return 0;
}
static const struct uart_ops amba_pl011_pops = {
.tx_empty = pl011_tx_empty,
.set_mctrl = pl011_set_mctrl,
.get_mctrl = pl011_get_mctrl,
.stop_tx = pl011_stop_tx,
.start_tx = pl011_start_tx,
.stop_rx = pl011_stop_rx,
.throttle = pl011_throttle_rx,
.unthrottle = pl011_unthrottle_rx,
.enable_ms = pl011_enable_ms,
.break_ctl = pl011_break_ctl,
.startup = pl011_startup,
.shutdown = pl011_shutdown,
.flush_buffer = pl011_dma_flush_buffer,
.set_termios = pl011_set_termios,
.type = pl011_type,
.config_port = pl011_config_port,
.verify_port = pl011_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_init = pl011_hwinit,
.poll_get_char = pl011_get_poll_char,
.poll_put_char = pl011_put_poll_char,
#endif
};
static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}
static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
{
return 0;
}
static const struct uart_ops sbsa_uart_pops = {
.tx_empty = pl011_tx_empty,
.set_mctrl = sbsa_uart_set_mctrl,
.get_mctrl = sbsa_uart_get_mctrl,
.stop_tx = pl011_stop_tx,
.start_tx = pl011_start_tx,
.stop_rx = pl011_stop_rx,
.startup = sbsa_uart_startup,
.shutdown = sbsa_uart_shutdown,
.set_termios = sbsa_uart_set_termios,
.type = pl011_type,
.config_port = pl011_config_port,
.verify_port = pl011_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_init = pl011_hwinit,
.poll_get_char = pl011_get_poll_char,
.poll_put_char = pl011_put_poll_char,
#endif
};
static struct uart_amba_port *amba_ports[UART_NR];
#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
{
struct uart_amba_port *uap =
container_of(port, struct uart_amba_port, port);
while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
cpu_relax();
pl011_write(ch, uap, REG_DR);
}
static void
pl011_console_write(struct console *co, const char *s, unsigned int count)
{
struct uart_amba_port *uap = amba_ports[co->index];
unsigned int old_cr = 0, new_cr;
unsigned long flags;
int locked = 1;
clk_enable(uap->clk);
local_irq_save(flags);
if (uap->port.sysrq)
locked = 0;
else if (oops_in_progress)
locked = spin_trylock(&uap->port.lock);
else
spin_lock(&uap->port.lock);
/*
* First save the CR then disable the interrupts
*/
if (!uap->vendor->always_enabled) {
old_cr = pl011_read(uap, REG_CR);
new_cr = old_cr & ~UART011_CR_CTSEN;
new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
pl011_write(new_cr, uap, REG_CR);
}
uart_console_write(&uap->port, s, count, pl011_console_putchar);
/*
* Finally, wait for transmitter to become empty and restore the
* TCR. Allow feature register bits to be inverted to work around
* errata.
*/
while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
& uap->vendor->fr_busy)
cpu_relax();
if (!uap->vendor->always_enabled)
pl011_write(old_cr, uap, REG_CR);
if (locked)
spin_unlock(&uap->port.lock);
local_irq_restore(flags);
clk_disable(uap->clk);
}
static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
int *parity, int *bits)
{
if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
unsigned int lcr_h, ibrd, fbrd;
lcr_h = pl011_read(uap, REG_LCRH_TX);
*parity = 'n';
if (lcr_h & UART01x_LCRH_PEN) {
if (lcr_h & UART01x_LCRH_EPS)
*parity = 'e';
else
*parity = 'o';
}
if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
*bits = 7;
else
*bits = 8;
ibrd = pl011_read(uap, REG_IBRD);
fbrd = pl011_read(uap, REG_FBRD);
*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
if (uap->vendor->oversampling) {
if (pl011_read(uap, REG_CR)
& ST_UART011_CR_OVSFACT)
*baud *= 2;
}
}
}
static int pl011_console_setup(struct console *co, char *options)
{
struct uart_amba_port *uap;
int baud = 38400;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= UART_NR)
co->index = 0;
uap = amba_ports[co->index];
if (!uap)
return -ENODEV;
/* Allow pins to be muxed in and configured */
pinctrl_pm_select_default_state(uap->port.dev);
ret = clk_prepare(uap->clk);
if (ret)
return ret;
if (dev_get_platdata(uap->port.dev)) {
struct amba_pl011_data *plat;
plat = dev_get_platdata(uap->port.dev);
if (plat->init)
plat->init();
}
uap->port.uartclk = clk_get_rate(uap->clk);
if (uap->vendor->fixed_options) {
baud = uap->fixed_baud;
} else {
if (options)
uart_parse_options(options,
&baud, &parity, &bits, &flow);
else
pl011_console_get_options(uap, &baud, &parity, &bits);
}
return uart_set_options(&uap->port, co, baud, parity, bits, flow);
}
/**
* pl011_console_match - non-standard console matching
* @co: registering console
* @name: name from console command line
* @idx: index from console command line
* @options: ptr to option string from console command line
*
* Only attempts to match console command lines of the form:
* console=pl011,mmio|mmio32,<addr>[,<options>]
* console=pl011,0x<addr>[,<options>]
* This form is used to register an initial earlycon boot console and
* replace it with the amba_console at pl011 driver init.
*
* Performs console setup for a match (as required by interface)
* If no <options> are specified, then assume the h/w is already setup.
*
* Returns 0 if console matches; otherwise non-zero to use default matching
*/
static int pl011_console_match(struct console *co, char *name, int idx,
char *options)
{
unsigned char iotype;
resource_size_t addr;
int i;
/*
* Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
* have a distinct console name, so make sure we check for that.
* The actual implementation of the erratum occurs in the probe
* function.
*/
if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
return -ENODEV;
if (uart_parse_earlycon(options, &iotype, &addr, &options))
return -ENODEV;
if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
return -ENODEV;
/* try to match the port specified on the command line */
for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
struct uart_port *port;
if (!amba_ports[i])
continue;
port = &amba_ports[i]->port;
if (port->mapbase != addr)
continue;
co->index = i;
port->cons = co;
return pl011_console_setup(co, options);
}
return -ENODEV;
}
static struct uart_driver amba_reg;
static struct console amba_console = {
.name = "ttyAMA",
.write = pl011_console_write,
.device = uart_console_device,
.setup = pl011_console_setup,
.match = pl011_console_match,
.flags = CON_PRINTBUFFER | CON_ANYTIME,
.index = -1,
.data = &amba_reg,
};
#define AMBA_CONSOLE (&amba_console)
static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
{
while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
cpu_relax();
writel(c, port->membase + UART01x_DR);
while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
cpu_relax();
}
static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
}
static void pl011_putc(struct uart_port *port, unsigned char c)
{
while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
cpu_relax();
if (port->iotype == UPIO_MEM32)
writel(c, port->membase + UART01x_DR);
else
writeb(c, port->membase + UART01x_DR);
while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
cpu_relax();
}
static void pl011_early_write(struct console *con, const char *s, unsigned n)
{
struct earlycon_device *dev = con->data;
uart_console_write(&dev->port, s, n, pl011_putc);
}
#ifdef CONFIG_CONSOLE_POLL
static int pl011_getc(struct uart_port *port)
{
if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
return NO_POLL_CHAR;
if (port->iotype == UPIO_MEM32)
return readl(port->membase + UART01x_DR);
else
return readb(port->membase + UART01x_DR);
}
static int pl011_early_read(struct console *con, char *s, unsigned int n)
{
struct earlycon_device *dev = con->data;
int ch, num_read = 0;
while (num_read < n) {
ch = pl011_getc(&dev->port);
if (ch == NO_POLL_CHAR)
break;
s[num_read++] = ch;
}
return num_read;
}
#else
#define pl011_early_read NULL
#endif
/*
* On non-ACPI systems, earlycon is enabled by specifying
* "earlycon=pl011,<address>" on the kernel command line.
*
* On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
* by specifying only "earlycon" on the command line. Because it requires
* SPCR, the console starts after ACPI is parsed, which is later than a
* traditional early console.
*
* To get the traditional early console that starts before ACPI is parsed,
* specify the full "earlycon=pl011,<address>" option.
*/
static int __init pl011_early_console_setup(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = pl011_early_write;
device->con->read = pl011_early_read;
return 0;
}
OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
/*
* On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
* Erratum 44, traditional earlycon can be enabled by specifying
* "earlycon=qdf2400_e44,<address>". Any options are ignored.
*
* Alternatively, you can just specify "earlycon", and the early console
* will be enabled with the information from the SPCR table. In this
* case, the SPCR code will detect the need for the E44 work-around,
* and set the console name to "qdf2400_e44".
*/
static int __init
qdf2400_e44_early_console_setup(struct earlycon_device *device,
const char *opt)
{
if (!device->port.membase)
return -ENODEV;
device->con->write = qdf2400_e44_early_write;
return 0;
}
EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
#else
#define AMBA_CONSOLE NULL
#endif
static struct uart_driver amba_reg = {
.owner = THIS_MODULE,
.driver_name = "ttyAMA",
.dev_name = "ttyAMA",
.major = SERIAL_AMBA_MAJOR,
.minor = SERIAL_AMBA_MINOR,
.nr = UART_NR,
.cons = AMBA_CONSOLE,
};
static int pl011_probe_dt_alias(int index, struct device *dev)
{
struct device_node *np;
static bool seen_dev_with_alias = false;
static bool seen_dev_without_alias = false;
int ret = index;
if (!IS_ENABLED(CONFIG_OF))
return ret;
np = dev->of_node;
if (!np)
return ret;
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
seen_dev_without_alias = true;
ret = index;
} else {
seen_dev_with_alias = true;
if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
dev_warn(dev, "requested serial port %d not available.\n", ret);
ret = index;
}
}
if (seen_dev_with_alias && seen_dev_without_alias)
dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
return ret;
}
/* unregisters the driver also if no more ports are left */
static void pl011_unregister_port(struct uart_amba_port *uap)
{
int i;
bool busy = false;
for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
if (amba_ports[i] == uap)
amba_ports[i] = NULL;
else if (amba_ports[i])
busy = true;
}
pl011_dma_remove(uap);
if (!busy)
uart_unregister_driver(&amba_reg);
}
static int pl011_find_free_port(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
if (amba_ports[i] == NULL)
return i;
return -EBUSY;
}
static int pl011_get_rs485_mode(struct uart_amba_port *uap)
{
struct uart_port *port = &uap->port;
int ret;
ret = uart_get_rs485_mode(port);
if (ret)
return ret;
return 0;
}
static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
struct resource *mmiobase, int index)
{
void __iomem *base;
int ret;
base = devm_ioremap_resource(dev, mmiobase);
if (IS_ERR(base))
return PTR_ERR(base);
index = pl011_probe_dt_alias(index, dev);
uap->port.dev = dev;
uap->port.mapbase = mmiobase->start;
uap->port.membase = base;
uap->port.fifosize = uap->fifosize;
uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
uap->port.flags = UPF_BOOT_AUTOCONF;
uap->port.line = index;
ret = pl011_get_rs485_mode(uap);
if (ret)
return ret;
amba_ports[index] = uap;
return 0;
}
static int pl011_register_port(struct uart_amba_port *uap)
{
int ret, i;
/* Ensure interrupts from this UART are masked and cleared */
pl011_write(0, uap, REG_IMSC);
pl011_write(0xffff, uap, REG_ICR);
if (!amba_reg.state) {
ret = uart_register_driver(&amba_reg);
if (ret < 0) {
dev_err(uap->port.dev,
"Failed to register AMBA-PL011 driver\n");
for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
if (amba_ports[i] == uap)
amba_ports[i] = NULL;
return ret;
}
}
ret = uart_add_one_port(&amba_reg, &uap->port);
if (ret)
pl011_unregister_port(uap);
return ret;
}
static const struct serial_rs485 pl011_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
SER_RS485_RX_DURING_TX,
.delay_rts_before_send = 1,
.delay_rts_after_send = 1,
};
static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
{
struct uart_amba_port *uap;
struct vendor_data *vendor = id->data;
int portnr, ret;
u32 val;
portnr = pl011_find_free_port();
if (portnr < 0)
return portnr;
uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
GFP_KERNEL);
if (!uap)
return -ENOMEM;
uap->clk = devm_clk_get(&dev->dev, NULL);
if (IS_ERR(uap->clk))
return PTR_ERR(uap->clk);
uap->reg_offset = vendor->reg_offset;
uap->vendor = vendor;
uap->fifosize = vendor->get_fifosize(dev);
uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
uap->port.irq = dev->irq[0];
uap->port.ops = &amba_pl011_pops;
uap->port.rs485_config = pl011_rs485_config;
uap->port.rs485_supported = pl011_rs485_supported;
snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
switch (val) {
case 1:
uap->port.iotype = UPIO_MEM;
break;
case 4:
uap->port.iotype = UPIO_MEM32;
break;
default:
dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
val);
return -EINVAL;
}
}
ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
if (ret)
return ret;
amba_set_drvdata(dev, uap);
return pl011_register_port(uap);
}
static void pl011_remove(struct amba_device *dev)
{
struct uart_amba_port *uap = amba_get_drvdata(dev);
uart_remove_one_port(&amba_reg, &uap->port);
pl011_unregister_port(uap);
}
#ifdef CONFIG_PM_SLEEP
static int pl011_suspend(struct device *dev)
{
struct uart_amba_port *uap = dev_get_drvdata(dev);
if (!uap)
return -EINVAL;
return uart_suspend_port(&amba_reg, &uap->port);
}
static int pl011_resume(struct device *dev)
{
struct uart_amba_port *uap = dev_get_drvdata(dev);
if (!uap)
return -EINVAL;
return uart_resume_port(&amba_reg, &uap->port);
}
#endif
static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
static int sbsa_uart_probe(struct platform_device *pdev)
{
struct uart_amba_port *uap;
struct resource *r;
int portnr, ret;
int baudrate;
/*
* Check the mandatory baud rate parameter in the DT node early
* so that we can easily exit with the error.
*/
if (pdev->dev.of_node) {
struct device_node *np = pdev->dev.of_node;
ret = of_property_read_u32(np, "current-speed", &baudrate);
if (ret)
return ret;
} else {
baudrate = 115200;
}
portnr = pl011_find_free_port();
if (portnr < 0)
return portnr;
uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
GFP_KERNEL);
if (!uap)
return -ENOMEM;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
uap->port.irq = ret;
#ifdef CONFIG_ACPI_SPCR_TABLE
if (qdf2400_e44_present) {
dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
uap->vendor = &vendor_qdt_qdf2400_e44;
} else
#endif
uap->vendor = &vendor_sbsa;
uap->reg_offset = uap->vendor->reg_offset;
uap->fifosize = 32;
uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
uap->port.ops = &sbsa_uart_pops;
uap->fixed_baud = baudrate;
snprintf(uap->type, sizeof(uap->type), "SBSA");
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
if (ret)
return ret;
platform_set_drvdata(pdev, uap);
return pl011_register_port(uap);
}
static int sbsa_uart_remove(struct platform_device *pdev)
{
struct uart_amba_port *uap = platform_get_drvdata(pdev);
uart_remove_one_port(&amba_reg, &uap->port);
pl011_unregister_port(uap);
return 0;
}
static const struct of_device_id sbsa_uart_of_match[] = {
{ .compatible = "arm,sbsa-uart", },
{},
};
MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
{ "ARMH0011", 0 },
{ "ARMHB000", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
static struct platform_driver arm_sbsa_uart_platform_driver = {
.probe = sbsa_uart_probe,
.remove = sbsa_uart_remove,
.driver = {
.name = "sbsa-uart",
.pm = &pl011_dev_pm_ops,
.of_match_table = of_match_ptr(sbsa_uart_of_match),
.acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
},
};
static const struct amba_id pl011_ids[] = {
{
.id = 0x00041011,
.mask = 0x000fffff,
.data = &vendor_arm,
},
{
.id = 0x00380802,
.mask = 0x00ffffff,
.data = &vendor_st,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl011_ids);
static struct amba_driver pl011_driver = {
.drv = {
.name = "uart-pl011",
.pm = &pl011_dev_pm_ops,
.suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
},
.id_table = pl011_ids,
.probe = pl011_probe,
.remove = pl011_remove,
};
static int __init pl011_init(void)
{
printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
if (platform_driver_register(&arm_sbsa_uart_platform_driver))
pr_warn("could not register SBSA UART platform driver\n");
return amba_driver_register(&pl011_driver);
}
static void __exit pl011_exit(void)
{
platform_driver_unregister(&arm_sbsa_uart_platform_driver);
amba_driver_unregister(&pl011_driver);
}
/*
* While this can be a module, if builtin it's most likely the console
* So let's leave module_exit but move module_init to an earlier place
*/
arch_initcall(pl011_init);
module_exit(pl011_exit);
MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
MODULE_DESCRIPTION("ARM AMBA serial port driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/amba-pl011.c |
// SPDX-License-Identifier: GPL-2.0+
/* Synopsys DesignWare 8250 library. */
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/math.h>
#include <linux/property.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include "8250_dwlib.h"
/* Offsets for the DesignWare specific registers */
#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
#define DW_UART_RAR 0xc4 /* Receive Address Register */
#define DW_UART_TAR 0xc8 /* Transmit Address Register */
#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
#define DW_UART_CPR 0xf4 /* Component Parameter Register */
#define DW_UART_UCV 0xf8 /* UART Component Version */
/* Receive / Transmit Address Register bits */
#define DW_UART_ADDR_MASK GENMASK(7, 0)
/* Line Status Register bits */
#define DW_UART_LSR_ADDR_RCVD BIT(8)
/* Transceiver Control Register bits */
#define DW_UART_TCR_RS485_EN BIT(0)
#define DW_UART_TCR_RE_POL BIT(1)
#define DW_UART_TCR_DE_POL BIT(2)
#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
/* Line Extended Control Register bits */
#define DW_UART_LCR_EXT_DLS_E BIT(0)
#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
/* Component Parameter Register bits */
#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
#define DW_UART_CPR_AFCE_MODE BIT(4)
#define DW_UART_CPR_THRE_MODE BIT(5)
#define DW_UART_CPR_SIR_MODE BIT(6)
#define DW_UART_CPR_SIR_LP_MODE BIT(7)
#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
#define DW_UART_CPR_FIFO_ACCESS BIT(9)
#define DW_UART_CPR_FIFO_STAT BIT(10)
#define DW_UART_CPR_SHADOW BIT(11)
#define DW_UART_CPR_ENCODED_PARMS BIT(12)
#define DW_UART_CPR_DMA_EXTRA BIT(13)
#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
/* Helper for FIFO size calculation */
#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
/*
* divisor = div(I) + div(F)
* "I" means integer, "F" means fractional
* quot = div(I) = clk / (16 * baud)
* frac = div(F) * 2^dlf_size
*
* let rem = clk % (16 * baud)
* we have: div(F) * (16 * baud) = rem
* so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
*/
static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud,
unsigned int *frac)
{
unsigned int quot, rem, base_baud = baud * 16;
struct dw8250_port_data *d = p->private_data;
quot = p->uartclk / base_baud;
rem = p->uartclk % base_baud;
*frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
return quot;
}
static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
unsigned int quot, unsigned int quot_frac)
{
dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
serial8250_do_set_divisor(p, baud, quot, quot_frac);
}
void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios,
const struct ktermios *old)
{
p->status &= ~UPSTAT_AUTOCTS;
if (termios->c_cflag & CRTSCTS)
p->status |= UPSTAT_AUTOCTS;
serial8250_do_set_termios(p, termios, old);
/* Filter addresses which have 9th bit set */
p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD;
p->read_status_mask |= DW_UART_LSR_ADDR_RCVD;
}
EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
/*
* Wait until re is de-asserted for sure. An ongoing receive will keep
* re asserted until end of frame. Without BUSY indication available,
* only available course of action is to wait for the time it takes to
* receive one frame (there might nothing to receive but w/o BUSY the
* driver cannot know).
*/
static void dw8250_wait_re_deassert(struct uart_port *p)
{
ndelay(p->frame_time);
}
static void dw8250_update_rar(struct uart_port *p, u32 addr)
{
u32 re_en = dw8250_readl_ext(p, DW_UART_RE_EN);
/*
* RAR shouldn't be changed while receiving. Thus, de-assert RE_EN
* if asserted and wait.
*/
if (re_en)
dw8250_writel_ext(p, DW_UART_RE_EN, 0);
dw8250_wait_re_deassert(p);
dw8250_writel_ext(p, DW_UART_RAR, addr);
if (re_en)
dw8250_writel_ext(p, DW_UART_RE_EN, re_en);
}
static void dw8250_rs485_set_addr(struct uart_port *p, struct serial_rs485 *rs485,
struct ktermios *termios)
{
u32 lcr = dw8250_readl_ext(p, DW_UART_LCR_EXT);
if (rs485->flags & SER_RS485_ADDRB) {
lcr |= DW_UART_LCR_EXT_DLS_E;
if (termios)
termios->c_cflag |= ADDRB;
if (rs485->flags & SER_RS485_ADDR_RECV) {
u32 delta = p->rs485.flags ^ rs485->flags;
/*
* rs485 (param) is equal to uart_port's rs485 only during init
* (during init, delta is not yet applicable).
*/
if (unlikely(&p->rs485 == rs485))
delta = rs485->flags;
if ((delta & SER_RS485_ADDR_RECV) ||
(p->rs485.addr_recv != rs485->addr_recv))
dw8250_update_rar(p, rs485->addr_recv);
lcr |= DW_UART_LCR_EXT_ADDR_MATCH;
} else {
lcr &= ~DW_UART_LCR_EXT_ADDR_MATCH;
}
if (rs485->flags & SER_RS485_ADDR_DEST) {
/*
* Don't skip writes here as another endpoint could
* have changed communication line's destination
* address in between.
*/
dw8250_writel_ext(p, DW_UART_TAR, rs485->addr_dest);
lcr |= DW_UART_LCR_EXT_SEND_ADDR;
}
} else {
lcr = 0;
}
dw8250_writel_ext(p, DW_UART_LCR_EXT, lcr);
}
static int dw8250_rs485_config(struct uart_port *p, struct ktermios *termios,
struct serial_rs485 *rs485)
{
u32 tcr;
tcr = dw8250_readl_ext(p, DW_UART_TCR);
tcr &= ~DW_UART_TCR_XFER_MODE;
if (rs485->flags & SER_RS485_ENABLED) {
tcr |= DW_UART_TCR_RS485_EN;
if (rs485->flags & SER_RS485_RX_DURING_TX)
tcr |= DW_UART_TCR_XFER_MODE_DE_DURING_RE;
else
tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE;
dw8250_writel_ext(p, DW_UART_DE_EN, 1);
dw8250_writel_ext(p, DW_UART_RE_EN, 1);
} else {
if (termios)
termios->c_cflag &= ~ADDRB;
tcr &= ~DW_UART_TCR_RS485_EN;
}
/* Reset to default polarity */
tcr |= DW_UART_TCR_DE_POL;
tcr &= ~DW_UART_TCR_RE_POL;
if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
tcr &= ~DW_UART_TCR_DE_POL;
if (device_property_read_bool(p->dev, "rs485-rx-active-high"))
tcr |= DW_UART_TCR_RE_POL;
dw8250_writel_ext(p, DW_UART_TCR, tcr);
/* Addressing mode can only be set up after TCR */
if (rs485->flags & SER_RS485_ENABLED)
dw8250_rs485_set_addr(p, rs485, termios);
return 0;
}
/*
* Tests if RE_EN register can have non-zero value to see if RS-485 HW support
* is present.
*/
static bool dw8250_detect_rs485_hw(struct uart_port *p)
{
u32 reg;
dw8250_writel_ext(p, DW_UART_RE_EN, 1);
reg = dw8250_readl_ext(p, DW_UART_RE_EN);
dw8250_writel_ext(p, DW_UART_RE_EN, 0);
return reg;
}
static const struct serial_rs485 dw8250_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_RTS_ON_SEND |
SER_RS485_RTS_AFTER_SEND | SER_RS485_ADDRB | SER_RS485_ADDR_RECV |
SER_RS485_ADDR_DEST,
};
void dw8250_setup_port(struct uart_port *p)
{
struct dw8250_port_data *pd = p->private_data;
struct dw8250_data *data = to_dw8250_data(pd);
struct uart_8250_port *up = up_to_u8250p(p);
u32 reg, old_dlf;
pd->hw_rs485_support = dw8250_detect_rs485_hw(p);
if (pd->hw_rs485_support) {
p->rs485_config = dw8250_rs485_config;
up->lsr_save_mask = LSR_SAVE_FLAGS | DW_UART_LSR_ADDR_RCVD;
p->rs485_supported = dw8250_rs485_supported;
} else {
p->rs485_config = serial8250_em485_config;
p->rs485_supported = serial8250_em485_supported;
up->rs485_start_tx = serial8250_em485_start_tx;
up->rs485_stop_tx = serial8250_em485_stop_tx;
}
up->capabilities |= UART_CAP_NOTEMT;
/*
* If the Component Version Register returns zero, we know that
* ADDITIONAL_FEATURES are not enabled. No need to go any further.
*/
reg = dw8250_readl_ext(p, DW_UART_UCV);
if (!reg)
return;
dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
/* Preserve value written by firmware or bootloader */
old_dlf = dw8250_readl_ext(p, DW_UART_DLF);
dw8250_writel_ext(p, DW_UART_DLF, ~0U);
reg = dw8250_readl_ext(p, DW_UART_DLF);
dw8250_writel_ext(p, DW_UART_DLF, old_dlf);
if (reg) {
pd->dlf_size = fls(reg);
p->get_divisor = dw8250_get_divisor;
p->set_divisor = dw8250_set_divisor;
}
reg = dw8250_readl_ext(p, DW_UART_CPR);
if (!reg) {
reg = data->pdata->cpr_val;
dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
}
if (!reg)
return;
/* Select the type based on FIFO */
if (reg & DW_UART_CPR_FIFO_MODE) {
p->type = PORT_16550A;
p->flags |= UPF_FIXED_TYPE;
p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;
}
if (reg & DW_UART_CPR_AFCE_MODE)
up->capabilities |= UART_CAP_AFE;
if (reg & DW_UART_CPR_SIR_MODE)
up->capabilities |= UART_CAP_IRDA;
}
EXPORT_SYMBOL_GPL(dw8250_setup_port);
| linux-master | drivers/tty/serial/8250/8250_dwlib.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
* Based on 8250_boca.
*
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include "8250.h"
static struct plat_serial8250_port exar_data[] = {
SERIAL8250_PORT(0x100, 5),
SERIAL8250_PORT(0x108, 5),
SERIAL8250_PORT(0x110, 5),
SERIAL8250_PORT(0x118, 5),
{ },
};
static struct platform_device exar_device = {
.name = "serial8250",
.id = PLAT8250_DEV_EXAR_ST16C554,
.dev = {
.platform_data = exar_data,
},
};
static int __init exar_init(void)
{
return platform_device_register(&exar_device);
}
module_init(exar_init);
MODULE_AUTHOR("Paul B Schroeder");
MODULE_DESCRIPTION("8250 serial probe module for Exar cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_exar_st16c554.c |
// SPDX-License-Identifier: GPL-2.0+
#include <asm/machvec.h>
#include "8250.h"
bool alpha_jensen(void)
{
return !strcmp(alpha_mv.vector_name, "Jensen");
}
void alpha_jensen_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
/*
* Digital did something really horribly wrong with the OUT1 and OUT2
* lines on Alpha Jensen. The failure mode is that if either is
* cleared, the machine locks up with endless interrupts.
*/
mctrl |= TIOCM_OUT1 | TIOCM_OUT2;
serial8250_do_set_mctrl(port, mctrl);
}
| linux-master | drivers/tty/serial/8250/8250_alpha.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include "8250.h"
#define SERIAL8250_FOURPORT(_base, _irq) \
SERIAL8250_PORT_FLAGS(_base, _irq, UPF_FOURPORT)
static struct plat_serial8250_port fourport_data[] = {
SERIAL8250_FOURPORT(0x1a0, 9),
SERIAL8250_FOURPORT(0x1a8, 9),
SERIAL8250_FOURPORT(0x1b0, 9),
SERIAL8250_FOURPORT(0x1b8, 9),
SERIAL8250_FOURPORT(0x2a0, 5),
SERIAL8250_FOURPORT(0x2a8, 5),
SERIAL8250_FOURPORT(0x2b0, 5),
SERIAL8250_FOURPORT(0x2b8, 5),
{ },
};
static struct platform_device fourport_device = {
.name = "serial8250",
.id = PLAT8250_DEV_FOURPORT,
.dev = {
.platform_data = fourport_data,
},
};
static int __init fourport_init(void)
{
return platform_device_register(&fourport_device);
}
module_init(fourport_init);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("8250 serial probe module for AST Fourport cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_fourport.c |
// SPDX-License-Identifier: (GPL-2.0 OR MPL-1.1)
/*======================================================================
A driver for PCMCIA serial devices
serial_cs.c 1.134 2002/05/04 05:48:53
The contents of this file are subject to the Mozilla Public
License Version 1.1 (the "License"); you may not use this file
except in compliance with the License. You may obtain a copy of
the License at http://www.mozilla.org/MPL/
Software distributed under the License is distributed on an "AS
IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
implied. See the License for the specific language governing
rights and limitations under the License.
The initial developer of the original code is David A. Hinds
<[email protected]>. Portions created by David A. Hinds
are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
Alternatively, the contents of this file may be used under the
terms of the GNU General Public License version 2 (the "GPL"), in which
case the provisions of the GPL are applicable instead of the
above. If you wish to allow the use of your version of this file
only under the terms of the GPL and not to allow others to use
your version of this file under the MPL, indicate your decision
by deleting the provisions above and replace them with the notice
and other provisions required by the GPL. If you do not delete
the provisions above, a recipient may use your version of this
file under either the MPL or the GPL.
======================================================================*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/major.h>
#include <asm/io.h>
#include <pcmcia/cistpl.h>
#include <pcmcia/ciscode.h>
#include <pcmcia/ds.h>
#include <pcmcia/cisreg.h>
#include "8250.h"
/*====================================================================*/
/* Parameters that can be set with 'insmod' */
/* Enable the speaker? */
static int do_sound = 1;
/* Skip strict UART tests? */
static int buggy_uart;
module_param(do_sound, int, 0444);
module_param(buggy_uart, int, 0444);
/*====================================================================*/
/* Table of multi-port card ID's */
struct serial_quirk {
unsigned int manfid;
unsigned int prodid;
int multi; /* 1 = multifunction, > 1 = # ports */
void (*config)(struct pcmcia_device *);
void (*setup)(struct pcmcia_device *, struct uart_8250_port *);
void (*wakeup)(struct pcmcia_device *);
int (*post)(struct pcmcia_device *);
};
struct serial_info {
struct pcmcia_device *p_dev;
int ndev;
int multi;
int slave;
int manfid;
int prodid;
int c950ctrl;
int line[4];
const struct serial_quirk *quirk;
};
struct serial_cfg_mem {
tuple_t tuple;
cisparse_t parse;
u_char buf[256];
};
/*
* vers_1 5.0, "Brain Boxes", "2-Port RS232 card", "r6"
* manfid 0x0160, 0x0104
* This card appears to have a 14.7456MHz clock.
*/
/* Generic Modem: MD55x (GPRS/EDGE) have
* Elan VPU16551 UART with 14.7456MHz oscillator
* manfid 0x015D, 0x4C45
*/
static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_8250_port *uart)
{
uart->port.uartclk = 14745600;
}
static int quirk_post_ibm(struct pcmcia_device *link)
{
u8 val;
int ret;
ret = pcmcia_read_config_byte(link, 0x800, &val);
if (ret)
goto failed;
ret = pcmcia_write_config_byte(link, 0x800, val | 1);
if (ret)
goto failed;
return 0;
failed:
return -ENODEV;
}
/*
* Nokia cards are not really multiport cards. Shouldn't this
* be handled by setting the quirk entry .multi = 0 | 1 ?
*/
static void quirk_config_nokia(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
if (info->multi > 1)
info->multi = 1;
}
static void quirk_wakeup_oxsemi(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
if (info->c950ctrl)
outb(12, info->c950ctrl + 1);
}
/* request_region? oxsemi branch does no request_region too... */
/*
* This sequence is needed to properly initialize MC45 attached to OXCF950.
* I tried decreasing these msleep()s, but it worked properly (survived
* 1000 stop/start operations) with these timeouts (or bigger).
*/
static void quirk_wakeup_possio_gcc(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
unsigned int ctrl = info->c950ctrl;
outb(0xA, ctrl + 1);
msleep(100);
outb(0xE, ctrl + 1);
msleep(300);
outb(0xC, ctrl + 1);
msleep(100);
outb(0xE, ctrl + 1);
msleep(200);
outb(0xF, ctrl + 1);
msleep(100);
outb(0xE, ctrl + 1);
msleep(100);
outb(0xC, ctrl + 1);
}
/*
* Socket Dual IO: this enables irq's for second port
*/
static void quirk_config_socket(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
if (info->multi)
link->config_flags |= CONF_ENABLE_ESR;
}
static const struct serial_quirk quirks[] = {
{
.manfid = 0x0160,
.prodid = 0x0104,
.multi = -1,
.setup = quirk_setup_brainboxes_0104,
}, {
.manfid = 0x015D,
.prodid = 0x4C45,
.multi = -1,
.setup = quirk_setup_brainboxes_0104,
}, {
.manfid = MANFID_IBM,
.prodid = ~0,
.multi = -1,
.post = quirk_post_ibm,
}, {
.manfid = MANFID_INTEL,
.prodid = PRODID_INTEL_DUAL_RS232,
.multi = 2,
}, {
.manfid = MANFID_NATINST,
.prodid = PRODID_NATINST_QUAD_RS232,
.multi = 4,
}, {
.manfid = MANFID_NOKIA,
.prodid = ~0,
.multi = -1,
.config = quirk_config_nokia,
}, {
.manfid = MANFID_OMEGA,
.prodid = PRODID_OMEGA_QSP_100,
.multi = 4,
}, {
.manfid = MANFID_OXSEMI,
.prodid = ~0,
.multi = -1,
.wakeup = quirk_wakeup_oxsemi,
}, {
.manfid = MANFID_POSSIO,
.prodid = PRODID_POSSIO_GCC,
.multi = -1,
.wakeup = quirk_wakeup_possio_gcc,
}, {
.manfid = MANFID_QUATECH,
.prodid = PRODID_QUATECH_DUAL_RS232,
.multi = 2,
}, {
.manfid = MANFID_QUATECH,
.prodid = PRODID_QUATECH_DUAL_RS232_D1,
.multi = 2,
}, {
.manfid = MANFID_QUATECH,
.prodid = PRODID_QUATECH_DUAL_RS232_G,
.multi = 2,
}, {
.manfid = MANFID_QUATECH,
.prodid = PRODID_QUATECH_QUAD_RS232,
.multi = 4,
}, {
.manfid = MANFID_SOCKET,
.prodid = PRODID_SOCKET_DUAL_RS232,
.multi = 2,
.config = quirk_config_socket,
}, {
.manfid = MANFID_SOCKET,
.prodid = ~0,
.multi = -1,
.config = quirk_config_socket,
}
};
static int serial_config(struct pcmcia_device *link);
static void serial_remove(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
int i;
dev_dbg(&link->dev, "serial_release\n");
/*
* Recheck to see if the device is still configured.
*/
for (i = 0; i < info->ndev; i++)
serial8250_unregister_port(info->line[i]);
if (!info->slave)
pcmcia_disable_device(link);
}
static int serial_suspend(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
int i;
for (i = 0; i < info->ndev; i++)
serial8250_suspend_port(info->line[i]);
return 0;
}
static int serial_resume(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
int i;
for (i = 0; i < info->ndev; i++)
serial8250_resume_port(info->line[i]);
if (info->quirk && info->quirk->wakeup)
info->quirk->wakeup(link);
return 0;
}
static int serial_probe(struct pcmcia_device *link)
{
struct serial_info *info;
int ret;
dev_dbg(&link->dev, "serial_attach()\n");
/* Create new serial device */
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->p_dev = link;
link->priv = info;
link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
if (do_sound)
link->config_flags |= CONF_ENABLE_SPKR;
ret = serial_config(link);
if (ret)
goto free_info;
return 0;
free_info:
kfree(info);
return ret;
}
static void serial_detach(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
dev_dbg(&link->dev, "serial_detach\n");
/*
* Ensure that the ports have been released.
*/
serial_remove(link);
/* free bits */
kfree(info);
}
/*====================================================================*/
static int setup_serial(struct pcmcia_device *handle, struct serial_info *info,
unsigned int iobase, int irq)
{
struct uart_8250_port uart;
int line;
memset(&uart, 0, sizeof(uart));
uart.port.iobase = iobase;
uart.port.irq = irq;
uart.port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
uart.port.uartclk = 1843200;
uart.port.dev = &handle->dev;
if (buggy_uart)
uart.port.flags |= UPF_BUGGY_UART;
if (info->quirk && info->quirk->setup)
info->quirk->setup(handle, &uart);
line = serial8250_register_8250_port(&uart);
if (line < 0) {
pr_err("serial_cs: serial8250_register_8250_port() at 0x%04lx, irq %d failed\n",
(unsigned long)iobase, irq);
return -EINVAL;
}
info->line[info->ndev] = line;
info->ndev++;
return 0;
}
/*====================================================================*/
static int pfc_config(struct pcmcia_device *p_dev)
{
unsigned int port = 0;
struct serial_info *info = p_dev->priv;
if ((p_dev->resource[1]->end != 0) &&
(resource_size(p_dev->resource[1]) == 8)) {
port = p_dev->resource[1]->start;
info->slave = 1;
} else if ((info->manfid == MANFID_OSITECH) &&
(resource_size(p_dev->resource[0]) == 0x40)) {
port = p_dev->resource[0]->start + 0x28;
info->slave = 1;
}
if (info->slave)
return setup_serial(p_dev, info, port, p_dev->irq);
dev_warn(&p_dev->dev, "no usable port range found, giving up\n");
return -ENODEV;
}
static int simple_config_check(struct pcmcia_device *p_dev, void *priv_data)
{
static const int size_table[2] = { 8, 16 };
int *try = priv_data;
if (p_dev->resource[0]->start == 0)
return -ENODEV;
if ((*try & 0x1) == 0)
p_dev->io_lines = 16;
if (p_dev->resource[0]->end != size_table[(*try >> 1)])
return -ENODEV;
p_dev->resource[0]->end = 8;
p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
return pcmcia_request_io(p_dev);
}
static int simple_config_check_notpicky(struct pcmcia_device *p_dev,
void *priv_data)
{
static const unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
int j;
if (p_dev->io_lines > 3)
return -ENODEV;
p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
p_dev->resource[0]->end = 8;
for (j = 0; j < 5; j++) {
p_dev->resource[0]->start = base[j];
p_dev->io_lines = base[j] ? 16 : 3;
if (!pcmcia_request_io(p_dev))
return 0;
}
return -ENODEV;
}
static int simple_config(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
int ret, try;
/*
* First pass: look for a config entry that looks normal.
* Two tries: without IO aliases, then with aliases.
*/
link->config_flags |= CONF_AUTO_SET_VPP;
for (try = 0; try < 4; try++)
if (!pcmcia_loop_config(link, simple_config_check, &try))
goto found_port;
/*
* Second pass: try to find an entry that isn't picky about
* its base address, then try to grab any standard serial port
* address, and finally try to get any free port.
*/
ret = pcmcia_loop_config(link, simple_config_check_notpicky, NULL);
if (ret) {
dev_warn(&link->dev, "no usable port range found, giving up\n");
return ret;
}
found_port:
if (info->multi && (info->manfid == MANFID_3COM))
link->config_index &= ~(0x08);
/*
* Apply any configuration quirks.
*/
if (info->quirk && info->quirk->config)
info->quirk->config(link);
ret = pcmcia_enable_device(link);
if (ret != 0)
return ret;
return setup_serial(link, info, link->resource[0]->start, link->irq);
}
static int multi_config_check(struct pcmcia_device *p_dev, void *priv_data)
{
int *multi = priv_data;
if (p_dev->resource[1]->end)
return -EINVAL;
/*
* The quad port cards have bad CIS's, so just look for a
* window larger than 8 ports and assume it will be right.
*/
if (p_dev->resource[0]->end <= 8)
return -EINVAL;
p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
p_dev->resource[0]->end = *multi * 8;
if (pcmcia_request_io(p_dev))
return -ENODEV;
return 0;
}
static int multi_config_check_notpicky(struct pcmcia_device *p_dev,
void *priv_data)
{
int *base2 = priv_data;
if (!p_dev->resource[0]->end || !p_dev->resource[1]->end ||
p_dev->resource[0]->start + 8 != p_dev->resource[1]->start)
return -ENODEV;
p_dev->resource[0]->end = p_dev->resource[1]->end = 8;
p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
if (pcmcia_request_io(p_dev))
return -ENODEV;
*base2 = p_dev->resource[0]->start + 8;
return 0;
}
static int multi_config(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
int i, base2 = 0;
/* First, look for a generic full-sized window */
if (!pcmcia_loop_config(link, multi_config_check, &info->multi))
base2 = link->resource[0]->start + 8;
else {
/* If that didn't work, look for two windows */
info->multi = 2;
if (pcmcia_loop_config(link, multi_config_check_notpicky,
&base2)) {
dev_warn(&link->dev,
"no usable port range found, giving up\n");
return -ENODEV;
}
}
if (!link->irq)
dev_warn(&link->dev, "no usable IRQ found, continuing...\n");
/*
* Apply any configuration quirks.
*/
if (info->quirk && info->quirk->config)
info->quirk->config(link);
i = pcmcia_enable_device(link);
if (i != 0)
return -ENODEV;
/* The Oxford Semiconductor OXCF950 cards are in fact single-port:
* 8 registers are for the UART, the others are extra registers.
* Siemen's MC45 PCMCIA (Possio's GCC) is OXCF950 based too.
*/
if (info->manfid == MANFID_OXSEMI || (info->manfid == MANFID_POSSIO &&
info->prodid == PRODID_POSSIO_GCC)) {
if (link->config_index == 1 ||
link->config_index == 3) {
setup_serial(link, info, base2, link->irq);
base2 = link->resource[0]->start;
} else {
setup_serial(link, info, link->resource[0]->start,
link->irq);
}
info->c950ctrl = base2;
/*
* FIXME: We really should wake up the port prior to
* handing it over to the serial layer.
*/
if (info->quirk && info->quirk->wakeup)
info->quirk->wakeup(link);
return 0;
}
setup_serial(link, info, link->resource[0]->start, link->irq);
for (i = 0; i < info->multi - 1; i++)
setup_serial(link, info, base2 + (8 * i),
link->irq);
return 0;
}
static int serial_check_for_multi(struct pcmcia_device *p_dev, void *priv_data)
{
struct serial_info *info = p_dev->priv;
if (!p_dev->resource[0]->end)
return -EINVAL;
if ((!p_dev->resource[1]->end) && (p_dev->resource[0]->end % 8 == 0))
info->multi = p_dev->resource[0]->end >> 3;
if ((p_dev->resource[1]->end) && (p_dev->resource[0]->end == 8)
&& (p_dev->resource[1]->end == 8))
info->multi = 2;
return 0; /* break */
}
static int serial_config(struct pcmcia_device *link)
{
struct serial_info *info = link->priv;
int i;
dev_dbg(&link->dev, "serial_config\n");
/* Is this a compliant multifunction card? */
info->multi = (link->socket->functions > 1);
/* Is this a multiport card? */
info->manfid = link->manf_id;
info->prodid = link->card_id;
for (i = 0; i < ARRAY_SIZE(quirks); i++)
if ((quirks[i].manfid == ~0 ||
quirks[i].manfid == info->manfid) &&
(quirks[i].prodid == ~0 ||
quirks[i].prodid == info->prodid)) {
info->quirk = &quirks[i];
break;
}
/*
* Another check for dual-serial cards: look for either serial or
* multifunction cards that ask for appropriate IO port ranges.
*/
if ((info->multi == 0) &&
(link->has_func_id) &&
(link->socket->pcmcia_pfc == 0) &&
((link->func_id == CISTPL_FUNCID_MULTI) ||
(link->func_id == CISTPL_FUNCID_SERIAL))) {
if (pcmcia_loop_config(link, serial_check_for_multi, info))
goto failed;
}
/*
* Apply any multi-port quirk.
*/
if (info->quirk && info->quirk->multi != -1)
info->multi = info->quirk->multi;
dev_info(&link->dev,
"trying to set up [0x%04x:0x%04x] (pfc: %d, multi: %d, quirk: %p)\n",
link->manf_id, link->card_id,
link->socket->pcmcia_pfc, info->multi, info->quirk);
if (link->socket->pcmcia_pfc)
i = pfc_config(link);
else if (info->multi > 1)
i = multi_config(link);
else
i = simple_config(link);
if (i || info->ndev == 0)
goto failed;
/*
* Apply any post-init quirk. FIXME: This should really happen
* before we register the port, since it might already be in use.
*/
if (info->quirk && info->quirk->post)
if (info->quirk->post(link))
goto failed;
return 0;
failed:
dev_warn(&link->dev, "failed to initialize\n");
serial_remove(link);
return -ENODEV;
}
static const struct pcmcia_device_id serial_ids[] = {
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0057, 0x0021),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0089, 0x110a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0104, 0x000a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0d0a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0e0a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0xea15),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0109, 0x0501),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0138, 0x110a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0140, 0x000a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0x3341),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0xc0ab),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x016c, 0x0081),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x021b, 0x0101),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x08a1, 0xc0ab),
PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3336", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x0143b773, 0x46a52d63),
PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "EM1144T", "PCMCIA MODEM", 0xf510db04, 0x856d66c8, 0xbd6c43ef),
PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM33", 0x2e3ee845, 0x80609023),
PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "ATKK", "LM33-PCM-T", 0xba9eb7e2, 0x077c174e),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "LINKSYS", "PCMLM336", 0xf7cb0b07, 0x7a821b58),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "MICRO RESEARCH", "COMBO-L/M-336", 0xb2ced065, 0x3ced0555),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "NEC", "PK-UG-J001", 0x18df0ba0, 0x831b1064),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "ComboCard", 0xdcfe12d3, 0xcd8906cc),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "LanModem", 0xdcfe12d3, 0xc67c648f),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "TDK", "GlobalNetworker 3410/3412", 0x1eae9475, 0xd9a93bed),
PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0e01),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0a05),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0b05),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x1101),
PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0104, 0x0070),
PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x016c, 0x0020),
PCMCIA_MFC_DEVICE_PROD_ID123(1, "APEX DATA", "MULTICARD", "ETHERNET-MODEM", 0x11c2da09, 0x7289dc5d, 0xaad95e1f),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away 28.8 PC Card ", 0xb569a6e5, 0x5bd4ff2c),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away Credit Card Adapter", 0xb569a6e5, 0x4bdf15c3),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "w95 Home and Away Credit Card ", 0xb569a6e5, 0xae911c15),
PCMCIA_MFC_DEVICE_PROD_ID1(1, "Motorola MARQUIS", 0xf03e4e77),
PCMCIA_MFC_DEVICE_PROD_ID2(1, "FAX/Modem/Ethernet Combo Card ", 0x1ed59302),
PCMCIA_DEVICE_MANF_CARD(0x0089, 0x0301),
PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x0276),
PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0039),
PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0006),
PCMCIA_DEVICE_MANF_CARD(0x0105, 0x0101), /* TDK DF2814 */
PCMCIA_DEVICE_MANF_CARD(0x0105, 0x100a), /* Xircom CM-56G */
PCMCIA_DEVICE_MANF_CARD(0x0105, 0x3e0a), /* TDK DF5660 */
PCMCIA_DEVICE_MANF_CARD(0x0105, 0x410a),
PCMCIA_DEVICE_MANF_CARD(0x0107, 0x0002), /* USRobotics 14,400 */
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d50),
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d51),
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d52),
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d53),
PCMCIA_DEVICE_MANF_CARD(0x010b, 0xd180),
PCMCIA_DEVICE_MANF_CARD(0x0115, 0x3330), /* USRobotics/SUN 14,400 */
PCMCIA_DEVICE_MANF_CARD(0x0124, 0x0100), /* Nokia DTP-2 ver II */
PCMCIA_DEVICE_MANF_CARD(0x0134, 0x5600), /* LASAT COMMUNICATIONS A/S */
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x000e),
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x001b),
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025),
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045),
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052),
PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */
PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */
PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae),
PCMCIA_DEVICE_PROD_ID124("GATEWAY2000", "CC3144", "PCMCIA MODEM", 0x506bccae, 0xcb3685f1, 0xbd6c43ef),
PCMCIA_DEVICE_PROD_ID14("MEGAHERTZ", "PCMCIA MODEM", 0xf510db04, 0xbd6c43ef),
PCMCIA_DEVICE_PROD_ID124("TOSHIBA", "T144PF", "PCMCIA MODEM", 0xb4585a1a, 0x7271409c, 0xbd6c43ef),
PCMCIA_DEVICE_PROD_ID123("FUJITSU", "FC14F ", "MBH10213", 0x6ee5a3d8, 0x30ead12b, 0xb00f05a0),
PCMCIA_DEVICE_PROD_ID123("Novatel Wireless", "Merlin UMTS Modem", "U630", 0x32607776, 0xd9e73b13, 0xe87332e),
PCMCIA_DEVICE_PROD_ID13("MEGAHERTZ", "V.34 PCMCIA MODEM", 0xf510db04, 0xbb2cce4a),
PCMCIA_DEVICE_PROD_ID12("Brain Boxes", "Bluetooth PC Card", 0xee138382, 0xd4ce9b02),
PCMCIA_DEVICE_PROD_ID12("CIRRUS LOGIC", "FAX MODEM", 0xe625f451, 0xcecd6dfa),
PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 28800 FAX/DATA MODEM", 0xa3a3062c, 0x8cbd7c76),
PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 33600 FAX/DATA MODEM", 0xa3a3062c, 0x5a00ce95),
PCMCIA_DEVICE_PROD_ID12("Computerboards, Inc.", "PCM-COM422", 0xd0b78f51, 0x7e2d49ed),
PCMCIA_DEVICE_PROD_ID12("Dr. Neuhaus", "FURY CARD 14K4", 0x76942813, 0x8b96ce65),
PCMCIA_DEVICE_PROD_ID12("IBM", "ISDN/56K/GSM", 0xb569a6e5, 0xfee5297b),
PCMCIA_DEVICE_PROD_ID12("Intelligent", "ANGIA FAX/MODEM", 0xb496e65e, 0xf31602a6),
PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400+", 0x816cc815, 0x412729fb),
PCMCIA_DEVICE_PROD_ID12("Intertex", "IX34-PCMCIA", 0xf8a097e3, 0x97880447),
PCMCIA_DEVICE_PROD_ID12("IOTech Inc ", "PCMCIA Dual RS-232 Serial Port Card", 0x3bd2d898, 0x92abc92f),
PCMCIA_DEVICE_PROD_ID12("MACRONIX", "FAX/MODEM", 0x668388b3, 0x3f9bdf2f),
PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT1432LT", 0x5f73be51, 0x0b3e2383),
PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT2834LT", 0x5f73be51, 0x4cd7c09e),
PCMCIA_DEVICE_PROD_ID12("OEM ", "C288MX ", 0xb572d360, 0xd2385b7a),
PCMCIA_DEVICE_PROD_ID12("Option International", "V34bis GSM/PSTN Data/Fax Modem", 0x9d7cd6f5, 0x5cb8bf41),
PCMCIA_DEVICE_PROD_ID12("Option International", "GSM-Ready 56K/ISDN", 0x9d7cd6f5, 0xb23844aa),
PCMCIA_DEVICE_PROD_ID12("PCMCIA ", "C336MX ", 0x99bcafe9, 0xaa25bcab),
PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "PCMCIA Dual RS-232 Serial Port Card", 0xc4420b35, 0x92abc92f),
PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "Dual RS-232 Serial Port PC Card", 0xc4420b35, 0x031a380d),
PCMCIA_DEVICE_PROD_ID12("Telia", "SurfinBird 560P/A+", 0xe2cdd5e, 0xc9314b38),
PCMCIA_DEVICE_PROD_ID1("Smart Serial Port", 0x2d8ce292),
PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "EN2218-LAN/MODEM", 0x281f1c5d, 0x570f348e, "cis/PCMLM28.cis"),
PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "UE2218-LAN/MODEM", 0x281f1c5d, 0x6fdcacee, "cis/PCMLM28.cis"),
PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "TOSHIBA", "Modem/LAN Card", 0xb4585a1a, 0x53f922f8, "cis/PCMLM28.cis"),
PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "cis/DP83903.cis"),
PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0035, "cis/3CXEM556.cis"),
PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x003d, "cis/3CXEM556.cis"),
PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC850 3G Network Adapter R1 */
PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC860", 0xd85f6206, 0x698f93db, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC860 3G Network Adapter R1 */
PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC710/AC750", 0xd85f6206, 0x761b11e0, "cis/SW_7xx_SER.cis"), /* Sierra Wireless AC710/AC750 GPRS Network Adapter R1 */
PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "cis/SW_555_SER.cis"), /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "cis/MT5634ZLX.cis"),
PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "cis/COMpad2.cis"),
PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "cis/COMpad4.cis"),
PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "cis/COMpad2.cis"),
PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "cis/RS-COM-2P.cis"),
PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.", "SERIAL CARD: SL100 1.00.", 0x19ca78af, 0xf964f42b),
PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.", "SERIAL CARD: SL100", 0x19ca78af, 0x71d98e83),
PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.", "SERIAL CARD: SL232 1.00.", 0x19ca78af, 0x69fb7490),
PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.", "SERIAL CARD: SL232", 0x19ca78af, 0xb6bc0235),
PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.", "SERIAL CARD: CF232", 0x63f2e0bd, 0xb9e175d3),
PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.", "SERIAL CARD: CF232-5", 0x63f2e0bd, 0xfce33442),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: CF232", 0x3beb8cf2, 0x171e7190),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: CF232-5", 0x3beb8cf2, 0x20da4262),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: CF428", 0x3beb8cf2, 0xea5dd57d),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: CF500", 0x3beb8cf2, 0xd77255fa),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: IC232", 0x3beb8cf2, 0x6a709903),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: SL232", 0x3beb8cf2, 0x18430676),
PCMCIA_DEVICE_PROD_ID12("Elan", "Serial Port: XL232", 0x3beb8cf2, 0x6f933767),
PCMCIA_MFC_DEVICE_PROD_ID12(0, "Elan", "Serial Port: CF332", 0x3beb8cf2, 0x16dc1ba7),
PCMCIA_MFC_DEVICE_PROD_ID12(0, "Elan", "Serial Port: SL332", 0x3beb8cf2, 0x19816c41),
PCMCIA_MFC_DEVICE_PROD_ID12(0, "Elan", "Serial Port: SL385", 0x3beb8cf2, 0x64112029),
PCMCIA_MFC_DEVICE_PROD_ID12(0, "Elan", "Serial Port: SL432", 0x3beb8cf2, 0x1cce7ac4),
PCMCIA_MFC_DEVICE_PROD_ID12(0, "Elan", "Serial+Parallel Port: SP230", 0x3beb8cf2, 0xdb9e58bc),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "Elan", "Serial Port: CF332", 0x3beb8cf2, 0x16dc1ba7),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "Elan", "Serial Port: SL332", 0x3beb8cf2, 0x19816c41),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "Elan", "Serial Port: SL385", 0x3beb8cf2, 0x64112029),
PCMCIA_MFC_DEVICE_PROD_ID12(1, "Elan", "Serial Port: SL432", 0x3beb8cf2, 0x1cce7ac4),
PCMCIA_MFC_DEVICE_PROD_ID12(2, "Elan", "Serial Port: SL432", 0x3beb8cf2, 0x1cce7ac4),
PCMCIA_MFC_DEVICE_PROD_ID12(3, "Elan", "Serial Port: SL432", 0x3beb8cf2, 0x1cce7ac4),
PCMCIA_DEVICE_MANF_CARD(0x0279, 0x950b),
/* too generic */
/* PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0160, 0x0002), */
/* PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0160, 0x0002), */
PCMCIA_DEVICE_FUNC_ID(2),
PCMCIA_DEVICE_NULL,
};
MODULE_DEVICE_TABLE(pcmcia, serial_ids);
MODULE_FIRMWARE("cis/PCMLM28.cis");
MODULE_FIRMWARE("cis/DP83903.cis");
MODULE_FIRMWARE("cis/3CCFEM556.cis");
MODULE_FIRMWARE("cis/3CXEM556.cis");
MODULE_FIRMWARE("cis/SW_8xx_SER.cis");
MODULE_FIRMWARE("cis/SW_7xx_SER.cis");
MODULE_FIRMWARE("cis/SW_555_SER.cis");
MODULE_FIRMWARE("cis/MT5634ZLX.cis");
MODULE_FIRMWARE("cis/COMpad2.cis");
MODULE_FIRMWARE("cis/COMpad4.cis");
MODULE_FIRMWARE("cis/RS-COM-2P.cis");
static struct pcmcia_driver serial_cs_driver = {
.owner = THIS_MODULE,
.name = "serial_cs",
.probe = serial_probe,
.remove = serial_detach,
.id_table = serial_ids,
.suspend = serial_suspend,
.resume = serial_resume,
};
module_pcmcia_driver(serial_cs_driver);
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/serial_cs.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas Emma Mobile 8250 driver
*
* Copyright (C) 2012 Magnus Damm
*/
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include "8250.h"
#define UART_DLL_EM 9
#define UART_DLM_EM 10
#define UART_HCR0_EM 11
/*
* A high value for UART_FCR_EM avoids overlapping with existing UART_*
* register defines. UART_FCR_EM_HW is the real HW register offset.
*/
#define UART_FCR_EM 0x10003
#define UART_FCR_EM_HW 3
#define UART_HCR0_EM_SW_RESET BIT(7) /* SW Reset */
struct serial8250_em_priv {
int line;
};
static void serial8250_em_serial_out_helper(struct uart_port *p, int offset,
int value)
{
switch (offset) {
case UART_TX: /* TX @ 0x00 */
writeb(value, p->membase);
break;
case UART_LCR: /* LCR @ 0x10 (+1) */
case UART_MCR: /* MCR @ 0x14 (+1) */
case UART_SCR: /* SCR @ 0x20 (+1) */
writel(value, p->membase + ((offset + 1) << 2));
break;
case UART_FCR_EM:
writel(value, p->membase + (UART_FCR_EM_HW << 2));
break;
case UART_IER: /* IER @ 0x04 */
value &= 0x0f; /* only 4 valid bits - not Xscale */
fallthrough;
case UART_DLL_EM: /* DLL @ 0x24 (+9) */
case UART_DLM_EM: /* DLM @ 0x28 (+9) */
case UART_HCR0_EM: /* HCR0 @ 0x2c */
writel(value, p->membase + (offset << 2));
break;
}
}
static unsigned int serial8250_em_serial_in(struct uart_port *p, int offset)
{
switch (offset) {
case UART_RX: /* RX @ 0x00 */
return readb(p->membase);
case UART_LCR: /* LCR @ 0x10 (+1) */
case UART_MCR: /* MCR @ 0x14 (+1) */
case UART_LSR: /* LSR @ 0x18 (+1) */
case UART_MSR: /* MSR @ 0x1c (+1) */
case UART_SCR: /* SCR @ 0x20 (+1) */
return readl(p->membase + ((offset + 1) << 2));
case UART_FCR_EM:
return readl(p->membase + (UART_FCR_EM_HW << 2));
case UART_IER: /* IER @ 0x04 */
case UART_IIR: /* IIR @ 0x08 */
case UART_DLL_EM: /* DLL @ 0x24 (+9) */
case UART_DLM_EM: /* DLM @ 0x28 (+9) */
case UART_HCR0_EM: /* HCR0 @ 0x2c */
return readl(p->membase + (offset << 2));
}
return 0;
}
static void serial8250_em_reg_update(struct uart_port *p, int off, int value)
{
unsigned int ier, fcr, lcr, mcr, hcr0;
ier = serial8250_em_serial_in(p, UART_IER);
fcr = serial8250_em_serial_in(p, UART_FCR_EM);
lcr = serial8250_em_serial_in(p, UART_LCR);
mcr = serial8250_em_serial_in(p, UART_MCR);
hcr0 = serial8250_em_serial_in(p, UART_HCR0_EM);
serial8250_em_serial_out_helper(p, UART_FCR_EM, fcr |
UART_FCR_CLEAR_RCVR |
UART_FCR_CLEAR_XMIT);
serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0 |
UART_HCR0_EM_SW_RESET);
serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0 &
~UART_HCR0_EM_SW_RESET);
switch (off) {
case UART_FCR_EM:
fcr = value;
break;
case UART_LCR:
lcr = value;
break;
case UART_MCR:
mcr = value;
break;
}
serial8250_em_serial_out_helper(p, UART_IER, ier);
serial8250_em_serial_out_helper(p, UART_FCR_EM, fcr);
serial8250_em_serial_out_helper(p, UART_MCR, mcr);
serial8250_em_serial_out_helper(p, UART_LCR, lcr);
serial8250_em_serial_out_helper(p, UART_HCR0_EM, hcr0);
}
static void serial8250_em_serial_out(struct uart_port *p, int offset, int value)
{
switch (offset) {
case UART_TX:
case UART_SCR:
case UART_IER:
case UART_DLL_EM:
case UART_DLM_EM:
serial8250_em_serial_out_helper(p, offset, value);
break;
case UART_FCR:
serial8250_em_reg_update(p, UART_FCR_EM, value);
break;
case UART_LCR:
case UART_MCR:
serial8250_em_reg_update(p, offset, value);
break;
}
}
static u32 serial8250_em_serial_dl_read(struct uart_8250_port *up)
{
return serial_in(up, UART_DLL_EM) | serial_in(up, UART_DLM_EM) << 8;
}
static void serial8250_em_serial_dl_write(struct uart_8250_port *up, u32 value)
{
serial_out(up, UART_DLL_EM, value & 0xff);
serial_out(up, UART_DLM_EM, value >> 8 & 0xff);
}
static int serial8250_em_probe(struct platform_device *pdev)
{
struct serial8250_em_priv *priv;
struct device *dev = &pdev->dev;
struct uart_8250_port up;
struct resource *regs;
struct clk *sclk;
int irq, ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs)
return dev_err_probe(dev, -EINVAL, "missing registers\n");
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
sclk = devm_clk_get_enabled(dev, "sclk");
if (IS_ERR(sclk))
return dev_err_probe(dev, PTR_ERR(sclk), "unable to get clock\n");
memset(&up, 0, sizeof(up));
up.port.mapbase = regs->start;
up.port.irq = irq;
up.port.type = PORT_16750;
up.port.flags = UPF_FIXED_PORT | UPF_IOREMAP | UPF_FIXED_TYPE;
up.port.dev = dev;
up.port.private_data = priv;
up.port.uartclk = clk_get_rate(sclk);
up.port.iotype = UPIO_MEM32;
up.port.serial_in = serial8250_em_serial_in;
up.port.serial_out = serial8250_em_serial_out;
up.dl_read = serial8250_em_serial_dl_read;
up.dl_write = serial8250_em_serial_dl_write;
ret = serial8250_register_8250_port(&up);
if (ret < 0)
return dev_err_probe(dev, ret, "unable to register 8250 port\n");
priv->line = ret;
platform_set_drvdata(pdev, priv);
return 0;
}
static int serial8250_em_remove(struct platform_device *pdev)
{
struct serial8250_em_priv *priv = platform_get_drvdata(pdev);
serial8250_unregister_port(priv->line);
return 0;
}
static const struct of_device_id serial8250_em_dt_ids[] = {
{ .compatible = "renesas,em-uart", },
{},
};
MODULE_DEVICE_TABLE(of, serial8250_em_dt_ids);
static struct platform_driver serial8250_em_platform_driver = {
.driver = {
.name = "serial8250-em",
.of_match_table = serial8250_em_dt_ids,
},
.probe = serial8250_em_probe,
.remove = serial8250_em_remove,
};
module_platform_driver(serial8250_em_platform_driver);
MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas Emma Mobile 8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/8250/8250_em.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/mcb.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#define MEN_UART_ID_Z025 0x19
#define MEN_UART_ID_Z057 0x39
#define MEN_UART_ID_Z125 0x7d
/*
* IP Cores Z025 and Z057 can have up to 4 UART
* The UARTs available are stored in a global
* register saved in physical address + 0x40
* Is saved as follows:
*
* 7 0
* +------+-------+-------+-------+-------+-------+-------+-------+
* |UART4 | UART3 | UART2 | UART1 | U4irq | U3irq | U2irq | U1irq |
* +------+-------+-------+-------+-------+-------+-------+-------+
*/
#define MEN_UART1_MASK 0x01
#define MEN_UART2_MASK 0x02
#define MEN_UART3_MASK 0x04
#define MEN_UART4_MASK 0x08
#define MEN_Z125_UARTS_AVAILABLE 0x01
#define MEN_Z025_MAX_UARTS 4
#define MEN_UART_MEM_SIZE 0x10
#define MEM_UART_REGISTER_SIZE 0x01
#define MEN_Z025_REGISTER_OFFSET 0x40
#define MEN_UART1_OFFSET 0
#define MEN_UART2_OFFSET (MEN_UART1_OFFSET + MEN_UART_MEM_SIZE)
#define MEN_UART3_OFFSET (MEN_UART2_OFFSET + MEN_UART_MEM_SIZE)
#define MEN_UART4_OFFSET (MEN_UART3_OFFSET + MEN_UART_MEM_SIZE)
#define MEN_READ_REGISTER(addr) readb(addr)
#define MAX_PORTS 4
struct serial_8250_men_mcb_data {
int num_ports;
int line[MAX_PORTS];
unsigned int offset[MAX_PORTS];
};
/*
* The Z125 16550-compatible UART has no fixed base clock assigned
* So, depending on the board we're on, we need to adjust the
* parameter in order to really set the correct baudrate, and
* do so if possible without user interaction
*/
static u32 men_lookup_uartclk(struct mcb_device *mdev)
{
/* use default value if board is not available below */
u32 clkval = 1041666;
dev_info(&mdev->dev, "%s on board %s\n",
dev_name(&mdev->dev),
mdev->bus->name);
if (strncmp(mdev->bus->name, "F075", 4) == 0)
clkval = 1041666;
else if (strncmp(mdev->bus->name, "F216", 4) == 0)
clkval = 1843200;
else if (strncmp(mdev->bus->name, "F210", 4) == 0)
clkval = 115200;
else if (strstr(mdev->bus->name, "215"))
clkval = 1843200;
else
dev_info(&mdev->dev,
"board not detected, using default uartclk\n");
clkval = clkval << 4;
return clkval;
}
static int read_uarts_available_from_register(struct resource *mem_res,
u8 *uarts_available)
{
void __iomem *mem;
int reg_value;
if (!request_mem_region(mem_res->start + MEN_Z025_REGISTER_OFFSET,
MEM_UART_REGISTER_SIZE, KBUILD_MODNAME)) {
return -EBUSY;
}
mem = ioremap(mem_res->start + MEN_Z025_REGISTER_OFFSET,
MEM_UART_REGISTER_SIZE);
if (!mem) {
release_mem_region(mem_res->start + MEN_Z025_REGISTER_OFFSET,
MEM_UART_REGISTER_SIZE);
return -ENOMEM;
}
reg_value = MEN_READ_REGISTER(mem);
iounmap(mem);
release_mem_region(mem_res->start + MEN_Z025_REGISTER_OFFSET,
MEM_UART_REGISTER_SIZE);
*uarts_available = reg_value >> 4;
return 0;
}
static int read_serial_data(struct mcb_device *mdev,
struct resource *mem_res,
struct serial_8250_men_mcb_data *serial_data)
{
u8 uarts_available;
int count = 0;
int mask;
int res;
int i;
res = read_uarts_available_from_register(mem_res, &uarts_available);
if (res < 0)
return res;
for (i = 0; i < MAX_PORTS; i++) {
mask = 0x1 << i;
switch (uarts_available & mask) {
case MEN_UART1_MASK:
serial_data->offset[count] = MEN_UART1_OFFSET;
count++;
break;
case MEN_UART2_MASK:
serial_data->offset[count] = MEN_UART2_OFFSET;
count++;
break;
case MEN_UART3_MASK:
serial_data->offset[count] = MEN_UART3_OFFSET;
count++;
break;
case MEN_UART4_MASK:
serial_data->offset[count] = MEN_UART4_OFFSET;
count++;
break;
default:
return -EINVAL;
}
}
if (count <= 0 || count > MAX_PORTS) {
dev_err(&mdev->dev, "unexpected number of ports: %u\n",
count);
return -ENODEV;
}
serial_data->num_ports = count;
return 0;
}
static int init_serial_data(struct mcb_device *mdev,
struct resource *mem_res,
struct serial_8250_men_mcb_data *serial_data)
{
switch (mdev->id) {
case MEN_UART_ID_Z125:
serial_data->num_ports = 1;
serial_data->offset[0] = 0;
return 0;
case MEN_UART_ID_Z025:
case MEN_UART_ID_Z057:
return read_serial_data(mdev, mem_res, serial_data);
default:
dev_err(&mdev->dev, "no supported device!\n");
return -ENODEV;
}
}
static int serial_8250_men_mcb_probe(struct mcb_device *mdev,
const struct mcb_device_id *id)
{
struct uart_8250_port uart;
struct serial_8250_men_mcb_data *data;
struct resource *mem;
int i;
int res;
mem = mcb_get_resource(mdev, IORESOURCE_MEM);
if (mem == NULL)
return -ENXIO;
data = devm_kzalloc(&mdev->dev,
sizeof(struct serial_8250_men_mcb_data),
GFP_KERNEL);
if (!data)
return -ENOMEM;
res = init_serial_data(mdev, mem, data);
if (res < 0)
return res;
dev_dbg(&mdev->dev, "found a 16z%03u with %u ports\n",
mdev->id, data->num_ports);
mcb_set_drvdata(mdev, data);
for (i = 0; i < data->num_ports; i++) {
memset(&uart, 0, sizeof(struct uart_8250_port));
spin_lock_init(&uart.port.lock);
uart.port.flags = UPF_SKIP_TEST |
UPF_SHARE_IRQ |
UPF_BOOT_AUTOCONF |
UPF_IOREMAP;
uart.port.iotype = UPIO_MEM;
uart.port.uartclk = men_lookup_uartclk(mdev);
uart.port.irq = mcb_get_irq(mdev);
uart.port.mapbase = (unsigned long) mem->start
+ data->offset[i];
/* ok, register the port */
res = serial8250_register_8250_port(&uart);
if (res < 0) {
dev_err(&mdev->dev, "unable to register UART port\n");
return res;
}
data->line[i] = res;
dev_info(&mdev->dev, "found MCB UART: ttyS%d\n", data->line[i]);
}
return 0;
}
static void serial_8250_men_mcb_remove(struct mcb_device *mdev)
{
int i;
struct serial_8250_men_mcb_data *data = mcb_get_drvdata(mdev);
if (!data)
return;
for (i = 0; i < data->num_ports; i++)
serial8250_unregister_port(data->line[i]);
}
static const struct mcb_device_id serial_8250_men_mcb_ids[] = {
{ .device = MEN_UART_ID_Z025 },
{ .device = MEN_UART_ID_Z057 },
{ .device = MEN_UART_ID_Z125 },
{ }
};
MODULE_DEVICE_TABLE(mcb, serial_8250_men_mcb_ids);
static struct mcb_driver mcb_driver = {
.driver = {
.name = "8250_men_mcb",
},
.probe = serial_8250_men_mcb_probe,
.remove = serial_8250_men_mcb_remove,
.id_table = serial_8250_men_mcb_ids,
};
module_mcb_driver(mcb_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MEN 8250 UART driver");
MODULE_AUTHOR("Michael Moese <[email protected]");
MODULE_ALIAS("mcb:16z125");
MODULE_ALIAS("mcb:16z025");
MODULE_ALIAS("mcb:16z057");
MODULE_IMPORT_NS(MCB);
| linux-master | drivers/tty/serial/8250/8250_men_mcb.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Early serial console for 8250/16550 devices
*
* (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
* Bjorn Helgaas <[email protected]>
*
* Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
* and on early_printk.c by Andi Kleen.
*
* This is for use before the serial driver has initialized, in
* particular, before the UARTs have been discovered and named.
* Instead of specifying the console device as, e.g., "ttyS0",
* we locate the device directly by its MMIO or I/O port address.
*
* The user can specify the device directly, e.g.,
* earlycon=uart8250,io,0x3f8,9600n8
* earlycon=uart8250,mmio,0xff5e0000,115200n8
* earlycon=uart8250,mmio32,0xff5e0000,115200n8
* or
* console=uart8250,io,0x3f8,9600n8
* console=uart8250,mmio,0xff5e0000,115200n8
* console=uart8250,mmio32,0xff5e0000,115200n8
*/
#include <linux/tty.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/of.h>
#include <linux/serial_reg.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <asm/io.h>
#include <asm/serial.h>
static unsigned int serial8250_early_in(struct uart_port *port, int offset)
{
offset <<= port->regshift;
switch (port->iotype) {
case UPIO_MEM:
return readb(port->membase + offset);
case UPIO_MEM16:
return readw(port->membase + offset);
case UPIO_MEM32:
return readl(port->membase + offset);
case UPIO_MEM32BE:
return ioread32be(port->membase + offset);
case UPIO_PORT:
return inb(port->iobase + offset);
default:
return 0;
}
}
static void serial8250_early_out(struct uart_port *port, int offset, int value)
{
offset <<= port->regshift;
switch (port->iotype) {
case UPIO_MEM:
writeb(value, port->membase + offset);
break;
case UPIO_MEM16:
writew(value, port->membase + offset);
break;
case UPIO_MEM32:
writel(value, port->membase + offset);
break;
case UPIO_MEM32BE:
iowrite32be(value, port->membase + offset);
break;
case UPIO_PORT:
outb(value, port->iobase + offset);
break;
}
}
static void serial_putc(struct uart_port *port, unsigned char c)
{
unsigned int status;
serial8250_early_out(port, UART_TX, c);
for (;;) {
status = serial8250_early_in(port, UART_LSR);
if (uart_lsr_tx_empty(status))
break;
cpu_relax();
}
}
static void early_serial8250_write(struct console *console,
const char *s, unsigned int count)
{
struct earlycon_device *device = console->data;
struct uart_port *port = &device->port;
uart_console_write(port, s, count, serial_putc);
}
#ifdef CONFIG_CONSOLE_POLL
static int early_serial8250_read(struct console *console,
char *s, unsigned int count)
{
struct earlycon_device *device = console->data;
struct uart_port *port = &device->port;
unsigned int status;
int num_read = 0;
while (num_read < count) {
status = serial8250_early_in(port, UART_LSR);
if (!(status & UART_LSR_DR))
break;
s[num_read++] = serial8250_early_in(port, UART_RX);
}
return num_read;
}
#else
#define early_serial8250_read NULL
#endif
static void __init init_port(struct earlycon_device *device)
{
struct uart_port *port = &device->port;
unsigned int divisor;
unsigned char c;
unsigned int ier;
serial8250_early_out(port, UART_LCR, UART_LCR_WLEN8); /* 8n1 */
ier = serial8250_early_in(port, UART_IER);
serial8250_early_out(port, UART_IER, ier & UART_IER_UUE); /* no interrupt */
serial8250_early_out(port, UART_FCR, 0); /* no fifo */
serial8250_early_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
if (port->uartclk) {
divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud);
c = serial8250_early_in(port, UART_LCR);
serial8250_early_out(port, UART_LCR, c | UART_LCR_DLAB);
serial8250_early_out(port, UART_DLL, divisor & 0xff);
serial8250_early_out(port, UART_DLM, (divisor >> 8) & 0xff);
serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB);
}
}
int __init early_serial8250_setup(struct earlycon_device *device,
const char *options)
{
if (!(device->port.membase || device->port.iobase))
return -ENODEV;
if (!device->baud) {
struct uart_port *port = &device->port;
unsigned int ier;
/* assume the device was initialized, only mask interrupts */
ier = serial8250_early_in(port, UART_IER);
serial8250_early_out(port, UART_IER, ier & UART_IER_UUE);
} else
init_port(device);
device->con->write = early_serial8250_write;
device->con->read = early_serial8250_read;
return 0;
}
EARLYCON_DECLARE(uart8250, early_serial8250_setup);
EARLYCON_DECLARE(uart, early_serial8250_setup);
OF_EARLYCON_DECLARE(ns16550, "ns16550", early_serial8250_setup);
OF_EARLYCON_DECLARE(ns16550a, "ns16550a", early_serial8250_setup);
OF_EARLYCON_DECLARE(uart, "nvidia,tegra20-uart", early_serial8250_setup);
OF_EARLYCON_DECLARE(uart, "snps,dw-apb-uart", early_serial8250_setup);
#ifdef CONFIG_SERIAL_8250_OMAP
static int __init early_omap8250_setup(struct earlycon_device *device,
const char *options)
{
struct uart_port *port = &device->port;
if (!(device->port.membase || device->port.iobase))
return -ENODEV;
port->regshift = 2;
device->con->write = early_serial8250_write;
return 0;
}
OF_EARLYCON_DECLARE(omap8250, "ti,omap2-uart", early_omap8250_setup);
OF_EARLYCON_DECLARE(omap8250, "ti,omap3-uart", early_omap8250_setup);
OF_EARLYCON_DECLARE(omap8250, "ti,omap4-uart", early_omap8250_setup);
#endif
| linux-master | drivers/tty/serial/8250/8250_early.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 Lars-Peter Clausen <[email protected]>
* Copyright (C) 2015 Imagination Technologies
*
* Ingenic SoC UART support
*/
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/io.h>
#include <linux/libfdt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include "8250.h"
/** ingenic_uart_config: SOC specific config data. */
struct ingenic_uart_config {
int tx_loadsz;
int fifosize;
};
struct ingenic_uart_data {
struct clk *clk_module;
struct clk *clk_baud;
int line;
};
static const struct of_device_id of_match[];
#define UART_FCR_UME BIT(4)
#define UART_MCR_MDCE BIT(7)
#define UART_MCR_FCM BIT(6)
static struct earlycon_device *early_device;
static uint8_t early_in(struct uart_port *port, int offset)
{
return readl(port->membase + (offset << 2));
}
static void early_out(struct uart_port *port, int offset, uint8_t value)
{
writel(value, port->membase + (offset << 2));
}
static void ingenic_early_console_putc(struct uart_port *port, unsigned char c)
{
u16 lsr;
do {
lsr = early_in(port, UART_LSR);
} while ((lsr & UART_LSR_TEMT) == 0);
early_out(port, UART_TX, c);
}
static void ingenic_early_console_write(struct console *console,
const char *s, unsigned int count)
{
uart_console_write(&early_device->port, s, count,
ingenic_early_console_putc);
}
static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
{
void *fdt = initial_boot_params;
const __be32 *prop;
int offset;
offset = fdt_path_offset(fdt, "/ext");
if (offset < 0)
return;
prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
if (!prop)
return;
dev->port.uartclk = be32_to_cpup(prop);
}
static int __init ingenic_earlycon_setup_tail(struct earlycon_device *dev,
const char *opt)
{
struct uart_port *port = &dev->port;
unsigned int divisor;
int baud = 115200;
if (!dev->port.membase)
return -ENODEV;
if (opt) {
unsigned int parity, bits, flow; /* unused for now */
uart_parse_options(opt, &baud, &parity, &bits, &flow);
}
if (dev->baud)
baud = dev->baud;
divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
early_out(port, UART_IER, 0);
early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
early_out(port, UART_DLL, 0);
early_out(port, UART_DLM, 0);
early_out(port, UART_LCR, UART_LCR_WLEN8);
early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
early_out(port, UART_DLL, divisor & 0xff);
early_out(port, UART_DLM, (divisor >> 8) & 0xff);
early_out(port, UART_LCR, UART_LCR_WLEN8);
early_device = dev;
dev->con->write = ingenic_early_console_write;
return 0;
}
static int __init ingenic_early_console_setup(struct earlycon_device *dev,
const char *opt)
{
ingenic_early_console_setup_clock(dev);
return ingenic_earlycon_setup_tail(dev, opt);
}
static int __init jz4750_early_console_setup(struct earlycon_device *dev,
const char *opt)
{
/*
* JZ4750/55/60 have an optional /2 divider between the EXT
* oscillator and some peripherals including UART, which will
* be enabled if using a 24 MHz oscillator, and disabled when
* using a 12 MHz oscillator.
*/
ingenic_early_console_setup_clock(dev);
if (dev->port.uartclk >= 16000000)
dev->port.uartclk /= 2;
return ingenic_earlycon_setup_tail(dev, opt);
}
OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
ingenic_early_console_setup);
OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
jz4750_early_console_setup);
OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
ingenic_early_console_setup);
OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
ingenic_early_console_setup);
OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
ingenic_early_console_setup);
OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
ingenic_early_console_setup);
static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
{
int ier;
switch (offset) {
case UART_FCR:
/* UART module enable */
value |= UART_FCR_UME;
break;
case UART_IER:
/*
* Enable receive timeout interrupt with the receive line
* status interrupt.
*/
value |= (value & 0x4) << 2;
break;
case UART_MCR:
/*
* If we have enabled modem status IRQs we should enable
* modem mode.
*/
ier = p->serial_in(p, UART_IER);
if (ier & UART_IER_MSI)
value |= UART_MCR_MDCE | UART_MCR_FCM;
else
value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
break;
default:
break;
}
writeb(value, p->membase + (offset << p->regshift));
}
static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
{
unsigned int value;
value = readb(p->membase + (offset << p->regshift));
/* Hide non-16550 compliant bits from higher levels */
switch (offset) {
case UART_FCR:
value &= ~UART_FCR_UME;
break;
case UART_MCR:
value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
break;
default:
break;
}
return value;
}
static int ingenic_uart_probe(struct platform_device *pdev)
{
struct uart_8250_port uart = {};
struct ingenic_uart_data *data;
const struct ingenic_uart_config *cdata;
struct resource *regs;
int irq, err, line;
cdata = of_device_get_match_data(&pdev->dev);
if (!cdata) {
dev_err(&pdev->dev, "Error: No device match found\n");
return -ENODEV;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(&pdev->dev, "no registers defined\n");
return -EINVAL;
}
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
spin_lock_init(&uart.port.lock);
uart.port.type = PORT_16550A;
uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
uart.port.iotype = UPIO_MEM;
uart.port.mapbase = regs->start;
uart.port.regshift = 2;
uart.port.serial_out = ingenic_uart_serial_out;
uart.port.serial_in = ingenic_uart_serial_in;
uart.port.irq = irq;
uart.port.dev = &pdev->dev;
uart.port.fifosize = cdata->fifosize;
uart.tx_loadsz = cdata->tx_loadsz;
uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
/* Check for a fixed line number */
line = of_alias_get_id(pdev->dev.of_node, "serial");
if (line >= 0)
uart.port.line = line;
uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
resource_size(regs));
if (!uart.port.membase)
return -ENOMEM;
data->clk_module = devm_clk_get(&pdev->dev, "module");
if (IS_ERR(data->clk_module))
return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
"unable to get module clock\n");
data->clk_baud = devm_clk_get(&pdev->dev, "baud");
if (IS_ERR(data->clk_baud))
return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
"unable to get baud clock\n");
err = clk_prepare_enable(data->clk_module);
if (err) {
dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
goto out;
}
err = clk_prepare_enable(data->clk_baud);
if (err) {
dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
goto out_disable_moduleclk;
}
uart.port.uartclk = clk_get_rate(data->clk_baud);
data->line = serial8250_register_8250_port(&uart);
if (data->line < 0) {
err = data->line;
goto out_disable_baudclk;
}
platform_set_drvdata(pdev, data);
return 0;
out_disable_baudclk:
clk_disable_unprepare(data->clk_baud);
out_disable_moduleclk:
clk_disable_unprepare(data->clk_module);
out:
return err;
}
static int ingenic_uart_remove(struct platform_device *pdev)
{
struct ingenic_uart_data *data = platform_get_drvdata(pdev);
serial8250_unregister_port(data->line);
clk_disable_unprepare(data->clk_module);
clk_disable_unprepare(data->clk_baud);
return 0;
}
static const struct ingenic_uart_config jz4740_uart_config = {
.tx_loadsz = 8,
.fifosize = 16,
};
static const struct ingenic_uart_config jz4760_uart_config = {
.tx_loadsz = 16,
.fifosize = 32,
};
static const struct ingenic_uart_config jz4780_uart_config = {
.tx_loadsz = 32,
.fifosize = 64,
};
static const struct ingenic_uart_config x1000_uart_config = {
.tx_loadsz = 32,
.fifosize = 64,
};
static const struct of_device_id of_match[] = {
{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
{ .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
{ .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_match);
static struct platform_driver ingenic_uart_platform_driver = {
.driver = {
.name = "ingenic-uart",
.of_match_table = of_match,
},
.probe = ingenic_uart_probe,
.remove = ingenic_uart_remove,
};
module_platform_driver(ingenic_uart_platform_driver);
MODULE_AUTHOR("Paul Burton");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Ingenic SoC UART driver");
| linux-master | drivers/tty/serial/8250/8250_ingenic.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Probe module for 8250/16550-type MCHP PCI serial ports.
*
* Based on drivers/tty/serial/8250/8250_pci.c,
*
* Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved.
*/
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/units.h>
#include <linux/tty.h>
#include <asm/byteorder.h>
#include "8250.h"
#include "8250_pcilib.h"
#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002
#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012
#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022
#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032
#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e
#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f
#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000
#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010
#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101
#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400
#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414
#define UART_ACTV_REG 0x11
#define UART_BLOCK_SET_ACTIVE BIT(0)
#define UART_PCI_CTRL_REG 0x80
#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4)
#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0)
#define ADCL_CFG_REG 0x40
#define ADCL_CFG_POL_SEL BIT(2)
#define ADCL_CFG_PIN_SEL BIT(1)
#define ADCL_CFG_EN BIT(0)
#define UART_BIT_SAMPLE_CNT 16
#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8)
#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8)
#define UART_CLOCK_DEFAULT (62500 * HZ_PER_KHZ)
#define UART_WAKE_REG 0x8C
#define UART_WAKE_MASK_REG 0x90
#define UART_WAKE_N_PIN BIT(2)
#define UART_WAKE_NCTS BIT(1)
#define UART_WAKE_INT BIT(0)
#define UART_WAKE_SRCS \
(UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT)
#define UART_BAUD_CLK_DIVISOR_REG 0x54
#define UART_RESET_REG 0x94
#define UART_RESET_D3_RESET_DISABLE BIT(16)
#define MAX_PORTS 4
#define PORT_OFFSET 0x100
static const int logical_to_physical_port_idx[][MAX_PORTS] = {
{0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */
{0, 1, 2, 3}, /* PCI4p */
{0, 1, 2, -1}, /* PCI3p012 */
{0, 1, 3, -1}, /* PCI3p013 */
{0, 2, 3, -1}, /* PCI3p023 */
{1, 2, 3, -1}, /* PCI3p123 */
{0, 1, -1, -1}, /* PCI2p01 */
{0, 2, -1, -1}, /* PCI2p02 */
{0, 3, -1, -1}, /* PCI2p03 */
{1, 2, -1, -1}, /* PCI2p12 */
{1, 3, -1, -1}, /* PCI2p13 */
{2, 3, -1, -1}, /* PCI2p23 */
{0, -1, -1, -1}, /* PCI1p0 */
{1, -1, -1, -1}, /* PCI1p1 */
{2, -1, -1, -1}, /* PCI1p2 */
{3, -1, -1, -1}, /* PCI1p3 */
};
struct pci1xxxx_8250 {
unsigned int nr;
void __iomem *membase;
int line[];
};
static int pci1xxxx_get_num_ports(struct pci_dev *dev)
{
switch (dev->subsystem_device) {
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3:
case PCI_SUBDEVICE_ID_EFAR_PCI12000:
case PCI_SUBDEVICE_ID_EFAR_PCI11010:
case PCI_SUBDEVICE_ID_EFAR_PCI11101:
case PCI_SUBDEVICE_ID_EFAR_PCI11400:
default:
return 1;
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23:
return 2;
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013:
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023:
return 3;
case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p:
case PCI_SUBDEVICE_ID_EFAR_PCI11414:
return 4;
}
}
static unsigned int pci1xxxx_get_divisor(struct uart_port *port,
unsigned int baud, unsigned int *frac)
{
unsigned int quot;
/*
* Calculate baud rate sampling period in nanoseconds.
* Fractional part x denotes x/255 parts of a nanosecond.
*/
quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT);
*frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) *
255 / UART_BIT_SAMPLE_CNT / baud;
return quot;
}
static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,
unsigned int quot, unsigned int frac)
{
writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac,
port->membase + UART_BAUD_CLK_DIVISOR_REG);
}
static int pci1xxxx_rs485_config(struct uart_port *port,
struct ktermios *termios,
struct serial_rs485 *rs485)
{
u32 delay_in_baud_periods;
u32 baud_period_in_ns;
u32 mode_cfg = 0;
u32 clock_div;
/*
* pci1xxxx's uart hardware supports only RTS delay after
* Tx and in units of bit times to a maximum of 15
*/
if (rs485->flags & SER_RS485_ENABLED) {
mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
mode_cfg |= ADCL_CFG_POL_SEL;
if (rs485->delay_rts_after_send) {
clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);
baud_period_in_ns =
FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *
UART_BIT_SAMPLE_CNT;
delay_in_baud_periods =
rs485->delay_rts_after_send * NSEC_PER_MSEC /
baud_period_in_ns;
delay_in_baud_periods =
min_t(u32, delay_in_baud_periods,
FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,
delay_in_baud_periods);
rs485->delay_rts_after_send =
baud_period_in_ns * delay_in_baud_periods /
NSEC_PER_MSEC;
}
}
writel(mode_cfg, port->membase + ADCL_CFG_REG);
return 0;
}
static const struct serial_rs485 pci1xxxx_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
SER_RS485_RTS_AFTER_SEND,
.delay_rts_after_send = 1,
/* Delay RTS before send is not supported */
};
static bool pci1xxxx_port_suspend(int line)
{
struct uart_8250_port *up = serial8250_get_port(line);
struct uart_port *port = &up->port;
struct tty_port *tport = &port->state->port;
unsigned long flags;
bool ret = false;
u8 wakeup_mask;
mutex_lock(&tport->mutex);
if (port->suspended == 0 && port->dev) {
wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);
spin_lock_irqsave(&port->lock, flags);
port->mctrl &= ~TIOCM_OUT2;
port->ops->set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS;
}
writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
mutex_unlock(&tport->mutex);
return ret;
}
static void pci1xxxx_port_resume(int line)
{
struct uart_8250_port *up = serial8250_get_port(line);
struct uart_port *port = &up->port;
struct tty_port *tport = &port->state->port;
unsigned long flags;
mutex_lock(&tport->mutex);
writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG);
writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
if (port->suspended == 0) {
spin_lock_irqsave(&port->lock, flags);
port->mctrl |= TIOCM_OUT2;
port->ops->set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
}
mutex_unlock(&tport->mutex);
}
static int pci1xxxx_suspend(struct device *dev)
{
struct pci1xxxx_8250 *priv = dev_get_drvdata(dev);
struct pci_dev *pcidev = to_pci_dev(dev);
bool wakeup = false;
unsigned int data;
void __iomem *p;
int i;
for (i = 0; i < priv->nr; i++) {
if (priv->line[i] >= 0) {
serial8250_suspend_port(priv->line[i]);
wakeup |= pci1xxxx_port_suspend(priv->line[i]);
}
}
p = pci_ioremap_bar(pcidev, 0);
if (!p) {
dev_err(dev, "remapping of bar 0 memory failed");
return -ENOMEM;
}
data = readl(p + UART_RESET_REG);
writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
if (wakeup)
writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG);
iounmap(p);
device_set_wakeup_enable(dev, true);
pci_wake_from_d3(pcidev, true);
return 0;
}
static int pci1xxxx_resume(struct device *dev)
{
struct pci1xxxx_8250 *priv = dev_get_drvdata(dev);
struct pci_dev *pcidev = to_pci_dev(dev);
unsigned int data;
void __iomem *p;
int i;
p = pci_ioremap_bar(pcidev, 0);
if (!p) {
dev_err(dev, "remapping of bar 0 memory failed");
return -ENOMEM;
}
data = readl(p + UART_RESET_REG);
writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
iounmap(p);
for (i = 0; i < priv->nr; i++) {
if (priv->line[i] >= 0) {
pci1xxxx_port_resume(priv->line[i]);
serial8250_resume_port(priv->line[i]);
}
}
return 0;
}
static int pci1xxxx_setup(struct pci_dev *pdev,
struct uart_8250_port *port, int port_idx)
{
int ret;
port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST;
port->port.type = PORT_MCHP16550A;
port->port.set_termios = serial8250_do_set_termios;
port->port.get_divisor = pci1xxxx_get_divisor;
port->port.set_divisor = pci1xxxx_set_divisor;
port->port.rs485_config = pci1xxxx_rs485_config;
port->port.rs485_supported = pci1xxxx_rs485_supported;
ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0);
if (ret < 0)
return ret;
writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);
writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);
writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);
return 0;
}
static unsigned int pci1xxxx_get_max_port(int subsys_dev)
{
unsigned int i = MAX_PORTS;
if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))
while (i--) {
if (logical_to_physical_port_idx[subsys_dev][i] != -1)
return logical_to_physical_port_idx[subsys_dev][i] + 1;
}
if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414)
return 4;
return 1;
}
static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port)
{
if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))
return logical_to_physical_port_idx[subsys_dev][port];
return logical_to_physical_port_idx[0][port];
}
static int pci1xxxx_serial_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct device *dev = &pdev->dev;
struct pci1xxxx_8250 *priv;
struct uart_8250_port uart;
unsigned int max_vec_reqd;
unsigned int nr_ports, i;
int num_vectors;
int subsys_dev;
int port_idx;
int rc;
rc = pcim_enable_device(pdev);
if (rc)
return rc;
nr_ports = pci1xxxx_get_num_ports(pdev);
priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->membase = pci_ioremap_bar(pdev, 0);
if (!priv->membase)
return -ENOMEM;
pci_set_master(pdev);
priv->nr = nr_ports;
subsys_dev = pdev->subsystem_device;
max_vec_reqd = pci1xxxx_get_max_port(subsys_dev);
num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES);
if (num_vectors < 0) {
pci_iounmap(pdev, priv->membase);
return num_vectors;
}
memset(&uart, 0, sizeof(uart));
uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
uart.port.uartclk = UART_CLOCK_DEFAULT;
uart.port.dev = dev;
if (num_vectors == max_vec_reqd)
writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);
for (i = 0; i < nr_ports; i++) {
priv->line[i] = -ENODEV;
port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i);
if (num_vectors == max_vec_reqd)
uart.port.irq = pci_irq_vector(pdev, port_idx);
else
uart.port.irq = pci_irq_vector(pdev, 0);
rc = pci1xxxx_setup(pdev, &uart, port_idx);
if (rc) {
dev_warn(dev, "Failed to setup port %u\n", i);
continue;
}
priv->line[i] = serial8250_register_8250_port(&uart);
if (priv->line[i] < 0) {
dev_warn(dev,
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
uart.port.iobase, uart.port.irq, uart.port.iotype,
priv->line[i]);
}
}
pci_set_drvdata(pdev, priv);
return 0;
}
static void pci1xxxx_serial_remove(struct pci_dev *dev)
{
struct pci1xxxx_8250 *priv = pci_get_drvdata(dev);
unsigned int i;
for (i = 0; i < priv->nr; i++) {
if (priv->line[i] >= 0)
serial8250_unregister_port(priv->line[i]);
}
pci_free_irq_vectors(dev);
pci_iounmap(dev, priv->membase);
}
static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume);
static const struct pci_device_id pci1xxxx_pci_tbl[] = {
{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) },
{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) },
{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) },
{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) },
{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) },
{}
};
MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl);
static struct pci_driver pci1xxxx_pci_driver = {
.name = "pci1xxxx serial",
.probe = pci1xxxx_serial_probe,
.remove = pci1xxxx_serial_remove,
.driver = {
.pm = pm_sleep_ptr(&pci1xxxx_pm_ops),
},
.id_table = pci1xxxx_pci_tbl,
};
module_pci_driver(pci1xxxx_pci_driver);
static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1));
MODULE_IMPORT_NS(SERIAL_8250_PCI);
MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module");
MODULE_AUTHOR("Kumaravel Thiagarajan <[email protected]>");
MODULE_AUTHOR("Tharun Kumar P <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_pci1xxxx.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Probe module for 8250/16550-type Exar chips PCI serial ports.
*
* Based on drivers/tty/serial/8250/8250_pci.c,
*
* Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
*/
#include <linux/acpi.h>
#include <linux/dmi.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/property.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/tty.h>
#include <linux/8250_pci.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
#include "8250.h"
#define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
#define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
#define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
#define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
#define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
#define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
#define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
#define PCI_SUBDEVICE_ID_USR_2980 0x0128
#define PCI_SUBDEVICE_ID_USR_2981 0x0129
#define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001
#define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002
#define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004
#define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008
#define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010
#define UART_EXAR_INT0 0x80
#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
#define UART_EXAR_DVID 0x8d /* Device identification */
#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
#define UART_EXAR_RS485_DLY(x) ((x) << 4)
/*
* IOT2040 MPIO wiring semantics:
*
* MPIO Port Function
* ---- ---- --------
* 0 2 Mode bit 0
* 1 2 Mode bit 1
* 2 2 Terminate bus
* 3 - <reserved>
* 4 3 Mode bit 0
* 5 3 Mode bit 1
* 6 3 Terminate bus
* 7 - <reserved>
* 8 2 Enable
* 9 3 Enable
* 10 - Red LED
* 11..15 - <unused>
*/
/* IOT2040 MPIOs 0..7 */
#define IOT2040_UART_MODE_RS232 0x01
#define IOT2040_UART_MODE_RS485 0x02
#define IOT2040_UART_MODE_RS422 0x03
#define IOT2040_UART_TERMINATE_BUS 0x04
#define IOT2040_UART1_MASK 0x0f
#define IOT2040_UART2_SHIFT 4
#define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
#define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
/* IOT2040 MPIOs 8..15 */
#define IOT2040_UARTS_ENABLE 0x03
#define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
struct exar8250;
struct exar8250_platform {
int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485);
const struct serial_rs485 *rs485_supported;
int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
void (*unregister_gpio)(struct uart_8250_port *);
};
/**
* struct exar8250_board - board information
* @num_ports: number of serial ports
* @reg_shift: describes UART register mapping in PCI memory
* @setup: quirk run at ->probe() stage
* @exit: quirk run at ->remove() stage
*/
struct exar8250_board {
unsigned int num_ports;
unsigned int reg_shift;
int (*setup)(struct exar8250 *, struct pci_dev *,
struct uart_8250_port *, int);
void (*exit)(struct pci_dev *pcidev);
};
struct exar8250 {
unsigned int nr;
struct exar8250_board *board;
void __iomem *virt;
int line[];
};
static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
{
/*
* Exar UARTs have a SLEEP register that enables or disables each UART
* to enter sleep mode separately. On the XR17V35x the register
* is accessible to each UART at the UART_EXAR_SLEEP offset, but
* the UART channel may only write to the corresponding bit.
*/
serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
}
/*
* XR17V35x UARTs have an extra fractional divisor register (DLD)
* Calculate divisor with extra 4-bit fractional portion
*/
static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
unsigned int *frac)
{
unsigned int quot_16;
quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
*frac = quot_16 & 0x0f;
return quot_16 >> 4;
}
static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
unsigned int quot, unsigned int quot_frac)
{
serial8250_do_set_divisor(p, baud, quot, quot_frac);
/* Preserve bits not related to baudrate; DLD[7:4]. */
quot_frac |= serial_port_in(p, 0x2) & 0xf0;
serial_port_out(p, 0x2, quot_frac);
}
static int xr17v35x_startup(struct uart_port *port)
{
/*
* First enable access to IER [7:5], ISR [5:4], FCR [5:4],
* MCR [7:5] and MSR [7:0]
*/
serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
/*
* Make sure all interrups are masked until initialization is
* complete and the FIFOs are cleared
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irq(&port->lock);
serial_port_out(port, UART_IER, 0);
spin_unlock_irq(&port->lock);
return serial8250_do_startup(port);
}
static void exar_shutdown(struct uart_port *port)
{
bool tx_complete = false;
struct uart_8250_port *up = up_to_u8250p(port);
struct circ_buf *xmit = &port->state->xmit;
int i = 0;
u16 lsr;
do {
lsr = serial_in(up, UART_LSR);
if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
tx_complete = true;
else
tx_complete = false;
usleep_range(1000, 1100);
} while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
serial8250_do_shutdown(port);
}
static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
int idx, unsigned int offset,
struct uart_8250_port *port)
{
const struct exar8250_board *board = priv->board;
unsigned int bar = 0;
unsigned char status;
port->port.iotype = UPIO_MEM;
port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
port->port.membase = priv->virt + offset;
port->port.regshift = board->reg_shift;
/*
* XR17V35x UARTs have an extra divisor register, DLD that gets enabled
* with when DLAB is set which will cause the device to incorrectly match
* and assign port type to PORT_16650. The EFR for this UART is found
* at offset 0x09. Instead check the Deice ID (DVID) register
* for a 2, 4 or 8 port UART.
*/
status = readb(port->port.membase + UART_EXAR_DVID);
if (status == 0x82 || status == 0x84 || status == 0x88) {
port->port.type = PORT_XR17V35X;
port->port.get_divisor = xr17v35x_get_divisor;
port->port.set_divisor = xr17v35x_set_divisor;
port->port.startup = xr17v35x_startup;
} else {
port->port.type = PORT_XR17D15X;
}
port->port.pm = exar_pm;
port->port.shutdown = exar_shutdown;
return 0;
}
static int
pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
struct uart_8250_port *port, int idx)
{
unsigned int offset = idx * 0x200;
unsigned int baud = 1843200;
u8 __iomem *p;
int err;
port->port.uartclk = baud * 16;
err = default_setup(priv, pcidev, idx, offset, port);
if (err)
return err;
p = port->port.membase;
writeb(0x00, p + UART_EXAR_8XMODE);
writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
writeb(32, p + UART_EXAR_TXTRG);
writeb(32, p + UART_EXAR_RXTRG);
/*
* Setup Multipurpose Input/Output pins.
*/
if (idx == 0) {
switch (pcidev->device) {
case PCI_DEVICE_ID_COMMTECH_4222PCI335:
case PCI_DEVICE_ID_COMMTECH_4224PCI335:
writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
break;
case PCI_DEVICE_ID_COMMTECH_2324PCI335:
case PCI_DEVICE_ID_COMMTECH_2328PCI335:
writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
break;
}
writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
}
return 0;
}
static int
pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
struct uart_8250_port *port, int idx)
{
unsigned int offset = idx * 0x200;
unsigned int baud = 1843200;
port->port.uartclk = baud * 16;
return default_setup(priv, pcidev, idx, offset, port);
}
static int
pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
struct uart_8250_port *port, int idx)
{
unsigned int offset = idx * 0x200;
unsigned int baud = 921600;
port->port.uartclk = baud * 16;
return default_setup(priv, pcidev, idx, offset, port);
}
static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
{
/*
* The Commtech adapters required the MPIOs to be driven low. The Exar
* devices will export them as GPIOs, so we pre-configure them safely
* as inputs.
*/
u8 dir = 0x00;
if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
// Configure GPIO as inputs for Commtech adapters
dir = 0xff;
} else {
// Configure GPIO as outputs for SeaLevel adapters
dir = 0x00;
}
writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
}
static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
const struct software_node *node)
{
struct platform_device *pdev;
pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
if (!pdev)
return NULL;
pdev->dev.parent = &pcidev->dev;
ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
if (device_add_software_node(&pdev->dev, node) < 0 ||
platform_device_add(pdev) < 0) {
platform_device_put(pdev);
return NULL;
}
return pdev;
}
static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
{
device_remove_software_node(&pdev->dev);
platform_device_unregister(pdev);
}
static const struct property_entry exar_gpio_properties[] = {
PROPERTY_ENTRY_U32("exar,first-pin", 0),
PROPERTY_ENTRY_U32("ngpios", 16),
{ }
};
static const struct software_node exar_gpio_node = {
.properties = exar_gpio_properties,
};
static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
{
if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
port->port.private_data =
__xr17v35x_register_gpio(pcidev, &exar_gpio_node);
return 0;
}
static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
{
if (!port->port.private_data)
return;
__xr17v35x_unregister_gpio(port->port.private_data);
port->port.private_data = NULL;
}
static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
u8 __iomem *p = port->membase;
u8 value;
value = readb(p + UART_EXAR_FCTR);
if (is_rs485)
value |= UART_FCTR_EXAR_485;
else
value &= ~UART_FCTR_EXAR_485;
writeb(value, p + UART_EXAR_FCTR);
if (is_rs485)
writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
return 0;
}
static const struct serial_rs485 generic_rs485_supported = {
.flags = SER_RS485_ENABLED,
};
static const struct exar8250_platform exar8250_default_platform = {
.register_gpio = xr17v35x_register_gpio,
.unregister_gpio = xr17v35x_unregister_gpio,
.rs485_config = generic_rs485_config,
.rs485_supported = &generic_rs485_supported,
};
static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
u8 __iomem *p = port->membase;
u8 mask = IOT2040_UART1_MASK;
u8 mode, value;
if (is_rs485) {
if (rs485->flags & SER_RS485_RX_DURING_TX)
mode = IOT2040_UART_MODE_RS422;
else
mode = IOT2040_UART_MODE_RS485;
if (rs485->flags & SER_RS485_TERMINATE_BUS)
mode |= IOT2040_UART_TERMINATE_BUS;
} else {
mode = IOT2040_UART_MODE_RS232;
}
if (port->line == 3) {
mask <<= IOT2040_UART2_SHIFT;
mode <<= IOT2040_UART2_SHIFT;
}
value = readb(p + UART_EXAR_MPIOLVL_7_0);
value &= ~mask;
value |= mode;
writeb(value, p + UART_EXAR_MPIOLVL_7_0);
return generic_rs485_config(port, termios, rs485);
}
static const struct serial_rs485 iot2040_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
};
static const struct property_entry iot2040_gpio_properties[] = {
PROPERTY_ENTRY_U32("exar,first-pin", 10),
PROPERTY_ENTRY_U32("ngpios", 1),
{ }
};
static const struct software_node iot2040_gpio_node = {
.properties = iot2040_gpio_properties,
};
static int iot2040_register_gpio(struct pci_dev *pcidev,
struct uart_8250_port *port)
{
u8 __iomem *p = port->port.membase;
writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
port->port.private_data =
__xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
return 0;
}
static const struct exar8250_platform iot2040_platform = {
.rs485_config = iot2040_rs485_config,
.rs485_supported = &iot2040_rs485_supported,
.register_gpio = iot2040_register_gpio,
.unregister_gpio = xr17v35x_unregister_gpio,
};
/*
* For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
* IOT2020 doesn't have. Therefore it is sufficient to match on the common
* board name after the device was found.
*/
static const struct dmi_system_id exar_platforms[] = {
{
.matches = {
DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
},
.driver_data = (void *)&iot2040_platform,
},
{}
};
static const struct exar8250_platform *exar_get_platform(void)
{
const struct dmi_system_id *dmi_match;
dmi_match = dmi_first_match(exar_platforms);
if (dmi_match)
return dmi_match->driver_data;
return &exar8250_default_platform;
}
static int
pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
struct uart_8250_port *port, int idx)
{
const struct exar8250_platform *platform = exar_get_platform();
unsigned int offset = idx * 0x400;
unsigned int baud = 7812500;
u8 __iomem *p;
int ret;
port->port.uartclk = baud * 16;
port->port.rs485_config = platform->rs485_config;
port->port.rs485_supported = *(platform->rs485_supported);
/*
* Setup the UART clock for the devices on expansion slot to
* half the clock speed of the main chip (which is 125MHz)
*/
if (idx >= 8)
port->port.uartclk /= 2;
ret = default_setup(priv, pcidev, idx, offset, port);
if (ret)
return ret;
p = port->port.membase;
writeb(0x00, p + UART_EXAR_8XMODE);
writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
writeb(128, p + UART_EXAR_TXTRG);
writeb(128, p + UART_EXAR_RXTRG);
if (idx == 0) {
/* Setup Multipurpose Input/Output pins. */
setup_gpio(pcidev, p);
ret = platform->register_gpio(pcidev, port);
}
return ret;
}
static void pci_xr17v35x_exit(struct pci_dev *pcidev)
{
const struct exar8250_platform *platform = exar_get_platform();
struct exar8250 *priv = pci_get_drvdata(pcidev);
struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
platform->unregister_gpio(port);
}
static inline void exar_misc_clear(struct exar8250 *priv)
{
/* Clear all PCI interrupts by reading INT0. No effect on IIR */
readb(priv->virt + UART_EXAR_INT0);
/* Clear INT0 for Expansion Interface slave ports, too */
if (priv->board->num_ports > 8)
readb(priv->virt + 0x2000 + UART_EXAR_INT0);
}
/*
* These Exar UARTs have an extra interrupt indicator that could fire for a
* few interrupts that are not presented/cleared through IIR. One of which is
* a wakeup interrupt when coming out of sleep. These interrupts are only
* cleared by reading global INT0 or INT1 registers as interrupts are
* associated with channel 0. The INT[3:0] registers _are_ accessible from each
* channel's address space, but for the sake of bus efficiency we register a
* dedicated handler at the PCI device level to handle them.
*/
static irqreturn_t exar_misc_handler(int irq, void *data)
{
exar_misc_clear(data);
return IRQ_HANDLED;
}
static int
exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
{
unsigned int nr_ports, i, bar = 0, maxnr;
struct exar8250_board *board;
struct uart_8250_port uart;
struct exar8250 *priv;
int rc;
board = (struct exar8250_board *)ent->driver_data;
if (!board)
return -EINVAL;
rc = pcim_enable_device(pcidev);
if (rc)
return rc;
maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
else if (board->num_ports)
nr_ports = board->num_ports;
else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
nr_ports = pcidev->device & 0xff;
else
nr_ports = pcidev->device & 0x0f;
priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->board = board;
priv->virt = pcim_iomap(pcidev, bar, 0);
if (!priv->virt)
return -ENOMEM;
pci_set_master(pcidev);
rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
if (rc < 0)
return rc;
memset(&uart, 0, sizeof(uart));
uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
uart.port.irq = pci_irq_vector(pcidev, 0);
uart.port.dev = &pcidev->dev;
rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
IRQF_SHARED, "exar_uart", priv);
if (rc)
return rc;
/* Clear interrupts */
exar_misc_clear(priv);
for (i = 0; i < nr_ports && i < maxnr; i++) {
rc = board->setup(priv, pcidev, &uart, i);
if (rc) {
dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
break;
}
dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
uart.port.iobase, uart.port.irq, uart.port.iotype);
priv->line[i] = serial8250_register_8250_port(&uart);
if (priv->line[i] < 0) {
dev_err(&pcidev->dev,
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
uart.port.iobase, uart.port.irq,
uart.port.iotype, priv->line[i]);
break;
}
}
priv->nr = i;
pci_set_drvdata(pcidev, priv);
return 0;
}
static void exar_pci_remove(struct pci_dev *pcidev)
{
struct exar8250 *priv = pci_get_drvdata(pcidev);
unsigned int i;
for (i = 0; i < priv->nr; i++)
serial8250_unregister_port(priv->line[i]);
if (priv->board->exit)
priv->board->exit(pcidev);
}
static int __maybe_unused exar_suspend(struct device *dev)
{
struct pci_dev *pcidev = to_pci_dev(dev);
struct exar8250 *priv = pci_get_drvdata(pcidev);
unsigned int i;
for (i = 0; i < priv->nr; i++)
if (priv->line[i] >= 0)
serial8250_suspend_port(priv->line[i]);
/* Ensure that every init quirk is properly torn down */
if (priv->board->exit)
priv->board->exit(pcidev);
return 0;
}
static int __maybe_unused exar_resume(struct device *dev)
{
struct exar8250 *priv = dev_get_drvdata(dev);
unsigned int i;
exar_misc_clear(priv);
for (i = 0; i < priv->nr; i++)
if (priv->line[i] >= 0)
serial8250_resume_port(priv->line[i]);
return 0;
}
static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
static const struct exar8250_board pbn_fastcom335_2 = {
.num_ports = 2,
.setup = pci_fastcom335_setup,
};
static const struct exar8250_board pbn_fastcom335_4 = {
.num_ports = 4,
.setup = pci_fastcom335_setup,
};
static const struct exar8250_board pbn_fastcom335_8 = {
.num_ports = 8,
.setup = pci_fastcom335_setup,
};
static const struct exar8250_board pbn_connect = {
.setup = pci_connect_tech_setup,
};
static const struct exar8250_board pbn_exar_ibm_saturn = {
.num_ports = 1,
.setup = pci_xr17c154_setup,
};
static const struct exar8250_board pbn_exar_XR17C15x = {
.setup = pci_xr17c154_setup,
};
static const struct exar8250_board pbn_exar_XR17V35x = {
.setup = pci_xr17v35x_setup,
.exit = pci_xr17v35x_exit,
};
static const struct exar8250_board pbn_fastcom35x_2 = {
.num_ports = 2,
.setup = pci_xr17v35x_setup,
.exit = pci_xr17v35x_exit,
};
static const struct exar8250_board pbn_fastcom35x_4 = {
.num_ports = 4,
.setup = pci_xr17v35x_setup,
.exit = pci_xr17v35x_exit,
};
static const struct exar8250_board pbn_fastcom35x_8 = {
.num_ports = 8,
.setup = pci_xr17v35x_setup,
.exit = pci_xr17v35x_exit,
};
static const struct exar8250_board pbn_exar_XR17V4358 = {
.num_ports = 12,
.setup = pci_xr17v35x_setup,
.exit = pci_xr17v35x_exit,
};
static const struct exar8250_board pbn_exar_XR17V8358 = {
.num_ports = 16,
.setup = pci_xr17v35x_setup,
.exit = pci_xr17v35x_exit,
};
#define CONNECT_DEVICE(devid, sdevid, bd) { \
PCI_DEVICE_SUB( \
PCI_VENDOR_ID_EXAR, \
PCI_DEVICE_ID_EXAR_##devid, \
PCI_SUBVENDOR_ID_CONNECT_TECH, \
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
(kernel_ulong_t)&bd \
}
#define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
#define IBM_DEVICE(devid, sdevid, bd) { \
PCI_DEVICE_SUB( \
PCI_VENDOR_ID_EXAR, \
PCI_DEVICE_ID_EXAR_##devid, \
PCI_VENDOR_ID_IBM, \
PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
(kernel_ulong_t)&bd \
}
#define USR_DEVICE(devid, sdevid, bd) { \
PCI_DEVICE_SUB( \
PCI_VENDOR_ID_USR, \
PCI_DEVICE_ID_EXAR_##devid, \
PCI_VENDOR_ID_EXAR, \
PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
(kernel_ulong_t)&bd \
}
static const struct pci_device_id exar_pci_tbl[] = {
EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
/* USRobotics USR298x-OEM PCI Modems */
USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
/* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
/* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
{ 0, }
};
MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
static struct pci_driver exar_pci_driver = {
.name = "exar_serial",
.probe = exar_pci_probe,
.remove = exar_pci_remove,
.driver = {
.pm = &exar_pci_pm,
},
.id_table = exar_pci_tbl,
};
module_pci_driver(exar_pci_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Exar Serial Driver");
MODULE_AUTHOR("Sudip Mukherjee <[email protected]>");
| linux-master | drivers/tty/serial/8250/8250_exar.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/drivers/serial/acorn.c
*
* Copyright (C) 1996-2003 Russell King.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/ecard.h>
#include <asm/string.h>
#include "8250.h"
#define MAX_PORTS 3
struct serial_card_type {
unsigned int num_ports;
unsigned int uartclk;
unsigned int type;
unsigned int offset[MAX_PORTS];
};
struct serial_card_info {
unsigned int num_ports;
int ports[MAX_PORTS];
void __iomem *vaddr;
};
static int
serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
{
struct serial_card_info *info;
struct serial_card_type *type = id->data;
struct uart_8250_port uart;
unsigned long bus_addr;
unsigned int i;
info = kzalloc(sizeof(struct serial_card_info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->num_ports = type->num_ports;
bus_addr = ecard_resource_start(ec, type->type);
info->vaddr = ecardm_iomap(ec, type->type, 0, 0);
if (!info->vaddr) {
kfree(info);
return -ENOMEM;
}
ecard_set_drvdata(ec, info);
memset(&uart, 0, sizeof(struct uart_8250_port));
uart.port.irq = ec->irq;
uart.port.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
uart.port.uartclk = type->uartclk;
uart.port.iotype = UPIO_MEM;
uart.port.regshift = 2;
uart.port.dev = &ec->dev;
for (i = 0; i < info->num_ports; i++) {
uart.port.membase = info->vaddr + type->offset[i];
uart.port.mapbase = bus_addr + type->offset[i];
info->ports[i] = serial8250_register_8250_port(&uart);
}
return 0;
}
static void serial_card_remove(struct expansion_card *ec)
{
struct serial_card_info *info = ecard_get_drvdata(ec);
int i;
ecard_set_drvdata(ec, NULL);
for (i = 0; i < info->num_ports; i++)
if (info->ports[i] > 0)
serial8250_unregister_port(info->ports[i]);
kfree(info);
}
static struct serial_card_type atomwide_type = {
.num_ports = 3,
.uartclk = 7372800,
.type = ECARD_RES_IOCSLOW,
.offset = { 0x2800, 0x2400, 0x2000 },
};
static struct serial_card_type serport_type = {
.num_ports = 2,
.uartclk = 3686400,
.type = ECARD_RES_IOCSLOW,
.offset = { 0x2000, 0x2020 },
};
static const struct ecard_id serial_cids[] = {
{ MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, &atomwide_type },
{ MANU_SERPORT, PROD_SERPORT_DSPORT, &serport_type },
{ 0xffff, 0xffff }
};
static struct ecard_driver serial_card_driver = {
.probe = serial_card_probe,
.remove = serial_card_remove,
.id_table = serial_cids,
.drv = {
.name = "8250_acorn",
},
};
static int __init serial_card_init(void)
{
return ecard_register_driver(&serial_card_driver);
}
static void __exit serial_card_exit(void)
{
ecard_remove_driver(&serial_card_driver);
}
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("Acorn 8250-compatible serial port expansion card driver");
MODULE_LICENSE("GPL");
module_init(serial_card_init);
module_exit(serial_card_exit);
| linux-master | drivers/tty/serial/8250/8250_acorn.c |
// SPDX-License-Identifier: GPL-2.0
/*
* 8250 PCI library.
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*/
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/types.h>
#include "8250.h"
#include "8250_pcilib.h"
int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port,
u8 bar, unsigned int offset, int regshift)
{
if (bar >= PCI_STD_NUM_BARS)
return -EINVAL;
if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
return -ENOMEM;
port->port.iotype = UPIO_MEM;
port->port.iobase = 0;
port->port.mapbase = pci_resource_start(dev, bar) + offset;
port->port.membase = pcim_iomap_table(dev)[bar] + offset;
port->port.regshift = regshift;
} else {
port->port.iotype = UPIO_PORT;
port->port.iobase = pci_resource_start(dev, bar) + offset;
port->port.mapbase = 0;
port->port.membase = NULL;
port->port.regshift = 0;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(serial8250_pci_setup_port, SERIAL_8250_PCI);
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_pcilib.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for FPGA UART
*
* Copyright (C) 2022 Intel Corporation.
*
* Authors:
* Ananda Ravuri <[email protected]>
* Matthew Gerlach <[email protected]>
*/
#include <linux/bitfield.h>
#include <linux/device.h>
#include <linux/dfl.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#define DFHv1_PARAM_ID_CLK_FRQ 0x2
#define DFHv1_PARAM_ID_FIFO_LEN 0x3
#define DFHv1_PARAM_ID_REG_LAYOUT 0x4
#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32)
#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0)
struct dfl_uart {
int line;
};
static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval)
{
size_t psize;
u64 *p;
p = dfh_find_param(dfl_dev, param_id, &psize);
if (IS_ERR(p))
return PTR_ERR(p);
if (psize != sizeof(*pval))
return -EINVAL;
*pval = *p;
return 0;
}
static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart)
{
struct device *dev = &dfl_dev->dev;
u64 fifo_len, clk_freq, reg_layout;
u32 reg_width;
int ret;
ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ, &clk_freq);
if (ret)
return dev_err_probe(dev, ret, "missing CLK_FRQ param\n");
uart->port.uartclk = clk_freq;
ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN, &fifo_len);
if (ret)
return dev_err_probe(dev, ret, "missing FIFO_LEN param\n");
switch (fifo_len) {
case 32:
uart->port.type = PORT_ALTR_16550_F32;
break;
case 64:
uart->port.type = PORT_ALTR_16550_F64;
break;
case 128:
uart->port.type = PORT_ALTR_16550_F128;
break;
default:
return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len);
}
ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout);
if (ret)
return dev_err_probe(dev, ret, "missing REG_LAYOUT param\n");
uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout);
reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout);
switch (reg_width) {
case 4:
uart->port.iotype = UPIO_MEM32;
break;
case 2:
uart->port.iotype = UPIO_MEM16;
break;
default:
return dev_err_probe(dev, -EINVAL, "unsupported reg-width %u\n", reg_width);
}
return 0;
}
static int dfl_uart_probe(struct dfl_device *dfl_dev)
{
struct device *dev = &dfl_dev->dev;
struct uart_8250_port uart = { };
struct dfl_uart *dfluart;
int ret;
uart.port.flags = UPF_IOREMAP;
uart.port.mapbase = dfl_dev->mmio_res.start;
uart.port.mapsize = resource_size(&dfl_dev->mmio_res);
ret = dfl_uart_get_params(dfl_dev, &uart);
if (ret < 0)
return dev_err_probe(dev, ret, "failed uart feature walk\n");
if (dfl_dev->num_irqs == 1)
uart.port.irq = dfl_dev->irqs[0];
dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL);
if (!dfluart)
return -ENOMEM;
dfluart->line = serial8250_register_8250_port(&uart);
if (dfluart->line < 0)
return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n");
dev_set_drvdata(dev, dfluart);
return 0;
}
static void dfl_uart_remove(struct dfl_device *dfl_dev)
{
struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev);
serial8250_unregister_port(dfluart->line);
}
#define FME_FEATURE_ID_UART 0x24
static const struct dfl_device_id dfl_uart_ids[] = {
{ FME_ID, FME_FEATURE_ID_UART },
{ }
};
MODULE_DEVICE_TABLE(dfl, dfl_uart_ids);
static struct dfl_driver dfl_uart_driver = {
.drv = {
.name = "dfl-uart",
},
.id_table = dfl_uart_ids,
.probe = dfl_uart_probe,
.remove = dfl_uart_remove,
};
module_dfl_driver(dfl_uart_driver);
MODULE_DESCRIPTION("DFL Intel UART driver");
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_dfl.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2020, Broadcom */
/*
* 8250-core based driver for Broadcom ns16550a UARTs
*
* This driver uses the standard 8250 driver core but adds additional
* optional features including the ability to use a baud rate clock
* mux for more accurate high speed baud rate selection and also
* an optional DMA engine.
*
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/tty.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/dma-mapping.h>
#include <linux/tty_flip.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include "8250.h"
/* Register definitions for UART DMA block. Version 1.1 or later. */
#define UDMA_ARB_RX 0x00
#define UDMA_ARB_TX 0x04
#define UDMA_ARB_REQ 0x00000001
#define UDMA_ARB_GRANT 0x00000002
#define UDMA_RX_REVISION 0x00
#define UDMA_RX_REVISION_REQUIRED 0x00000101
#define UDMA_RX_CTRL 0x04
#define UDMA_RX_CTRL_BUF_CLOSE_MODE 0x00010000
#define UDMA_RX_CTRL_MASK_WR_DONE 0x00008000
#define UDMA_RX_CTRL_ENDIAN_OVERRIDE 0x00004000
#define UDMA_RX_CTRL_ENDIAN 0x00002000
#define UDMA_RX_CTRL_OE_IS_ERR 0x00001000
#define UDMA_RX_CTRL_PE_IS_ERR 0x00000800
#define UDMA_RX_CTRL_FE_IS_ERR 0x00000400
#define UDMA_RX_CTRL_NUM_BUF_USED_MASK 0x000003c0
#define UDMA_RX_CTRL_NUM_BUF_USED_SHIFT 6
#define UDMA_RX_CTRL_BUF_CLOSE_CLK_SEL_SYS 0x00000020
#define UDMA_RX_CTRL_BUF_CLOSE_ENA 0x00000010
#define UDMA_RX_CTRL_TIMEOUT_CLK_SEL_SYS 0x00000008
#define UDMA_RX_CTRL_TIMEOUT_ENA 0x00000004
#define UDMA_RX_CTRL_ABORT 0x00000002
#define UDMA_RX_CTRL_ENA 0x00000001
#define UDMA_RX_STATUS 0x08
#define UDMA_RX_STATUS_ACTIVE_BUF_MASK 0x0000000f
#define UDMA_RX_TRANSFER_LEN 0x0c
#define UDMA_RX_TRANSFER_TOTAL 0x10
#define UDMA_RX_BUFFER_SIZE 0x14
#define UDMA_RX_SRC_ADDR 0x18
#define UDMA_RX_TIMEOUT 0x1c
#define UDMA_RX_BUFFER_CLOSE 0x20
#define UDMA_RX_BLOCKOUT_COUNTER 0x24
#define UDMA_RX_BUF0_PTR_LO 0x28
#define UDMA_RX_BUF0_PTR_HI 0x2c
#define UDMA_RX_BUF0_STATUS 0x30
#define UDMA_RX_BUFX_STATUS_OVERRUN_ERR 0x00000010
#define UDMA_RX_BUFX_STATUS_FRAME_ERR 0x00000008
#define UDMA_RX_BUFX_STATUS_PARITY_ERR 0x00000004
#define UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED 0x00000002
#define UDMA_RX_BUFX_STATUS_DATA_RDY 0x00000001
#define UDMA_RX_BUF0_DATA_LEN 0x34
#define UDMA_RX_BUF1_PTR_LO 0x38
#define UDMA_RX_BUF1_PTR_HI 0x3c
#define UDMA_RX_BUF1_STATUS 0x40
#define UDMA_RX_BUF1_DATA_LEN 0x44
#define UDMA_TX_REVISION 0x00
#define UDMA_TX_REVISION_REQUIRED 0x00000101
#define UDMA_TX_CTRL 0x04
#define UDMA_TX_CTRL_ENDIAN_OVERRIDE 0x00000080
#define UDMA_TX_CTRL_ENDIAN 0x00000040
#define UDMA_TX_CTRL_NUM_BUF_USED_MASK 0x00000030
#define UDMA_TX_CTRL_NUM_BUF_USED_1 0x00000010
#define UDMA_TX_CTRL_ABORT 0x00000002
#define UDMA_TX_CTRL_ENA 0x00000001
#define UDMA_TX_DST_ADDR 0x08
#define UDMA_TX_BLOCKOUT_COUNTER 0x10
#define UDMA_TX_TRANSFER_LEN 0x14
#define UDMA_TX_TRANSFER_TOTAL 0x18
#define UDMA_TX_STATUS 0x20
#define UDMA_TX_BUF0_PTR_LO 0x24
#define UDMA_TX_BUF0_PTR_HI 0x28
#define UDMA_TX_BUF0_STATUS 0x2c
#define UDMA_TX_BUFX_LAST 0x00000002
#define UDMA_TX_BUFX_EMPTY 0x00000001
#define UDMA_TX_BUF0_DATA_LEN 0x30
#define UDMA_TX_BUF0_DATA_SENT 0x34
#define UDMA_TX_BUF1_PTR_LO 0x38
#define UDMA_INTR_STATUS 0x00
#define UDMA_INTR_ARB_TX_GRANT 0x00040000
#define UDMA_INTR_ARB_RX_GRANT 0x00020000
#define UDMA_INTR_TX_ALL_EMPTY 0x00010000
#define UDMA_INTR_TX_EMPTY_BUF1 0x00008000
#define UDMA_INTR_TX_EMPTY_BUF0 0x00004000
#define UDMA_INTR_TX_ABORT 0x00002000
#define UDMA_INTR_TX_DONE 0x00001000
#define UDMA_INTR_RX_ERROR 0x00000800
#define UDMA_INTR_RX_TIMEOUT 0x00000400
#define UDMA_INTR_RX_READY_BUF7 0x00000200
#define UDMA_INTR_RX_READY_BUF6 0x00000100
#define UDMA_INTR_RX_READY_BUF5 0x00000080
#define UDMA_INTR_RX_READY_BUF4 0x00000040
#define UDMA_INTR_RX_READY_BUF3 0x00000020
#define UDMA_INTR_RX_READY_BUF2 0x00000010
#define UDMA_INTR_RX_READY_BUF1 0x00000008
#define UDMA_INTR_RX_READY_BUF0 0x00000004
#define UDMA_INTR_RX_READY_MASK 0x000003fc
#define UDMA_INTR_RX_READY_SHIFT 2
#define UDMA_INTR_RX_ABORT 0x00000002
#define UDMA_INTR_RX_DONE 0x00000001
#define UDMA_INTR_SET 0x04
#define UDMA_INTR_CLEAR 0x08
#define UDMA_INTR_MASK_STATUS 0x0c
#define UDMA_INTR_MASK_SET 0x10
#define UDMA_INTR_MASK_CLEAR 0x14
#define UDMA_RX_INTERRUPTS ( \
UDMA_INTR_RX_ERROR | \
UDMA_INTR_RX_TIMEOUT | \
UDMA_INTR_RX_READY_BUF0 | \
UDMA_INTR_RX_READY_BUF1 | \
UDMA_INTR_RX_READY_BUF2 | \
UDMA_INTR_RX_READY_BUF3 | \
UDMA_INTR_RX_READY_BUF4 | \
UDMA_INTR_RX_READY_BUF5 | \
UDMA_INTR_RX_READY_BUF6 | \
UDMA_INTR_RX_READY_BUF7 | \
UDMA_INTR_RX_ABORT | \
UDMA_INTR_RX_DONE)
#define UDMA_RX_ERR_INTERRUPTS ( \
UDMA_INTR_RX_ERROR | \
UDMA_INTR_RX_TIMEOUT | \
UDMA_INTR_RX_ABORT | \
UDMA_INTR_RX_DONE)
#define UDMA_TX_INTERRUPTS ( \
UDMA_INTR_TX_ABORT | \
UDMA_INTR_TX_DONE)
#define UDMA_IS_RX_INTERRUPT(status) ((status) & UDMA_RX_INTERRUPTS)
#define UDMA_IS_TX_INTERRUPT(status) ((status) & UDMA_TX_INTERRUPTS)
/* Current devices have 8 sets of RX buffer registers */
#define UDMA_RX_BUFS_COUNT 8
#define UDMA_RX_BUFS_REG_OFFSET (UDMA_RX_BUF1_PTR_LO - UDMA_RX_BUF0_PTR_LO)
#define UDMA_RX_BUFx_PTR_LO(x) (UDMA_RX_BUF0_PTR_LO + \
((x) * UDMA_RX_BUFS_REG_OFFSET))
#define UDMA_RX_BUFx_PTR_HI(x) (UDMA_RX_BUF0_PTR_HI + \
((x) * UDMA_RX_BUFS_REG_OFFSET))
#define UDMA_RX_BUFx_STATUS(x) (UDMA_RX_BUF0_STATUS + \
((x) * UDMA_RX_BUFS_REG_OFFSET))
#define UDMA_RX_BUFx_DATA_LEN(x) (UDMA_RX_BUF0_DATA_LEN + \
((x) * UDMA_RX_BUFS_REG_OFFSET))
/* Current devices have 2 sets of TX buffer registers */
#define UDMA_TX_BUFS_COUNT 2
#define UDMA_TX_BUFS_REG_OFFSET (UDMA_TX_BUF1_PTR_LO - UDMA_TX_BUF0_PTR_LO)
#define UDMA_TX_BUFx_PTR_LO(x) (UDMA_TX_BUF0_PTR_LO + \
((x) * UDMA_TX_BUFS_REG_OFFSET))
#define UDMA_TX_BUFx_PTR_HI(x) (UDMA_TX_BUF0_PTR_HI + \
((x) * UDMA_TX_BUFS_REG_OFFSET))
#define UDMA_TX_BUFx_STATUS(x) (UDMA_TX_BUF0_STATUS + \
((x) * UDMA_TX_BUFS_REG_OFFSET))
#define UDMA_TX_BUFx_DATA_LEN(x) (UDMA_TX_BUF0_DATA_LEN + \
((x) * UDMA_TX_BUFS_REG_OFFSET))
#define UDMA_TX_BUFx_DATA_SENT(x) (UDMA_TX_BUF0_DATA_SENT + \
((x) * UDMA_TX_BUFS_REG_OFFSET))
#define REGS_8250 0
#define REGS_DMA_RX 1
#define REGS_DMA_TX 2
#define REGS_DMA_ISR 3
#define REGS_DMA_ARB 4
#define REGS_MAX 5
#define TX_BUF_SIZE 4096
#define RX_BUF_SIZE 4096
#define RX_BUFS_COUNT 2
#define KHZ 1000
#define MHZ(x) ((x) * KHZ * KHZ)
static const u32 brcmstb_rate_table[] = {
MHZ(81),
MHZ(108),
MHZ(64), /* Actually 64285715 for some chips */
MHZ(48),
};
static const u32 brcmstb_rate_table_7278[] = {
MHZ(81),
MHZ(108),
0,
MHZ(48),
};
struct brcmuart_priv {
int line;
struct clk *baud_mux_clk;
unsigned long default_mux_rate;
u32 real_rates[ARRAY_SIZE(brcmstb_rate_table)];
const u32 *rate_table;
ktime_t char_wait;
struct uart_port *up;
struct hrtimer hrt;
bool shutdown;
bool dma_enabled;
struct uart_8250_dma dma;
void __iomem *regs[REGS_MAX];
dma_addr_t rx_addr;
void *rx_bufs;
size_t rx_size;
int rx_next_buf;
dma_addr_t tx_addr;
void *tx_buf;
size_t tx_size;
bool tx_running;
bool rx_running;
struct dentry *debugfs_dir;
/* stats exposed through debugfs */
u64 dma_rx_partial_buf;
u64 dma_rx_full_buf;
u32 rx_bad_timeout_late_char;
u32 rx_bad_timeout_no_char;
u32 rx_missing_close_timeout;
u32 rx_err;
u32 rx_timeout;
u32 rx_abort;
u32 saved_mctrl;
};
static struct dentry *brcmuart_debugfs_root;
/*
* Register access routines
*/
static u32 udma_readl(struct brcmuart_priv *priv,
int reg_type, int offset)
{
return readl(priv->regs[reg_type] + offset);
}
static void udma_writel(struct brcmuart_priv *priv,
int reg_type, int offset, u32 value)
{
writel(value, priv->regs[reg_type] + offset);
}
static void udma_set(struct brcmuart_priv *priv,
int reg_type, int offset, u32 bits)
{
void __iomem *reg = priv->regs[reg_type] + offset;
u32 value;
value = readl(reg);
value |= bits;
writel(value, reg);
}
static void udma_unset(struct brcmuart_priv *priv,
int reg_type, int offset, u32 bits)
{
void __iomem *reg = priv->regs[reg_type] + offset;
u32 value;
value = readl(reg);
value &= ~bits;
writel(value, reg);
}
/*
* The UART DMA engine hardware can be used by multiple UARTS, but
* only one at a time. Sharing is not currently supported so
* the first UART to request the DMA engine will get it and any
* subsequent requests by other UARTS will fail.
*/
static int brcmuart_arbitration(struct brcmuart_priv *priv, bool acquire)
{
u32 rx_grant;
u32 tx_grant;
int waits;
int ret = 0;
if (acquire) {
udma_set(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ);
udma_set(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ);
waits = 1;
while (1) {
rx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_RX);
tx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_TX);
if (rx_grant & tx_grant & UDMA_ARB_GRANT)
return 0;
if (waits-- == 0)
break;
msleep(1);
}
ret = 1;
}
udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ);
udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ);
return ret;
}
static void brcmuart_init_dma_hardware(struct brcmuart_priv *priv)
{
u32 daddr;
u32 value;
int x;
/* Start with all interrupts disabled */
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, 0xffffffff);
udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_SIZE, RX_BUF_SIZE);
/*
* Setup buffer close to happen when 32 character times have
* elapsed since the last character was received.
*/
udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_CLOSE, 16*10*32);
value = (RX_BUFS_COUNT << UDMA_RX_CTRL_NUM_BUF_USED_SHIFT)
| UDMA_RX_CTRL_BUF_CLOSE_MODE
| UDMA_RX_CTRL_BUF_CLOSE_ENA;
udma_writel(priv, REGS_DMA_RX, UDMA_RX_CTRL, value);
udma_writel(priv, REGS_DMA_RX, UDMA_RX_BLOCKOUT_COUNTER, 0);
daddr = priv->rx_addr;
for (x = 0; x < RX_BUFS_COUNT; x++) {
/* Set RX transfer length to 0 for unknown */
udma_writel(priv, REGS_DMA_RX, UDMA_RX_TRANSFER_LEN, 0);
udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_LO(x),
lower_32_bits(daddr));
udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_HI(x),
upper_32_bits(daddr));
daddr += RX_BUF_SIZE;
}
daddr = priv->tx_addr;
udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_LO(0),
lower_32_bits(daddr));
udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_HI(0),
upper_32_bits(daddr));
udma_writel(priv, REGS_DMA_TX, UDMA_TX_CTRL,
UDMA_TX_CTRL_NUM_BUF_USED_1);
/* clear all interrupts then enable them */
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, 0xffffffff);
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,
UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);
}
static void start_rx_dma(struct uart_8250_port *p)
{
struct brcmuart_priv *priv = p->port.private_data;
int x;
udma_unset(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA);
/* Clear the RX ready bit for all buffers */
for (x = 0; x < RX_BUFS_COUNT; x++)
udma_unset(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(x),
UDMA_RX_BUFX_STATUS_DATA_RDY);
/* always start with buffer 0 */
udma_unset(priv, REGS_DMA_RX, UDMA_RX_STATUS,
UDMA_RX_STATUS_ACTIVE_BUF_MASK);
priv->rx_next_buf = 0;
udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA);
priv->rx_running = true;
}
static void stop_rx_dma(struct uart_8250_port *p)
{
struct brcmuart_priv *priv = p->port.private_data;
/* If RX is running, set the RX ABORT */
if (priv->rx_running)
udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ABORT);
}
static int stop_tx_dma(struct uart_8250_port *p)
{
struct brcmuart_priv *priv = p->port.private_data;
u32 value;
/* If TX is running, set the TX ABORT */
value = udma_readl(priv, REGS_DMA_TX, UDMA_TX_CTRL);
if (value & UDMA_TX_CTRL_ENA)
udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ABORT);
priv->tx_running = false;
return 0;
}
/*
* NOTE: printk's in this routine will hang the system if this is
* the console tty
*/
static int brcmuart_tx_dma(struct uart_8250_port *p)
{
struct brcmuart_priv *priv = p->port.private_data;
struct circ_buf *xmit = &p->port.state->xmit;
u32 tx_size;
if (uart_tx_stopped(&p->port) || priv->tx_running ||
uart_circ_empty(xmit)) {
return 0;
}
tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
priv->dma.tx_err = 0;
memcpy(priv->tx_buf, &xmit->buf[xmit->tail], tx_size);
uart_xmit_advance(&p->port, tx_size);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&p->port);
udma_writel(priv, REGS_DMA_TX, UDMA_TX_TRANSFER_LEN, tx_size);
udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUF0_DATA_LEN, tx_size);
udma_unset(priv, REGS_DMA_TX, UDMA_TX_BUF0_STATUS, UDMA_TX_BUFX_EMPTY);
udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ENA);
priv->tx_running = true;
return 0;
}
static void brcmuart_rx_buf_done_isr(struct uart_port *up, int index)
{
struct brcmuart_priv *priv = up->private_data;
struct tty_port *tty_port = &up->state->port;
u32 status;
u32 length;
u32 copied;
/* Make sure we're still in sync with the hardware */
status = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(index));
length = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_DATA_LEN(index));
if ((status & UDMA_RX_BUFX_STATUS_DATA_RDY) == 0) {
dev_err(up->dev, "RX done interrupt but DATA_RDY not found\n");
return;
}
if (status & (UDMA_RX_BUFX_STATUS_OVERRUN_ERR |
UDMA_RX_BUFX_STATUS_FRAME_ERR |
UDMA_RX_BUFX_STATUS_PARITY_ERR)) {
if (status & UDMA_RX_BUFX_STATUS_OVERRUN_ERR) {
up->icount.overrun++;
dev_warn(up->dev, "RX OVERRUN Error\n");
}
if (status & UDMA_RX_BUFX_STATUS_FRAME_ERR) {
up->icount.frame++;
dev_warn(up->dev, "RX FRAMING Error\n");
}
if (status & UDMA_RX_BUFX_STATUS_PARITY_ERR) {
up->icount.parity++;
dev_warn(up->dev, "RX PARITY Error\n");
}
}
copied = (u32)tty_insert_flip_string(
tty_port,
priv->rx_bufs + (index * RX_BUF_SIZE),
length);
if (copied != length) {
dev_warn(up->dev, "Flip buffer overrun of %d bytes\n",
length - copied);
up->icount.overrun += length - copied;
}
up->icount.rx += length;
if (status & UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED)
priv->dma_rx_partial_buf++;
else if (length != RX_BUF_SIZE)
/*
* This is a bug in the controller that doesn't cause
* any problems but will be fixed in the future.
*/
priv->rx_missing_close_timeout++;
else
priv->dma_rx_full_buf++;
tty_flip_buffer_push(tty_port);
}
static void brcmuart_rx_isr(struct uart_port *up, u32 rx_isr)
{
struct brcmuart_priv *priv = up->private_data;
struct device *dev = up->dev;
u32 rx_done_isr;
u32 check_isr;
rx_done_isr = (rx_isr & UDMA_INTR_RX_READY_MASK);
while (rx_done_isr) {
check_isr = UDMA_INTR_RX_READY_BUF0 << priv->rx_next_buf;
if (check_isr & rx_done_isr) {
brcmuart_rx_buf_done_isr(up, priv->rx_next_buf);
} else {
dev_err(dev,
"RX buffer ready out of sequence, restarting RX DMA\n");
start_rx_dma(up_to_u8250p(up));
break;
}
if (rx_isr & UDMA_RX_ERR_INTERRUPTS) {
if (rx_isr & UDMA_INTR_RX_ERROR)
priv->rx_err++;
if (rx_isr & UDMA_INTR_RX_TIMEOUT) {
priv->rx_timeout++;
dev_err(dev, "RX TIMEOUT Error\n");
}
if (rx_isr & UDMA_INTR_RX_ABORT)
priv->rx_abort++;
priv->rx_running = false;
}
/* If not ABORT, re-enable RX buffer */
if (!(rx_isr & UDMA_INTR_RX_ABORT))
udma_unset(priv, REGS_DMA_RX,
UDMA_RX_BUFx_STATUS(priv->rx_next_buf),
UDMA_RX_BUFX_STATUS_DATA_RDY);
rx_done_isr &= ~check_isr;
priv->rx_next_buf++;
if (priv->rx_next_buf == RX_BUFS_COUNT)
priv->rx_next_buf = 0;
}
}
static void brcmuart_tx_isr(struct uart_port *up, u32 isr)
{
struct brcmuart_priv *priv = up->private_data;
struct device *dev = up->dev;
struct uart_8250_port *port_8250 = up_to_u8250p(up);
struct circ_buf *xmit = &port_8250->port.state->xmit;
if (isr & UDMA_INTR_TX_ABORT) {
if (priv->tx_running)
dev_err(dev, "Unexpected TX_ABORT interrupt\n");
return;
}
priv->tx_running = false;
if (!uart_circ_empty(xmit) && !uart_tx_stopped(up))
brcmuart_tx_dma(port_8250);
}
static irqreturn_t brcmuart_isr(int irq, void *dev_id)
{
struct uart_port *up = dev_id;
struct device *dev = up->dev;
struct brcmuart_priv *priv = up->private_data;
unsigned long flags;
u32 interrupts;
u32 rval;
u32 tval;
interrupts = udma_readl(priv, REGS_DMA_ISR, UDMA_INTR_STATUS);
if (interrupts == 0)
return IRQ_NONE;
spin_lock_irqsave(&up->lock, flags);
/* Clear all interrupts */
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, interrupts);
rval = UDMA_IS_RX_INTERRUPT(interrupts);
if (rval)
brcmuart_rx_isr(up, rval);
tval = UDMA_IS_TX_INTERRUPT(interrupts);
if (tval)
brcmuart_tx_isr(up, tval);
if ((rval | tval) == 0)
dev_warn(dev, "Spurious interrupt: 0x%x\n", interrupts);
spin_unlock_irqrestore(&up->lock, flags);
return IRQ_HANDLED;
}
static int brcmuart_startup(struct uart_port *port)
{
int res;
struct uart_8250_port *up = up_to_u8250p(port);
struct brcmuart_priv *priv = up->port.private_data;
priv->shutdown = false;
/*
* prevent serial8250_do_startup() from allocating non-existent
* DMA resources
*/
up->dma = NULL;
res = serial8250_do_startup(port);
if (!priv->dma_enabled)
return res;
/*
* Disable the Receive Data Interrupt because the DMA engine
* will handle this.
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irq(&port->lock);
up->ier &= ~UART_IER_RDI;
serial_port_out(port, UART_IER, up->ier);
spin_unlock_irq(&port->lock);
priv->tx_running = false;
priv->dma.rx_dma = NULL;
priv->dma.tx_dma = brcmuart_tx_dma;
up->dma = &priv->dma;
brcmuart_init_dma_hardware(priv);
start_rx_dma(up);
return res;
}
static void brcmuart_shutdown(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct brcmuart_priv *priv = up->port.private_data;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
priv->shutdown = true;
if (priv->dma_enabled) {
stop_rx_dma(up);
stop_tx_dma(up);
/* disable all interrupts */
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET,
UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS);
}
/*
* prevent serial8250_do_shutdown() from trying to free
* DMA resources that we never alloc'd for this driver.
*/
up->dma = NULL;
spin_unlock_irqrestore(&port->lock, flags);
serial8250_do_shutdown(port);
}
/*
* Not all clocks run at the exact specified rate, so set each requested
* rate and then get the actual rate.
*/
static void init_real_clk_rates(struct device *dev, struct brcmuart_priv *priv)
{
int x;
int rc;
priv->default_mux_rate = clk_get_rate(priv->baud_mux_clk);
for (x = 0; x < ARRAY_SIZE(priv->real_rates); x++) {
if (priv->rate_table[x] == 0) {
priv->real_rates[x] = 0;
continue;
}
rc = clk_set_rate(priv->baud_mux_clk, priv->rate_table[x]);
if (rc) {
dev_err(dev, "Error selecting BAUD MUX clock for %u\n",
priv->rate_table[x]);
priv->real_rates[x] = priv->rate_table[x];
} else {
priv->real_rates[x] = clk_get_rate(priv->baud_mux_clk);
}
}
clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate);
}
static void set_clock_mux(struct uart_port *up, struct brcmuart_priv *priv,
u32 baud)
{
u32 percent;
u32 best_percent = UINT_MAX;
u32 quot;
u32 best_quot = 1;
u32 rate;
int best_index = -1;
u64 hires_rate;
u64 hires_baud;
u64 hires_err;
int rc;
int i;
int real_baud;
/* If the Baud Mux Clock was not specified, just return */
if (priv->baud_mux_clk == NULL)
return;
/* Find the closest match for specified baud */
for (i = 0; i < ARRAY_SIZE(priv->real_rates); i++) {
if (priv->real_rates[i] == 0)
continue;
rate = priv->real_rates[i] / 16;
quot = DIV_ROUND_CLOSEST(rate, baud);
if (!quot)
continue;
/* increase resolution to get xx.xx percent */
hires_rate = (u64)rate * 10000;
hires_baud = (u64)baud * 10000;
hires_err = div_u64(hires_rate, (u64)quot);
/* get the delta */
if (hires_err > hires_baud)
hires_err = (hires_err - hires_baud);
else
hires_err = (hires_baud - hires_err);
percent = (unsigned long)DIV_ROUND_CLOSEST_ULL(hires_err, baud);
dev_dbg(up->dev,
"Baud rate: %u, MUX Clk: %u, Error: %u.%u%%\n",
baud, priv->real_rates[i], percent / 100,
percent % 100);
if (percent < best_percent) {
best_percent = percent;
best_index = i;
best_quot = quot;
}
}
if (best_index == -1) {
dev_err(up->dev, "Error, %d BAUD rate is too fast.\n", baud);
return;
}
rate = priv->real_rates[best_index];
rc = clk_set_rate(priv->baud_mux_clk, rate);
if (rc)
dev_err(up->dev, "Error selecting BAUD MUX clock\n");
/* Error over 3 percent will cause data errors */
if (best_percent > 300)
dev_err(up->dev, "Error, baud: %d has %u.%u%% error\n",
baud, percent / 100, percent % 100);
real_baud = rate / 16 / best_quot;
dev_dbg(up->dev, "Selecting BAUD MUX rate: %u\n", rate);
dev_dbg(up->dev, "Requested baud: %u, Actual baud: %u\n",
baud, real_baud);
/* calc nanoseconds for 1.5 characters time at the given baud rate */
i = NSEC_PER_SEC / real_baud / 10;
i += (i / 2);
priv->char_wait = ns_to_ktime(i);
up->uartclk = rate;
}
static void brcmstb_set_termios(struct uart_port *up,
struct ktermios *termios,
const struct ktermios *old)
{
struct uart_8250_port *p8250 = up_to_u8250p(up);
struct brcmuart_priv *priv = up->private_data;
if (priv->dma_enabled)
stop_rx_dma(p8250);
set_clock_mux(up, priv, tty_termios_baud_rate(termios));
serial8250_do_set_termios(up, termios, old);
if (p8250->mcr & UART_MCR_AFE)
p8250->port.status |= UPSTAT_AUTOCTS;
if (priv->dma_enabled)
start_rx_dma(p8250);
}
static int brcmuart_handle_irq(struct uart_port *p)
{
unsigned int iir = serial_port_in(p, UART_IIR);
struct brcmuart_priv *priv = p->private_data;
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int status;
unsigned long flags;
unsigned int ier;
unsigned int mcr;
int handled = 0;
/*
* There's a bug in some 8250 cores where we get a timeout
* interrupt but there is no data ready.
*/
if (((iir & UART_IIR_ID) == UART_IIR_RX_TIMEOUT) && !(priv->shutdown)) {
spin_lock_irqsave(&p->lock, flags);
status = serial_port_in(p, UART_LSR);
if ((status & UART_LSR_DR) == 0) {
ier = serial_port_in(p, UART_IER);
/*
* if Receive Data Interrupt is enabled and
* we're uing hardware flow control, deassert
* RTS and wait for any chars in the pipline to
* arrive and then check for DR again.
*/
if ((ier & UART_IER_RDI) && (up->mcr & UART_MCR_AFE)) {
ier &= ~(UART_IER_RLSI | UART_IER_RDI);
serial_port_out(p, UART_IER, ier);
mcr = serial_port_in(p, UART_MCR);
mcr &= ~UART_MCR_RTS;
serial_port_out(p, UART_MCR, mcr);
hrtimer_start(&priv->hrt, priv->char_wait,
HRTIMER_MODE_REL);
} else {
serial_port_in(p, UART_RX);
}
handled = 1;
}
spin_unlock_irqrestore(&p->lock, flags);
if (handled)
return 1;
}
return serial8250_handle_irq(p, iir);
}
static enum hrtimer_restart brcmuart_hrtimer_func(struct hrtimer *t)
{
struct brcmuart_priv *priv = container_of(t, struct brcmuart_priv, hrt);
struct uart_port *p = priv->up;
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int status;
unsigned long flags;
if (priv->shutdown)
return HRTIMER_NORESTART;
spin_lock_irqsave(&p->lock, flags);
status = serial_port_in(p, UART_LSR);
/*
* If a character did not arrive after the timeout, clear the false
* receive timeout.
*/
if ((status & UART_LSR_DR) == 0) {
serial_port_in(p, UART_RX);
priv->rx_bad_timeout_no_char++;
} else {
priv->rx_bad_timeout_late_char++;
}
/* re-enable receive unless upper layer has disabled it */
if ((up->ier & (UART_IER_RLSI | UART_IER_RDI)) ==
(UART_IER_RLSI | UART_IER_RDI)) {
status = serial_port_in(p, UART_IER);
status |= (UART_IER_RLSI | UART_IER_RDI);
serial_port_out(p, UART_IER, status);
status = serial_port_in(p, UART_MCR);
status |= UART_MCR_RTS;
serial_port_out(p, UART_MCR, status);
}
spin_unlock_irqrestore(&p->lock, flags);
return HRTIMER_NORESTART;
}
static const struct of_device_id brcmuart_dt_ids[] = {
{
.compatible = "brcm,bcm7278-uart",
.data = brcmstb_rate_table_7278,
},
{
.compatible = "brcm,bcm7271-uart",
.data = brcmstb_rate_table,
},
{},
};
MODULE_DEVICE_TABLE(of, brcmuart_dt_ids);
static void brcmuart_free_bufs(struct device *dev, struct brcmuart_priv *priv)
{
if (priv->rx_bufs)
dma_free_coherent(dev, priv->rx_size, priv->rx_bufs,
priv->rx_addr);
if (priv->tx_buf)
dma_free_coherent(dev, priv->tx_size, priv->tx_buf,
priv->tx_addr);
}
static void brcmuart_throttle(struct uart_port *port)
{
struct brcmuart_priv *priv = port->private_data;
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, UDMA_RX_INTERRUPTS);
}
static void brcmuart_unthrottle(struct uart_port *port)
{
struct brcmuart_priv *priv = port->private_data;
udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR,
UDMA_RX_INTERRUPTS);
}
static int debugfs_stats_show(struct seq_file *s, void *unused)
{
struct brcmuart_priv *priv = s->private;
seq_printf(s, "rx_err:\t\t\t\t%u\n",
priv->rx_err);
seq_printf(s, "rx_timeout:\t\t\t%u\n",
priv->rx_timeout);
seq_printf(s, "rx_abort:\t\t\t%u\n",
priv->rx_abort);
seq_printf(s, "rx_bad_timeout_late_char:\t%u\n",
priv->rx_bad_timeout_late_char);
seq_printf(s, "rx_bad_timeout_no_char:\t\t%u\n",
priv->rx_bad_timeout_no_char);
seq_printf(s, "rx_missing_close_timeout:\t%u\n",
priv->rx_missing_close_timeout);
if (priv->dma_enabled) {
seq_printf(s, "dma_rx_partial_buf:\t\t%llu\n",
priv->dma_rx_partial_buf);
seq_printf(s, "dma_rx_full_buf:\t\t%llu\n",
priv->dma_rx_full_buf);
}
return 0;
}
DEFINE_SHOW_ATTRIBUTE(debugfs_stats);
static void brcmuart_init_debugfs(struct brcmuart_priv *priv,
const char *device)
{
priv->debugfs_dir = debugfs_create_dir(device, brcmuart_debugfs_root);
debugfs_create_file("stats", 0444, priv->debugfs_dir, priv,
&debugfs_stats_fops);
}
static int brcmuart_probe(struct platform_device *pdev)
{
struct resource *regs;
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *of_id = NULL;
struct uart_8250_port *new_port;
struct device *dev = &pdev->dev;
struct brcmuart_priv *priv;
struct clk *baud_mux_clk;
struct uart_8250_port up;
int irq;
void __iomem *membase = NULL;
resource_size_t mapbase = 0;
u32 clk_rate = 0;
int ret;
int x;
int dma_irq;
static const char * const reg_names[REGS_MAX] = {
"uart", "dma_rx", "dma_tx", "dma_intr2", "dma_arb"
};
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
priv = devm_kzalloc(dev, sizeof(struct brcmuart_priv),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
of_id = of_match_node(brcmuart_dt_ids, np);
if (!of_id || !of_id->data)
priv->rate_table = brcmstb_rate_table;
else
priv->rate_table = of_id->data;
for (x = 0; x < REGS_MAX; x++) {
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
reg_names[x]);
if (!regs)
break;
priv->regs[x] = devm_ioremap(dev, regs->start,
resource_size(regs));
if (!priv->regs[x])
return -ENOMEM;
if (x == REGS_8250) {
mapbase = regs->start;
membase = priv->regs[x];
}
}
/* We should have just the uart base registers or all the registers */
if (x != 1 && x != REGS_MAX) {
dev_warn(dev, "%s registers not specified\n", reg_names[x]);
return -EINVAL;
}
/* if the DMA registers were specified, try to enable DMA */
if (x > REGS_DMA_RX) {
if (brcmuart_arbitration(priv, 1) == 0) {
u32 txrev = 0;
u32 rxrev = 0;
txrev = udma_readl(priv, REGS_DMA_RX, UDMA_RX_REVISION);
rxrev = udma_readl(priv, REGS_DMA_TX, UDMA_TX_REVISION);
if ((txrev >= UDMA_TX_REVISION_REQUIRED) &&
(rxrev >= UDMA_RX_REVISION_REQUIRED)) {
/* Enable the use of the DMA hardware */
priv->dma_enabled = true;
} else {
brcmuart_arbitration(priv, 0);
dev_err(dev,
"Unsupported DMA Hardware Revision\n");
}
} else {
dev_err(dev,
"Timeout arbitrating for UART DMA hardware\n");
}
}
of_property_read_u32(np, "clock-frequency", &clk_rate);
/* See if a Baud clock has been specified */
baud_mux_clk = devm_clk_get(dev, "sw_baud");
if (IS_ERR(baud_mux_clk)) {
if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto release_dma;
}
dev_dbg(dev, "BAUD MUX clock not specified\n");
} else {
dev_dbg(dev, "BAUD MUX clock found\n");
ret = clk_prepare_enable(baud_mux_clk);
if (ret)
goto release_dma;
priv->baud_mux_clk = baud_mux_clk;
init_real_clk_rates(dev, priv);
clk_rate = priv->default_mux_rate;
}
if (clk_rate == 0) {
dev_err(dev, "clock-frequency or clk not defined\n");
ret = -EINVAL;
goto err_clk_disable;
}
dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");
memset(&up, 0, sizeof(up));
up.port.type = PORT_BCM7271;
up.port.uartclk = clk_rate;
up.port.dev = dev;
up.port.mapbase = mapbase;
up.port.membase = membase;
up.port.irq = irq;
up.port.handle_irq = brcmuart_handle_irq;
up.port.regshift = 2;
up.port.iotype = of_device_is_big_endian(np) ?
UPIO_MEM32BE : UPIO_MEM32;
up.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF
| UPF_FIXED_PORT | UPF_FIXED_TYPE;
up.port.dev = dev;
up.port.private_data = priv;
/* Check for a fixed line number */
ret = of_alias_get_id(np, "serial");
if (ret >= 0)
up.port.line = ret;
/* setup HR timer */
hrtimer_init(&priv->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
priv->hrt.function = brcmuart_hrtimer_func;
up.port.shutdown = brcmuart_shutdown;
up.port.startup = brcmuart_startup;
up.port.throttle = brcmuart_throttle;
up.port.unthrottle = brcmuart_unthrottle;
up.port.set_termios = brcmstb_set_termios;
if (priv->dma_enabled) {
priv->rx_size = RX_BUF_SIZE * RX_BUFS_COUNT;
priv->rx_bufs = dma_alloc_coherent(dev,
priv->rx_size,
&priv->rx_addr, GFP_KERNEL);
if (!priv->rx_bufs) {
ret = -ENOMEM;
goto err;
}
priv->tx_size = UART_XMIT_SIZE;
priv->tx_buf = dma_alloc_coherent(dev,
priv->tx_size,
&priv->tx_addr, GFP_KERNEL);
if (!priv->tx_buf) {
ret = -ENOMEM;
goto err;
}
}
ret = serial8250_register_8250_port(&up);
if (ret < 0) {
dev_err(dev, "unable to register 8250 port\n");
goto err;
}
priv->line = ret;
new_port = serial8250_get_port(ret);
priv->up = &new_port->port;
if (priv->dma_enabled) {
dma_irq = platform_get_irq_byname(pdev, "dma");
if (dma_irq < 0) {
ret = dma_irq;
dev_err(dev, "no IRQ resource info\n");
goto err1;
}
ret = devm_request_irq(dev, dma_irq, brcmuart_isr,
IRQF_SHARED, "uart DMA irq", &new_port->port);
if (ret) {
dev_err(dev, "unable to register IRQ handler\n");
goto err1;
}
}
platform_set_drvdata(pdev, priv);
brcmuart_init_debugfs(priv, dev_name(&pdev->dev));
return 0;
err1:
serial8250_unregister_port(priv->line);
err:
brcmuart_free_bufs(dev, priv);
err_clk_disable:
clk_disable_unprepare(baud_mux_clk);
release_dma:
if (priv->dma_enabled)
brcmuart_arbitration(priv, 0);
return ret;
}
static int brcmuart_remove(struct platform_device *pdev)
{
struct brcmuart_priv *priv = platform_get_drvdata(pdev);
debugfs_remove_recursive(priv->debugfs_dir);
hrtimer_cancel(&priv->hrt);
serial8250_unregister_port(priv->line);
brcmuart_free_bufs(&pdev->dev, priv);
clk_disable_unprepare(priv->baud_mux_clk);
if (priv->dma_enabled)
brcmuart_arbitration(priv, 0);
return 0;
}
static int __maybe_unused brcmuart_suspend(struct device *dev)
{
struct brcmuart_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
struct uart_port *port = &up->port;
unsigned long flags;
/*
* This will prevent resume from enabling RTS before the
* baud rate has been restored.
*/
spin_lock_irqsave(&port->lock, flags);
priv->saved_mctrl = port->mctrl;
port->mctrl &= ~TIOCM_RTS;
spin_unlock_irqrestore(&port->lock, flags);
serial8250_suspend_port(priv->line);
clk_disable_unprepare(priv->baud_mux_clk);
return 0;
}
static int __maybe_unused brcmuart_resume(struct device *dev)
{
struct brcmuart_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
struct uart_port *port = &up->port;
unsigned long flags;
int ret;
ret = clk_prepare_enable(priv->baud_mux_clk);
if (ret)
dev_err(dev, "Error enabling BAUD MUX clock\n");
/*
* The hardware goes back to it's default after suspend
* so get the "clk" back in sync.
*/
ret = clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate);
if (ret)
dev_err(dev, "Error restoring default BAUD MUX clock\n");
if (priv->dma_enabled) {
if (brcmuart_arbitration(priv, 1)) {
dev_err(dev, "Timeout arbitrating for DMA hardware on resume\n");
return(-EBUSY);
}
brcmuart_init_dma_hardware(priv);
start_rx_dma(serial8250_get_port(priv->line));
}
serial8250_resume_port(priv->line);
if (priv->saved_mctrl & TIOCM_RTS) {
/* Restore RTS */
spin_lock_irqsave(&port->lock, flags);
port->mctrl |= TIOCM_RTS;
port->ops->set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
}
return 0;
}
static const struct dev_pm_ops brcmuart_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(brcmuart_suspend, brcmuart_resume)
};
static struct platform_driver brcmuart_platform_driver = {
.driver = {
.name = "bcm7271-uart",
.pm = &brcmuart_dev_pm_ops,
.of_match_table = brcmuart_dt_ids,
},
.probe = brcmuart_probe,
.remove = brcmuart_remove,
};
static int __init brcmuart_init(void)
{
int ret;
brcmuart_debugfs_root = debugfs_create_dir(
brcmuart_platform_driver.driver.name, NULL);
ret = platform_driver_register(&brcmuart_platform_driver);
if (ret) {
debugfs_remove_recursive(brcmuart_debugfs_root);
return ret;
}
return 0;
}
module_init(brcmuart_init);
static void __exit brcmuart_deinit(void)
{
platform_driver_unregister(&brcmuart_platform_driver);
debugfs_remove_recursive(brcmuart_debugfs_root);
}
module_exit(brcmuart_deinit);
MODULE_AUTHOR("Al Cooper");
MODULE_DESCRIPTION("Broadcom NS16550A compatible serial port driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/8250/8250_bcm7271.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include "8250.h"
static struct plat_serial8250_port boca_data[] = {
SERIAL8250_PORT(0x100, 12),
SERIAL8250_PORT(0x108, 12),
SERIAL8250_PORT(0x110, 12),
SERIAL8250_PORT(0x118, 12),
SERIAL8250_PORT(0x120, 12),
SERIAL8250_PORT(0x128, 12),
SERIAL8250_PORT(0x130, 12),
SERIAL8250_PORT(0x138, 12),
SERIAL8250_PORT(0x140, 12),
SERIAL8250_PORT(0x148, 12),
SERIAL8250_PORT(0x150, 12),
SERIAL8250_PORT(0x158, 12),
SERIAL8250_PORT(0x160, 12),
SERIAL8250_PORT(0x168, 12),
SERIAL8250_PORT(0x170, 12),
SERIAL8250_PORT(0x178, 12),
{ },
};
static struct platform_device boca_device = {
.name = "serial8250",
.id = PLAT8250_DEV_BOCA,
.dev = {
.platform_data = boca_data,
},
};
static int __init boca_init(void)
{
return platform_device_register(&boca_device);
}
module_init(boca_init);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("8250 serial probe module for Boca cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_boca.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* 8250_dma.c - DMA Engine API support for 8250.c
*
* Copyright (C) 2013 Intel Corporation
*/
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_reg.h>
#include <linux/dma-mapping.h>
#include "8250.h"
static void __dma_tx_complete(void *param)
{
struct uart_8250_port *p = param;
struct uart_8250_dma *dma = p->dma;
struct circ_buf *xmit = &p->port.state->xmit;
unsigned long flags;
int ret;
dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
spin_lock_irqsave(&p->port.lock, flags);
dma->tx_running = 0;
uart_xmit_advance(&p->port, dma->tx_size);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&p->port);
ret = serial8250_tx_dma(p);
if (ret || !dma->tx_running)
serial8250_set_THRI(p);
spin_unlock_irqrestore(&p->port.lock, flags);
}
static void __dma_rx_complete(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
struct tty_port *tty_port = &p->port.state->port;
struct dma_tx_state state;
enum dma_status dma_status;
int count;
/*
* New DMA Rx can be started during the completion handler before it
* could acquire port's lock and it might still be ongoing. Don't to
* anything in such case.
*/
dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
if (dma_status == DMA_IN_PROGRESS)
return;
count = dma->rx_size - state.residue;
tty_insert_flip_string(tty_port, dma->rx_buf, count);
p->port.icount.rx += count;
dma->rx_running = 0;
tty_flip_buffer_push(tty_port);
}
static void dma_rx_complete(void *param)
{
struct uart_8250_port *p = param;
struct uart_8250_dma *dma = p->dma;
unsigned long flags;
spin_lock_irqsave(&p->port.lock, flags);
if (dma->rx_running)
__dma_rx_complete(p);
/*
* Cannot be combined with the previous check because __dma_rx_complete()
* changes dma->rx_running.
*/
if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR))
p->dma->rx_dma(p);
spin_unlock_irqrestore(&p->port.lock, flags);
}
int serial8250_tx_dma(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
struct circ_buf *xmit = &p->port.state->xmit;
struct dma_async_tx_descriptor *desc;
struct uart_port *up = &p->port;
int ret;
if (dma->tx_running) {
if (up->x_char) {
dmaengine_pause(dma->txchan);
uart_xchar_out(up, UART_TX);
dmaengine_resume(dma->txchan);
}
return 0;
} else if (up->x_char) {
uart_xchar_out(up, UART_TX);
}
if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
/* We have been called from __dma_tx_complete() */
return 0;
}
dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
serial8250_do_prepare_tx_dma(p);
desc = dmaengine_prep_slave_single(dma->txchan,
dma->tx_addr + xmit->tail,
dma->tx_size, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
ret = -EBUSY;
goto err;
}
dma->tx_running = 1;
desc->callback = __dma_tx_complete;
desc->callback_param = p;
dma->tx_cookie = dmaengine_submit(desc);
dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
dma_async_issue_pending(dma->txchan);
serial8250_clear_THRI(p);
dma->tx_err = 0;
return 0;
err:
dma->tx_err = 1;
return ret;
}
int serial8250_rx_dma(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
struct dma_async_tx_descriptor *desc;
if (dma->rx_running)
return 0;
serial8250_do_prepare_rx_dma(p);
desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
dma->rx_size, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc)
return -EBUSY;
dma->rx_running = 1;
desc->callback = dma_rx_complete;
desc->callback_param = p;
dma->rx_cookie = dmaengine_submit(desc);
dma_async_issue_pending(dma->rxchan);
return 0;
}
void serial8250_rx_dma_flush(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
if (dma->rx_running) {
dmaengine_pause(dma->rxchan);
__dma_rx_complete(p);
dmaengine_terminate_async(dma->rxchan);
}
}
EXPORT_SYMBOL_GPL(serial8250_rx_dma_flush);
int serial8250_request_dma(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
phys_addr_t rx_dma_addr = dma->rx_dma_addr ?
dma->rx_dma_addr : p->port.mapbase;
phys_addr_t tx_dma_addr = dma->tx_dma_addr ?
dma->tx_dma_addr : p->port.mapbase;
dma_cap_mask_t mask;
struct dma_slave_caps caps;
int ret;
/* Default slave configuration parameters */
dma->rxconf.direction = DMA_DEV_TO_MEM;
dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dma->rxconf.src_addr = rx_dma_addr + UART_RX;
dma->txconf.direction = DMA_MEM_TO_DEV;
dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
dma->txconf.dst_addr = tx_dma_addr + UART_TX;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
/* Get a channel for RX */
dma->rxchan = dma_request_slave_channel_compat(mask,
dma->fn, dma->rx_param,
p->port.dev, "rx");
if (!dma->rxchan)
return -ENODEV;
/* 8250 rx dma requires dmaengine driver to support pause/terminate */
ret = dma_get_slave_caps(dma->rxchan, &caps);
if (ret)
goto release_rx;
if (!caps.cmd_pause || !caps.cmd_terminate ||
caps.residue_granularity == DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
ret = -EINVAL;
goto release_rx;
}
dmaengine_slave_config(dma->rxchan, &dma->rxconf);
/* Get a channel for TX */
dma->txchan = dma_request_slave_channel_compat(mask,
dma->fn, dma->tx_param,
p->port.dev, "tx");
if (!dma->txchan) {
ret = -ENODEV;
goto release_rx;
}
/* 8250 tx dma requires dmaengine driver to support terminate */
ret = dma_get_slave_caps(dma->txchan, &caps);
if (ret)
goto err;
if (!caps.cmd_terminate) {
ret = -EINVAL;
goto err;
}
dmaengine_slave_config(dma->txchan, &dma->txconf);
/* RX buffer */
if (!dma->rx_size)
dma->rx_size = PAGE_SIZE;
dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
&dma->rx_addr, GFP_KERNEL);
if (!dma->rx_buf) {
ret = -ENOMEM;
goto err;
}
/* TX buffer */
dma->tx_addr = dma_map_single(dma->txchan->device->dev,
p->port.state->xmit.buf,
UART_XMIT_SIZE,
DMA_TO_DEVICE);
if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) {
dma_free_coherent(dma->rxchan->device->dev, dma->rx_size,
dma->rx_buf, dma->rx_addr);
ret = -ENOMEM;
goto err;
}
dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
return 0;
err:
dma_release_channel(dma->txchan);
release_rx:
dma_release_channel(dma->rxchan);
return ret;
}
EXPORT_SYMBOL_GPL(serial8250_request_dma);
void serial8250_release_dma(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
if (!dma)
return;
/* Release RX resources */
dmaengine_terminate_sync(dma->rxchan);
dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
dma->rx_addr);
dma_release_channel(dma->rxchan);
dma->rxchan = NULL;
/* Release TX resources */
dmaengine_terminate_sync(dma->txchan);
dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
dma_release_channel(dma->txchan);
dma->txchan = NULL;
dma->tx_running = 0;
dev_dbg_ratelimited(p->port.dev, "dma channels released\n");
}
EXPORT_SYMBOL_GPL(serial8250_release_dma);
| linux-master | drivers/tty/serial/8250/8250_dma.c |
// SPDX-License-Identifier: GPL-2.0
/*
* 8250_mid.c - Driver for UART on Intel Penwell and various other Intel SOCs
*
* Copyright (C) 2015 Intel Corporation
* Author: Heikki Krogerus <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/rational.h>
#include <linux/dma/hsu.h>
#include <linux/8250_pci.h>
#include "8250.h"
#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
#define PCI_DEVICE_ID_INTEL_CDF_UART 0x18d8
#define PCI_DEVICE_ID_INTEL_DNV_UART 0x19d8
/* Intel MID Specific registers */
#define INTEL_MID_UART_FISR 0x08
#define INTEL_MID_UART_PS 0x30
#define INTEL_MID_UART_MUL 0x34
#define INTEL_MID_UART_DIV 0x38
struct mid8250;
struct mid8250_board {
unsigned int flags;
unsigned long freq;
unsigned int base_baud;
int (*setup)(struct mid8250 *, struct uart_port *p);
void (*exit)(struct mid8250 *);
};
struct mid8250 {
int line;
int dma_index;
struct pci_dev *dma_dev;
struct uart_8250_dma dma;
struct mid8250_board *board;
struct hsu_dma_chip dma_chip;
};
/*****************************************************************************/
static int pnw_setup(struct mid8250 *mid, struct uart_port *p)
{
struct pci_dev *pdev = to_pci_dev(p->dev);
switch (pdev->device) {
case PCI_DEVICE_ID_INTEL_PNW_UART1:
mid->dma_index = 0;
break;
case PCI_DEVICE_ID_INTEL_PNW_UART2:
mid->dma_index = 1;
break;
case PCI_DEVICE_ID_INTEL_PNW_UART3:
mid->dma_index = 2;
break;
default:
return -EINVAL;
}
mid->dma_dev = pci_get_slot(pdev->bus,
PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
return 0;
}
static void pnw_exit(struct mid8250 *mid)
{
pci_dev_put(mid->dma_dev);
}
static int tng_handle_irq(struct uart_port *p)
{
struct mid8250 *mid = p->private_data;
struct uart_8250_port *up = up_to_u8250p(p);
struct hsu_dma_chip *chip;
u32 status;
int ret = 0;
int err;
chip = pci_get_drvdata(mid->dma_dev);
/* Rx DMA */
err = hsu_dma_get_status(chip, mid->dma_index * 2 + 1, &status);
if (err > 0) {
serial8250_rx_dma_flush(up);
ret |= 1;
} else if (err == 0)
ret |= hsu_dma_do_irq(chip, mid->dma_index * 2 + 1, status);
/* Tx DMA */
err = hsu_dma_get_status(chip, mid->dma_index * 2, &status);
if (err > 0)
ret |= 1;
else if (err == 0)
ret |= hsu_dma_do_irq(chip, mid->dma_index * 2, status);
/* UART */
ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
return IRQ_RETVAL(ret);
}
static int tng_setup(struct mid8250 *mid, struct uart_port *p)
{
struct pci_dev *pdev = to_pci_dev(p->dev);
int index = PCI_FUNC(pdev->devfn);
/*
* Device 0000:00:04.0 is not a real HSU port. It provides a global
* register set for all HSU ports, although it has the same PCI ID.
* Skip it here.
*/
if (index-- == 0)
return -ENODEV;
mid->dma_index = index;
mid->dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
p->handle_irq = tng_handle_irq;
return 0;
}
static void tng_exit(struct mid8250 *mid)
{
pci_dev_put(mid->dma_dev);
}
static int dnv_handle_irq(struct uart_port *p)
{
struct mid8250 *mid = p->private_data;
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int fisr = serial_port_in(p, INTEL_MID_UART_FISR);
u32 status;
int ret = 0;
int err;
if (fisr & BIT(2)) {
err = hsu_dma_get_status(&mid->dma_chip, 1, &status);
if (err > 0) {
serial8250_rx_dma_flush(up);
ret |= 1;
} else if (err == 0)
ret |= hsu_dma_do_irq(&mid->dma_chip, 1, status);
}
if (fisr & BIT(1)) {
err = hsu_dma_get_status(&mid->dma_chip, 0, &status);
if (err > 0)
ret |= 1;
else if (err == 0)
ret |= hsu_dma_do_irq(&mid->dma_chip, 0, status);
}
if (fisr & BIT(0))
ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
return IRQ_RETVAL(ret);
}
#define DNV_DMA_CHAN_OFFSET 0x80
static int dnv_setup(struct mid8250 *mid, struct uart_port *p)
{
struct hsu_dma_chip *chip = &mid->dma_chip;
struct pci_dev *pdev = to_pci_dev(p->dev);
unsigned int bar = FL_GET_BASE(mid->board->flags);
int ret;
pci_set_master(pdev);
ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
if (ret < 0)
return ret;
p->irq = pci_irq_vector(pdev, 0);
chip->dev = &pdev->dev;
chip->irq = pci_irq_vector(pdev, 0);
chip->regs = p->membase;
chip->length = pci_resource_len(pdev, bar);
chip->offset = DNV_DMA_CHAN_OFFSET;
/* Falling back to PIO mode if DMA probing fails */
ret = hsu_dma_probe(chip);
if (ret)
return 0;
mid->dma_dev = pdev;
p->handle_irq = dnv_handle_irq;
return 0;
}
static void dnv_exit(struct mid8250 *mid)
{
if (!mid->dma_dev)
return;
hsu_dma_remove(&mid->dma_chip);
}
/*****************************************************************************/
static void mid8250_set_termios(struct uart_port *p, struct ktermios *termios,
const struct ktermios *old)
{
unsigned int baud = tty_termios_baud_rate(termios);
struct mid8250 *mid = p->private_data;
unsigned short ps = 16;
unsigned long fuart = baud * ps;
unsigned long w = BIT(24) - 1;
unsigned long mul, div;
/* Gracefully handle the B0 case: fall back to B9600 */
fuart = fuart ? fuart : 9600 * 16;
if (mid->board->freq < fuart) {
/* Find prescaler value that satisfies Fuart < Fref */
if (mid->board->freq > baud)
ps = mid->board->freq / baud; /* baud rate too high */
else
ps = 1; /* PLL case */
fuart = baud * ps;
} else {
/* Get Fuart closer to Fref */
fuart *= rounddown_pow_of_two(mid->board->freq / fuart);
}
rational_best_approximation(fuart, mid->board->freq, w, w, &mul, &div);
p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
writel(div, p->membase + INTEL_MID_UART_DIV);
serial8250_do_set_termios(p, termios, old);
}
static bool mid8250_dma_filter(struct dma_chan *chan, void *param)
{
struct hsu_dma_slave *s = param;
if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
return false;
chan->private = s;
return true;
}
static int mid8250_dma_setup(struct mid8250 *mid, struct uart_8250_port *port)
{
struct uart_8250_dma *dma = &mid->dma;
struct device *dev = port->port.dev;
struct hsu_dma_slave *rx_param;
struct hsu_dma_slave *tx_param;
if (!mid->dma_dev)
return 0;
rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
if (!rx_param)
return -ENOMEM;
tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
if (!tx_param)
return -ENOMEM;
rx_param->chan_id = mid->dma_index * 2 + 1;
tx_param->chan_id = mid->dma_index * 2;
dma->rxconf.src_maxburst = 64;
dma->txconf.dst_maxburst = 64;
rx_param->dma_dev = &mid->dma_dev->dev;
tx_param->dma_dev = &mid->dma_dev->dev;
dma->fn = mid8250_dma_filter;
dma->rx_param = rx_param;
dma->tx_param = tx_param;
port->dma = dma;
return 0;
}
static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port uart;
struct mid8250 *mid;
unsigned int bar;
int ret;
ret = pcim_enable_device(pdev);
if (ret)
return ret;
mid = devm_kzalloc(&pdev->dev, sizeof(*mid), GFP_KERNEL);
if (!mid)
return -ENOMEM;
mid->board = (struct mid8250_board *)id->driver_data;
bar = FL_GET_BASE(mid->board->flags);
memset(&uart, 0, sizeof(struct uart_8250_port));
uart.port.dev = &pdev->dev;
uart.port.irq = pdev->irq;
uart.port.private_data = mid;
uart.port.type = PORT_16750;
uart.port.iotype = UPIO_MEM;
uart.port.uartclk = mid->board->base_baud * 16;
uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
uart.port.set_termios = mid8250_set_termios;
uart.port.mapbase = pci_resource_start(pdev, bar);
uart.port.membase = pcim_iomap(pdev, bar, 0);
if (!uart.port.membase)
return -ENOMEM;
ret = mid->board->setup(mid, &uart.port);
if (ret)
return ret;
ret = mid8250_dma_setup(mid, &uart);
if (ret)
goto err;
ret = serial8250_register_8250_port(&uart);
if (ret < 0)
goto err;
mid->line = ret;
pci_set_drvdata(pdev, mid);
return 0;
err:
mid->board->exit(mid);
return ret;
}
static void mid8250_remove(struct pci_dev *pdev)
{
struct mid8250 *mid = pci_get_drvdata(pdev);
serial8250_unregister_port(mid->line);
mid->board->exit(mid);
}
static const struct mid8250_board pnw_board = {
.flags = FL_BASE0,
.freq = 50000000,
.base_baud = 115200,
.setup = pnw_setup,
.exit = pnw_exit,
};
static const struct mid8250_board tng_board = {
.flags = FL_BASE0,
.freq = 38400000,
.base_baud = 1843200,
.setup = tng_setup,
.exit = tng_exit,
};
static const struct mid8250_board dnv_board = {
.flags = FL_BASE1,
.freq = 133333333,
.base_baud = 115200,
.setup = dnv_setup,
.exit = dnv_exit,
};
static const struct pci_device_id pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, PNW_UART1, &pnw_board) },
{ PCI_DEVICE_DATA(INTEL, PNW_UART2, &pnw_board) },
{ PCI_DEVICE_DATA(INTEL, PNW_UART3, &pnw_board) },
{ PCI_DEVICE_DATA(INTEL, TNG_UART, &tng_board) },
{ PCI_DEVICE_DATA(INTEL, CDF_UART, &dnv_board) },
{ PCI_DEVICE_DATA(INTEL, DNV_UART, &dnv_board) },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);
static struct pci_driver mid8250_pci_driver = {
.name = "8250_mid",
.id_table = pci_ids,
.probe = mid8250_probe,
.remove = mid8250_remove,
};
module_pci_driver(mid8250_pci_driver);
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel MID UART driver");
| linux-master | drivers/tty/serial/8250/8250_mid.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#define HUB6(card, port) \
{ \
.iobase = 0x302, \
.irq = 3, \
.uartclk = 1843200, \
.iotype = UPIO_HUB6, \
.flags = UPF_BOOT_AUTOCONF, \
.hub6 = (card) << 6 | (port) << 3 | 1, \
}
static struct plat_serial8250_port hub6_data[] = {
HUB6(0, 0),
HUB6(0, 1),
HUB6(0, 2),
HUB6(0, 3),
HUB6(0, 4),
HUB6(0, 5),
HUB6(1, 0),
HUB6(1, 1),
HUB6(1, 2),
HUB6(1, 3),
HUB6(1, 4),
HUB6(1, 5),
{ },
};
static struct platform_device hub6_device = {
.name = "serial8250",
.id = PLAT8250_DEV_HUB6,
.dev = {
.platform_data = hub6_data,
},
};
static int __init hub6_init(void)
{
return platform_device_register(&hub6_device);
}
module_init(hub6_init);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("8250 serial probe module for Hub6 cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_hub6.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Mediatek 8250 driver.
*
* Copyright (c) 2014 MundoReader S.L.
* Author: Matthias Brugger <[email protected]>
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/console.h>
#include <linux/dma-mapping.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include "8250.h"
#define MTK_UART_HIGHS 0x09 /* Highspeed register */
#define MTK_UART_SAMPLE_COUNT 0x0a /* Sample count register */
#define MTK_UART_SAMPLE_POINT 0x0b /* Sample point register */
#define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */
#define MTK_UART_ESCAPE_DAT 0x10 /* Escape Character register */
#define MTK_UART_ESCAPE_EN 0x11 /* Escape Enable register */
#define MTK_UART_DMA_EN 0x13 /* DMA Enable register */
#define MTK_UART_RXTRI_AD 0x14 /* RX Trigger address */
#define MTK_UART_FRACDIV_L 0x15 /* Fractional divider LSB address */
#define MTK_UART_FRACDIV_M 0x16 /* Fractional divider MSB address */
#define MTK_UART_DEBUG0 0x18
#define MTK_UART_IER_XOFFI 0x20 /* Enable XOFF character interrupt */
#define MTK_UART_IER_RTSI 0x40 /* Enable RTS Modem status interrupt */
#define MTK_UART_IER_CTSI 0x80 /* Enable CTS Modem status interrupt */
#define MTK_UART_EFR 38 /* I/O: Extended Features Register */
#define MTK_UART_EFR_EN 0x10 /* Enable enhancement feature */
#define MTK_UART_EFR_RTS 0x40 /* Enable hardware rx flow control */
#define MTK_UART_EFR_CTS 0x80 /* Enable hardware tx flow control */
#define MTK_UART_EFR_NO_SW_FC 0x0 /* no sw flow control */
#define MTK_UART_EFR_XON1_XOFF1 0xa /* XON1/XOFF1 as sw flow control */
#define MTK_UART_EFR_XON2_XOFF2 0x5 /* XON2/XOFF2 as sw flow control */
#define MTK_UART_EFR_SW_FC_MASK 0xf /* Enable CTS Modem status interrupt */
#define MTK_UART_EFR_HW_FC (MTK_UART_EFR_RTS | MTK_UART_EFR_CTS)
#define MTK_UART_DMA_EN_TX 0x2
#define MTK_UART_DMA_EN_RX 0x5
#define MTK_UART_ESCAPE_CHAR 0x77 /* Escape char added under sw fc */
#define MTK_UART_RX_SIZE 0x8000
#define MTK_UART_TX_TRIGGER 1
#define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE
#define MTK_UART_XON1 40 /* I/O: Xon character 1 */
#define MTK_UART_XOFF1 42 /* I/O: Xoff character 1 */
#ifdef CONFIG_SERIAL_8250_DMA
enum dma_rx_status {
DMA_RX_START = 0,
DMA_RX_RUNNING = 1,
DMA_RX_SHUTDOWN = 2,
};
#endif
struct mtk8250_data {
int line;
unsigned int rx_pos;
unsigned int clk_count;
struct clk *uart_clk;
struct clk *bus_clk;
struct uart_8250_dma *dma;
#ifdef CONFIG_SERIAL_8250_DMA
enum dma_rx_status rx_status;
#endif
int rx_wakeup_irq;
};
/* flow control mode */
enum {
MTK_UART_FC_NONE,
MTK_UART_FC_SW,
MTK_UART_FC_HW,
};
#ifdef CONFIG_SERIAL_8250_DMA
static void mtk8250_rx_dma(struct uart_8250_port *up);
static void mtk8250_dma_rx_complete(void *param)
{
struct uart_8250_port *up = param;
struct uart_8250_dma *dma = up->dma;
struct mtk8250_data *data = up->port.private_data;
struct tty_port *tty_port = &up->port.state->port;
struct dma_tx_state state;
int copied, total, cnt;
unsigned char *ptr;
unsigned long flags;
if (data->rx_status == DMA_RX_SHUTDOWN)
return;
spin_lock_irqsave(&up->port.lock, flags);
dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
total = dma->rx_size - state.residue;
cnt = total;
if ((data->rx_pos + cnt) > dma->rx_size)
cnt = dma->rx_size - data->rx_pos;
ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
copied = tty_insert_flip_string(tty_port, ptr, cnt);
data->rx_pos += cnt;
if (total > cnt) {
ptr = (unsigned char *)(dma->rx_buf);
cnt = total - cnt;
copied += tty_insert_flip_string(tty_port, ptr, cnt);
data->rx_pos = cnt;
}
up->port.icount.rx += copied;
tty_flip_buffer_push(tty_port);
mtk8250_rx_dma(up);
spin_unlock_irqrestore(&up->port.lock, flags);
}
static void mtk8250_rx_dma(struct uart_8250_port *up)
{
struct uart_8250_dma *dma = up->dma;
struct dma_async_tx_descriptor *desc;
desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
dma->rx_size, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
pr_err("failed to prepare rx slave single\n");
return;
}
desc->callback = mtk8250_dma_rx_complete;
desc->callback_param = up;
dma->rx_cookie = dmaengine_submit(desc);
dma_async_issue_pending(dma->rxchan);
}
static void mtk8250_dma_enable(struct uart_8250_port *up)
{
struct uart_8250_dma *dma = up->dma;
struct mtk8250_data *data = up->port.private_data;
int lcr = serial_in(up, UART_LCR);
if (data->rx_status != DMA_RX_START)
return;
dma->rxconf.src_port_window_size = dma->rx_size;
dma->rxconf.src_addr = dma->rx_addr;
dma->txconf.dst_port_window_size = UART_XMIT_SIZE;
dma->txconf.dst_addr = dma->tx_addr;
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
UART_FCR_CLEAR_XMIT);
serial_out(up, MTK_UART_DMA_EN,
MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
serial_out(up, UART_LCR, lcr);
if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0)
pr_err("failed to configure rx dma channel\n");
if (dmaengine_slave_config(dma->txchan, &dma->txconf) != 0)
pr_err("failed to configure tx dma channel\n");
data->rx_status = DMA_RX_RUNNING;
data->rx_pos = 0;
mtk8250_rx_dma(up);
}
#endif
static int mtk8250_startup(struct uart_port *port)
{
#ifdef CONFIG_SERIAL_8250_DMA
struct uart_8250_port *up = up_to_u8250p(port);
struct mtk8250_data *data = port->private_data;
/* disable DMA for console */
if (uart_console(port))
up->dma = NULL;
if (up->dma) {
data->rx_status = DMA_RX_START;
uart_circ_clear(&port->state->xmit);
}
#endif
memset(&port->icount, 0, sizeof(port->icount));
return serial8250_do_startup(port);
}
static void mtk8250_shutdown(struct uart_port *port)
{
#ifdef CONFIG_SERIAL_8250_DMA
struct uart_8250_port *up = up_to_u8250p(port);
struct mtk8250_data *data = port->private_data;
if (up->dma)
data->rx_status = DMA_RX_SHUTDOWN;
#endif
return serial8250_do_shutdown(port);
}
static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask)
{
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&up->port.lock);
serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask));
}
static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask)
{
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&up->port.lock);
serial_out(up, UART_IER, serial_in(up, UART_IER) | mask);
}
static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode)
{
struct uart_port *port = &up->port;
int lcr = serial_in(up, UART_LCR);
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&port->lock);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, MTK_UART_EFR, UART_EFR_ECB);
serial_out(up, UART_LCR, lcr);
lcr = serial_in(up, UART_LCR);
switch (mode) {
case MTK_UART_FC_NONE:
serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) &
(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)));
serial_out(up, UART_LCR, lcr);
mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI |
MTK_UART_IER_RTSI | MTK_UART_IER_CTSI);
break;
case MTK_UART_FC_HW:
serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
serial_out(up, MTK_UART_ESCAPE_EN, 0x00);
serial_out(up, UART_MCR, UART_MCR_RTS);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
/*enable hw flow control*/
serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC |
(serial_in(up, MTK_UART_EFR) &
(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
serial_out(up, UART_LCR, lcr);
mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI);
mtk8250_enable_intrs(up, MTK_UART_IER_CTSI | MTK_UART_IER_RTSI);
break;
case MTK_UART_FC_SW: /*MTK software flow control */
serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR);
serial_out(up, MTK_UART_ESCAPE_EN, 0x01);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
/*enable sw flow control */
serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 |
(serial_in(up, MTK_UART_EFR) &
(~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))));
serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty));
serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty));
serial_out(up, UART_LCR, lcr);
mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI);
mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI);
break;
default:
break;
}
}
static void
mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
static const unsigned short fraction_L_mapping[] = {
0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
};
static const unsigned short fraction_M_mapping[] = {
0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
};
struct uart_8250_port *up = up_to_u8250p(port);
unsigned int baud, quot, fraction;
unsigned long flags;
int mode;
#ifdef CONFIG_SERIAL_8250_DMA
if (up->dma) {
if (uart_console(port)) {
devm_kfree(up->port.dev, up->dma);
up->dma = NULL;
} else {
mtk8250_dma_enable(up);
}
}
#endif
/*
* Store the requested baud rate before calling the generic 8250
* set_termios method. Standard 8250 port expects bauds to be
* no higher than (uartclk / 16) so the baud will be clamped if it
* gets out of that bound. Mediatek 8250 port supports speed
* higher than that, therefore we'll get original baud rate back
* after calling the generic set_termios method and recalculate
* the speed later in this method.
*/
baud = tty_termios_baud_rate(termios);
serial8250_do_set_termios(port, termios, NULL);
tty_termios_encode_baud_rate(termios, baud, baud);
/*
* Mediatek UARTs use an extra highspeed register (MTK_UART_HIGHS)
*
* We need to recalcualte the quot register, as the claculation depends
* on the vaule in the highspeed register.
*
* Some baudrates are not supported by the chip, so we use the next
* lower rate supported and update termios c_flag.
*
* If highspeed register is set to 3, we need to specify sample count
* and sample point to increase accuracy. If not, we reset the
* registers to their default values.
*/
baud = uart_get_baud_rate(port, termios, old,
port->uartclk / 16 / UART_DIV_MAX,
port->uartclk);
if (baud < 115200) {
serial_port_out(port, MTK_UART_HIGHS, 0x0);
quot = uart_get_divisor(port, baud);
} else {
serial_port_out(port, MTK_UART_HIGHS, 0x3);
quot = DIV_ROUND_UP(port->uartclk, 256 * baud);
}
/*
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*/
spin_lock_irqsave(&port->lock, flags);
/*
* Update the per-port timeout.
*/
uart_update_timeout(port, termios->c_cflag, baud);
/* set DLAB we have cval saved in up->lcr from the call to the core */
serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
serial_dl_write(up, quot);
/* reset DLAB */
serial_port_out(port, UART_LCR, up->lcr);
if (baud >= 115200) {
unsigned int tmp;
tmp = (port->uartclk / (baud * quot)) - 1;
serial_port_out(port, MTK_UART_SAMPLE_COUNT, tmp);
serial_port_out(port, MTK_UART_SAMPLE_POINT,
(tmp >> 1) - 1);
/*count fraction to set fractoin register */
fraction = ((port->uartclk * 100) / baud / quot) % 100;
fraction = DIV_ROUND_CLOSEST(fraction, 10);
serial_port_out(port, MTK_UART_FRACDIV_L,
fraction_L_mapping[fraction]);
serial_port_out(port, MTK_UART_FRACDIV_M,
fraction_M_mapping[fraction]);
} else {
serial_port_out(port, MTK_UART_SAMPLE_COUNT, 0x00);
serial_port_out(port, MTK_UART_SAMPLE_POINT, 0xff);
serial_port_out(port, MTK_UART_FRACDIV_L, 0x00);
serial_port_out(port, MTK_UART_FRACDIV_M, 0x00);
}
if ((termios->c_cflag & CRTSCTS) && (!(termios->c_iflag & CRTSCTS)))
mode = MTK_UART_FC_HW;
else if (termios->c_iflag & CRTSCTS)
mode = MTK_UART_FC_SW;
else
mode = MTK_UART_FC_NONE;
mtk8250_set_flow_ctrl(up, mode);
if (uart_console(port))
up->port.cons->cflag = termios->c_cflag;
spin_unlock_irqrestore(&port->lock, flags);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);
}
static int __maybe_unused mtk8250_runtime_suspend(struct device *dev)
{
struct mtk8250_data *data = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(data->line);
/* wait until UART in idle status */
while
(serial_in(up, MTK_UART_DEBUG0));
clk_disable_unprepare(data->bus_clk);
return 0;
}
static int __maybe_unused mtk8250_runtime_resume(struct device *dev)
{
struct mtk8250_data *data = dev_get_drvdata(dev);
clk_prepare_enable(data->bus_clk);
return 0;
}
static void
mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
{
if (!state)
pm_runtime_get_sync(port->dev);
serial8250_do_pm(port, state, old);
if (state)
pm_runtime_put_sync_suspend(port->dev);
}
#ifdef CONFIG_SERIAL_8250_DMA
static bool mtk8250_dma_filter(struct dma_chan *chan, void *param)
{
return false;
}
#endif
static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p,
struct mtk8250_data *data)
{
#ifdef CONFIG_SERIAL_8250_DMA
int dmacnt;
#endif
data->uart_clk = devm_clk_get(&pdev->dev, "baud");
if (IS_ERR(data->uart_clk)) {
/*
* For compatibility with older device trees try unnamed
* clk when no baud clk can be found.
*/
data->uart_clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(data->uart_clk)) {
dev_warn(&pdev->dev, "Can't get uart clock\n");
return PTR_ERR(data->uart_clk);
}
return 0;
}
data->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus");
if (IS_ERR(data->bus_clk))
return PTR_ERR(data->bus_clk);
data->dma = NULL;
#ifdef CONFIG_SERIAL_8250_DMA
dmacnt = of_property_count_strings(pdev->dev.of_node, "dma-names");
if (dmacnt == 2) {
data->dma = devm_kzalloc(&pdev->dev, sizeof(*data->dma),
GFP_KERNEL);
if (!data->dma)
return -ENOMEM;
data->dma->fn = mtk8250_dma_filter;
data->dma->rx_size = MTK_UART_RX_SIZE;
data->dma->rxconf.src_maxburst = MTK_UART_RX_TRIGGER;
data->dma->txconf.dst_maxburst = MTK_UART_TX_TRIGGER;
}
#endif
return 0;
}
static int mtk8250_probe(struct platform_device *pdev)
{
struct uart_8250_port uart = {};
struct mtk8250_data *data;
struct resource *regs;
int irq, err;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(&pdev->dev, "no registers defined\n");
return -EINVAL;
}
uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
resource_size(regs));
if (!uart.port.membase)
return -ENOMEM;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->clk_count = 0;
if (pdev->dev.of_node) {
err = mtk8250_probe_of(pdev, &uart.port, data);
if (err)
return err;
} else
return -ENODEV;
spin_lock_init(&uart.port.lock);
uart.port.mapbase = regs->start;
uart.port.irq = irq;
uart.port.pm = mtk8250_do_pm;
uart.port.type = PORT_16550;
uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
uart.port.dev = &pdev->dev;
uart.port.iotype = UPIO_MEM32;
uart.port.regshift = 2;
uart.port.private_data = data;
uart.port.shutdown = mtk8250_shutdown;
uart.port.startup = mtk8250_startup;
uart.port.set_termios = mtk8250_set_termios;
uart.port.uartclk = clk_get_rate(data->uart_clk);
#ifdef CONFIG_SERIAL_8250_DMA
if (data->dma)
uart.dma = data->dma;
#endif
/* Disable Rate Fix function */
writel(0x0, uart.port.membase +
(MTK_UART_RATE_FIX << uart.port.regshift));
platform_set_drvdata(pdev, data);
data->line = serial8250_register_8250_port(&uart);
if (data->line < 0)
return data->line;
data->rx_wakeup_irq = platform_get_irq_optional(pdev, 1);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
return 0;
}
static int mtk8250_remove(struct platform_device *pdev)
{
struct mtk8250_data *data = platform_get_drvdata(pdev);
pm_runtime_get_sync(&pdev->dev);
serial8250_unregister_port(data->line);
pm_runtime_disable(&pdev->dev);
pm_runtime_put_noidle(&pdev->dev);
return 0;
}
static int __maybe_unused mtk8250_suspend(struct device *dev)
{
struct mtk8250_data *data = dev_get_drvdata(dev);
int irq = data->rx_wakeup_irq;
int err;
serial8250_suspend_port(data->line);
pinctrl_pm_select_sleep_state(dev);
if (irq >= 0) {
err = enable_irq_wake(irq);
if (err) {
dev_err(dev,
"failed to enable irq wake on IRQ %d: %d\n",
irq, err);
pinctrl_pm_select_default_state(dev);
serial8250_resume_port(data->line);
return err;
}
}
return 0;
}
static int __maybe_unused mtk8250_resume(struct device *dev)
{
struct mtk8250_data *data = dev_get_drvdata(dev);
int irq = data->rx_wakeup_irq;
if (irq >= 0)
disable_irq_wake(irq);
pinctrl_pm_select_default_state(dev);
serial8250_resume_port(data->line);
return 0;
}
static const struct dev_pm_ops mtk8250_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(mtk8250_suspend, mtk8250_resume)
SET_RUNTIME_PM_OPS(mtk8250_runtime_suspend, mtk8250_runtime_resume,
NULL)
};
static const struct of_device_id mtk8250_of_match[] = {
{ .compatible = "mediatek,mt6577-uart" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk8250_of_match);
static struct platform_driver mtk8250_platform_driver = {
.driver = {
.name = "mt6577-uart",
.pm = &mtk8250_pm_ops,
.of_match_table = mtk8250_of_match,
},
.probe = mtk8250_probe,
.remove = mtk8250_remove,
};
module_platform_driver(mtk8250_platform_driver);
#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init early_mtk8250_setup(struct earlycon_device *device,
const char *options)
{
if (!device->port.membase)
return -ENODEV;
device->port.iotype = UPIO_MEM32;
device->port.regshift = 2;
return early_serial8250_setup(device, NULL);
}
OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);
#endif
MODULE_AUTHOR("Matthias Brugger");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Mediatek 8250 serial port driver");
| linux-master | drivers/tty/serial/8250/8250_mtk.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Synopsys DesignWare 8250 driver.
*
* Copyright 2011 Picochip, Jamie Iles.
* Copyright 2013 Intel Corporation
*
* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
* LCR is written whilst busy. If it is, then a busy detect interrupt is
* raised, the LCR needs to be rewritten and the uart status register read.
*/
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <asm/byteorder.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include "8250_dwlib.h"
/* Offsets for the DesignWare specific registers */
#define DW_UART_USR 0x1f /* UART Status Register */
#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
#define OCTEON_UART_USR 0x27 /* UART Status Register */
#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
/* DesignWare specific register fields */
#define DW_UART_MCR_SIRE BIT(6)
/* Renesas specific register fields */
#define RZN1_UART_xDMACR_DMA_EN BIT(0)
#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
#define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
/* Quirks */
#define DW_UART_QUIRK_OCTEON BIT(0)
#define DW_UART_QUIRK_ARMADA_38X BIT(1)
#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
#define DW_UART_QUIRK_IS_DMA_FC BIT(3)
static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
{
return container_of(nb, struct dw8250_data, clk_notifier);
}
static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
{
return container_of(work, struct dw8250_data, clk_work);
}
static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = to_dw8250_data(p->private_data);
/* Override any modem control signals if needed */
if (offset == UART_MSR) {
value |= d->msr_mask_on;
value &= ~d->msr_mask_off;
}
return value;
}
static void dw8250_force_idle(struct uart_port *p)
{
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int lsr;
serial8250_clear_and_reinit_fifos(up);
/*
* With PSLVERR_RESP_EN parameter set to 1, the device generates an
* error response when an attempt to read an empty RBR with FIFO
* enabled.
*/
if (up->fcr & UART_FCR_ENABLE_FIFO) {
lsr = p->serial_in(p, UART_LSR);
if (!(lsr & UART_LSR_DR))
return;
}
(void)p->serial_in(p, UART_RX);
}
static void dw8250_check_lcr(struct uart_port *p, int value)
{
void __iomem *offset = p->membase + (UART_LCR << p->regshift);
int tries = 1000;
/* Make sure LCR write wasn't ignored */
while (tries--) {
unsigned int lcr = p->serial_in(p, UART_LCR);
if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
return;
dw8250_force_idle(p);
#ifdef CONFIG_64BIT
if (p->type == PORT_OCTEON)
__raw_writeq(value & 0xff, offset);
else
#endif
if (p->iotype == UPIO_MEM32)
writel(value, offset);
else if (p->iotype == UPIO_MEM32BE)
iowrite32be(value, offset);
else
writeb(value, offset);
}
/*
* FIXME: this deadlocks if port->lock is already held
* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
*/
}
/* Returns once the transmitter is empty or we run out of retries */
static void dw8250_tx_wait_empty(struct uart_port *p)
{
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int tries = 20000;
unsigned int delay_threshold = tries - 1000;
unsigned int lsr;
while (tries--) {
lsr = readb (p->membase + (UART_LSR << p->regshift));
up->lsr_saved_flags |= lsr & up->lsr_save_mask;
if (lsr & UART_LSR_TEMT)
break;
/* The device is first given a chance to empty without delay,
* to avoid slowdowns at high bitrates. If after 1000 tries
* the buffer has still not emptied, allow more time for low-
* speed links. */
if (tries < delay_threshold)
udelay (1);
}
}
static void dw8250_serial_out(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = to_dw8250_data(p->private_data);
writeb(value, p->membase + (offset << p->regshift));
if (offset == UART_LCR && !d->uart_16550_compatible)
dw8250_check_lcr(p, value);
}
static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
{
/* Allow the TX to drain before we reconfigure */
if (offset == UART_LCR)
dw8250_tx_wait_empty(p);
dw8250_serial_out(p, offset, value);
}
static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
{
unsigned int value = readb(p->membase + (offset << p->regshift));
return dw8250_modify_msr(p, offset, value);
}
#ifdef CONFIG_64BIT
static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
{
unsigned int value;
value = (u8)__raw_readq(p->membase + (offset << p->regshift));
return dw8250_modify_msr(p, offset, value);
}
static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = to_dw8250_data(p->private_data);
value &= 0xff;
__raw_writeq(value, p->membase + (offset << p->regshift));
/* Read back to ensure register write ordering. */
__raw_readq(p->membase + (UART_LCR << p->regshift));
if (offset == UART_LCR && !d->uart_16550_compatible)
dw8250_check_lcr(p, value);
}
#endif /* CONFIG_64BIT */
static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = to_dw8250_data(p->private_data);
writel(value, p->membase + (offset << p->regshift));
if (offset == UART_LCR && !d->uart_16550_compatible)
dw8250_check_lcr(p, value);
}
static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
{
unsigned int value = readl(p->membase + (offset << p->regshift));
return dw8250_modify_msr(p, offset, value);
}
static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = to_dw8250_data(p->private_data);
iowrite32be(value, p->membase + (offset << p->regshift));
if (offset == UART_LCR && !d->uart_16550_compatible)
dw8250_check_lcr(p, value);
}
static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
{
unsigned int value = ioread32be(p->membase + (offset << p->regshift));
return dw8250_modify_msr(p, offset, value);
}
static int dw8250_handle_irq(struct uart_port *p)
{
struct uart_8250_port *up = up_to_u8250p(p);
struct dw8250_data *d = to_dw8250_data(p->private_data);
unsigned int iir = p->serial_in(p, UART_IIR);
bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
unsigned int quirks = d->pdata->quirks;
unsigned int status;
unsigned long flags;
/*
* There are ways to get Designware-based UARTs into a state where
* they are asserting UART_IIR_RX_TIMEOUT but there is no actual
* data available. If we see such a case then we'll do a bogus
* read. If we don't do this then the "RX TIMEOUT" interrupt will
* fire forever.
*
* This problem has only been observed so far when not in DMA mode
* so we limit the workaround only to non-DMA mode.
*/
if (!up->dma && rx_timeout) {
spin_lock_irqsave(&p->lock, flags);
status = serial_lsr_in(up);
if (!(status & (UART_LSR_DR | UART_LSR_BI)))
(void) p->serial_in(p, UART_RX);
spin_unlock_irqrestore(&p->lock, flags);
}
/* Manually stop the Rx DMA transfer when acting as flow controller */
if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
spin_lock_irqsave(&p->lock, flags);
status = serial_lsr_in(up);
spin_unlock_irqrestore(&p->lock, flags);
if (status & (UART_LSR_DR | UART_LSR_BI)) {
dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
dw8250_writel_ext(p, DW_UART_DMASA, 1);
}
}
if (serial8250_handle_irq(p, iir))
return 1;
if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
/* Clear the USR */
(void)p->serial_in(p, d->pdata->usr_reg);
return 1;
}
return 0;
}
static void dw8250_clk_work_cb(struct work_struct *work)
{
struct dw8250_data *d = work_to_dw8250_data(work);
struct uart_8250_port *up;
unsigned long rate;
rate = clk_get_rate(d->clk);
if (rate <= 0)
return;
up = serial8250_get_port(d->data.line);
serial8250_update_uartclk(&up->port, rate);
}
static int dw8250_clk_notifier_cb(struct notifier_block *nb,
unsigned long event, void *data)
{
struct dw8250_data *d = clk_to_dw8250_data(nb);
/*
* We have no choice but to defer the uartclk update due to two
* deadlocks. First one is caused by a recursive mutex lock which
* happens when clk_set_rate() is called from dw8250_set_termios().
* Second deadlock is more tricky and is caused by an inverted order of
* the clk and tty-port mutexes lock. It happens if clock rate change
* is requested asynchronously while set_termios() is executed between
* tty-port mutex lock and clk_set_rate() function invocation and
* vise-versa. Anyway if we didn't have the reference clock alteration
* in the dw8250_set_termios() method we wouldn't have needed this
* deferred event handling complication.
*/
if (event == POST_RATE_CHANGE) {
queue_work(system_unbound_wq, &d->clk_work);
return NOTIFY_OK;
}
return NOTIFY_DONE;
}
static void
dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
{
if (!state)
pm_runtime_get_sync(port->dev);
serial8250_do_pm(port, state, old);
if (state)
pm_runtime_put_sync_suspend(port->dev);
}
static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
const struct ktermios *old)
{
unsigned long newrate = tty_termios_baud_rate(termios) * 16;
struct dw8250_data *d = to_dw8250_data(p->private_data);
long rate;
int ret;
clk_disable_unprepare(d->clk);
rate = clk_round_rate(d->clk, newrate);
if (rate > 0) {
/*
* Note that any clock-notifer worker will block in
* serial8250_update_uartclk() until we are done.
*/
ret = clk_set_rate(d->clk, newrate);
if (!ret)
p->uartclk = rate;
}
clk_prepare_enable(d->clk);
dw8250_do_set_termios(p, termios, old);
}
static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
{
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int mcr = p->serial_in(p, UART_MCR);
if (up->capabilities & UART_CAP_IRDA) {
if (termios->c_line == N_IRDA)
mcr |= DW_UART_MCR_SIRE;
else
mcr &= ~DW_UART_MCR_SIRE;
p->serial_out(p, UART_MCR, mcr);
}
serial8250_do_set_ldisc(p, termios);
}
/*
* dw8250_fallback_dma_filter will prevent the UART from getting just any free
* channel on platforms that have DMA engines, but don't have any channels
* assigned to the UART.
*
* REVISIT: This is a work around for limitation in the DMA Engine API. Once the
* core problem is fixed, this function is no longer needed.
*/
static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
{
return false;
}
static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
{
return param == chan->device->dev;
}
static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
{
if (max_burst >= 8)
return RZN1_UART_xDMACR_8_WORD_BURST;
else if (max_burst >= 4)
return RZN1_UART_xDMACR_4_WORD_BURST;
else
return RZN1_UART_xDMACR_1_WORD_BURST;
}
static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
{
struct uart_port *up = &p->port;
struct uart_8250_dma *dma = p->dma;
u32 val;
dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
RZN1_UART_xDMACR_DMA_EN;
dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
}
static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
{
struct uart_port *up = &p->port;
struct uart_8250_dma *dma = p->dma;
u32 val;
dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
RZN1_UART_xDMACR_DMA_EN;
dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
}
static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
{
struct device_node *np = p->dev->of_node;
if (np) {
unsigned int quirks = data->pdata->quirks;
int id;
/* get index of serial line, if found in DT aliases */
id = of_alias_get_id(np, "serial");
if (id >= 0)
p->line = id;
#ifdef CONFIG_64BIT
if (quirks & DW_UART_QUIRK_OCTEON) {
p->serial_in = dw8250_serial_inq;
p->serial_out = dw8250_serial_outq;
p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
p->type = PORT_OCTEON;
data->skip_autocfg = true;
}
#endif
if (of_device_is_big_endian(np)) {
p->iotype = UPIO_MEM32BE;
p->serial_in = dw8250_serial_in32be;
p->serial_out = dw8250_serial_out32be;
}
if (quirks & DW_UART_QUIRK_ARMADA_38X)
p->serial_out = dw8250_serial_out38x;
if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
p->set_termios = dw8250_do_set_termios;
if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
data->data.dma.txconf.device_fc = 1;
data->data.dma.rxconf.device_fc = 1;
data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
}
} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
p->iotype = UPIO_MEM32;
p->regshift = 2;
p->serial_in = dw8250_serial_in32;
data->uart_16550_compatible = true;
}
/* Platforms with iDMA 64-bit */
if (platform_get_resource_byname(to_platform_device(p->dev),
IORESOURCE_MEM, "lpss_priv")) {
data->data.dma.rx_param = p->dev->parent;
data->data.dma.tx_param = p->dev->parent;
data->data.dma.fn = dw8250_idma_filter;
}
}
static void dw8250_clk_disable_unprepare(void *data)
{
clk_disable_unprepare(data);
}
static void dw8250_reset_control_assert(void *data)
{
reset_control_assert(data);
}
static int dw8250_probe(struct platform_device *pdev)
{
struct uart_8250_port uart = {}, *up = &uart;
struct uart_port *p = &up->port;
struct device *dev = &pdev->dev;
struct dw8250_data *data;
struct resource *regs;
int irq;
int err;
u32 val;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs)
return dev_err_probe(dev, -EINVAL, "no registers defined\n");
irq = platform_get_irq_optional(pdev, 0);
/* no interrupt -> fall back to polling */
if (irq == -ENXIO)
irq = 0;
if (irq < 0)
return irq;
spin_lock_init(&p->lock);
p->mapbase = regs->start;
p->irq = irq;
p->handle_irq = dw8250_handle_irq;
p->pm = dw8250_do_pm;
p->type = PORT_8250;
p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
p->dev = dev;
p->iotype = UPIO_MEM;
p->serial_in = dw8250_serial_in;
p->serial_out = dw8250_serial_out;
p->set_ldisc = dw8250_set_ldisc;
p->set_termios = dw8250_set_termios;
p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
if (!p->membase)
return -ENOMEM;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->data.dma.fn = dw8250_fallback_dma_filter;
data->pdata = device_get_match_data(p->dev);
p->private_data = &data->data;
data->uart_16550_compatible = device_property_read_bool(dev,
"snps,uart-16550-compatible");
err = device_property_read_u32(dev, "reg-shift", &val);
if (!err)
p->regshift = val;
err = device_property_read_u32(dev, "reg-io-width", &val);
if (!err && val == 4) {
p->iotype = UPIO_MEM32;
p->serial_in = dw8250_serial_in32;
p->serial_out = dw8250_serial_out32;
}
if (device_property_read_bool(dev, "dcd-override")) {
/* Always report DCD as active */
data->msr_mask_on |= UART_MSR_DCD;
data->msr_mask_off |= UART_MSR_DDCD;
}
if (device_property_read_bool(dev, "dsr-override")) {
/* Always report DSR as active */
data->msr_mask_on |= UART_MSR_DSR;
data->msr_mask_off |= UART_MSR_DDSR;
}
if (device_property_read_bool(dev, "cts-override")) {
/* Always report CTS as active */
data->msr_mask_on |= UART_MSR_CTS;
data->msr_mask_off |= UART_MSR_DCTS;
}
if (device_property_read_bool(dev, "ri-override")) {
/* Always report Ring indicator as inactive */
data->msr_mask_off |= UART_MSR_RI;
data->msr_mask_off |= UART_MSR_TERI;
}
/* Always ask for fixed clock rate from a property. */
device_property_read_u32(dev, "clock-frequency", &p->uartclk);
/* If there is separate baudclk, get the rate from it. */
data->clk = devm_clk_get_optional(dev, "baudclk");
if (data->clk == NULL)
data->clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(data->clk))
return PTR_ERR(data->clk);
INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
err = clk_prepare_enable(data->clk);
if (err)
return dev_err_probe(dev, err, "could not enable optional baudclk\n");
err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
if (err)
return err;
if (data->clk)
p->uartclk = clk_get_rate(data->clk);
/* If no clock rate is defined, fail. */
if (!p->uartclk)
return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
data->pclk = devm_clk_get_optional(dev, "apb_pclk");
if (IS_ERR(data->pclk))
return PTR_ERR(data->pclk);
err = clk_prepare_enable(data->pclk);
if (err)
return dev_err_probe(dev, err, "could not enable apb_pclk\n");
err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
if (err)
return err;
data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(data->rst))
return PTR_ERR(data->rst);
reset_control_deassert(data->rst);
err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
if (err)
return err;
dw8250_quirks(p, data);
/* If the Busy Functionality is not implemented, don't handle it */
if (data->uart_16550_compatible)
p->handle_irq = NULL;
if (!data->skip_autocfg)
dw8250_setup_port(p);
/* If we have a valid fifosize, try hooking up DMA */
if (p->fifosize) {
data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
up->dma = &data->data.dma;
}
data->data.line = serial8250_register_8250_port(up);
if (data->data.line < 0)
return data->data.line;
/*
* Some platforms may provide a reference clock shared between several
* devices. In this case any clock state change must be known to the
* UART port at least post factum.
*/
if (data->clk) {
err = clk_notifier_register(data->clk, &data->clk_notifier);
if (err)
return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
queue_work(system_unbound_wq, &data->clk_work);
}
platform_set_drvdata(pdev, data);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
return 0;
}
static int dw8250_remove(struct platform_device *pdev)
{
struct dw8250_data *data = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
pm_runtime_get_sync(dev);
if (data->clk) {
clk_notifier_unregister(data->clk, &data->clk_notifier);
flush_work(&data->clk_work);
}
serial8250_unregister_port(data->data.line);
pm_runtime_disable(dev);
pm_runtime_put_noidle(dev);
return 0;
}
static int dw8250_suspend(struct device *dev)
{
struct dw8250_data *data = dev_get_drvdata(dev);
serial8250_suspend_port(data->data.line);
return 0;
}
static int dw8250_resume(struct device *dev)
{
struct dw8250_data *data = dev_get_drvdata(dev);
serial8250_resume_port(data->data.line);
return 0;
}
static int dw8250_runtime_suspend(struct device *dev)
{
struct dw8250_data *data = dev_get_drvdata(dev);
clk_disable_unprepare(data->clk);
clk_disable_unprepare(data->pclk);
return 0;
}
static int dw8250_runtime_resume(struct device *dev)
{
struct dw8250_data *data = dev_get_drvdata(dev);
clk_prepare_enable(data->pclk);
clk_prepare_enable(data->clk);
return 0;
}
static const struct dev_pm_ops dw8250_pm_ops = {
SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
};
static const struct dw8250_platform_data dw8250_dw_apb = {
.usr_reg = DW_UART_USR,
};
static const struct dw8250_platform_data dw8250_octeon_3860_data = {
.usr_reg = OCTEON_UART_USR,
.quirks = DW_UART_QUIRK_OCTEON,
};
static const struct dw8250_platform_data dw8250_armada_38x_data = {
.usr_reg = DW_UART_USR,
.quirks = DW_UART_QUIRK_ARMADA_38X,
};
static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
.usr_reg = DW_UART_USR,
.cpr_val = 0x00012f32,
.quirks = DW_UART_QUIRK_IS_DMA_FC,
};
static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
.usr_reg = DW_UART_USR,
.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
};
static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);
static const struct acpi_device_id dw8250_acpi_match[] = {
{ "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
{ "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
{ "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
{ "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
{ "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
{ "APMC0D08", (kernel_ulong_t)&dw8250_dw_apb},
{ "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
{ "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
{ "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
{ "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
{ "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
{ "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
{ },
};
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
static struct platform_driver dw8250_platform_driver = {
.driver = {
.name = "dw-apb-uart",
.pm = pm_ptr(&dw8250_pm_ops),
.of_match_table = dw8250_of_match,
.acpi_match_table = dw8250_acpi_match,
},
.probe = dw8250_probe,
.remove = dw8250_remove,
};
module_platform_driver(dw8250_platform_driver);
MODULE_AUTHOR("Jamie Iles");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
MODULE_ALIAS("platform:dw-apb-uart");
| linux-master | drivers/tty/serial/8250/8250_dw.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Serial port driver for NXP LPC18xx/43xx UART
*
* Copyright (C) 2015 Joachim Eastwood <[email protected]>
*
* Based on 8250_mtk.c:
* Copyright (c) 2014 MundoReader S.L.
* Matthias Brugger <[email protected]>
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "8250.h"
/* Additional LPC18xx/43xx 8250 registers and bits */
#define LPC18XX_UART_RS485CTRL (0x04c / sizeof(u32))
#define LPC18XX_UART_RS485CTRL_NMMEN BIT(0)
#define LPC18XX_UART_RS485CTRL_DCTRL BIT(4)
#define LPC18XX_UART_RS485CTRL_OINV BIT(5)
#define LPC18XX_UART_RS485DLY (0x054 / sizeof(u32))
#define LPC18XX_UART_RS485DLY_MAX 255
struct lpc18xx_uart_data {
struct uart_8250_dma dma;
struct clk *clk_uart;
struct clk *clk_reg;
int line;
};
static int lpc18xx_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct uart_8250_port *up = up_to_u8250p(port);
u32 rs485_ctrl_reg = 0;
u32 rs485_dly_reg = 0;
unsigned baud_clk;
if (rs485->flags & SER_RS485_ENABLED) {
rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_NMMEN |
LPC18XX_UART_RS485CTRL_DCTRL;
if (rs485->flags & SER_RS485_RTS_ON_SEND)
rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_OINV;
}
if (rs485->delay_rts_after_send) {
baud_clk = port->uartclk / up->dl_read(up);
rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send
* baud_clk, MSEC_PER_SEC);
if (rs485_dly_reg > LPC18XX_UART_RS485DLY_MAX)
rs485_dly_reg = LPC18XX_UART_RS485DLY_MAX;
/* Calculate the resulting delay in ms */
rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC)
/ baud_clk;
}
serial_out(up, LPC18XX_UART_RS485CTRL, rs485_ctrl_reg);
serial_out(up, LPC18XX_UART_RS485DLY, rs485_dly_reg);
return 0;
}
static void lpc18xx_uart_serial_out(struct uart_port *p, int offset, int value)
{
/*
* For DMA mode one must ensure that the UART_FCR_DMA_SELECT
* bit is set when FIFO is enabled. Even if DMA is not used
* setting this bit doesn't seem to affect anything.
*/
if (offset == UART_FCR && (value & UART_FCR_ENABLE_FIFO))
value |= UART_FCR_DMA_SELECT;
offset = offset << p->regshift;
writel(value, p->membase + offset);
}
static const struct serial_rs485 lpc18xx_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
.delay_rts_after_send = 1,
/* Delay RTS before send is not supported */
};
static int lpc18xx_serial_probe(struct platform_device *pdev)
{
struct lpc18xx_uart_data *data;
struct uart_8250_port uart;
struct resource *res;
int irq, ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "memory resource not found");
return -EINVAL;
}
memset(&uart, 0, sizeof(uart));
uart.port.membase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!uart.port.membase)
return -ENOMEM;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->clk_uart = devm_clk_get(&pdev->dev, "uartclk");
if (IS_ERR(data->clk_uart)) {
dev_err(&pdev->dev, "uart clock not found\n");
return PTR_ERR(data->clk_uart);
}
data->clk_reg = devm_clk_get(&pdev->dev, "reg");
if (IS_ERR(data->clk_reg)) {
dev_err(&pdev->dev, "reg clock not found\n");
return PTR_ERR(data->clk_reg);
}
ret = clk_prepare_enable(data->clk_reg);
if (ret) {
dev_err(&pdev->dev, "unable to enable reg clock\n");
return ret;
}
ret = clk_prepare_enable(data->clk_uart);
if (ret) {
dev_err(&pdev->dev, "unable to enable uart clock\n");
goto dis_clk_reg;
}
ret = of_alias_get_id(pdev->dev.of_node, "serial");
if (ret >= 0)
uart.port.line = ret;
data->dma.rx_param = data;
data->dma.tx_param = data;
spin_lock_init(&uart.port.lock);
uart.port.dev = &pdev->dev;
uart.port.irq = irq;
uart.port.iotype = UPIO_MEM32;
uart.port.mapbase = res->start;
uart.port.regshift = 2;
uart.port.type = PORT_16550A;
uart.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SKIP_TEST;
uart.port.uartclk = clk_get_rate(data->clk_uart);
uart.port.private_data = data;
uart.port.rs485_config = lpc18xx_rs485_config;
uart.port.rs485_supported = lpc18xx_rs485_supported;
uart.port.serial_out = lpc18xx_uart_serial_out;
uart.dma = &data->dma;
uart.dma->rxconf.src_maxburst = 1;
uart.dma->txconf.dst_maxburst = 1;
ret = serial8250_register_8250_port(&uart);
if (ret < 0) {
dev_err(&pdev->dev, "unable to register 8250 port\n");
goto dis_uart_clk;
}
data->line = ret;
platform_set_drvdata(pdev, data);
return 0;
dis_uart_clk:
clk_disable_unprepare(data->clk_uart);
dis_clk_reg:
clk_disable_unprepare(data->clk_reg);
return ret;
}
static int lpc18xx_serial_remove(struct platform_device *pdev)
{
struct lpc18xx_uart_data *data = platform_get_drvdata(pdev);
serial8250_unregister_port(data->line);
clk_disable_unprepare(data->clk_uart);
clk_disable_unprepare(data->clk_reg);
return 0;
}
static const struct of_device_id lpc18xx_serial_match[] = {
{ .compatible = "nxp,lpc1850-uart" },
{ },
};
MODULE_DEVICE_TABLE(of, lpc18xx_serial_match);
static struct platform_driver lpc18xx_serial_driver = {
.probe = lpc18xx_serial_probe,
.remove = lpc18xx_serial_remove,
.driver = {
.name = "lpc18xx-uart",
.of_match_table = lpc18xx_serial_match,
},
};
module_platform_driver(lpc18xx_serial_driver);
MODULE_AUTHOR("Joachim Eastwood <[email protected]>");
MODULE_DESCRIPTION("Serial port driver NXP LPC18xx/43xx devices");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/8250/8250_lpc18xx.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Serial Port driver for Open Firmware platform devices
*
* Copyright (C) 2006 Arnd Bergmann <[email protected]>, IBM Corp.
*/
#include <linux/console.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/reset.h>
#include "8250.h"
struct of_serial_info {
struct clk *clk;
struct reset_control *rst;
int type;
int line;
};
/*
* Fill a struct uart_port for a given device node
*/
static int of_platform_serial_setup(struct platform_device *ofdev,
int type, struct uart_8250_port *up,
struct of_serial_info *info)
{
struct resource resource;
struct device_node *np = ofdev->dev.of_node;
struct uart_port *port = &up->port;
u32 clk, spd, prop;
int ret, irq;
memset(port, 0, sizeof *port);
pm_runtime_enable(&ofdev->dev);
pm_runtime_get_sync(&ofdev->dev);
if (of_property_read_u32(np, "clock-frequency", &clk)) {
/* Get clk rate through clk driver if present */
info->clk = devm_clk_get(&ofdev->dev, NULL);
if (IS_ERR(info->clk)) {
ret = PTR_ERR(info->clk);
if (ret != -EPROBE_DEFER)
dev_warn(&ofdev->dev,
"failed to get clock: %d\n", ret);
goto err_pmruntime;
}
ret = clk_prepare_enable(info->clk);
if (ret < 0)
goto err_pmruntime;
clk = clk_get_rate(info->clk);
}
/* If current-speed was set, then try not to change it. */
if (of_property_read_u32(np, "current-speed", &spd) == 0)
port->custom_divisor = clk / (16 * spd);
ret = of_address_to_resource(np, 0, &resource);
if (ret) {
dev_warn(&ofdev->dev, "invalid address\n");
goto err_unprepare;
}
port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
UPF_FIXED_TYPE;
spin_lock_init(&port->lock);
if (resource_type(&resource) == IORESOURCE_IO) {
port->iotype = UPIO_PORT;
port->iobase = resource.start;
} else {
port->mapbase = resource.start;
port->mapsize = resource_size(&resource);
/* Check for shifted address mapping */
if (of_property_read_u32(np, "reg-offset", &prop) == 0) {
if (prop >= port->mapsize) {
dev_warn(&ofdev->dev, "reg-offset %u exceeds region size %pa\n",
prop, &port->mapsize);
ret = -EINVAL;
goto err_unprepare;
}
port->mapbase += prop;
port->mapsize -= prop;
}
port->iotype = UPIO_MEM;
if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
switch (prop) {
case 1:
port->iotype = UPIO_MEM;
break;
case 2:
port->iotype = UPIO_MEM16;
break;
case 4:
port->iotype = of_device_is_big_endian(np) ?
UPIO_MEM32BE : UPIO_MEM32;
break;
default:
dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
prop);
ret = -EINVAL;
goto err_unprepare;
}
}
port->flags |= UPF_IOREMAP;
}
/* Compatibility with the deprecated pxa driver and 8250_pxa drivers. */
if (of_device_is_compatible(np, "mrvl,mmp-uart"))
port->regshift = 2;
/* Check for registers offset within the devices address range */
if (of_property_read_u32(np, "reg-shift", &prop) == 0)
port->regshift = prop;
/* Check for fifo size */
if (of_property_read_u32(np, "fifo-size", &prop) == 0)
port->fifosize = prop;
/* Check for a fixed line number */
ret = of_alias_get_id(np, "serial");
if (ret >= 0)
port->line = ret;
irq = of_irq_get(np, 0);
if (irq < 0) {
if (irq == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto err_unprepare;
}
/* IRQ support not mandatory */
irq = 0;
}
port->irq = irq;
info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
if (IS_ERR(info->rst)) {
ret = PTR_ERR(info->rst);
goto err_unprepare;
}
ret = reset_control_deassert(info->rst);
if (ret)
goto err_unprepare;
port->type = type;
port->uartclk = clk;
if (of_property_read_bool(np, "no-loopback-test"))
port->flags |= UPF_SKIP_TEST;
port->dev = &ofdev->dev;
port->rs485_config = serial8250_em485_config;
port->rs485_supported = serial8250_em485_supported;
up->rs485_start_tx = serial8250_em485_start_tx;
up->rs485_stop_tx = serial8250_em485_stop_tx;
switch (type) {
case PORT_RT2880:
ret = rt288x_setup(port);
if (ret)
goto err_unprepare;
break;
}
if (IS_REACHABLE(CONFIG_SERIAL_8250_FSL) &&
(of_device_is_compatible(np, "fsl,ns16550") ||
of_device_is_compatible(np, "fsl,16550-FIFO64"))) {
port->handle_irq = fsl8250_handle_irq;
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
}
return 0;
err_unprepare:
clk_disable_unprepare(info->clk);
err_pmruntime:
pm_runtime_put_sync(&ofdev->dev);
pm_runtime_disable(&ofdev->dev);
return ret;
}
/*
* Try to register a serial port
*/
static int of_platform_serial_probe(struct platform_device *ofdev)
{
struct of_serial_info *info;
struct uart_8250_port port8250;
unsigned int port_type;
u32 tx_threshold;
int ret;
if (IS_ENABLED(CONFIG_SERIAL_8250_BCM7271) &&
of_device_is_compatible(ofdev->dev.of_node, "brcm,bcm7271-uart"))
return -ENODEV;
port_type = (unsigned long)of_device_get_match_data(&ofdev->dev);
if (port_type == PORT_UNKNOWN)
return -EINVAL;
if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
return -EBUSY;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (info == NULL)
return -ENOMEM;
memset(&port8250, 0, sizeof(port8250));
ret = of_platform_serial_setup(ofdev, port_type, &port8250, info);
if (ret)
goto err_free;
if (port8250.port.fifosize)
port8250.capabilities = UART_CAP_FIFO;
/* Check for TX FIFO threshold & set tx_loadsz */
if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
&tx_threshold) == 0) &&
(tx_threshold < port8250.port.fifosize))
port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
port8250.capabilities |= UART_CAP_AFE;
if (of_property_read_u32(ofdev->dev.of_node,
"overrun-throttle-ms",
&port8250.overrun_backoff_time_ms) != 0)
port8250.overrun_backoff_time_ms = 0;
ret = serial8250_register_8250_port(&port8250);
if (ret < 0)
goto err_dispose;
info->type = port_type;
info->line = ret;
platform_set_drvdata(ofdev, info);
return 0;
err_dispose:
irq_dispose_mapping(port8250.port.irq);
pm_runtime_put_sync(&ofdev->dev);
pm_runtime_disable(&ofdev->dev);
clk_disable_unprepare(info->clk);
err_free:
kfree(info);
return ret;
}
/*
* Release a line
*/
static int of_platform_serial_remove(struct platform_device *ofdev)
{
struct of_serial_info *info = platform_get_drvdata(ofdev);
serial8250_unregister_port(info->line);
reset_control_assert(info->rst);
pm_runtime_put_sync(&ofdev->dev);
pm_runtime_disable(&ofdev->dev);
clk_disable_unprepare(info->clk);
kfree(info);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int of_serial_suspend(struct device *dev)
{
struct of_serial_info *info = dev_get_drvdata(dev);
struct uart_8250_port *port8250 = serial8250_get_port(info->line);
struct uart_port *port = &port8250->port;
serial8250_suspend_port(info->line);
if (!uart_console(port) || console_suspend_enabled) {
pm_runtime_put_sync(dev);
clk_disable_unprepare(info->clk);
}
return 0;
}
static int of_serial_resume(struct device *dev)
{
struct of_serial_info *info = dev_get_drvdata(dev);
struct uart_8250_port *port8250 = serial8250_get_port(info->line);
struct uart_port *port = &port8250->port;
if (!uart_console(port) || console_suspend_enabled) {
pm_runtime_get_sync(dev);
clk_prepare_enable(info->clk);
}
serial8250_resume_port(info->line);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
/*
* A few common types, add more as needed.
*/
static const struct of_device_id of_platform_serial_table[] = {
{ .compatible = "ns8250", .data = (void *)PORT_8250, },
{ .compatible = "ns16450", .data = (void *)PORT_16450, },
{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
{ .compatible = "ns16550", .data = (void *)PORT_16550, },
{ .compatible = "ns16750", .data = (void *)PORT_16750, },
{ .compatible = "ns16850", .data = (void *)PORT_16850, },
{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
{ .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
{ .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, },
{ .compatible = "altr,16550-FIFO32",
.data = (void *)PORT_ALTR_16550_F32, },
{ .compatible = "altr,16550-FIFO64",
.data = (void *)PORT_ALTR_16550_F64, },
{ .compatible = "altr,16550-FIFO128",
.data = (void *)PORT_ALTR_16550_F128, },
{ .compatible = "fsl,16550-FIFO64",
.data = (void *)PORT_16550A_FSL64, },
{ .compatible = "mediatek,mtk-btif",
.data = (void *)PORT_MTK_BTIF, },
{ .compatible = "mrvl,mmp-uart",
.data = (void *)PORT_XSCALE, },
{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
{ .compatible = "nuvoton,wpcm450-uart", .data = (void *)PORT_NPCM, },
{ .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
{ /* end of list */ },
};
MODULE_DEVICE_TABLE(of, of_platform_serial_table);
static struct platform_driver of_platform_serial_driver = {
.driver = {
.name = "of_serial",
.of_match_table = of_platform_serial_table,
.pm = &of_serial_pm_ops,
},
.probe = of_platform_serial_probe,
.remove = of_platform_serial_remove,
};
module_platform_driver(of_platform_serial_driver);
MODULE_AUTHOR("Arnd Bergmann <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");
| linux-master | drivers/tty/serial/8250/8250_of.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Serial Port driver for Tegra devices
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include "8250.h"
struct tegra_uart {
struct clk *clk;
struct reset_control *rst;
int line;
};
static void tegra_uart_handle_break(struct uart_port *p)
{
unsigned int status, tmout = 10000;
while (1) {
status = p->serial_in(p, UART_LSR);
if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)))
break;
p->serial_in(p, UART_RX);
if (--tmout == 0)
break;
udelay(1);
}
}
static int tegra_uart_probe(struct platform_device *pdev)
{
struct uart_8250_port port8250;
struct tegra_uart *uart;
struct uart_port *port;
struct resource *res;
int ret;
uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
if (!uart)
return -ENOMEM;
memset(&port8250, 0, sizeof(port8250));
port = &port8250.port;
spin_lock_init(&port->lock);
port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
UPF_FIXED_TYPE;
port->iotype = UPIO_MEM32;
port->regshift = 2;
port->type = PORT_TEGRA;
port->irqflags |= IRQF_SHARED;
port->dev = &pdev->dev;
port->handle_break = tegra_uart_handle_break;
ret = of_alias_get_id(pdev->dev.of_node, "serial");
if (ret >= 0)
port->line = ret;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
port->irq = ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
port->membase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!port->membase)
return -ENOMEM;
port->mapbase = res->start;
port->mapsize = resource_size(res);
uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(uart->rst))
return PTR_ERR(uart->rst);
if (device_property_read_u32(&pdev->dev, "clock-frequency",
&port->uartclk)) {
uart->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(uart->clk)) {
dev_err(&pdev->dev, "failed to get clock!\n");
return -ENODEV;
}
ret = clk_prepare_enable(uart->clk);
if (ret < 0)
return ret;
port->uartclk = clk_get_rate(uart->clk);
}
ret = reset_control_deassert(uart->rst);
if (ret)
goto err_clkdisable;
ret = serial8250_register_8250_port(&port8250);
if (ret < 0)
goto err_ctrl_assert;
platform_set_drvdata(pdev, uart);
uart->line = ret;
return 0;
err_ctrl_assert:
reset_control_assert(uart->rst);
err_clkdisable:
clk_disable_unprepare(uart->clk);
return ret;
}
static int tegra_uart_remove(struct platform_device *pdev)
{
struct tegra_uart *uart = platform_get_drvdata(pdev);
serial8250_unregister_port(uart->line);
reset_control_assert(uart->rst);
clk_disable_unprepare(uart->clk);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int tegra_uart_suspend(struct device *dev)
{
struct tegra_uart *uart = dev_get_drvdata(dev);
struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
struct uart_port *port = &port8250->port;
serial8250_suspend_port(uart->line);
if (!uart_console(port) || console_suspend_enabled)
clk_disable_unprepare(uart->clk);
return 0;
}
static int tegra_uart_resume(struct device *dev)
{
struct tegra_uart *uart = dev_get_drvdata(dev);
struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
struct uart_port *port = &port8250->port;
if (!uart_console(port) || console_suspend_enabled)
clk_prepare_enable(uart->clk);
serial8250_resume_port(uart->line);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
tegra_uart_resume);
static const struct of_device_id tegra_uart_of_match[] = {
{ .compatible = "nvidia,tegra20-uart", },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
static const struct acpi_device_id tegra_uart_acpi_match[] __maybe_unused = {
{ "NVDA0100", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
static struct platform_driver tegra_uart_driver = {
.driver = {
.name = "tegra-uart",
.pm = &tegra_uart_pm_ops,
.of_match_table = tegra_uart_of_match,
.acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
},
.probe = tegra_uart_probe,
.remove = tegra_uart_remove,
};
module_platform_driver(tegra_uart_driver);
MODULE_AUTHOR("Jeff Brasen <[email protected]>");
MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/8250/8250_tegra.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SGI IOC3 8250 UART driver
*
* Copyright (C) 2019 Thomas Bogendoerfer <[email protected]>
*
* based on code Copyright (C) 2005 Stanislaw Skowronek <[email protected]>
* Copyright (C) 2014 Joshua Kinard <[email protected]>
*/
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include "8250.h"
#define IOC3_UARTCLK (22000000 / 3)
struct ioc3_8250_data {
int line;
};
static unsigned int ioc3_serial_in(struct uart_port *p, int offset)
{
return readb(p->membase + (offset ^ 3));
}
static void ioc3_serial_out(struct uart_port *p, int offset, int value)
{
writeb(value, p->membase + (offset ^ 3));
}
static int serial8250_ioc3_probe(struct platform_device *pdev)
{
struct ioc3_8250_data *data;
struct uart_8250_port up;
struct resource *r;
void __iomem *membase;
int irq, line;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r)
return -ENODEV;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
membase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!membase)
return -ENOMEM;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
irq = 0; /* no interrupt -> use polling */
/* Register serial ports with 8250.c */
memset(&up, 0, sizeof(struct uart_8250_port));
up.port.iotype = UPIO_MEM;
up.port.uartclk = IOC3_UARTCLK;
up.port.type = PORT_16550A;
up.port.irq = irq;
up.port.flags = (UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ);
up.port.dev = &pdev->dev;
up.port.membase = membase;
up.port.mapbase = r->start;
up.port.serial_in = ioc3_serial_in;
up.port.serial_out = ioc3_serial_out;
line = serial8250_register_8250_port(&up);
if (line < 0)
return line;
platform_set_drvdata(pdev, data);
return 0;
}
static int serial8250_ioc3_remove(struct platform_device *pdev)
{
struct ioc3_8250_data *data = platform_get_drvdata(pdev);
serial8250_unregister_port(data->line);
return 0;
}
static struct platform_driver serial8250_ioc3_driver = {
.probe = serial8250_ioc3_probe,
.remove = serial8250_ioc3_remove,
.driver = {
.name = "ioc3-serial8250",
}
};
module_platform_driver(serial8250_ioc3_driver);
MODULE_AUTHOR("Thomas Bogendoerfer <[email protected]>");
MODULE_DESCRIPTION("SGI IOC3 8250 UART driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_ioc3.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Serial Device Initialisation for Lasi/Asp/Wax/Dino
*
* (c) Copyright Matthew Wilcox <[email protected]> 2001-2002
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/serial_core.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <asm/hardware.h>
#include <asm/parisc-device.h>
#include <asm/io.h>
#include "8250.h"
static int __init serial_init_chip(struct parisc_device *dev)
{
struct uart_8250_port uart;
unsigned long address;
int err;
#if defined(CONFIG_64BIT) && defined(CONFIG_IOSAPIC)
if (!dev->irq && (dev->id.sversion == 0xad))
dev->irq = iosapic_serial_irq(dev);
#endif
if (!dev->irq) {
/* We find some unattached serial ports by walking native
* busses. These should be silently ignored. Otherwise,
* what we have here is a missing parent device, so tell
* the user what they're missing.
*/
if (parisc_parent(dev)->id.hw_type != HPHW_IOA)
dev_info(&dev->dev,
"Serial: device 0x%llx not configured.\n"
"Enable support for Wax, Lasi, Asp or Dino.\n",
(unsigned long long)dev->hpa.start);
return -ENODEV;
}
address = dev->hpa.start;
if (dev->id.sversion != 0x8d)
address += 0x800;
memset(&uart, 0, sizeof(uart));
uart.port.iotype = UPIO_MEM;
/* 7.272727MHz on Lasi. Assumed the same for Dino, Wax and Timi. */
uart.port.uartclk = (dev->id.sversion != 0xad) ?
7272727 : 1843200;
uart.port.mapbase = address;
uart.port.membase = ioremap(address, 16);
if (!uart.port.membase) {
dev_warn(&dev->dev, "Failed to map memory\n");
return -ENOMEM;
}
uart.port.irq = dev->irq;
uart.port.flags = UPF_BOOT_AUTOCONF;
uart.port.dev = &dev->dev;
err = serial8250_register_8250_port(&uart);
if (err < 0) {
dev_warn(&dev->dev,
"serial8250_register_8250_port returned error %d\n",
err);
iounmap(uart.port.membase);
return err;
}
return 0;
}
static const struct parisc_device_id serial_tbl[] __initconst = {
{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
{ HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x000ad },
{ 0 }
};
/* Hack. Some machines have SERIAL_0 attached to Lasi and SERIAL_1
* attached to Dino. Unfortunately, Dino appears before Lasi in the device
* tree. To ensure that ttyS0 == SERIAL_0, we register two drivers; one
* which only knows about Lasi and then a second which will find all the
* other serial ports. HPUX ignores this problem.
*/
static const struct parisc_device_id lasi_tbl[] __initconst = {
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03B, 0x0008C }, /* C1xx/C1xxL */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03C, 0x0008C }, /* B132L */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03D, 0x0008C }, /* B160L */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03E, 0x0008C }, /* B132L+ */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x03F, 0x0008C }, /* B180L+ */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x046, 0x0008C }, /* Rocky2 120 */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x047, 0x0008C }, /* Rocky2 150 */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
{ HPHW_FIO, HVERSION_REV_ANY_ID, 0x056, 0x0008C }, /* Raven+ */
{ 0 }
};
MODULE_DEVICE_TABLE(parisc, serial_tbl);
static struct parisc_driver lasi_driver __refdata = {
.name = "serial_1",
.id_table = lasi_tbl,
.probe = serial_init_chip,
};
static struct parisc_driver serial_driver __refdata = {
.name = "serial",
.id_table = serial_tbl,
.probe = serial_init_chip,
};
static int __init probe_serial_gsc(void)
{
register_parisc_driver(&lasi_driver);
register_parisc_driver(&serial_driver);
return 0;
}
module_init(probe_serial_gsc);
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_parisc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the 98626/98644/internal serial interface on hp300/hp400
* (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
*
* Ported from 2.2 and modified to use the normal 8250 driver
* by Kars de Jong <[email protected]>, May 2004.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/delay.h>
#include <linux/dio.h>
#include <linux/console.h>
#include <linux/slab.h>
#include <asm/io.h>
#include "8250.h"
#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI) && !defined(CONFIG_COMPILE_TEST)
#warning CONFIG_SERIAL_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
#endif
#ifdef CONFIG_HPAPCI
struct hp300_port {
struct hp300_port *next; /* next port */
int line; /* line (tty) number */
};
static struct hp300_port *hp300_ports;
#endif
#ifdef CONFIG_HPDCA
static int hpdca_init_one(struct dio_dev *d,
const struct dio_device_id *ent);
static void hpdca_remove_one(struct dio_dev *d);
static struct dio_device_id hpdca_dio_tbl[] = {
{ DIO_ID_DCA0 },
{ DIO_ID_DCA0REM },
{ DIO_ID_DCA1 },
{ DIO_ID_DCA1REM },
{ 0 }
};
static struct dio_driver hpdca_driver = {
.name = "hpdca",
.id_table = hpdca_dio_tbl,
.probe = hpdca_init_one,
.remove = hpdca_remove_one,
};
#endif
static unsigned int num_ports;
extern int hp300_uart_scode;
/* Offset to UART registers from base of DCA */
#define UART_OFFSET 17
#define DCA_ID 0x01 /* ID (read), reset (write) */
#define DCA_IC 0x03 /* Interrupt control */
/* Interrupt control */
#define DCA_IC_IE 0x80 /* Master interrupt enable */
#define HPDCA_BAUD_BASE 153600
/* Base address of the Frodo part */
#define FRODO_BASE (0x41c000)
/*
* Where we find the 8250-like APCI ports, and how far apart they are.
*/
#define FRODO_APCIBASE 0x0
#define FRODO_APCISPACE 0x20
#define FRODO_APCI_OFFSET(x) (FRODO_APCIBASE + ((x) * FRODO_APCISPACE))
#define HPAPCI_BAUD_BASE 500400
#ifdef CONFIG_SERIAL_8250_CONSOLE
/*
* Parse the bootinfo to find descriptions for headless console and
* debug serial ports and register them with the 8250 driver.
*/
int __init hp300_setup_serial_console(void)
{
int scode;
struct uart_port port;
memset(&port, 0, sizeof(port));
if (hp300_uart_scode < 0 || hp300_uart_scode > DIO_SCMAX)
return 0;
if (DIO_SCINHOLE(hp300_uart_scode))
return 0;
scode = hp300_uart_scode;
/* Memory mapped I/O */
port.iotype = UPIO_MEM;
port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
port.type = PORT_UNKNOWN;
/* Check for APCI console */
if (scode == 256) {
#ifdef CONFIG_HPAPCI
pr_info("Serial console is HP APCI 1\n");
port.uartclk = HPAPCI_BAUD_BASE * 16;
port.mapbase = (FRODO_BASE + FRODO_APCI_OFFSET(1));
port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
port.regshift = 2;
add_preferred_console("ttyS", port.line, "9600n8");
#else
pr_warn("Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
return 0;
#endif
} else {
#ifdef CONFIG_HPDCA
unsigned long pa = dio_scodetophysaddr(scode);
if (!pa)
return 0;
pr_info("Serial console is HP DCA at select code %d\n", scode);
port.uartclk = HPDCA_BAUD_BASE * 16;
port.mapbase = (pa + UART_OFFSET);
port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
port.regshift = 1;
port.irq = DIO_IPL(pa + DIO_VIRADDRBASE);
/* Enable board-interrupts */
out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80)
add_preferred_console("ttyS", port.line, "9600n8");
#else
pr_warn("Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
return 0;
#endif
}
if (early_serial_setup(&port) < 0)
pr_warn("%s: early_serial_setup() failed.\n", __func__);
return 0;
}
#endif /* CONFIG_SERIAL_8250_CONSOLE */
#ifdef CONFIG_HPDCA
static int hpdca_init_one(struct dio_dev *d,
const struct dio_device_id *ent)
{
struct uart_8250_port uart;
int line;
#ifdef CONFIG_SERIAL_8250_CONSOLE
if (hp300_uart_scode == d->scode) {
/* Already got it. */
return 0;
}
#endif
memset(&uart, 0, sizeof(uart));
/* Memory mapped I/O */
uart.port.iotype = UPIO_MEM;
uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
uart.port.irq = d->ipl;
uart.port.uartclk = HPDCA_BAUD_BASE * 16;
uart.port.mapbase = (d->resource.start + UART_OFFSET);
uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE);
uart.port.regshift = 1;
uart.port.dev = &d->dev;
line = serial8250_register_8250_port(&uart);
if (line < 0) {
dev_notice(&d->dev,
"8250_hp300: register_serial() DCA scode %d irq %d failed\n",
d->scode, uart.port.irq);
return -ENOMEM;
}
/* Enable board-interrupts */
out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
dio_set_drvdata(d, (void *)line);
/* Reset the DCA */
out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
udelay(100);
num_ports++;
return 0;
}
#endif
static int __init hp300_8250_init(void)
{
static int called;
#ifdef CONFIG_HPAPCI
int line;
unsigned long base;
struct uart_8250_port uart;
struct hp300_port *port;
int i;
#endif
if (called)
return -ENODEV;
called = 1;
if (!MACH_IS_HP300)
return -ENODEV;
#ifdef CONFIG_HPDCA
dio_register_driver(&hpdca_driver);
#endif
#ifdef CONFIG_HPAPCI
if (hp300_model < HP_400) {
if (!num_ports)
return -ENODEV;
return 0;
}
/* These models have the Frodo chip.
* Port 0 is reserved for the Apollo Domain keyboard.
* Port 1 is either the console or the DCA.
*/
for (i = 1; i < 4; i++) {
/* Port 1 is the console on a 425e, on other machines it's
* mapped to DCA.
*/
#ifdef CONFIG_SERIAL_8250_CONSOLE
if (i == 1)
continue;
#endif
/* Create new serial device */
port = kmalloc(sizeof(struct hp300_port), GFP_KERNEL);
if (!port)
return -ENOMEM;
memset(&uart, 0, sizeof(uart));
base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
/* Memory mapped I/O */
uart.port.iotype = UPIO_MEM;
uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ
| UPF_BOOT_AUTOCONF;
/* XXX - no interrupt support yet */
uart.port.irq = 0;
uart.port.uartclk = HPAPCI_BAUD_BASE * 16;
uart.port.mapbase = base;
uart.port.membase = (char *)(base + DIO_VIRADDRBASE);
uart.port.regshift = 2;
line = serial8250_register_8250_port(&uart);
if (line < 0) {
dev_notice(uart.port.dev,
"8250_hp300: register_serial() APCI %d irq %d failed\n",
i, uart.port.irq);
kfree(port);
continue;
}
port->line = line;
port->next = hp300_ports;
hp300_ports = port;
num_ports++;
}
#endif
/* Any boards found? */
if (!num_ports)
return -ENODEV;
return 0;
}
#ifdef CONFIG_HPDCA
static void hpdca_remove_one(struct dio_dev *d)
{
int line;
line = (int) dio_get_drvdata(d);
if (d->resource.start) {
/* Disable board-interrupts */
out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0);
}
serial8250_unregister_port(line);
}
#endif
static void __exit hp300_8250_exit(void)
{
#ifdef CONFIG_HPAPCI
struct hp300_port *port, *to_free;
for (port = hp300_ports; port; ) {
serial8250_unregister_port(port->line);
to_free = port;
port = port->next;
kfree(to_free);
}
hp300_ports = NULL;
#endif
#ifdef CONFIG_HPDCA
dio_unregister_driver(&hpdca_driver);
#endif
}
module_init(hp300_8250_init);
module_exit(hp300_8250_exit);
MODULE_DESCRIPTION("HP DCA/APCI serial driver");
MODULE_AUTHOR("Kars de Jong <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_hp300.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Probe module for 8250/16550-type PCI serial ports.
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*/
#undef DEBUG
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/math.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/tty.h>
#include <linux/serial_reg.h>
#include <linux/serial_core.h>
#include <linux/8250_pci.h>
#include <linux/bitops.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include "8250.h"
#include "8250_pcilib.h"
/*
* init function returns:
* > 0 - number of ports
* = 0 - use board->num_ports
* < 0 - error
*/
struct pci_serial_quirk {
u32 vendor;
u32 device;
u32 subvendor;
u32 subdevice;
int (*probe)(struct pci_dev *dev);
int (*init)(struct pci_dev *dev);
int (*setup)(struct serial_private *,
const struct pciserial_board *,
struct uart_8250_port *, int);
void (*exit)(struct pci_dev *dev);
};
struct f815xxa_data {
spinlock_t lock;
int idx;
};
struct serial_private {
struct pci_dev *dev;
unsigned int nr;
struct pci_serial_quirk *quirk;
const struct pciserial_board *board;
int line[];
};
#define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
static const struct pci_device_id pci_use_msi[] = {
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
0xA000, 0x1000) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
0xA000, 0x1000) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
0xA000, 0x1000) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
0xA000, 0x1000) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
PCI_ANY_ID, PCI_ANY_ID) },
{ }
};
static int pci_default_setup(struct serial_private*,
const struct pciserial_board*, struct uart_8250_port *, int);
static void moan_device(const char *str, struct pci_dev *dev)
{
pci_err(dev, "%s\n"
"Please send the output of lspci -vv, this\n"
"message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
"manufacturer and name of serial board or\n"
"modem board to <[email protected]>.\n",
str, dev->vendor, dev->device,
dev->subsystem_vendor, dev->subsystem_device);
}
static int
setup_port(struct serial_private *priv, struct uart_8250_port *port,
u8 bar, unsigned int offset, int regshift)
{
return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
}
/*
* ADDI-DATA GmbH communication cards <[email protected]>
*/
static int addidata_apci7800_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar = 0, offset = board->first_offset;
bar = FL_GET_BASE(board->flags);
if (idx < 2) {
offset += idx * board->uart_offset;
} else if ((idx >= 2) && (idx < 4)) {
bar += 1;
offset += ((idx - 2) * board->uart_offset);
} else if ((idx >= 4) && (idx < 6)) {
bar += 2;
offset += ((idx - 4) * board->uart_offset);
} else if (idx >= 6) {
bar += 3;
offset += ((idx - 6) * board->uart_offset);
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* AFAVLAB uses a different mixture of BARs and offsets
* Not that ugly ;) -- HW
*/
static int
afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
bar = FL_GET_BASE(board->flags);
if (idx < 4)
bar += idx;
else {
bar = 4;
offset += (idx - 4) * board->uart_offset;
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* HP's Remote Management Console. The Diva chip came in several
* different versions. N-class, L2000 and A500 have two Diva chips, each
* with 3 UARTs (the third UART on the second chip is unused). Superdome
* and Keystone have one Diva chip with 3 UARTs. Some later machines have
* one Diva chip, but it has been expanded to 5 UARTs.
*/
static int pci_hp_diva_init(struct pci_dev *dev)
{
int rc = 0;
switch (dev->subsystem_device) {
case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
case PCI_DEVICE_ID_HP_DIVA_EVEREST:
rc = 3;
break;
case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
rc = 2;
break;
case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
rc = 4;
break;
case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
rc = 1;
break;
}
return rc;
}
/*
* HP's Diva chip puts the 4th/5th serial port further out, and
* some serial ports are supposed to be hidden on certain models.
*/
static int
pci_hp_diva_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int offset = board->first_offset;
unsigned int bar = FL_GET_BASE(board->flags);
switch (priv->dev->subsystem_device) {
case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
if (idx == 3)
idx++;
break;
case PCI_DEVICE_ID_HP_DIVA_EVEREST:
if (idx > 0)
idx++;
if (idx > 2)
idx++;
break;
}
if (idx > 2)
offset = 0x18;
offset += idx * board->uart_offset;
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* Added for EKF Intel i960 serial boards
*/
static int pci_inteli960ni_init(struct pci_dev *dev)
{
u32 oldval;
if (!(dev->subsystem_device & 0x1000))
return -ENODEV;
/* is firmware started? */
pci_read_config_dword(dev, 0x44, &oldval);
if (oldval == 0x00001000L) { /* RESET value */
pci_dbg(dev, "Local i960 firmware missing\n");
return -ENODEV;
}
return 0;
}
/*
* Some PCI serial cards using the PLX 9050 PCI interface chip require
* that the card interrupt be explicitly enabled or disabled. This
* seems to be mainly needed on card using the PLX which also use I/O
* mapped memory.
*/
static int pci_plx9050_init(struct pci_dev *dev)
{
u8 irq_config;
void __iomem *p;
if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar 0", dev);
return 0;
}
irq_config = 0x41;
if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
irq_config = 0x43;
if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
(dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
/*
* As the megawolf cards have the int pins active
* high, and have 2 UART chips, both ints must be
* enabled on the 9050. Also, the UARTS are set in
* 16450 mode by default, so we have to enable the
* 16C950 'enhanced' mode so that we can use the
* deep FIFOs
*/
irq_config = 0x5b;
/*
* enable/disable interrupts
*/
p = ioremap(pci_resource_start(dev, 0), 0x80);
if (p == NULL)
return -ENOMEM;
writel(irq_config, p + 0x4c);
/*
* Read the register back to ensure that it took effect.
*/
readl(p + 0x4c);
iounmap(p);
return 0;
}
static void pci_plx9050_exit(struct pci_dev *dev)
{
u8 __iomem *p;
if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
return;
/*
* disable interrupts
*/
p = ioremap(pci_resource_start(dev, 0), 0x80);
if (p != NULL) {
writel(0, p + 0x4c);
/*
* Read the register back to ensure that it took effect.
*/
readl(p + 0x4c);
iounmap(p);
}
}
#define NI8420_INT_ENABLE_REG 0x38
#define NI8420_INT_ENABLE_BIT 0x2000
static void pci_ni8420_exit(struct pci_dev *dev)
{
void __iomem *p;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return;
}
p = pci_ioremap_bar(dev, bar);
if (p == NULL)
return;
/* Disable the CPU Interrupt */
writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
p + NI8420_INT_ENABLE_REG);
iounmap(p);
}
/* MITE registers */
#define MITE_IOWBSR1 0xc4
#define MITE_IOWCR1 0xf4
#define MITE_LCIMR1 0x08
#define MITE_LCIMR2 0x10
#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
static void pci_ni8430_exit(struct pci_dev *dev)
{
void __iomem *p;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return;
}
p = pci_ioremap_bar(dev, bar);
if (p == NULL)
return;
/* Disable the CPU Interrupt */
writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
iounmap(p);
}
/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
static int
sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
bar = 0;
if (idx < 4) {
/* first four channels map to 0, 0x100, 0x200, 0x300 */
offset += idx * board->uart_offset;
} else if (idx < 8) {
/* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
offset += idx * board->uart_offset + 0xC00;
} else /* we have only 8 ports on PMC-OCTALPRO */
return 1;
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* This does initialization for PMC OCTALPRO cards:
* maps the device memory, resets the UARTs (needed, bc
* if the module is removed and inserted again, the card
* is in the sleep mode) and enables global interrupt.
*/
/* global control register offset for SBS PMC-OctalPro */
#define OCT_REG_CR_OFF 0x500
static int sbs_init(struct pci_dev *dev)
{
u8 __iomem *p;
p = pci_ioremap_bar(dev, 0);
if (p == NULL)
return -ENOMEM;
/* Set bit-4 Control Register (UART RESET) in to reset the uarts */
writeb(0x10, p + OCT_REG_CR_OFF);
udelay(50);
writeb(0x0, p + OCT_REG_CR_OFF);
/* Set bit-2 (INTENABLE) of Control Register */
writeb(0x4, p + OCT_REG_CR_OFF);
iounmap(p);
return 0;
}
/*
* Disables the global interrupt of PMC-OctalPro
*/
static void sbs_exit(struct pci_dev *dev)
{
u8 __iomem *p;
p = pci_ioremap_bar(dev, 0);
/* FIXME: What if resource_len < OCT_REG_CR_OFF */
if (p != NULL)
writeb(0, p + OCT_REG_CR_OFF);
iounmap(p);
}
/*
* SIIG serial cards have an PCI interface chip which also controls
* the UART clocking frequency. Each UART can be clocked independently
* (except cards equipped with 4 UARTs) and initial clocking settings
* are stored in the EEPROM chip. It can cause problems because this
* version of serial driver doesn't support differently clocked UART's
* on single PCI card. To prevent this, initialization functions set
* high frequency clocking for all UART's on given card. It is safe (I
* hope) because it doesn't touch EEPROM settings to prevent conflicts
* with other OSes (like M$ DOS).
*
* SIIG support added by Andrey Panin <[email protected]>, 10/1999
*
* There is two family of SIIG serial cards with different PCI
* interface chip and different configuration methods:
* - 10x cards have control registers in IO and/or memory space;
* - 20x cards have control registers in standard PCI configuration space.
*
* Note: all 10x cards have PCI device ids 0x10..
* all 20x cards have PCI device ids 0x20..
*
* There are also Quartet Serial cards which use Oxford Semiconductor
* 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
*
* Note: some SIIG cards are probed by the parport_serial object.
*/
#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
static int pci_siig10x_init(struct pci_dev *dev)
{
u16 data;
void __iomem *p;
switch (dev->device & 0xfff8) {
case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
data = 0xffdf;
break;
case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
data = 0xf7ff;
break;
default: /* 1S1P, 4S */
data = 0xfffb;
break;
}
p = ioremap(pci_resource_start(dev, 0), 0x80);
if (p == NULL)
return -ENOMEM;
writew(readw(p + 0x28) & data, p + 0x28);
readw(p + 0x28);
iounmap(p);
return 0;
}
#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
static int pci_siig20x_init(struct pci_dev *dev)
{
u8 data;
/* Change clock frequency for the first UART. */
pci_read_config_byte(dev, 0x6f, &data);
pci_write_config_byte(dev, 0x6f, data & 0xef);
/* If this card has 2 UART, we have to do the same with second UART. */
if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
pci_read_config_byte(dev, 0x73, &data);
pci_write_config_byte(dev, 0x73, data & 0xef);
}
return 0;
}
static int pci_siig_init(struct pci_dev *dev)
{
unsigned int type = dev->device & 0xff00;
if (type == 0x1000)
return pci_siig10x_init(dev);
if (type == 0x2000)
return pci_siig20x_init(dev);
moan_device("Unknown SIIG card", dev);
return -ENODEV;
}
static int pci_siig_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
if (idx > 3) {
bar = 4;
offset = (idx - 4) * 8;
}
return setup_port(priv, port, bar, offset, 0);
}
/*
* Timedia has an explosion of boards, and to avoid the PCI table from
* growing *huge*, we use this function to collapse some 70 entries
* in the PCI table into one, for sanity's and compactness's sake.
*/
static const unsigned short timedia_single_port[] = {
0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
};
static const unsigned short timedia_dual_port[] = {
0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
0xD079, 0
};
static const unsigned short timedia_quad_port[] = {
0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
0xB157, 0
};
static const unsigned short timedia_eight_port[] = {
0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
};
static const struct timedia_struct {
int num;
const unsigned short *ids;
} timedia_data[] = {
{ 1, timedia_single_port },
{ 2, timedia_dual_port },
{ 4, timedia_quad_port },
{ 8, timedia_eight_port }
};
/*
* There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
* listing them individually, this driver merely grabs them all with
* PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
* and should be left free to be claimed by parport_serial instead.
*/
static int pci_timedia_probe(struct pci_dev *dev)
{
/*
* Check the third digit of the subdevice ID
* (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
*/
if ((dev->subsystem_device & 0x00f0) >= 0x70) {
pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
dev->subsystem_device);
return -ENODEV;
}
return 0;
}
static int pci_timedia_init(struct pci_dev *dev)
{
const unsigned short *ids;
int i, j;
for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
ids = timedia_data[i].ids;
for (j = 0; ids[j]; j++)
if (dev->subsystem_device == ids[j])
return timedia_data[i].num;
}
return 0;
}
/*
* Timedia/SUNIX uses a mixture of BARs and offsets
* Ugh, this is ugly as all hell --- TYT
*/
static int
pci_timedia_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar = 0, offset = board->first_offset;
switch (idx) {
case 0:
bar = 0;
break;
case 1:
offset = board->uart_offset;
bar = 0;
break;
case 2:
bar = 1;
break;
case 3:
offset = board->uart_offset;
fallthrough;
case 4: /* BAR 2 */
case 5: /* BAR 3 */
case 6: /* BAR 4 */
case 7: /* BAR 5 */
bar = idx - 2;
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
/*
* Some Titan cards are also a little weird
*/
static int
titan_400l_800l_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
switch (idx) {
case 0:
bar = 1;
break;
case 1:
bar = 2;
break;
default:
bar = 4;
offset = (idx - 2) * board->uart_offset;
}
return setup_port(priv, port, bar, offset, board->reg_shift);
}
static int pci_xircom_init(struct pci_dev *dev)
{
msleep(100);
return 0;
}
static int pci_ni8420_init(struct pci_dev *dev)
{
void __iomem *p;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return 0;
}
p = pci_ioremap_bar(dev, bar);
if (p == NULL)
return -ENOMEM;
/* Enable CPU Interrupt */
writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
p + NI8420_INT_ENABLE_REG);
iounmap(p);
return 0;
}
#define MITE_IOWBSR1_WSIZE 0xa
#define MITE_IOWBSR1_WIN_OFFSET 0x800
#define MITE_IOWBSR1_WENAB (1 << 7)
#define MITE_LCIMR1_IO_IE_0 (1 << 24)
#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
static int pci_ni8430_init(struct pci_dev *dev)
{
void __iomem *p;
struct pci_bus_region region;
u32 device_window;
unsigned int bar = 0;
if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
moan_device("no memory in bar", dev);
return 0;
}
p = pci_ioremap_bar(dev, bar);
if (p == NULL)
return -ENOMEM;
/*
* Set device window address and size in BAR0, while acknowledging that
* the resource structure may contain a translated address that differs
* from the address the device responds to.
*/
pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
| MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
writel(device_window, p + MITE_IOWBSR1);
/* Set window access to go to RAMSEL IO address space */
writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
p + MITE_IOWCR1);
/* Enable IO Bus Interrupt 0 */
writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
/* Enable CPU Interrupt */
writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
iounmap(p);
return 0;
}
/* UART Port Control Register */
#define NI8430_PORTCON 0x0f
#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
static int
pci_ni8430_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
struct pci_dev *dev = priv->dev;
void __iomem *p;
unsigned int bar, offset = board->first_offset;
if (idx >= board->num_ports)
return 1;
bar = FL_GET_BASE(board->flags);
offset += idx * board->uart_offset;
p = pci_ioremap_bar(dev, bar);
if (!p)
return -ENOMEM;
/* enable the transceiver */
writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
p + offset + NI8430_PORTCON);
iounmap(p);
return setup_port(priv, port, bar, offset, board->reg_shift);
}
static int pci_netmos_9900_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar;
if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
(priv->dev->subsystem_device & 0xff00) == 0x3000) {
/* netmos apparently orders BARs by datasheet layout, so serial
* ports get BARs 0 and 3 (or 1 and 4 for memmapped)
*/
bar = 3 * idx;
return setup_port(priv, port, bar, 0, board->reg_shift);
}
return pci_default_setup(priv, board, port, idx);
}
/* the 99xx series comes with a range of device IDs and a variety
* of capabilities:
*
* 9900 has varying capabilities and can cascade to sub-controllers
* (cascading should be purely internal)
* 9904 is hardwired with 4 serial ports
* 9912 and 9922 are hardwired with 2 serial ports
*/
static int pci_netmos_9900_numports(struct pci_dev *dev)
{
unsigned int c = dev->class;
unsigned int pi;
unsigned short sub_serports;
pi = c & 0xff;
if (pi == 2)
return 1;
if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
/* two possibilities: 0x30ps encodes number of parallel and
* serial ports, or 0x1000 indicates *something*. This is not
* immediately obvious, since the 2s1p+4s configuration seems
* to offer all functionality on functions 0..2, while still
* advertising the same function 3 as the 4s+2s1p config.
*/
sub_serports = dev->subsystem_device & 0xf;
if (sub_serports > 0)
return sub_serports;
pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
return 0;
}
moan_device("unknown NetMos/Mostech program interface", dev);
return 0;
}
static int pci_netmos_init(struct pci_dev *dev)
{
/* subdevice 0x00PS means <P> parallel, <S> serial */
unsigned int num_serial = dev->subsystem_device & 0xf;
if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
(dev->device == PCI_DEVICE_ID_NETMOS_9865))
return 0;
if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
dev->subsystem_device == 0x0299)
return 0;
switch (dev->device) { /* FALLTHROUGH on all */
case PCI_DEVICE_ID_NETMOS_9904:
case PCI_DEVICE_ID_NETMOS_9912:
case PCI_DEVICE_ID_NETMOS_9922:
case PCI_DEVICE_ID_NETMOS_9900:
num_serial = pci_netmos_9900_numports(dev);
break;
default:
break;
}
if (num_serial == 0) {
moan_device("unknown NetMos/Mostech device", dev);
return -ENODEV;
}
return num_serial;
}
/*
* These chips are available with optionally one parallel port and up to
* two serial ports. Unfortunately they all have the same product id.
*
* Basic configuration is done over a region of 32 I/O ports. The base
* ioport is called INTA or INTC, depending on docs/other drivers.
*
* The region of the 32 I/O ports is configured in POSIO0R...
*/
/* registers */
#define ITE_887x_MISCR 0x9c
#define ITE_887x_INTCBAR 0x78
#define ITE_887x_UARTBAR 0x7c
#define ITE_887x_PS0BAR 0x10
#define ITE_887x_POSIO0 0x60
/* I/O space size */
#define ITE_887x_IOSIZE 32
/* I/O space size (bits 26-24; 8 bytes = 011b) */
#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
/* I/O space size (bits 26-24; 32 bytes = 101b) */
#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
#define ITE_887x_POSIO_SPEED (3 << 29)
/* enable IO_Space bit */
#define ITE_887x_POSIO_ENABLE (1 << 31)
/* inta_addr are the configuration addresses of the ITE */
static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
static int pci_ite887x_init(struct pci_dev *dev)
{
int ret, i, type;
struct resource *iobase = NULL;
u32 miscr, uartbar, ioport;
/* search for the base-ioport */
for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
"ite887x");
if (iobase != NULL) {
/* write POSIO0R - speed | size | ioport */
pci_write_config_dword(dev, ITE_887x_POSIO0,
ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
/* write INTCBAR - ioport */
pci_write_config_dword(dev, ITE_887x_INTCBAR,
inta_addr[i]);
ret = inb(inta_addr[i]);
if (ret != 0xff) {
/* ioport connected */
break;
}
release_region(iobase->start, ITE_887x_IOSIZE);
}
}
if (i == ARRAY_SIZE(inta_addr)) {
pci_err(dev, "could not find iobase\n");
return -ENODEV;
}
/* start of undocumented type checking (see parport_pc.c) */
type = inb(iobase->start + 0x18) & 0x0f;
switch (type) {
case 0x2: /* ITE8871 (1P) */
case 0xa: /* ITE8875 (1P) */
ret = 0;
break;
case 0xe: /* ITE8872 (2S1P) */
ret = 2;
break;
case 0x6: /* ITE8873 (1S) */
ret = 1;
break;
case 0x8: /* ITE8874 (2S) */
ret = 2;
break;
default:
moan_device("Unknown ITE887x", dev);
ret = -ENODEV;
}
/* configure all serial ports */
for (i = 0; i < ret; i++) {
/* read the I/O port from the device */
pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
&ioport);
ioport &= 0x0000FF00; /* the actual base address */
pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
ITE_887x_POSIO_IOSIZE_8 | ioport);
/* write the ioport to the UARTBAR */
pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
uartbar |= (ioport << (16 * i)); /* set the ioport */
pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
/* get current config */
pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
/* disable interrupts (UARTx_Routing[3:0]) */
miscr &= ~(0xf << (12 - 4 * i));
/* activate the UART (UARTx_En) */
miscr |= 1 << (23 - i);
/* write new config with activated UART */
pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
}
if (ret <= 0) {
/* the device has no UARTs if we get here */
release_region(iobase->start, ITE_887x_IOSIZE);
}
return ret;
}
static void pci_ite887x_exit(struct pci_dev *dev)
{
u32 ioport;
/* the ioport is bit 0-15 in POSIO0R */
pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
ioport &= 0xffff;
release_region(ioport, ITE_887x_IOSIZE);
}
/*
* Oxford Semiconductor Inc.
* Check if an OxSemi device is part of the Tornado range of devices.
*/
#define PCI_VENDOR_ID_ENDRUN 0x7401
#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
{
/* OxSemi Tornado devices are all 0xCxxx */
if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
(dev->device & 0xf000) != 0xc000)
return false;
/* EndRun devices are all 0xExxx */
if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
(dev->device & 0xf000) != 0xe000)
return false;
return true;
}
/*
* Determine the number of ports available on a Tornado device.
*/
static int pci_oxsemi_tornado_init(struct pci_dev *dev)
{
u8 __iomem *p;
unsigned long deviceID;
unsigned int number_uarts = 0;
if (!pci_oxsemi_tornado_p(dev))
return 0;
p = pci_iomap(dev, 0, 5);
if (p == NULL)
return -ENOMEM;
deviceID = ioread32(p);
/* Tornado device */
if (deviceID == 0x07000200) {
number_uarts = ioread8(p + 4);
pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
number_uarts,
dev->vendor == PCI_VENDOR_ID_ENDRUN ?
"EndRun" : "Oxford");
}
pci_iounmap(dev, p);
return number_uarts;
}
/* Tornado-specific constants for the TCR and CPR registers; see below. */
#define OXSEMI_TORNADO_TCR_MASK 0xf
#define OXSEMI_TORNADO_CPR_MASK 0x1ff
#define OXSEMI_TORNADO_CPR_MIN 0x008
#define OXSEMI_TORNADO_CPR_DEF 0x10f
/*
* Determine the oversampling rate, the clock prescaler, and the clock
* divisor for the requested baud rate. The clock rate is 62.5 MHz,
* which is four times the baud base, and the prescaler increments in
* steps of 1/8. Therefore to make calculations on integers we need
* to use a scaled clock rate, which is the baud base multiplied by 32
* (or our assumed UART clock rate multiplied by 2).
*
* The allowed oversampling rates are from 4 up to 16 inclusive (values
* from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
* values between 1.000 and 63.875 inclusive (operation for values from
* 0.000 to 0.875 has not been specified). The clock divisor is the usual
* unsigned 16-bit integer.
*
* For the most accurate baud rate we use a table of predetermined
* oversampling rates and clock prescalers that records all possible
* products of the two parameters in the range from 4 up to 255 inclusive,
* and additionally 335 for the 1500000bps rate, with the prescaler scaled
* by 8. The table is sorted by the decreasing value of the oversampling
* rate and ties are resolved by sorting by the decreasing value of the
* product. This way preference is given to higher oversampling rates.
*
* We iterate over the table and choose the product of an oversampling
* rate and a clock prescaler that gives the lowest integer division
* result deviation, or if an exact integer divider is found we stop
* looking for it right away. We do some fixup if the resulting clock
* divisor required would be out of its unsigned 16-bit integer range.
*
* Finally we abuse the supposed fractional part returned to encode the
* 4-bit value of the oversampling rate and the 9-bit value of the clock
* prescaler which will end up in the TCR and CPR/CPR2 registers.
*/
static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
unsigned int baud,
unsigned int *frac)
{
static u8 p[][2] = {
{ 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
{ 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
{ 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
{ 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
{ 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
{ 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
{ 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
{ 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
{ 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
{ 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
{ 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
{ 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
{ 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
{ 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
{ 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
{ 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
{ 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
{ 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
{ 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
{ 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
{ 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
{ 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
{ 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
{ 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
{ 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
{ 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
{ 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
{ 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
{ 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
{ 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
{ 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
{ 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
{ 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
{ 4, 9, }, { 4, 8, },
};
/* Scale the quotient for comparison to get the fractional part. */
const unsigned int quot_scale = 65536;
unsigned int sclk = port->uartclk * 2;
unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
unsigned int best_squot;
unsigned int squot;
unsigned int quot;
u16 cpr;
u8 tcr;
int i;
/* Old custom speed handling. */
if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
unsigned int cust_div = port->custom_divisor;
quot = cust_div & UART_DIV_MAX;
tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
if (cpr < OXSEMI_TORNADO_CPR_MIN)
cpr = OXSEMI_TORNADO_CPR_DEF;
} else {
best_squot = quot_scale;
for (i = 0; i < ARRAY_SIZE(p); i++) {
unsigned int spre;
unsigned int srem;
u8 cp;
u8 tc;
tc = p[i][0];
cp = p[i][1];
spre = tc * cp;
srem = sdiv % spre;
if (srem > spre / 2)
srem = spre - srem;
squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
if (srem == 0) {
tcr = tc;
cpr = cp;
quot = sdiv / spre;
break;
} else if (squot < best_squot) {
best_squot = squot;
tcr = tc;
cpr = cp;
quot = DIV_ROUND_CLOSEST(sdiv, spre);
}
}
while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
quot % 2 == 0) {
quot >>= 1;
tcr <<= 1;
}
while (quot > UART_DIV_MAX) {
if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
quot >>= 1;
tcr <<= 1;
} else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
quot >>= 1;
cpr <<= 1;
} else {
quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
cpr = OXSEMI_TORNADO_CPR_MASK;
}
}
}
*frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
return quot;
}
/*
* Set the oversampling rate in the transmitter clock cycle register (TCR),
* the clock prescaler in the clock prescaler register (CPR and CPR2), and
* the clock divisor in the divisor latch (DLL and DLM). Note that for
* backwards compatibility any write to CPR clears CPR2 and therefore CPR
* has to be written first, followed by CPR2, which occupies the location
* of CKS used with earlier UART designs.
*/
static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
unsigned int baud,
unsigned int quot,
unsigned int quot_frac)
{
struct uart_8250_port *up = up_to_u8250p(port);
u8 cpr2 = quot_frac >> 16;
u8 cpr = quot_frac >> 8;
u8 tcr = quot_frac;
serial_icr_write(up, UART_TCR, tcr);
serial_icr_write(up, UART_CPR, cpr);
serial_icr_write(up, UART_CKS, cpr2);
serial8250_do_set_divisor(port, baud, quot, 0);
}
/*
* For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
* generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
*/
static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
unsigned int mctrl)
{
struct uart_8250_port *up = up_to_u8250p(port);
up->mcr |= UART_MCR_CLKSEL;
serial8250_do_set_mctrl(port, mctrl);
}
/*
* We require EFR features for clock programming, so set UPF_FULL_PROBE
* for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
*/
static int pci_oxsemi_tornado_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *up, int idx)
{
struct pci_dev *dev = priv->dev;
if (pci_oxsemi_tornado_p(dev)) {
up->port.flags |= UPF_FULL_PROBE;
up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
}
return pci_default_setup(priv, board, up, idx);
}
#define QPCR_TEST_FOR1 0x3F
#define QPCR_TEST_GET1 0x00
#define QPCR_TEST_FOR2 0x40
#define QPCR_TEST_GET2 0x40
#define QPCR_TEST_FOR3 0x80
#define QPCR_TEST_GET3 0x40
#define QPCR_TEST_FOR4 0xC0
#define QPCR_TEST_GET4 0x80
#define QOPR_CLOCK_X1 0x0000
#define QOPR_CLOCK_X2 0x0001
#define QOPR_CLOCK_X4 0x0002
#define QOPR_CLOCK_X8 0x0003
#define QOPR_CLOCK_RATE_MASK 0x0003
/* Quatech devices have their own extra interface features */
static struct pci_device_id quatech_cards[] = {
{ PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
{ PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
{ PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
{ PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
{ PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
{ PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
{ PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
{ PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
{ PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
{ PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
{ PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
{ PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
{ PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
{ PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
{ PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
{ PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
{ PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
{ PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
{ PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
{ 0, }
};
static int pci_quatech_rqopr(struct uart_8250_port *port)
{
unsigned long base = port->port.iobase;
u8 LCR, val;
LCR = inb(base + UART_LCR);
outb(0xBF, base + UART_LCR);
val = inb(base + UART_SCR);
outb(LCR, base + UART_LCR);
return val;
}
static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
{
unsigned long base = port->port.iobase;
u8 LCR;
LCR = inb(base + UART_LCR);
outb(0xBF, base + UART_LCR);
inb(base + UART_SCR);
outb(qopr, base + UART_SCR);
outb(LCR, base + UART_LCR);
}
static int pci_quatech_rqmcr(struct uart_8250_port *port)
{
unsigned long base = port->port.iobase;
u8 LCR, val, qmcr;
LCR = inb(base + UART_LCR);
outb(0xBF, base + UART_LCR);
val = inb(base + UART_SCR);
outb(val | 0x10, base + UART_SCR);
qmcr = inb(base + UART_MCR);
outb(val, base + UART_SCR);
outb(LCR, base + UART_LCR);
return qmcr;
}
static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
{
unsigned long base = port->port.iobase;
u8 LCR, val;
LCR = inb(base + UART_LCR);
outb(0xBF, base + UART_LCR);
val = inb(base + UART_SCR);
outb(val | 0x10, base + UART_SCR);
outb(qmcr, base + UART_MCR);
outb(val, base + UART_SCR);
outb(LCR, base + UART_LCR);
}
static int pci_quatech_has_qmcr(struct uart_8250_port *port)
{
unsigned long base = port->port.iobase;
u8 LCR, val;
LCR = inb(base + UART_LCR);
outb(0xBF, base + UART_LCR);
val = inb(base + UART_SCR);
if (val & 0x20) {
outb(0x80, UART_LCR);
if (!(inb(UART_SCR) & 0x20)) {
outb(LCR, base + UART_LCR);
return 1;
}
}
return 0;
}
static int pci_quatech_test(struct uart_8250_port *port)
{
u8 reg, qopr;
qopr = pci_quatech_rqopr(port);
pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
reg = pci_quatech_rqopr(port) & 0xC0;
if (reg != QPCR_TEST_GET1)
return -EINVAL;
pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
reg = pci_quatech_rqopr(port) & 0xC0;
if (reg != QPCR_TEST_GET2)
return -EINVAL;
pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
reg = pci_quatech_rqopr(port) & 0xC0;
if (reg != QPCR_TEST_GET3)
return -EINVAL;
pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
reg = pci_quatech_rqopr(port) & 0xC0;
if (reg != QPCR_TEST_GET4)
return -EINVAL;
pci_quatech_wqopr(port, qopr);
return 0;
}
static int pci_quatech_clock(struct uart_8250_port *port)
{
u8 qopr, reg, set;
unsigned long clock;
if (pci_quatech_test(port) < 0)
return 1843200;
qopr = pci_quatech_rqopr(port);
pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
reg = pci_quatech_rqopr(port);
if (reg & QOPR_CLOCK_X8) {
clock = 1843200;
goto out;
}
pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
reg = pci_quatech_rqopr(port);
if (!(reg & QOPR_CLOCK_X8)) {
clock = 1843200;
goto out;
}
reg &= QOPR_CLOCK_X8;
if (reg == QOPR_CLOCK_X2) {
clock = 3685400;
set = QOPR_CLOCK_X2;
} else if (reg == QOPR_CLOCK_X4) {
clock = 7372800;
set = QOPR_CLOCK_X4;
} else if (reg == QOPR_CLOCK_X8) {
clock = 14745600;
set = QOPR_CLOCK_X8;
} else {
clock = 1843200;
set = QOPR_CLOCK_X1;
}
qopr &= ~QOPR_CLOCK_RATE_MASK;
qopr |= set;
out:
pci_quatech_wqopr(port, qopr);
return clock;
}
static int pci_quatech_rs422(struct uart_8250_port *port)
{
u8 qmcr;
int rs422 = 0;
if (!pci_quatech_has_qmcr(port))
return 0;
qmcr = pci_quatech_rqmcr(port);
pci_quatech_wqmcr(port, 0xFF);
if (pci_quatech_rqmcr(port))
rs422 = 1;
pci_quatech_wqmcr(port, qmcr);
return rs422;
}
static int pci_quatech_init(struct pci_dev *dev)
{
const struct pci_device_id *match;
bool amcc = false;
match = pci_match_id(quatech_cards, dev);
if (match)
amcc = match->driver_data;
else
pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
if (amcc) {
unsigned long base = pci_resource_start(dev, 0);
if (base) {
u32 tmp;
outl(inl(base + 0x38) | 0x00002000, base + 0x38);
tmp = inl(base + 0x3c);
outl(tmp | 0x01000000, base + 0x3c);
outl(tmp & ~0x01000000, base + 0x3c);
}
}
return 0;
}
static int pci_quatech_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
/* Needed by pci_quatech calls below */
port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
/* Set up the clocking */
port->port.uartclk = pci_quatech_clock(port);
/* For now just warn about RS422 */
if (pci_quatech_rs422(port))
pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
return pci_default_setup(priv, board, port, idx);
}
static int pci_default_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar, offset = board->first_offset, maxnr;
bar = FL_GET_BASE(board->flags);
if (board->flags & FL_BASE_BARS)
bar += idx;
else
offset += idx * board->uart_offset;
maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
(board->reg_shift + 3);
if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
return 1;
return setup_port(priv, port, bar, offset, board->reg_shift);
}
static int
ce4100_serial_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
int ret;
ret = setup_port(priv, port, idx, 0, board->reg_shift);
port->port.iotype = UPIO_MEM32;
port->port.type = PORT_XSCALE;
port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
port->port.regshift = 2;
return ret;
}
static int
pci_omegapci_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
return setup_port(priv, port, 2, idx * 8, 0);
}
static int
pci_brcm_trumanage_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
int ret = pci_default_setup(priv, board, port, idx);
port->port.type = PORT_BRCM_TRUMANAGE;
port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
return ret;
}
/* RTS will control by MCR if this bit is 0 */
#define FINTEK_RTS_CONTROL_BY_HW BIT(4)
/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
#define FINTEK_RTS_INVERT BIT(5)
/* We should do proper H/W transceiver setting before change to RS485 mode */
static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct pci_dev *pci_dev = to_pci_dev(port->dev);
u8 setting;
u8 *index = (u8 *) port->private_data;
pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
if (rs485->flags & SER_RS485_ENABLED) {
/* Enable RTS H/W control mode */
setting |= FINTEK_RTS_CONTROL_BY_HW;
if (rs485->flags & SER_RS485_RTS_ON_SEND) {
/* RTS driving high on TX */
setting &= ~FINTEK_RTS_INVERT;
} else {
/* RTS driving low on TX */
setting |= FINTEK_RTS_INVERT;
}
} else {
/* Disable RTS H/W control mode */
setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
}
pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
return 0;
}
static const struct serial_rs485 pci_fintek_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
/* F81504/508/512 does not support RTS delay before or after send */
};
static int pci_fintek_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
struct pci_dev *pdev = priv->dev;
u8 *data;
u8 config_base;
u16 iobase;
config_base = 0x40 + 0x08 * idx;
/* Get the io address from configuration space */
pci_read_config_word(pdev, config_base + 4, &iobase);
pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
port->port.iotype = UPIO_PORT;
port->port.iobase = iobase;
port->port.rs485_config = pci_fintek_rs485_config;
port->port.rs485_supported = pci_fintek_rs485_supported;
data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
if (!data)
return -ENOMEM;
/* preserve index in PCI configuration space */
*data = idx;
port->port.private_data = data;
return 0;
}
static int pci_fintek_init(struct pci_dev *dev)
{
unsigned long iobase;
u32 max_port, i;
resource_size_t bar_data[3];
u8 config_base;
struct serial_private *priv = pci_get_drvdata(dev);
if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
!(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
!(pci_resource_flags(dev, 3) & IORESOURCE_IO))
return -ENODEV;
switch (dev->device) {
case 0x1104: /* 4 ports */
case 0x1108: /* 8 ports */
max_port = dev->device & 0xff;
break;
case 0x1112: /* 12 ports */
max_port = 12;
break;
default:
return -EINVAL;
}
/* Get the io address dispatch from the BIOS */
bar_data[0] = pci_resource_start(dev, 5);
bar_data[1] = pci_resource_start(dev, 4);
bar_data[2] = pci_resource_start(dev, 3);
for (i = 0; i < max_port; ++i) {
/* UART0 configuration offset start from 0x40 */
config_base = 0x40 + 0x08 * i;
/* Calculate Real IO Port */
iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
/* Enable UART I/O port */
pci_write_config_byte(dev, config_base + 0x00, 0x01);
/* Select 128-byte FIFO and 8x FIFO threshold */
pci_write_config_byte(dev, config_base + 0x01, 0x33);
/* LSB UART */
pci_write_config_byte(dev, config_base + 0x04,
(u8)(iobase & 0xff));
/* MSB UART */
pci_write_config_byte(dev, config_base + 0x05,
(u8)((iobase & 0xff00) >> 8));
pci_write_config_byte(dev, config_base + 0x06, dev->irq);
if (!priv) {
/* First init without port data
* force init to RS232 Mode
*/
pci_write_config_byte(dev, config_base + 0x07, 0x01);
}
}
return max_port;
}
static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
{
struct f815xxa_data *data = p->private_data;
unsigned long flags;
spin_lock_irqsave(&data->lock, flags);
writeb(value, p->membase + offset);
readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
spin_unlock_irqrestore(&data->lock, flags);
}
static int pci_fintek_f815xxa_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
struct pci_dev *pdev = priv->dev;
struct f815xxa_data *data;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->idx = idx;
spin_lock_init(&data->lock);
port->port.private_data = data;
port->port.iotype = UPIO_MEM;
port->port.flags |= UPF_IOREMAP;
port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
port->port.serial_out = f815xxa_mem_serial_out;
return 0;
}
static int pci_fintek_f815xxa_init(struct pci_dev *dev)
{
u32 max_port, i;
int config_base;
if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
return -ENODEV;
switch (dev->device) {
case 0x1204: /* 4 ports */
case 0x1208: /* 8 ports */
max_port = dev->device & 0xff;
break;
case 0x1212: /* 12 ports */
max_port = 12;
break;
default:
return -EINVAL;
}
/* Set to mmio decode */
pci_write_config_byte(dev, 0x209, 0x40);
for (i = 0; i < max_port; ++i) {
/* UART0 configuration offset start from 0x2A0 */
config_base = 0x2A0 + 0x08 * i;
/* Select 128-byte FIFO and 8x FIFO threshold */
pci_write_config_byte(dev, config_base + 0x01, 0x33);
/* Enable UART I/O port */
pci_write_config_byte(dev, config_base + 0, 0x01);
}
return max_port;
}
static int skip_tx_en_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
port->port.quirks |= UPQ_NO_TXEN_TEST;
pci_dbg(priv->dev,
"serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
priv->dev->vendor, priv->dev->device,
priv->dev->subsystem_vendor, priv->dev->subsystem_device);
return pci_default_setup(priv, board, port, idx);
}
static void kt_handle_break(struct uart_port *p)
{
struct uart_8250_port *up = up_to_u8250p(p);
/*
* On receipt of a BI, serial device in Intel ME (Intel
* management engine) needs to have its fifos cleared for sane
* SOL (Serial Over Lan) output.
*/
serial8250_clear_and_reinit_fifos(up);
}
static unsigned int kt_serial_in(struct uart_port *p, int offset)
{
struct uart_8250_port *up = up_to_u8250p(p);
unsigned int val;
/*
* When the Intel ME (management engine) gets reset its serial
* port registers could return 0 momentarily. Functions like
* serial8250_console_write, read and save the IER, perform
* some operation and then restore it. In order to avoid
* setting IER register inadvertently to 0, if the value read
* is 0, double check with ier value in uart_8250_port and use
* that instead. up->ier should be the same value as what is
* currently configured.
*/
val = inb(p->iobase + offset);
if (offset == UART_IER) {
if (val == 0)
val = up->ier;
}
return val;
}
static int kt_serial_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
port->port.flags |= UPF_BUG_THRE;
port->port.serial_in = kt_serial_in;
port->port.handle_break = kt_handle_break;
return skip_tx_en_setup(priv, board, port, idx);
}
static int pci_eg20t_init(struct pci_dev *dev)
{
#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
return -ENODEV;
#else
return 0;
#endif
}
static int
pci_wch_ch353_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
port->port.flags |= UPF_FIXED_TYPE;
port->port.type = PORT_16550A;
return pci_default_setup(priv, board, port, idx);
}
static int
pci_wch_ch355_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
port->port.flags |= UPF_FIXED_TYPE;
port->port.type = PORT_16550A;
return pci_default_setup(priv, board, port, idx);
}
static int
pci_wch_ch38x_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
port->port.flags |= UPF_FIXED_TYPE;
port->port.type = PORT_16850;
return pci_default_setup(priv, board, port, idx);
}
#define CH384_XINT_ENABLE_REG 0xEB
#define CH384_XINT_ENABLE_BIT 0x02
static int pci_wch_ch38x_init(struct pci_dev *dev)
{
int max_port;
unsigned long iobase;
switch (dev->device) {
case 0x3853: /* 8 ports */
max_port = 8;
break;
default:
return -EINVAL;
}
iobase = pci_resource_start(dev, 0);
outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
return max_port;
}
static void pci_wch_ch38x_exit(struct pci_dev *dev)
{
unsigned long iobase;
iobase = pci_resource_start(dev, 0);
outb(0x0, iobase + CH384_XINT_ENABLE_REG);
}
static int
pci_sunix_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
int bar;
int offset;
port->port.flags |= UPF_FIXED_TYPE;
port->port.type = PORT_SUNIX;
if (idx < 4) {
bar = 0;
offset = idx * board->uart_offset;
} else {
bar = 1;
idx -= 4;
idx = div_s64_rem(idx, 4, &offset);
offset = idx * 64 + offset * board->uart_offset;
}
return setup_port(priv, port, bar, offset, 0);
}
static int
pci_moxa_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_8250_port *port, int idx)
{
unsigned int bar = FL_GET_BASE(board->flags);
int offset;
if (board->num_ports == 4 && idx == 3)
offset = 7 * board->uart_offset;
else
offset = idx * board->uart_offset;
return setup_port(priv, port, bar, offset, 0);
}
#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
#define PCI_DEVICE_ID_OCTPRO 0x0001
#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
#define PCI_VENDOR_ID_ADVANTECH 0x13fe
#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
#define PCI_DEVICE_ID_TITAN_200I 0x8028
#define PCI_DEVICE_ID_TITAN_400I 0x8048
#define PCI_DEVICE_ID_TITAN_800I 0x8088
#define PCI_DEVICE_ID_TITAN_800EH 0xA007
#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
#define PCI_DEVICE_ID_TITAN_400EH 0xA009
#define PCI_DEVICE_ID_TITAN_100E 0xA010
#define PCI_DEVICE_ID_TITAN_200E 0xA012
#define PCI_DEVICE_ID_TITAN_400E 0xA013
#define PCI_DEVICE_ID_TITAN_800E 0xA014
#define PCI_DEVICE_ID_TITAN_200EI 0xA016
#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
#define PCI_DEVICE_ID_TITAN_200V3 0xA306
#define PCI_DEVICE_ID_TITAN_400V3 0xA310
#define PCI_DEVICE_ID_TITAN_410V3 0xA312
#define PCI_DEVICE_ID_TITAN_800V3 0xA314
#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
#define PCI_VENDOR_ID_WCH 0x4348
#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
#define PCI_VENDOR_ID_AGESTAR 0x5372
#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
#define PCIE_VENDOR_ID_WCH 0x1c00
#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
#define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
#define PCI_DEVICE_ID_MOXA_CP102E 0x1024
#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
/*
* Master list of serial port init/setup/exit quirks.
* This does not describe the general nature of the port.
* (ie, baud base, number and location of ports, etc)
*
* This list is ordered alphabetically by vendor then device.
* Specific entries must come before more generic entries.
*/
static struct pci_serial_quirk pci_serial_quirks[] = {
/*
* ADDI-DATA GmbH communication cards <[email protected]>
*/
{
.vendor = PCI_VENDOR_ID_AMCC,
.device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = addidata_apci7800_setup,
},
/*
* AFAVLAB cards - these may be called via parport_serial
* It is not clear whether this applies to all products.
*/
{
.vendor = PCI_VENDOR_ID_AFAVLAB,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = afavlab_setup,
},
/*
* HP Diva
*/
{
.vendor = PCI_VENDOR_ID_HP,
.device = PCI_DEVICE_ID_HP_DIVA,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_hp_diva_init,
.setup = pci_hp_diva_setup,
},
/*
* HPE PCI serial device
*/
{
.vendor = PCI_VENDOR_ID_HP_3PAR,
.device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_hp_diva_setup,
},
/*
* Intel
*/
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_80960_RP,
.subvendor = 0xe4bf,
.subdevice = PCI_ANY_ID,
.init = pci_inteli960ni_init,
.setup = pci_default_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_8257X_SOL,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = skip_tx_en_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82573L_SOL,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = skip_tx_en_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82573E_SOL,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = skip_tx_en_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_CE4100_UART,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = ce4100_serial_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = kt_serial_setup,
},
/*
* ITE
*/
{
.vendor = PCI_VENDOR_ID_ITE,
.device = PCI_DEVICE_ID_ITE_8872,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ite887x_init,
.setup = pci_default_setup,
.exit = pci_ite887x_exit,
},
/*
* National Instruments
*/
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PCI23216,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PCI2328,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PCI2324,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PCI2322,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PCI2324I,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PCI2322I,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PXI8420_23216,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PXI8420_2328,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PXI8420_2324,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PXI8420_2322,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PXI8422_2324,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_DEVICE_ID_NI_PXI8422_2322,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8420_init,
.setup = pci_default_setup,
.exit = pci_ni8420_exit,
},
{
.vendor = PCI_VENDOR_ID_NI,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_ni8430_init,
.setup = pci_ni8430_setup,
.exit = pci_ni8430_exit,
},
/* Quatech */
{
.vendor = PCI_VENDOR_ID_QUATECH,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_quatech_init,
.setup = pci_quatech_setup,
},
/*
* Panacom
*/
{
.vendor = PCI_VENDOR_ID_PANACOM,
.device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_plx9050_init,
.setup = pci_default_setup,
.exit = pci_plx9050_exit,
},
{
.vendor = PCI_VENDOR_ID_PANACOM,
.device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_plx9050_init,
.setup = pci_default_setup,
.exit = pci_plx9050_exit,
},
/*
* PLX
*/
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_9050,
.subvendor = PCI_SUBVENDOR_ID_EXSYS,
.subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
.init = pci_plx9050_init,
.setup = pci_default_setup,
.exit = pci_plx9050_exit,
},
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_9050,
.subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
.subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
.init = pci_plx9050_init,
.setup = pci_default_setup,
.exit = pci_plx9050_exit,
},
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_ROMULUS,
.subvendor = PCI_VENDOR_ID_PLX,
.subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
.init = pci_plx9050_init,
.setup = pci_default_setup,
.exit = pci_plx9050_exit,
},
/*
* SBS Technologies, Inc., PMC-OCTALPRO 232
*/
{
.vendor = PCI_VENDOR_ID_SBSMODULARIO,
.device = PCI_DEVICE_ID_OCTPRO,
.subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
.subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
.init = sbs_init,
.setup = sbs_setup,
.exit = sbs_exit,
},
/*
* SBS Technologies, Inc., PMC-OCTALPRO 422
*/
{
.vendor = PCI_VENDOR_ID_SBSMODULARIO,
.device = PCI_DEVICE_ID_OCTPRO,
.subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
.subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
.init = sbs_init,
.setup = sbs_setup,
.exit = sbs_exit,
},
/*
* SBS Technologies, Inc., P-Octal 232
*/
{
.vendor = PCI_VENDOR_ID_SBSMODULARIO,
.device = PCI_DEVICE_ID_OCTPRO,
.subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
.subdevice = PCI_SUBDEVICE_ID_POCTAL232,
.init = sbs_init,
.setup = sbs_setup,
.exit = sbs_exit,
},
/*
* SBS Technologies, Inc., P-Octal 422
*/
{
.vendor = PCI_VENDOR_ID_SBSMODULARIO,
.device = PCI_DEVICE_ID_OCTPRO,
.subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
.subdevice = PCI_SUBDEVICE_ID_POCTAL422,
.init = sbs_init,
.setup = sbs_setup,
.exit = sbs_exit,
},
/*
* SIIG cards - these may be called via parport_serial
*/
{
.vendor = PCI_VENDOR_ID_SIIG,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_siig_init,
.setup = pci_siig_setup,
},
/*
* Titan cards
*/
{
.vendor = PCI_VENDOR_ID_TITAN,
.device = PCI_DEVICE_ID_TITAN_400L,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = titan_400l_800l_setup,
},
{
.vendor = PCI_VENDOR_ID_TITAN,
.device = PCI_DEVICE_ID_TITAN_800L,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = titan_400l_800l_setup,
},
/*
* Timedia cards
*/
{
.vendor = PCI_VENDOR_ID_TIMEDIA,
.device = PCI_DEVICE_ID_TIMEDIA_1889,
.subvendor = PCI_VENDOR_ID_TIMEDIA,
.subdevice = PCI_ANY_ID,
.probe = pci_timedia_probe,
.init = pci_timedia_init,
.setup = pci_timedia_setup,
},
{
.vendor = PCI_VENDOR_ID_TIMEDIA,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_timedia_setup,
},
/*
* Sunix PCI serial boards
*/
{
.vendor = PCI_VENDOR_ID_SUNIX,
.device = PCI_DEVICE_ID_SUNIX_1999,
.subvendor = PCI_VENDOR_ID_SUNIX,
.subdevice = PCI_ANY_ID,
.setup = pci_sunix_setup,
},
/*
* Xircom cards
*/
{
.vendor = PCI_VENDOR_ID_XIRCOM,
.device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_xircom_init,
.setup = pci_default_setup,
},
/*
* Netmos cards - these may be called via parport_serial
*/
{
.vendor = PCI_VENDOR_ID_NETMOS,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_netmos_init,
.setup = pci_netmos_9900_setup,
},
/*
* EndRun Technologies
*/
{
.vendor = PCI_VENDOR_ID_ENDRUN,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_default_setup,
},
/*
* For Oxford Semiconductor Tornado based devices
*/
{
.vendor = PCI_VENDOR_ID_OXSEMI,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_MAINPINE,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_DIGI,
.device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
.subvendor = PCI_SUBVENDOR_ID_IBM,
.subdevice = PCI_ANY_ID,
.init = pci_oxsemi_tornado_init,
.setup = pci_oxsemi_tornado_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8811,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8812,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8813,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8814,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = 0x10DB,
.device = 0x8027,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = 0x10DB,
.device = 0x8028,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = 0x10DB,
.device = 0x8029,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = 0x10DB,
.device = 0x800C,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
{
.vendor = 0x10DB,
.device = 0x800D,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_eg20t_init,
.setup = pci_default_setup,
},
/*
* Cronyx Omega PCI (PLX-chip based)
*/
{
.vendor = PCI_VENDOR_ID_PLX,
.device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_omegapci_setup,
},
/* WCH CH353 1S1P card (16550 clone) */
{
.vendor = PCI_VENDOR_ID_WCH,
.device = PCI_DEVICE_ID_WCH_CH353_1S1P,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch353_setup,
},
/* WCH CH353 2S1P card (16550 clone) */
{
.vendor = PCI_VENDOR_ID_WCH,
.device = PCI_DEVICE_ID_WCH_CH353_2S1P,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch353_setup,
},
/* WCH CH353 4S card (16550 clone) */
{
.vendor = PCI_VENDOR_ID_WCH,
.device = PCI_DEVICE_ID_WCH_CH353_4S,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch353_setup,
},
/* WCH CH353 2S1PF card (16550 clone) */
{
.vendor = PCI_VENDOR_ID_WCH,
.device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch353_setup,
},
/* WCH CH352 2S card (16550 clone) */
{
.vendor = PCI_VENDOR_ID_WCH,
.device = PCI_DEVICE_ID_WCH_CH352_2S,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch353_setup,
},
/* WCH CH355 4S card (16550 clone) */
{
.vendor = PCI_VENDOR_ID_WCH,
.device = PCI_DEVICE_ID_WCH_CH355_4S,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch355_setup,
},
/* WCH CH382 2S card (16850 clone) */
{
.vendor = PCIE_VENDOR_ID_WCH,
.device = PCIE_DEVICE_ID_WCH_CH382_2S,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch38x_setup,
},
/* WCH CH382 2S1P card (16850 clone) */
{
.vendor = PCIE_VENDOR_ID_WCH,
.device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch38x_setup,
},
/* WCH CH384 4S card (16850 clone) */
{
.vendor = PCIE_VENDOR_ID_WCH,
.device = PCIE_DEVICE_ID_WCH_CH384_4S,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_wch_ch38x_setup,
},
/* WCH CH384 8S card (16850 clone) */
{
.vendor = PCIE_VENDOR_ID_WCH,
.device = PCIE_DEVICE_ID_WCH_CH384_8S,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.init = pci_wch_ch38x_init,
.exit = pci_wch_ch38x_exit,
.setup = pci_wch_ch38x_setup,
},
/*
* Broadcom TruManage (NetXtreme)
*/
{
.vendor = PCI_VENDOR_ID_BROADCOM,
.device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_brcm_trumanage_setup,
},
{
.vendor = 0x1c29,
.device = 0x1104,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_fintek_setup,
.init = pci_fintek_init,
},
{
.vendor = 0x1c29,
.device = 0x1108,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_fintek_setup,
.init = pci_fintek_init,
},
{
.vendor = 0x1c29,
.device = 0x1112,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_fintek_setup,
.init = pci_fintek_init,
},
/*
* MOXA
*/
{
.vendor = PCI_VENDOR_ID_MOXA,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_moxa_setup,
},
{
.vendor = 0x1c29,
.device = 0x1204,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_fintek_f815xxa_setup,
.init = pci_fintek_f815xxa_init,
},
{
.vendor = 0x1c29,
.device = 0x1208,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_fintek_f815xxa_setup,
.init = pci_fintek_f815xxa_init,
},
{
.vendor = 0x1c29,
.device = 0x1212,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_fintek_f815xxa_setup,
.init = pci_fintek_f815xxa_init,
},
/*
* Default "match everything" terminator entry
*/
{
.vendor = PCI_ANY_ID,
.device = PCI_ANY_ID,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
.setup = pci_default_setup,
}
};
static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
{
return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
}
static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
{
struct pci_serial_quirk *quirk;
for (quirk = pci_serial_quirks; ; quirk++)
if (quirk_id_matches(quirk->vendor, dev->vendor) &&
quirk_id_matches(quirk->device, dev->device) &&
quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
quirk_id_matches(quirk->subdevice, dev->subsystem_device))
break;
return quirk;
}
/*
* This is the configuration table for all of the PCI serial boards
* which we support. It is directly indexed by the pci_board_num_t enum
* value, which is encoded in the pci_device_id PCI probe table's
* driver_data member.
*
* The makeup of these names are:
* pbn_bn{_bt}_n_baud{_offsetinhex}
*
* bn = PCI BAR number
* bt = Index using PCI BARs
* n = number of serial ports
* baud = baud rate
* offsetinhex = offset for each sequential port (in hex)
*
* This table is sorted by (in order): bn, bt, baud, offsetindex, n.
*
* Please note: in theory if n = 1, _bt infix should make no difference.
* ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
*/
enum pci_board_num_t {
pbn_default = 0,
pbn_b0_1_115200,
pbn_b0_2_115200,
pbn_b0_4_115200,
pbn_b0_5_115200,
pbn_b0_8_115200,
pbn_b0_1_921600,
pbn_b0_2_921600,
pbn_b0_4_921600,
pbn_b0_2_1130000,
pbn_b0_4_1152000,
pbn_b0_4_1250000,
pbn_b0_2_1843200,
pbn_b0_4_1843200,
pbn_b0_1_15625000,
pbn_b0_bt_1_115200,
pbn_b0_bt_2_115200,
pbn_b0_bt_4_115200,
pbn_b0_bt_8_115200,
pbn_b0_bt_1_460800,
pbn_b0_bt_2_460800,
pbn_b0_bt_4_460800,
pbn_b0_bt_1_921600,
pbn_b0_bt_2_921600,
pbn_b0_bt_4_921600,
pbn_b0_bt_8_921600,
pbn_b1_1_115200,
pbn_b1_2_115200,
pbn_b1_4_115200,
pbn_b1_8_115200,
pbn_b1_16_115200,
pbn_b1_1_921600,
pbn_b1_2_921600,
pbn_b1_4_921600,
pbn_b1_8_921600,
pbn_b1_2_1250000,
pbn_b1_bt_1_115200,
pbn_b1_bt_2_115200,
pbn_b1_bt_4_115200,
pbn_b1_bt_2_921600,
pbn_b1_1_1382400,
pbn_b1_2_1382400,
pbn_b1_4_1382400,
pbn_b1_8_1382400,
pbn_b2_1_115200,
pbn_b2_2_115200,
pbn_b2_4_115200,
pbn_b2_8_115200,
pbn_b2_1_460800,
pbn_b2_4_460800,
pbn_b2_8_460800,
pbn_b2_16_460800,
pbn_b2_1_921600,
pbn_b2_4_921600,
pbn_b2_8_921600,
pbn_b2_8_1152000,
pbn_b2_bt_1_115200,
pbn_b2_bt_2_115200,
pbn_b2_bt_4_115200,
pbn_b2_bt_2_921600,
pbn_b2_bt_4_921600,
pbn_b3_2_115200,
pbn_b3_4_115200,
pbn_b3_8_115200,
pbn_b4_bt_2_921600,
pbn_b4_bt_4_921600,
pbn_b4_bt_8_921600,
/*
* Board-specific versions.
*/
pbn_panacom,
pbn_panacom2,
pbn_panacom4,
pbn_plx_romulus,
pbn_oxsemi,
pbn_oxsemi_1_15625000,
pbn_oxsemi_2_15625000,
pbn_oxsemi_4_15625000,
pbn_oxsemi_8_15625000,
pbn_intel_i960,
pbn_sgi_ioc3,
pbn_computone_4,
pbn_computone_6,
pbn_computone_8,
pbn_sbsxrsio,
pbn_pasemi_1682M,
pbn_ni8430_2,
pbn_ni8430_4,
pbn_ni8430_8,
pbn_ni8430_16,
pbn_ADDIDATA_PCIe_1_3906250,
pbn_ADDIDATA_PCIe_2_3906250,
pbn_ADDIDATA_PCIe_4_3906250,
pbn_ADDIDATA_PCIe_8_3906250,
pbn_ce4100_1_115200,
pbn_omegapci,
pbn_NETMOS9900_2s_115200,
pbn_brcm_trumanage,
pbn_fintek_4,
pbn_fintek_8,
pbn_fintek_12,
pbn_fintek_F81504A,
pbn_fintek_F81508A,
pbn_fintek_F81512A,
pbn_wch382_2,
pbn_wch384_4,
pbn_wch384_8,
pbn_sunix_pci_1s,
pbn_sunix_pci_2s,
pbn_sunix_pci_4s,
pbn_sunix_pci_8s,
pbn_sunix_pci_16s,
pbn_titan_1_4000000,
pbn_titan_2_4000000,
pbn_titan_4_4000000,
pbn_titan_8_4000000,
pbn_moxa8250_2p,
pbn_moxa8250_4p,
pbn_moxa8250_8p,
};
/*
* uart_offset - the space between channels
* reg_shift - describes how the UART registers are mapped
* to PCI memory by the card.
* For example IER register on SBS, Inc. PMC-OctPro is located at
* offset 0x10 from the UART base, while UART_IER is defined as 1
* in include/linux/serial_reg.h,
* see first lines of serial_in() and serial_out() in 8250.c
*/
static struct pciserial_board pci_boards[] = {
[pbn_default] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_1_115200] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_2_115200] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_4_115200] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_5_115200] = {
.flags = FL_BASE0,
.num_ports = 5,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_8_115200] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_1_921600] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b0_2_921600] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b0_4_921600] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b0_2_1130000] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 1130000,
.uart_offset = 8,
},
[pbn_b0_4_1152000] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 1152000,
.uart_offset = 8,
},
[pbn_b0_4_1250000] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 1250000,
.uart_offset = 8,
},
[pbn_b0_2_1843200] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 1843200,
.uart_offset = 8,
},
[pbn_b0_4_1843200] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 1843200,
.uart_offset = 8,
},
[pbn_b0_1_15625000] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 15625000,
.uart_offset = 8,
},
[pbn_b0_bt_1_115200] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_bt_2_115200] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_bt_4_115200] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_bt_8_115200] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b0_bt_1_460800] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 1,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b0_bt_2_460800] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b0_bt_4_460800] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b0_bt_1_921600] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 1,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b0_bt_2_921600] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b0_bt_4_921600] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b0_bt_8_921600] = {
.flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b1_1_115200] = {
.flags = FL_BASE1,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_2_115200] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_4_115200] = {
.flags = FL_BASE1,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_8_115200] = {
.flags = FL_BASE1,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_16_115200] = {
.flags = FL_BASE1,
.num_ports = 16,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_1_921600] = {
.flags = FL_BASE1,
.num_ports = 1,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b1_2_921600] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b1_4_921600] = {
.flags = FL_BASE1,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b1_8_921600] = {
.flags = FL_BASE1,
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b1_2_1250000] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 1250000,
.uart_offset = 8,
},
[pbn_b1_bt_1_115200] = {
.flags = FL_BASE1|FL_BASE_BARS,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_bt_2_115200] = {
.flags = FL_BASE1|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_bt_4_115200] = {
.flags = FL_BASE1|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b1_bt_2_921600] = {
.flags = FL_BASE1|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b1_1_1382400] = {
.flags = FL_BASE1,
.num_ports = 1,
.base_baud = 1382400,
.uart_offset = 8,
},
[pbn_b1_2_1382400] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 1382400,
.uart_offset = 8,
},
[pbn_b1_4_1382400] = {
.flags = FL_BASE1,
.num_ports = 4,
.base_baud = 1382400,
.uart_offset = 8,
},
[pbn_b1_8_1382400] = {
.flags = FL_BASE1,
.num_ports = 8,
.base_baud = 1382400,
.uart_offset = 8,
},
[pbn_b2_1_115200] = {
.flags = FL_BASE2,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_2_115200] = {
.flags = FL_BASE2,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_4_115200] = {
.flags = FL_BASE2,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_8_115200] = {
.flags = FL_BASE2,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_1_460800] = {
.flags = FL_BASE2,
.num_ports = 1,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b2_4_460800] = {
.flags = FL_BASE2,
.num_ports = 4,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b2_8_460800] = {
.flags = FL_BASE2,
.num_ports = 8,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b2_16_460800] = {
.flags = FL_BASE2,
.num_ports = 16,
.base_baud = 460800,
.uart_offset = 8,
},
[pbn_b2_1_921600] = {
.flags = FL_BASE2,
.num_ports = 1,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b2_4_921600] = {
.flags = FL_BASE2,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b2_8_921600] = {
.flags = FL_BASE2,
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b2_8_1152000] = {
.flags = FL_BASE2,
.num_ports = 8,
.base_baud = 1152000,
.uart_offset = 8,
},
[pbn_b2_bt_1_115200] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 1,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_bt_2_115200] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_bt_4_115200] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b2_bt_2_921600] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b2_bt_4_921600] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b3_2_115200] = {
.flags = FL_BASE3,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b3_4_115200] = {
.flags = FL_BASE3,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b3_8_115200] = {
.flags = FL_BASE3,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_b4_bt_2_921600] = {
.flags = FL_BASE4,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b4_bt_4_921600] = {
.flags = FL_BASE4,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8,
},
[pbn_b4_bt_8_921600] = {
.flags = FL_BASE4,
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 8,
},
/*
* Entries following this are board-specific.
*/
/*
* Panacom - IOMEM
*/
[pbn_panacom] = {
.flags = FL_BASE2,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 0x400,
.reg_shift = 7,
},
[pbn_panacom2] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 0x400,
.reg_shift = 7,
},
[pbn_panacom4] = {
.flags = FL_BASE2|FL_BASE_BARS,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 0x400,
.reg_shift = 7,
},
/* I think this entry is broken - the first_offset looks wrong --rmk */
[pbn_plx_romulus] = {
.flags = FL_BASE2,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 8 << 2,
.reg_shift = 2,
.first_offset = 0x03,
},
/*
* This board uses the size of PCI Base region 0 to
* signal now many ports are available
*/
[pbn_oxsemi] = {
.flags = FL_BASE0|FL_REGION_SZ_CAP,
.num_ports = 32,
.base_baud = 115200,
.uart_offset = 8,
},
[pbn_oxsemi_1_15625000] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 15625000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_oxsemi_2_15625000] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 15625000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_oxsemi_4_15625000] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 15625000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_oxsemi_8_15625000] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 15625000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
/*
* EKF addition for i960 Boards form EKF with serial port.
* Max 256 ports.
*/
[pbn_intel_i960] = {
.flags = FL_BASE0,
.num_ports = 32,
.base_baud = 921600,
.uart_offset = 8 << 2,
.reg_shift = 2,
.first_offset = 0x10000,
},
[pbn_sgi_ioc3] = {
.flags = FL_BASE0|FL_NOIRQ,
.num_ports = 1,
.base_baud = 458333,
.uart_offset = 8,
.reg_shift = 0,
.first_offset = 0x20178,
},
/*
* Computone - uses IOMEM.
*/
[pbn_computone_4] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 0x40,
.reg_shift = 2,
.first_offset = 0x200,
},
[pbn_computone_6] = {
.flags = FL_BASE0,
.num_ports = 6,
.base_baud = 921600,
.uart_offset = 0x40,
.reg_shift = 2,
.first_offset = 0x200,
},
[pbn_computone_8] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 0x40,
.reg_shift = 2,
.first_offset = 0x200,
},
[pbn_sbsxrsio] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 460800,
.uart_offset = 256,
.reg_shift = 4,
},
/*
* PA Semi PWRficient PA6T-1682M on-chip UART
*/
[pbn_pasemi_1682M] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 8333333,
},
/*
* National Instruments 843x
*/
[pbn_ni8430_16] = {
.flags = FL_BASE0,
.num_ports = 16,
.base_baud = 3686400,
.uart_offset = 0x10,
.first_offset = 0x800,
},
[pbn_ni8430_8] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 3686400,
.uart_offset = 0x10,
.first_offset = 0x800,
},
[pbn_ni8430_4] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 3686400,
.uart_offset = 0x10,
.first_offset = 0x800,
},
[pbn_ni8430_2] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 3686400,
.uart_offset = 0x10,
.first_offset = 0x800,
},
/*
* ADDI-DATA GmbH PCI-Express communication cards <[email protected]>
*/
[pbn_ADDIDATA_PCIe_1_3906250] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 3906250,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_ADDIDATA_PCIe_2_3906250] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 3906250,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_ADDIDATA_PCIe_4_3906250] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 3906250,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_ADDIDATA_PCIe_8_3906250] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 3906250,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_ce4100_1_115200] = {
.flags = FL_BASE_BARS,
.num_ports = 2,
.base_baud = 921600,
.reg_shift = 2,
},
[pbn_omegapci] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 0x200,
},
[pbn_NETMOS9900_2s_115200] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 115200,
},
[pbn_brcm_trumanage] = {
.flags = FL_BASE0,
.num_ports = 1,
.reg_shift = 2,
.base_baud = 115200,
},
[pbn_fintek_4] = {
.num_ports = 4,
.uart_offset = 8,
.base_baud = 115200,
.first_offset = 0x40,
},
[pbn_fintek_8] = {
.num_ports = 8,
.uart_offset = 8,
.base_baud = 115200,
.first_offset = 0x40,
},
[pbn_fintek_12] = {
.num_ports = 12,
.uart_offset = 8,
.base_baud = 115200,
.first_offset = 0x40,
},
[pbn_fintek_F81504A] = {
.num_ports = 4,
.uart_offset = 8,
.base_baud = 115200,
},
[pbn_fintek_F81508A] = {
.num_ports = 8,
.uart_offset = 8,
.base_baud = 115200,
},
[pbn_fintek_F81512A] = {
.num_ports = 12,
.uart_offset = 8,
.base_baud = 115200,
},
[pbn_wch382_2] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 115200,
.uart_offset = 8,
.first_offset = 0xC0,
},
[pbn_wch384_4] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 115200,
.uart_offset = 8,
.first_offset = 0xC0,
},
[pbn_wch384_8] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 115200,
.uart_offset = 8,
.first_offset = 0x00,
},
[pbn_sunix_pci_1s] = {
.num_ports = 1,
.base_baud = 921600,
.uart_offset = 0x8,
},
[pbn_sunix_pci_2s] = {
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 0x8,
},
[pbn_sunix_pci_4s] = {
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 0x8,
},
[pbn_sunix_pci_8s] = {
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 0x8,
},
[pbn_sunix_pci_16s] = {
.num_ports = 16,
.base_baud = 921600,
.uart_offset = 0x8,
},
[pbn_titan_1_4000000] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 4000000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_titan_2_4000000] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 4000000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_titan_4_4000000] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 4000000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_titan_8_4000000] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 4000000,
.uart_offset = 0x200,
.first_offset = 0x1000,
},
[pbn_moxa8250_2p] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 921600,
.uart_offset = 0x200,
},
[pbn_moxa8250_4p] = {
.flags = FL_BASE1,
.num_ports = 4,
.base_baud = 921600,
.uart_offset = 0x200,
},
[pbn_moxa8250_8p] = {
.flags = FL_BASE1,
.num_ports = 8,
.base_baud = 921600,
.uart_offset = 0x200,
},
};
#define REPORT_CONFIG(option) \
(IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
#define REPORT_8250_CONFIG(option) \
(IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
static const struct pci_device_id blacklist[] = {
/* softmodems */
{ PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
{ PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
{ PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
/* multi-io cards handled by parport_serial */
/* WCH CH353 2S1P */
{ PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
/* WCH CH353 1S1P */
{ PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
/* WCH CH382 2S1P */
{ PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
/* Intel platforms with MID UART */
{ PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
{ PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
{ PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
{ PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
{ PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
{ PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
/* Intel platforms with DesignWare UART */
{ PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
{ PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
/* Exar devices */
{ PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
{ PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
/* Pericom devices */
{ PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
{ PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
/* End of the black list */
{ }
};
static int serial_pci_is_class_communication(struct pci_dev *dev)
{
/*
* If it is not a communications device or the programming
* interface is greater than 6, give up.
*/
if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
(dev->class & 0xff) > 6)
return -ENODEV;
return 0;
}
/*
* Given a complete unknown PCI device, try to use some heuristics to
* guess what the configuration might be, based on the pitiful PCI
* serial specs. Returns 0 on success, -ENODEV on failure.
*/
static int
serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
{
int num_iomem, num_port, first_port = -1, i;
int rc;
rc = serial_pci_is_class_communication(dev);
if (rc)
return rc;
/*
* Should we try to make guesses for multiport serial devices later?
*/
if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
return -ENODEV;
num_iomem = num_port = 0;
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
num_port++;
if (first_port == -1)
first_port = i;
}
if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
num_iomem++;
}
/*
* If there is 1 or 0 iomem regions, and exactly one port,
* use it. We guess the number of ports based on the IO
* region size.
*/
if (num_iomem <= 1 && num_port == 1) {
board->flags = first_port;
board->num_ports = pci_resource_len(dev, first_port) / 8;
return 0;
}
/*
* Now guess if we've got a board which indexes by BARs.
* Each IO BAR should be 8 bytes, and they should follow
* consecutively.
*/
first_port = -1;
num_port = 0;
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
pci_resource_len(dev, i) == 8 &&
(first_port == -1 || (first_port + num_port) == i)) {
num_port++;
if (first_port == -1)
first_port = i;
}
}
if (num_port > 1) {
board->flags = first_port | FL_BASE_BARS;
board->num_ports = num_port;
return 0;
}
return -ENODEV;
}
static inline int
serial_pci_matches(const struct pciserial_board *board,
const struct pciserial_board *guessed)
{
return
board->num_ports == guessed->num_ports &&
board->base_baud == guessed->base_baud &&
board->uart_offset == guessed->uart_offset &&
board->reg_shift == guessed->reg_shift &&
board->first_offset == guessed->first_offset;
}
struct serial_private *
pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
{
struct uart_8250_port uart;
struct serial_private *priv;
struct pci_serial_quirk *quirk;
int rc, nr_ports, i;
nr_ports = board->num_ports;
/*
* Find an init and setup quirks.
*/
quirk = find_quirk(dev);
/*
* Run the new-style initialization function.
* The initialization function returns:
* <0 - error
* 0 - use board->num_ports
* >0 - number of ports
*/
if (quirk->init) {
rc = quirk->init(dev);
if (rc < 0) {
priv = ERR_PTR(rc);
goto err_out;
}
if (rc)
nr_ports = rc;
}
priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
if (!priv) {
priv = ERR_PTR(-ENOMEM);
goto err_deinit;
}
priv->dev = dev;
priv->quirk = quirk;
memset(&uart, 0, sizeof(uart));
uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
uart.port.uartclk = board->base_baud * 16;
if (board->flags & FL_NOIRQ) {
uart.port.irq = 0;
} else {
if (pci_match_id(pci_use_msi, dev)) {
pci_dbg(dev, "Using MSI(-X) interrupts\n");
pci_set_master(dev);
uart.port.flags &= ~UPF_SHARE_IRQ;
rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
} else {
pci_dbg(dev, "Using legacy interrupts\n");
rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
}
if (rc < 0) {
kfree(priv);
priv = ERR_PTR(rc);
goto err_deinit;
}
uart.port.irq = pci_irq_vector(dev, 0);
}
uart.port.dev = &dev->dev;
for (i = 0; i < nr_ports; i++) {
if (quirk->setup(priv, board, &uart, i))
break;
pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
uart.port.iobase, uart.port.irq, uart.port.iotype);
priv->line[i] = serial8250_register_8250_port(&uart);
if (priv->line[i] < 0) {
pci_err(dev,
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
uart.port.iobase, uart.port.irq,
uart.port.iotype, priv->line[i]);
break;
}
}
priv->nr = i;
priv->board = board;
return priv;
err_deinit:
if (quirk->exit)
quirk->exit(dev);
err_out:
return priv;
}
EXPORT_SYMBOL_GPL(pciserial_init_ports);
static void pciserial_detach_ports(struct serial_private *priv)
{
struct pci_serial_quirk *quirk;
int i;
for (i = 0; i < priv->nr; i++)
serial8250_unregister_port(priv->line[i]);
/*
* Find the exit quirks.
*/
quirk = find_quirk(priv->dev);
if (quirk->exit)
quirk->exit(priv->dev);
}
void pciserial_remove_ports(struct serial_private *priv)
{
pciserial_detach_ports(priv);
kfree(priv);
}
EXPORT_SYMBOL_GPL(pciserial_remove_ports);
void pciserial_suspend_ports(struct serial_private *priv)
{
int i;
for (i = 0; i < priv->nr; i++)
if (priv->line[i] >= 0)
serial8250_suspend_port(priv->line[i]);
/*
* Ensure that every init quirk is properly torn down
*/
if (priv->quirk->exit)
priv->quirk->exit(priv->dev);
}
EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
void pciserial_resume_ports(struct serial_private *priv)
{
int i;
/*
* Ensure that the board is correctly configured.
*/
if (priv->quirk->init)
priv->quirk->init(priv->dev);
for (i = 0; i < priv->nr; i++)
if (priv->line[i] >= 0)
serial8250_resume_port(priv->line[i]);
}
EXPORT_SYMBOL_GPL(pciserial_resume_ports);
/*
* Probe one serial board. Unfortunately, there is no rhyme nor reason
* to the arrangement of serial ports on a PCI card.
*/
static int
pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct pci_serial_quirk *quirk;
struct serial_private *priv;
const struct pciserial_board *board;
const struct pci_device_id *exclude;
struct pciserial_board tmp;
int rc;
quirk = find_quirk(dev);
if (quirk->probe) {
rc = quirk->probe(dev);
if (rc)
return rc;
}
if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
return -EINVAL;
}
board = &pci_boards[ent->driver_data];
exclude = pci_match_id(blacklist, dev);
if (exclude) {
if (exclude->driver_data)
pci_warn(dev, "ignoring port, enable %s to handle\n",
(const char *)exclude->driver_data);
return -ENODEV;
}
rc = pcim_enable_device(dev);
pci_save_state(dev);
if (rc)
return rc;
if (ent->driver_data == pbn_default) {
/*
* Use a copy of the pci_board entry for this;
* avoid changing entries in the table.
*/
memcpy(&tmp, board, sizeof(struct pciserial_board));
board = &tmp;
/*
* We matched one of our class entries. Try to
* determine the parameters of this board.
*/
rc = serial_pci_guess_board(dev, &tmp);
if (rc)
return rc;
} else {
/*
* We matched an explicit entry. If we are able to
* detect this boards settings with our heuristic,
* then we no longer need this entry.
*/
memcpy(&tmp, &pci_boards[pbn_default],
sizeof(struct pciserial_board));
rc = serial_pci_guess_board(dev, &tmp);
if (rc == 0 && serial_pci_matches(board, &tmp))
moan_device("Redundant entry in serial pci_table.",
dev);
}
priv = pciserial_init_ports(dev, board);
if (IS_ERR(priv))
return PTR_ERR(priv);
pci_set_drvdata(dev, priv);
return 0;
}
static void pciserial_remove_one(struct pci_dev *dev)
{
struct serial_private *priv = pci_get_drvdata(dev);
pciserial_remove_ports(priv);
}
#ifdef CONFIG_PM_SLEEP
static int pciserial_suspend_one(struct device *dev)
{
struct serial_private *priv = dev_get_drvdata(dev);
if (priv)
pciserial_suspend_ports(priv);
return 0;
}
static int pciserial_resume_one(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct serial_private *priv = pci_get_drvdata(pdev);
int err;
if (priv) {
/*
* The device may have been disabled. Re-enable it.
*/
err = pci_enable_device(pdev);
/* FIXME: We cannot simply error out here */
if (err)
pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
pciserial_resume_ports(priv);
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
pciserial_resume_one);
static const struct pci_device_id serial_pci_tbl[] = {
{ PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
/* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
{ PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
pbn_b2_8_921600 },
/* Advantech also use 0x3618 and 0xf618 */
{ PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
pbn_b1_8_1382400 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
pbn_b1_4_1382400 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
pbn_b1_2_1382400 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
pbn_b1_8_1382400 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
pbn_b1_4_1382400 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
pbn_b1_2_1382400 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
pbn_b1_8_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
pbn_b1_8_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
pbn_b1_4_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
pbn_b1_4_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
pbn_b1_2_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
pbn_b1_8_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
pbn_b1_8_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
pbn_b1_4_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
pbn_b1_2_1250000 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
pbn_b0_2_1843200 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
pbn_b0_4_1843200 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_VENDOR_ID_AFAVLAB,
PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
pbn_b0_4_1152000 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_1_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_460800 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_115200 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_115200 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_921600 },
/*
* VScom SPCOM800, from [email protected]
*/
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_921600 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_4_921600 },
/* Unknown card - subdevice 0x1584 */
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_VENDOR_ID_PLX,
PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
pbn_b2_4_115200 },
/* Unknown card - subdevice 0x1588 */
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_VENDOR_ID_PLX,
PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
pbn_b2_8_115200 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_KEYSPAN,
PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
pbn_panacom },
{ PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_panacom4 },
{ PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_panacom2 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
PCI_VENDOR_ID_ESDGMBH,
PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
pbn_b2_4_115200 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
pbn_b2_4_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
pbn_b2_8_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
pbn_b2_16_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
pbn_b2_16_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIRAS,
PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
pbn_b2_4_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIRAS,
PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
pbn_b2_8_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_EXSYS,
PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
pbn_b2_4_115200 },
/*
* Megawolf Romulus PCI Serial Card, from Mike Hudson
* ([email protected])
*/
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
0x10b5, 0x106a, 0, 0,
pbn_plx_romulus },
/*
* Quatech cards. These actually have configurable clocks but for
* now we just use the default.
*
* 100 series are RS232, 200 series RS422,
*/
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_4_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_4_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_8_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_8_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_4_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_4_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_4_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_4_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_115200 },
{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_8_115200 },
{ PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
0, 0,
pbn_b0_4_1152000 },
{ PCI_VENDOR_ID_OXSEMI, 0x9505,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
/*
* The below card is a little controversial since it is the
* subject of a PCI vendor/device ID clash. (See
* www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
* For now just used the hex ID 0x950a.
*/
{ PCI_VENDOR_ID_OXSEMI, 0x950a,
PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
0, 0, pbn_b0_2_115200 },
{ PCI_VENDOR_ID_OXSEMI, 0x950a,
PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
0, 0, pbn_b0_2_115200 },
{ PCI_VENDOR_ID_OXSEMI, 0x950a,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_2_1130000 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
pbn_b0_1_921600 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_115200 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_1152000 },
/*
* Oxford Semiconductor Inc. Tornado PCI express device range.
*/
{ PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_2_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_2_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_4_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_4_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_8_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_8_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_15625000 },
/*
* Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
*/
{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
pbn_oxsemi_1_15625000 },
{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
pbn_oxsemi_2_15625000 },
{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
pbn_oxsemi_4_15625000 },
{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
pbn_oxsemi_8_15625000 },
/*
* Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
*/
{ PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
pbn_oxsemi_2_15625000 },
/*
* EndRun Technologies. PCI express device range.
* EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
*/
{ PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_2_15625000 },
/*
* SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
* from [email protected]
*/
{ PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
pbn_sbsxrsio },
{ PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
pbn_sbsxrsio },
{ PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
pbn_sbsxrsio },
{ PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
pbn_sbsxrsio },
/*
* Digitan DS560-558, from [email protected]
*/
{ PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_1_115200 },
/*
* Titan Electronic cards
* The 400L and 800L have a custom setup quirk.
*/
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_2_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_1_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_2_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_8_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b4_bt_2_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b4_bt_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b4_bt_8_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_titan_1_4000000 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_titan_2_4000000 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_titan_4_4000000 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_titan_8_4000000 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_titan_2_4000000 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_titan_2_4000000 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_460800 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_460800 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_460800 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_4_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_8_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_8_921600 },
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_8_921600 },
/*
* Computone devices submitted by Doug McNash [email protected]
*/
{ PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
0, 0, pbn_computone_4 },
{ PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
0, 0, pbn_computone_8 },
{ PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
0, 0, pbn_computone_6 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi },
{ PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
pbn_b0_bt_1_921600 },
/*
* Sunix PCI serial boards
*/
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
pbn_sunix_pci_1s },
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
pbn_sunix_pci_2s },
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
pbn_sunix_pci_4s },
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
pbn_sunix_pci_4s },
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
pbn_sunix_pci_8s },
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
pbn_sunix_pci_8s },
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
pbn_sunix_pci_16s },
/*
* AFAVLAB serial card, from Harald Welte <[email protected]>
*/
{ PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_8_115200 },
{ PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_8_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_4_460800 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_4_460800 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_460800 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_460800 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_460800 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_1_115200 },
{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_1_460800 },
/*
* Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
* Cards are identified by their subsystem vendor IDs, which
* (in hex) match the model number.
*
* Note that JC140x are RS422/485 cards which require ox950
* ACR = 0x10, and as such are not currently fully supported.
*/
{ PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
0x1204, 0x0004, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
0x1208, 0x0004, 0, 0,
pbn_b0_4_921600 },
/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
0x1402, 0x0002, 0, 0,
pbn_b0_2_921600 }, */
/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
0x1404, 0x0004, 0, 0,
pbn_b0_4_921600 }, */
{ PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
0x1208, 0x0004, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
0x1204, 0x0004, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
0x1208, 0x0004, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
0x1208, 0x0004, 0, 0,
pbn_b0_4_921600 },
/*
* Dell Remote Access Card 4 - [email protected]
*/
{ PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_1_1382400 },
/*
* Dell Remote Access Card III - [email protected]
*/
{ PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_1_1382400 },
/*
* RAStel 2 port modem, [email protected]
*/
{ PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_115200 },
/*
* EKF addition for i960 Boards form EKF with serial port
*/
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
0xE4BF, PCI_ANY_ID, 0, 0,
pbn_intel_i960 },
/*
* Xircom Cardbus/Ethernet combos
*/
{ PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_115200 },
/*
* Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
*/
{ PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_115200 },
/*
* Untested PCI modems, sent in from various folks...
*/
/*
* Elsa Model 56K PCI Modem, from Andreas Rath <[email protected]>
*/
{ PCI_VENDOR_ID_ROCKWELL, 0x1004,
0x1048, 0x1500, 0, 0,
pbn_b1_1_115200 },
{ PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
0xFF00, 0, 0, 0,
pbn_sgi_ioc3 },
/*
* HP Diva card
*/
{ PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
pbn_b1_1_115200 },
{ PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_5_115200 },
{ PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_1_115200 },
/* HPE PCI serial device */
{ PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_1_115200 },
{ PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b3_2_115200 },
{ PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b3_4_115200 },
{ PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b3_8_115200 },
/*
* Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
*/
{ PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_115200 },
/*
* ITE
*/
{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b1_bt_1_115200 },
/*
* IntaShield IS-200
*/
{ PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
pbn_b2_2_115200 },
/*
* IntaShield IS-400
*/
{ PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
pbn_b2_4_115200 },
/* Brainboxes Devices */
/*
* Brainboxes UC-101
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-235/246
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_1_115200 },
/*
* Brainboxes UC-257
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0861,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-260/271/701/756
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0D21,
PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
pbn_b2_4_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0E34,
PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
pbn_b2_4_115200 },
/*
* Brainboxes UC-268
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0841,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes UC-275/279
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0881,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_8_115200 },
/*
* Brainboxes UC-302
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x08E1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-310
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x08C1,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-313
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x08A3,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-320/324
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0A61,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_1_115200 },
/*
* Brainboxes UC-346
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0B02,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes UC-357
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0A81,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x0A83,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_2_115200 },
/*
* Brainboxes UC-368
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0C41,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes UC-420/431
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x0921,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b2_4_115200 },
/*
* Brainboxes PX-101
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4005,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4019,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_2_15625000 },
/*
* Brainboxes PX-235/246
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4004,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4016,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_1_15625000 },
/*
* Brainboxes PX-203/PX-257
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4006,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_2_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4015,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-260/PX-701
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x400A,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-310
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x400E,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_2_15625000 },
/*
* Brainboxes PX-313
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x400C,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_2_15625000 },
/*
* Brainboxes PX-320/324/PX-376/PX-387
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x400B,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_1_15625000 },
/*
* Brainboxes PX-335/346
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x400F,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-368
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4010,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-420
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4000,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_4_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4011,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_4_15625000 },
/*
* Brainboxes PX-803
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4009,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x401E,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_1_15625000 },
/*
* Brainboxes PX-846
*/
{ PCI_VENDOR_ID_INTASHIELD, 0x4008,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_INTASHIELD, 0x4017,
PCI_ANY_ID, PCI_ANY_ID,
0, 0,
pbn_oxsemi_1_15625000 },
/*
* Perle PCI-RAS cards
*/
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
0, 0, pbn_b2_4_921600 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
0, 0, pbn_b2_8_921600 },
/*
* Mainpine series cards: Fairly standard layout but fools
* parts of the autodetect in some cases and uses otherwise
* unmatched communications subclasses in the PCI Express case
*/
{ /* RockForceDUO */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0200,
0, 0, pbn_b0_2_115200 },
{ /* RockForceQUATRO */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0300,
0, 0, pbn_b0_4_115200 },
{ /* RockForceDUO+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0400,
0, 0, pbn_b0_2_115200 },
{ /* RockForceQUATRO+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0500,
0, 0, pbn_b0_4_115200 },
{ /* RockForce+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0600,
0, 0, pbn_b0_2_115200 },
{ /* RockForce+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0700,
0, 0, pbn_b0_4_115200 },
{ /* RockForceOCTO+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0800,
0, 0, pbn_b0_8_115200 },
{ /* RockForceDUO+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0C00,
0, 0, pbn_b0_2_115200 },
{ /* RockForceQUARTRO+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x0D00,
0, 0, pbn_b0_4_115200 },
{ /* RockForceOCTO+ */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x1D00,
0, 0, pbn_b0_8_115200 },
{ /* RockForceD1 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2000,
0, 0, pbn_b0_1_115200 },
{ /* RockForceF1 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2100,
0, 0, pbn_b0_1_115200 },
{ /* RockForceD2 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2200,
0, 0, pbn_b0_2_115200 },
{ /* RockForceF2 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2300,
0, 0, pbn_b0_2_115200 },
{ /* RockForceD4 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2400,
0, 0, pbn_b0_4_115200 },
{ /* RockForceF4 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2500,
0, 0, pbn_b0_4_115200 },
{ /* RockForceD8 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2600,
0, 0, pbn_b0_8_115200 },
{ /* RockForceF8 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x2700,
0, 0, pbn_b0_8_115200 },
{ /* IQ Express D1 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3000,
0, 0, pbn_b0_1_115200 },
{ /* IQ Express F1 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3100,
0, 0, pbn_b0_1_115200 },
{ /* IQ Express D2 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3200,
0, 0, pbn_b0_2_115200 },
{ /* IQ Express F2 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3300,
0, 0, pbn_b0_2_115200 },
{ /* IQ Express D4 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3400,
0, 0, pbn_b0_4_115200 },
{ /* IQ Express F4 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3500,
0, 0, pbn_b0_4_115200 },
{ /* IQ Express D8 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3C00,
0, 0, pbn_b0_8_115200 },
{ /* IQ Express F8 */
PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
PCI_VENDOR_ID_MAINPINE, 0x3D00,
0, 0, pbn_b0_8_115200 },
/*
* PA Semi PA6T-1682M on-chip UART
*/
{ PCI_VENDOR_ID_PASEMI, 0xa004,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_pasemi_1682M },
/*
* National Instruments
*/
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_16_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_8_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_4_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_2_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_4_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_2_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_16_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_8_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_4_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_2_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_4_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_bt_2_115200 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_2 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_2 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_4 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_4 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_8 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_8 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_16 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_16 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_2 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_2 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_4 },
{ PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ni8430_4 },
/*
* MOXA
*/
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_2p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_2p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_4p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_4p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_2p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_4p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
{ PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_moxa8250_8p },
/*
* ADDI-DATA GmbH communication cards <[email protected]>
*/
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7500,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_4_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7420,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_2_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7300,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_AMCC,
PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b1_8_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_4_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_2_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_4_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_2_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_1_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_b0_8_115200 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCIe7500,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_ADDIDATA_PCIe_4_3906250 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCIe7420,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_ADDIDATA_PCIe_2_3906250 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCIe7300,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_ADDIDATA_PCIe_1_3906250 },
{ PCI_VENDOR_ID_ADDIDATA,
PCI_DEVICE_ID_ADDIDATA_APCIe7800,
PCI_ANY_ID,
PCI_ANY_ID,
0,
0,
pbn_ADDIDATA_PCIe_8_3906250 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
PCI_VENDOR_ID_IBM, 0x0299,
0, 0, pbn_b0_bt_2_115200 },
/*
* other NetMos 9835 devices are most likely handled by the
* parport_serial driver, check drivers/parport/parport_serial.c
* before adding them here.
*/
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
/* the 9901 is a rebranded 9912 */
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
0xA000, 0x3002,
0, 0, pbn_NETMOS9900_2s_115200 },
/*
* Best Connectivity and Rosewill PCI Multi I/O cards
*/
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
0xA000, 0x3002,
0, 0, pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
0xA000, 0x3004,
0, 0, pbn_b0_bt_4_115200 },
/*
* ASIX AX99100 PCIe to Multi I/O Controller
*/
{ PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
0xA000, 0x1000,
0, 0, pbn_b0_1_115200 },
/* Intel CE4100 */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ce4100_1_115200 },
/*
* Cronyx Omega PCI
*/
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_omegapci },
/*
* Broadcom TruManage
*/
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_brcm_trumanage },
/*
* AgeStar as-prs2-009
*/
{ PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_bt_2_115200 },
/*
* WCH CH353 series devices: The 2S1P is handled by parport_serial
* so not listed here.
*/
{ PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_bt_4_115200 },
{ PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_bt_2_115200 },
{ PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_bt_4_115200 },
{ PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_wch382_2 },
{ PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_wch384_4 },
{ PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_wch384_8 },
/*
* Realtek RealManage
*/
{ PCI_VENDOR_ID_REALTEK, 0x816a,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_1_115200 },
{ PCI_VENDOR_ID_REALTEK, 0x816b,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_1_115200 },
/* Fintek PCI serial cards */
{ PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
{ PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
{ PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
{ PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
{ PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
{ PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
/* MKS Tenta SCOM-080x serial cards */
{ PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
{ PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
/* Amazon PCI serial device */
{ PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
/*
* These entries match devices with class COMMUNICATION_SERIAL,
* COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
*/
{ PCI_ANY_ID, PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_COMMUNICATION_SERIAL << 8,
0xffff00, pbn_default },
{ PCI_ANY_ID, PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_COMMUNICATION_MODEM << 8,
0xffff00, pbn_default },
{ PCI_ANY_ID, PCI_ANY_ID,
PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
0xffff00, pbn_default },
{ 0, }
};
static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
pci_channel_state_t state)
{
struct serial_private *priv = pci_get_drvdata(dev);
if (state == pci_channel_io_perm_failure)
return PCI_ERS_RESULT_DISCONNECT;
if (priv)
pciserial_detach_ports(priv);
pci_disable_device(dev);
return PCI_ERS_RESULT_NEED_RESET;
}
static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
{
int rc;
rc = pci_enable_device(dev);
if (rc)
return PCI_ERS_RESULT_DISCONNECT;
pci_restore_state(dev);
pci_save_state(dev);
return PCI_ERS_RESULT_RECOVERED;
}
static void serial8250_io_resume(struct pci_dev *dev)
{
struct serial_private *priv = pci_get_drvdata(dev);
struct serial_private *new;
if (!priv)
return;
new = pciserial_init_ports(dev, priv->board);
if (!IS_ERR(new)) {
pci_set_drvdata(dev, new);
kfree(priv);
}
}
static const struct pci_error_handlers serial8250_err_handler = {
.error_detected = serial8250_io_error_detected,
.slot_reset = serial8250_io_slot_reset,
.resume = serial8250_io_resume,
};
static struct pci_driver serial_pci_driver = {
.name = "serial",
.probe = pciserial_init_one,
.remove = pciserial_remove_one,
.driver = {
.pm = &pciserial_pm_ops,
},
.id_table = serial_pci_tbl,
.err_handler = &serial8250_err_handler,
};
module_pci_driver(serial_pci_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
MODULE_IMPORT_NS(SERIAL_8250_PCI);
| linux-master | drivers/tty/serial/8250/8250_pci.c |
// SPDX-License-Identifier: GPL-2.0
/*
* 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
*
* Copyright (C) 2016 Intel Corporation
* Author: Andy Shevchenko <[email protected]>
*/
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/rational.h>
#include <linux/dmaengine.h>
#include <linux/dma/dw.h>
#include "8250_dwlib.h"
#define PCI_DEVICE_ID_INTEL_QRK_UARTx 0x0936
#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
#define PCI_DEVICE_ID_INTEL_EHL_UART0 0x4b96
#define PCI_DEVICE_ID_INTEL_EHL_UART1 0x4b97
#define PCI_DEVICE_ID_INTEL_EHL_UART2 0x4b98
#define PCI_DEVICE_ID_INTEL_EHL_UART3 0x4b99
#define PCI_DEVICE_ID_INTEL_EHL_UART4 0x4b9a
#define PCI_DEVICE_ID_INTEL_EHL_UART5 0x4b9b
#define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
#define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
/* Intel LPSS specific registers */
#define BYT_PRV_CLK 0x800
#define BYT_PRV_CLK_EN BIT(0)
#define BYT_PRV_CLK_M_VAL_SHIFT 1
#define BYT_PRV_CLK_N_VAL_SHIFT 16
#define BYT_PRV_CLK_UPDATE BIT(31)
#define BYT_TX_OVF_INT 0x820
#define BYT_TX_OVF_INT_MASK BIT(1)
struct lpss8250;
struct lpss8250_board {
unsigned long freq;
unsigned int base_baud;
int (*setup)(struct lpss8250 *, struct uart_port *p);
void (*exit)(struct lpss8250 *);
};
struct lpss8250 {
struct dw8250_port_data data;
struct lpss8250_board *board;
/* DMA parameters */
struct dw_dma_chip dma_chip;
struct dw_dma_slave dma_param;
u8 dma_maxburst;
};
static inline struct lpss8250 *to_lpss8250(struct dw8250_port_data *data)
{
return container_of(data, struct lpss8250, data);
}
static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
const struct ktermios *old)
{
unsigned int baud = tty_termios_baud_rate(termios);
struct lpss8250 *lpss = to_lpss8250(p->private_data);
unsigned long fref = lpss->board->freq, fuart = baud * 16;
unsigned long w = BIT(15) - 1;
unsigned long m, n;
u32 reg;
/* Gracefully handle the B0 case: fall back to B9600 */
fuart = fuart ? fuart : 9600 * 16;
/* Get Fuart closer to Fref */
fuart *= rounddown_pow_of_two(fref / fuart);
/*
* For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
* dividers must be adjusted.
*
* uartclk = (m / n) * 100 MHz, where m <= n
*/
rational_best_approximation(fuart, fref, w, w, &m, &n);
p->uartclk = fuart;
/* Reset the clock */
reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
writel(reg, p->membase + BYT_PRV_CLK);
reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
writel(reg, p->membase + BYT_PRV_CLK);
dw8250_do_set_termios(p, termios, old);
}
static unsigned int byt_get_mctrl(struct uart_port *port)
{
unsigned int ret = serial8250_do_get_mctrl(port);
/* Force DCD and DSR signals to permanently be reported as active */
ret |= TIOCM_CAR | TIOCM_DSR;
return ret;
}
static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
struct dw_dma_slave *param = &lpss->dma_param;
struct pci_dev *pdev = to_pci_dev(port->dev);
struct pci_dev *dma_dev;
switch (pdev->device) {
case PCI_DEVICE_ID_INTEL_BYT_UART1:
case PCI_DEVICE_ID_INTEL_BSW_UART1:
case PCI_DEVICE_ID_INTEL_BDW_UART1:
param->src_id = 3;
param->dst_id = 2;
break;
case PCI_DEVICE_ID_INTEL_BYT_UART2:
case PCI_DEVICE_ID_INTEL_BSW_UART2:
case PCI_DEVICE_ID_INTEL_BDW_UART2:
param->src_id = 5;
param->dst_id = 4;
break;
default:
return -EINVAL;
}
dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
param->dma_dev = &dma_dev->dev;
param->m_master = 0;
param->p_master = 1;
lpss->dma_maxburst = 16;
port->set_termios = byt_set_termios;
port->get_mctrl = byt_get_mctrl;
/* Disable TX counter interrupts */
writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
return 0;
}
static void byt_serial_exit(struct lpss8250 *lpss)
{
struct dw_dma_slave *param = &lpss->dma_param;
/* Paired with pci_get_slot() in the byt_serial_setup() above */
put_device(param->dma_dev);
}
static int ehl_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
struct uart_8250_dma *dma = &lpss->data.dma;
struct uart_8250_port *up = up_to_u8250p(port);
/*
* This simply makes the checks in the 8250_port to try the DMA
* channel request which in turn uses the magic of ACPI tables
* parsing (see drivers/dma/acpi-dma.c for the details) and
* matching with the registered General Purpose DMA controllers.
*/
up->dma = dma;
lpss->dma_maxburst = 16;
port->set_termios = dw8250_do_set_termios;
return 0;
}
static void ehl_serial_exit(struct lpss8250 *lpss)
{
struct uart_8250_port *up = serial8250_get_port(lpss->data.line);
up->dma = NULL;
}
#ifdef CONFIG_SERIAL_8250_DMA
static const struct dw_dma_platform_data qrk_serial_dma_pdata = {
.nr_channels = 2,
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
.chan_priority = CHAN_PRIORITY_ASCENDING,
.block_size = 4095,
.nr_masters = 1,
.data_width = {4},
.multi_block = {0},
};
static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port)
{
struct uart_8250_dma *dma = &lpss->data.dma;
struct dw_dma_chip *chip = &lpss->dma_chip;
struct dw_dma_slave *param = &lpss->dma_param;
struct pci_dev *pdev = to_pci_dev(port->dev);
int ret;
chip->pdata = &qrk_serial_dma_pdata;
chip->dev = &pdev->dev;
chip->id = pdev->devfn;
chip->irq = pci_irq_vector(pdev, 0);
chip->regs = pci_ioremap_bar(pdev, 1);
if (!chip->regs)
return;
/* Falling back to PIO mode if DMA probing fails */
ret = dw_dma_probe(chip);
if (ret)
return;
pci_try_set_mwi(pdev);
/* Special DMA address for UART */
dma->rx_dma_addr = 0xfffff000;
dma->tx_dma_addr = 0xfffff000;
param->dma_dev = &pdev->dev;
param->src_id = 0;
param->dst_id = 1;
param->hs_polarity = true;
lpss->dma_maxburst = 8;
}
static void qrk_serial_exit_dma(struct lpss8250 *lpss)
{
struct dw_dma_chip *chip = &lpss->dma_chip;
struct dw_dma_slave *param = &lpss->dma_param;
if (!param->dma_dev)
return;
dw_dma_remove(chip);
pci_iounmap(to_pci_dev(chip->dev), chip->regs);
}
#else /* CONFIG_SERIAL_8250_DMA */
static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port) {}
static void qrk_serial_exit_dma(struct lpss8250 *lpss) {}
#endif /* !CONFIG_SERIAL_8250_DMA */
static int qrk_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
{
qrk_serial_setup_dma(lpss, port);
return 0;
}
static void qrk_serial_exit(struct lpss8250 *lpss)
{
qrk_serial_exit_dma(lpss);
}
static bool lpss8250_dma_filter(struct dma_chan *chan, void *param)
{
struct dw_dma_slave *dws = param;
if (dws->dma_dev != chan->device->dev)
return false;
chan->private = dws;
return true;
}
static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port)
{
struct uart_8250_dma *dma = &lpss->data.dma;
struct dw_dma_slave *rx_param, *tx_param;
struct device *dev = port->port.dev;
if (!lpss->dma_param.dma_dev) {
dma = port->dma;
if (dma)
goto out_configuration_only;
return 0;
}
rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
if (!rx_param)
return -ENOMEM;
tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
if (!tx_param)
return -ENOMEM;
*rx_param = lpss->dma_param;
*tx_param = lpss->dma_param;
dma->fn = lpss8250_dma_filter;
dma->rx_param = rx_param;
dma->tx_param = tx_param;
port->dma = dma;
out_configuration_only:
dma->rxconf.src_maxburst = lpss->dma_maxburst;
dma->txconf.dst_maxburst = lpss->dma_maxburst;
return 0;
}
static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct uart_8250_port uart;
struct lpss8250 *lpss;
int ret;
ret = pcim_enable_device(pdev);
if (ret)
return ret;
pci_set_master(pdev);
lpss = devm_kzalloc(&pdev->dev, sizeof(*lpss), GFP_KERNEL);
if (!lpss)
return -ENOMEM;
ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
if (ret < 0)
return ret;
lpss->board = (struct lpss8250_board *)id->driver_data;
memset(&uart, 0, sizeof(struct uart_8250_port));
uart.port.dev = &pdev->dev;
uart.port.irq = pci_irq_vector(pdev, 0);
uart.port.private_data = &lpss->data;
uart.port.type = PORT_16550A;
uart.port.iotype = UPIO_MEM32;
uart.port.regshift = 2;
uart.port.uartclk = lpss->board->base_baud * 16;
uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
uart.port.mapbase = pci_resource_start(pdev, 0);
uart.port.membase = pcim_iomap(pdev, 0, 0);
if (!uart.port.membase)
return -ENOMEM;
ret = lpss->board->setup(lpss, &uart.port);
if (ret)
return ret;
dw8250_setup_port(&uart.port);
ret = lpss8250_dma_setup(lpss, &uart);
if (ret)
goto err_exit;
ret = serial8250_register_8250_port(&uart);
if (ret < 0)
goto err_exit;
lpss->data.line = ret;
pci_set_drvdata(pdev, lpss);
return 0;
err_exit:
lpss->board->exit(lpss);
pci_free_irq_vectors(pdev);
return ret;
}
static void lpss8250_remove(struct pci_dev *pdev)
{
struct lpss8250 *lpss = pci_get_drvdata(pdev);
serial8250_unregister_port(lpss->data.line);
lpss->board->exit(lpss);
pci_free_irq_vectors(pdev);
}
static const struct lpss8250_board byt_board = {
.freq = 100000000,
.base_baud = 2764800,
.setup = byt_serial_setup,
.exit = byt_serial_exit,
};
static const struct lpss8250_board ehl_board = {
.freq = 200000000,
.base_baud = 12500000,
.setup = ehl_serial_setup,
.exit = ehl_serial_exit,
};
static const struct lpss8250_board qrk_board = {
.freq = 44236800,
.base_baud = 2764800,
.setup = qrk_serial_setup,
.exit = qrk_serial_exit,
};
static const struct pci_device_id pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, QRK_UARTx, &qrk_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART0, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART1, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART2, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART3, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART4, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, EHL_UART5, &ehl_board) },
{ PCI_DEVICE_DATA(INTEL, BYT_UART1, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BYT_UART2, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BSW_UART1, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BSW_UART2, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BDW_UART1, &byt_board) },
{ PCI_DEVICE_DATA(INTEL, BDW_UART2, &byt_board) },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);
static struct pci_driver lpss8250_pci_driver = {
.name = "8250_lpss",
.id_table = pci_ids,
.probe = lpss8250_probe,
.remove = lpss8250_remove,
};
module_pci_driver(lpss8250_pci_driver);
MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel LPSS UART driver");
| linux-master | drivers/tty/serial/8250/8250_lpss.c |
// SPDX-License-Identifier: GPL-2.0
/* Driver for Pericom UART */
#include <linux/bits.h>
#include <linux/module.h>
#include <linux/overflow.h>
#include <linux/pci.h>
#include "8250.h"
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM_2SDB 0x1051
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_2S 0x1053
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM422_4 0x105a
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM485_4 0x105b
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM_4SDB 0x105c
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_4S 0x105e
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM422_8 0x106a
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM485_8 0x106b
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_2DB 0x1091
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_COM232_2 0x1093
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_4 0x1098
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_4DB 0x1099
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_COM232_4 0x109b
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_8 0x10a9
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM_2SMDB 0x10d1
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_2SM 0x10d3
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM_4SM 0x10d9
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM_4SMDB 0x10da
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_4SM 0x10dc
#define PCI_DEVICE_ID_ACCESSIO_PCIE_COM_8SM 0x10e9
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM485_1 0x1108
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM422_2 0x1110
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM485_2 0x1111
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM422_4 0x1118
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM485_4 0x1119
#define PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_2S 0x1152
#define PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_4S 0x115a
#define PCI_DEVICE_ID_ACCESSIO_PCIE_ICM232_2 0x1190
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM232_2 0x1191
#define PCI_DEVICE_ID_ACCESSIO_PCIE_ICM232_4 0x1198
#define PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM232_4 0x1199
#define PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_2SM 0x11d0
#define PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_4SM 0x11d8
struct pericom8250 {
void __iomem *virt;
unsigned int nr;
int line[];
};
static void pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
unsigned int quot, unsigned int quot_frac)
{
int scr;
for (scr = 16; scr > 4; scr--) {
unsigned int maxrate = port->uartclk / scr;
unsigned int divisor = max(maxrate / baud, 1U);
int delta = maxrate / divisor - baud;
if (baud > maxrate + baud / 50)
continue;
if (delta > baud / 50)
divisor++;
if (divisor > 0xffff)
continue;
/* Update delta due to possible divisor change */
delta = maxrate / divisor - baud;
if (abs(delta) < baud / 50) {
struct uart_8250_port *up = up_to_u8250p(port);
int lcr = serial_port_in(port, UART_LCR);
serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
serial_dl_write(up, divisor);
serial_port_out(port, 2, 16 - scr);
serial_port_out(port, UART_LCR, lcr);
return;
}
}
}
static int pericom8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
unsigned int nr, i, bar = 0, maxnr;
struct pericom8250 *pericom;
struct uart_8250_port uart;
int ret;
ret = pcim_enable_device(pdev);
if (ret)
return ret;
maxnr = pci_resource_len(pdev, bar) >> 3;
if (pdev->vendor == PCI_VENDOR_ID_PERICOM)
nr = pdev->device & 0x0f;
else if (pdev->vendor == PCI_VENDOR_ID_ACCESSIO)
nr = BIT(((pdev->device & 0x38) >> 3) - 1);
else
nr = 1;
pericom = devm_kzalloc(&pdev->dev, struct_size(pericom, line, nr), GFP_KERNEL);
if (!pericom)
return -ENOMEM;
pericom->virt = pcim_iomap(pdev, bar, 0);
if (!pericom->virt)
return -ENOMEM;
memset(&uart, 0, sizeof(uart));
uart.port.dev = &pdev->dev;
uart.port.irq = pdev->irq;
uart.port.private_data = pericom;
uart.port.iotype = UPIO_PORT;
uart.port.uartclk = 921600 * 16;
uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
uart.port.set_divisor = pericom_do_set_divisor;
for (i = 0; i < nr && i < maxnr; i++) {
unsigned int offset = (i == 3 && nr == 4) ? 0x38 : i * 0x8;
uart.port.iobase = pci_resource_start(pdev, bar) + offset;
dev_dbg(&pdev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
uart.port.iobase, uart.port.irq, uart.port.iotype);
pericom->line[i] = serial8250_register_8250_port(&uart);
if (pericom->line[i] < 0) {
dev_err(&pdev->dev,
"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
uart.port.iobase, uart.port.irq,
uart.port.iotype, pericom->line[i]);
break;
}
}
pericom->nr = i;
pci_set_drvdata(pdev, pericom);
return 0;
}
static void pericom8250_remove(struct pci_dev *pdev)
{
struct pericom8250 *pericom = pci_get_drvdata(pdev);
unsigned int i;
for (i = 0; i < pericom->nr; i++)
serial8250_unregister_port(pericom->line[i]);
}
static const struct pci_device_id pericom8250_pci_ids[] = {
/*
* Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
* (Only 7954 has an offset jump for port 4)
*/
{ PCI_VDEVICE(PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951) },
{ PCI_VDEVICE(PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952) },
{ PCI_VDEVICE(PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954) },
{ PCI_VDEVICE(PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958) },
/*
* ACCES I/O Products quad
* (Only 7954 has an offset jump for port 4)
*/
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM_2SDB) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_2S) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM422_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM485_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM_4SDB) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_4S) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM422_8) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM485_8) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_2DB) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_COM232_2) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_4DB) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_COM232_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM232_8) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM_2SMDB) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_2SM) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM_4SM) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM_4SMDB) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_COM_4SM) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_COM_8SM) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM485_1) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM422_2) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM485_2) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM422_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM485_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_2S) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_4S) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_ICM232_2) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM232_2) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_ICM232_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_MPCIE_ICM232_4) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_2SM) },
{ PCI_VDEVICE(ACCESSIO, PCI_DEVICE_ID_ACCESSIO_PCIE_ICM_4SM) },
{ }
};
MODULE_DEVICE_TABLE(pci, pericom8250_pci_ids);
static struct pci_driver pericom8250_pci_driver = {
.name = "8250_pericom",
.id_table = pericom8250_pci_ids,
.probe = pericom8250_probe,
.remove = pericom8250_remove,
};
module_pci_driver(pericom8250_pci_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Pericom UART driver");
| linux-master | drivers/tty/serial/8250/8250_pericom.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
* Copyright: (C) 2013 Sergei Ianovich <[email protected]>
*
* replaces drivers/serial/pxa.c by Nicolas Pitre
* Created: Feb 20, 2003
* Copyright: (C) 2003 Monta Vista Software, Inc.
*
* Based on drivers/serial/8250.c by Russell King.
*/
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include "8250.h"
struct pxa8250_data {
int line;
struct clk *clk;
};
static int __maybe_unused serial_pxa_suspend(struct device *dev)
{
struct pxa8250_data *data = dev_get_drvdata(dev);
serial8250_suspend_port(data->line);
return 0;
}
static int __maybe_unused serial_pxa_resume(struct device *dev)
{
struct pxa8250_data *data = dev_get_drvdata(dev);
serial8250_resume_port(data->line);
return 0;
}
static const struct dev_pm_ops serial_pxa_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(serial_pxa_suspend, serial_pxa_resume)
};
static const struct of_device_id serial_pxa_dt_ids[] = {
{ .compatible = "mrvl,pxa-uart", },
{ .compatible = "mrvl,mmp-uart", },
{}
};
MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
/* Uart divisor latch write */
static void serial_pxa_dl_write(struct uart_8250_port *up, u32 value)
{
unsigned int dll;
serial_out(up, UART_DLL, value & 0xff);
/*
* work around Erratum #74 according to Marvel(R) PXA270M Processor
* Specification Update (April 19, 2010)
*/
dll = serial_in(up, UART_DLL);
WARN_ON(dll != (value & 0xff));
serial_out(up, UART_DLM, value >> 8 & 0xff);
}
static void serial_pxa_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
struct pxa8250_data *data = port->private_data;
if (!state)
clk_prepare_enable(data->clk);
else
clk_disable_unprepare(data->clk);
}
static int serial_pxa_probe(struct platform_device *pdev)
{
struct uart_8250_port uart = {};
struct pxa8250_data *data;
struct resource *mmres;
int irq, ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mmres)
return -ENODEV;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(data->clk))
return PTR_ERR(data->clk);
ret = clk_prepare(data->clk);
if (ret)
return ret;
ret = of_alias_get_id(pdev->dev.of_node, "serial");
if (ret >= 0)
uart.port.line = ret;
uart.port.type = PORT_XSCALE;
uart.port.iotype = UPIO_MEM32;
uart.port.mapbase = mmres->start;
uart.port.regshift = 2;
uart.port.irq = irq;
uart.port.fifosize = 64;
uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE;
uart.port.dev = &pdev->dev;
uart.port.uartclk = clk_get_rate(data->clk);
uart.port.pm = serial_pxa_pm;
uart.port.private_data = data;
uart.dl_write = serial_pxa_dl_write;
ret = serial8250_register_8250_port(&uart);
if (ret < 0)
goto err_clk;
data->line = ret;
platform_set_drvdata(pdev, data);
return 0;
err_clk:
clk_unprepare(data->clk);
return ret;
}
static int serial_pxa_remove(struct platform_device *pdev)
{
struct pxa8250_data *data = platform_get_drvdata(pdev);
serial8250_unregister_port(data->line);
clk_unprepare(data->clk);
return 0;
}
static struct platform_driver serial_pxa_driver = {
.probe = serial_pxa_probe,
.remove = serial_pxa_remove,
.driver = {
.name = "pxa2xx-uart",
.pm = &serial_pxa_pm_ops,
.of_match_table = serial_pxa_dt_ids,
},
};
module_platform_driver(serial_pxa_driver);
#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init early_serial_pxa_setup(struct earlycon_device *device,
const char *options)
{
struct uart_port *port = &device->port;
if (!(device->port.membase || device->port.iobase))
return -ENODEV;
port->regshift = 2;
return early_serial8250_setup(device, NULL);
}
OF_EARLYCON_DECLARE(early_pxa, "mrvl,pxa-uart", early_serial_pxa_setup);
OF_EARLYCON_DECLARE(mmp, "mrvl,mmp-uart", early_serial_pxa_setup);
#endif
MODULE_AUTHOR("Sergei Ianovich");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-uart");
| linux-master | drivers/tty/serial/8250/8250_pxa.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Serial port driver for BCM2835AUX UART
*
* Copyright (C) 2016 Martin Sperl <[email protected]>
*
* Based on 8250_lpc18xx.c:
* Copyright (C) 2015 Joachim Eastwood <[email protected]>
*
* The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
* take advantage of it yet. When adding support, be sure not to enable it
* simultaneously to rs485.
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include "8250.h"
#define BCM2835_AUX_UART_CNTL 8
#define BCM2835_AUX_UART_CNTL_RXEN 0x01 /* Receiver enable */
#define BCM2835_AUX_UART_CNTL_TXEN 0x02 /* Transmitter enable */
#define BCM2835_AUX_UART_CNTL_AUTORTS 0x04 /* RTS set by RX fill level */
#define BCM2835_AUX_UART_CNTL_AUTOCTS 0x08 /* CTS stops transmitter */
#define BCM2835_AUX_UART_CNTL_RTS3 0x00 /* RTS set until 3 chars left */
#define BCM2835_AUX_UART_CNTL_RTS2 0x10 /* RTS set until 2 chars left */
#define BCM2835_AUX_UART_CNTL_RTS1 0x20 /* RTS set until 1 chars left */
#define BCM2835_AUX_UART_CNTL_RTS4 0x30 /* RTS set until 4 chars left */
#define BCM2835_AUX_UART_CNTL_RTSINV 0x40 /* Invert auto RTS polarity */
#define BCM2835_AUX_UART_CNTL_CTSINV 0x80 /* Invert auto CTS polarity */
/**
* struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
* @clk: clock producer of the port's uartclk
* @line: index of the port's serial8250_ports[] entry
* @cntl: cached copy of CNTL register
*/
struct bcm2835aux_data {
struct clk *clk;
int line;
u32 cntl;
};
struct bcm2835_aux_serial_driver_data {
resource_size_t offset;
};
static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up)
{
if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);
data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN;
serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);
}
/*
* On the bcm2835aux, the MCR register contains no other
* flags besides RTS. So no need for a read-modify-write.
*/
if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
serial8250_out_MCR(up, 0);
else
serial8250_out_MCR(up, UART_MCR_RTS);
}
static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up)
{
if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
serial8250_out_MCR(up, 0);
else
serial8250_out_MCR(up, UART_MCR_RTS);
if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev);
data->cntl |= BCM2835_AUX_UART_CNTL_RXEN;
serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl);
}
}
static int bcm2835aux_serial_probe(struct platform_device *pdev)
{
const struct bcm2835_aux_serial_driver_data *bcm_data;
struct uart_8250_port up = { };
struct bcm2835aux_data *data;
resource_size_t offset = 0;
struct resource *res;
unsigned int uartclk;
int ret;
/* allocate the custom structure */
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
/* initialize data */
up.capabilities = UART_CAP_FIFO | UART_CAP_MINI;
up.port.dev = &pdev->dev;
up.port.regshift = 2;
up.port.type = PORT_16550;
up.port.iotype = UPIO_MEM;
up.port.fifosize = 8;
up.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE |
UPF_SKIP_TEST | UPF_IOREMAP;
up.port.rs485_config = serial8250_em485_config;
up.port.rs485_supported = serial8250_em485_supported;
up.rs485_start_tx = bcm2835aux_rs485_start_tx;
up.rs485_stop_tx = bcm2835aux_rs485_stop_tx;
/* initialize cached copy with power-on reset value */
data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN;
platform_set_drvdata(pdev, data);
/* get the clock - this also enables the HW */
data->clk = devm_clk_get_optional(&pdev->dev, NULL);
/* get the interrupt */
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
up.port.irq = ret;
/* map the main registers */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "memory resource not found");
return -EINVAL;
}
bcm_data = device_get_match_data(&pdev->dev);
/* Some UEFI implementations (e.g. tianocore/edk2 for the Raspberry Pi)
* describe the miniuart with a base address that encompasses the auxiliary
* registers shared between the miniuart and spi.
*
* This is due to historical reasons, see discussion here :
* https://edk2.groups.io/g/devel/topic/87501357#84349
*
* We need to add the offset between the miniuart and auxiliary
* registers to get the real miniuart base address.
*/
if (bcm_data)
offset = bcm_data->offset;
up.port.mapbase = res->start + offset;
up.port.mapsize = resource_size(res) - offset;
/* Check for a fixed line number */
ret = of_alias_get_id(pdev->dev.of_node, "serial");
if (ret >= 0)
up.port.line = ret;
/* enable the clock as a last step */
ret = clk_prepare_enable(data->clk);
if (ret) {
dev_err(&pdev->dev, "unable to enable uart clock - %d\n",
ret);
return ret;
}
uartclk = clk_get_rate(data->clk);
if (!uartclk) {
ret = device_property_read_u32(&pdev->dev, "clock-frequency", &uartclk);
if (ret) {
dev_err_probe(&pdev->dev, ret, "could not get clk rate\n");
goto dis_clk;
}
}
/* the HW-clock divider for bcm2835aux is 8,
* but 8250 expects a divider of 16,
* so we have to multiply the actual clock by 2
* to get identical baudrates.
*/
up.port.uartclk = uartclk * 2;
/* register the port */
ret = serial8250_register_8250_port(&up);
if (ret < 0) {
dev_err_probe(&pdev->dev, ret, "unable to register 8250 port\n");
goto dis_clk;
}
data->line = ret;
return 0;
dis_clk:
clk_disable_unprepare(data->clk);
return ret;
}
static int bcm2835aux_serial_remove(struct platform_device *pdev)
{
struct bcm2835aux_data *data = platform_get_drvdata(pdev);
serial8250_unregister_port(data->line);
clk_disable_unprepare(data->clk);
return 0;
}
static const struct bcm2835_aux_serial_driver_data bcm2835_acpi_data = {
.offset = 0x40,
};
static const struct of_device_id bcm2835aux_serial_match[] = {
{ .compatible = "brcm,bcm2835-aux-uart" },
{ },
};
MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match);
static const struct acpi_device_id bcm2835aux_serial_acpi_match[] = {
{ "BCM2836", (kernel_ulong_t)&bcm2835_acpi_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match);
static struct platform_driver bcm2835aux_serial_driver = {
.driver = {
.name = "bcm2835-aux-uart",
.of_match_table = bcm2835aux_serial_match,
.acpi_match_table = bcm2835aux_serial_acpi_match,
},
.probe = bcm2835aux_serial_probe,
.remove = bcm2835aux_serial_remove,
};
module_platform_driver(bcm2835aux_serial_driver);
#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init early_bcm2835aux_setup(struct earlycon_device *device,
const char *options)
{
if (!device->port.membase)
return -ENODEV;
device->port.iotype = UPIO_MEM32;
device->port.regshift = 2;
return early_serial8250_setup(device, NULL);
}
OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart",
early_bcm2835aux_setup);
#endif
MODULE_DESCRIPTION("BCM2835 auxiliar UART driver");
MODULE_AUTHOR("Martin Sperl <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/8250/8250_bcm2835aux.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Base port operations for 8250/16550-type serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
* Split from 8250_core.c, Copyright (C) 2001 Russell King.
*
* A note about mapbase / membase
*
* mapbase is the physical address of the IO port.
* membase is an 'ioremapped' cookie.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/console.h>
#include <linux/gpio/consumer.h>
#include <linux/sysrq.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/ratelimit.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/nmi.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/pm_runtime.h>
#include <linux/ktime.h>
#include <asm/io.h>
#include <asm/irq.h>
#include "8250.h"
/* Nuvoton NPCM timeout register */
#define UART_NPCM_TOR 7
#define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
/*
* Debugging.
*/
#if 0
#define DEBUG_AUTOCONF(fmt...) printk(fmt)
#else
#define DEBUG_AUTOCONF(fmt...) do { } while (0)
#endif
/*
* Here we define the default xmit fifo size used for each type of UART.
*/
static const struct serial8250_config uart_config[] = {
[PORT_UNKNOWN] = {
.name = "unknown",
.fifo_size = 1,
.tx_loadsz = 1,
},
[PORT_8250] = {
.name = "8250",
.fifo_size = 1,
.tx_loadsz = 1,
},
[PORT_16450] = {
.name = "16450",
.fifo_size = 1,
.tx_loadsz = 1,
},
[PORT_16550] = {
.name = "16550",
.fifo_size = 1,
.tx_loadsz = 1,
},
[PORT_16550A] = {
.name = "16550A",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
[PORT_CIRRUS] = {
.name = "Cirrus",
.fifo_size = 1,
.tx_loadsz = 1,
},
[PORT_16650] = {
.name = "ST16650",
.fifo_size = 1,
.tx_loadsz = 1,
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
[PORT_16650V2] = {
.name = "ST16650V2",
.fifo_size = 32,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
UART_FCR_T_TRIG_00,
.rxtrig_bytes = {8, 16, 24, 28},
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
[PORT_16750] = {
.name = "TI16750",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
UART_FCR7_64BYTE,
.rxtrig_bytes = {1, 16, 32, 56},
.flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
},
[PORT_STARTECH] = {
.name = "Startech",
.fifo_size = 1,
.tx_loadsz = 1,
},
[PORT_16C950] = {
.name = "16C950/954",
.fifo_size = 128,
.tx_loadsz = 128,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
.rxtrig_bytes = {16, 32, 112, 120},
/* UART_CAP_EFR breaks billionon CF bluetooth card. */
.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
},
[PORT_16654] = {
.name = "ST16654",
.fifo_size = 64,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
UART_FCR_T_TRIG_10,
.rxtrig_bytes = {8, 16, 56, 60},
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
[PORT_16850] = {
.name = "XR16850",
.fifo_size = 128,
.tx_loadsz = 128,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
},
[PORT_RSA] = {
.name = "RSA",
.fifo_size = 2048,
.tx_loadsz = 2048,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
.flags = UART_CAP_FIFO,
},
[PORT_NS16550A] = {
.name = "NS16550A",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_NATSEMI,
},
[PORT_XSCALE] = {
.name = "XScale",
.fifo_size = 32,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
},
[PORT_OCTEON] = {
.name = "OCTEON",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO,
},
[PORT_AR7] = {
.name = "AR7",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
.flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
},
[PORT_U6_16550A] = {
.name = "U6_16550A",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
[PORT_TEGRA] = {
.name = "Tegra",
.fifo_size = 32,
.tx_loadsz = 8,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
UART_FCR_T_TRIG_01,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO | UART_CAP_RTOIE,
},
[PORT_XR17D15X] = {
.name = "XR17D15X",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
UART_CAP_SLEEP,
},
[PORT_XR17V35X] = {
.name = "XR17V35X",
.fifo_size = 256,
.tx_loadsz = 256,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
UART_FCR_T_TRIG_11,
.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
UART_CAP_SLEEP,
},
[PORT_LPC3220] = {
.name = "LPC3220",
.fifo_size = 64,
.tx_loadsz = 32,
.fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
.flags = UART_CAP_FIFO,
},
[PORT_BRCM_TRUMANAGE] = {
.name = "TruManage",
.fifo_size = 1,
.tx_loadsz = 1024,
.flags = UART_CAP_HFIFO,
},
[PORT_8250_CIR] = {
.name = "CIR port"
},
[PORT_ALTR_16550_F32] = {
.name = "Altera 16550 FIFO32",
.fifo_size = 32,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 8, 16, 30},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
[PORT_ALTR_16550_F64] = {
.name = "Altera 16550 FIFO64",
.fifo_size = 64,
.tx_loadsz = 64,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 16, 32, 62},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
[PORT_ALTR_16550_F128] = {
.name = "Altera 16550 FIFO128",
.fifo_size = 128,
.tx_loadsz = 128,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 32, 64, 126},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
/*
* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
* workaround of errata A-008006 which states that tx_loadsz should
* be configured less than Maximum supported fifo bytes.
*/
[PORT_16550A_FSL64] = {
.name = "16550A_FSL64",
.fifo_size = 64,
.tx_loadsz = 63,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
UART_FCR7_64BYTE,
.flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
},
[PORT_RT2880] = {
.name = "Palmchip BK-3103",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
[PORT_DA830] = {
.name = "TI DA8xx/66AK2x",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
[PORT_MTK_BTIF] = {
.name = "MediaTek BTIF",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
.flags = UART_CAP_FIFO,
},
[PORT_NPCM] = {
.name = "Nuvoton 16550",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
[PORT_SUNIX] = {
.name = "Sunix",
.fifo_size = 128,
.tx_loadsz = 128,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.rxtrig_bytes = {1, 32, 64, 112},
.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
},
[PORT_ASPEED_VUART] = {
.name = "ASPEED VUART",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},
[PORT_MCHP16550A] = {
.name = "MCHP16550A",
.fifo_size = 256,
.tx_loadsz = 256,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
.rxtrig_bytes = {2, 66, 130, 194},
.flags = UART_CAP_FIFO,
},
[PORT_BCM7271] = {
.name = "Broadcom BCM7271 UART",
.fifo_size = 32,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
.rxtrig_bytes = {1, 8, 16, 30},
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
};
/* Uart divisor latch read */
static u32 default_serial_dl_read(struct uart_8250_port *up)
{
/* Assign these in pieces to truncate any bits above 7. */
unsigned char dll = serial_in(up, UART_DLL);
unsigned char dlm = serial_in(up, UART_DLM);
return dll | dlm << 8;
}
/* Uart divisor latch write */
static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
{
serial_out(up, UART_DLL, value & 0xff);
serial_out(up, UART_DLM, value >> 8 & 0xff);
}
static unsigned int hub6_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
outb(p->hub6 - 1 + offset, p->iobase);
return inb(p->iobase + 1);
}
static void hub6_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
outb(p->hub6 - 1 + offset, p->iobase);
outb(value, p->iobase + 1);
}
static unsigned int mem_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
return readb(p->membase + offset);
}
static void mem_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
writeb(value, p->membase + offset);
}
static void mem16_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
writew(value, p->membase + offset);
}
static unsigned int mem16_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
return readw(p->membase + offset);
}
static void mem32_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
writel(value, p->membase + offset);
}
static unsigned int mem32_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
return readl(p->membase + offset);
}
static void mem32be_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
iowrite32be(value, p->membase + offset);
}
static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
return ioread32be(p->membase + offset);
}
static unsigned int io_serial_in(struct uart_port *p, int offset)
{
offset = offset << p->regshift;
return inb(p->iobase + offset);
}
static void io_serial_out(struct uart_port *p, int offset, int value)
{
offset = offset << p->regshift;
outb(value, p->iobase + offset);
}
static int serial8250_default_handle_irq(struct uart_port *port);
static void set_io_from_upio(struct uart_port *p)
{
struct uart_8250_port *up = up_to_u8250p(p);
up->dl_read = default_serial_dl_read;
up->dl_write = default_serial_dl_write;
switch (p->iotype) {
case UPIO_HUB6:
p->serial_in = hub6_serial_in;
p->serial_out = hub6_serial_out;
break;
case UPIO_MEM:
p->serial_in = mem_serial_in;
p->serial_out = mem_serial_out;
break;
case UPIO_MEM16:
p->serial_in = mem16_serial_in;
p->serial_out = mem16_serial_out;
break;
case UPIO_MEM32:
p->serial_in = mem32_serial_in;
p->serial_out = mem32_serial_out;
break;
case UPIO_MEM32BE:
p->serial_in = mem32be_serial_in;
p->serial_out = mem32be_serial_out;
break;
default:
p->serial_in = io_serial_in;
p->serial_out = io_serial_out;
break;
}
/* Remember loaded iotype */
up->cur_iotype = p->iotype;
p->handle_irq = serial8250_default_handle_irq;
}
static void
serial_port_out_sync(struct uart_port *p, int offset, int value)
{
switch (p->iotype) {
case UPIO_MEM:
case UPIO_MEM16:
case UPIO_MEM32:
case UPIO_MEM32BE:
case UPIO_AU:
p->serial_out(p, offset, value);
p->serial_in(p, UART_LCR); /* safe, no side-effects */
break;
default:
p->serial_out(p, offset, value);
}
}
/*
* FIFO support.
*/
static void serial8250_clear_fifos(struct uart_8250_port *p)
{
if (p->capabilities & UART_CAP_FIFO) {
serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_out(p, UART_FCR, 0);
}
}
static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
{
serial8250_clear_fifos(p);
serial_out(p, UART_FCR, p->fcr);
}
EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
void serial8250_rpm_get(struct uart_8250_port *p)
{
if (!(p->capabilities & UART_CAP_RPM))
return;
pm_runtime_get_sync(p->port.dev);
}
EXPORT_SYMBOL_GPL(serial8250_rpm_get);
void serial8250_rpm_put(struct uart_8250_port *p)
{
if (!(p->capabilities & UART_CAP_RPM))
return;
pm_runtime_mark_last_busy(p->port.dev);
pm_runtime_put_autosuspend(p->port.dev);
}
EXPORT_SYMBOL_GPL(serial8250_rpm_put);
/**
* serial8250_em485_init() - put uart_8250_port into rs485 emulating
* @p: uart_8250_port port instance
*
* The function is used to start rs485 software emulating on the
* &struct uart_8250_port* @p. Namely, RTS is switched before/after
* transmission. The function is idempotent, so it is safe to call it
* multiple times.
*
* The caller MUST enable interrupt on empty shift register before
* calling serial8250_em485_init(). This interrupt is not a part of
* 8250 standard, but implementation defined.
*
* The function is supposed to be called from .rs485_config callback
* or from any other callback protected with p->port.lock spinlock.
*
* See also serial8250_em485_destroy()
*
* Return 0 - success, -errno - otherwise
*/
static int serial8250_em485_init(struct uart_8250_port *p)
{
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&p->port.lock);
if (p->em485)
goto deassert_rts;
p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
if (!p->em485)
return -ENOMEM;
hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
p->em485->port = p;
p->em485->active_timer = NULL;
p->em485->tx_stopped = true;
deassert_rts:
if (p->em485->tx_stopped)
p->rs485_stop_tx(p);
return 0;
}
/**
* serial8250_em485_destroy() - put uart_8250_port into normal state
* @p: uart_8250_port port instance
*
* The function is used to stop rs485 software emulating on the
* &struct uart_8250_port* @p. The function is idempotent, so it is safe to
* call it multiple times.
*
* The function is supposed to be called from .rs485_config callback
* or from any other callback protected with p->port.lock spinlock.
*
* See also serial8250_em485_init()
*/
void serial8250_em485_destroy(struct uart_8250_port *p)
{
if (!p->em485)
return;
hrtimer_cancel(&p->em485->start_tx_timer);
hrtimer_cancel(&p->em485->stop_tx_timer);
kfree(p->em485);
p->em485 = NULL;
}
EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
struct serial_rs485 serial8250_em485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
.delay_rts_before_send = 1,
.delay_rts_after_send = 1,
};
EXPORT_SYMBOL_GPL(serial8250_em485_supported);
/**
* serial8250_em485_config() - generic ->rs485_config() callback
* @port: uart port
* @termios: termios structure
* @rs485: rs485 settings
*
* Generic callback usable by 8250 uart drivers to activate rs485 settings
* if the uart is incapable of driving RTS as a Transmit Enable signal in
* hardware, relying on software emulation instead.
*/
int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct uart_8250_port *up = up_to_u8250p(port);
/* pick sane settings if the user hasn't */
if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
!!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
rs485->flags |= SER_RS485_RTS_ON_SEND;
rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
}
/*
* Both serial8250_em485_init() and serial8250_em485_destroy()
* are idempotent.
*/
if (rs485->flags & SER_RS485_ENABLED)
return serial8250_em485_init(up);
serial8250_em485_destroy(up);
return 0;
}
EXPORT_SYMBOL_GPL(serial8250_em485_config);
/*
* These two wrappers ensure that enable_runtime_pm_tx() can be called more than
* once and disable_runtime_pm_tx() will still disable RPM because the fifo is
* empty and the HW can idle again.
*/
void serial8250_rpm_get_tx(struct uart_8250_port *p)
{
unsigned char rpm_active;
if (!(p->capabilities & UART_CAP_RPM))
return;
rpm_active = xchg(&p->rpm_tx_active, 1);
if (rpm_active)
return;
pm_runtime_get_sync(p->port.dev);
}
EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
void serial8250_rpm_put_tx(struct uart_8250_port *p)
{
unsigned char rpm_active;
if (!(p->capabilities & UART_CAP_RPM))
return;
rpm_active = xchg(&p->rpm_tx_active, 0);
if (!rpm_active)
return;
pm_runtime_mark_last_busy(p->port.dev);
pm_runtime_put_autosuspend(p->port.dev);
}
EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
/*
* IER sleep support. UARTs which have EFRs need the "extended
* capability" bit enabled. Note that on XR16C850s, we need to
* reset LCR to write to IER.
*/
static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
{
unsigned char lcr = 0, efr = 0;
serial8250_rpm_get(p);
if (p->capabilities & UART_CAP_SLEEP) {
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&p->port.lock);
if (p->capabilities & UART_CAP_EFR) {
lcr = serial_in(p, UART_LCR);
efr = serial_in(p, UART_EFR);
serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(p, UART_EFR, UART_EFR_ECB);
serial_out(p, UART_LCR, 0);
}
serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
if (p->capabilities & UART_CAP_EFR) {
serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(p, UART_EFR, efr);
serial_out(p, UART_LCR, lcr);
}
spin_unlock_irq(&p->port.lock);
}
serial8250_rpm_put(p);
}
static void serial8250_clear_IER(struct uart_8250_port *up)
{
if (up->capabilities & UART_CAP_UUE)
serial_out(up, UART_IER, UART_IER_UUE);
else
serial_out(up, UART_IER, 0);
}
#ifdef CONFIG_SERIAL_8250_RSA
/*
* Attempts to turn on the RSA FIFO. Returns zero on failure.
* We set the port uart clock rate if we succeed.
*/
static int __enable_rsa(struct uart_8250_port *up)
{
unsigned char mode;
int result;
mode = serial_in(up, UART_RSA_MSR);
result = mode & UART_RSA_MSR_FIFO;
if (!result) {
serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
mode = serial_in(up, UART_RSA_MSR);
result = mode & UART_RSA_MSR_FIFO;
}
if (result)
up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
return result;
}
static void enable_rsa(struct uart_8250_port *up)
{
if (up->port.type == PORT_RSA) {
if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
spin_lock_irq(&up->port.lock);
__enable_rsa(up);
spin_unlock_irq(&up->port.lock);
}
if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
serial_out(up, UART_RSA_FRR, 0);
}
}
/*
* Attempts to turn off the RSA FIFO. Returns zero on failure.
* It is unknown why interrupts were disabled in here. However,
* the caller is expected to preserve this behaviour by grabbing
* the spinlock before calling this function.
*/
static void disable_rsa(struct uart_8250_port *up)
{
unsigned char mode;
int result;
if (up->port.type == PORT_RSA &&
up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
spin_lock_irq(&up->port.lock);
mode = serial_in(up, UART_RSA_MSR);
result = !(mode & UART_RSA_MSR_FIFO);
if (!result) {
serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
mode = serial_in(up, UART_RSA_MSR);
result = !(mode & UART_RSA_MSR_FIFO);
}
if (result)
up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
spin_unlock_irq(&up->port.lock);
}
}
#endif /* CONFIG_SERIAL_8250_RSA */
/*
* This is a quickie test to see how big the FIFO is.
* It doesn't work at all the time, more's the pity.
*/
static int size_fifo(struct uart_8250_port *up)
{
unsigned char old_fcr, old_mcr, old_lcr;
u32 old_dl;
int count;
old_lcr = serial_in(up, UART_LCR);
serial_out(up, UART_LCR, 0);
old_fcr = serial_in(up, UART_FCR);
old_mcr = serial8250_in_MCR(up);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial8250_out_MCR(up, UART_MCR_LOOP);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
old_dl = serial_dl_read(up);
serial_dl_write(up, 0x0001);
serial_out(up, UART_LCR, UART_LCR_WLEN8);
for (count = 0; count < 256; count++)
serial_out(up, UART_TX, count);
mdelay(20);/* FIXME - schedule_timeout */
for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
(count < 256); count++)
serial_in(up, UART_RX);
serial_out(up, UART_FCR, old_fcr);
serial8250_out_MCR(up, old_mcr);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_dl_write(up, old_dl);
serial_out(up, UART_LCR, old_lcr);
return count;
}
/*
* Read UART ID using the divisor method - set DLL and DLM to zero
* and the revision will be in DLL and device type in DLM. We
* preserve the device state across this.
*/
static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
{
unsigned char old_lcr;
unsigned int id, old_dl;
old_lcr = serial_in(p, UART_LCR);
serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
old_dl = serial_dl_read(p);
serial_dl_write(p, 0);
id = serial_dl_read(p);
serial_dl_write(p, old_dl);
serial_out(p, UART_LCR, old_lcr);
return id;
}
/*
* This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
* When this function is called we know it is at least a StarTech
* 16650 V2, but it might be one of several StarTech UARTs, or one of
* its clones. (We treat the broken original StarTech 16650 V1 as a
* 16550, and why not? Startech doesn't seem to even acknowledge its
* existence.)
*
* What evil have men's minds wrought...
*/
static void autoconfig_has_efr(struct uart_8250_port *up)
{
unsigned int id1, id2, id3, rev;
/*
* Everything with an EFR has SLEEP
*/
up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
/*
* First we check to see if it's an Oxford Semiconductor UART.
*
* If we have to do this here because some non-National
* Semiconductor clone chips lock up if you try writing to the
* LSR register (which serial_icr_read does)
*/
/*
* Check for Oxford Semiconductor 16C950.
*
* EFR [4] must be set else this test fails.
*
* This shouldn't be necessary, but Mike Hudson ([email protected])
* claims that it's needed for 952 dual UART's (which are not
* recommended for new designs).
*/
up->acr = 0;
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, UART_EFR_ECB);
serial_out(up, UART_LCR, 0x00);
id1 = serial_icr_read(up, UART_ID1);
id2 = serial_icr_read(up, UART_ID2);
id3 = serial_icr_read(up, UART_ID3);
rev = serial_icr_read(up, UART_REV);
DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
if (id1 == 0x16 && id2 == 0xC9 &&
(id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
up->port.type = PORT_16C950;
/*
* Enable work around for the Oxford Semiconductor 952 rev B
* chip which causes it to seriously miscalculate baud rates
* when DLL is 0.
*/
if (id3 == 0x52 && rev == 0x01)
up->bugs |= UART_BUG_QUOT;
return;
}
/*
* We check for a XR16C850 by setting DLL and DLM to 0, and then
* reading back DLL and DLM. The chip type depends on the DLM
* value read back:
* 0x10 - XR16C850 and the DLL contains the chip revision.
* 0x12 - XR16C2850.
* 0x14 - XR16C854.
*/
id1 = autoconfig_read_divisor_id(up);
DEBUG_AUTOCONF("850id=%04x ", id1);
id2 = id1 >> 8;
if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
up->port.type = PORT_16850;
return;
}
/*
* It wasn't an XR16C850.
*
* We distinguish between the '654 and the '650 by counting
* how many bytes are in the FIFO. I'm using this for now,
* since that's the technique that was sent to me in the
* serial driver update, but I'm not convinced this works.
* I've had problems doing this in the past. -TYT
*/
if (size_fifo(up) == 64)
up->port.type = PORT_16654;
else
up->port.type = PORT_16650V2;
}
/*
* We detected a chip without a FIFO. Only two fall into
* this category - the original 8250 and the 16450. The
* 16450 has a scratch register (accessible with LCR=0)
*/
static void autoconfig_8250(struct uart_8250_port *up)
{
unsigned char scratch, status1, status2;
up->port.type = PORT_8250;
scratch = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, 0xa5);
status1 = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, 0x5a);
status2 = serial_in(up, UART_SCR);
serial_out(up, UART_SCR, scratch);
if (status1 == 0xa5 && status2 == 0x5a)
up->port.type = PORT_16450;
}
static int broken_efr(struct uart_8250_port *up)
{
/*
* Exar ST16C2550 "A2" devices incorrectly detect as
* having an EFR, and report an ID of 0x0201. See
* http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
*/
if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
return 1;
return 0;
}
/*
* We know that the chip has FIFOs. Does it have an EFR? The
* EFR is located in the same register position as the IIR and
* we know the top two bits of the IIR are currently set. The
* EFR should contain zero. Try to read the EFR.
*/
static void autoconfig_16550a(struct uart_8250_port *up)
{
unsigned char status1, status2;
unsigned int iersave;
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&up->port.lock);
up->port.type = PORT_16550A;
up->capabilities |= UART_CAP_FIFO;
if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
!(up->port.flags & UPF_FULL_PROBE))
return;
/*
* Check for presence of the EFR when DLAB is set.
* Only ST16C650V1 UARTs pass this test.
*/
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
if (serial_in(up, UART_EFR) == 0) {
serial_out(up, UART_EFR, 0xA8);
if (serial_in(up, UART_EFR) != 0) {
DEBUG_AUTOCONF("EFRv1 ");
up->port.type = PORT_16650;
up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
} else {
serial_out(up, UART_LCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
UART_FCR7_64BYTE);
status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
UART_IIR_FIFO_ENABLED);
serial_out(up, UART_FCR, 0);
serial_out(up, UART_LCR, 0);
if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
up->port.type = PORT_16550A_FSL64;
else
DEBUG_AUTOCONF("Motorola 8xxx DUART ");
}
serial_out(up, UART_EFR, 0);
return;
}
/*
* Maybe it requires 0xbf to be written to the LCR.
* (other ST16C650V2 UARTs, TI16C752A, etc)
*/
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
DEBUG_AUTOCONF("EFRv2 ");
autoconfig_has_efr(up);
return;
}
/*
* Check for a National Semiconductor SuperIO chip.
* Attempt to switch to bank 2, read the value of the LOOP bit
* from EXCR1. Switch back to bank 0, change it in MCR. Then
* switch back to bank 2, read it from EXCR1 again and check
* it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
*/
serial_out(up, UART_LCR, 0);
status1 = serial8250_in_MCR(up);
serial_out(up, UART_LCR, 0xE0);
status2 = serial_in(up, 0x02); /* EXCR1 */
if (!((status2 ^ status1) & UART_MCR_LOOP)) {
serial_out(up, UART_LCR, 0);
serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
serial_out(up, UART_LCR, 0xE0);
status2 = serial_in(up, 0x02); /* EXCR1 */
serial_out(up, UART_LCR, 0);
serial8250_out_MCR(up, status1);
if ((status2 ^ status1) & UART_MCR_LOOP) {
unsigned short quot;
serial_out(up, UART_LCR, 0xE0);
quot = serial_dl_read(up);
quot <<= 3;
if (ns16550a_goto_highspeed(up))
serial_dl_write(up, quot);
serial_out(up, UART_LCR, 0);
up->port.uartclk = 921600*16;
up->port.type = PORT_NS16550A;
up->capabilities |= UART_NATSEMI;
return;
}
}
/*
* No EFR. Try to detect a TI16750, which only sets bit 5 of
* the IIR when 64 byte FIFO mode is enabled when DLAB is set.
* Try setting it with and without DLAB set. Cheap clones
* set bit 5 without DLAB set.
*/
serial_out(up, UART_LCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_out(up, UART_LCR, 0);
DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
up->port.type = PORT_16750;
up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
return;
}
/*
* Try writing and reading the UART_IER_UUE bit (b6).
* If it works, this is probably one of the Xscale platform's
* internal UARTs.
* We're going to explicitly set the UUE bit to 0 before
* trying to write and read a 1 just to make sure it's not
* already a 1 and maybe locked there before we even start.
*/
iersave = serial_in(up, UART_IER);
serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
/*
* OK it's in a known zero state, try writing and reading
* without disturbing the current state of the other bits.
*/
serial_out(up, UART_IER, iersave | UART_IER_UUE);
if (serial_in(up, UART_IER) & UART_IER_UUE) {
/*
* It's an Xscale.
* We'll leave the UART_IER_UUE bit set to 1 (enabled).
*/
DEBUG_AUTOCONF("Xscale ");
up->port.type = PORT_XSCALE;
up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
return;
}
} else {
/*
* If we got here we couldn't force the IER_UUE bit to 0.
* Log it and continue.
*/
DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
}
serial_out(up, UART_IER, iersave);
/*
* We distinguish between 16550A and U6 16550A by counting
* how many bytes are in the FIFO.
*/
if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
up->port.type = PORT_U6_16550A;
up->capabilities |= UART_CAP_AFE;
}
}
/*
* This routine is called by rs_init() to initialize a specific serial
* port. It determines what type of UART chip this serial port is
* using: 8250, 16450, 16550, 16550A. The important question is
* whether or not this UART is a 16550A or not, since this will
* determine whether or not we can use its FIFO features or not.
*/
static void autoconfig(struct uart_8250_port *up)
{
unsigned char status1, scratch, scratch2, scratch3;
unsigned char save_lcr, save_mcr;
struct uart_port *port = &up->port;
unsigned long flags;
unsigned int old_capabilities;
if (!port->iobase && !port->mapbase && !port->membase)
return;
DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
port->name, port->iobase, port->membase);
/*
* We really do need global IRQs disabled here - we're going to
* be frobbing the chips IRQ enable register to see if it exists.
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
up->capabilities = 0;
up->bugs = 0;
if (!(port->flags & UPF_BUGGY_UART)) {
/*
* Do a simple existence test first; if we fail this,
* there's no point trying anything else.
*
* 0x80 is used as a nonsense port to prevent against
* false positives due to ISA bus float. The
* assumption is that 0x80 is a non-existent port;
* which should be safe since include/asm/io.h also
* makes this assumption.
*
* Note: this is safe as long as MCR bit 4 is clear
* and the device is in "PC" mode.
*/
scratch = serial_in(up, UART_IER);
serial_out(up, UART_IER, 0);
#ifdef __i386__
outb(0xff, 0x080);
#endif
/*
* Mask out IER[7:4] bits for test as some UARTs (e.g. TL
* 16C754B) allow only to modify them if an EFR bit is set.
*/
scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
serial_out(up, UART_IER, UART_IER_ALL_INTR);
#ifdef __i386__
outb(0, 0x080);
#endif
scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
serial_out(up, UART_IER, scratch);
if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
/*
* We failed; there's nothing here
*/
spin_unlock_irqrestore(&port->lock, flags);
DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
scratch2, scratch3);
goto out;
}
}
save_mcr = serial8250_in_MCR(up);
save_lcr = serial_in(up, UART_LCR);
/*
* Check to see if a UART is really there. Certain broken
* internal modems based on the Rockwell chipset fail this
* test, because they apparently don't implement the loopback
* test mode. So this test is skipped on the COM 1 through
* COM 4 ports. This *should* be safe, since no board
* manufacturer would be stupid enough to design a board
* that conflicts with COM 1-4 --- we hope!
*/
if (!(port->flags & UPF_SKIP_TEST)) {
serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
serial8250_out_MCR(up, save_mcr);
if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
spin_unlock_irqrestore(&port->lock, flags);
DEBUG_AUTOCONF("LOOP test failed (%02x) ",
status1);
goto out;
}
}
/*
* We're pretty sure there's a port here. Lets find out what
* type of port it is. The IIR top two bits allows us to find
* out if it's 8250 or 16450, 16550, 16550A or later. This
* determines what we test for next.
*
* We also initialise the EFR (if any) to zero for later. The
* EFR occupies the same register location as the FCR and IIR.
*/
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, 0);
serial_out(up, UART_LCR, 0);
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
case UART_IIR_FIFO_ENABLED_8250:
autoconfig_8250(up);
break;
case UART_IIR_FIFO_ENABLED_16550:
port->type = PORT_16550;
break;
case UART_IIR_FIFO_ENABLED_16550A:
autoconfig_16550a(up);
break;
default:
port->type = PORT_UNKNOWN;
break;
}
#ifdef CONFIG_SERIAL_8250_RSA
/*
* Only probe for RSA ports if we got the region.
*/
if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
__enable_rsa(up))
port->type = PORT_RSA;
#endif
serial_out(up, UART_LCR, save_lcr);
port->fifosize = uart_config[up->port.type].fifo_size;
old_capabilities = up->capabilities;
up->capabilities = uart_config[port->type].flags;
up->tx_loadsz = uart_config[port->type].tx_loadsz;
if (port->type == PORT_UNKNOWN)
goto out_unlock;
/*
* Reset the UART.
*/
#ifdef CONFIG_SERIAL_8250_RSA
if (port->type == PORT_RSA)
serial_out(up, UART_RSA_FRR, 0);
#endif
serial8250_out_MCR(up, save_mcr);
serial8250_clear_fifos(up);
serial_in(up, UART_RX);
serial8250_clear_IER(up);
out_unlock:
spin_unlock_irqrestore(&port->lock, flags);
/*
* Check if the device is a Fintek F81216A
*/
if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
fintek_8250_probe(up);
if (up->capabilities != old_capabilities) {
dev_warn(port->dev, "detected caps %08x should be %08x\n",
old_capabilities, up->capabilities);
}
out:
DEBUG_AUTOCONF("iir=%d ", scratch);
DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
}
static void autoconfig_irq(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
unsigned char save_mcr, save_ier;
unsigned char save_ICP = 0;
unsigned int ICP = 0;
unsigned long irqs;
int irq;
if (port->flags & UPF_FOURPORT) {
ICP = (port->iobase & 0xfe0) | 0x1f;
save_ICP = inb_p(ICP);
outb_p(0x80, ICP);
inb_p(ICP);
}
if (uart_console(port))
console_lock();
/* forget possible initially masked and pending IRQ */
probe_irq_off(probe_irq_on());
save_mcr = serial8250_in_MCR(up);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
save_ier = serial_in(up, UART_IER);
spin_unlock_irq(&port->lock);
serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
irqs = probe_irq_on();
serial8250_out_MCR(up, 0);
udelay(10);
if (port->flags & UPF_FOURPORT) {
serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
} else {
serial8250_out_MCR(up,
UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
}
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
serial_out(up, UART_IER, UART_IER_ALL_INTR);
spin_unlock_irq(&port->lock);
serial_in(up, UART_LSR);
serial_in(up, UART_RX);
serial_in(up, UART_IIR);
serial_in(up, UART_MSR);
serial_out(up, UART_TX, 0xFF);
udelay(20);
irq = probe_irq_off(irqs);
serial8250_out_MCR(up, save_mcr);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
serial_out(up, UART_IER, save_ier);
spin_unlock_irq(&port->lock);
if (port->flags & UPF_FOURPORT)
outb_p(save_ICP, ICP);
if (uart_console(port))
console_unlock();
port->irq = (irq > 0) ? irq : 0;
}
static void serial8250_stop_rx(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&port->lock);
serial8250_rpm_get(up);
up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
up->port.read_status_mask &= ~UART_LSR_DR;
serial_port_out(port, UART_IER, up->ier);
serial8250_rpm_put(up);
}
/**
* serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
* @p: uart 8250 port
*
* Generic callback usable by 8250 uart drivers to stop rs485 transmission.
*/
void serial8250_em485_stop_tx(struct uart_8250_port *p)
{
unsigned char mcr = serial8250_in_MCR(p);
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&p->port.lock);
if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
mcr |= UART_MCR_RTS;
else
mcr &= ~UART_MCR_RTS;
serial8250_out_MCR(p, mcr);
/*
* Empty the RX FIFO, we are not interested in anything
* received during the half-duplex transmission.
* Enable previously disabled RX interrupts.
*/
if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
serial8250_clear_and_reinit_fifos(p);
p->ier |= UART_IER_RLSI | UART_IER_RDI;
serial_port_out(&p->port, UART_IER, p->ier);
}
}
EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
{
struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
stop_tx_timer);
struct uart_8250_port *p = em485->port;
unsigned long flags;
serial8250_rpm_get(p);
spin_lock_irqsave(&p->port.lock, flags);
if (em485->active_timer == &em485->stop_tx_timer) {
p->rs485_stop_tx(p);
em485->active_timer = NULL;
em485->tx_stopped = true;
}
spin_unlock_irqrestore(&p->port.lock, flags);
serial8250_rpm_put(p);
return HRTIMER_NORESTART;
}
static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
{
hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
}
static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
{
struct uart_8250_em485 *em485 = p->em485;
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&p->port.lock);
stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
/*
* rs485_stop_tx() is going to set RTS according to config
* AND flush RX FIFO if required.
*/
if (stop_delay > 0) {
em485->active_timer = &em485->stop_tx_timer;
hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
} else {
p->rs485_stop_tx(p);
em485->active_timer = NULL;
em485->tx_stopped = true;
}
}
static inline void __stop_tx(struct uart_8250_port *p)
{
struct uart_8250_em485 *em485 = p->em485;
if (em485) {
u16 lsr = serial_lsr_in(p);
u64 stop_delay = 0;
if (!(lsr & UART_LSR_THRE))
return;
/*
* To provide required timing and allow FIFO transfer,
* __stop_tx_rs485() must be called only when both FIFO and
* shift register are empty. The device driver should either
* enable interrupt on TEMT or set UART_CAP_NOTEMT that will
* enlarge stop_tx_timer by the tx time of one frame to cover
* for emptying of the shift register.
*/
if (!(lsr & UART_LSR_TEMT)) {
if (!(p->capabilities & UART_CAP_NOTEMT))
return;
/*
* RTS might get deasserted too early with the normal
* frame timing formula. It seems to suggest THRE might
* get asserted already during tx of the stop bit
* rather than after it is fully sent.
* Roughly estimate 1 extra bit here with / 7.
*/
stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
}
__stop_tx_rs485(p, stop_delay);
}
if (serial8250_clear_THRI(p))
serial8250_rpm_put_tx(p);
}
static void serial8250_stop_tx(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
serial8250_rpm_get(up);
__stop_tx(up);
/*
* We really want to stop the transmitter from sending.
*/
if (port->type == PORT_16C950) {
up->acr |= UART_ACR_TXDIS;
serial_icr_write(up, UART_ACR, up->acr);
}
serial8250_rpm_put(up);
}
static inline void __start_tx(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
if (up->dma && !up->dma->tx_dma(up))
return;
if (serial8250_set_THRI(up)) {
if (up->bugs & UART_BUG_TXEN) {
u16 lsr = serial_lsr_in(up);
if (lsr & UART_LSR_THRE)
serial8250_tx_chars(up);
}
}
/*
* Re-enable the transmitter if we disabled it.
*/
if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
up->acr &= ~UART_ACR_TXDIS;
serial_icr_write(up, UART_ACR, up->acr);
}
}
/**
* serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
* @up: uart 8250 port
*
* Generic callback usable by 8250 uart drivers to start rs485 transmission.
* Assumes that setting the RTS bit in the MCR register means RTS is high.
* (Some chips use inverse semantics.) Further assumes that reception is
* stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
* UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
*/
void serial8250_em485_start_tx(struct uart_8250_port *up)
{
unsigned char mcr = serial8250_in_MCR(up);
if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
serial8250_stop_rx(&up->port);
if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
mcr |= UART_MCR_RTS;
else
mcr &= ~UART_MCR_RTS;
serial8250_out_MCR(up, mcr);
}
EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
/* Returns false, if start_tx_timer was setup to defer TX start */
static bool start_tx_rs485(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct uart_8250_em485 *em485 = up->em485;
/*
* While serial8250_em485_handle_stop_tx() is a noop if
* em485->active_timer != &em485->stop_tx_timer, it might happen that
* the timer is still armed and triggers only after the current bunch of
* chars is send and em485->active_timer == &em485->stop_tx_timer again.
* So cancel the timer. There is still a theoretical race condition if
* the timer is already running and only comes around to check for
* em485->active_timer when &em485->stop_tx_timer is armed again.
*/
if (em485->active_timer == &em485->stop_tx_timer)
hrtimer_try_to_cancel(&em485->stop_tx_timer);
em485->active_timer = NULL;
if (em485->tx_stopped) {
em485->tx_stopped = false;
up->rs485_start_tx(up);
if (up->port.rs485.delay_rts_before_send > 0) {
em485->active_timer = &em485->start_tx_timer;
start_hrtimer_ms(&em485->start_tx_timer,
up->port.rs485.delay_rts_before_send);
return false;
}
}
return true;
}
static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
{
struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
start_tx_timer);
struct uart_8250_port *p = em485->port;
unsigned long flags;
spin_lock_irqsave(&p->port.lock, flags);
if (em485->active_timer == &em485->start_tx_timer) {
__start_tx(&p->port);
em485->active_timer = NULL;
}
spin_unlock_irqrestore(&p->port.lock, flags);
return HRTIMER_NORESTART;
}
static void serial8250_start_tx(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct uart_8250_em485 *em485 = up->em485;
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&port->lock);
if (!port->x_char && uart_circ_empty(&port->state->xmit))
return;
serial8250_rpm_get_tx(up);
if (em485) {
if ((em485->active_timer == &em485->start_tx_timer) ||
!start_tx_rs485(port))
return;
}
__start_tx(port);
}
static void serial8250_throttle(struct uart_port *port)
{
port->throttle(port);
}
static void serial8250_unthrottle(struct uart_port *port)
{
port->unthrottle(port);
}
static void serial8250_disable_ms(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&port->lock);
/* no MSR capabilities */
if (up->bugs & UART_BUG_NOMSR)
return;
mctrl_gpio_disable_ms(up->gpios);
up->ier &= ~UART_IER_MSI;
serial_port_out(port, UART_IER, up->ier);
}
static void serial8250_enable_ms(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&port->lock);
/* no MSR capabilities */
if (up->bugs & UART_BUG_NOMSR)
return;
mctrl_gpio_enable_ms(up->gpios);
up->ier |= UART_IER_MSI;
serial8250_rpm_get(up);
serial_port_out(port, UART_IER, up->ier);
serial8250_rpm_put(up);
}
void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
{
struct uart_port *port = &up->port;
u8 ch, flag = TTY_NORMAL;
if (likely(lsr & UART_LSR_DR))
ch = serial_in(up, UART_RX);
else
/*
* Intel 82571 has a Serial Over Lan device that will
* set UART_LSR_BI without setting UART_LSR_DR when
* it receives a break. To avoid reading from the
* receive buffer without UART_LSR_DR bit set, we
* just force the read character to be 0
*/
ch = 0;
port->icount.rx++;
lsr |= up->lsr_saved_flags;
up->lsr_saved_flags = 0;
if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
if (lsr & UART_LSR_BI) {
lsr &= ~(UART_LSR_FE | UART_LSR_PE);
port->icount.brk++;
/*
* We do the SysRQ and SAK checking
* here because otherwise the break
* may get masked by ignore_status_mask
* or read_status_mask.
*/
if (uart_handle_break(port))
return;
} else if (lsr & UART_LSR_PE)
port->icount.parity++;
else if (lsr & UART_LSR_FE)
port->icount.frame++;
if (lsr & UART_LSR_OE)
port->icount.overrun++;
/*
* Mask off conditions which should be ignored.
*/
lsr &= port->read_status_mask;
if (lsr & UART_LSR_BI) {
dev_dbg(port->dev, "handling break\n");
flag = TTY_BREAK;
} else if (lsr & UART_LSR_PE)
flag = TTY_PARITY;
else if (lsr & UART_LSR_FE)
flag = TTY_FRAME;
}
if (uart_prepare_sysrq_char(port, ch))
return;
uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
}
EXPORT_SYMBOL_GPL(serial8250_read_char);
/*
* serial8250_rx_chars - Read characters. The first LSR value must be passed in.
*
* Returns LSR bits. The caller should rely only on non-Rx related LSR bits
* (such as THRE) because the LSR value might come from an already consumed
* character.
*/
u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
{
struct uart_port *port = &up->port;
int max_count = 256;
do {
serial8250_read_char(up, lsr);
if (--max_count == 0)
break;
lsr = serial_in(up, UART_LSR);
} while (lsr & (UART_LSR_DR | UART_LSR_BI));
tty_flip_buffer_push(&port->state->port);
return lsr;
}
EXPORT_SYMBOL_GPL(serial8250_rx_chars);
void serial8250_tx_chars(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
struct circ_buf *xmit = &port->state->xmit;
int count;
if (port->x_char) {
uart_xchar_out(port, UART_TX);
return;
}
if (uart_tx_stopped(port)) {
serial8250_stop_tx(port);
return;
}
if (uart_circ_empty(xmit)) {
__stop_tx(up);
return;
}
count = up->tx_loadsz;
do {
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
if (up->bugs & UART_BUG_TXRACE) {
/*
* The Aspeed BMC virtual UARTs have a bug where data
* may get stuck in the BMC's Tx FIFO from bursts of
* writes on the APB interface.
*
* Delay back-to-back writes by a read cycle to avoid
* stalling the VUART. Read a register that won't have
* side-effects and discard the result.
*/
serial_in(up, UART_SCR);
}
uart_xmit_advance(port, 1);
if (uart_circ_empty(xmit))
break;
if ((up->capabilities & UART_CAP_HFIFO) &&
!uart_lsr_tx_empty(serial_in(up, UART_LSR)))
break;
/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
if ((up->capabilities & UART_CAP_MINI) &&
!(serial_in(up, UART_LSR) & UART_LSR_THRE))
break;
} while (--count > 0);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
/*
* With RPM enabled, we have to wait until the FIFO is empty before the
* HW can go idle. So we get here once again with empty FIFO and disable
* the interrupt and RPM in __stop_tx()
*/
if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
__stop_tx(up);
}
EXPORT_SYMBOL_GPL(serial8250_tx_chars);
/* Caller holds uart port lock */
unsigned int serial8250_modem_status(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
unsigned int status = serial_in(up, UART_MSR);
status |= up->msr_saved_flags;
up->msr_saved_flags = 0;
if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
port->state != NULL) {
if (status & UART_MSR_TERI)
port->icount.rng++;
if (status & UART_MSR_DDSR)
port->icount.dsr++;
if (status & UART_MSR_DDCD)
uart_handle_dcd_change(port, status & UART_MSR_DCD);
if (status & UART_MSR_DCTS)
uart_handle_cts_change(port, status & UART_MSR_CTS);
wake_up_interruptible(&port->state->port.delta_msr_wait);
}
return status;
}
EXPORT_SYMBOL_GPL(serial8250_modem_status);
static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
{
switch (iir & 0x3f) {
case UART_IIR_THRI:
/*
* Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
* because it's impossible to do an informed decision about
* that with IIR_THRI.
*
* This also fixes one known DMA Rx corruption issue where
* DR is asserted but DMA Rx only gets a corrupted zero byte
* (too early DR?).
*/
return false;
case UART_IIR_RDI:
if (!up->dma->rx_running)
break;
fallthrough;
case UART_IIR_RLSI:
case UART_IIR_RX_TIMEOUT:
serial8250_rx_dma_flush(up);
return true;
}
return up->dma->rx_dma(up);
}
/*
* This handles the interrupt from one port.
*/
int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct tty_port *tport = &port->state->port;
bool skip_rx = false;
unsigned long flags;
u16 status;
if (iir & UART_IIR_NO_INT)
return 0;
spin_lock_irqsave(&port->lock, flags);
status = serial_lsr_in(up);
/*
* If port is stopped and there are no error conditions in the
* FIFO, then don't drain the FIFO, as this may lead to TTY buffer
* overflow. Not servicing, RX FIFO would trigger auto HW flow
* control when FIFO occupancy reaches preset threshold, thus
* halting RX. This only works when auto HW flow control is
* available.
*/
if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
(port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
!(port->read_status_mask & UART_LSR_DR))
skip_rx = true;
if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
pm_wakeup_event(tport->tty->dev, 0);
if (!up->dma || handle_rx_dma(up, iir))
status = serial8250_rx_chars(up, status);
}
serial8250_modem_status(up);
if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
if (!up->dma || up->dma->tx_err)
serial8250_tx_chars(up);
else if (!up->dma->tx_running)
__stop_tx(up);
}
uart_unlock_and_check_sysrq_irqrestore(port, flags);
return 1;
}
EXPORT_SYMBOL_GPL(serial8250_handle_irq);
static int serial8250_default_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned int iir;
int ret;
serial8250_rpm_get(up);
iir = serial_port_in(port, UART_IIR);
ret = serial8250_handle_irq(port, iir);
serial8250_rpm_put(up);
return ret;
}
/*
* Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
* have a programmable TX threshold that triggers the THRE interrupt in
* the IIR register. In this case, the THRE interrupt indicates the FIFO
* has space available. Load it up with tx_loadsz bytes.
*/
static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
{
unsigned long flags;
unsigned int iir = serial_port_in(port, UART_IIR);
/* TX Threshold IRQ triggered so load up FIFO */
if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
struct uart_8250_port *up = up_to_u8250p(port);
spin_lock_irqsave(&port->lock, flags);
serial8250_tx_chars(up);
spin_unlock_irqrestore(&port->lock, flags);
}
iir = serial_port_in(port, UART_IIR);
return serial8250_handle_irq(port, iir);
}
static unsigned int serial8250_tx_empty(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned int result = 0;
unsigned long flags;
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
result = TIOCSER_TEMT;
spin_unlock_irqrestore(&port->lock, flags);
serial8250_rpm_put(up);
return result;
}
unsigned int serial8250_do_get_mctrl(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned int status;
unsigned int val;
serial8250_rpm_get(up);
status = serial8250_modem_status(up);
serial8250_rpm_put(up);
val = serial8250_MSR_to_TIOCM(status);
if (up->gpios)
return mctrl_gpio_get(up->gpios, &val);
return val;
}
EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
static unsigned int serial8250_get_mctrl(struct uart_port *port)
{
if (port->get_mctrl)
return port->get_mctrl(port);
return serial8250_do_get_mctrl(port);
}
void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned char mcr;
mcr = serial8250_TIOCM_to_MCR(mctrl);
mcr |= up->mcr;
serial8250_out_MCR(up, mcr);
}
EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
if (port->rs485.flags & SER_RS485_ENABLED)
return;
if (port->set_mctrl)
port->set_mctrl(port, mctrl);
else
serial8250_do_set_mctrl(port, mctrl);
}
static void serial8250_break_ctl(struct uart_port *port, int break_state)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
if (break_state == -1)
up->lcr |= UART_LCR_SBC;
else
up->lcr &= ~UART_LCR_SBC;
serial_port_out(port, UART_LCR, up->lcr);
spin_unlock_irqrestore(&port->lock, flags);
serial8250_rpm_put(up);
}
static void wait_for_lsr(struct uart_8250_port *up, int bits)
{
unsigned int status, tmout = 10000;
/* Wait up to 10ms for the character(s) to be sent. */
for (;;) {
status = serial_lsr_in(up);
if ((status & bits) == bits)
break;
if (--tmout == 0)
break;
udelay(1);
touch_nmi_watchdog();
}
}
/*
* Wait for transmitter & holding register to empty
*/
static void wait_for_xmitr(struct uart_8250_port *up, int bits)
{
unsigned int tmout;
wait_for_lsr(up, bits);
/* Wait up to 1s for flow control if necessary */
if (up->port.flags & UPF_CONS_FLOW) {
for (tmout = 1000000; tmout; tmout--) {
unsigned int msr = serial_in(up, UART_MSR);
up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
if (msr & UART_MSR_CTS)
break;
udelay(1);
touch_nmi_watchdog();
}
}
}
#ifdef CONFIG_CONSOLE_POLL
/*
* Console polling routines for writing and reading from the uart while
* in an interrupt or debug context.
*/
static int serial8250_get_poll_char(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
int status;
u16 lsr;
serial8250_rpm_get(up);
lsr = serial_port_in(port, UART_LSR);
if (!(lsr & UART_LSR_DR)) {
status = NO_POLL_CHAR;
goto out;
}
status = serial_port_in(port, UART_RX);
out:
serial8250_rpm_put(up);
return status;
}
static void serial8250_put_poll_char(struct uart_port *port,
unsigned char c)
{
unsigned int ier;
struct uart_8250_port *up = up_to_u8250p(port);
/*
* Normally the port is locked to synchronize UART_IER access
* against the console. However, this function is only used by
* KDB/KGDB, where it may not be possible to acquire the port
* lock because all other CPUs are quiesced. The quiescence
* should allow safe lockless usage here.
*/
serial8250_rpm_get(up);
/*
* First save the IER then disable the interrupts
*/
ier = serial_port_in(port, UART_IER);
serial8250_clear_IER(up);
wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
/*
* Send the character out.
*/
serial_port_out(port, UART_TX, c);
/*
* Finally, wait for transmitter to become empty
* and restore the IER
*/
wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
serial_port_out(port, UART_IER, ier);
serial8250_rpm_put(up);
}
#endif /* CONFIG_CONSOLE_POLL */
int serial8250_do_startup(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
unsigned char iir;
int retval;
u16 lsr;
if (!port->fifosize)
port->fifosize = uart_config[port->type].fifo_size;
if (!up->tx_loadsz)
up->tx_loadsz = uart_config[port->type].tx_loadsz;
if (!up->capabilities)
up->capabilities = uart_config[port->type].flags;
up->mcr = 0;
if (port->iotype != up->cur_iotype)
set_io_from_upio(port);
serial8250_rpm_get(up);
if (port->type == PORT_16C950) {
/*
* Wake up and initialize UART
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
up->acr = 0;
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
serial_port_out(port, UART_EFR, UART_EFR_ECB);
serial_port_out(port, UART_IER, 0);
serial_port_out(port, UART_LCR, 0);
serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
serial_port_out(port, UART_EFR, UART_EFR_ECB);
serial_port_out(port, UART_LCR, 0);
spin_unlock_irqrestore(&port->lock, flags);
}
if (port->type == PORT_DA830) {
/*
* Reset the port
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
serial_port_out(port, UART_IER, 0);
serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
spin_unlock_irqrestore(&port->lock, flags);
mdelay(10);
/* Enable Tx, Rx and free run mode */
serial_port_out(port, UART_DA830_PWREMU_MGMT,
UART_DA830_PWREMU_MGMT_UTRST |
UART_DA830_PWREMU_MGMT_URRST |
UART_DA830_PWREMU_MGMT_FREE);
}
if (port->type == PORT_NPCM) {
/*
* Nuvoton calls the scratch register 'UART_TOR' (timeout
* register). Enable it, and set TIOC (timeout interrupt
* comparator) to be 0x20 for correct operation.
*/
serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
}
#ifdef CONFIG_SERIAL_8250_RSA
/*
* If this is an RSA port, see if we can kick it up to the
* higher speed clock.
*/
enable_rsa(up);
#endif
/*
* Clear the FIFO buffers and disable them.
* (they will be reenabled in set_termios())
*/
serial8250_clear_fifos(up);
/*
* Clear the interrupt registers.
*/
serial_port_in(port, UART_LSR);
serial_port_in(port, UART_RX);
serial_port_in(port, UART_IIR);
serial_port_in(port, UART_MSR);
/*
* At this point, there's no way the LSR could still be 0xff;
* if it is, then bail out, because there's likely no UART
* here.
*/
if (!(port->flags & UPF_BUGGY_UART) &&
(serial_port_in(port, UART_LSR) == 0xff)) {
dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
retval = -ENODEV;
goto out;
}
/*
* For a XR16C850, we need to set the trigger levels
*/
if (port->type == PORT_16850) {
unsigned char fctr;
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
serial_port_out(port, UART_FCTR,
fctr | UART_FCTR_TRGD | UART_FCTR_RX);
serial_port_out(port, UART_TRG, UART_TRG_96);
serial_port_out(port, UART_FCTR,
fctr | UART_FCTR_TRGD | UART_FCTR_TX);
serial_port_out(port, UART_TRG, UART_TRG_96);
serial_port_out(port, UART_LCR, 0);
}
/*
* For the Altera 16550 variants, set TX threshold trigger level.
*/
if (((port->type == PORT_ALTR_16550_F32) ||
(port->type == PORT_ALTR_16550_F64) ||
(port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
} else {
serial_port_out(port, UART_ALTR_AFR,
UART_ALTR_EN_TXFIFO_LW);
serial_port_out(port, UART_ALTR_TX_LOW,
port->fifosize - up->tx_loadsz);
port->handle_irq = serial8250_tx_threshold_handle_irq;
}
}
/* Check if we need to have shared IRQs */
if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
up->port.irqflags |= IRQF_SHARED;
retval = up->ops->setup_irq(up);
if (retval)
goto out;
if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
unsigned char iir1;
if (port->irqflags & IRQF_SHARED)
disable_irq_nosync(port->irq);
/*
* Test for UARTs that do not reassert THRE when the
* transmitter is idle and the interrupt has already
* been cleared. Real 16550s should always reassert
* this interrupt whenever the transmitter is idle and
* the interrupt is enabled. Delays are necessary to
* allow register changes to become visible.
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
wait_for_xmitr(up, UART_LSR_THRE);
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
udelay(1); /* allow THRE to set */
iir1 = serial_port_in(port, UART_IIR);
serial_port_out(port, UART_IER, 0);
serial_port_out_sync(port, UART_IER, UART_IER_THRI);
udelay(1); /* allow a working UART time to re-assert THRE */
iir = serial_port_in(port, UART_IIR);
serial_port_out(port, UART_IER, 0);
spin_unlock_irqrestore(&port->lock, flags);
if (port->irqflags & IRQF_SHARED)
enable_irq(port->irq);
/*
* If the interrupt is not reasserted, or we otherwise
* don't trust the iir, setup a timer to kick the UART
* on a regular basis.
*/
if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
up->port.flags & UPF_BUG_THRE) {
up->bugs |= UART_BUG_THRE;
}
}
up->ops->setup_timer(up);
/*
* Now, initialize the UART
*/
serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
spin_lock_irqsave(&port->lock, flags);
if (up->port.flags & UPF_FOURPORT) {
if (!up->port.irq)
up->port.mctrl |= TIOCM_OUT1;
} else
/*
* Most PC uarts need OUT2 raised to enable interrupts.
*/
if (port->irq)
up->port.mctrl |= TIOCM_OUT2;
serial8250_set_mctrl(port, port->mctrl);
/*
* Serial over Lan (SoL) hack:
* Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
* used for Serial Over Lan. Those chips take a longer time than a
* normal serial device to signalize that a transmission data was
* queued. Due to that, the above test generally fails. One solution
* would be to delay the reading of iir. However, this is not
* reliable, since the timeout is variable. So, let's just don't
* test if we receive TX irq. This way, we'll never enable
* UART_BUG_TXEN.
*/
if (up->port.quirks & UPQ_NO_TXEN_TEST)
goto dont_test_tx_en;
/*
* Do a quick test to see if we receive an interrupt when we enable
* the TX irq.
*/
serial_port_out(port, UART_IER, UART_IER_THRI);
lsr = serial_port_in(port, UART_LSR);
iir = serial_port_in(port, UART_IIR);
serial_port_out(port, UART_IER, 0);
if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
if (!(up->bugs & UART_BUG_TXEN)) {
up->bugs |= UART_BUG_TXEN;
dev_dbg(port->dev, "enabling bad tx status workarounds\n");
}
} else {
up->bugs &= ~UART_BUG_TXEN;
}
dont_test_tx_en:
spin_unlock_irqrestore(&port->lock, flags);
/*
* Clear the interrupt registers again for luck, and clear the
* saved flags to avoid getting false values from polling
* routines or the previous session.
*/
serial_port_in(port, UART_LSR);
serial_port_in(port, UART_RX);
serial_port_in(port, UART_IIR);
serial_port_in(port, UART_MSR);
up->lsr_saved_flags = 0;
up->msr_saved_flags = 0;
/*
* Request DMA channels for both RX and TX.
*/
if (up->dma) {
const char *msg = NULL;
if (uart_console(port))
msg = "forbid DMA for kernel console";
else if (serial8250_request_dma(up))
msg = "failed to request DMA";
if (msg) {
dev_warn_ratelimited(port->dev, "%s\n", msg);
up->dma = NULL;
}
}
/*
* Set the IER shadow for rx interrupts but defer actual interrupt
* enable until after the FIFOs are enabled; otherwise, an already-
* active sender can swamp the interrupt handler with "too much work".
*/
up->ier = UART_IER_RLSI | UART_IER_RDI;
if (port->flags & UPF_FOURPORT) {
unsigned int icp;
/*
* Enable interrupts on the AST Fourport board
*/
icp = (port->iobase & 0xfe0) | 0x01f;
outb_p(0x80, icp);
inb_p(icp);
}
retval = 0;
out:
serial8250_rpm_put(up);
return retval;
}
EXPORT_SYMBOL_GPL(serial8250_do_startup);
static int serial8250_startup(struct uart_port *port)
{
if (port->startup)
return port->startup(port);
return serial8250_do_startup(port);
}
void serial8250_do_shutdown(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
serial8250_rpm_get(up);
/*
* Disable interrupts from this port
*
* Synchronize UART_IER access against the console.
*/
spin_lock_irqsave(&port->lock, flags);
up->ier = 0;
serial_port_out(port, UART_IER, 0);
spin_unlock_irqrestore(&port->lock, flags);
synchronize_irq(port->irq);
if (up->dma)
serial8250_release_dma(up);
spin_lock_irqsave(&port->lock, flags);
if (port->flags & UPF_FOURPORT) {
/* reset interrupts on the AST Fourport board */
inb((port->iobase & 0xfe0) | 0x1f);
port->mctrl |= TIOCM_OUT1;
} else
port->mctrl &= ~TIOCM_OUT2;
serial8250_set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
/*
* Disable break condition and FIFOs
*/
serial_port_out(port, UART_LCR,
serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
serial8250_clear_fifos(up);
#ifdef CONFIG_SERIAL_8250_RSA
/*
* Reset the RSA board back to 115kbps compat mode.
*/
disable_rsa(up);
#endif
/*
* Read data port to reset things, and then unlink from
* the IRQ chain.
*/
serial_port_in(port, UART_RX);
serial8250_rpm_put(up);
up->ops->release_irq(up);
}
EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
static void serial8250_shutdown(struct uart_port *port)
{
if (port->shutdown)
port->shutdown(port);
else
serial8250_do_shutdown(port);
}
/* Nuvoton NPCM UARTs have a custom divisor calculation */
static unsigned int npcm_get_divisor(struct uart_8250_port *up,
unsigned int baud)
{
struct uart_port *port = &up->port;
return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
}
static unsigned int serial8250_do_get_divisor(struct uart_port *port,
unsigned int baud,
unsigned int *frac)
{
upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
struct uart_8250_port *up = up_to_u8250p(port);
unsigned int quot;
/*
* Handle magic divisors for baud rates above baud_base on SMSC
* Super I/O chips. We clamp custom rates from clk/6 and clk/12
* up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
* magic divisors actually reprogram the baud rate generator's
* reference clock derived from chips's 14.318MHz clock input.
*
* Documentation claims that with these magic divisors the base
* frequencies of 7.3728MHz and 3.6864MHz are used respectively
* for the extra baud rates of 460800bps and 230400bps rather
* than the usual base frequency of 1.8462MHz. However empirical
* evidence contradicts that.
*
* Instead bit 7 of the DLM register (bit 15 of the divisor) is
* effectively used as a clock prescaler selection bit for the
* base frequency of 7.3728MHz, always used. If set to 0, then
* the base frequency is divided by 4 for use by the Baud Rate
* Generator, for the usual arrangement where the value of 1 of
* the divisor produces the baud rate of 115200bps. Conversely,
* if set to 1 and high-speed operation has been enabled with the
* Serial Port Mode Register in the Device Configuration Space,
* then the base frequency is supplied directly to the Baud Rate
* Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
* 0x8004, etc. the respective baud rates produced are 460800bps,
* 230400bps, 153600bps, 115200bps, etc.
*
* In all cases only low 15 bits of the divisor are used to divide
* the baud base and therefore 32767 is the maximum divisor value
* possible, even though documentation says that the programmable
* Baud Rate Generator is capable of dividing the internal PLL
* clock by any divisor from 1 to 65535.
*/
if (magic_multiplier && baud >= port->uartclk / 6)
quot = 0x8001;
else if (magic_multiplier && baud >= port->uartclk / 12)
quot = 0x8002;
else if (up->port.type == PORT_NPCM)
quot = npcm_get_divisor(up, baud);
else
quot = uart_get_divisor(port, baud);
/*
* Oxford Semi 952 rev B workaround
*/
if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
quot++;
return quot;
}
static unsigned int serial8250_get_divisor(struct uart_port *port,
unsigned int baud,
unsigned int *frac)
{
if (port->get_divisor)
return port->get_divisor(port, baud, frac);
return serial8250_do_get_divisor(port, baud, frac);
}
static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
tcflag_t c_cflag)
{
unsigned char cval;
cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
if (c_cflag & CSTOPB)
cval |= UART_LCR_STOP;
if (c_cflag & PARENB)
cval |= UART_LCR_PARITY;
if (!(c_cflag & PARODD))
cval |= UART_LCR_EPAR;
if (c_cflag & CMSPAR)
cval |= UART_LCR_SPAR;
return cval;
}
void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
unsigned int quot, unsigned int quot_frac)
{
struct uart_8250_port *up = up_to_u8250p(port);
/* Workaround to enable 115200 baud on OMAP1510 internal ports */
if (is_omap1510_8250(up)) {
if (baud == 115200) {
quot = 1;
serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
} else
serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
}
/*
* For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
* otherwise just set DLAB
*/
if (up->capabilities & UART_NATSEMI)
serial_port_out(port, UART_LCR, 0xe0);
else
serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
serial_dl_write(up, quot);
}
EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
unsigned int quot, unsigned int quot_frac)
{
if (port->set_divisor)
port->set_divisor(port, baud, quot, quot_frac);
else
serial8250_do_set_divisor(port, baud, quot, quot_frac);
}
static unsigned int serial8250_get_baud_rate(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
unsigned int tolerance = port->uartclk / 100;
unsigned int min;
unsigned int max;
/*
* Handle magic divisors for baud rates above baud_base on SMSC
* Super I/O chips. Enable custom rates of clk/4 and clk/8, but
* disable divisor values beyond 32767, which are unavailable.
*/
if (port->flags & UPF_MAGIC_MULTIPLIER) {
min = port->uartclk / 16 / UART_DIV_MAX >> 1;
max = (port->uartclk + tolerance) / 4;
} else {
min = port->uartclk / 16 / UART_DIV_MAX;
max = (port->uartclk + tolerance) / 16;
}
/*
* Ask the core to calculate the divisor for us.
* Allow 1% tolerance at the upper limit so uart clks marginally
* slower than nominal still match standard baud rates without
* causing transmission errors.
*/
return uart_get_baud_rate(port, termios, old, min, max);
}
/*
* Note in order to avoid the tty port mutex deadlock don't use the next method
* within the uart port callbacks. Primarily it's supposed to be utilized to
* handle a sudden reference clock rate change.
*/
void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct tty_port *tport = &port->state->port;
unsigned int baud, quot, frac = 0;
struct ktermios *termios;
struct tty_struct *tty;
unsigned long flags;
tty = tty_port_tty_get(tport);
if (!tty) {
mutex_lock(&tport->mutex);
port->uartclk = uartclk;
mutex_unlock(&tport->mutex);
return;
}
down_write(&tty->termios_rwsem);
mutex_lock(&tport->mutex);
if (port->uartclk == uartclk)
goto out_unlock;
port->uartclk = uartclk;
if (!tty_port_initialized(tport))
goto out_unlock;
termios = &tty->termios;
baud = serial8250_get_baud_rate(port, termios, NULL);
quot = serial8250_get_divisor(port, baud, &frac);
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
uart_update_timeout(port, termios->c_cflag, baud);
serial8250_set_divisor(port, baud, quot, frac);
serial_port_out(port, UART_LCR, up->lcr);
spin_unlock_irqrestore(&port->lock, flags);
serial8250_rpm_put(up);
out_unlock:
mutex_unlock(&tport->mutex);
up_write(&tty->termios_rwsem);
tty_kref_put(tty);
}
EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
void
serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned char cval;
unsigned long flags;
unsigned int baud, quot, frac = 0;
if (up->capabilities & UART_CAP_MINI) {
termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
if ((termios->c_cflag & CSIZE) == CS5 ||
(termios->c_cflag & CSIZE) == CS6)
termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
}
cval = serial8250_compute_lcr(up, termios->c_cflag);
baud = serial8250_get_baud_rate(port, termios, old);
quot = serial8250_get_divisor(port, baud, &frac);
/*
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*
* Synchronize UART_IER access against the console.
*/
serial8250_rpm_get(up);
spin_lock_irqsave(&port->lock, flags);
up->lcr = cval; /* Save computed LCR */
if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
if (baud < 2400 && !up->dma) {
up->fcr &= ~UART_FCR_TRIGGER_MASK;
up->fcr |= UART_FCR_TRIGGER_1;
}
}
/*
* MCR-based auto flow control. When AFE is enabled, RTS will be
* deasserted when the receive FIFO contains more characters than
* the trigger, or the MCR RTS bit is cleared.
*/
if (up->capabilities & UART_CAP_AFE) {
up->mcr &= ~UART_MCR_AFE;
if (termios->c_cflag & CRTSCTS)
up->mcr |= UART_MCR_AFE;
}
/*
* Update the per-port timeout.
*/
uart_update_timeout(port, termios->c_cflag, baud);
port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (termios->c_iflag & INPCK)
port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
port->read_status_mask |= UART_LSR_BI;
/*
* Characters to ignore
*/
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
if (termios->c_iflag & IGNBRK) {
port->ignore_status_mask |= UART_LSR_BI;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= UART_LSR_OE;
}
/*
* ignore all characters if CREAD is not set
*/
if ((termios->c_cflag & CREAD) == 0)
port->ignore_status_mask |= UART_LSR_DR;
/*
* CTS flow control flag and modem status interrupts
*/
up->ier &= ~UART_IER_MSI;
if (!(up->bugs & UART_BUG_NOMSR) &&
UART_ENABLE_MS(&up->port, termios->c_cflag))
up->ier |= UART_IER_MSI;
if (up->capabilities & UART_CAP_UUE)
up->ier |= UART_IER_UUE;
if (up->capabilities & UART_CAP_RTOIE)
up->ier |= UART_IER_RTOIE;
serial_port_out(port, UART_IER, up->ier);
if (up->capabilities & UART_CAP_EFR) {
unsigned char efr = 0;
/*
* TI16C752/Startech hardware flow control. FIXME:
* - TI16C752 requires control thresholds to be set.
* - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
*/
if (termios->c_cflag & CRTSCTS)
efr |= UART_EFR_CTS;
serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
if (port->flags & UPF_EXAR_EFR)
serial_port_out(port, UART_XR_EFR, efr);
else
serial_port_out(port, UART_EFR, efr);
}
serial8250_set_divisor(port, baud, quot, frac);
/*
* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
* is written without DLAB set, this mode will be disabled.
*/
if (port->type == PORT_16750)
serial_port_out(port, UART_FCR, up->fcr);
serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
if (port->type != PORT_16750) {
/* emulated UARTs (Lucent Venus 167x) need two steps */
if (up->fcr & UART_FCR_ENABLE_FIFO)
serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
}
serial8250_set_mctrl(port, port->mctrl);
spin_unlock_irqrestore(&port->lock, flags);
serial8250_rpm_put(up);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);
}
EXPORT_SYMBOL(serial8250_do_set_termios);
static void
serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
if (port->set_termios)
port->set_termios(port, termios, old);
else
serial8250_do_set_termios(port, termios, old);
}
void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
{
if (termios->c_line == N_PPS) {
port->flags |= UPF_HARDPPS_CD;
spin_lock_irq(&port->lock);
serial8250_enable_ms(port);
spin_unlock_irq(&port->lock);
} else {
port->flags &= ~UPF_HARDPPS_CD;
if (!UART_ENABLE_MS(port, termios->c_cflag)) {
spin_lock_irq(&port->lock);
serial8250_disable_ms(port);
spin_unlock_irq(&port->lock);
}
}
}
EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
static void
serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
{
if (port->set_ldisc)
port->set_ldisc(port, termios);
else
serial8250_do_set_ldisc(port, termios);
}
void serial8250_do_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
struct uart_8250_port *p = up_to_u8250p(port);
serial8250_set_sleep(p, state != 0);
}
EXPORT_SYMBOL(serial8250_do_pm);
static void
serial8250_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
if (port->pm)
port->pm(port, state, oldstate);
else
serial8250_do_pm(port, state, oldstate);
}
static unsigned int serial8250_port_size(struct uart_8250_port *pt)
{
if (pt->port.mapsize)
return pt->port.mapsize;
if (is_omap1_8250(pt))
return 0x16 << pt->port.regshift;
return 8 << pt->port.regshift;
}
/*
* Resource handling.
*/
static int serial8250_request_std_resource(struct uart_8250_port *up)
{
unsigned int size = serial8250_port_size(up);
struct uart_port *port = &up->port;
int ret = 0;
switch (port->iotype) {
case UPIO_AU:
case UPIO_TSI:
case UPIO_MEM32:
case UPIO_MEM32BE:
case UPIO_MEM16:
case UPIO_MEM:
if (!port->mapbase) {
ret = -EINVAL;
break;
}
if (!request_mem_region(port->mapbase, size, "serial")) {
ret = -EBUSY;
break;
}
if (port->flags & UPF_IOREMAP) {
port->membase = ioremap(port->mapbase, size);
if (!port->membase) {
release_mem_region(port->mapbase, size);
ret = -ENOMEM;
}
}
break;
case UPIO_HUB6:
case UPIO_PORT:
if (!request_region(port->iobase, size, "serial"))
ret = -EBUSY;
break;
}
return ret;
}
static void serial8250_release_std_resource(struct uart_8250_port *up)
{
unsigned int size = serial8250_port_size(up);
struct uart_port *port = &up->port;
switch (port->iotype) {
case UPIO_AU:
case UPIO_TSI:
case UPIO_MEM32:
case UPIO_MEM32BE:
case UPIO_MEM16:
case UPIO_MEM:
if (!port->mapbase)
break;
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
port->membase = NULL;
}
release_mem_region(port->mapbase, size);
break;
case UPIO_HUB6:
case UPIO_PORT:
release_region(port->iobase, size);
break;
}
}
static void serial8250_release_port(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
serial8250_release_std_resource(up);
}
static int serial8250_request_port(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
return serial8250_request_std_resource(up);
}
static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
{
const struct serial8250_config *conf_type = &uart_config[up->port.type];
unsigned char bytes;
bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
return bytes ? bytes : -EOPNOTSUPP;
}
static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
{
const struct serial8250_config *conf_type = &uart_config[up->port.type];
int i;
if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
return -EOPNOTSUPP;
for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
if (bytes < conf_type->rxtrig_bytes[i])
/* Use the nearest lower value */
return (--i) << UART_FCR_R_TRIG_SHIFT;
}
return UART_FCR_R_TRIG_11;
}
static int do_get_rxtrig(struct tty_port *port)
{
struct uart_state *state = container_of(port, struct uart_state, port);
struct uart_port *uport = state->uart_port;
struct uart_8250_port *up = up_to_u8250p(uport);
if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
return -EINVAL;
return fcr_get_rxtrig_bytes(up);
}
static int do_serial8250_get_rxtrig(struct tty_port *port)
{
int rxtrig_bytes;
mutex_lock(&port->mutex);
rxtrig_bytes = do_get_rxtrig(port);
mutex_unlock(&port->mutex);
return rxtrig_bytes;
}
static ssize_t rx_trig_bytes_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct tty_port *port = dev_get_drvdata(dev);
int rxtrig_bytes;
rxtrig_bytes = do_serial8250_get_rxtrig(port);
if (rxtrig_bytes < 0)
return rxtrig_bytes;
return sysfs_emit(buf, "%d\n", rxtrig_bytes);
}
static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
{
struct uart_state *state = container_of(port, struct uart_state, port);
struct uart_port *uport = state->uart_port;
struct uart_8250_port *up = up_to_u8250p(uport);
int rxtrig;
if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
return -EINVAL;
rxtrig = bytes_to_fcr_rxtrig(up, bytes);
if (rxtrig < 0)
return rxtrig;
serial8250_clear_fifos(up);
up->fcr &= ~UART_FCR_TRIGGER_MASK;
up->fcr |= (unsigned char)rxtrig;
serial_out(up, UART_FCR, up->fcr);
return 0;
}
static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
{
int ret;
mutex_lock(&port->mutex);
ret = do_set_rxtrig(port, bytes);
mutex_unlock(&port->mutex);
return ret;
}
static ssize_t rx_trig_bytes_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct tty_port *port = dev_get_drvdata(dev);
unsigned char bytes;
int ret;
if (!count)
return -EINVAL;
ret = kstrtou8(buf, 10, &bytes);
if (ret < 0)
return ret;
ret = do_serial8250_set_rxtrig(port, bytes);
if (ret < 0)
return ret;
return count;
}
static DEVICE_ATTR_RW(rx_trig_bytes);
static struct attribute *serial8250_dev_attrs[] = {
&dev_attr_rx_trig_bytes.attr,
NULL
};
static struct attribute_group serial8250_dev_attr_group = {
.attrs = serial8250_dev_attrs,
};
static void register_dev_spec_attr_grp(struct uart_8250_port *up)
{
const struct serial8250_config *conf_type = &uart_config[up->port.type];
if (conf_type->rxtrig_bytes[0])
up->port.attr_group = &serial8250_dev_attr_group;
}
static void serial8250_config_port(struct uart_port *port, int flags)
{
struct uart_8250_port *up = up_to_u8250p(port);
int ret;
/*
* Find the region that we can probe for. This in turn
* tells us whether we can probe for the type of port.
*/
ret = serial8250_request_std_resource(up);
if (ret < 0)
return;
if (port->iotype != up->cur_iotype)
set_io_from_upio(port);
if (flags & UART_CONFIG_TYPE)
autoconfig(up);
/* HW bugs may trigger IRQ while IIR == NO_INT */
if (port->type == PORT_TEGRA)
up->bugs |= UART_BUG_NOMSR;
if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
autoconfig_irq(up);
if (port->type == PORT_UNKNOWN)
serial8250_release_std_resource(up);
register_dev_spec_attr_grp(up);
up->fcr = uart_config[up->port.type].fcr;
}
static int
serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
{
if (ser->irq >= nr_irqs || ser->irq < 0 ||
ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
ser->type == PORT_STARTECH)
return -EINVAL;
return 0;
}
static const char *serial8250_type(struct uart_port *port)
{
int type = port->type;
if (type >= ARRAY_SIZE(uart_config))
type = 0;
return uart_config[type].name;
}
static const struct uart_ops serial8250_pops = {
.tx_empty = serial8250_tx_empty,
.set_mctrl = serial8250_set_mctrl,
.get_mctrl = serial8250_get_mctrl,
.stop_tx = serial8250_stop_tx,
.start_tx = serial8250_start_tx,
.throttle = serial8250_throttle,
.unthrottle = serial8250_unthrottle,
.stop_rx = serial8250_stop_rx,
.enable_ms = serial8250_enable_ms,
.break_ctl = serial8250_break_ctl,
.startup = serial8250_startup,
.shutdown = serial8250_shutdown,
.set_termios = serial8250_set_termios,
.set_ldisc = serial8250_set_ldisc,
.pm = serial8250_pm,
.type = serial8250_type,
.release_port = serial8250_release_port,
.request_port = serial8250_request_port,
.config_port = serial8250_config_port,
.verify_port = serial8250_verify_port,
#ifdef CONFIG_CONSOLE_POLL
.poll_get_char = serial8250_get_poll_char,
.poll_put_char = serial8250_put_poll_char,
#endif
};
void serial8250_init_port(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
spin_lock_init(&port->lock);
port->ctrl_id = 0;
port->pm = NULL;
port->ops = &serial8250_pops;
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
up->cur_iotype = 0xFF;
}
EXPORT_SYMBOL_GPL(serial8250_init_port);
void serial8250_set_defaults(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
if (up->port.flags & UPF_FIXED_TYPE) {
unsigned int type = up->port.type;
if (!up->port.fifosize)
up->port.fifosize = uart_config[type].fifo_size;
if (!up->tx_loadsz)
up->tx_loadsz = uart_config[type].tx_loadsz;
if (!up->capabilities)
up->capabilities = uart_config[type].flags;
}
set_io_from_upio(port);
/* default dma handlers */
if (up->dma) {
if (!up->dma->tx_dma)
up->dma->tx_dma = serial8250_tx_dma;
if (!up->dma->rx_dma)
up->dma->rx_dma = serial8250_rx_dma;
}
}
EXPORT_SYMBOL_GPL(serial8250_set_defaults);
#ifdef CONFIG_SERIAL_8250_CONSOLE
static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
{
struct uart_8250_port *up = up_to_u8250p(port);
wait_for_xmitr(up, UART_LSR_THRE);
serial_port_out(port, UART_TX, ch);
}
/*
* Restore serial console when h/w power-off detected
*/
static void serial8250_console_restore(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
struct ktermios termios;
unsigned int baud, quot, frac = 0;
termios.c_cflag = port->cons->cflag;
termios.c_ispeed = port->cons->ispeed;
termios.c_ospeed = port->cons->ospeed;
if (port->state->port.tty && termios.c_cflag == 0) {
termios.c_cflag = port->state->port.tty->termios.c_cflag;
termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
}
baud = serial8250_get_baud_rate(port, &termios, NULL);
quot = serial8250_get_divisor(port, baud, &frac);
serial8250_set_divisor(port, baud, quot, frac);
serial_port_out(port, UART_LCR, up->lcr);
serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
}
/*
* Print a string to the serial port using the device FIFO
*
* It sends fifosize bytes and then waits for the fifo
* to get empty.
*/
static void serial8250_console_fifo_write(struct uart_8250_port *up,
const char *s, unsigned int count)
{
int i;
const char *end = s + count;
unsigned int fifosize = up->tx_loadsz;
bool cr_sent = false;
while (s != end) {
wait_for_lsr(up, UART_LSR_THRE);
for (i = 0; i < fifosize && s != end; ++i) {
if (*s == '\n' && !cr_sent) {
serial_out(up, UART_TX, '\r');
cr_sent = true;
} else {
serial_out(up, UART_TX, *s++);
cr_sent = false;
}
}
}
}
/*
* Print a string to the serial port trying not to disturb
* any possible real use of the port...
*
* The console_lock must be held when we get here.
*
* Doing runtime PM is really a bad idea for the kernel console.
* Thus, we assume the function is called when device is powered up.
*/
void serial8250_console_write(struct uart_8250_port *up, const char *s,
unsigned int count)
{
struct uart_8250_em485 *em485 = up->em485;
struct uart_port *port = &up->port;
unsigned long flags;
unsigned int ier, use_fifo;
int locked = 1;
touch_nmi_watchdog();
if (oops_in_progress)
locked = spin_trylock_irqsave(&port->lock, flags);
else
spin_lock_irqsave(&port->lock, flags);
/*
* First save the IER then disable the interrupts
*/
ier = serial_port_in(port, UART_IER);
serial8250_clear_IER(up);
/* check scratch reg to see if port powered off during system sleep */
if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
serial8250_console_restore(up);
up->canary = 0;
}
if (em485) {
if (em485->tx_stopped)
up->rs485_start_tx(up);
mdelay(port->rs485.delay_rts_before_send);
}
use_fifo = (up->capabilities & UART_CAP_FIFO) &&
/*
* BCM283x requires to check the fifo
* after each byte.
*/
!(up->capabilities & UART_CAP_MINI) &&
/*
* tx_loadsz contains the transmit fifo size
*/
up->tx_loadsz > 1 &&
(up->fcr & UART_FCR_ENABLE_FIFO) &&
port->state &&
test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
/*
* After we put a data in the fifo, the controller will send
* it regardless of the CTS state. Therefore, only use fifo
* if we don't use control flow.
*/
!(up->port.flags & UPF_CONS_FLOW);
if (likely(use_fifo))
serial8250_console_fifo_write(up, s, count);
else
uart_console_write(port, s, count, serial8250_console_putchar);
/*
* Finally, wait for transmitter to become empty
* and restore the IER
*/
wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
if (em485) {
mdelay(port->rs485.delay_rts_after_send);
if (em485->tx_stopped)
up->rs485_stop_tx(up);
}
serial_port_out(port, UART_IER, ier);
/*
* The receive handling will happen properly because the
* receive ready bit will still be set; it is not cleared
* on read. However, modem control will not, we must
* call it if we have saved something in the saved flags
* while processing with interrupts off.
*/
if (up->msr_saved_flags)
serial8250_modem_status(up);
if (locked)
spin_unlock_irqrestore(&port->lock, flags);
}
static unsigned int probe_baud(struct uart_port *port)
{
unsigned char lcr, dll, dlm;
unsigned int quot;
lcr = serial_port_in(port, UART_LCR);
serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
dll = serial_port_in(port, UART_DLL);
dlm = serial_port_in(port, UART_DLM);
serial_port_out(port, UART_LCR, lcr);
quot = (dlm << 8) | dll;
return (port->uartclk / 16) / quot;
}
int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
{
int baud = 9600;
int bits = 8;
int parity = 'n';
int flow = 'n';
int ret;
if (!port->iobase && !port->membase)
return -ENODEV;
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
else if (probe)
baud = probe_baud(port);
ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
if (ret)
return ret;
if (port->dev)
pm_runtime_get_sync(port->dev);
return 0;
}
int serial8250_console_exit(struct uart_port *port)
{
if (port->dev)
pm_runtime_put_sync(port->dev);
return 0;
}
#endif /* CONFIG_SERIAL_8250_CONSOLE */
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_port.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Probe for 8250/16550-type ISAPNP serial ports.
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
* Ported to the Linux PnP Layer - (C) Adam Belay.
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pnp.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/property.h>
#include <linux/serial_core.h>
#include <linux/bitops.h>
#include <asm/byteorder.h>
#include "8250.h"
#define UNKNOWN_DEV 0x3000
#define CIR_PORT 0x0800
static const struct pnp_device_id pnp_dev_table[] = {
/* Archtek America Corp. */
/* Archtek SmartLink Modem 3334BT Plug & Play */
{ "AAC000F", 0 },
/* Anchor Datacomm BV */
/* SXPro 144 External Data Fax Modem Plug & Play */
{ "ADC0001", 0 },
/* SXPro 288 External Data Fax Modem Plug & Play */
{ "ADC0002", 0 },
/* PROLiNK 1456VH ISA PnP K56flex Fax Modem */
{ "AEI0250", 0 },
/* Actiontec ISA PNP 56K X2 Fax Modem */
{ "AEI1240", 0 },
/* Rockwell 56K ACF II Fax+Data+Voice Modem */
{ "AKY1021", 0 /*SPCI_FL_NO_SHIRQ*/ },
/*
* ALi Fast Infrared Controller
* Native driver (ali-ircc) is broken so at least
* it can be used with irtty-sir.
*/
{ "ALI5123", 0 },
/* AZT3005 PnP SOUND DEVICE */
{ "AZT4001", 0 },
/* Best Data Products Inc. Smart One 336F PnP Modem */
{ "BDP3336", 0 },
/* Boca Research */
/* Boca Complete Ofc Communicator 14.4 Data-FAX */
{ "BRI0A49", 0 },
/* Boca Research 33,600 ACF Modem */
{ "BRI1400", 0 },
/* Boca 33.6 Kbps Internal FD34FSVD */
{ "BRI3400", 0 },
/* Computer Peripherals Inc */
/* EuroViVa CommCenter-33.6 SP PnP */
{ "CPI4050", 0 },
/* Creative Labs */
/* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
{ "CTL3001", 0 },
/* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
{ "CTL3011", 0 },
/* Davicom ISA 33.6K Modem */
{ "DAV0336", 0 },
/* Creative */
/* Creative Modem Blaster Flash56 DI5601-1 */
{ "DMB1032", 0 },
/* Creative Modem Blaster V.90 DI5660 */
{ "DMB2001", 0 },
/* E-Tech */
/* E-Tech CyberBULLET PC56RVP */
{ "ETT0002", 0 },
/* FUJITSU */
/* Fujitsu 33600 PnP-I2 R Plug & Play */
{ "FUJ0202", 0 },
/* Fujitsu FMV-FX431 Plug & Play */
{ "FUJ0205", 0 },
/* Fujitsu 33600 PnP-I4 R Plug & Play */
{ "FUJ0206", 0 },
/* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
{ "FUJ0209", 0 },
/* Archtek America Corp. */
/* Archtek SmartLink Modem 3334BT Plug & Play */
{ "GVC000F", 0 },
/* Archtek SmartLink Modem 3334BRV 33.6K Data Fax Voice */
{ "GVC0303", 0 },
/* Hayes */
/* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
{ "HAY0001", 0 },
/* Hayes Optima 336 V.34 + FAX + Voice PnP */
{ "HAY000C", 0 },
/* Hayes Optima 336B V.34 + FAX + Voice PnP */
{ "HAY000D", 0 },
/* Hayes Accura 56K Ext Fax Modem PnP */
{ "HAY5670", 0 },
/* Hayes Accura 56K Ext Fax Modem PnP */
{ "HAY5674", 0 },
/* Hayes Accura 56K Fax Modem PnP */
{ "HAY5675", 0 },
/* Hayes 288, V.34 + FAX */
{ "HAYF000", 0 },
/* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
{ "HAYF001", 0 },
/* IBM */
/* IBM Thinkpad 701 Internal Modem Voice */
{ "IBM0033", 0 },
/* Intermec */
/* Intermec CV60 touchscreen port */
{ "PNP4972", 0 },
/* Intertex */
/* Intertex 28k8 33k6 Voice EXT PnP */
{ "IXDC801", 0 },
/* Intertex 33k6 56k Voice EXT PnP */
{ "IXDC901", 0 },
/* Intertex 28k8 33k6 Voice SP EXT PnP */
{ "IXDD801", 0 },
/* Intertex 33k6 56k Voice SP EXT PnP */
{ "IXDD901", 0 },
/* Intertex 28k8 33k6 Voice SP INT PnP */
{ "IXDF401", 0 },
/* Intertex 28k8 33k6 Voice SP EXT PnP */
{ "IXDF801", 0 },
/* Intertex 33k6 56k Voice SP EXT PnP */
{ "IXDF901", 0 },
/* Kortex International */
/* KORTEX 28800 Externe PnP */
{ "KOR4522", 0 },
/* KXPro 33.6 Vocal ASVD PnP */
{ "KORF661", 0 },
/* Lasat */
/* LASAT Internet 33600 PnP */
{ "LAS4040", 0 },
/* Lasat Safire 560 PnP */
{ "LAS4540", 0 },
/* Lasat Safire 336 PnP */
{ "LAS5440", 0 },
/* Microcom, Inc. */
/* Microcom TravelPorte FAST V.34 Plug & Play */
{ "MNP0281", 0 },
/* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
{ "MNP0336", 0 },
/* Microcom DeskPorte FAST EP 28.8 Plug & Play */
{ "MNP0339", 0 },
/* Microcom DeskPorte 28.8P Plug & Play */
{ "MNP0342", 0 },
/* Microcom DeskPorte FAST ES 28.8 Plug & Play */
{ "MNP0500", 0 },
/* Microcom DeskPorte FAST ES 28.8 Plug & Play */
{ "MNP0501", 0 },
/* Microcom DeskPorte 28.8S Internal Plug & Play */
{ "MNP0502", 0 },
/* Motorola */
/* Motorola BitSURFR Plug & Play */
{ "MOT1105", 0 },
/* Motorola TA210 Plug & Play */
{ "MOT1111", 0 },
/* Motorola HMTA 200 (ISDN) Plug & Play */
{ "MOT1114", 0 },
/* Motorola BitSURFR Plug & Play */
{ "MOT1115", 0 },
/* Motorola Lifestyle 28.8 Internal */
{ "MOT1190", 0 },
/* Motorola V.3400 Plug & Play */
{ "MOT1501", 0 },
/* Motorola Lifestyle 28.8 V.34 Plug & Play */
{ "MOT1502", 0 },
/* Motorola Power 28.8 V.34 Plug & Play */
{ "MOT1505", 0 },
/* Motorola ModemSURFR External 28.8 Plug & Play */
{ "MOT1509", 0 },
/* Motorola Premier 33.6 Desktop Plug & Play */
{ "MOT150A", 0 },
/* Motorola VoiceSURFR 56K External PnP */
{ "MOT150F", 0 },
/* Motorola ModemSURFR 56K External PnP */
{ "MOT1510", 0 },
/* Motorola ModemSURFR 56K Internal PnP */
{ "MOT1550", 0 },
/* Motorola ModemSURFR Internal 28.8 Plug & Play */
{ "MOT1560", 0 },
/* Motorola Premier 33.6 Internal Plug & Play */
{ "MOT1580", 0 },
/* Motorola OnlineSURFR 28.8 Internal Plug & Play */
{ "MOT15B0", 0 },
/* Motorola VoiceSURFR 56K Internal PnP */
{ "MOT15F0", 0 },
/* Com 1 */
/* Deskline K56 Phone System PnP */
{ "MVX00A1", 0 },
/* PC Rider K56 Phone System PnP */
{ "MVX00F2", 0 },
/* NEC 98NOTE SPEAKER PHONE FAX MODEM(33600bps) */
{ "nEC8241", 0 },
/* Pace 56 Voice Internal Plug & Play Modem */
{ "PMC2430", 0 },
/* Generic */
/* Generic standard PC COM port */
{ "PNP0500", 0 },
/* Generic 16550A-compatible COM port */
{ "PNP0501", 0 },
/* Compaq 14400 Modem */
{ "PNPC000", 0 },
/* Compaq 2400/9600 Modem */
{ "PNPC001", 0 },
/* Dial-Up Networking Serial Cable between 2 PCs */
{ "PNPC031", 0 },
/* Dial-Up Networking Parallel Cable between 2 PCs */
{ "PNPC032", 0 },
/* Standard 9600 bps Modem */
{ "PNPC100", 0 },
/* Standard 14400 bps Modem */
{ "PNPC101", 0 },
/* Standard 28800 bps Modem*/
{ "PNPC102", 0 },
/* Standard Modem*/
{ "PNPC103", 0 },
/* Standard 9600 bps Modem*/
{ "PNPC104", 0 },
/* Standard 14400 bps Modem*/
{ "PNPC105", 0 },
/* Standard 28800 bps Modem*/
{ "PNPC106", 0 },
/* Standard Modem */
{ "PNPC107", 0 },
/* Standard 9600 bps Modem */
{ "PNPC108", 0 },
/* Standard 14400 bps Modem */
{ "PNPC109", 0 },
/* Standard 28800 bps Modem */
{ "PNPC10A", 0 },
/* Standard Modem */
{ "PNPC10B", 0 },
/* Standard 9600 bps Modem */
{ "PNPC10C", 0 },
/* Standard 14400 bps Modem */
{ "PNPC10D", 0 },
/* Standard 28800 bps Modem */
{ "PNPC10E", 0 },
/* Standard Modem */
{ "PNPC10F", 0 },
/* Standard PCMCIA Card Modem */
{ "PNP2000", 0 },
/* Rockwell */
/* Modular Technology */
/* Rockwell 33.6 DPF Internal PnP */
/* Modular Technology 33.6 Internal PnP */
{ "ROK0030", 0 },
/* Kortex International */
/* KORTEX 14400 Externe PnP */
{ "ROK0100", 0 },
/* Rockwell 28.8 */
{ "ROK4120", 0 },
/* Viking Components, Inc */
/* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
{ "ROK4920", 0 },
/* Rockwell */
/* British Telecom */
/* Modular Technology */
/* Rockwell 33.6 DPF External PnP */
/* BT Prologue 33.6 External PnP */
/* Modular Technology 33.6 External PnP */
{ "RSS00A0", 0 },
/* Viking 56K FAX INT */
{ "RSS0262", 0 },
/* K56 par,VV,Voice,Speakphone,AudioSpan,PnP */
{ "RSS0250", 0 },
/* SupraExpress 28.8 Data/Fax PnP modem */
{ "SUP1310", 0 },
/* SupraExpress 336i PnP Voice Modem */
{ "SUP1381", 0 },
/* SupraExpress 33.6 Data/Fax PnP modem */
{ "SUP1421", 0 },
/* SupraExpress 33.6 Data/Fax PnP modem */
{ "SUP1590", 0 },
/* SupraExpress 336i Sp ASVD */
{ "SUP1620", 0 },
/* SupraExpress 33.6 Data/Fax PnP modem */
{ "SUP1760", 0 },
/* SupraExpress 56i Sp Intl */
{ "SUP2171", 0 },
/* Phoebe Micro */
/* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
{ "TEX0011", 0 },
/* Archtek America Corp. */
/* Archtek SmartLink Modem 3334BT Plug & Play */
{ "UAC000F", 0 },
/* 3Com Corp. */
/* Gateway Telepath IIvi 33.6 */
{ "USR0000", 0 },
/* U.S. Robotics Sporster 33.6K Fax INT PnP */
{ "USR0002", 0 },
/* Sportster Vi 14.4 PnP FAX Voicemail */
{ "USR0004", 0 },
/* U.S. Robotics 33.6K Voice INT PnP */
{ "USR0006", 0 },
/* U.S. Robotics 33.6K Voice EXT PnP */
{ "USR0007", 0 },
/* U.S. Robotics Courier V.Everything INT PnP */
{ "USR0009", 0 },
/* U.S. Robotics 33.6K Voice INT PnP */
{ "USR2002", 0 },
/* U.S. Robotics 56K Voice INT PnP */
{ "USR2070", 0 },
/* U.S. Robotics 56K Voice EXT PnP */
{ "USR2080", 0 },
/* U.S. Robotics 56K FAX INT */
{ "USR3031", 0 },
/* U.S. Robotics 56K FAX INT */
{ "USR3050", 0 },
/* U.S. Robotics 56K Voice INT PnP */
{ "USR3070", 0 },
/* U.S. Robotics 56K Voice EXT PnP */
{ "USR3080", 0 },
/* U.S. Robotics 56K Voice INT PnP */
{ "USR3090", 0 },
/* U.S. Robotics 56K Message */
{ "USR9100", 0 },
/* U.S. Robotics 56K FAX EXT PnP*/
{ "USR9160", 0 },
/* U.S. Robotics 56K FAX INT PnP*/
{ "USR9170", 0 },
/* U.S. Robotics 56K Voice EXT PnP*/
{ "USR9180", 0 },
/* U.S. Robotics 56K Voice INT PnP*/
{ "USR9190", 0 },
/* Wacom tablets */
{ "WACFXXX", 0 },
/* Compaq touchscreen */
{ "FPI2002", 0 },
/* Fujitsu Stylistic touchscreens */
{ "FUJ02B2", 0 },
{ "FUJ02B3", 0 },
/* Fujitsu Stylistic LT touchscreens */
{ "FUJ02B4", 0 },
/* Passive Fujitsu Stylistic touchscreens */
{ "FUJ02B6", 0 },
{ "FUJ02B7", 0 },
{ "FUJ02B8", 0 },
{ "FUJ02B9", 0 },
{ "FUJ02BC", 0 },
/* Fujitsu Wacom Tablet PC device */
{ "FUJ02E5", 0 },
/* Fujitsu P-series tablet PC device */
{ "FUJ02E6", 0 },
/* Fujitsu Wacom 2FGT Tablet PC device */
{ "FUJ02E7", 0 },
/* Fujitsu Wacom 1FGT Tablet PC device */
{ "FUJ02E9", 0 },
/*
* LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6
* in disguise).
*/
{ "LTS0001", 0 },
/* Rockwell's (PORALiNK) 33600 INT PNP */
{ "WCI0003", 0 },
/* Unknown PnP modems */
{ "PNPCXXX", UNKNOWN_DEV },
/* More unknown PnP modems */
{ "PNPDXXX", UNKNOWN_DEV },
/*
* Winbond CIR port, should not be probed. We should keep track of
* it to prevent the legacy serial driver from probing it.
*/
{ "WEC1022", CIR_PORT },
/*
* SMSC IrCC SIR/FIR port, should not be probed by serial driver as
* well so its own driver can bind to it.
*/
{ "SMCF010", CIR_PORT },
{ "", 0 }
};
MODULE_DEVICE_TABLE(pnp, pnp_dev_table);
static const char *modem_names[] = {
"MODEM", "Modem", "modem", "FAX", "Fax", "fax",
"56K", "56k", "K56", "33.6", "28.8", "14.4",
"33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
"33600", "28800", "14400", "V.90", "V.34", "V.32", NULL
};
static bool check_name(const char *name)
{
const char **tmp;
for (tmp = modem_names; *tmp; tmp++)
if (strstr(name, *tmp))
return true;
return false;
}
static bool check_resources(struct pnp_dev *dev)
{
static const resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8};
unsigned int i;
for (i = 0; i < ARRAY_SIZE(base); i++) {
if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8))
return true;
}
return false;
}
/*
* Given a complete unknown PnP device, try to use some heuristics to
* detect modems. Currently use such heuristic set:
* - dev->name or dev->bus->name must contain "modem" substring;
* - device must have only one IO region (8 byte long) with base address
* 0x2e8, 0x3e8, 0x2f8 or 0x3f8.
*
* Such detection looks very ugly, but can detect at least some of numerous
* PnP modems, alternatively we must hardcode all modems in pnp_devices[]
* table.
*/
static int serial_pnp_guess_board(struct pnp_dev *dev)
{
if (!(check_name(pnp_dev_name(dev)) ||
(dev->card && check_name(dev->card->name))))
return -ENODEV;
if (check_resources(dev))
return 0;
return -ENODEV;
}
static int
serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
{
struct uart_8250_port uart, *port;
int ret, line, flags = dev_id->driver_data;
if (flags & UNKNOWN_DEV) {
ret = serial_pnp_guess_board(dev);
if (ret < 0)
return ret;
}
memset(&uart, 0, sizeof(uart));
if (pnp_irq_valid(dev, 0))
uart.port.irq = pnp_irq(dev, 0);
if ((flags & CIR_PORT) && pnp_port_valid(dev, 2)) {
uart.port.iobase = pnp_port_start(dev, 2);
uart.port.iotype = UPIO_PORT;
} else if (pnp_port_valid(dev, 0)) {
uart.port.iobase = pnp_port_start(dev, 0);
uart.port.iotype = UPIO_PORT;
} else if (pnp_mem_valid(dev, 0)) {
uart.port.mapbase = pnp_mem_start(dev, 0);
uart.port.iotype = UPIO_MEM;
uart.port.flags = UPF_IOREMAP;
} else
return -ENODEV;
dev_dbg(&dev->dev,
"Setup PNP port: port %#lx, mem %#llx, irq %u, type %u\n",
uart.port.iobase, (unsigned long long)uart.port.mapbase,
uart.port.irq, uart.port.iotype);
if (flags & CIR_PORT) {
uart.port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
uart.port.type = PORT_8250_CIR;
}
uart.port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE)
uart.port.flags |= UPF_SHARE_IRQ;
uart.port.uartclk = 1843200;
device_property_read_u32(&dev->dev, "clock-frequency", &uart.port.uartclk);
uart.port.dev = &dev->dev;
line = serial8250_register_8250_port(&uart);
if (line < 0 || (flags & CIR_PORT))
return -ENODEV;
port = serial8250_get_port(line);
if (uart_console(&port->port))
dev->capabilities |= PNP_CONSOLE;
pnp_set_drvdata(dev, (void *)((long)line + 1));
return 0;
}
static void serial_pnp_remove(struct pnp_dev *dev)
{
long line = (long)pnp_get_drvdata(dev);
dev->capabilities &= ~PNP_CONSOLE;
if (line)
serial8250_unregister_port(line - 1);
}
static int __maybe_unused serial_pnp_suspend(struct device *dev)
{
long line = (long)dev_get_drvdata(dev);
if (!line)
return -ENODEV;
serial8250_suspend_port(line - 1);
return 0;
}
static int __maybe_unused serial_pnp_resume(struct device *dev)
{
long line = (long)dev_get_drvdata(dev);
if (!line)
return -ENODEV;
serial8250_resume_port(line - 1);
return 0;
}
static SIMPLE_DEV_PM_OPS(serial_pnp_pm_ops, serial_pnp_suspend, serial_pnp_resume);
static struct pnp_driver serial_pnp_driver = {
.name = "serial",
.probe = serial_pnp_probe,
.remove = serial_pnp_remove,
.driver = {
.pm = &serial_pnp_pm_ops,
},
.id_table = pnp_dev_table,
};
int serial8250_pnp_init(void)
{
return pnp_register_driver(&serial_pnp_driver);
}
void serial8250_pnp_exit(void)
{
pnp_unregister_driver(&serial_pnp_driver);
}
| linux-master | drivers/tty/serial/8250/8250_pnp.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Universal/legacy driver for 8250/16550-type serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
* Copyright (C) 2001 Russell King.
*
* Supports: ISA-compatible 8250/16550 ports
* PNP 8250/16550 ports
* early_serial_setup() ports
* userspace-configurable "phantom" ports
* "serial8250" platform devices
* serial8250_register_8250_port() ports
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/tty.h>
#include <linux/ratelimit.h>
#include <linux/tty_flip.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/nmi.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#ifdef CONFIG_SPARC
#include <linux/sunserialcore.h>
#endif
#include <asm/irq.h>
#include "8250.h"
/*
* Configuration:
* share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
* is unsafe when used on edge-triggered interrupts.
*/
static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
static struct uart_driver serial8250_reg;
static unsigned int skip_txen_test; /* force skip of txen test at init time */
#define PASS_LIMIT 512
#include <asm/serial.h>
/*
* SERIAL_PORT_DFNS tells us about built-in ports that have no
* standard enumeration mechanism. Platforms that can find all
* serial ports via mechanisms like ACPI or PCI need not supply it.
*/
#ifndef SERIAL_PORT_DFNS
#define SERIAL_PORT_DFNS
#endif
static const struct old_serial_port old_serial_port[] = {
SERIAL_PORT_DFNS /* defined in asm/serial.h */
};
#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
#ifdef CONFIG_SERIAL_8250_RSA
#define PORT_RSA_MAX 4
static unsigned long probe_rsa[PORT_RSA_MAX];
static unsigned int probe_rsa_count;
#endif /* CONFIG_SERIAL_8250_RSA */
struct irq_info {
struct hlist_node node;
int irq;
spinlock_t lock; /* Protects list not the hash */
struct list_head *head;
};
#define NR_IRQ_HASH 32 /* Can be adjusted later */
static struct hlist_head irq_lists[NR_IRQ_HASH];
static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
/*
* This is the serial driver's interrupt routine.
*
* Arjan thinks the old way was overly complex, so it got simplified.
* Alan disagrees, saying that need the complexity to handle the weird
* nature of ISA shared interrupts. (This is a special exception.)
*
* In order to handle ISA shared interrupts properly, we need to check
* that all ports have been serviced, and therefore the ISA interrupt
* line has been de-asserted.
*
* This means we need to loop through all ports. checking that they
* don't have an interrupt pending.
*/
static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
{
struct irq_info *i = dev_id;
struct list_head *l, *end = NULL;
int pass_counter = 0, handled = 0;
pr_debug("%s(%d): start\n", __func__, irq);
spin_lock(&i->lock);
l = i->head;
do {
struct uart_8250_port *up;
struct uart_port *port;
up = list_entry(l, struct uart_8250_port, list);
port = &up->port;
if (port->handle_irq(port)) {
handled = 1;
end = NULL;
} else if (end == NULL)
end = l;
l = l->next;
if (l == i->head && pass_counter++ > PASS_LIMIT)
break;
} while (l != end);
spin_unlock(&i->lock);
pr_debug("%s(%d): end\n", __func__, irq);
return IRQ_RETVAL(handled);
}
/*
* To support ISA shared interrupts, we need to have one interrupt
* handler that ensures that the IRQ line has been deasserted
* before returning. Failing to do this will result in the IRQ
* line being stuck active, and, since ISA irqs are edge triggered,
* no more IRQs will be seen.
*/
static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
{
spin_lock_irq(&i->lock);
if (!list_empty(i->head)) {
if (i->head == &up->list)
i->head = i->head->next;
list_del(&up->list);
} else {
BUG_ON(i->head != &up->list);
i->head = NULL;
}
spin_unlock_irq(&i->lock);
/* List empty so throw away the hash node */
if (i->head == NULL) {
hlist_del(&i->node);
kfree(i);
}
}
static int serial_link_irq_chain(struct uart_8250_port *up)
{
struct hlist_head *h;
struct irq_info *i;
int ret;
mutex_lock(&hash_mutex);
h = &irq_lists[up->port.irq % NR_IRQ_HASH];
hlist_for_each_entry(i, h, node)
if (i->irq == up->port.irq)
break;
if (i == NULL) {
i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
if (i == NULL) {
mutex_unlock(&hash_mutex);
return -ENOMEM;
}
spin_lock_init(&i->lock);
i->irq = up->port.irq;
hlist_add_head(&i->node, h);
}
mutex_unlock(&hash_mutex);
spin_lock_irq(&i->lock);
if (i->head) {
list_add(&up->list, i->head);
spin_unlock_irq(&i->lock);
ret = 0;
} else {
INIT_LIST_HEAD(&up->list);
i->head = &up->list;
spin_unlock_irq(&i->lock);
ret = request_irq(up->port.irq, serial8250_interrupt,
up->port.irqflags, up->port.name, i);
if (ret < 0)
serial_do_unlink(i, up);
}
return ret;
}
static void serial_unlink_irq_chain(struct uart_8250_port *up)
{
struct irq_info *i;
struct hlist_head *h;
mutex_lock(&hash_mutex);
h = &irq_lists[up->port.irq % NR_IRQ_HASH];
hlist_for_each_entry(i, h, node)
if (i->irq == up->port.irq)
break;
BUG_ON(i == NULL);
BUG_ON(i->head == NULL);
if (list_empty(i->head))
free_irq(up->port.irq, i);
serial_do_unlink(i, up);
mutex_unlock(&hash_mutex);
}
/*
* This function is used to handle ports that do not have an
* interrupt. This doesn't work very well for 16450's, but gives
* barely passable results for a 16550A. (Although at the expense
* of much CPU overhead).
*/
static void serial8250_timeout(struct timer_list *t)
{
struct uart_8250_port *up = from_timer(up, t, timer);
up->port.handle_irq(&up->port);
mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
}
static void serial8250_backup_timeout(struct timer_list *t)
{
struct uart_8250_port *up = from_timer(up, t, timer);
unsigned int iir, ier = 0, lsr;
unsigned long flags;
spin_lock_irqsave(&up->port.lock, flags);
/*
* Must disable interrupts or else we risk racing with the interrupt
* based handler.
*/
if (up->port.irq) {
ier = serial_in(up, UART_IER);
serial_out(up, UART_IER, 0);
}
iir = serial_in(up, UART_IIR);
/*
* This should be a safe test for anyone who doesn't trust the
* IIR bits on their UART, but it's specifically designed for
* the "Diva" UART used on the management processor on many HP
* ia64 and parisc boxes.
*/
lsr = serial_lsr_in(up);
if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
(!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
(lsr & UART_LSR_THRE)) {
iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
iir |= UART_IIR_THRI;
}
if (!(iir & UART_IIR_NO_INT))
serial8250_tx_chars(up);
if (up->port.irq)
serial_out(up, UART_IER, ier);
spin_unlock_irqrestore(&up->port.lock, flags);
/* Standard timer interval plus 0.2s to keep the port running */
mod_timer(&up->timer,
jiffies + uart_poll_timeout(&up->port) + HZ / 5);
}
static void univ8250_setup_timer(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
/*
* The above check will only give an accurate result the first time
* the port is opened so this value needs to be preserved.
*/
if (up->bugs & UART_BUG_THRE) {
pr_debug("%s - using backup timer\n", port->name);
up->timer.function = serial8250_backup_timeout;
mod_timer(&up->timer, jiffies +
uart_poll_timeout(port) + HZ / 5);
}
/*
* If the "interrupt" for this port doesn't correspond with any
* hardware interrupt, we use a timer-based system. The original
* driver used to do this with IRQ0.
*/
if (!port->irq)
mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
}
static int univ8250_setup_irq(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
if (port->irq)
return serial_link_irq_chain(up);
return 0;
}
static void univ8250_release_irq(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
del_timer_sync(&up->timer);
up->timer.function = serial8250_timeout;
if (port->irq)
serial_unlink_irq_chain(up);
}
#ifdef CONFIG_SERIAL_8250_RSA
static int serial8250_request_rsa_resource(struct uart_8250_port *up)
{
unsigned long start = UART_RSA_BASE << up->port.regshift;
unsigned int size = 8 << up->port.regshift;
struct uart_port *port = &up->port;
int ret = -EINVAL;
switch (port->iotype) {
case UPIO_HUB6:
case UPIO_PORT:
start += port->iobase;
if (request_region(start, size, "serial-rsa"))
ret = 0;
else
ret = -EBUSY;
break;
}
return ret;
}
static void serial8250_release_rsa_resource(struct uart_8250_port *up)
{
unsigned long offset = UART_RSA_BASE << up->port.regshift;
unsigned int size = 8 << up->port.regshift;
struct uart_port *port = &up->port;
switch (port->iotype) {
case UPIO_HUB6:
case UPIO_PORT:
release_region(port->iobase + offset, size);
break;
}
}
#endif
static const struct uart_ops *base_ops;
static struct uart_ops univ8250_port_ops;
static const struct uart_8250_ops univ8250_driver_ops = {
.setup_irq = univ8250_setup_irq,
.release_irq = univ8250_release_irq,
.setup_timer = univ8250_setup_timer,
};
static struct uart_8250_port serial8250_ports[UART_NR];
/**
* serial8250_get_port - retrieve struct uart_8250_port
* @line: serial line number
*
* This function retrieves struct uart_8250_port for the specific line.
* This struct *must* *not* be used to perform a 8250 or serial core operation
* which is not accessible otherwise. Its only purpose is to make the struct
* accessible to the runtime-pm callbacks for context suspend/restore.
* The lock assumption made here is none because runtime-pm suspend/resume
* callbacks should not be invoked if there is any operation performed on the
* port.
*/
struct uart_8250_port *serial8250_get_port(int line)
{
return &serial8250_ports[line];
}
EXPORT_SYMBOL_GPL(serial8250_get_port);
static void (*serial8250_isa_config)(int port, struct uart_port *up,
u32 *capabilities);
void serial8250_set_isa_configurator(
void (*v)(int port, struct uart_port *up, u32 *capabilities))
{
serial8250_isa_config = v;
}
EXPORT_SYMBOL(serial8250_set_isa_configurator);
#ifdef CONFIG_SERIAL_8250_RSA
static void univ8250_config_port(struct uart_port *port, int flags)
{
struct uart_8250_port *up = up_to_u8250p(port);
up->probe &= ~UART_PROBE_RSA;
if (port->type == PORT_RSA) {
if (serial8250_request_rsa_resource(up) == 0)
up->probe |= UART_PROBE_RSA;
} else if (flags & UART_CONFIG_TYPE) {
int i;
for (i = 0; i < probe_rsa_count; i++) {
if (probe_rsa[i] == up->port.iobase) {
if (serial8250_request_rsa_resource(up) == 0)
up->probe |= UART_PROBE_RSA;
break;
}
}
}
base_ops->config_port(port, flags);
if (port->type != PORT_RSA && up->probe & UART_PROBE_RSA)
serial8250_release_rsa_resource(up);
}
static int univ8250_request_port(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
int ret;
ret = base_ops->request_port(port);
if (ret == 0 && port->type == PORT_RSA) {
ret = serial8250_request_rsa_resource(up);
if (ret < 0)
base_ops->release_port(port);
}
return ret;
}
static void univ8250_release_port(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
if (port->type == PORT_RSA)
serial8250_release_rsa_resource(up);
base_ops->release_port(port);
}
static void univ8250_rsa_support(struct uart_ops *ops)
{
ops->config_port = univ8250_config_port;
ops->request_port = univ8250_request_port;
ops->release_port = univ8250_release_port;
}
#else
#define univ8250_rsa_support(x) do { } while (0)
#endif /* CONFIG_SERIAL_8250_RSA */
static inline void serial8250_apply_quirks(struct uart_8250_port *up)
{
up->port.quirks |= skip_txen_test ? UPQ_NO_TXEN_TEST : 0;
}
static struct uart_8250_port *serial8250_setup_port(int index)
{
struct uart_8250_port *up;
if (index >= UART_NR)
return NULL;
up = &serial8250_ports[index];
up->port.line = index;
up->port.port_id = index;
serial8250_init_port(up);
if (!base_ops)
base_ops = up->port.ops;
up->port.ops = &univ8250_port_ops;
timer_setup(&up->timer, serial8250_timeout, 0);
up->ops = &univ8250_driver_ops;
if (IS_ENABLED(CONFIG_ALPHA_JENSEN) ||
(IS_ENABLED(CONFIG_ALPHA_GENERIC) && alpha_jensen()))
up->port.set_mctrl = alpha_jensen_set_mctrl;
serial8250_set_defaults(up);
return up;
}
static void __init serial8250_isa_init_ports(void)
{
struct uart_8250_port *up;
static int first = 1;
int i, irqflag = 0;
if (!first)
return;
first = 0;
if (nr_uarts > UART_NR)
nr_uarts = UART_NR;
/*
* Set up initial isa ports based on nr_uart module param, or else
* default to CONFIG_SERIAL_8250_RUNTIME_UARTS. Note that we do not
* need to increase nr_uarts when setting up the initial isa ports.
*/
for (i = 0; i < nr_uarts; i++)
serial8250_setup_port(i);
/* chain base port ops to support Remote Supervisor Adapter */
univ8250_port_ops = *base_ops;
univ8250_rsa_support(&univ8250_port_ops);
if (share_irqs)
irqflag = IRQF_SHARED;
for (i = 0, up = serial8250_ports;
i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
i++, up++) {
struct uart_port *port = &up->port;
port->iobase = old_serial_port[i].port;
port->irq = irq_canonicalize(old_serial_port[i].irq);
port->irqflags = 0;
port->uartclk = old_serial_port[i].baud_base * 16;
port->flags = old_serial_port[i].flags;
port->hub6 = 0;
port->membase = old_serial_port[i].iomem_base;
port->iotype = old_serial_port[i].io_type;
port->regshift = old_serial_port[i].iomem_reg_shift;
port->irqflags |= irqflag;
if (serial8250_isa_config != NULL)
serial8250_isa_config(i, &up->port, &up->capabilities);
}
}
static void __init
serial8250_register_ports(struct uart_driver *drv, struct device *dev)
{
int i;
for (i = 0; i < nr_uarts; i++) {
struct uart_8250_port *up = &serial8250_ports[i];
if (up->port.type == PORT_8250_CIR)
continue;
if (up->port.dev)
continue;
up->port.dev = dev;
if (uart_console_registered(&up->port))
pm_runtime_get_sync(up->port.dev);
serial8250_apply_quirks(up);
uart_add_one_port(drv, &up->port);
}
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
static void univ8250_console_write(struct console *co, const char *s,
unsigned int count)
{
struct uart_8250_port *up = &serial8250_ports[co->index];
serial8250_console_write(up, s, count);
}
static int univ8250_console_setup(struct console *co, char *options)
{
struct uart_8250_port *up;
struct uart_port *port;
int retval, i;
/*
* Check whether an invalid uart number has been specified, and
* if so, search for the first available port that does have
* console support.
*/
if (co->index >= UART_NR)
co->index = 0;
/*
* If the console is past the initial isa ports, init more ports up to
* co->index as needed and increment nr_uarts accordingly.
*/
for (i = nr_uarts; i <= co->index; i++) {
up = serial8250_setup_port(i);
if (!up)
return -ENODEV;
nr_uarts++;
}
port = &serial8250_ports[co->index].port;
/* link port to console */
port->cons = co;
retval = serial8250_console_setup(port, options, false);
if (retval != 0)
port->cons = NULL;
return retval;
}
static int univ8250_console_exit(struct console *co)
{
struct uart_port *port;
port = &serial8250_ports[co->index].port;
return serial8250_console_exit(port);
}
/**
* univ8250_console_match - non-standard console matching
* @co: registering console
* @name: name from console command line
* @idx: index from console command line
* @options: ptr to option string from console command line
*
* Only attempts to match console command lines of the form:
* console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
* console=uart[8250],0x<addr>[,<options>]
* This form is used to register an initial earlycon boot console and
* replace it with the serial8250_console at 8250 driver init.
*
* Performs console setup for a match (as required by interface)
* If no <options> are specified, then assume the h/w is already setup.
*
* Returns 0 if console matches; otherwise non-zero to use default matching
*/
static int univ8250_console_match(struct console *co, char *name, int idx,
char *options)
{
char match[] = "uart"; /* 8250-specific earlycon name */
unsigned char iotype;
resource_size_t addr;
int i;
if (strncmp(name, match, 4) != 0)
return -ENODEV;
if (uart_parse_earlycon(options, &iotype, &addr, &options))
return -ENODEV;
/* try to match the port specified on the command line */
for (i = 0; i < nr_uarts; i++) {
struct uart_port *port = &serial8250_ports[i].port;
if (port->iotype != iotype)
continue;
if ((iotype == UPIO_MEM || iotype == UPIO_MEM16 ||
iotype == UPIO_MEM32 || iotype == UPIO_MEM32BE)
&& (port->mapbase != addr))
continue;
if (iotype == UPIO_PORT && port->iobase != addr)
continue;
co->index = i;
port->cons = co;
return serial8250_console_setup(port, options, true);
}
return -ENODEV;
}
static struct console univ8250_console = {
.name = "ttyS",
.write = univ8250_console_write,
.device = uart_console_device,
.setup = univ8250_console_setup,
.exit = univ8250_console_exit,
.match = univ8250_console_match,
.flags = CON_PRINTBUFFER | CON_ANYTIME,
.index = -1,
.data = &serial8250_reg,
};
static int __init univ8250_console_init(void)
{
if (nr_uarts == 0)
return -ENODEV;
serial8250_isa_init_ports();
register_console(&univ8250_console);
return 0;
}
console_initcall(univ8250_console_init);
#define SERIAL8250_CONSOLE (&univ8250_console)
#else
#define SERIAL8250_CONSOLE NULL
#endif
static struct uart_driver serial8250_reg = {
.owner = THIS_MODULE,
.driver_name = "serial",
.dev_name = "ttyS",
.major = TTY_MAJOR,
.minor = 64,
.cons = SERIAL8250_CONSOLE,
};
/*
* early_serial_setup - early registration for 8250 ports
*
* Setup an 8250 port structure prior to console initialisation. Use
* after console initialisation will cause undefined behaviour.
*/
int __init early_serial_setup(struct uart_port *port)
{
struct uart_port *p;
if (port->line >= ARRAY_SIZE(serial8250_ports) || nr_uarts == 0)
return -ENODEV;
serial8250_isa_init_ports();
p = &serial8250_ports[port->line].port;
p->iobase = port->iobase;
p->membase = port->membase;
p->irq = port->irq;
p->irqflags = port->irqflags;
p->uartclk = port->uartclk;
p->fifosize = port->fifosize;
p->regshift = port->regshift;
p->iotype = port->iotype;
p->flags = port->flags;
p->mapbase = port->mapbase;
p->mapsize = port->mapsize;
p->private_data = port->private_data;
p->type = port->type;
p->line = port->line;
serial8250_set_defaults(up_to_u8250p(p));
if (port->serial_in)
p->serial_in = port->serial_in;
if (port->serial_out)
p->serial_out = port->serial_out;
if (port->handle_irq)
p->handle_irq = port->handle_irq;
return 0;
}
/**
* serial8250_suspend_port - suspend one serial port
* @line: serial line number
*
* Suspend one serial port.
*/
void serial8250_suspend_port(int line)
{
struct uart_8250_port *up = &serial8250_ports[line];
struct uart_port *port = &up->port;
if (!console_suspend_enabled && uart_console(port) &&
port->type != PORT_8250) {
unsigned char canary = 0xa5;
serial_out(up, UART_SCR, canary);
if (serial_in(up, UART_SCR) == canary)
up->canary = canary;
}
uart_suspend_port(&serial8250_reg, port);
}
EXPORT_SYMBOL(serial8250_suspend_port);
/**
* serial8250_resume_port - resume one serial port
* @line: serial line number
*
* Resume one serial port.
*/
void serial8250_resume_port(int line)
{
struct uart_8250_port *up = &serial8250_ports[line];
struct uart_port *port = &up->port;
up->canary = 0;
if (up->capabilities & UART_NATSEMI) {
/* Ensure it's still in high speed mode */
serial_port_out(port, UART_LCR, 0xE0);
ns16550a_goto_highspeed(up);
serial_port_out(port, UART_LCR, 0);
port->uartclk = 921600*16;
}
uart_resume_port(&serial8250_reg, port);
}
EXPORT_SYMBOL(serial8250_resume_port);
/*
* Register a set of serial devices attached to a platform device. The
* list is terminated with a zero flags entry, which means we expect
* all entries to have at least UPF_BOOT_AUTOCONF set.
*/
static int serial8250_probe(struct platform_device *dev)
{
struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
struct uart_8250_port uart;
int ret, i, irqflag = 0;
memset(&uart, 0, sizeof(uart));
if (share_irqs)
irqflag = IRQF_SHARED;
for (i = 0; p && p->flags != 0; p++, i++) {
uart.port.iobase = p->iobase;
uart.port.membase = p->membase;
uart.port.irq = p->irq;
uart.port.irqflags = p->irqflags;
uart.port.uartclk = p->uartclk;
uart.port.regshift = p->regshift;
uart.port.iotype = p->iotype;
uart.port.flags = p->flags;
uart.port.mapbase = p->mapbase;
uart.port.mapsize = p->mapsize;
uart.port.hub6 = p->hub6;
uart.port.has_sysrq = p->has_sysrq;
uart.port.private_data = p->private_data;
uart.port.type = p->type;
uart.bugs = p->bugs;
uart.port.serial_in = p->serial_in;
uart.port.serial_out = p->serial_out;
uart.dl_read = p->dl_read;
uart.dl_write = p->dl_write;
uart.port.handle_irq = p->handle_irq;
uart.port.handle_break = p->handle_break;
uart.port.set_termios = p->set_termios;
uart.port.set_ldisc = p->set_ldisc;
uart.port.get_mctrl = p->get_mctrl;
uart.port.pm = p->pm;
uart.port.dev = &dev->dev;
uart.port.irqflags |= irqflag;
ret = serial8250_register_8250_port(&uart);
if (ret < 0) {
dev_err(&dev->dev, "unable to register port at index %d "
"(IO%lx MEM%llx IRQ%d): %d\n", i,
p->iobase, (unsigned long long)p->mapbase,
p->irq, ret);
}
}
return 0;
}
/*
* Remove serial ports registered against a platform device.
*/
static int serial8250_remove(struct platform_device *dev)
{
int i;
for (i = 0; i < nr_uarts; i++) {
struct uart_8250_port *up = &serial8250_ports[i];
if (up->port.dev == &dev->dev)
serial8250_unregister_port(i);
}
return 0;
}
static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
{
int i;
for (i = 0; i < UART_NR; i++) {
struct uart_8250_port *up = &serial8250_ports[i];
if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
uart_suspend_port(&serial8250_reg, &up->port);
}
return 0;
}
static int serial8250_resume(struct platform_device *dev)
{
int i;
for (i = 0; i < UART_NR; i++) {
struct uart_8250_port *up = &serial8250_ports[i];
if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
serial8250_resume_port(i);
}
return 0;
}
static struct platform_driver serial8250_isa_driver = {
.probe = serial8250_probe,
.remove = serial8250_remove,
.suspend = serial8250_suspend,
.resume = serial8250_resume,
.driver = {
.name = "serial8250",
},
};
/*
* This "device" covers _all_ ISA 8250-compatible serial devices listed
* in the table in include/asm/serial.h
*/
static struct platform_device *serial8250_isa_devs;
/*
* serial8250_register_8250_port and serial8250_unregister_port allows for
* 16x50 serial ports to be configured at run-time, to support PCMCIA
* modems and PCI multiport cards.
*/
static DEFINE_MUTEX(serial_mutex);
static struct uart_8250_port *serial8250_find_match_or_unused(const struct uart_port *port)
{
int i;
/*
* First, find a port entry which matches.
*/
for (i = 0; i < nr_uarts; i++)
if (uart_match_port(&serial8250_ports[i].port, port))
return &serial8250_ports[i];
/* try line number first if still available */
i = port->line;
if (i < nr_uarts && serial8250_ports[i].port.type == PORT_UNKNOWN &&
serial8250_ports[i].port.iobase == 0)
return &serial8250_ports[i];
/*
* We didn't find a matching entry, so look for the first
* free entry. We look for one which hasn't been previously
* used (indicated by zero iobase).
*/
for (i = 0; i < nr_uarts; i++)
if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
serial8250_ports[i].port.iobase == 0)
return &serial8250_ports[i];
/*
* That also failed. Last resort is to find any entry which
* doesn't have a real port associated with it.
*/
for (i = 0; i < nr_uarts; i++)
if (serial8250_ports[i].port.type == PORT_UNKNOWN)
return &serial8250_ports[i];
return NULL;
}
static void serial_8250_overrun_backoff_work(struct work_struct *work)
{
struct uart_8250_port *up =
container_of(to_delayed_work(work), struct uart_8250_port,
overrun_backoff);
struct uart_port *port = &up->port;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
up->ier |= UART_IER_RLSI | UART_IER_RDI;
up->port.read_status_mask |= UART_LSR_DR;
serial_out(up, UART_IER, up->ier);
spin_unlock_irqrestore(&port->lock, flags);
}
/**
* serial8250_register_8250_port - register a serial port
* @up: serial port template
*
* Configure the serial port specified by the request. If the
* port exists and is in use, it is hung up and unregistered
* first.
*
* The port is then probed and if necessary the IRQ is autodetected
* If this fails an error is returned.
*
* On success the port is ready to use and the line number is returned.
*/
int serial8250_register_8250_port(const struct uart_8250_port *up)
{
struct uart_8250_port *uart;
int ret = -ENOSPC;
if (up->port.uartclk == 0)
return -EINVAL;
mutex_lock(&serial_mutex);
uart = serial8250_find_match_or_unused(&up->port);
if (!uart) {
/*
* If the port is past the initial isa ports, initialize a new
* port and increment nr_uarts accordingly.
*/
uart = serial8250_setup_port(nr_uarts);
if (!uart)
goto unlock;
nr_uarts++;
}
if (uart->port.type != PORT_8250_CIR) {
struct mctrl_gpios *gpios;
if (uart->port.dev)
uart_remove_one_port(&serial8250_reg, &uart->port);
uart->port.ctrl_id = up->port.ctrl_id;
uart->port.port_id = up->port.port_id;
uart->port.iobase = up->port.iobase;
uart->port.membase = up->port.membase;
uart->port.irq = up->port.irq;
uart->port.irqflags = up->port.irqflags;
uart->port.uartclk = up->port.uartclk;
uart->port.fifosize = up->port.fifosize;
uart->port.regshift = up->port.regshift;
uart->port.iotype = up->port.iotype;
uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
uart->bugs = up->bugs;
uart->port.mapbase = up->port.mapbase;
uart->port.mapsize = up->port.mapsize;
uart->port.private_data = up->port.private_data;
uart->tx_loadsz = up->tx_loadsz;
uart->capabilities = up->capabilities;
uart->port.throttle = up->port.throttle;
uart->port.unthrottle = up->port.unthrottle;
uart->port.rs485_config = up->port.rs485_config;
uart->port.rs485_supported = up->port.rs485_supported;
uart->port.rs485 = up->port.rs485;
uart->rs485_start_tx = up->rs485_start_tx;
uart->rs485_stop_tx = up->rs485_stop_tx;
uart->lsr_save_mask = up->lsr_save_mask;
uart->dma = up->dma;
/* Take tx_loadsz from fifosize if it wasn't set separately */
if (uart->port.fifosize && !uart->tx_loadsz)
uart->tx_loadsz = uart->port.fifosize;
if (up->port.dev) {
uart->port.dev = up->port.dev;
ret = uart_get_rs485_mode(&uart->port);
if (ret)
goto err;
}
if (up->port.flags & UPF_FIXED_TYPE)
uart->port.type = up->port.type;
/*
* Only call mctrl_gpio_init(), if the device has no ACPI
* companion device
*/
if (!has_acpi_companion(uart->port.dev)) {
gpios = mctrl_gpio_init(&uart->port, 0);
if (IS_ERR(gpios)) {
ret = PTR_ERR(gpios);
goto err;
} else {
uart->gpios = gpios;
}
}
serial8250_set_defaults(uart);
/* Possibly override default I/O functions. */
if (up->port.serial_in)
uart->port.serial_in = up->port.serial_in;
if (up->port.serial_out)
uart->port.serial_out = up->port.serial_out;
if (up->port.handle_irq)
uart->port.handle_irq = up->port.handle_irq;
/* Possibly override set_termios call */
if (up->port.set_termios)
uart->port.set_termios = up->port.set_termios;
if (up->port.set_ldisc)
uart->port.set_ldisc = up->port.set_ldisc;
if (up->port.get_mctrl)
uart->port.get_mctrl = up->port.get_mctrl;
if (up->port.set_mctrl)
uart->port.set_mctrl = up->port.set_mctrl;
if (up->port.get_divisor)
uart->port.get_divisor = up->port.get_divisor;
if (up->port.set_divisor)
uart->port.set_divisor = up->port.set_divisor;
if (up->port.startup)
uart->port.startup = up->port.startup;
if (up->port.shutdown)
uart->port.shutdown = up->port.shutdown;
if (up->port.pm)
uart->port.pm = up->port.pm;
if (up->port.handle_break)
uart->port.handle_break = up->port.handle_break;
if (up->dl_read)
uart->dl_read = up->dl_read;
if (up->dl_write)
uart->dl_write = up->dl_write;
if (uart->port.type != PORT_8250_CIR) {
if (serial8250_isa_config != NULL)
serial8250_isa_config(0, &uart->port,
&uart->capabilities);
serial8250_apply_quirks(uart);
ret = uart_add_one_port(&serial8250_reg,
&uart->port);
if (ret)
goto err;
ret = uart->port.line;
} else {
dev_info(uart->port.dev,
"skipping CIR port at 0x%lx / 0x%llx, IRQ %d\n",
uart->port.iobase,
(unsigned long long)uart->port.mapbase,
uart->port.irq);
ret = 0;
}
if (!uart->lsr_save_mask)
uart->lsr_save_mask = LSR_SAVE_FLAGS; /* Use default LSR mask */
/* Initialise interrupt backoff work if required */
if (up->overrun_backoff_time_ms > 0) {
uart->overrun_backoff_time_ms =
up->overrun_backoff_time_ms;
INIT_DELAYED_WORK(&uart->overrun_backoff,
serial_8250_overrun_backoff_work);
} else {
uart->overrun_backoff_time_ms = 0;
}
}
unlock:
mutex_unlock(&serial_mutex);
return ret;
err:
uart->port.dev = NULL;
mutex_unlock(&serial_mutex);
return ret;
}
EXPORT_SYMBOL(serial8250_register_8250_port);
/**
* serial8250_unregister_port - remove a 16x50 serial port at runtime
* @line: serial line number
*
* Remove one serial port. This may not be called from interrupt
* context. We hand the port back to the our control.
*/
void serial8250_unregister_port(int line)
{
struct uart_8250_port *uart = &serial8250_ports[line];
mutex_lock(&serial_mutex);
if (uart->em485) {
unsigned long flags;
spin_lock_irqsave(&uart->port.lock, flags);
serial8250_em485_destroy(uart);
spin_unlock_irqrestore(&uart->port.lock, flags);
}
uart_remove_one_port(&serial8250_reg, &uart->port);
if (serial8250_isa_devs) {
uart->port.flags &= ~UPF_BOOT_AUTOCONF;
uart->port.type = PORT_UNKNOWN;
uart->port.dev = &serial8250_isa_devs->dev;
uart->port.port_id = line;
uart->capabilities = 0;
serial8250_init_port(uart);
serial8250_apply_quirks(uart);
uart_add_one_port(&serial8250_reg, &uart->port);
} else {
uart->port.dev = NULL;
}
mutex_unlock(&serial_mutex);
}
EXPORT_SYMBOL(serial8250_unregister_port);
static int __init serial8250_init(void)
{
int ret;
if (nr_uarts == 0)
return -ENODEV;
serial8250_isa_init_ports();
pr_info("Serial: 8250/16550 driver, %d ports, IRQ sharing %s\n",
nr_uarts, str_enabled_disabled(share_irqs));
#ifdef CONFIG_SPARC
ret = sunserial_register_minors(&serial8250_reg, UART_NR);
#else
serial8250_reg.nr = UART_NR;
ret = uart_register_driver(&serial8250_reg);
#endif
if (ret)
goto out;
ret = serial8250_pnp_init();
if (ret)
goto unreg_uart_drv;
serial8250_isa_devs = platform_device_alloc("serial8250",
PLAT8250_DEV_LEGACY);
if (!serial8250_isa_devs) {
ret = -ENOMEM;
goto unreg_pnp;
}
ret = platform_device_add(serial8250_isa_devs);
if (ret)
goto put_dev;
serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
ret = platform_driver_register(&serial8250_isa_driver);
if (ret == 0)
goto out;
platform_device_del(serial8250_isa_devs);
put_dev:
platform_device_put(serial8250_isa_devs);
unreg_pnp:
serial8250_pnp_exit();
unreg_uart_drv:
#ifdef CONFIG_SPARC
sunserial_unregister_minors(&serial8250_reg, UART_NR);
#else
uart_unregister_driver(&serial8250_reg);
#endif
out:
return ret;
}
static void __exit serial8250_exit(void)
{
struct platform_device *isa_dev = serial8250_isa_devs;
/*
* This tells serial8250_unregister_port() not to re-register
* the ports (thereby making serial8250_isa_driver permanently
* in use.)
*/
serial8250_isa_devs = NULL;
platform_driver_unregister(&serial8250_isa_driver);
platform_device_unregister(isa_dev);
serial8250_pnp_exit();
#ifdef CONFIG_SPARC
sunserial_unregister_minors(&serial8250_reg, UART_NR);
#else
uart_unregister_driver(&serial8250_reg);
#endif
}
module_init(serial8250_init);
module_exit(serial8250_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
module_param_hw(share_irqs, uint, other, 0644);
MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices (unsafe)");
module_param(nr_uarts, uint, 0644);
MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
module_param(skip_txen_test, uint, 0644);
MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
#ifdef CONFIG_SERIAL_8250_RSA
module_param_hw_array(probe_rsa, ulong, ioport, &probe_rsa_count, 0444);
MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
#endif
MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
#ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
#ifndef MODULE
/* This module was renamed to 8250_core in 3.7. Keep the old "8250" name
* working as well for the module options so we don't break people. We
* need to keep the names identical and the convenient macros will happily
* refuse to let us do that by failing the build with redefinition errors
* of global variables. So we stick them inside a dummy function to avoid
* those conflicts. The options still get parsed, and the redefined
* MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
*
* This is hacky. I'm sorry.
*/
static void __used s8250_options(void)
{
#undef MODULE_PARAM_PREFIX
#define MODULE_PARAM_PREFIX "8250_core."
module_param_cb(share_irqs, ¶m_ops_uint, &share_irqs, 0644);
module_param_cb(nr_uarts, ¶m_ops_uint, &nr_uarts, 0644);
module_param_cb(skip_txen_test, ¶m_ops_uint, &skip_txen_test, 0644);
#ifdef CONFIG_SERIAL_8250_RSA
__module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
¶m_array_ops, .arr = &__param_arr_probe_rsa,
0444, -1, 0);
#endif
}
#else
MODULE_ALIAS("8250_core");
#endif
#endif
| linux-master | drivers/tty/serial/8250/8250_core.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Masahiro Yamada <[email protected]>
*/
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "8250.h"
/*
* This hardware is similar to 8250, but its register map is a bit different:
* - MMIO32 (regshift = 2)
* - FCR is not at 2, but 3
* - LCR and MCR are not at 3 and 4, they share 4
* - No SCR (Instead, CHAR can be used as a scratch register)
* - Divisor latch at 9, no divisor latch access bit
*/
#define UNIPHIER_UART_REGSHIFT 2
/* bit[15:8] = CHAR, bit[7:0] = FCR */
#define UNIPHIER_UART_CHAR_FCR (3 << (UNIPHIER_UART_REGSHIFT))
/* bit[15:8] = LCR, bit[7:0] = MCR */
#define UNIPHIER_UART_LCR_MCR (4 << (UNIPHIER_UART_REGSHIFT))
/* Divisor Latch Register */
#define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT))
struct uniphier8250_priv {
int line;
struct clk *clk;
spinlock_t atomic_write_lock;
};
#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init uniphier_early_console_setup(struct earlycon_device *device,
const char *options)
{
if (!device->port.membase)
return -ENODEV;
/* This hardware always expects MMIO32 register interface. */
device->port.iotype = UPIO_MEM32;
device->port.regshift = UNIPHIER_UART_REGSHIFT;
/*
* Do not touch the divisor register in early_serial8250_setup();
* we assume it has been initialized by a boot loader.
*/
device->baud = 0;
return early_serial8250_setup(device, options);
}
OF_EARLYCON_DECLARE(uniphier, "socionext,uniphier-uart",
uniphier_early_console_setup);
#endif
/*
* The register map is slightly different from that of 8250.
* IO callbacks must be overridden for correct access to FCR, LCR, MCR and SCR.
*/
static unsigned int uniphier_serial_in(struct uart_port *p, int offset)
{
unsigned int valshift = 0;
switch (offset) {
case UART_SCR:
/* No SCR for this hardware. Use CHAR as a scratch register */
valshift = 8;
offset = UNIPHIER_UART_CHAR_FCR;
break;
case UART_LCR:
valshift = 8;
fallthrough;
case UART_MCR:
offset = UNIPHIER_UART_LCR_MCR;
break;
default:
offset <<= UNIPHIER_UART_REGSHIFT;
break;
}
/*
* The return value must be masked with 0xff because some registers
* share the same offset that must be accessed by 32-bit write/read.
* 8 or 16 bit access to this hardware result in unexpected behavior.
*/
return (readl(p->membase + offset) >> valshift) & 0xff;
}
static void uniphier_serial_out(struct uart_port *p, int offset, int value)
{
unsigned int valshift = 0;
bool normal = false;
switch (offset) {
case UART_SCR:
/* No SCR for this hardware. Use CHAR as a scratch register */
valshift = 8;
fallthrough;
case UART_FCR:
offset = UNIPHIER_UART_CHAR_FCR;
break;
case UART_LCR:
valshift = 8;
/* Divisor latch access bit does not exist. */
value &= ~UART_LCR_DLAB;
fallthrough;
case UART_MCR:
offset = UNIPHIER_UART_LCR_MCR;
break;
default:
offset <<= UNIPHIER_UART_REGSHIFT;
normal = true;
break;
}
if (normal) {
writel(value, p->membase + offset);
} else {
/*
* Special case: two registers share the same address that
* must be 32-bit accessed. As this is not longer atomic safe,
* take a lock just in case.
*/
struct uniphier8250_priv *priv = p->private_data;
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&priv->atomic_write_lock, flags);
tmp = readl(p->membase + offset);
tmp &= ~(0xff << valshift);
tmp |= value << valshift;
writel(tmp, p->membase + offset);
spin_unlock_irqrestore(&priv->atomic_write_lock, flags);
}
}
/*
* This hardware does not have the divisor latch access bit.
* The divisor latch register exists at different address.
* Override dl_read/write callbacks.
*/
static u32 uniphier_serial_dl_read(struct uart_8250_port *up)
{
return readl(up->port.membase + UNIPHIER_UART_DLR);
}
static void uniphier_serial_dl_write(struct uart_8250_port *up, u32 value)
{
writel(value, up->port.membase + UNIPHIER_UART_DLR);
}
static int uniphier_uart_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct uart_8250_port up;
struct uniphier8250_priv *priv;
struct resource *regs;
void __iomem *membase;
int irq;
int ret;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(dev, "failed to get memory resource\n");
return -EINVAL;
}
membase = devm_ioremap(dev, regs->start, resource_size(regs));
if (!membase)
return -ENOMEM;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
memset(&up, 0, sizeof(up));
ret = of_alias_get_id(dev->of_node, "serial");
if (ret < 0) {
dev_err(dev, "failed to get alias id\n");
return ret;
}
up.port.line = ret;
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk)) {
dev_err(dev, "failed to get clock\n");
return PTR_ERR(priv->clk);
}
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
up.port.uartclk = clk_get_rate(priv->clk);
spin_lock_init(&priv->atomic_write_lock);
up.port.dev = dev;
up.port.private_data = priv;
up.port.mapbase = regs->start;
up.port.mapsize = resource_size(regs);
up.port.membase = membase;
up.port.irq = irq;
up.port.type = PORT_16550A;
up.port.iotype = UPIO_MEM32;
up.port.fifosize = 64;
up.port.regshift = UNIPHIER_UART_REGSHIFT;
up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE;
up.capabilities = UART_CAP_FIFO;
if (of_property_read_bool(dev->of_node, "auto-flow-control"))
up.capabilities |= UART_CAP_AFE;
up.port.serial_in = uniphier_serial_in;
up.port.serial_out = uniphier_serial_out;
up.dl_read = uniphier_serial_dl_read;
up.dl_write = uniphier_serial_dl_write;
ret = serial8250_register_8250_port(&up);
if (ret < 0) {
dev_err(dev, "failed to register 8250 port\n");
clk_disable_unprepare(priv->clk);
return ret;
}
priv->line = ret;
platform_set_drvdata(pdev, priv);
return 0;
}
static int uniphier_uart_remove(struct platform_device *pdev)
{
struct uniphier8250_priv *priv = platform_get_drvdata(pdev);
serial8250_unregister_port(priv->line);
clk_disable_unprepare(priv->clk);
return 0;
}
static int __maybe_unused uniphier_uart_suspend(struct device *dev)
{
struct uniphier8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
serial8250_suspend_port(priv->line);
if (!uart_console(&up->port) || console_suspend_enabled)
clk_disable_unprepare(priv->clk);
return 0;
}
static int __maybe_unused uniphier_uart_resume(struct device *dev)
{
struct uniphier8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
int ret;
if (!uart_console(&up->port) || console_suspend_enabled) {
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
}
serial8250_resume_port(priv->line);
return 0;
}
static const struct dev_pm_ops uniphier_uart_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(uniphier_uart_suspend, uniphier_uart_resume)
};
static const struct of_device_id uniphier_uart_match[] = {
{ .compatible = "socionext,uniphier-uart" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, uniphier_uart_match);
static struct platform_driver uniphier_uart_platform_driver = {
.probe = uniphier_uart_probe,
.remove = uniphier_uart_remove,
.driver = {
.name = "uniphier-uart",
.of_match_table = uniphier_uart_match,
.pm = &uniphier_uart_pm_ops,
},
};
module_platform_driver(uniphier_uart_platform_driver);
MODULE_AUTHOR("Masahiro Yamada <[email protected]>");
MODULE_DESCRIPTION("UniPhier UART driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_uniphier.c |
// SPDX-License-Identifier: GPL-2.0
/*
* 8250-core based driver for the OMAP internal UART
*
* based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
*
* Copyright (C) 2014 Sebastian Andrzej Siewior
*
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/tty_flip.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>
#include <linux/pm_qos.h>
#include <linux/pm_wakeirq.h>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
#include "8250.h"
#define DEFAULT_CLK_SPEED 48000000
#define OMAP_UART_REGSHIFT 2
#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
#define OMAP_DMA_TX_KICK (1 << 2)
/*
* See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
* The same errata is applicable to AM335x and DRA7x processors too.
*/
#define UART_ERRATA_CLOCK_DISABLE (1 << 3)
#define UART_HAS_EFR2 BIT(4)
#define UART_HAS_RHR_IT_DIS BIT(5)
#define UART_RX_TIMEOUT_QUIRK BIT(6)
#define UART_HAS_NATIVE_RS485 BIT(7)
#define OMAP_UART_FCR_RX_TRIG 6
#define OMAP_UART_FCR_TX_TRIG 4
/* SCR register bitmasks */
#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
#define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
/* MVR register bitmasks */
#define OMAP_UART_MVR_SCHEME_SHIFT 30
#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
#define OMAP_UART_MVR_MAJ_MASK 0x700
#define OMAP_UART_MVR_MAJ_SHIFT 8
#define OMAP_UART_MVR_MIN_MASK 0x3f
/* SYSC register bitmasks */
#define OMAP_UART_SYSC_SOFTRESET (1 << 1)
/* SYSS register bitmasks */
#define OMAP_UART_SYSS_RESETDONE (1 << 0)
#define UART_TI752_TLR_TX 0
#define UART_TI752_TLR_RX 4
#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
#define TRIGGER_FCR_MASK(x) (x & 3)
/* Enable XON/XOFF flow control on output */
#define OMAP_UART_SW_TX 0x08
/* Enable XON/XOFF flow control on input */
#define OMAP_UART_SW_RX 0x02
#define OMAP_UART_WER_MOD_WKUP 0x7f
#define OMAP_UART_TX_WAKEUP_EN (1 << 7)
#define TX_TRIGGER 1
#define RX_TRIGGER 48
#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
#define OMAP_UART_REV_46 0x0406
#define OMAP_UART_REV_52 0x0502
#define OMAP_UART_REV_63 0x0603
/* Interrupt Enable Register 2 */
#define UART_OMAP_IER2 0x1B
#define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
/* Mode Definition Register 3 */
#define UART_OMAP_MDR3 0x20
#define UART_OMAP_MDR3_DIR_POL BIT(3)
#define UART_OMAP_MDR3_DIR_EN BIT(4)
/* Enhanced features register 2 */
#define UART_OMAP_EFR2 0x23
#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
/* RX FIFO occupancy indicator */
#define UART_OMAP_RX_LVL 0x19
struct omap8250_priv {
void __iomem *membase;
int line;
u8 habit;
u8 mdr1;
u8 mdr3;
u8 efr;
u8 scr;
u8 wer;
u8 xon;
u8 xoff;
u8 delayed_restore;
u16 quot;
u8 tx_trigger;
u8 rx_trigger;
bool is_suspending;
int wakeirq;
int wakeups_enabled;
u32 latency;
u32 calc_latency;
struct pm_qos_request pm_qos_request;
struct work_struct qos_work;
struct uart_8250_dma omap8250_dma;
spinlock_t rx_dma_lock;
bool rx_dma_broken;
bool throttled;
};
struct omap8250_dma_params {
u32 rx_size;
u8 rx_trigger;
u8 tx_trigger;
};
struct omap8250_platdata {
struct omap8250_dma_params *dma_params;
u8 habit;
};
#ifdef CONFIG_SERIAL_8250_DMA
static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
#else
static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
#endif
static u32 uart_read(struct omap8250_priv *priv, u32 reg)
{
return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
}
/*
* Called on runtime PM resume path from omap8250_restore_regs(), and
* omap8250_set_mctrl().
*/
static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct omap8250_priv *priv = up->port.private_data;
u8 lcr;
serial8250_do_set_mctrl(port, mctrl);
if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
/*
* Turn off autoRTS if RTS is lowered and restore autoRTS
* setting if RTS is raised
*/
lcr = serial_in(up, UART_LCR);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
priv->efr |= UART_EFR_RTS;
else
priv->efr &= ~UART_EFR_RTS;
serial_out(up, UART_EFR, priv->efr);
serial_out(up, UART_LCR, lcr);
}
}
static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
int err;
err = pm_runtime_resume_and_get(port->dev);
if (err)
return;
__omap8250_set_mctrl(port, mctrl);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
}
/*
* Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
* The access to uart register after MDR1 Access
* causes UART to corrupt data.
*
* Need a delay =
* 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
* give 10 times as much
*/
static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
struct omap8250_priv *priv)
{
serial_out(up, UART_OMAP_MDR1, priv->mdr1);
udelay(2);
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
UART_FCR_CLEAR_RCVR);
}
static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
struct omap8250_priv *priv)
{
unsigned int uartclk = port->uartclk;
unsigned int div_13, div_16;
unsigned int abs_d13, abs_d16;
/*
* Old custom speed handling.
*/
if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
priv->quot = port->custom_divisor & UART_DIV_MAX;
/*
* I assume that nobody is using this. But hey, if somebody
* would like to specify the divisor _and_ the mode then the
* driver is ready and waiting for it.
*/
if (port->custom_divisor & (1 << 16))
priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
else
priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
return;
}
div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
if (!div_13)
div_13 = 1;
if (!div_16)
div_16 = 1;
abs_d13 = abs(baud - uartclk / 13 / div_13);
abs_d16 = abs(baud - uartclk / 16 / div_16);
if (abs_d13 >= abs_d16) {
priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
priv->quot = div_16;
} else {
priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
priv->quot = div_13;
}
}
static void omap8250_update_scr(struct uart_8250_port *up,
struct omap8250_priv *priv)
{
u8 old_scr;
old_scr = serial_in(up, UART_OMAP_SCR);
if (old_scr == priv->scr)
return;
/*
* The manual recommends not to enable the DMA mode selector in the SCR
* (instead of the FCR) register _and_ selecting the DMA mode as one
* register write because this may lead to malfunction.
*/
if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
serial_out(up, UART_OMAP_SCR,
priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
serial_out(up, UART_OMAP_SCR, priv->scr);
}
static void omap8250_update_mdr1(struct uart_8250_port *up,
struct omap8250_priv *priv)
{
if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
omap_8250_mdr1_errataset(up, priv);
else
serial_out(up, UART_OMAP_MDR1, priv->mdr1);
}
static void omap8250_restore_regs(struct uart_8250_port *up)
{
struct omap8250_priv *priv = up->port.private_data;
struct uart_8250_dma *dma = up->dma;
u8 mcr = serial8250_in_MCR(up);
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&up->port.lock);
if (dma && dma->tx_running) {
/*
* TCSANOW requests the change to occur immediately however if
* we have a TX-DMA operation in progress then it has been
* observed that it might stall and never complete. Therefore we
* delay DMA completes to prevent this hang from happen.
*/
priv->delayed_restore = 1;
return;
}
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, UART_EFR_ECB);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
serial_out(up, UART_FCR, up->fcr);
omap8250_update_scr(up, priv);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
OMAP_UART_TCR_HALT(52));
serial_out(up, UART_TI752_TLR,
TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
serial_out(up, UART_LCR, 0);
/* drop TCR + TLR access, we setup XON/XOFF later */
serial8250_out_MCR(up, mcr);
serial_out(up, UART_IER, up->ier);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_dl_write(up, priv->quot);
serial_out(up, UART_EFR, priv->efr);
/* Configure flow control */
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_XON1, priv->xon);
serial_out(up, UART_XOFF1, priv->xoff);
serial_out(up, UART_LCR, up->lcr);
omap8250_update_mdr1(up, priv);
__omap8250_set_mctrl(&up->port, up->port.mctrl);
serial_out(up, UART_OMAP_MDR3, priv->mdr3);
if (up->port.rs485.flags & SER_RS485_ENABLED &&
up->port.rs485_config == serial8250_em485_config)
serial8250_em485_stop_tx(up);
}
/*
* OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
* some differences in how we want to handle flow control.
*/
static void omap_8250_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct omap8250_priv *priv = up->port.private_data;
unsigned char cval = 0;
unsigned int baud;
cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
if (termios->c_cflag & CSTOPB)
cval |= UART_LCR_STOP;
if (termios->c_cflag & PARENB)
cval |= UART_LCR_PARITY;
if (!(termios->c_cflag & PARODD))
cval |= UART_LCR_EPAR;
if (termios->c_cflag & CMSPAR)
cval |= UART_LCR_SPAR;
/*
* Ask the core to calculate the divisor for us.
*/
baud = uart_get_baud_rate(port, termios, old,
port->uartclk / 16 / UART_DIV_MAX,
port->uartclk / 13);
omap_8250_get_divisor(port, baud, priv);
/*
* Ok, we're now changing the port state. Do it with
* interrupts disabled.
*/
pm_runtime_get_sync(port->dev);
spin_lock_irq(&port->lock);
/*
* Update the per-port timeout.
*/
uart_update_timeout(port, termios->c_cflag, baud);
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
if (termios->c_iflag & INPCK)
up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
if (termios->c_iflag & (IGNBRK | PARMRK))
up->port.read_status_mask |= UART_LSR_BI;
/*
* Characters to ignore
*/
up->port.ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR)
up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
if (termios->c_iflag & IGNBRK) {
up->port.ignore_status_mask |= UART_LSR_BI;
/*
* If we're ignoring parity and break indicators,
* ignore overruns too (for real raw support).
*/
if (termios->c_iflag & IGNPAR)
up->port.ignore_status_mask |= UART_LSR_OE;
}
/*
* ignore all characters if CREAD is not set
*/
if ((termios->c_cflag & CREAD) == 0)
up->port.ignore_status_mask |= UART_LSR_DR;
/*
* Modem status interrupts
*/
up->ier &= ~UART_IER_MSI;
if (UART_ENABLE_MS(&up->port, termios->c_cflag))
up->ier |= UART_IER_MSI;
up->lcr = cval;
/* Up to here it was mostly serial8250_do_set_termios() */
/*
* We enable TRIG_GRANU for RX and TX and additionally we set
* SCR_TX_EMPTY bit. The result is the following:
* - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
* - less than RX_TRIGGER number of bytes will also cause an interrupt
* once the UART decides that there no new bytes arriving.
* - Once THRE is enabled, the interrupt will be fired once the FIFO is
* empty - the trigger level is ignored here.
*
* Once DMA is enabled:
* - UART will assert the TX DMA line once there is room for TX_TRIGGER
* bytes in the TX FIFO. On each assert the DMA engine will move
* TX_TRIGGER bytes into the FIFO.
* - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
* the FIFO and move RX_TRIGGER bytes.
* This is because threshold and trigger values are the same.
*/
up->fcr = UART_FCR_ENABLE_FIFO;
up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
if (up->dma)
priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
OMAP_UART_SCR_DMAMODE_CTL;
priv->xon = termios->c_cc[VSTART];
priv->xoff = termios->c_cc[VSTOP];
priv->efr = 0;
up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
priv->efr |= UART_EFR_CTS;
} else if (up->port.flags & UPF_SOFT_FLOW) {
/*
* OMAP rx s/w flow control is borked; the transmitter remains
* stuck off even if rx flow control is subsequently disabled
*/
/*
* IXOFF Flag:
* Enable XON/XOFF flow control on output.
* Transmit XON1, XOFF1
*/
if (termios->c_iflag & IXOFF) {
up->port.status |= UPSTAT_AUTOXOFF;
priv->efr |= OMAP_UART_SW_TX;
}
}
omap8250_restore_regs(up);
spin_unlock_irq(&up->port.lock);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
/* calculate wakeup latency constraint */
priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
priv->latency = priv->calc_latency;
schedule_work(&priv->qos_work);
/* Don't rewrite B0 */
if (tty_termios_baud_rate(termios))
tty_termios_encode_baud_rate(termios, baud, baud);
}
/* same as 8250 except that we may have extra flow bits set in EFR */
static void omap_8250_pm(struct uart_port *port, unsigned int state,
unsigned int oldstate)
{
struct uart_8250_port *up = up_to_u8250p(port);
u8 efr;
pm_runtime_get_sync(port->dev);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
efr = serial_in(up, UART_EFR);
serial_out(up, UART_EFR, efr | UART_EFR_ECB);
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, efr);
serial_out(up, UART_LCR, 0);
spin_unlock_irq(&port->lock);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
}
static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
struct omap8250_priv *priv)
{
static const struct soc_device_attribute k3_soc_devices[] = {
{ .family = "AM65X", },
{ .family = "J721E", .revision = "SR1.0" },
{ /* sentinel */ }
};
u32 mvr, scheme;
u16 revision, major, minor;
mvr = uart_read(priv, UART_OMAP_MVER);
/* Check revision register scheme */
scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
switch (scheme) {
case 0: /* Legacy Scheme: OMAP2/3 */
/* MINOR_REV[0:4], MAJOR_REV[4:7] */
major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
break;
case 1:
/* New Scheme: OMAP4+ */
/* MINOR_REV[0:5], MAJOR_REV[8:10] */
major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
OMAP_UART_MVR_MAJ_SHIFT;
minor = (mvr & OMAP_UART_MVR_MIN_MASK);
break;
default:
dev_warn(up->port.dev,
"Unknown revision, defaulting to highest\n");
/* highest possible revision */
major = 0xff;
minor = 0xff;
}
/* normalize revision for the driver */
revision = UART_BUILD_REVISION(major, minor);
switch (revision) {
case OMAP_UART_REV_46:
priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
break;
case OMAP_UART_REV_52:
priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
OMAP_UART_WER_HAS_TX_WAKEUP;
break;
case OMAP_UART_REV_63:
priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
OMAP_UART_WER_HAS_TX_WAKEUP;
break;
default:
break;
}
/*
* AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
* don't have RHR_IT_DIS bit in IER2 register. So drop to flag
* to enable errata workaround.
*/
if (soc_device_match(k3_soc_devices))
priv->habit &= ~UART_HAS_RHR_IT_DIS;
}
static void omap8250_uart_qos_work(struct work_struct *work)
{
struct omap8250_priv *priv;
priv = container_of(work, struct omap8250_priv, qos_work);
cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
}
#ifdef CONFIG_SERIAL_8250_DMA
static int omap_8250_dma_handle_irq(struct uart_port *port);
#endif
static irqreturn_t omap8250_irq(int irq, void *dev_id)
{
struct omap8250_priv *priv = dev_id;
struct uart_8250_port *up = serial8250_get_port(priv->line);
struct uart_port *port = &up->port;
unsigned int iir, lsr;
int ret;
#ifdef CONFIG_SERIAL_8250_DMA
if (up->dma) {
ret = omap_8250_dma_handle_irq(port);
return IRQ_RETVAL(ret);
}
#endif
serial8250_rpm_get(up);
lsr = serial_port_in(port, UART_LSR);
iir = serial_port_in(port, UART_IIR);
ret = serial8250_handle_irq(port, iir);
/*
* On K3 SoCs, it is observed that RX TIMEOUT is signalled after
* FIFO has been drained, in which case a dummy read of RX FIFO
* is required to clear RX TIMEOUT condition.
*/
if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
(iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
serial_port_in(port, UART_RX);
}
/* Stop processing interrupts on input overrun */
if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
unsigned long delay;
/* Synchronize UART_IER access against the console. */
spin_lock(&port->lock);
up->ier = port->serial_in(port, UART_IER);
if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
port->ops->stop_rx(port);
} else {
/* Keep restarting the timer until
* the input overrun subsides.
*/
cancel_delayed_work(&up->overrun_backoff);
}
spin_unlock(&port->lock);
delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
schedule_delayed_work(&up->overrun_backoff, delay);
}
serial8250_rpm_put(up);
return IRQ_RETVAL(ret);
}
static int omap_8250_startup(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct omap8250_priv *priv = port->private_data;
struct uart_8250_dma *dma = &priv->omap8250_dma;
int ret;
if (priv->wakeirq) {
ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
if (ret)
return ret;
}
pm_runtime_get_sync(port->dev);
serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
serial_out(up, UART_LCR, UART_LCR_WLEN8);
up->lsr_saved_flags = 0;
up->msr_saved_flags = 0;
/* Disable DMA for console UART */
if (dma->fn && !uart_console(port)) {
up->dma = &priv->omap8250_dma;
ret = serial8250_request_dma(up);
if (ret) {
dev_warn_ratelimited(port->dev,
"failed to request DMA\n");
up->dma = NULL;
}
} else {
up->dma = NULL;
}
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
up->ier = UART_IER_RLSI | UART_IER_RDI;
serial_out(up, UART_IER, up->ier);
spin_unlock_irq(&port->lock);
#ifdef CONFIG_PM
up->capabilities |= UART_CAP_RPM;
#endif
/* Enable module level wake up */
priv->wer = OMAP_UART_WER_MOD_WKUP;
if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
priv->wer |= OMAP_UART_TX_WAKEUP_EN;
serial_out(up, UART_OMAP_WER, priv->wer);
if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
spin_lock_irq(&port->lock);
up->dma->rx_dma(up);
spin_unlock_irq(&port->lock);
}
enable_irq(up->port.irq);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
return 0;
}
static void omap_8250_shutdown(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct omap8250_priv *priv = port->private_data;
flush_work(&priv->qos_work);
if (up->dma)
omap_8250_rx_dma_flush(up);
pm_runtime_get_sync(port->dev);
serial_out(up, UART_OMAP_WER, 0);
if (priv->habit & UART_HAS_EFR2)
serial_out(up, UART_OMAP_EFR2, 0x0);
/* Synchronize UART_IER access against the console. */
spin_lock_irq(&port->lock);
up->ier = 0;
serial_out(up, UART_IER, 0);
spin_unlock_irq(&port->lock);
disable_irq_nosync(up->port.irq);
dev_pm_clear_wake_irq(port->dev);
serial8250_release_dma(up);
up->dma = NULL;
/*
* Disable break condition and FIFOs
*/
if (up->lcr & UART_LCR_SBC)
serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
}
static void omap_8250_throttle(struct uart_port *port)
{
struct omap8250_priv *priv = port->private_data;
unsigned long flags;
pm_runtime_get_sync(port->dev);
spin_lock_irqsave(&port->lock, flags);
port->ops->stop_rx(port);
priv->throttled = true;
spin_unlock_irqrestore(&port->lock, flags);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
}
static void omap_8250_unthrottle(struct uart_port *port)
{
struct omap8250_priv *priv = port->private_data;
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
pm_runtime_get_sync(port->dev);
/* Synchronize UART_IER access against the console. */
spin_lock_irqsave(&port->lock, flags);
priv->throttled = false;
if (up->dma)
up->dma->rx_dma(up);
up->ier |= UART_IER_RLSI | UART_IER_RDI;
port->read_status_mask |= UART_LSR_DR;
serial_out(up, UART_IER, up->ier);
spin_unlock_irqrestore(&port->lock, flags);
pm_runtime_mark_last_busy(port->dev);
pm_runtime_put_autosuspend(port->dev);
}
static int omap8250_rs485_config(struct uart_port *port,
struct ktermios *termios,
struct serial_rs485 *rs485)
{
struct omap8250_priv *priv = port->private_data;
struct uart_8250_port *up = up_to_u8250p(port);
u32 fixed_delay_rts_before_send = 0;
u32 fixed_delay_rts_after_send = 0;
unsigned int baud;
/*
* There is a fixed delay of 3 bit clock cycles after the TX shift
* register is going empty to allow time for the stop bit to transition
* through the transceiver before direction is changed to receive.
*
* Additionally there appears to be a 1 bit clock delay between writing
* to the THR register and transmission of the start bit, per page 8783
* of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
*/
if (priv->quot) {
if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE)
baud = port->uartclk / (16 * priv->quot);
else
baud = port->uartclk / (13 * priv->quot);
fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud;
fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud;
}
/*
* Fall back to RS485 software emulation if the UART is missing
* hardware support, if the device tree specifies an mctrl_gpio
* (indicates that RTS is unavailable due to a pinmux conflict)
* or if the requested delays exceed the fixed hardware delays.
*/
if (!(priv->habit & UART_HAS_NATIVE_RS485) ||
mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
rs485->delay_rts_after_send > fixed_delay_rts_after_send ||
rs485->delay_rts_before_send > fixed_delay_rts_before_send) {
priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
serial_out(up, UART_OMAP_MDR3, priv->mdr3);
port->rs485_config = serial8250_em485_config;
return serial8250_em485_config(port, termios, rs485);
}
rs485->delay_rts_after_send = fixed_delay_rts_after_send;
rs485->delay_rts_before_send = fixed_delay_rts_before_send;
if (rs485->flags & SER_RS485_ENABLED)
priv->mdr3 |= UART_OMAP_MDR3_DIR_EN;
else
priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
/*
* Retain same polarity semantics as RS485 software emulation,
* i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send.
*/
if (rs485->flags & SER_RS485_RTS_ON_SEND)
priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL;
else
priv->mdr3 |= UART_OMAP_MDR3_DIR_POL;
serial_out(up, UART_OMAP_MDR3, priv->mdr3);
return 0;
}
#ifdef CONFIG_SERIAL_8250_DMA
static int omap_8250_rx_dma(struct uart_8250_port *p);
/* Must be called while priv->rx_dma_lock is held */
static void __dma_rx_do_complete(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
struct tty_port *tty_port = &p->port.state->port;
struct omap8250_priv *priv = p->port.private_data;
struct dma_chan *rxchan = dma->rxchan;
dma_cookie_t cookie;
struct dma_tx_state state;
int count;
int ret;
u32 reg;
if (!dma->rx_running)
goto out;
cookie = dma->rx_cookie;
dma->rx_running = 0;
/* Re-enable RX FIFO interrupt now that transfer is complete */
if (priv->habit & UART_HAS_RHR_IT_DIS) {
reg = serial_in(p, UART_OMAP_IER2);
reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
}
dmaengine_tx_status(rxchan, cookie, &state);
count = dma->rx_size - state.residue + state.in_flight_bytes;
if (count < dma->rx_size) {
dmaengine_terminate_async(rxchan);
/*
* Poll for teardown to complete which guarantees in
* flight data is drained.
*/
if (state.in_flight_bytes) {
int poll_count = 25;
while (dmaengine_tx_status(rxchan, cookie, NULL) &&
poll_count--)
cpu_relax();
if (poll_count == -1)
dev_err(p->port.dev, "teardown incomplete\n");
}
}
if (!count)
goto out;
ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
p->port.icount.rx += ret;
p->port.icount.buf_overrun += count - ret;
out:
tty_flip_buffer_push(tty_port);
}
static void __dma_rx_complete(void *param)
{
struct uart_8250_port *p = param;
struct omap8250_priv *priv = p->port.private_data;
struct uart_8250_dma *dma = p->dma;
struct dma_tx_state state;
unsigned long flags;
/* Synchronize UART_IER access against the console. */
spin_lock_irqsave(&p->port.lock, flags);
/*
* If the tx status is not DMA_COMPLETE, then this is a delayed
* completion callback. A previous RX timeout flush would have
* already pushed the data, so exit.
*/
if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
DMA_COMPLETE) {
spin_unlock_irqrestore(&p->port.lock, flags);
return;
}
__dma_rx_do_complete(p);
if (!priv->throttled) {
p->ier |= UART_IER_RLSI | UART_IER_RDI;
serial_out(p, UART_IER, p->ier);
if (!(priv->habit & UART_HAS_EFR2))
omap_8250_rx_dma(p);
}
spin_unlock_irqrestore(&p->port.lock, flags);
}
static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
{
struct omap8250_priv *priv = p->port.private_data;
struct uart_8250_dma *dma = p->dma;
struct dma_tx_state state;
unsigned long flags;
int ret;
spin_lock_irqsave(&priv->rx_dma_lock, flags);
if (!dma->rx_running) {
spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
return;
}
ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
if (ret == DMA_IN_PROGRESS) {
ret = dmaengine_pause(dma->rxchan);
if (WARN_ON_ONCE(ret))
priv->rx_dma_broken = true;
}
__dma_rx_do_complete(p);
spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
}
static int omap_8250_rx_dma(struct uart_8250_port *p)
{
struct omap8250_priv *priv = p->port.private_data;
struct uart_8250_dma *dma = p->dma;
int err = 0;
struct dma_async_tx_descriptor *desc;
unsigned long flags;
u32 reg;
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&p->port.lock);
if (priv->rx_dma_broken)
return -EINVAL;
spin_lock_irqsave(&priv->rx_dma_lock, flags);
if (dma->rx_running) {
enum dma_status state;
state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
if (state == DMA_COMPLETE) {
/*
* Disable RX interrupts to allow RX DMA completion
* callback to run.
*/
p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
serial_out(p, UART_IER, p->ier);
}
goto out;
}
desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
dma->rx_size, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
err = -EBUSY;
goto out;
}
dma->rx_running = 1;
desc->callback = __dma_rx_complete;
desc->callback_param = p;
dma->rx_cookie = dmaengine_submit(desc);
/*
* Disable RX FIFO interrupt while RX DMA is enabled, else
* spurious interrupt may be raised when data is in the RX FIFO
* but is yet to be drained by DMA.
*/
if (priv->habit & UART_HAS_RHR_IT_DIS) {
reg = serial_in(p, UART_OMAP_IER2);
reg |= UART_OMAP_IER2_RHR_IT_DIS;
serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
}
dma_async_issue_pending(dma->rxchan);
out:
spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
return err;
}
static int omap_8250_tx_dma(struct uart_8250_port *p);
static void omap_8250_dma_tx_complete(void *param)
{
struct uart_8250_port *p = param;
struct uart_8250_dma *dma = p->dma;
struct circ_buf *xmit = &p->port.state->xmit;
unsigned long flags;
bool en_thri = false;
struct omap8250_priv *priv = p->port.private_data;
dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
spin_lock_irqsave(&p->port.lock, flags);
dma->tx_running = 0;
uart_xmit_advance(&p->port, dma->tx_size);
if (priv->delayed_restore) {
priv->delayed_restore = 0;
omap8250_restore_regs(p);
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&p->port);
if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
int ret;
ret = omap_8250_tx_dma(p);
if (ret)
en_thri = true;
} else if (p->capabilities & UART_CAP_RPM) {
en_thri = true;
}
if (en_thri) {
dma->tx_err = 1;
serial8250_set_THRI(p);
}
spin_unlock_irqrestore(&p->port.lock, flags);
}
static int omap_8250_tx_dma(struct uart_8250_port *p)
{
struct uart_8250_dma *dma = p->dma;
struct omap8250_priv *priv = p->port.private_data;
struct circ_buf *xmit = &p->port.state->xmit;
struct dma_async_tx_descriptor *desc;
unsigned int skip_byte = 0;
int ret;
if (dma->tx_running)
return 0;
if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
/*
* Even if no data, we need to return an error for the two cases
* below so serial8250_tx_chars() is invoked and properly clears
* THRI and/or runtime suspend.
*/
if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
ret = -EBUSY;
goto err;
}
serial8250_clear_THRI(p);
return 0;
}
dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
if (priv->habit & OMAP_DMA_TX_KICK) {
u8 tx_lvl;
/*
* We need to put the first byte into the FIFO in order to start
* the DMA transfer. For transfers smaller than four bytes we
* don't bother doing DMA at all. It seem not matter if there
* are still bytes in the FIFO from the last transfer (in case
* we got here directly from omap_8250_dma_tx_complete()). Bytes
* leaving the FIFO seem not to trigger the DMA transfer. It is
* really the byte that we put into the FIFO.
* If the FIFO is already full then we most likely got here from
* omap_8250_dma_tx_complete(). And this means the DMA engine
* just completed its work. We don't have to wait the complete
* 86us at 115200,8n1 but around 60us (not to mention lower
* baudrates). So in that case we take the interrupt and try
* again with an empty FIFO.
*/
tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
if (tx_lvl == p->tx_loadsz) {
ret = -EBUSY;
goto err;
}
if (dma->tx_size < 4) {
ret = -EINVAL;
goto err;
}
skip_byte = 1;
}
desc = dmaengine_prep_slave_single(dma->txchan,
dma->tx_addr + xmit->tail + skip_byte,
dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!desc) {
ret = -EBUSY;
goto err;
}
dma->tx_running = 1;
desc->callback = omap_8250_dma_tx_complete;
desc->callback_param = p;
dma->tx_cookie = dmaengine_submit(desc);
dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
UART_XMIT_SIZE, DMA_TO_DEVICE);
dma_async_issue_pending(dma->txchan);
if (dma->tx_err)
dma->tx_err = 0;
serial8250_clear_THRI(p);
if (skip_byte)
serial_out(p, UART_TX, xmit->buf[xmit->tail]);
return 0;
err:
dma->tx_err = 1;
return ret;
}
static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
{
switch (iir & 0x3f) {
case UART_IIR_RLSI:
case UART_IIR_RX_TIMEOUT:
case UART_IIR_RDI:
omap_8250_rx_dma_flush(up);
return true;
}
return omap_8250_rx_dma(up);
}
static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
{
if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
(iir & UART_IIR_RDI)) {
if (handle_rx_dma(up, iir)) {
status = serial8250_rx_chars(up, status);
omap_8250_rx_dma(up);
}
}
return status;
}
static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
u16 status)
{
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&up->port.lock);
/*
* Queue a new transfer if FIFO has data.
*/
if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
(up->ier & UART_IER_RDI)) {
omap_8250_rx_dma(up);
serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
} else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
/*
* Disable RX timeout, read IIR to clear
* current timeout condition, clear EFR2 to
* periodic timeouts, re-enable interrupts.
*/
up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
serial_out(up, UART_IER, up->ier);
omap_8250_rx_dma_flush(up);
serial_in(up, UART_IIR);
serial_out(up, UART_OMAP_EFR2, 0x0);
up->ier |= UART_IER_RLSI | UART_IER_RDI;
serial_out(up, UART_IER, up->ier);
}
}
/*
* This is mostly serial8250_handle_irq(). We have a slightly different DMA
* hoook for RX/TX and need different logic for them in the ISR. Therefore we
* use the default routine in the non-DMA case and this one for with DMA.
*/
static int omap_8250_dma_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
struct omap8250_priv *priv = up->port.private_data;
u16 status;
u8 iir;
serial8250_rpm_get(up);
iir = serial_port_in(port, UART_IIR);
if (iir & UART_IIR_NO_INT) {
serial8250_rpm_put(up);
return IRQ_HANDLED;
}
spin_lock(&port->lock);
status = serial_port_in(port, UART_LSR);
if (priv->habit & UART_HAS_EFR2)
am654_8250_handle_rx_dma(up, iir, status);
else
status = omap_8250_handle_rx_dma(up, iir, status);
serial8250_modem_status(up);
if (status & UART_LSR_THRE && up->dma->tx_err) {
if (uart_tx_stopped(&up->port) ||
uart_circ_empty(&up->port.state->xmit)) {
up->dma->tx_err = 0;
serial8250_tx_chars(up);
} else {
/*
* try again due to an earlier failer which
* might have been resolved by now.
*/
if (omap_8250_tx_dma(up))
serial8250_tx_chars(up);
}
}
uart_unlock_and_check_sysrq(port);
serial8250_rpm_put(up);
return 1;
}
static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
{
return false;
}
#else
static inline int omap_8250_rx_dma(struct uart_8250_port *p)
{
return -EINVAL;
}
#endif
static int omap8250_no_handle_irq(struct uart_port *port)
{
/* IRQ has not been requested but handling irq? */
WARN_ONCE(1, "Unexpected irq handling before port startup\n");
return 0;
}
static struct omap8250_dma_params am654_dma = {
.rx_size = SZ_2K,
.rx_trigger = 1,
.tx_trigger = TX_TRIGGER,
};
static struct omap8250_dma_params am33xx_dma = {
.rx_size = RX_TRIGGER,
.rx_trigger = RX_TRIGGER,
.tx_trigger = TX_TRIGGER,
};
static struct omap8250_platdata am654_platdata = {
.dma_params = &am654_dma,
.habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485,
};
static struct omap8250_platdata am33xx_platdata = {
.dma_params = &am33xx_dma,
.habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
};
static struct omap8250_platdata omap4_platdata = {
.dma_params = &am33xx_dma,
.habit = UART_ERRATA_CLOCK_DISABLE,
};
static const struct of_device_id omap8250_dt_ids[] = {
{ .compatible = "ti,am654-uart", .data = &am654_platdata, },
{ .compatible = "ti,omap2-uart" },
{ .compatible = "ti,omap3-uart" },
{ .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
{ .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
{ .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
{ .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
{},
};
MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
static int omap8250_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct omap8250_priv *priv;
const struct omap8250_platdata *pdata;
struct uart_8250_port up;
struct resource *regs;
void __iomem *membase;
int irq, ret;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(&pdev->dev, "missing registers\n");
return -EINVAL;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
membase = devm_ioremap(&pdev->dev, regs->start,
resource_size(regs));
if (!membase)
return -ENODEV;
memset(&up, 0, sizeof(up));
up.port.dev = &pdev->dev;
up.port.mapbase = regs->start;
up.port.membase = membase;
up.port.irq = irq;
/*
* It claims to be 16C750 compatible however it is a little different.
* It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
* have) is enabled via EFR instead of MCR. The type is set here 8250
* just to get things going. UNKNOWN does not work for a few reasons and
* we don't need our own type since we don't use 8250's set_termios()
* or pm callback.
*/
up.port.type = PORT_8250;
up.port.iotype = UPIO_MEM;
up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
UPF_HARD_FLOW;
up.port.private_data = priv;
up.port.regshift = OMAP_UART_REGSHIFT;
up.port.fifosize = 64;
up.tx_loadsz = 64;
up.capabilities = UART_CAP_FIFO;
#ifdef CONFIG_PM
/*
* Runtime PM is mostly transparent. However to do it right we need to a
* TX empty interrupt before we can put the device to auto idle. So if
* PM is not enabled we don't add that flag and can spare that one extra
* interrupt in the TX path.
*/
up.capabilities |= UART_CAP_RPM;
#endif
up.port.set_termios = omap_8250_set_termios;
up.port.set_mctrl = omap8250_set_mctrl;
up.port.pm = omap_8250_pm;
up.port.startup = omap_8250_startup;
up.port.shutdown = omap_8250_shutdown;
up.port.throttle = omap_8250_throttle;
up.port.unthrottle = omap_8250_unthrottle;
up.port.rs485_config = omap8250_rs485_config;
/* same rs485_supported for software emulation and native RS485 */
up.port.rs485_supported = serial8250_em485_supported;
up.rs485_start_tx = serial8250_em485_start_tx;
up.rs485_stop_tx = serial8250_em485_stop_tx;
up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
ret = of_alias_get_id(np, "serial");
if (ret < 0) {
dev_err(&pdev->dev, "failed to get alias\n");
return ret;
}
up.port.line = ret;
if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
struct clk *clk;
clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) == -EPROBE_DEFER)
return -EPROBE_DEFER;
} else {
up.port.uartclk = clk_get_rate(clk);
}
}
if (of_property_read_u32(np, "overrun-throttle-ms",
&up.overrun_backoff_time_ms) != 0)
up.overrun_backoff_time_ms = 0;
pdata = of_device_get_match_data(&pdev->dev);
if (pdata)
priv->habit |= pdata->habit;
if (!up.port.uartclk) {
up.port.uartclk = DEFAULT_CLK_SPEED;
dev_warn(&pdev->dev,
"No clock speed specified: using default: %d\n",
DEFAULT_CLK_SPEED);
}
priv->membase = membase;
priv->line = -ENODEV;
priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
spin_lock_init(&priv->rx_dma_lock);
platform_set_drvdata(pdev, priv);
device_init_wakeup(&pdev->dev, true);
pm_runtime_enable(&pdev->dev);
pm_runtime_use_autosuspend(&pdev->dev);
/*
* Disable runtime PM until autosuspend delay unless specifically
* enabled by the user via sysfs. This is the historic way to
* prevent an unsafe default policy with lossy characters on wake-up.
* For serdev devices this is not needed, the policy can be managed by
* the serdev driver.
*/
if (!of_get_available_child_count(pdev->dev.of_node))
pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
pm_runtime_irq_safe(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
omap_serial_fill_features_erratas(&up, priv);
up.port.handle_irq = omap8250_no_handle_irq;
priv->rx_trigger = RX_TRIGGER;
priv->tx_trigger = TX_TRIGGER;
#ifdef CONFIG_SERIAL_8250_DMA
/*
* Oh DMA support. If there are no DMA properties in the DT then
* we will fall back to a generic DMA channel which does not
* really work here. To ensure that we do not get a generic DMA
* channel assigned, we have the the_no_dma_filter_fn() here.
* To avoid "failed to request DMA" messages we check for DMA
* properties in DT.
*/
ret = of_property_count_strings(np, "dma-names");
if (ret == 2) {
struct omap8250_dma_params *dma_params = NULL;
struct uart_8250_dma *dma = &priv->omap8250_dma;
dma->fn = the_no_dma_filter_fn;
dma->tx_dma = omap_8250_tx_dma;
dma->rx_dma = omap_8250_rx_dma;
if (pdata)
dma_params = pdata->dma_params;
if (dma_params) {
dma->rx_size = dma_params->rx_size;
dma->rxconf.src_maxburst = dma_params->rx_trigger;
dma->txconf.dst_maxburst = dma_params->tx_trigger;
priv->rx_trigger = dma_params->rx_trigger;
priv->tx_trigger = dma_params->tx_trigger;
} else {
dma->rx_size = RX_TRIGGER;
dma->rxconf.src_maxburst = RX_TRIGGER;
dma->txconf.dst_maxburst = TX_TRIGGER;
}
}
#endif
irq_set_status_flags(irq, IRQ_NOAUTOEN);
ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0,
dev_name(&pdev->dev), priv);
if (ret < 0)
return ret;
priv->wakeirq = irq_of_parse_and_map(np, 1);
ret = serial8250_register_8250_port(&up);
if (ret < 0) {
dev_err(&pdev->dev, "unable to register 8250 port\n");
goto err;
}
priv->line = ret;
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
return 0;
err:
pm_runtime_dont_use_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
flush_work(&priv->qos_work);
pm_runtime_disable(&pdev->dev);
cpu_latency_qos_remove_request(&priv->pm_qos_request);
return ret;
}
static int omap8250_remove(struct platform_device *pdev)
{
struct omap8250_priv *priv = platform_get_drvdata(pdev);
struct uart_8250_port *up;
int err;
err = pm_runtime_resume_and_get(&pdev->dev);
if (err)
return err;
up = serial8250_get_port(priv->line);
omap_8250_shutdown(&up->port);
serial8250_unregister_port(priv->line);
priv->line = -ENODEV;
pm_runtime_dont_use_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
flush_work(&priv->qos_work);
pm_runtime_disable(&pdev->dev);
cpu_latency_qos_remove_request(&priv->pm_qos_request);
device_init_wakeup(&pdev->dev, false);
return 0;
}
static int omap8250_prepare(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
if (!priv)
return 0;
priv->is_suspending = true;
return 0;
}
static void omap8250_complete(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
if (!priv)
return;
priv->is_suspending = false;
}
static int omap8250_suspend(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = serial8250_get_port(priv->line);
int err;
serial8250_suspend_port(priv->line);
err = pm_runtime_resume_and_get(dev);
if (err)
return err;
if (!device_may_wakeup(dev))
priv->wer = 0;
serial_out(up, UART_OMAP_WER, priv->wer);
err = pm_runtime_force_suspend(dev);
flush_work(&priv->qos_work);
return err;
}
static int omap8250_resume(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
int err;
err = pm_runtime_force_resume(dev);
if (err)
return err;
serial8250_resume_port(priv->line);
/* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */
pm_runtime_mark_last_busy(dev);
pm_runtime_put_autosuspend(dev);
return 0;
}
static int omap8250_lost_context(struct uart_8250_port *up)
{
u32 val;
val = serial_in(up, UART_OMAP_SCR);
/*
* If we lose context, then SCR is set to its reset value of zero.
* After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
* among other bits, to never set the register back to zero again.
*/
if (!val)
return 1;
return 0;
}
static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val)
{
writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
}
/* TODO: in future, this should happen via API in drivers/reset/ */
static int omap8250_soft_reset(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
int timeout = 100;
int sysc;
int syss;
/*
* At least on omap4, unused uarts may not idle after reset without
* a basic scr dma configuration even with no dma in use. The
* module clkctrl status bits will be 1 instead of 3 blocking idle
* for the whole clockdomain. The softreset below will clear scr,
* and we restore it on resume so this is safe to do on all SoCs
* needing omap8250_soft_reset() quirk. Do it in two writes as
* recommended in the comment for omap8250_update_scr().
*/
uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
uart_write(priv, UART_OMAP_SCR,
OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
sysc = uart_read(priv, UART_OMAP_SYSC);
/* softreset the UART */
sysc |= OMAP_UART_SYSC_SOFTRESET;
uart_write(priv, UART_OMAP_SYSC, sysc);
/* By experiments, 1us enough for reset complete on AM335x */
do {
udelay(1);
syss = uart_read(priv, UART_OMAP_SYSS);
} while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
if (!timeout) {
dev_err(dev, "timed out waiting for reset done\n");
return -ETIMEDOUT;
}
return 0;
}
static int omap8250_runtime_suspend(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = NULL;
if (priv->line >= 0)
up = serial8250_get_port(priv->line);
/*
* When using 'no_console_suspend', the console UART must not be
* suspended. Since driver suspend is managed by runtime suspend,
* preventing runtime suspend (by returning error) will keep device
* active during suspend.
*/
if (priv->is_suspending && !console_suspend_enabled) {
if (up && uart_console(&up->port))
return -EBUSY;
}
if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
int ret;
ret = omap8250_soft_reset(dev);
if (ret)
return ret;
if (up) {
/* Restore to UART mode after reset (for wakeup) */
omap8250_update_mdr1(up, priv);
/* Restore wakeup enable register */
serial_out(up, UART_OMAP_WER, priv->wer);
}
}
if (up && up->dma && up->dma->rxchan)
omap_8250_rx_dma_flush(up);
priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
schedule_work(&priv->qos_work);
return 0;
}
static int omap8250_runtime_resume(struct device *dev)
{
struct omap8250_priv *priv = dev_get_drvdata(dev);
struct uart_8250_port *up = NULL;
if (priv->line >= 0)
up = serial8250_get_port(priv->line);
if (up && omap8250_lost_context(up)) {
spin_lock_irq(&up->port.lock);
omap8250_restore_regs(up);
spin_unlock_irq(&up->port.lock);
}
if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
spin_lock_irq(&up->port.lock);
omap_8250_rx_dma(up);
spin_unlock_irq(&up->port.lock);
}
priv->latency = priv->calc_latency;
schedule_work(&priv->qos_work);
return 0;
}
#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
static int __init omap8250_console_fixup(void)
{
char *omap_str;
char *options;
u8 idx;
if (strstr(boot_command_line, "console=ttyS"))
/* user set a ttyS based name for the console */
return 0;
omap_str = strstr(boot_command_line, "console=ttyO");
if (!omap_str)
/* user did not set ttyO based console, so we don't care */
return 0;
omap_str += 12;
if ('0' <= *omap_str && *omap_str <= '9')
idx = *omap_str - '0';
else
return 0;
omap_str++;
if (omap_str[0] == ',') {
omap_str++;
options = omap_str;
} else {
options = NULL;
}
add_preferred_console("ttyS", idx, options);
pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
idx, idx);
pr_err("This ensures that you still see kernel messages. Please\n");
pr_err("update your kernel commandline.\n");
return 0;
}
console_initcall(omap8250_console_fixup);
#endif
static const struct dev_pm_ops omap8250_dev_pm_ops = {
SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
RUNTIME_PM_OPS(omap8250_runtime_suspend,
omap8250_runtime_resume, NULL)
.prepare = pm_sleep_ptr(omap8250_prepare),
.complete = pm_sleep_ptr(omap8250_complete),
};
static struct platform_driver omap8250_platform_driver = {
.driver = {
.name = "omap8250",
.pm = pm_ptr(&omap8250_dev_pm_ops),
.of_match_table = omap8250_dt_ids,
},
.probe = omap8250_probe,
.remove = omap8250_remove,
};
module_platform_driver(omap8250_platform_driver);
MODULE_AUTHOR("Sebastian Andrzej Siewior");
MODULE_DESCRIPTION("OMAP 8250 Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/tty/serial/8250/8250_omap.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Probe for F81216A LPC to 4 UART
*
* Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pnp.h>
#include <linux/kernel.h>
#include <linux/serial_core.h>
#include <linux/irq.h>
#include "8250.h"
#define ADDR_PORT 0
#define DATA_PORT 1
#define EXIT_KEY 0xAA
#define CHIP_ID1 0x20
#define CHIP_ID2 0x21
#define CHIP_ID_F81865 0x0407
#define CHIP_ID_F81866 0x1010
#define CHIP_ID_F81966 0x0215
#define CHIP_ID_F81216AD 0x1602
#define CHIP_ID_F81216H 0x0501
#define CHIP_ID_F81216 0x0802
#define VENDOR_ID1 0x23
#define VENDOR_ID1_VAL 0x19
#define VENDOR_ID2 0x24
#define VENDOR_ID2_VAL 0x34
#define IO_ADDR1 0x61
#define IO_ADDR2 0x60
#define LDN 0x7
#define FINTEK_IRQ_MODE 0x70
#define IRQ_SHARE BIT(4)
#define IRQ_MODE_MASK (BIT(6) | BIT(5))
#define IRQ_LEVEL_LOW 0
#define IRQ_EDGE_HIGH BIT(5)
/*
* F81216H clock source register, the value and mask is the same with F81866,
* but it's on F0h.
*
* Clock speeds for UART (register F0h)
* 00: 1.8432MHz.
* 01: 18.432MHz.
* 10: 24MHz.
* 11: 14.769MHz.
*/
#define RS485 0xF0
#define RTS_INVERT BIT(5)
#define RS485_URA BIT(4)
#define RXW4C_IRA BIT(3)
#define TXW4C_IRA BIT(2)
#define FIFO_CTRL 0xF6
#define FIFO_MODE_MASK (BIT(1) | BIT(0))
#define FIFO_MODE_128 (BIT(1) | BIT(0))
#define RXFTHR_MODE_MASK (BIT(5) | BIT(4))
#define RXFTHR_MODE_4X BIT(5)
#define F81216_LDN_LOW 0x0
#define F81216_LDN_HIGH 0x4
/*
* F81866/966 registers
*
* The IRQ setting mode of F81866/966 is not the same with F81216 series.
* Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
* Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
*
* Clock speeds for UART (register F2h)
* 00: 1.8432MHz.
* 01: 18.432MHz.
* 10: 24MHz.
* 11: 14.769MHz.
*/
#define F81866_IRQ_MODE 0xf0
#define F81866_IRQ_SHARE BIT(0)
#define F81866_IRQ_MODE0 BIT(1)
#define F81866_FIFO_CTRL FIFO_CTRL
#define F81866_IRQ_MODE1 BIT(3)
#define F81866_LDN_LOW 0x10
#define F81866_LDN_HIGH 0x16
#define F81866_UART_CLK 0xF2
#define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
#define F81866_UART_CLK_1_8432MHZ 0
#define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
#define F81866_UART_CLK_18_432MHZ BIT(0)
#define F81866_UART_CLK_24MHZ BIT(1)
struct fintek_8250 {
u16 pid;
u16 base_port;
u8 index;
u8 key;
};
static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
{
outb(reg, pdata->base_port + ADDR_PORT);
return inb(pdata->base_port + DATA_PORT);
}
static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
{
outb(reg, pdata->base_port + ADDR_PORT);
outb(data, pdata->base_port + DATA_PORT);
}
static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
u8 data)
{
u8 tmp;
tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
sio_write_reg(pdata, reg, tmp);
}
static int fintek_8250_enter_key(u16 base_port, u8 key)
{
if (!request_muxed_region(base_port, 2, "8250_fintek"))
return -EBUSY;
/* Force to deactive all SuperIO in this base_port */
outb(EXIT_KEY, base_port + ADDR_PORT);
outb(key, base_port + ADDR_PORT);
outb(key, base_port + ADDR_PORT);
return 0;
}
static void fintek_8250_exit_key(u16 base_port)
{
outb(EXIT_KEY, base_port + ADDR_PORT);
release_region(base_port + ADDR_PORT, 2);
}
static int fintek_8250_check_id(struct fintek_8250 *pdata)
{
u16 chip;
if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
return -ENODEV;
if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
return -ENODEV;
chip = sio_read_reg(pdata, CHIP_ID1);
chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
switch (chip) {
case CHIP_ID_F81865:
case CHIP_ID_F81866:
case CHIP_ID_F81966:
case CHIP_ID_F81216AD:
case CHIP_ID_F81216H:
case CHIP_ID_F81216:
break;
default:
return -ENODEV;
}
pdata->pid = chip;
return 0;
}
static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
int *max)
{
switch (pdata->pid) {
case CHIP_ID_F81966:
case CHIP_ID_F81865:
case CHIP_ID_F81866:
*min = F81866_LDN_LOW;
*max = F81866_LDN_HIGH;
return 0;
case CHIP_ID_F81216AD:
case CHIP_ID_F81216H:
case CHIP_ID_F81216:
*min = F81216_LDN_LOW;
*max = F81216_LDN_HIGH;
return 0;
}
return -ENODEV;
}
static int fintek_8250_rs485_config(struct uart_port *port, struct ktermios *termios,
struct serial_rs485 *rs485)
{
uint8_t config = 0;
struct fintek_8250 *pdata = port->private_data;
if (!pdata)
return -EINVAL;
if (rs485->flags & SER_RS485_ENABLED) {
/* Hardware do not support same RTS level on send and receive */
if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
!(rs485->flags & SER_RS485_RTS_AFTER_SEND))
return -EINVAL;
config |= RS485_URA;
}
if (rs485->delay_rts_before_send) {
rs485->delay_rts_before_send = 1;
config |= TXW4C_IRA;
}
if (rs485->delay_rts_after_send) {
rs485->delay_rts_after_send = 1;
config |= RXW4C_IRA;
}
if (rs485->flags & SER_RS485_RTS_ON_SEND)
config |= RTS_INVERT;
if (fintek_8250_enter_key(pdata->base_port, pdata->key))
return -EBUSY;
sio_write_reg(pdata, LDN, pdata->index);
sio_write_reg(pdata, RS485, config);
fintek_8250_exit_key(pdata->base_port);
return 0;
}
static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
{
sio_write_reg(pdata, LDN, pdata->index);
switch (pdata->pid) {
case CHIP_ID_F81966:
case CHIP_ID_F81866:
sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
0);
fallthrough;
case CHIP_ID_F81865:
sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
F81866_IRQ_SHARE);
sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
is_level ? 0 : F81866_IRQ_MODE0);
break;
case CHIP_ID_F81216AD:
case CHIP_ID_F81216H:
case CHIP_ID_F81216:
sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
IRQ_SHARE);
sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
break;
}
}
static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
{
switch (pdata->pid) {
case CHIP_ID_F81216H: /* 128Bytes FIFO */
case CHIP_ID_F81966:
case CHIP_ID_F81866:
sio_write_mask_reg(pdata, FIFO_CTRL,
FIFO_MODE_MASK | RXFTHR_MODE_MASK,
FIFO_MODE_128 | RXFTHR_MODE_4X);
break;
default: /* Default 16Bytes FIFO */
break;
}
}
static void fintek_8250_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old)
{
struct fintek_8250 *pdata = port->private_data;
unsigned int baud = tty_termios_baud_rate(termios);
int i;
u8 reg;
static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
F81866_UART_CLK_24MHZ };
/*
* We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
* crash on baudrate_table[i] % baud with "division by zero".
*/
if (!baud)
goto exit;
switch (pdata->pid) {
case CHIP_ID_F81216H:
reg = RS485;
break;
case CHIP_ID_F81966:
case CHIP_ID_F81866:
reg = F81866_UART_CLK;
break;
default:
/* Don't change clocksource with unknown PID */
dev_warn(port->dev,
"%s: pid: %x Not support. use default set_termios.\n",
__func__, pdata->pid);
goto exit;
}
for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
continue;
if (port->uartclk == baudrate_table[i] * 16)
break;
if (fintek_8250_enter_key(pdata->base_port, pdata->key))
continue;
port->uartclk = baudrate_table[i] * 16;
sio_write_reg(pdata, LDN, pdata->index);
sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
clock_table[i]);
fintek_8250_exit_key(pdata->base_port);
break;
}
if (i == ARRAY_SIZE(baudrate_table)) {
baud = tty_termios_baud_rate(old);
tty_termios_encode_baud_rate(termios, baud, baud);
}
exit:
serial8250_do_set_termios(port, termios, old);
}
static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
{
struct fintek_8250 *pdata = uart->port.private_data;
switch (pdata->pid) {
case CHIP_ID_F81216H:
case CHIP_ID_F81966:
case CHIP_ID_F81866:
uart->port.set_termios = fintek_8250_set_termios;
break;
default:
break;
}
}
static int probe_setup_port(struct fintek_8250 *pdata,
struct uart_8250_port *uart)
{
static const u16 addr[] = {0x4e, 0x2e};
static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
struct irq_data *irq_data;
bool level_mode = false;
int i, j, k, min, max;
for (i = 0; i < ARRAY_SIZE(addr); i++) {
for (j = 0; j < ARRAY_SIZE(keys); j++) {
pdata->base_port = addr[i];
pdata->key = keys[j];
if (fintek_8250_enter_key(addr[i], keys[j]))
continue;
if (fintek_8250_check_id(pdata) ||
fintek_8250_get_ldn_range(pdata, &min, &max)) {
fintek_8250_exit_key(addr[i]);
continue;
}
for (k = min; k < max; k++) {
u16 aux;
sio_write_reg(pdata, LDN, k);
aux = sio_read_reg(pdata, IO_ADDR1);
aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
if (aux != uart->port.iobase)
continue;
pdata->index = k;
irq_data = irq_get_irq_data(uart->port.irq);
if (irq_data)
level_mode =
irqd_is_level_type(irq_data);
fintek_8250_set_irq_mode(pdata, level_mode);
fintek_8250_set_max_fifo(pdata);
fintek_8250_exit_key(addr[i]);
return 0;
}
fintek_8250_exit_key(addr[i]);
}
}
return -ENODEV;
}
/* Only the first port supports delays */
static const struct serial_rs485 fintek_8250_rs485_supported_port0 = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
.delay_rts_before_send = 1,
.delay_rts_after_send = 1,
};
static const struct serial_rs485 fintek_8250_rs485_supported = {
.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
};
static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
{
struct fintek_8250 *pdata = uart->port.private_data;
switch (pdata->pid) {
case CHIP_ID_F81216AD:
case CHIP_ID_F81216H:
case CHIP_ID_F81966:
case CHIP_ID_F81866:
case CHIP_ID_F81865:
uart->port.rs485_config = fintek_8250_rs485_config;
if (!pdata->index)
uart->port.rs485_supported = fintek_8250_rs485_supported_port0;
else
uart->port.rs485_supported = fintek_8250_rs485_supported;
break;
default: /* No RS485 Auto direction functional */
break;
}
}
int fintek_8250_probe(struct uart_8250_port *uart)
{
struct fintek_8250 *pdata;
struct fintek_8250 probe_data;
if (probe_setup_port(&probe_data, uart))
return -ENODEV;
pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
memcpy(pdata, &probe_data, sizeof(probe_data));
uart->port.private_data = pdata;
fintek_8250_set_rs485_handler(uart);
fintek_8250_set_termios_handler(uart);
return 0;
}
| linux-master | drivers/tty/serial/8250/8250_fintek.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Freescale 16550 UART "driver", Copyright (C) 2011 Paul Gortmaker.
* Copyright 2020 NXP
* Copyright 2020 Puresoftware Ltd.
*
* This isn't a full driver; it just provides an alternate IRQ
* handler to deal with an errata and provide ACPI wrapper.
* Everything else is just using the bog standard 8250 support.
*
* We follow code flow of serial8250_default_handle_irq() but add
* a check for a break and insert a dummy read on the Rx for the
* immediately following IRQ event.
*
* We re-use the already existing "bug handling" lsr_saved_flags
* field to carry the "what we just did" information from the one
* IRQ event to the next one.
*/
#include <linux/acpi.h>
#include <linux/serial_reg.h>
#include <linux/serial_8250.h>
#include "8250.h"
int fsl8250_handle_irq(struct uart_port *port)
{
unsigned long flags;
u16 lsr, orig_lsr;
unsigned int iir;
struct uart_8250_port *up = up_to_u8250p(port);
spin_lock_irqsave(&up->port.lock, flags);
iir = port->serial_in(port, UART_IIR);
if (iir & UART_IIR_NO_INT) {
spin_unlock_irqrestore(&up->port.lock, flags);
return 0;
}
/*
* For a single break the hardware reports LSR.BI for each character
* time. This is described in the MPC8313E chip errata as "General17".
* A typical break has a duration of 0.3s, with a 115200n8 configuration
* that (theoretically) corresponds to ~3500 interrupts in these 0.3s.
* In practise it's less (around 500) because of hardware
* and software latencies. The workaround recommended by the vendor is
* to read the RX register (to clear LSR.DR and thus prevent a FIFO
* aging interrupt). To prevent the irq from retriggering LSR must not be
* read. (This would clear LSR.BI, hardware would reassert the BI event
* immediately and interrupt the CPU again. The hardware clears LSR.BI
* when the next valid char is read.)
*/
if (unlikely(up->lsr_saved_flags & UART_LSR_BI)) {
up->lsr_saved_flags &= ~UART_LSR_BI;
port->serial_in(port, UART_RX);
spin_unlock_irqrestore(&up->port.lock, flags);
return 1;
}
lsr = orig_lsr = up->port.serial_in(&up->port, UART_LSR);
/* Process incoming characters first */
if ((lsr & (UART_LSR_DR | UART_LSR_BI)) &&
(up->ier & (UART_IER_RLSI | UART_IER_RDI))) {
lsr = serial8250_rx_chars(up, lsr);
}
/* Stop processing interrupts on input overrun */
if ((orig_lsr & UART_LSR_OE) && (up->overrun_backoff_time_ms > 0)) {
unsigned long delay;
up->ier = port->serial_in(port, UART_IER);
if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
port->ops->stop_rx(port);
} else {
/* Keep restarting the timer until
* the input overrun subsides.
*/
cancel_delayed_work(&up->overrun_backoff);
}
delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
schedule_delayed_work(&up->overrun_backoff, delay);
}
serial8250_modem_status(up);
if ((lsr & UART_LSR_THRE) && (up->ier & UART_IER_THRI))
serial8250_tx_chars(up);
up->lsr_saved_flags |= orig_lsr & UART_LSR_BI;
uart_unlock_and_check_sysrq_irqrestore(&up->port, flags);
return 1;
}
EXPORT_SYMBOL_GPL(fsl8250_handle_irq);
#ifdef CONFIG_ACPI
struct fsl8250_data {
int line;
};
static int fsl8250_acpi_probe(struct platform_device *pdev)
{
struct fsl8250_data *data;
struct uart_8250_port port8250;
struct device *dev = &pdev->dev;
struct resource *regs;
int ret, irq;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(dev, "no registers defined\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
memset(&port8250, 0, sizeof(port8250));
ret = device_property_read_u32(dev, "clock-frequency",
&port8250.port.uartclk);
if (ret)
return ret;
spin_lock_init(&port8250.port.lock);
port8250.port.mapbase = regs->start;
port8250.port.irq = irq;
port8250.port.handle_irq = fsl8250_handle_irq;
port8250.port.type = PORT_16550A;
port8250.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF
| UPF_FIXED_PORT | UPF_IOREMAP
| UPF_FIXED_TYPE;
port8250.port.dev = dev;
port8250.port.mapsize = resource_size(regs);
port8250.port.iotype = UPIO_MEM;
port8250.port.irqflags = IRQF_SHARED;
port8250.port.membase = devm_ioremap(dev, port8250.port.mapbase,
port8250.port.mapsize);
if (!port8250.port.membase)
return -ENOMEM;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->line = serial8250_register_8250_port(&port8250);
if (data->line < 0)
return data->line;
platform_set_drvdata(pdev, data);
return 0;
}
static int fsl8250_acpi_remove(struct platform_device *pdev)
{
struct fsl8250_data *data = platform_get_drvdata(pdev);
serial8250_unregister_port(data->line);
return 0;
}
static const struct acpi_device_id fsl_8250_acpi_id[] = {
{ "NXP0018", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, fsl_8250_acpi_id);
static struct platform_driver fsl8250_platform_driver = {
.driver = {
.name = "fsl-16550-uart",
.acpi_match_table = ACPI_PTR(fsl_8250_acpi_id),
},
.probe = fsl8250_acpi_probe,
.remove = fsl8250_acpi_remove,
};
module_platform_driver(fsl8250_platform_driver);
#endif
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Handling of Freescale specific 8250 variants");
| linux-master | drivers/tty/serial/8250/8250_fsl.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include "8250.h"
static struct plat_serial8250_port accent_data[] = {
SERIAL8250_PORT(0x330, 4),
SERIAL8250_PORT(0x338, 4),
{ },
};
static struct platform_device accent_device = {
.name = "serial8250",
.id = PLAT8250_DEV_ACCENT,
.dev = {
.platform_data = accent_data,
},
};
static int __init accent_init(void)
{
return platform_device_register(&accent_device);
}
module_init(accent_init);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("8250 serial probe module for Accent Async cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_accent.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Serial Port driver for Aspeed VUART device
*
* Copyright (C) 2016 Jeremy Kerr <[email protected]>, IBM Corp.
* Copyright (C) 2006 Arnd Bergmann <[email protected]>, IBM Corp.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/clk.h>
#include "8250.h"
#define ASPEED_VUART_GCRA 0x20
#define ASPEED_VUART_GCRA_VUART_EN BIT(0)
#define ASPEED_VUART_GCRA_HOST_SIRQ_POLARITY BIT(1)
#define ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD BIT(5)
#define ASPEED_VUART_GCRB 0x24
#define ASPEED_VUART_GCRB_HOST_SIRQ_MASK GENMASK(7, 4)
#define ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT 4
#define ASPEED_VUART_ADDRL 0x28
#define ASPEED_VUART_ADDRH 0x2c
#define ASPEED_VUART_DEFAULT_LPC_ADDR 0x3f8
#define ASPEED_VUART_DEFAULT_SIRQ 4
#define ASPEED_VUART_DEFAULT_SIRQ_POLARITY IRQ_TYPE_LEVEL_LOW
struct aspeed_vuart {
struct device *dev;
struct clk *clk;
int line;
struct timer_list unthrottle_timer;
struct uart_8250_port *port;
};
/*
* If we fill the tty flip buffers, we throttle the data ready interrupt
* to prevent dropped characters. This timeout defines how long we wait
* to (conditionally, depending on buffer state) unthrottle.
*/
static const int unthrottle_timeout = HZ/10;
/*
* The VUART is basically two UART 'front ends' connected by their FIFO
* (no actual serial line in between). One is on the BMC side (management
* controller) and one is on the host CPU side.
*
* It allows the BMC to provide to the host a "UART" that pipes into
* the BMC itself and can then be turned by the BMC into a network console
* of some sort for example.
*
* This driver is for the BMC side. The sysfs files allow the BMC
* userspace which owns the system configuration policy, to specify
* at what IO port and interrupt number the host side will appear
* to the host on the Host <-> BMC LPC bus. It could be different on a
* different system (though most of them use 3f8/4).
*/
static inline u8 aspeed_vuart_readb(struct aspeed_vuart *vuart, u8 reg)
{
return readb(vuart->port->port.membase + reg);
}
static inline void aspeed_vuart_writeb(struct aspeed_vuart *vuart, u8 val, u8 reg)
{
writeb(val, vuart->port->port.membase + reg);
}
static ssize_t lpc_address_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct aspeed_vuart *vuart = dev_get_drvdata(dev);
u16 addr;
addr = (aspeed_vuart_readb(vuart, ASPEED_VUART_ADDRH) << 8) |
(aspeed_vuart_readb(vuart, ASPEED_VUART_ADDRL));
return sysfs_emit(buf, "0x%x\n", addr);
}
static int aspeed_vuart_set_lpc_address(struct aspeed_vuart *vuart, u32 addr)
{
if (addr > U16_MAX)
return -EINVAL;
aspeed_vuart_writeb(vuart, addr >> 8, ASPEED_VUART_ADDRH);
aspeed_vuart_writeb(vuart, addr >> 0, ASPEED_VUART_ADDRL);
return 0;
}
static ssize_t lpc_address_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct aspeed_vuart *vuart = dev_get_drvdata(dev);
u32 val;
int err;
err = kstrtou32(buf, 0, &val);
if (err)
return err;
err = aspeed_vuart_set_lpc_address(vuart, val);
return err ? : count;
}
static DEVICE_ATTR_RW(lpc_address);
static ssize_t sirq_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct aspeed_vuart *vuart = dev_get_drvdata(dev);
u8 reg;
reg = aspeed_vuart_readb(vuart, ASPEED_VUART_GCRB);
reg &= ASPEED_VUART_GCRB_HOST_SIRQ_MASK;
reg >>= ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT;
return sysfs_emit(buf, "%u\n", reg);
}
static int aspeed_vuart_set_sirq(struct aspeed_vuart *vuart, u32 sirq)
{
u8 reg;
if (sirq > (ASPEED_VUART_GCRB_HOST_SIRQ_MASK >> ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT))
return -EINVAL;
sirq <<= ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT;
sirq &= ASPEED_VUART_GCRB_HOST_SIRQ_MASK;
reg = aspeed_vuart_readb(vuart, ASPEED_VUART_GCRB);
reg &= ~ASPEED_VUART_GCRB_HOST_SIRQ_MASK;
reg |= sirq;
aspeed_vuart_writeb(vuart, reg, ASPEED_VUART_GCRB);
return 0;
}
static ssize_t sirq_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct aspeed_vuart *vuart = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 0, &val);
if (err)
return err;
err = aspeed_vuart_set_sirq(vuart, val);
return err ? : count;
}
static DEVICE_ATTR_RW(sirq);
static ssize_t sirq_polarity_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct aspeed_vuart *vuart = dev_get_drvdata(dev);
u8 reg;
reg = aspeed_vuart_readb(vuart, ASPEED_VUART_GCRA);
reg &= ASPEED_VUART_GCRA_HOST_SIRQ_POLARITY;
return sysfs_emit(buf, "%u\n", reg ? 1 : 0);
}
static void aspeed_vuart_set_sirq_polarity(struct aspeed_vuart *vuart,
bool polarity)
{
u8 reg = aspeed_vuart_readb(vuart, ASPEED_VUART_GCRA);
if (polarity)
reg |= ASPEED_VUART_GCRA_HOST_SIRQ_POLARITY;
else
reg &= ~ASPEED_VUART_GCRA_HOST_SIRQ_POLARITY;
aspeed_vuart_writeb(vuart, reg, ASPEED_VUART_GCRA);
}
static ssize_t sirq_polarity_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct aspeed_vuart *vuart = dev_get_drvdata(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 0, &val);
if (err)
return err;
aspeed_vuart_set_sirq_polarity(vuart, val != 0);
return count;
}
static DEVICE_ATTR_RW(sirq_polarity);
static struct attribute *aspeed_vuart_attrs[] = {
&dev_attr_sirq.attr,
&dev_attr_sirq_polarity.attr,
&dev_attr_lpc_address.attr,
NULL,
};
static const struct attribute_group aspeed_vuart_attr_group = {
.attrs = aspeed_vuart_attrs,
};
static void aspeed_vuart_set_enabled(struct aspeed_vuart *vuart, bool enabled)
{
u8 reg = aspeed_vuart_readb(vuart, ASPEED_VUART_GCRA);
if (enabled)
reg |= ASPEED_VUART_GCRA_VUART_EN;
else
reg &= ~ASPEED_VUART_GCRA_VUART_EN;
aspeed_vuart_writeb(vuart, reg, ASPEED_VUART_GCRA);
}
static void aspeed_vuart_set_host_tx_discard(struct aspeed_vuart *vuart,
bool discard)
{
u8 reg;
reg = aspeed_vuart_readb(vuart, ASPEED_VUART_GCRA);
/* If the DISABLE_HOST_TX_DISCARD bit is set, discard is disabled */
if (!discard)
reg |= ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD;
else
reg &= ~ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD;
aspeed_vuart_writeb(vuart, reg, ASPEED_VUART_GCRA);
}
static int aspeed_vuart_startup(struct uart_port *uart_port)
{
struct uart_8250_port *uart_8250_port = up_to_u8250p(uart_port);
struct aspeed_vuart *vuart = uart_8250_port->port.private_data;
int rc;
rc = serial8250_do_startup(uart_port);
if (rc)
return rc;
aspeed_vuart_set_host_tx_discard(vuart, false);
return 0;
}
static void aspeed_vuart_shutdown(struct uart_port *uart_port)
{
struct uart_8250_port *uart_8250_port = up_to_u8250p(uart_port);
struct aspeed_vuart *vuart = uart_8250_port->port.private_data;
aspeed_vuart_set_host_tx_discard(vuart, true);
serial8250_do_shutdown(uart_port);
}
static void __aspeed_vuart_set_throttle(struct uart_8250_port *up,
bool throttle)
{
unsigned char irqs = UART_IER_RLSI | UART_IER_RDI;
/* Port locked to synchronize UART_IER access against the console. */
lockdep_assert_held_once(&up->port.lock);
up->ier &= ~irqs;
if (!throttle)
up->ier |= irqs;
serial_out(up, UART_IER, up->ier);
}
static void aspeed_vuart_set_throttle(struct uart_port *port, bool throttle)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
__aspeed_vuart_set_throttle(up, throttle);
spin_unlock_irqrestore(&port->lock, flags);
}
static void aspeed_vuart_throttle(struct uart_port *port)
{
aspeed_vuart_set_throttle(port, true);
}
static void aspeed_vuart_unthrottle(struct uart_port *port)
{
aspeed_vuart_set_throttle(port, false);
}
static void aspeed_vuart_unthrottle_exp(struct timer_list *timer)
{
struct aspeed_vuart *vuart = from_timer(vuart, timer, unthrottle_timer);
struct uart_8250_port *up = vuart->port;
if (!tty_buffer_space_avail(&up->port.state->port)) {
mod_timer(&vuart->unthrottle_timer,
jiffies + unthrottle_timeout);
return;
}
aspeed_vuart_unthrottle(&up->port);
}
/*
* Custom interrupt handler to manage finer-grained flow control. Although we
* have throttle/unthrottle callbacks, we've seen that the VUART device can
* deliver characters faster than the ldisc has a chance to check buffer space
* against the throttle threshold. This results in dropped characters before
* the throttle.
*
* We do this by checking for flip buffer space before RX. If we have no space,
* throttle now and schedule an unthrottle for later, once the ldisc has had
* a chance to drain the buffers.
*/
static int aspeed_vuart_handle_irq(struct uart_port *port)
{
struct uart_8250_port *up = up_to_u8250p(port);
unsigned int iir, lsr;
unsigned long flags;
unsigned int space, count;
iir = serial_port_in(port, UART_IIR);
if (iir & UART_IIR_NO_INT)
return 0;
spin_lock_irqsave(&port->lock, flags);
lsr = serial_port_in(port, UART_LSR);
if (lsr & (UART_LSR_DR | UART_LSR_BI)) {
space = tty_buffer_space_avail(&port->state->port);
if (!space) {
/* throttle and schedule an unthrottle later */
struct aspeed_vuart *vuart = port->private_data;
__aspeed_vuart_set_throttle(up, true);
if (!timer_pending(&vuart->unthrottle_timer))
mod_timer(&vuart->unthrottle_timer,
jiffies + unthrottle_timeout);
} else {
count = min(space, 256U);
do {
serial8250_read_char(up, lsr);
lsr = serial_in(up, UART_LSR);
if (--count == 0)
break;
} while (lsr & (UART_LSR_DR | UART_LSR_BI));
tty_flip_buffer_push(&port->state->port);
}
}
serial8250_modem_status(up);
if (lsr & UART_LSR_THRE)
serial8250_tx_chars(up);
uart_unlock_and_check_sysrq_irqrestore(port, flags);
return 1;
}
static void aspeed_vuart_auto_configure_sirq_polarity(
struct aspeed_vuart *vuart, struct device_node *syscon_np,
u32 reg_offset, u32 reg_mask)
{
struct regmap *regmap;
u32 value;
regmap = syscon_node_to_regmap(syscon_np);
if (IS_ERR(regmap)) {
dev_warn(vuart->dev,
"could not get regmap for aspeed,sirq-polarity-sense\n");
return;
}
if (regmap_read(regmap, reg_offset, &value)) {
dev_warn(vuart->dev, "could not read hw strap table\n");
return;
}
aspeed_vuart_set_sirq_polarity(vuart, (value & reg_mask) == 0);
}
static int aspeed_vuart_map_irq_polarity(u32 dt)
{
switch (dt) {
case IRQ_TYPE_LEVEL_LOW:
return 0;
case IRQ_TYPE_LEVEL_HIGH:
return 1;
default:
return -EINVAL;
}
}
static int aspeed_vuart_probe(struct platform_device *pdev)
{
struct of_phandle_args sirq_polarity_sense_args;
struct uart_8250_port port;
struct aspeed_vuart *vuart;
struct device_node *np;
struct resource *res;
u32 clk, prop, sirq[2];
int rc, sirq_polarity;
np = pdev->dev.of_node;
vuart = devm_kzalloc(&pdev->dev, sizeof(*vuart), GFP_KERNEL);
if (!vuart)
return -ENOMEM;
vuart->dev = &pdev->dev;
timer_setup(&vuart->unthrottle_timer, aspeed_vuart_unthrottle_exp, 0);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
memset(&port, 0, sizeof(port));
port.port.private_data = vuart;
port.port.mapbase = res->start;
port.port.mapsize = resource_size(res);
port.port.startup = aspeed_vuart_startup;
port.port.shutdown = aspeed_vuart_shutdown;
port.port.throttle = aspeed_vuart_throttle;
port.port.unthrottle = aspeed_vuart_unthrottle;
port.port.status = UPSTAT_SYNC_FIFO;
port.port.dev = &pdev->dev;
port.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
port.bugs |= UART_BUG_TXRACE;
rc = sysfs_create_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
if (rc < 0)
return rc;
if (of_property_read_u32(np, "clock-frequency", &clk)) {
vuart->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(vuart->clk)) {
dev_warn(&pdev->dev,
"clk or clock-frequency not defined\n");
rc = PTR_ERR(vuart->clk);
goto err_sysfs_remove;
}
rc = clk_prepare_enable(vuart->clk);
if (rc < 0)
goto err_sysfs_remove;
clk = clk_get_rate(vuart->clk);
}
/* If current-speed was set, then try not to change it. */
if (of_property_read_u32(np, "current-speed", &prop) == 0)
port.port.custom_divisor = clk / (16 * prop);
/* Check for shifted address mapping */
if (of_property_read_u32(np, "reg-offset", &prop) == 0)
port.port.mapbase += prop;
/* Check for registers offset within the devices address range */
if (of_property_read_u32(np, "reg-shift", &prop) == 0)
port.port.regshift = prop;
/* Check for fifo size */
if (of_property_read_u32(np, "fifo-size", &prop) == 0)
port.port.fifosize = prop;
/* Check for a fixed line number */
rc = of_alias_get_id(np, "serial");
if (rc >= 0)
port.port.line = rc;
port.port.irq = irq_of_parse_and_map(np, 0);
port.port.handle_irq = aspeed_vuart_handle_irq;
port.port.iotype = UPIO_MEM;
port.port.type = PORT_ASPEED_VUART;
port.port.uartclk = clk;
port.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
| UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_NO_THRE_TEST;
if (of_property_read_bool(np, "no-loopback-test"))
port.port.flags |= UPF_SKIP_TEST;
if (port.port.fifosize)
port.capabilities = UART_CAP_FIFO;
if (of_property_read_bool(np, "auto-flow-control"))
port.capabilities |= UART_CAP_AFE;
rc = serial8250_register_8250_port(&port);
if (rc < 0)
goto err_clk_disable;
vuart->line = rc;
vuart->port = serial8250_get_port(vuart->line);
rc = of_parse_phandle_with_fixed_args(
np, "aspeed,sirq-polarity-sense", 2, 0,
&sirq_polarity_sense_args);
if (rc < 0) {
dev_dbg(&pdev->dev,
"aspeed,sirq-polarity-sense property not found\n");
} else {
aspeed_vuart_auto_configure_sirq_polarity(
vuart, sirq_polarity_sense_args.np,
sirq_polarity_sense_args.args[0],
BIT(sirq_polarity_sense_args.args[1]));
of_node_put(sirq_polarity_sense_args.np);
}
rc = of_property_read_u32(np, "aspeed,lpc-io-reg", &prop);
if (rc < 0)
prop = ASPEED_VUART_DEFAULT_LPC_ADDR;
rc = aspeed_vuart_set_lpc_address(vuart, prop);
if (rc < 0) {
dev_err(&pdev->dev, "invalid value in aspeed,lpc-io-reg property\n");
goto err_clk_disable;
}
rc = of_property_read_u32_array(np, "aspeed,lpc-interrupts", sirq, 2);
if (rc < 0) {
sirq[0] = ASPEED_VUART_DEFAULT_SIRQ;
sirq[1] = ASPEED_VUART_DEFAULT_SIRQ_POLARITY;
}
rc = aspeed_vuart_set_sirq(vuart, sirq[0]);
if (rc < 0) {
dev_err(&pdev->dev, "invalid sirq number in aspeed,lpc-interrupts property\n");
goto err_clk_disable;
}
sirq_polarity = aspeed_vuart_map_irq_polarity(sirq[1]);
if (sirq_polarity < 0) {
dev_err(&pdev->dev, "invalid sirq polarity in aspeed,lpc-interrupts property\n");
rc = sirq_polarity;
goto err_clk_disable;
}
aspeed_vuart_set_sirq_polarity(vuart, sirq_polarity);
aspeed_vuart_set_enabled(vuart, true);
aspeed_vuart_set_host_tx_discard(vuart, true);
platform_set_drvdata(pdev, vuart);
return 0;
err_clk_disable:
clk_disable_unprepare(vuart->clk);
irq_dispose_mapping(port.port.irq);
err_sysfs_remove:
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
return rc;
}
static int aspeed_vuart_remove(struct platform_device *pdev)
{
struct aspeed_vuart *vuart = platform_get_drvdata(pdev);
del_timer_sync(&vuart->unthrottle_timer);
aspeed_vuart_set_enabled(vuart, false);
serial8250_unregister_port(vuart->line);
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
clk_disable_unprepare(vuart->clk);
return 0;
}
static const struct of_device_id aspeed_vuart_table[] = {
{ .compatible = "aspeed,ast2400-vuart" },
{ .compatible = "aspeed,ast2500-vuart" },
{ },
};
static struct platform_driver aspeed_vuart_driver = {
.driver = {
.name = "aspeed-vuart",
.of_match_table = aspeed_vuart_table,
},
.probe = aspeed_vuart_probe,
.remove = aspeed_vuart_remove,
};
module_platform_driver(aspeed_vuart_driver);
MODULE_AUTHOR("Jeremy Kerr <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Driver for Aspeed VUART device");
| linux-master | drivers/tty/serial/8250/8250_aspeed_vuart.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RT288x/Au1xxx driver
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include "8250.h"
#define RT288X_DL 0x28
/* Au1x00/RT288x UART hardware has a weird register layout */
static const u8 au_io_in_map[7] = {
[UART_RX] = 0,
[UART_IER] = 2,
[UART_IIR] = 3,
[UART_LCR] = 5,
[UART_MCR] = 6,
[UART_LSR] = 7,
[UART_MSR] = 8,
};
static const u8 au_io_out_map[5] = {
[UART_TX] = 1,
[UART_IER] = 2,
[UART_FCR] = 4,
[UART_LCR] = 5,
[UART_MCR] = 6,
};
static unsigned int au_serial_in(struct uart_port *p, int offset)
{
if (offset >= ARRAY_SIZE(au_io_in_map))
return UINT_MAX;
offset = au_io_in_map[offset];
return __raw_readl(p->membase + (offset << p->regshift));
}
static void au_serial_out(struct uart_port *p, int offset, int value)
{
if (offset >= ARRAY_SIZE(au_io_out_map))
return;
offset = au_io_out_map[offset];
__raw_writel(value, p->membase + (offset << p->regshift));
}
/* Au1x00 haven't got a standard divisor latch */
static u32 au_serial_dl_read(struct uart_8250_port *up)
{
return __raw_readl(up->port.membase + RT288X_DL);
}
static void au_serial_dl_write(struct uart_8250_port *up, u32 value)
{
__raw_writel(value, up->port.membase + RT288X_DL);
}
int au_platform_setup(struct plat_serial8250_port *p)
{
p->iotype = UPIO_AU;
p->serial_in = au_serial_in;
p->serial_out = au_serial_out;
p->dl_read = au_serial_dl_read;
p->dl_write = au_serial_dl_write;
p->mapsize = 0x1000;
p->bugs |= UART_BUG_NOMSR;
return 0;
}
EXPORT_SYMBOL_GPL(au_platform_setup);
int rt288x_setup(struct uart_port *p)
{
struct uart_8250_port *up = up_to_u8250p(p);
p->iotype = UPIO_AU;
p->serial_in = au_serial_in;
p->serial_out = au_serial_out;
up->dl_read = au_serial_dl_read;
up->dl_write = au_serial_dl_write;
p->mapsize = 0x100;
up->bugs |= UART_BUG_NOMSR;
return 0;
}
EXPORT_SYMBOL_GPL(rt288x_setup);
#ifdef CONFIG_SERIAL_8250_CONSOLE
static void au_putc(struct uart_port *port, unsigned char c)
{
unsigned int status;
au_serial_out(port, UART_TX, c);
for (;;) {
status = au_serial_in(port, UART_LSR);
if (uart_lsr_tx_empty(status))
break;
cpu_relax();
}
}
static void au_early_serial8250_write(struct console *console,
const char *s, unsigned int count)
{
struct earlycon_device *device = console->data;
struct uart_port *port = &device->port;
uart_console_write(port, s, count, au_putc);
}
static int __init early_au_setup(struct earlycon_device *dev, const char *opt)
{
rt288x_setup(&dev->port);
dev->con->write = au_early_serial8250_write;
return 0;
}
OF_EARLYCON_DECLARE(palmchip, "ralink,rt2880-uart", early_au_setup);
#endif
MODULE_DESCRIPTION("RT288x/Au1xxx UART driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/tty/serial/8250/8250_rt288x.c |
// SPDX-License-Identifier: GPL-2.0+
/************************************************************************
* Copyright 2003 Digi International (www.digi.com)
*
* Copyright (C) 2004 IBM Corporation. All rights reserved.
*
* Contact Information:
* Scott H Kilau <[email protected]>
* Wendy Xiong <[email protected]>
*
*
***********************************************************************/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "jsm.h"
MODULE_AUTHOR("Digi International, https://www.digi.com");
MODULE_DESCRIPTION("Driver for the Digi International Neo and Classic PCI based product line");
MODULE_LICENSE("GPL");
#define JSM_DRIVER_NAME "jsm"
#define NR_PORTS 32
#define JSM_MINOR_START 0
struct uart_driver jsm_uart_driver = {
.owner = THIS_MODULE,
.driver_name = JSM_DRIVER_NAME,
.dev_name = "ttyn",
.major = 0,
.minor = JSM_MINOR_START,
.nr = NR_PORTS,
};
static pci_ers_result_t jsm_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state);
static pci_ers_result_t jsm_io_slot_reset(struct pci_dev *pdev);
static void jsm_io_resume(struct pci_dev *pdev);
static const struct pci_error_handlers jsm_err_handler = {
.error_detected = jsm_io_error_detected,
.slot_reset = jsm_io_slot_reset,
.resume = jsm_io_resume,
};
int jsm_debug;
module_param(jsm_debug, int, 0);
MODULE_PARM_DESC(jsm_debug, "Driver debugging level");
static int jsm_probe_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int rc = 0;
struct jsm_board *brd;
static int adapter_count;
rc = pci_enable_device(pdev);
if (rc) {
dev_err(&pdev->dev, "Device enable FAILED\n");
goto out;
}
rc = pci_request_regions(pdev, JSM_DRIVER_NAME);
if (rc) {
dev_err(&pdev->dev, "pci_request_region FAILED\n");
goto out_disable_device;
}
brd = kzalloc(sizeof(*brd), GFP_KERNEL);
if (!brd) {
rc = -ENOMEM;
goto out_release_regions;
}
/* store the info for the board we've found */
brd->boardnum = adapter_count++;
brd->pci_dev = pdev;
switch (pdev->device) {
case PCI_DEVICE_ID_NEO_2DB9:
case PCI_DEVICE_ID_NEO_2DB9PRI:
case PCI_DEVICE_ID_NEO_2RJ45:
case PCI_DEVICE_ID_NEO_2RJ45PRI:
case PCI_DEVICE_ID_NEO_2_422_485:
brd->maxports = 2;
break;
case PCI_DEVICE_ID_CLASSIC_4:
case PCI_DEVICE_ID_CLASSIC_4_422:
case PCI_DEVICE_ID_NEO_4:
case PCIE_DEVICE_ID_NEO_4:
case PCIE_DEVICE_ID_NEO_4RJ45:
case PCIE_DEVICE_ID_NEO_4_IBM:
brd->maxports = 4;
break;
case PCI_DEVICE_ID_CLASSIC_8:
case PCI_DEVICE_ID_CLASSIC_8_422:
case PCI_DEVICE_ID_DIGI_NEO_8:
case PCIE_DEVICE_ID_NEO_8:
case PCIE_DEVICE_ID_NEO_8RJ45:
brd->maxports = 8;
break;
default:
brd->maxports = 1;
break;
}
spin_lock_init(&brd->bd_intr_lock);
/* store which revision we have */
brd->rev = pdev->revision;
brd->irq = pdev->irq;
switch (pdev->device) {
case PCI_DEVICE_ID_CLASSIC_4:
case PCI_DEVICE_ID_CLASSIC_4_422:
case PCI_DEVICE_ID_CLASSIC_8:
case PCI_DEVICE_ID_CLASSIC_8_422:
jsm_dbg(INIT, &brd->pci_dev,
"jsm_found_board - Classic adapter\n");
/*
* For PCI ClassicBoards
* PCI Local Address (.i.e. "resource" number) space
* 0 PLX Memory Mapped Config
* 1 PLX I/O Mapped Config
* 2 I/O Mapped UARTs and Status
* 3 Memory Mapped VPD
* 4 Memory Mapped UARTs and Status
*/
/* Get the PCI Base Address Registers */
brd->membase = pci_resource_start(pdev, 4);
brd->membase_end = pci_resource_end(pdev, 4);
if (brd->membase & 0x1)
brd->membase &= ~0x3;
else
brd->membase &= ~0xF;
brd->iobase = pci_resource_start(pdev, 1);
brd->iobase_end = pci_resource_end(pdev, 1);
brd->iobase = ((unsigned int)(brd->iobase)) & 0xFFFE;
/* Assign the board_ops struct */
brd->bd_ops = &jsm_cls_ops;
brd->bd_uart_offset = 0x8;
brd->bd_dividend = 921600;
brd->re_map_membase = ioremap(brd->membase,
pci_resource_len(pdev, 4));
if (!brd->re_map_membase) {
dev_err(&pdev->dev,
"Card has no PCI Memory resources, failing board.\n");
rc = -ENOMEM;
goto out_kfree_brd;
}
/*
* Enable Local Interrupt 1 (0x1),
* Local Interrupt 1 Polarity Active high (0x2),
* Enable PCI interrupt (0x43)
*/
outb(0x43, brd->iobase + 0x4c);
break;
case PCI_DEVICE_ID_NEO_2DB9:
case PCI_DEVICE_ID_NEO_2DB9PRI:
case PCI_DEVICE_ID_NEO_2RJ45:
case PCI_DEVICE_ID_NEO_2RJ45PRI:
case PCI_DEVICE_ID_NEO_2_422_485:
case PCI_DEVICE_ID_NEO_4:
case PCIE_DEVICE_ID_NEO_4:
case PCIE_DEVICE_ID_NEO_4RJ45:
case PCIE_DEVICE_ID_NEO_4_IBM:
case PCI_DEVICE_ID_DIGI_NEO_8:
case PCIE_DEVICE_ID_NEO_8:
case PCIE_DEVICE_ID_NEO_8RJ45:
jsm_dbg(INIT, &brd->pci_dev, "jsm_found_board - NEO adapter\n");
/* get the PCI Base Address Registers */
brd->membase = pci_resource_start(pdev, 0);
brd->membase_end = pci_resource_end(pdev, 0);
if (brd->membase & 1)
brd->membase &= ~0x3;
else
brd->membase &= ~0xF;
/* Assign the board_ops struct */
brd->bd_ops = &jsm_neo_ops;
brd->bd_uart_offset = 0x200;
brd->bd_dividend = 921600;
brd->re_map_membase = ioremap(brd->membase,
pci_resource_len(pdev, 0));
if (!brd->re_map_membase) {
dev_err(&pdev->dev,
"Card has no PCI Memory resources, failing board.\n");
rc = -ENOMEM;
goto out_kfree_brd;
}
break;
default:
rc = -ENXIO;
goto out_kfree_brd;
}
rc = request_irq(brd->irq, brd->bd_ops->intr, IRQF_SHARED, "JSM", brd);
if (rc) {
dev_warn(&pdev->dev, "Failed to hook IRQ %d\n", brd->irq);
goto out_iounmap;
}
rc = jsm_tty_init(brd);
if (rc < 0) {
dev_err(&pdev->dev, "Can't init tty devices (%d)\n", rc);
rc = -ENXIO;
goto out_free_irq;
}
rc = jsm_uart_port_init(brd);
if (rc < 0) {
/* XXX: leaking all resources from jsm_tty_init here! */
dev_err(&pdev->dev, "Can't init uart port (%d)\n", rc);
rc = -ENXIO;
goto out_free_irq;
}
/* Log the information about the board */
dev_info(&pdev->dev, "board %d: Digi Classic/Neo (rev %d), irq %d\n",
adapter_count, brd->rev, brd->irq);
pci_set_drvdata(pdev, brd);
pci_save_state(pdev);
return 0;
out_free_irq:
jsm_remove_uart_port(brd);
free_irq(brd->irq, brd);
out_iounmap:
iounmap(brd->re_map_membase);
out_kfree_brd:
kfree(brd);
out_release_regions:
pci_release_regions(pdev);
out_disable_device:
pci_disable_device(pdev);
out:
return rc;
}
static void jsm_remove_one(struct pci_dev *pdev)
{
struct jsm_board *brd = pci_get_drvdata(pdev);
int i = 0;
switch (pdev->device) {
case PCI_DEVICE_ID_CLASSIC_4:
case PCI_DEVICE_ID_CLASSIC_4_422:
case PCI_DEVICE_ID_CLASSIC_8:
case PCI_DEVICE_ID_CLASSIC_8_422:
/* Tell card not to interrupt anymore. */
outb(0x0, brd->iobase + 0x4c);
break;
default:
break;
}
jsm_remove_uart_port(brd);
free_irq(brd->irq, brd);
iounmap(brd->re_map_membase);
/* Free all allocated channels structs */
for (i = 0; i < brd->maxports; i++) {
if (brd->channels[i]) {
kfree(brd->channels[i]->ch_rqueue);
kfree(brd->channels[i]->ch_equeue);
kfree(brd->channels[i]);
}
}
pci_release_regions(pdev);
pci_disable_device(pdev);
kfree(brd);
}
static const struct pci_device_id jsm_pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9), 0, 0, 0 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2DB9PRI), 0, 0, 1 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45), 0, 0, 2 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2RJ45PRI), 0, 0, 3 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_4_IBM), 0, 0, 4 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_NEO_8), 0, 0, 5 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_4), 0, 0, 6 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_1_422), 0, 0, 7 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_1_422_485), 0, 0, 8 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_NEO_2_422_485), 0, 0, 9 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_8), 0, 0, 10 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_4), 0, 0, 11 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_4RJ45), 0, 0, 12 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_8RJ45), 0, 0, 13 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_CLASSIC_4), 0, 0, 14 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_CLASSIC_4_422), 0, 0, 15 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_CLASSIC_8), 0, 0, 16 },
{ PCI_DEVICE(PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_CLASSIC_8_422), 0, 0, 17 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, jsm_pci_tbl);
static struct pci_driver jsm_driver = {
.name = JSM_DRIVER_NAME,
.id_table = jsm_pci_tbl,
.probe = jsm_probe_one,
.remove = jsm_remove_one,
.err_handler = &jsm_err_handler,
};
static pci_ers_result_t jsm_io_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
struct jsm_board *brd = pci_get_drvdata(pdev);
jsm_remove_uart_port(brd);
return PCI_ERS_RESULT_NEED_RESET;
}
static pci_ers_result_t jsm_io_slot_reset(struct pci_dev *pdev)
{
int rc;
rc = pci_enable_device(pdev);
if (rc)
return PCI_ERS_RESULT_DISCONNECT;
pci_set_master(pdev);
return PCI_ERS_RESULT_RECOVERED;
}
static void jsm_io_resume(struct pci_dev *pdev)
{
struct jsm_board *brd = pci_get_drvdata(pdev);
pci_restore_state(pdev);
pci_save_state(pdev);
jsm_uart_port_init(brd);
}
static int __init jsm_init_module(void)
{
int rc;
rc = uart_register_driver(&jsm_uart_driver);
if (!rc) {
rc = pci_register_driver(&jsm_driver);
if (rc)
uart_unregister_driver(&jsm_uart_driver);
}
return rc;
}
static void __exit jsm_exit_module(void)
{
pci_unregister_driver(&jsm_driver);
uart_unregister_driver(&jsm_uart_driver);
}
module_init(jsm_init_module);
module_exit(jsm_exit_module);
| linux-master | drivers/tty/serial/jsm/jsm_driver.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2003 Digi International (www.digi.com)
* Scott H Kilau <Scott_Kilau at digi dot com>
*
* NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
*
* This is shared code between Digi's CVS archive and the
* Linux Kernel sources.
* Changing the source just for reformatting needlessly breaks
* our CVS diff history.
*
* Send any bug fixes/changes to: Eng.Linux at digi dot com.
* Thank you.
*
*/
#include <linux/delay.h> /* For udelay */
#include <linux/io.h> /* For read[bwl]/write[bwl] */
#include <linux/serial.h> /* For struct async_serial */
#include <linux/serial_reg.h> /* For the various UART offsets */
#include <linux/pci.h>
#include <linux/tty.h>
#include "jsm.h" /* Driver main header file */
static struct {
unsigned int rate;
unsigned int cflag;
} baud_rates[] = {
{ 921600, B921600 },
{ 460800, B460800 },
{ 230400, B230400 },
{ 115200, B115200 },
{ 57600, B57600 },
{ 38400, B38400 },
{ 19200, B19200 },
{ 9600, B9600 },
{ 4800, B4800 },
{ 2400, B2400 },
{ 1200, B1200 },
{ 600, B600 },
{ 300, B300 },
{ 200, B200 },
{ 150, B150 },
{ 134, B134 },
{ 110, B110 },
{ 75, B75 },
{ 50, B50 },
};
static void cls_set_cts_flow_control(struct jsm_channel *ch)
{
u8 lcrb = readb(&ch->ch_cls_uart->lcr);
u8 ier = readb(&ch->ch_cls_uart->ier);
u8 isr_fcr = 0;
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn on CTS flow control, turn off IXON flow control */
isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
isr_fcr &= ~(UART_EXAR654_EFR_IXON);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/*
* Enable interrupts for CTS flow, turn off interrupts for
* received XOFF chars
*/
ier |= (UART_EXAR654_IER_CTSDSR);
ier &= ~(UART_EXAR654_IER_XOFF);
writeb(ier, &ch->ch_cls_uart->ier);
/* Set the usual FIFO values */
writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
ch->ch_t_tlevel = 16;
}
static void cls_set_ixon_flow_control(struct jsm_channel *ch)
{
u8 lcrb = readb(&ch->ch_cls_uart->lcr);
u8 ier = readb(&ch->ch_cls_uart->ier);
u8 isr_fcr = 0;
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn on IXON flow control, turn off CTS flow control */
isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Now set our current start/stop chars while in enhanced mode */
writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
writeb(0, &ch->ch_cls_uart->lsr);
writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
writeb(0, &ch->ch_cls_uart->spr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/*
* Disable interrupts for CTS flow, turn on interrupts for
* received XOFF chars
*/
ier &= ~(UART_EXAR654_IER_CTSDSR);
ier |= (UART_EXAR654_IER_XOFF);
writeb(ier, &ch->ch_cls_uart->ier);
/* Set the usual FIFO values */
writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
}
static void cls_set_no_output_flow_control(struct jsm_channel *ch)
{
u8 lcrb = readb(&ch->ch_cls_uart->lcr);
u8 ier = readb(&ch->ch_cls_uart->ier);
u8 isr_fcr = 0;
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn off IXON flow control, turn off CTS flow control */
isr_fcr |= (UART_EXAR654_EFR_ECB);
isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/*
* Disable interrupts for CTS flow, turn off interrupts for
* received XOFF chars
*/
ier &= ~(UART_EXAR654_IER_CTSDSR);
ier &= ~(UART_EXAR654_IER_XOFF);
writeb(ier, &ch->ch_cls_uart->ier);
/* Set the usual FIFO values */
writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
ch->ch_r_watermark = 0;
ch->ch_t_tlevel = 16;
ch->ch_r_tlevel = 16;
}
static void cls_set_rts_flow_control(struct jsm_channel *ch)
{
u8 lcrb = readb(&ch->ch_cls_uart->lcr);
u8 ier = readb(&ch->ch_cls_uart->ier);
u8 isr_fcr = 0;
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn on RTS flow control, turn off IXOFF flow control */
isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/* Enable interrupts for RTS flow */
ier |= (UART_EXAR654_IER_RTSDTR);
writeb(ier, &ch->ch_cls_uart->ier);
/* Set the usual FIFO values */
writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
ch->ch_r_watermark = 4;
ch->ch_r_tlevel = 8;
}
static void cls_set_ixoff_flow_control(struct jsm_channel *ch)
{
u8 lcrb = readb(&ch->ch_cls_uart->lcr);
u8 ier = readb(&ch->ch_cls_uart->ier);
u8 isr_fcr = 0;
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn on IXOFF flow control, turn off RTS flow control */
isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Now set our current start/stop chars while in enhanced mode */
writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
writeb(0, &ch->ch_cls_uart->lsr);
writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
writeb(0, &ch->ch_cls_uart->spr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/* Disable interrupts for RTS flow */
ier &= ~(UART_EXAR654_IER_RTSDTR);
writeb(ier, &ch->ch_cls_uart->ier);
/* Set the usual FIFO values */
writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
}
static void cls_set_no_input_flow_control(struct jsm_channel *ch)
{
u8 lcrb = readb(&ch->ch_cls_uart->lcr);
u8 ier = readb(&ch->ch_cls_uart->ier);
u8 isr_fcr = 0;
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn off IXOFF flow control, turn off RTS flow control */
isr_fcr |= (UART_EXAR654_EFR_ECB);
isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/* Disable interrupts for RTS flow */
ier &= ~(UART_EXAR654_IER_RTSDTR);
writeb(ier, &ch->ch_cls_uart->ier);
/* Set the usual FIFO values */
writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
&ch->ch_cls_uart->isr_fcr);
ch->ch_t_tlevel = 16;
ch->ch_r_tlevel = 16;
}
/*
* cls_clear_break.
* Determines whether its time to shut off break condition.
*
* No locks are assumed to be held when calling this function.
* channel lock is held and released in this function.
*/
static void cls_clear_break(struct jsm_channel *ch)
{
unsigned long lock_flags;
spin_lock_irqsave(&ch->ch_lock, lock_flags);
/* Turn break off, and unset some variables */
if (ch->ch_flags & CH_BREAK_SENDING) {
u8 temp = readb(&ch->ch_cls_uart->lcr);
writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
ch->ch_flags &= ~(CH_BREAK_SENDING);
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
"clear break Finishing UART_LCR_SBC! finished: %lx\n",
jiffies);
}
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
static void cls_disable_receiver(struct jsm_channel *ch)
{
u8 tmp = readb(&ch->ch_cls_uart->ier);
tmp &= ~(UART_IER_RDI);
writeb(tmp, &ch->ch_cls_uart->ier);
}
static void cls_enable_receiver(struct jsm_channel *ch)
{
u8 tmp = readb(&ch->ch_cls_uart->ier);
tmp |= (UART_IER_RDI);
writeb(tmp, &ch->ch_cls_uart->ier);
}
/* Make the UART raise any of the output signals we want up */
static void cls_assert_modem_signals(struct jsm_channel *ch)
{
if (!ch)
return;
writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr);
}
static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch)
{
int qleft = 0;
u8 linestatus;
u8 error_mask = 0;
u16 head;
u16 tail;
unsigned long flags;
if (!ch)
return;
spin_lock_irqsave(&ch->ch_lock, flags);
/* cache head and tail of queue */
head = ch->ch_r_head & RQUEUEMASK;
tail = ch->ch_r_tail & RQUEUEMASK;
ch->ch_cached_lsr = 0;
/* Store how much space we have left in the queue */
qleft = tail - head - 1;
if (qleft < 0)
qleft += RQUEUEMASK + 1;
/*
* Create a mask to determine whether we should
* insert the character (if any) into our queue.
*/
if (ch->ch_c_iflag & IGNBRK)
error_mask |= UART_LSR_BI;
while (1) {
/*
* Grab the linestatus register, we need to
* check to see if there is any data to read
*/
linestatus = readb(&ch->ch_cls_uart->lsr);
/* Break out if there is no data to fetch */
if (!(linestatus & UART_LSR_DR))
break;
/*
* Discard character if we are ignoring the error mask
* which in this case is the break signal.
*/
if (linestatus & error_mask) {
linestatus = 0;
readb(&ch->ch_cls_uart->txrx);
continue;
}
/*
* If our queue is full, we have no choice but to drop some
* data. The assumption is that HWFLOW or SWFLOW should have
* stopped things way way before we got to this point.
*
* I decided that I wanted to ditch the oldest data first,
* I hope thats okay with everyone? Yes? Good.
*/
while (qleft < 1) {
tail = (tail + 1) & RQUEUEMASK;
ch->ch_r_tail = tail;
ch->ch_err_overrun++;
qleft++;
}
ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
| UART_LSR_FE);
ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
qleft--;
if (ch->ch_equeue[head] & UART_LSR_PE)
ch->ch_err_parity++;
if (ch->ch_equeue[head] & UART_LSR_BI)
ch->ch_err_break++;
if (ch->ch_equeue[head] & UART_LSR_FE)
ch->ch_err_frame++;
/* Add to, and flip head if needed */
head = (head + 1) & RQUEUEMASK;
ch->ch_rxcount++;
}
/*
* Write new final heads to channel structure.
*/
ch->ch_r_head = head & RQUEUEMASK;
ch->ch_e_head = head & EQUEUEMASK;
spin_unlock_irqrestore(&ch->ch_lock, flags);
}
static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch)
{
u16 tail;
int n;
int qlen;
u32 len_written = 0;
struct circ_buf *circ;
if (!ch)
return;
circ = &ch->uart_port.state->xmit;
/* No data to write to the UART */
if (uart_circ_empty(circ))
return;
/* If port is "stopped", don't send any data to the UART */
if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
return;
/* We have to do it this way, because of the EXAR TXFIFO count bug. */
if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
return;
n = 32;
/* cache tail of queue */
tail = circ->tail & (UART_XMIT_SIZE - 1);
qlen = uart_circ_chars_pending(circ);
/* Find minimum of the FIFO space, versus queue length */
n = min(n, qlen);
while (n > 0) {
writeb(circ->buf[tail], &ch->ch_cls_uart->txrx);
tail = (tail + 1) & (UART_XMIT_SIZE - 1);
n--;
ch->ch_txcount++;
len_written++;
}
/* Update the final tail */
circ->tail = tail & (UART_XMIT_SIZE - 1);
if (len_written > ch->ch_t_tlevel)
ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
if (uart_circ_empty(circ))
uart_write_wakeup(&ch->uart_port);
}
static void cls_parse_modem(struct jsm_channel *ch, u8 signals)
{
u8 msignals = signals;
jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
"neo_parse_modem: port: %d msignals: %x\n",
ch->ch_portnum, msignals);
/*
* Scrub off lower bits.
* They signify delta's, which I don't care about
* Keep DDCD and DDSR though
*/
msignals &= 0xf8;
if (msignals & UART_MSR_DDCD)
uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
if (msignals & UART_MSR_DDSR)
uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS);
if (msignals & UART_MSR_DCD)
ch->ch_mistat |= UART_MSR_DCD;
else
ch->ch_mistat &= ~UART_MSR_DCD;
if (msignals & UART_MSR_DSR)
ch->ch_mistat |= UART_MSR_DSR;
else
ch->ch_mistat &= ~UART_MSR_DSR;
if (msignals & UART_MSR_RI)
ch->ch_mistat |= UART_MSR_RI;
else
ch->ch_mistat &= ~UART_MSR_RI;
if (msignals & UART_MSR_CTS)
ch->ch_mistat |= UART_MSR_CTS;
else
ch->ch_mistat &= ~UART_MSR_CTS;
jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
"Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
ch->ch_portnum,
!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
}
/* Parse the ISR register for the specific port */
static inline void cls_parse_isr(struct jsm_board *brd, uint port)
{
struct jsm_channel *ch;
u8 isr = 0;
unsigned long flags;
/*
* No need to verify board pointer, it was already
* verified in the interrupt routine.
*/
if (port >= brd->nasync)
return;
ch = brd->channels[port];
if (!ch)
return;
/* Here we try to figure out what caused the interrupt to happen */
while (1) {
isr = readb(&ch->ch_cls_uart->isr_fcr);
/* Bail if no pending interrupt on port */
if (isr & UART_IIR_NO_INT)
break;
/* Receive Interrupt pending */
if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
/* Read data from uart -> queue */
cls_copy_data_from_uart_to_queue(ch);
jsm_check_queue_flow_control(ch);
}
/* Transmit Hold register empty pending */
if (isr & UART_IIR_THRI) {
/* Transfer data (if any) from Write Queue -> UART. */
spin_lock_irqsave(&ch->ch_lock, flags);
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
spin_unlock_irqrestore(&ch->ch_lock, flags);
cls_copy_data_from_queue_to_uart(ch);
}
/*
* CTS/RTS change of state:
* Don't need to do anything, the cls_parse_modem
* below will grab the updated modem signals.
*/
/* Parse any modem signal changes */
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
}
}
/* Channel lock MUST be held before calling this function! */
static void cls_flush_uart_write(struct jsm_channel *ch)
{
u8 tmp = 0;
u8 i = 0;
if (!ch)
return;
writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
&ch->ch_cls_uart->isr_fcr);
for (i = 0; i < 10; i++) {
/* Check to see if the UART feels it completely flushed FIFO */
tmp = readb(&ch->ch_cls_uart->isr_fcr);
if (tmp & UART_FCR_CLEAR_XMIT) {
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
"Still flushing TX UART... i: %d\n", i);
udelay(10);
} else
break;
}
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
}
/* Channel lock MUST be held before calling this function! */
static void cls_flush_uart_read(struct jsm_channel *ch)
{
if (!ch)
return;
/*
* For complete POSIX compatibility, we should be purging the
* read FIFO in the UART here.
*
* However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
* incorrectly flushes write data as well as just basically trashing the
* FIFO.
*
* Presumably, this is a bug in this UART.
*/
udelay(10);
}
static void cls_send_start_character(struct jsm_channel *ch)
{
if (!ch)
return;
if (ch->ch_startc != __DISABLED_CHAR) {
ch->ch_xon_sends++;
writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
}
}
static void cls_send_stop_character(struct jsm_channel *ch)
{
if (!ch)
return;
if (ch->ch_stopc != __DISABLED_CHAR) {
ch->ch_xoff_sends++;
writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
}
}
/*
* cls_param()
* Send any/all changes to the line to the UART.
*/
static void cls_param(struct jsm_channel *ch)
{
u8 lcr = 0;
u8 uart_lcr = 0;
u8 ier = 0;
u32 baud = 9600;
int quot = 0;
struct jsm_board *bd;
int i;
unsigned int cflag;
bd = ch->ch_bd;
if (!bd)
return;
/*
* If baud rate is zero, flush queues, and set mval to drop DTR.
*/
if ((ch->ch_c_cflag & CBAUD) == B0) {
ch->ch_r_head = 0;
ch->ch_r_tail = 0;
ch->ch_e_head = 0;
ch->ch_e_tail = 0;
cls_flush_uart_write(ch);
cls_flush_uart_read(ch);
/* The baudrate is B0 so all modem lines are to be dropped. */
ch->ch_flags |= (CH_BAUD0);
ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
cls_assert_modem_signals(ch);
return;
}
cflag = C_BAUD(ch->uart_port.state->port.tty);
baud = 9600;
for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
if (baud_rates[i].cflag == cflag) {
baud = baud_rates[i].rate;
break;
}
}
if (ch->ch_flags & CH_BAUD0)
ch->ch_flags &= ~(CH_BAUD0);
if (ch->ch_c_cflag & PARENB)
lcr |= UART_LCR_PARITY;
if (!(ch->ch_c_cflag & PARODD))
lcr |= UART_LCR_EPAR;
if (ch->ch_c_cflag & CMSPAR)
lcr |= UART_LCR_SPAR;
if (ch->ch_c_cflag & CSTOPB)
lcr |= UART_LCR_STOP;
lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
ier = readb(&ch->ch_cls_uart->ier);
uart_lcr = readb(&ch->ch_cls_uart->lcr);
quot = ch->ch_bd->bd_dividend / baud;
if (quot != 0) {
writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
writeb((quot >> 8), &ch->ch_cls_uart->ier);
writeb(lcr, &ch->ch_cls_uart->lcr);
}
if (uart_lcr != lcr)
writeb(lcr, &ch->ch_cls_uart->lcr);
if (ch->ch_c_cflag & CREAD)
ier |= (UART_IER_RDI | UART_IER_RLSI);
ier |= (UART_IER_THRI | UART_IER_MSI);
writeb(ier, &ch->ch_cls_uart->ier);
if (ch->ch_c_cflag & CRTSCTS)
cls_set_cts_flow_control(ch);
else if (ch->ch_c_iflag & IXON) {
/*
* If start/stop is set to disable,
* then we should disable flow control.
*/
if ((ch->ch_startc == __DISABLED_CHAR) ||
(ch->ch_stopc == __DISABLED_CHAR))
cls_set_no_output_flow_control(ch);
else
cls_set_ixon_flow_control(ch);
} else
cls_set_no_output_flow_control(ch);
if (ch->ch_c_cflag & CRTSCTS)
cls_set_rts_flow_control(ch);
else if (ch->ch_c_iflag & IXOFF) {
/*
* If start/stop is set to disable,
* then we should disable flow control.
*/
if ((ch->ch_startc == __DISABLED_CHAR) ||
(ch->ch_stopc == __DISABLED_CHAR))
cls_set_no_input_flow_control(ch);
else
cls_set_ixoff_flow_control(ch);
} else
cls_set_no_input_flow_control(ch);
cls_assert_modem_signals(ch);
/* get current status of the modem signals now */
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
}
/*
* cls_intr()
*
* Classic specific interrupt handler.
*/
static irqreturn_t cls_intr(int irq, void *voidbrd)
{
struct jsm_board *brd = voidbrd;
unsigned long lock_flags;
unsigned char uart_poll;
uint i = 0;
/* Lock out the slow poller from running on this board. */
spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
/*
* Check the board's global interrupt offset to see if we
* acctually do have an interrupt pending on us.
*/
uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
__FILE__, __LINE__, uart_poll);
if (!uart_poll) {
jsm_dbg(INTR, &brd->pci_dev,
"Kernel interrupted to me, but no pending interrupts...\n");
spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
return IRQ_NONE;
}
/* At this point, we have at least SOMETHING to service, dig further. */
/* Parse each port to find out what caused the interrupt */
for (i = 0; i < brd->nasync; i++)
cls_parse_isr(brd, i);
spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
return IRQ_HANDLED;
}
/* Inits UART */
static void cls_uart_init(struct jsm_channel *ch)
{
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
unsigned char isr_fcr = 0;
writeb(0, &ch->ch_cls_uart->ier);
/*
* The Enhanced Register Set may only be accessed when
* the Line Control Register is set to 0xBFh.
*/
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
/* Turn on Enhanced/Extended controls */
isr_fcr |= (UART_EXAR654_EFR_ECB);
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
/* Write old LCR value back out, which turns enhanced access off */
writeb(lcrb, &ch->ch_cls_uart->lcr);
/* Clear out UART and FIFO */
readb(&ch->ch_cls_uart->txrx);
writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
&ch->ch_cls_uart->isr_fcr);
udelay(10);
ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
readb(&ch->ch_cls_uart->lsr);
readb(&ch->ch_cls_uart->msr);
}
/*
* Turns off UART.
*/
static void cls_uart_off(struct jsm_channel *ch)
{
/* Stop all interrupts from accurring. */
writeb(0, &ch->ch_cls_uart->ier);
}
/*
* cls_get_uarts_bytes_left.
* Returns 0 is nothing left in the FIFO, returns 1 otherwise.
*
* The channel lock MUST be held by the calling function.
*/
static u32 cls_get_uart_bytes_left(struct jsm_channel *ch)
{
u8 left = 0;
u8 lsr = readb(&ch->ch_cls_uart->lsr);
/* Determine whether the Transmitter is empty or not */
if (!(lsr & UART_LSR_TEMT))
left = 1;
else {
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
left = 0;
}
return left;
}
/*
* cls_send_break.
* Starts sending a break thru the UART.
*
* The channel lock MUST be held by the calling function.
*/
static void cls_send_break(struct jsm_channel *ch)
{
/* Tell the UART to start sending the break */
if (!(ch->ch_flags & CH_BREAK_SENDING)) {
u8 temp = readb(&ch->ch_cls_uart->lcr);
writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
ch->ch_flags |= (CH_BREAK_SENDING);
}
}
/*
* cls_send_immediate_char.
* Sends a specific character as soon as possible to the UART,
* jumping over any bytes that might be in the write queue.
*
* The channel lock MUST be held by the calling function.
*/
static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c)
{
writeb(c, &ch->ch_cls_uart->txrx);
}
struct board_ops jsm_cls_ops = {
.intr = cls_intr,
.uart_init = cls_uart_init,
.uart_off = cls_uart_off,
.param = cls_param,
.assert_modem_signals = cls_assert_modem_signals,
.flush_uart_write = cls_flush_uart_write,
.flush_uart_read = cls_flush_uart_read,
.disable_receiver = cls_disable_receiver,
.enable_receiver = cls_enable_receiver,
.send_break = cls_send_break,
.clear_break = cls_clear_break,
.send_start_character = cls_send_start_character,
.send_stop_character = cls_send_stop_character,
.copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
.get_uart_bytes_left = cls_get_uart_bytes_left,
.send_immediate_char = cls_send_immediate_char
};
| linux-master | drivers/tty/serial/jsm/jsm_cls.c |
// SPDX-License-Identifier: GPL-2.0+
/************************************************************************
* Copyright 2003 Digi International (www.digi.com)
*
* Copyright (C) 2004 IBM Corporation. All rights reserved.
*
* Contact Information:
* Scott H Kilau <[email protected]>
* Ananda Venkatarman <[email protected]>
* Modifications:
* 01/19/06: changed jsm_input routine to use the dynamically allocated
* tty_buffer changes. Contributors: Scott Kilau and Ananda V.
***********************************************************************/
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_reg.h>
#include <linux/delay.h> /* For udelay */
#include <linux/pci.h>
#include <linux/slab.h>
#include "jsm.h"
static DECLARE_BITMAP(linemap, MAXLINES);
static void jsm_carrier(struct jsm_channel *ch);
static inline int jsm_get_mstat(struct jsm_channel *ch)
{
unsigned char mstat;
int result;
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, "start\n");
mstat = (ch->ch_mostat | ch->ch_mistat);
result = 0;
if (mstat & UART_MCR_DTR)
result |= TIOCM_DTR;
if (mstat & UART_MCR_RTS)
result |= TIOCM_RTS;
if (mstat & UART_MSR_CTS)
result |= TIOCM_CTS;
if (mstat & UART_MSR_DSR)
result |= TIOCM_DSR;
if (mstat & UART_MSR_RI)
result |= TIOCM_RI;
if (mstat & UART_MSR_DCD)
result |= TIOCM_CD;
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, "finish\n");
return result;
}
static unsigned int jsm_tty_tx_empty(struct uart_port *port)
{
return TIOCSER_TEMT;
}
/*
* Return modem signals to ld.
*/
static unsigned int jsm_tty_get_mctrl(struct uart_port *port)
{
int result;
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n");
result = jsm_get_mstat(channel);
if (result < 0)
return -ENXIO;
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "finish\n");
return result;
}
/*
* jsm_set_modem_info()
*
* Set modem signals, called by ld.
*/
static void jsm_tty_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n");
if (mctrl & TIOCM_RTS)
channel->ch_mostat |= UART_MCR_RTS;
else
channel->ch_mostat &= ~UART_MCR_RTS;
if (mctrl & TIOCM_DTR)
channel->ch_mostat |= UART_MCR_DTR;
else
channel->ch_mostat &= ~UART_MCR_DTR;
channel->ch_bd->bd_ops->assert_modem_signals(channel);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "finish\n");
udelay(10);
}
/*
* jsm_tty_write()
*
* Take data from the user or kernel and send it out to the FEP.
* In here exists all the Transparent Print magic as well.
*/
static void jsm_tty_write(struct uart_port *port)
{
struct jsm_channel *channel;
channel = container_of(port, struct jsm_channel, uart_port);
channel->ch_bd->bd_ops->copy_data_from_queue_to_uart(channel);
}
static void jsm_tty_start_tx(struct uart_port *port)
{
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n");
channel->ch_flags &= ~(CH_STOP);
jsm_tty_write(port);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "finish\n");
}
static void jsm_tty_stop_tx(struct uart_port *port)
{
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "start\n");
channel->ch_flags |= (CH_STOP);
jsm_dbg(IOCTL, &channel->ch_bd->pci_dev, "finish\n");
}
static void jsm_tty_send_xchar(struct uart_port *port, char ch)
{
unsigned long lock_flags;
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
struct ktermios *termios;
spin_lock_irqsave(&port->lock, lock_flags);
termios = &port->state->port.tty->termios;
if (ch == termios->c_cc[VSTART])
channel->ch_bd->bd_ops->send_start_character(channel);
if (ch == termios->c_cc[VSTOP])
channel->ch_bd->bd_ops->send_stop_character(channel);
spin_unlock_irqrestore(&port->lock, lock_flags);
}
static void jsm_tty_stop_rx(struct uart_port *port)
{
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
channel->ch_bd->bd_ops->disable_receiver(channel);
}
static void jsm_tty_break(struct uart_port *port, int break_state)
{
unsigned long lock_flags;
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
spin_lock_irqsave(&port->lock, lock_flags);
if (break_state == -1)
channel->ch_bd->bd_ops->send_break(channel);
else
channel->ch_bd->bd_ops->clear_break(channel);
spin_unlock_irqrestore(&port->lock, lock_flags);
}
static int jsm_tty_open(struct uart_port *port)
{
unsigned long lock_flags;
struct jsm_board *brd;
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
struct ktermios *termios;
/* Get board pointer from our array of majors we have allocated */
brd = channel->ch_bd;
/*
* Allocate channel buffers for read/write/error.
* Set flag, so we don't get trounced on.
*/
channel->ch_flags |= (CH_OPENING);
/* Drop locks, as malloc with GFP_KERNEL can sleep */
if (!channel->ch_rqueue) {
channel->ch_rqueue = kzalloc(RQUEUESIZE, GFP_KERNEL);
if (!channel->ch_rqueue) {
jsm_dbg(INIT, &channel->ch_bd->pci_dev,
"unable to allocate read queue buf\n");
return -ENOMEM;
}
}
if (!channel->ch_equeue) {
channel->ch_equeue = kzalloc(EQUEUESIZE, GFP_KERNEL);
if (!channel->ch_equeue) {
jsm_dbg(INIT, &channel->ch_bd->pci_dev,
"unable to allocate error queue buf\n");
return -ENOMEM;
}
}
channel->ch_flags &= ~(CH_OPENING);
/*
* Initialize if neither terminal is open.
*/
jsm_dbg(OPEN, &channel->ch_bd->pci_dev,
"jsm_open: initializing channel in open...\n");
/*
* Flush input queues.
*/
channel->ch_r_head = channel->ch_r_tail = 0;
channel->ch_e_head = channel->ch_e_tail = 0;
brd->bd_ops->flush_uart_write(channel);
brd->bd_ops->flush_uart_read(channel);
channel->ch_flags = 0;
channel->ch_cached_lsr = 0;
channel->ch_stops_sent = 0;
spin_lock_irqsave(&port->lock, lock_flags);
termios = &port->state->port.tty->termios;
channel->ch_c_cflag = termios->c_cflag;
channel->ch_c_iflag = termios->c_iflag;
channel->ch_c_oflag = termios->c_oflag;
channel->ch_c_lflag = termios->c_lflag;
channel->ch_startc = termios->c_cc[VSTART];
channel->ch_stopc = termios->c_cc[VSTOP];
/* Tell UART to init itself */
brd->bd_ops->uart_init(channel);
/*
* Run param in case we changed anything
*/
brd->bd_ops->param(channel);
jsm_carrier(channel);
channel->ch_open_count++;
spin_unlock_irqrestore(&port->lock, lock_flags);
jsm_dbg(OPEN, &channel->ch_bd->pci_dev, "finish\n");
return 0;
}
static void jsm_tty_close(struct uart_port *port)
{
struct jsm_board *bd;
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
jsm_dbg(CLOSE, &channel->ch_bd->pci_dev, "start\n");
bd = channel->ch_bd;
channel->ch_flags &= ~(CH_STOPI);
channel->ch_open_count--;
/*
* If we have HUPCL set, lower DTR and RTS
*/
if (channel->ch_c_cflag & HUPCL) {
jsm_dbg(CLOSE, &channel->ch_bd->pci_dev,
"Close. HUPCL set, dropping DTR/RTS\n");
/* Drop RTS/DTR */
channel->ch_mostat &= ~(UART_MCR_DTR | UART_MCR_RTS);
bd->bd_ops->assert_modem_signals(channel);
}
/* Turn off UART interrupts for this port */
channel->ch_bd->bd_ops->uart_off(channel);
jsm_dbg(CLOSE, &channel->ch_bd->pci_dev, "finish\n");
}
static void jsm_tty_set_termios(struct uart_port *port,
struct ktermios *termios,
const struct ktermios *old_termios)
{
unsigned long lock_flags;
struct jsm_channel *channel =
container_of(port, struct jsm_channel, uart_port);
spin_lock_irqsave(&port->lock, lock_flags);
channel->ch_c_cflag = termios->c_cflag;
channel->ch_c_iflag = termios->c_iflag;
channel->ch_c_oflag = termios->c_oflag;
channel->ch_c_lflag = termios->c_lflag;
channel->ch_startc = termios->c_cc[VSTART];
channel->ch_stopc = termios->c_cc[VSTOP];
channel->ch_bd->bd_ops->param(channel);
jsm_carrier(channel);
spin_unlock_irqrestore(&port->lock, lock_flags);
}
static const char *jsm_tty_type(struct uart_port *port)
{
return "jsm";
}
static void jsm_tty_release_port(struct uart_port *port)
{
}
static int jsm_tty_request_port(struct uart_port *port)
{
return 0;
}
static void jsm_config_port(struct uart_port *port, int flags)
{
port->type = PORT_JSM;
}
static const struct uart_ops jsm_ops = {
.tx_empty = jsm_tty_tx_empty,
.set_mctrl = jsm_tty_set_mctrl,
.get_mctrl = jsm_tty_get_mctrl,
.stop_tx = jsm_tty_stop_tx,
.start_tx = jsm_tty_start_tx,
.send_xchar = jsm_tty_send_xchar,
.stop_rx = jsm_tty_stop_rx,
.break_ctl = jsm_tty_break,
.startup = jsm_tty_open,
.shutdown = jsm_tty_close,
.set_termios = jsm_tty_set_termios,
.type = jsm_tty_type,
.release_port = jsm_tty_release_port,
.request_port = jsm_tty_request_port,
.config_port = jsm_config_port,
};
/*
* jsm_tty_init()
*
* Init the tty subsystem. Called once per board after board has been
* downloaded and init'ed.
*/
int jsm_tty_init(struct jsm_board *brd)
{
int i;
void __iomem *vaddr;
struct jsm_channel *ch;
if (!brd)
return -ENXIO;
jsm_dbg(INIT, &brd->pci_dev, "start\n");
/*
* Initialize board structure elements.
*/
brd->nasync = brd->maxports;
/*
* Allocate channel memory that might not have been allocated
* when the driver was first loaded.
*/
for (i = 0; i < brd->nasync; i++) {
if (!brd->channels[i]) {
/*
* Okay to malloc with GFP_KERNEL, we are not at
* interrupt context, and there are no locks held.
*/
brd->channels[i] = kzalloc(sizeof(struct jsm_channel), GFP_KERNEL);
if (!brd->channels[i]) {
jsm_dbg(CORE, &brd->pci_dev,
"%s:%d Unable to allocate memory for channel struct\n",
__FILE__, __LINE__);
}
}
}
ch = brd->channels[0];
vaddr = brd->re_map_membase;
/* Set up channel variables */
for (i = 0; i < brd->nasync; i++, ch = brd->channels[i]) {
if (!brd->channels[i])
continue;
spin_lock_init(&ch->ch_lock);
if (brd->bd_uart_offset == 0x200)
ch->ch_neo_uart = vaddr + (brd->bd_uart_offset * i);
else
ch->ch_cls_uart = vaddr + (brd->bd_uart_offset * i);
ch->ch_bd = brd;
ch->ch_portnum = i;
/* .25 second delay */
ch->ch_close_delay = 250;
init_waitqueue_head(&ch->ch_flags_wait);
}
jsm_dbg(INIT, &brd->pci_dev, "finish\n");
return 0;
}
int jsm_uart_port_init(struct jsm_board *brd)
{
int i, rc;
unsigned int line;
if (!brd)
return -ENXIO;
jsm_dbg(INIT, &brd->pci_dev, "start\n");
/*
* Initialize board structure elements.
*/
brd->nasync = brd->maxports;
/* Set up channel variables */
for (i = 0; i < brd->nasync; i++) {
if (!brd->channels[i])
continue;
brd->channels[i]->uart_port.irq = brd->irq;
brd->channels[i]->uart_port.uartclk = 14745600;
brd->channels[i]->uart_port.type = PORT_JSM;
brd->channels[i]->uart_port.iotype = UPIO_MEM;
brd->channels[i]->uart_port.membase = brd->re_map_membase;
brd->channels[i]->uart_port.fifosize = 16;
brd->channels[i]->uart_port.ops = &jsm_ops;
line = find_first_zero_bit(linemap, MAXLINES);
if (line >= MAXLINES) {
printk(KERN_INFO "jsm: linemap is full, added device failed\n");
continue;
} else
set_bit(line, linemap);
brd->channels[i]->uart_port.line = line;
rc = uart_add_one_port(&jsm_uart_driver, &brd->channels[i]->uart_port);
if (rc) {
printk(KERN_INFO "jsm: Port %d failed. Aborting...\n", i);
return rc;
} else
printk(KERN_INFO "jsm: Port %d added\n", i);
}
jsm_dbg(INIT, &brd->pci_dev, "finish\n");
return 0;
}
int jsm_remove_uart_port(struct jsm_board *brd)
{
int i;
struct jsm_channel *ch;
if (!brd)
return -ENXIO;
jsm_dbg(INIT, &brd->pci_dev, "start\n");
/*
* Initialize board structure elements.
*/
brd->nasync = brd->maxports;
/* Set up channel variables */
for (i = 0; i < brd->nasync; i++) {
if (!brd->channels[i])
continue;
ch = brd->channels[i];
clear_bit(ch->uart_port.line, linemap);
uart_remove_one_port(&jsm_uart_driver, &brd->channels[i]->uart_port);
}
jsm_dbg(INIT, &brd->pci_dev, "finish\n");
return 0;
}
void jsm_input(struct jsm_channel *ch)
{
struct jsm_board *bd;
struct tty_struct *tp;
struct tty_port *port;
u32 rmask;
u16 head;
u16 tail;
int data_len;
unsigned long lock_flags;
int len = 0;
int s = 0;
int i = 0;
jsm_dbg(READ, &ch->ch_bd->pci_dev, "start\n");
port = &ch->uart_port.state->port;
tp = port->tty;
bd = ch->ch_bd;
if (!bd)
return;
spin_lock_irqsave(&ch->ch_lock, lock_flags);
/*
*Figure the number of characters in the buffer.
*Exit immediately if none.
*/
rmask = RQUEUEMASK;
head = ch->ch_r_head & rmask;
tail = ch->ch_r_tail & rmask;
data_len = (head - tail) & rmask;
if (data_len == 0) {
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
return;
}
jsm_dbg(READ, &ch->ch_bd->pci_dev, "start\n");
/*
*If the device is not open, or CREAD is off, flush
*input data and return immediately.
*/
if (!tp || !C_CREAD(tp)) {
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"input. dropping %d bytes on port %d...\n",
data_len, ch->ch_portnum);
ch->ch_r_head = tail;
/* Force queue flow control to be released, if needed */
jsm_check_queue_flow_control(ch);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
return;
}
/*
* If we are throttled, simply don't read any data.
*/
if (ch->ch_flags & CH_STOPI) {
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"Port %d throttled, not reading any data. head: %x tail: %x\n",
ch->ch_portnum, head, tail);
return;
}
jsm_dbg(READ, &ch->ch_bd->pci_dev, "start 2\n");
len = tty_buffer_request_room(port, data_len);
/*
* len now contains the most amount of data we can copy,
* bounded either by the flip buffer size or the amount
* of data the card actually has pending...
*/
while (len) {
s = ((head >= tail) ? head : RQUEUESIZE) - tail;
s = min(s, len);
if (s <= 0)
break;
/*
* If conditions are such that ld needs to see all
* UART errors, we will have to walk each character
* and error byte and send them to the buffer one at
* a time.
*/
if (I_PARMRK(tp) || I_BRKINT(tp) || I_INPCK(tp)) {
for (i = 0; i < s; i++) {
u8 chr = ch->ch_rqueue[tail + i];
u8 error = ch->ch_equeue[tail + i];
char flag = TTY_NORMAL;
/*
* Give the Linux ld the flags in the format it
* likes.
*/
if (error & UART_LSR_BI)
flag = TTY_BREAK;
else if (error & UART_LSR_PE)
flag = TTY_PARITY;
else if (error & UART_LSR_FE)
flag = TTY_FRAME;
tty_insert_flip_char(port, chr, flag);
}
} else {
tty_insert_flip_string(port, ch->ch_rqueue + tail, s);
}
tail += s;
len -= s;
/* Flip queue if needed */
tail &= rmask;
}
ch->ch_r_tail = tail & rmask;
ch->ch_e_tail = tail & rmask;
jsm_check_queue_flow_control(ch);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
/* Tell the tty layer its okay to "eat" the data now */
tty_flip_buffer_push(port);
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, "finish\n");
}
static void jsm_carrier(struct jsm_channel *ch)
{
struct jsm_board *bd;
int virt_carrier = 0;
int phys_carrier = 0;
jsm_dbg(CARR, &ch->ch_bd->pci_dev, "start\n");
bd = ch->ch_bd;
if (!bd)
return;
if (ch->ch_mistat & UART_MSR_DCD) {
jsm_dbg(CARR, &ch->ch_bd->pci_dev, "mistat: %x D_CD: %x\n",
ch->ch_mistat, ch->ch_mistat & UART_MSR_DCD);
phys_carrier = 1;
}
if (ch->ch_c_cflag & CLOCAL)
virt_carrier = 1;
jsm_dbg(CARR, &ch->ch_bd->pci_dev, "DCD: physical: %d virt: %d\n",
phys_carrier, virt_carrier);
/*
* Test for a VIRTUAL carrier transition to HIGH.
*/
if (((ch->ch_flags & CH_FCAR) == 0) && (virt_carrier == 1)) {
/*
* When carrier rises, wake any threads waiting
* for carrier in the open routine.
*/
jsm_dbg(CARR, &ch->ch_bd->pci_dev, "carrier: virt DCD rose\n");
if (waitqueue_active(&(ch->ch_flags_wait)))
wake_up_interruptible(&ch->ch_flags_wait);
}
/*
* Test for a PHYSICAL carrier transition to HIGH.
*/
if (((ch->ch_flags & CH_CD) == 0) && (phys_carrier == 1)) {
/*
* When carrier rises, wake any threads waiting
* for carrier in the open routine.
*/
jsm_dbg(CARR, &ch->ch_bd->pci_dev,
"carrier: physical DCD rose\n");
if (waitqueue_active(&(ch->ch_flags_wait)))
wake_up_interruptible(&ch->ch_flags_wait);
}
/*
* Test for a PHYSICAL transition to low, so long as we aren't
* currently ignoring physical transitions (which is what "virtual
* carrier" indicates).
*
* The transition of the virtual carrier to low really doesn't
* matter... it really only means "ignore carrier state", not
* "make pretend that carrier is there".
*/
if ((virt_carrier == 0) && ((ch->ch_flags & CH_CD) != 0)
&& (phys_carrier == 0)) {
/*
* When carrier drops:
*
* Drop carrier on all open units.
*
* Flush queues, waking up any task waiting in the
* line discipline.
*
* Send a hangup to the control terminal.
*
* Enable all select calls.
*/
if (waitqueue_active(&(ch->ch_flags_wait)))
wake_up_interruptible(&ch->ch_flags_wait);
}
/*
* Make sure that our cached values reflect the current reality.
*/
if (virt_carrier == 1)
ch->ch_flags |= CH_FCAR;
else
ch->ch_flags &= ~CH_FCAR;
if (phys_carrier == 1)
ch->ch_flags |= CH_CD;
else
ch->ch_flags &= ~CH_CD;
}
void jsm_check_queue_flow_control(struct jsm_channel *ch)
{
struct board_ops *bd_ops = ch->ch_bd->bd_ops;
int qleft;
/* Store how much space we have left in the queue */
qleft = ch->ch_r_tail - ch->ch_r_head - 1;
if (qleft < 0)
qleft += RQUEUEMASK + 1;
/*
* Check to see if we should enforce flow control on our queue because
* the ld (or user) isn't reading data out of our queue fast enuf.
*
* NOTE: This is done based on what the current flow control of the
* port is set for.
*
* 1) HWFLOW (RTS) - Turn off the UART's Receive interrupt.
* This will cause the UART's FIFO to back up, and force
* the RTS signal to be dropped.
* 2) SWFLOW (IXOFF) - Keep trying to send a stop character to
* the other side, in hopes it will stop sending data to us.
* 3) NONE - Nothing we can do. We will simply drop any extra data
* that gets sent into us when the queue fills up.
*/
if (qleft < 256) {
/* HWFLOW */
if (ch->ch_c_cflag & CRTSCTS) {
if (!(ch->ch_flags & CH_RECEIVER_OFF)) {
bd_ops->disable_receiver(ch);
ch->ch_flags |= (CH_RECEIVER_OFF);
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"Internal queue hit hilevel mark (%d)! Turning off interrupts\n",
qleft);
}
}
/* SWFLOW */
else if (ch->ch_c_iflag & IXOFF) {
if (ch->ch_stops_sent <= MAX_STOPS_SENT) {
bd_ops->send_stop_character(ch);
ch->ch_stops_sent++;
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"Sending stop char! Times sent: %x\n",
ch->ch_stops_sent);
}
}
}
/*
* Check to see if we should unenforce flow control because
* ld (or user) finally read enuf data out of our queue.
*
* NOTE: This is done based on what the current flow control of the
* port is set for.
*
* 1) HWFLOW (RTS) - Turn back on the UART's Receive interrupt.
* This will cause the UART's FIFO to raise RTS back up,
* which will allow the other side to start sending data again.
* 2) SWFLOW (IXOFF) - Send a start character to
* the other side, so it will start sending data to us again.
* 3) NONE - Do nothing. Since we didn't do anything to turn off the
* other side, we don't need to do anything now.
*/
if (qleft > (RQUEUESIZE / 2)) {
/* HWFLOW */
if (ch->ch_c_cflag & CRTSCTS) {
if (ch->ch_flags & CH_RECEIVER_OFF) {
bd_ops->enable_receiver(ch);
ch->ch_flags &= ~(CH_RECEIVER_OFF);
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"Internal queue hit lowlevel mark (%d)! Turning on interrupts\n",
qleft);
}
}
/* SWFLOW */
else if (ch->ch_c_iflag & IXOFF && ch->ch_stops_sent) {
ch->ch_stops_sent = 0;
bd_ops->send_start_character(ch);
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"Sending start char!\n");
}
}
}
| linux-master | drivers/tty/serial/jsm/jsm_tty.c |
// SPDX-License-Identifier: GPL-2.0+
/************************************************************************
* Copyright 2003 Digi International (www.digi.com)
*
* Copyright (C) 2004 IBM Corporation. All rights reserved.
*
* Contact Information:
* Scott H Kilau <[email protected]>
* Wendy Xiong <[email protected]>
*
***********************************************************************/
#include <linux/delay.h> /* For udelay */
#include <linux/serial_reg.h> /* For the various UART offsets */
#include <linux/tty.h>
#include <linux/pci.h>
#include <asm/io.h>
#include "jsm.h" /* Driver main header file */
static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
/*
* This function allows calls to ensure that all outstanding
* PCI writes have been completed, by doing a PCI read against
* a non-destructive, read-only location on the Neo card.
*
* In this case, we are reading the DVID (Read-only Device Identification)
* value of the Neo card.
*/
static inline void neo_pci_posting_flush(struct jsm_board *bd)
{
readb(bd->re_map_membase + 0x8D);
}
static void neo_set_cts_flow_control(struct jsm_channel *ch)
{
u8 ier, efr;
ier = readb(&ch->ch_neo_uart->ier);
efr = readb(&ch->ch_neo_uart->efr);
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
/* Turn on auto CTS flow control */
ier |= (UART_17158_IER_CTSDSR);
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
/* Turn off auto Xon flow control */
efr &= ~(UART_17158_EFR_IXON);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
/* Turn on table D, with 8 char hi/low watermarks */
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
/* Feed the UART our trigger levels */
writeb(8, &ch->ch_neo_uart->tfifo);
ch->ch_t_tlevel = 8;
writeb(ier, &ch->ch_neo_uart->ier);
}
static void neo_set_rts_flow_control(struct jsm_channel *ch)
{
u8 ier, efr;
ier = readb(&ch->ch_neo_uart->ier);
efr = readb(&ch->ch_neo_uart->efr);
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
/* Turn on auto RTS flow control */
ier |= (UART_17158_IER_RTSDTR);
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
/* Turn off auto Xoff flow control */
ier &= ~(UART_17158_IER_XOFF);
efr &= ~(UART_17158_EFR_IXOFF);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 4;
writeb(56, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 56;
writeb(ier, &ch->ch_neo_uart->ier);
/*
* From the Neo UART spec sheet:
* The auto RTS/DTR function must be started by asserting
* RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
* it is enabled.
*/
ch->ch_mostat |= (UART_MCR_RTS);
}
static void neo_set_ixon_flow_control(struct jsm_channel *ch)
{
u8 ier, efr;
ier = readb(&ch->ch_neo_uart->ier);
efr = readb(&ch->ch_neo_uart->efr);
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
/* Turn off auto CTS flow control */
ier &= ~(UART_17158_IER_CTSDSR);
efr &= ~(UART_17158_EFR_CTSDSR);
/* Turn on auto Xon flow control */
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 4;
writeb(32, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 32;
/* Tell UART what start/stop chars it should be looking for */
writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
writeb(0, &ch->ch_neo_uart->xonchar2);
writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
writeb(0, &ch->ch_neo_uart->xoffchar2);
writeb(ier, &ch->ch_neo_uart->ier);
}
static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
{
u8 ier, efr;
ier = readb(&ch->ch_neo_uart->ier);
efr = readb(&ch->ch_neo_uart->efr);
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
/* Turn off auto RTS flow control */
ier &= ~(UART_17158_IER_RTSDTR);
efr &= ~(UART_17158_EFR_RTSDTR);
/* Turn on auto Xoff flow control */
ier |= (UART_17158_IER_XOFF);
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
/* Turn on table D, with 8 char hi/low watermarks */
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
writeb(8, &ch->ch_neo_uart->tfifo);
ch->ch_t_tlevel = 8;
/* Tell UART what start/stop chars it should be looking for */
writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
writeb(0, &ch->ch_neo_uart->xonchar2);
writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
writeb(0, &ch->ch_neo_uart->xoffchar2);
writeb(ier, &ch->ch_neo_uart->ier);
}
static void neo_set_no_input_flow_control(struct jsm_channel *ch)
{
u8 ier, efr;
ier = readb(&ch->ch_neo_uart->ier);
efr = readb(&ch->ch_neo_uart->efr);
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
/* Turn off auto RTS flow control */
ier &= ~(UART_17158_IER_RTSDTR);
efr &= ~(UART_17158_EFR_RTSDTR);
/* Turn off auto Xoff flow control */
ier &= ~(UART_17158_IER_XOFF);
if (ch->ch_c_iflag & IXON)
efr &= ~(UART_17158_EFR_IXOFF);
else
efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
/* Turn on table D, with 8 char hi/low watermarks */
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 0;
writeb(16, &ch->ch_neo_uart->tfifo);
ch->ch_t_tlevel = 16;
writeb(16, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 16;
writeb(ier, &ch->ch_neo_uart->ier);
}
static void neo_set_no_output_flow_control(struct jsm_channel *ch)
{
u8 ier, efr;
ier = readb(&ch->ch_neo_uart->ier);
efr = readb(&ch->ch_neo_uart->efr);
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
/* Turn off auto CTS flow control */
ier &= ~(UART_17158_IER_CTSDSR);
efr &= ~(UART_17158_EFR_CTSDSR);
/* Turn off auto Xon flow control */
if (ch->ch_c_iflag & IXOFF)
efr &= ~(UART_17158_EFR_IXON);
else
efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
/* Turn on table D, with 8 char hi/low watermarks */
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 0;
writeb(16, &ch->ch_neo_uart->tfifo);
ch->ch_t_tlevel = 16;
writeb(16, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 16;
writeb(ier, &ch->ch_neo_uart->ier);
}
static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
{
/* if hardware flow control is set, then skip this whole thing */
if (ch->ch_c_cflag & CRTSCTS)
return;
jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
/* Tell UART what start/stop chars it should be looking for */
writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
writeb(0, &ch->ch_neo_uart->xonchar2);
writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
writeb(0, &ch->ch_neo_uart->xoffchar2);
}
static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
{
int qleft = 0;
u8 linestatus = 0;
u8 error_mask = 0;
int n = 0;
int total = 0;
u16 head;
u16 tail;
/* cache head and tail of queue */
head = ch->ch_r_head & RQUEUEMASK;
tail = ch->ch_r_tail & RQUEUEMASK;
/* Get our cached LSR */
linestatus = ch->ch_cached_lsr;
ch->ch_cached_lsr = 0;
/* Store how much space we have left in the queue */
qleft = tail - head - 1;
if (qleft < 0)
qleft += RQUEUEMASK + 1;
/*
* If the UART is not in FIFO mode, force the FIFO copy to
* NOT be run, by setting total to 0.
*
* On the other hand, if the UART IS in FIFO mode, then ask
* the UART to give us an approximation of data it has RX'ed.
*/
if (!(ch->ch_flags & CH_FIFO_ENABLED))
total = 0;
else {
total = readb(&ch->ch_neo_uart->rfifo);
/*
* EXAR chip bug - RX FIFO COUNT - Fudge factor.
*
* This resolves a problem/bug with the Exar chip that sometimes
* returns a bogus value in the rfifo register.
* The count can be any where from 0-3 bytes "off".
* Bizarre, but true.
*/
total -= 3;
}
/*
* Finally, bound the copy to make sure we don't overflow
* our own queue...
* The byte by byte copy loop below this loop this will
* deal with the queue overflow possibility.
*/
total = min(total, qleft);
while (total > 0) {
/*
* Grab the linestatus register, we need to check
* to see if there are any errors in the FIFO.
*/
linestatus = readb(&ch->ch_neo_uart->lsr);
/*
* Break out if there is a FIFO error somewhere.
* This will allow us to go byte by byte down below,
* finding the exact location of the error.
*/
if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
break;
/* Make sure we don't go over the end of our queue */
n = min(((u32) total), (RQUEUESIZE - (u32) head));
/*
* Cut down n even further if needed, this is to fix
* a problem with memcpy_fromio() with the Neo on the
* IBM pSeries platform.
* 15 bytes max appears to be the magic number.
*/
n = min((u32) n, (u32) 12);
/*
* Since we are grabbing the linestatus register, which
* will reset some bits after our read, we need to ensure
* we don't miss our TX FIFO emptys.
*/
if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
linestatus = 0;
/* Copy data from uart to the queue */
memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
/*
* Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
* that all the data currently in the FIFO is free of
* breaks and parity/frame/orun errors.
*/
memset(ch->ch_equeue + head, 0, n);
/* Add to and flip head if needed */
head = (head + n) & RQUEUEMASK;
total -= n;
qleft -= n;
ch->ch_rxcount += n;
}
/*
* Create a mask to determine whether we should
* insert the character (if any) into our queue.
*/
if (ch->ch_c_iflag & IGNBRK)
error_mask |= UART_LSR_BI;
/*
* Now cleanup any leftover bytes still in the UART.
* Also deal with any possible queue overflow here as well.
*/
while (1) {
/*
* Its possible we have a linestatus from the loop above
* this, so we "OR" on any extra bits.
*/
linestatus |= readb(&ch->ch_neo_uart->lsr);
/*
* If the chip tells us there is no more data pending to
* be read, we can then leave.
* But before we do, cache the linestatus, just in case.
*/
if (!(linestatus & UART_LSR_DR)) {
ch->ch_cached_lsr = linestatus;
break;
}
/* No need to store this bit */
linestatus &= ~UART_LSR_DR;
/*
* Since we are grabbing the linestatus register, which
* will reset some bits after our read, we need to ensure
* we don't miss our TX FIFO emptys.
*/
if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
}
/*
* Discard character if we are ignoring the error mask.
*/
if (linestatus & error_mask) {
u8 discard;
linestatus = 0;
memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
continue;
}
/*
* If our queue is full, we have no choice but to drop some data.
* The assumption is that HWFLOW or SWFLOW should have stopped
* things way way before we got to this point.
*
* I decided that I wanted to ditch the oldest data first,
* I hope thats okay with everyone? Yes? Good.
*/
while (qleft < 1) {
jsm_dbg(READ, &ch->ch_bd->pci_dev,
"Queue full, dropping DATA:%x LSR:%x\n",
ch->ch_rqueue[tail], ch->ch_equeue[tail]);
ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
ch->ch_err_overrun++;
qleft++;
}
memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
ch->ch_equeue[head] = (u8) linestatus;
jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
ch->ch_rqueue[head], ch->ch_equeue[head]);
/* Ditch any remaining linestatus value. */
linestatus = 0;
/* Add to and flip head if needed */
head = (head + 1) & RQUEUEMASK;
qleft--;
ch->ch_rxcount++;
}
/*
* Write new final heads to channel structure.
*/
ch->ch_r_head = head & RQUEUEMASK;
ch->ch_e_head = head & EQUEUEMASK;
jsm_input(ch);
}
static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
{
u16 head;
u16 tail;
int n;
int s;
int qlen;
u32 len_written = 0;
struct circ_buf *circ;
if (!ch)
return;
circ = &ch->uart_port.state->xmit;
/* No data to write to the UART */
if (uart_circ_empty(circ))
return;
/* If port is "stopped", don't send any data to the UART */
if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
return;
/*
* If FIFOs are disabled. Send data directly to txrx register
*/
if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
ch->ch_cached_lsr |= lsrbits;
if (ch->ch_cached_lsr & UART_LSR_THRE) {
ch->ch_cached_lsr &= ~(UART_LSR_THRE);
writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
"Tx data: %x\n", circ->buf[circ->tail]);
circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
ch->ch_txcount++;
}
return;
}
/*
* We have to do it this way, because of the EXAR TXFIFO count bug.
*/
if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
return;
n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
/* cache head and tail of queue */
head = circ->head & (UART_XMIT_SIZE - 1);
tail = circ->tail & (UART_XMIT_SIZE - 1);
qlen = uart_circ_chars_pending(circ);
/* Find minimum of the FIFO space, versus queue length */
n = min(n, qlen);
while (n > 0) {
s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
s = min(s, n);
if (s <= 0)
break;
memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
/* Add and flip queue if needed */
tail = (tail + s) & (UART_XMIT_SIZE - 1);
n -= s;
ch->ch_txcount += s;
len_written += s;
}
/* Update the final tail */
circ->tail = tail & (UART_XMIT_SIZE - 1);
if (len_written >= ch->ch_t_tlevel)
ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
if (uart_circ_empty(circ))
uart_write_wakeup(&ch->uart_port);
}
static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
{
u8 msignals = signals;
jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
"neo_parse_modem: port: %d msignals: %x\n",
ch->ch_portnum, msignals);
/* Scrub off lower bits. They signify delta's, which I don't care about */
/* Keep DDCD and DDSR though */
msignals &= 0xf8;
if (msignals & UART_MSR_DDCD)
uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
if (msignals & UART_MSR_DDSR)
uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
if (msignals & UART_MSR_DCD)
ch->ch_mistat |= UART_MSR_DCD;
else
ch->ch_mistat &= ~UART_MSR_DCD;
if (msignals & UART_MSR_DSR)
ch->ch_mistat |= UART_MSR_DSR;
else
ch->ch_mistat &= ~UART_MSR_DSR;
if (msignals & UART_MSR_RI)
ch->ch_mistat |= UART_MSR_RI;
else
ch->ch_mistat &= ~UART_MSR_RI;
if (msignals & UART_MSR_CTS)
ch->ch_mistat |= UART_MSR_CTS;
else
ch->ch_mistat &= ~UART_MSR_CTS;
jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
"Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
ch->ch_portnum,
!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
}
/* Make the UART raise any of the output signals we want up */
static void neo_assert_modem_signals(struct jsm_channel *ch)
{
if (!ch)
return;
writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
/*
* Flush the WRITE FIFO on the Neo.
*
* NOTE: Channel lock MUST be held before calling this function!
*/
static void neo_flush_uart_write(struct jsm_channel *ch)
{
u8 tmp = 0;
int i = 0;
if (!ch)
return;
writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
for (i = 0; i < 10; i++) {
/* Check to see if the UART feels it completely flushed the FIFO. */
tmp = readb(&ch->ch_neo_uart->isr_fcr);
if (tmp & UART_FCR_CLEAR_XMIT) {
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
"Still flushing TX UART... i: %d\n", i);
udelay(10);
}
else
break;
}
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
}
/*
* Flush the READ FIFO on the Neo.
*
* NOTE: Channel lock MUST be held before calling this function!
*/
static void neo_flush_uart_read(struct jsm_channel *ch)
{
u8 tmp = 0;
int i = 0;
if (!ch)
return;
writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
for (i = 0; i < 10; i++) {
/* Check to see if the UART feels it completely flushed the FIFO. */
tmp = readb(&ch->ch_neo_uart->isr_fcr);
if (tmp & 2) {
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
"Still flushing RX UART... i: %d\n", i);
udelay(10);
}
else
break;
}
}
/*
* No locks are assumed to be held when calling this function.
*/
static void neo_clear_break(struct jsm_channel *ch)
{
unsigned long lock_flags;
spin_lock_irqsave(&ch->ch_lock, lock_flags);
/* Turn break off, and unset some variables */
if (ch->ch_flags & CH_BREAK_SENDING) {
u8 temp = readb(&ch->ch_neo_uart->lcr);
writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
ch->ch_flags &= ~(CH_BREAK_SENDING);
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
"clear break Finishing UART_LCR_SBC! finished: %lx\n",
jiffies);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
/*
* Parse the ISR register.
*/
static void neo_parse_isr(struct jsm_board *brd, u32 port)
{
struct jsm_channel *ch;
u8 isr;
u8 cause;
unsigned long lock_flags;
if (!brd)
return;
if (port >= brd->maxports)
return;
ch = brd->channels[port];
if (!ch)
return;
/* Here we try to figure out what caused the interrupt to happen */
while (1) {
isr = readb(&ch->ch_neo_uart->isr_fcr);
/* Bail if no pending interrupt */
if (isr & UART_IIR_NO_INT)
break;
/*
* Yank off the upper 2 bits, which just show that the FIFO's are enabled.
*/
isr &= ~(UART_17158_IIR_FIFO_ENABLED);
jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
__FILE__, __LINE__, isr);
if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
/* Read data from uart -> queue */
neo_copy_data_from_uart_to_queue(ch);
/* Call our tty layer to enforce queue flow control if needed. */
spin_lock_irqsave(&ch->ch_lock, lock_flags);
jsm_check_queue_flow_control(ch);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
if (isr & UART_IIR_THRI) {
/* Transfer data (if any) from Write Queue -> UART. */
spin_lock_irqsave(&ch->ch_lock, lock_flags);
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
neo_copy_data_from_queue_to_uart(ch);
}
if (isr & UART_17158_IIR_XONXOFF) {
cause = readb(&ch->ch_neo_uart->xoffchar1);
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"Port %d. Got ISR_XONXOFF: cause:%x\n",
port, cause);
/*
* Since the UART detected either an XON or
* XOFF match, we need to figure out which
* one it was, so we can suspend or resume data flow.
*/
spin_lock_irqsave(&ch->ch_lock, lock_flags);
if (cause == UART_17158_XON_DETECT) {
/* Is output stopped right now, if so, resume it */
if (brd->channels[port]->ch_flags & CH_STOP) {
ch->ch_flags &= ~(CH_STOP);
}
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"Port %d. XON detected in incoming data\n",
port);
}
else if (cause == UART_17158_XOFF_DETECT) {
if (!(brd->channels[port]->ch_flags & CH_STOP)) {
ch->ch_flags |= CH_STOP;
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"Setting CH_STOP\n");
}
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"Port: %d. XOFF detected in incoming data\n",
port);
}
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
/*
* If we get here, this means the hardware is doing auto flow control.
* Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
*/
cause = readb(&ch->ch_neo_uart->mcr);
/* Which pin is doing auto flow? RTS or DTR? */
spin_lock_irqsave(&ch->ch_lock, lock_flags);
if ((cause & 0x4) == 0) {
if (cause & UART_MCR_RTS)
ch->ch_mostat |= UART_MCR_RTS;
else
ch->ch_mostat &= ~(UART_MCR_RTS);
} else {
if (cause & UART_MCR_DTR)
ch->ch_mostat |= UART_MCR_DTR;
else
ch->ch_mostat &= ~(UART_MCR_DTR);
}
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
/* Parse any modem signal changes */
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"MOD_STAT: sending to parse_modem_sigs\n");
spin_lock_irqsave(&ch->uart_port.lock, lock_flags);
neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags);
}
}
static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
{
struct jsm_channel *ch;
int linestatus;
unsigned long lock_flags;
if (!brd)
return;
if (port >= brd->maxports)
return;
ch = brd->channels[port];
if (!ch)
return;
linestatus = readb(&ch->ch_neo_uart->lsr);
jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
__FILE__, __LINE__, port, linestatus);
ch->ch_cached_lsr |= linestatus;
if (ch->ch_cached_lsr & UART_LSR_DR) {
/* Read data from uart -> queue */
neo_copy_data_from_uart_to_queue(ch);
spin_lock_irqsave(&ch->ch_lock, lock_flags);
jsm_check_queue_flow_control(ch);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
/*
* This is a special flag. It indicates that at least 1
* RX error (parity, framing, or break) has happened.
* Mark this in our struct, which will tell me that I have
*to do the special RX+LSR read for this FIFO load.
*/
if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"%s:%d Port: %d Got an RX error, need to parse LSR\n",
__FILE__, __LINE__, port);
/*
* The next 3 tests should *NOT* happen, as the above test
* should encapsulate all 3... At least, thats what Exar says.
*/
if (linestatus & UART_LSR_PE) {
ch->ch_err_parity++;
jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
__FILE__, __LINE__, port);
}
if (linestatus & UART_LSR_FE) {
ch->ch_err_frame++;
jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
__FILE__, __LINE__, port);
}
if (linestatus & UART_LSR_BI) {
ch->ch_err_break++;
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"%s:%d Port: %d. BRK INTR!\n",
__FILE__, __LINE__, port);
}
if (linestatus & UART_LSR_OE) {
/*
* Rx Oruns. Exar says that an orun will NOT corrupt
* the FIFO. It will just replace the holding register
* with this new data byte. So basically just ignore this.
* Probably we should eventually have an orun stat in our driver...
*/
ch->ch_err_overrun++;
jsm_dbg(INTR, &ch->ch_bd->pci_dev,
"%s:%d Port: %d. Rx Overrun!\n",
__FILE__, __LINE__, port);
}
if (linestatus & UART_LSR_THRE) {
spin_lock_irqsave(&ch->ch_lock, lock_flags);
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
/* Transfer data (if any) from Write Queue -> UART. */
neo_copy_data_from_queue_to_uart(ch);
}
else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
spin_lock_irqsave(&ch->ch_lock, lock_flags);
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
/* Transfer data (if any) from Write Queue -> UART. */
neo_copy_data_from_queue_to_uart(ch);
}
}
/*
* neo_param()
* Send any/all changes to the line to the UART.
*/
static void neo_param(struct jsm_channel *ch)
{
u8 lcr = 0;
u8 uart_lcr, ier;
u32 baud;
int quot;
struct jsm_board *bd;
bd = ch->ch_bd;
if (!bd)
return;
/*
* If baud rate is zero, flush queues, and set mval to drop DTR.
*/
if ((ch->ch_c_cflag & CBAUD) == B0) {
ch->ch_r_head = ch->ch_r_tail = 0;
ch->ch_e_head = ch->ch_e_tail = 0;
neo_flush_uart_write(ch);
neo_flush_uart_read(ch);
ch->ch_flags |= (CH_BAUD0);
ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
neo_assert_modem_signals(ch);
return;
} else {
int i;
unsigned int cflag;
static struct {
unsigned int rate;
unsigned int cflag;
} baud_rates[] = {
{ 921600, B921600 },
{ 460800, B460800 },
{ 230400, B230400 },
{ 115200, B115200 },
{ 57600, B57600 },
{ 38400, B38400 },
{ 19200, B19200 },
{ 9600, B9600 },
{ 4800, B4800 },
{ 2400, B2400 },
{ 1200, B1200 },
{ 600, B600 },
{ 300, B300 },
{ 200, B200 },
{ 150, B150 },
{ 134, B134 },
{ 110, B110 },
{ 75, B75 },
{ 50, B50 },
};
cflag = C_BAUD(ch->uart_port.state->port.tty);
baud = 9600;
for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
if (baud_rates[i].cflag == cflag) {
baud = baud_rates[i].rate;
break;
}
}
if (ch->ch_flags & CH_BAUD0)
ch->ch_flags &= ~(CH_BAUD0);
}
if (ch->ch_c_cflag & PARENB)
lcr |= UART_LCR_PARITY;
if (!(ch->ch_c_cflag & PARODD))
lcr |= UART_LCR_EPAR;
if (ch->ch_c_cflag & CMSPAR)
lcr |= UART_LCR_SPAR;
if (ch->ch_c_cflag & CSTOPB)
lcr |= UART_LCR_STOP;
lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
ier = readb(&ch->ch_neo_uart->ier);
uart_lcr = readb(&ch->ch_neo_uart->lcr);
quot = ch->ch_bd->bd_dividend / baud;
if (quot != 0) {
writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
writeb((quot >> 8), &ch->ch_neo_uart->ier);
writeb(lcr, &ch->ch_neo_uart->lcr);
}
if (uart_lcr != lcr)
writeb(lcr, &ch->ch_neo_uart->lcr);
if (ch->ch_c_cflag & CREAD)
ier |= (UART_IER_RDI | UART_IER_RLSI);
ier |= (UART_IER_THRI | UART_IER_MSI);
writeb(ier, &ch->ch_neo_uart->ier);
/* Set new start/stop chars */
neo_set_new_start_stop_chars(ch);
if (ch->ch_c_cflag & CRTSCTS)
neo_set_cts_flow_control(ch);
else if (ch->ch_c_iflag & IXON) {
/* If start/stop is set to disable, then we should disable flow control */
if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
neo_set_no_output_flow_control(ch);
else
neo_set_ixon_flow_control(ch);
}
else
neo_set_no_output_flow_control(ch);
if (ch->ch_c_cflag & CRTSCTS)
neo_set_rts_flow_control(ch);
else if (ch->ch_c_iflag & IXOFF) {
/* If start/stop is set to disable, then we should disable flow control */
if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
neo_set_no_input_flow_control(ch);
else
neo_set_ixoff_flow_control(ch);
}
else
neo_set_no_input_flow_control(ch);
/*
* Adjust the RX FIFO Trigger level if baud is less than 9600.
* Not exactly elegant, but this is needed because of the Exar chip's
* delay on firing off the RX FIFO interrupt on slower baud rates.
*/
if (baud < 9600) {
writeb(1, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 1;
}
neo_assert_modem_signals(ch);
/* Get current status of the modem signals now */
neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
return;
}
/*
* jsm_neo_intr()
*
* Neo specific interrupt handler.
*/
static irqreturn_t neo_intr(int irq, void *voidbrd)
{
struct jsm_board *brd = voidbrd;
struct jsm_channel *ch;
int port = 0;
int type = 0;
int current_port;
u32 tmp;
u32 uart_poll;
unsigned long lock_flags;
unsigned long lock_flags2;
int outofloop_count = 0;
/* Lock out the slow poller from running on this board. */
spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
/*
* Read in "extended" IRQ information from the 32bit Neo register.
* Bits 0-7: What port triggered the interrupt.
* Bits 8-31: Each 3bits indicate what type of interrupt occurred.
*/
uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
__FILE__, __LINE__, uart_poll);
if (!uart_poll) {
jsm_dbg(INTR, &brd->pci_dev,
"Kernel interrupted to me, but no pending interrupts...\n");
spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
return IRQ_NONE;
}
/* At this point, we have at least SOMETHING to service, dig further... */
current_port = 0;
/* Loop on each port */
while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
tmp = uart_poll;
outofloop_count++;
/* Check current port to see if it has interrupt pending */
if ((tmp & jsm_offset_table[current_port]) != 0) {
port = current_port;
type = tmp >> (8 + (port * 3));
type &= 0x7;
} else {
current_port++;
continue;
}
jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
__FILE__, __LINE__, port, type);
/* Remove this port + type from uart_poll */
uart_poll &= ~(jsm_offset_table[port]);
if (!type) {
/* If no type, just ignore it, and move onto next port */
jsm_dbg(INTR, &brd->pci_dev,
"Interrupt with no type! port: %d\n", port);
continue;
}
/* Switch on type of interrupt we have */
switch (type) {
case UART_17158_RXRDY_TIMEOUT:
/*
* RXRDY Time-out is cleared by reading data in the
* RX FIFO until it falls below the trigger level.
*/
/* Verify the port is in range. */
if (port >= brd->nasync)
continue;
ch = brd->channels[port];
if (!ch)
continue;
neo_copy_data_from_uart_to_queue(ch);
/* Call our tty layer to enforce queue flow control if needed. */
spin_lock_irqsave(&ch->ch_lock, lock_flags2);
jsm_check_queue_flow_control(ch);
spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
continue;
case UART_17158_RX_LINE_STATUS:
/*
* RXRDY and RX LINE Status (logic OR of LSR[4:1])
*/
neo_parse_lsr(brd, port);
continue;
case UART_17158_TXRDY:
/*
* TXRDY interrupt clears after reading ISR register for the UART channel.
*/
/*
* Yes, this is odd...
* Why would I check EVERY possibility of type of
* interrupt, when we know its TXRDY???
* Becuz for some reason, even tho we got triggered for TXRDY,
* it seems to be occasionally wrong. Instead of TX, which
* it should be, I was getting things like RXDY too. Weird.
*/
neo_parse_isr(brd, port);
continue;
case UART_17158_MSR:
/*
* MSR or flow control was seen.
*/
neo_parse_isr(brd, port);
continue;
default:
/*
* The UART triggered us with a bogus interrupt type.
* It appears the Exar chip, when REALLY bogged down, will throw
* these once and awhile.
* Its harmless, just ignore it and move on.
*/
jsm_dbg(INTR, &brd->pci_dev,
"%s:%d Unknown Interrupt type: %x\n",
__FILE__, __LINE__, type);
continue;
}
}
spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
jsm_dbg(INTR, &brd->pci_dev, "finish\n");
return IRQ_HANDLED;
}
/*
* Neo specific way of turning off the receiver.
* Used as a way to enforce queue flow control when in
* hardware flow control mode.
*/
static void neo_disable_receiver(struct jsm_channel *ch)
{
u8 tmp = readb(&ch->ch_neo_uart->ier);
tmp &= ~(UART_IER_RDI);
writeb(tmp, &ch->ch_neo_uart->ier);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
/*
* Neo specific way of turning on the receiver.
* Used as a way to un-enforce queue flow control when in
* hardware flow control mode.
*/
static void neo_enable_receiver(struct jsm_channel *ch)
{
u8 tmp = readb(&ch->ch_neo_uart->ier);
tmp |= (UART_IER_RDI);
writeb(tmp, &ch->ch_neo_uart->ier);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
static void neo_send_start_character(struct jsm_channel *ch)
{
if (!ch)
return;
if (ch->ch_startc != __DISABLED_CHAR) {
ch->ch_xon_sends++;
writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
}
static void neo_send_stop_character(struct jsm_channel *ch)
{
if (!ch)
return;
if (ch->ch_stopc != __DISABLED_CHAR) {
ch->ch_xoff_sends++;
writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
}
/*
* neo_uart_init
*/
static void neo_uart_init(struct jsm_channel *ch)
{
writeb(0, &ch->ch_neo_uart->ier);
writeb(0, &ch->ch_neo_uart->efr);
writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
/* Clear out UART and FIFO */
readb(&ch->ch_neo_uart->txrx);
writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
readb(&ch->ch_neo_uart->lsr);
readb(&ch->ch_neo_uart->msr);
ch->ch_flags |= CH_FIFO_ENABLED;
/* Assert any signals we want up */
writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
}
/*
* Make the UART completely turn off.
*/
static void neo_uart_off(struct jsm_channel *ch)
{
/* Turn off UART enhanced bits */
writeb(0, &ch->ch_neo_uart->efr);
/* Stop all interrupts from occurring. */
writeb(0, &ch->ch_neo_uart->ier);
}
static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
{
u8 left = 0;
u8 lsr = readb(&ch->ch_neo_uart->lsr);
/* We must cache the LSR as some of the bits get reset once read... */
ch->ch_cached_lsr |= lsr;
/* Determine whether the Transmitter is empty or not */
if (!(lsr & UART_LSR_TEMT))
left = 1;
else {
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
left = 0;
}
return left;
}
/* Channel lock MUST be held by the calling function! */
static void neo_send_break(struct jsm_channel *ch)
{
/*
* Set the time we should stop sending the break.
* If we are already sending a break, toss away the existing
* time to stop, and use this new value instead.
*/
/* Tell the UART to start sending the break */
if (!(ch->ch_flags & CH_BREAK_SENDING)) {
u8 temp = readb(&ch->ch_neo_uart->lcr);
writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
ch->ch_flags |= (CH_BREAK_SENDING);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
}
/*
* neo_send_immediate_char.
*
* Sends a specific character as soon as possible to the UART,
* jumping over any bytes that might be in the write queue.
*
* The channel lock MUST be held by the calling function.
*/
static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
{
if (!ch)
return;
writeb(c, &ch->ch_neo_uart->txrx);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
struct board_ops jsm_neo_ops = {
.intr = neo_intr,
.uart_init = neo_uart_init,
.uart_off = neo_uart_off,
.param = neo_param,
.assert_modem_signals = neo_assert_modem_signals,
.flush_uart_write = neo_flush_uart_write,
.flush_uart_read = neo_flush_uart_read,
.disable_receiver = neo_disable_receiver,
.enable_receiver = neo_enable_receiver,
.send_break = neo_send_break,
.clear_break = neo_clear_break,
.send_start_character = neo_send_start_character,
.send_stop_character = neo_send_stop_character,
.copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
.get_uart_bytes_left = neo_get_uart_bytes_left,
.send_immediate_char = neo_send_immediate_char
};
| linux-master | drivers/tty/serial/jsm/jsm_neo.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Fieldbus Device Driver Core
*
*/
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/idr.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/poll.h>
/* move to <linux/fieldbus_dev.h> when taking this out of staging */
#include "fieldbus_dev.h"
/* Maximum number of fieldbus devices */
#define MAX_FIELDBUSES 32
/* the dev_t structure to store the dynamically allocated fieldbus devices */
static dev_t fieldbus_devt;
static DEFINE_IDA(fieldbus_ida);
static DEFINE_MUTEX(fieldbus_mtx);
static ssize_t online_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", !!fb->online);
}
static DEVICE_ATTR_RO(online);
static ssize_t enabled_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
if (!fb->enable_get)
return -EINVAL;
return sysfs_emit(buf, "%d\n", !!fb->enable_get(fb));
}
static ssize_t enabled_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t n)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
bool value;
int ret;
if (!fb->simple_enable_set)
return -ENOTSUPP;
ret = kstrtobool(buf, &value);
if (ret)
return ret;
ret = fb->simple_enable_set(fb, value);
if (ret < 0)
return ret;
return n;
}
static DEVICE_ATTR_RW(enabled);
static ssize_t card_name_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
/* card_name was provided by child driver. */
return sysfs_emit(buf, "%s\n", fb->card_name);
}
static DEVICE_ATTR_RO(card_name);
static ssize_t read_area_size_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
return sysfs_emit(buf, "%zu\n", fb->read_area_sz);
}
static DEVICE_ATTR_RO(read_area_size);
static ssize_t write_area_size_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
return sysfs_emit(buf, "%zu\n", fb->write_area_sz);
}
static DEVICE_ATTR_RO(write_area_size);
static ssize_t fieldbus_id_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
return fb->fieldbus_id_get(fb, buf, PAGE_SIZE);
}
static DEVICE_ATTR_RO(fieldbus_id);
static ssize_t fieldbus_type_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fieldbus_dev *fb = dev_get_drvdata(dev);
const char *t;
switch (fb->fieldbus_type) {
case FIELDBUS_DEV_TYPE_PROFINET:
t = "profinet";
break;
default:
t = "unknown";
break;
}
return sysfs_emit(buf, "%s\n", t);
}
static DEVICE_ATTR_RO(fieldbus_type);
static struct attribute *fieldbus_attrs[] = {
&dev_attr_enabled.attr,
&dev_attr_card_name.attr,
&dev_attr_fieldbus_id.attr,
&dev_attr_read_area_size.attr,
&dev_attr_write_area_size.attr,
&dev_attr_online.attr,
&dev_attr_fieldbus_type.attr,
NULL,
};
static umode_t fieldbus_is_visible(struct kobject *kobj, struct attribute *attr,
int n)
{
struct device *dev = kobj_to_dev(kobj);
struct fieldbus_dev *fb = dev_get_drvdata(dev);
umode_t mode = attr->mode;
if (attr == &dev_attr_enabled.attr) {
mode = 0;
if (fb->enable_get)
mode |= 0444;
if (fb->simple_enable_set)
mode |= 0200;
}
return mode;
}
static const struct attribute_group fieldbus_group = {
.attrs = fieldbus_attrs,
.is_visible = fieldbus_is_visible,
};
__ATTRIBUTE_GROUPS(fieldbus);
static struct class fieldbus_class = {
.name = "fieldbus_dev",
.dev_groups = fieldbus_groups,
};
struct fb_open_file {
struct fieldbus_dev *fbdev;
int dc_event;
};
static int fieldbus_open(struct inode *inode, struct file *filp)
{
struct fb_open_file *of;
struct fieldbus_dev *fbdev = container_of(inode->i_cdev,
struct fieldbus_dev,
cdev);
of = kzalloc(sizeof(*of), GFP_KERNEL);
if (!of)
return -ENOMEM;
of->fbdev = fbdev;
filp->private_data = of;
return 0;
}
static int fieldbus_release(struct inode *node, struct file *filp)
{
struct fb_open_file *of = filp->private_data;
kfree(of);
return 0;
}
static ssize_t fieldbus_read(struct file *filp, char __user *buf, size_t size,
loff_t *offset)
{
struct fb_open_file *of = filp->private_data;
struct fieldbus_dev *fbdev = of->fbdev;
of->dc_event = fbdev->dc_event;
return fbdev->read_area(fbdev, buf, size, offset);
}
static ssize_t fieldbus_write(struct file *filp, const char __user *buf,
size_t size, loff_t *offset)
{
struct fb_open_file *of = filp->private_data;
struct fieldbus_dev *fbdev = of->fbdev;
return fbdev->write_area(fbdev, buf, size, offset);
}
static __poll_t fieldbus_poll(struct file *filp, poll_table *wait)
{
struct fb_open_file *of = filp->private_data;
struct fieldbus_dev *fbdev = of->fbdev;
__poll_t mask = EPOLLIN | EPOLLRDNORM | EPOLLOUT | EPOLLWRNORM;
poll_wait(filp, &fbdev->dc_wq, wait);
/* data changed ? */
if (fbdev->dc_event != of->dc_event)
mask |= EPOLLPRI | EPOLLERR;
return mask;
}
static const struct file_operations fieldbus_fops = {
.open = fieldbus_open,
.release = fieldbus_release,
.read = fieldbus_read,
.write = fieldbus_write,
.poll = fieldbus_poll,
.llseek = generic_file_llseek,
.owner = THIS_MODULE,
};
void fieldbus_dev_area_updated(struct fieldbus_dev *fb)
{
fb->dc_event++;
wake_up_all(&fb->dc_wq);
}
EXPORT_SYMBOL_GPL(fieldbus_dev_area_updated);
void fieldbus_dev_online_changed(struct fieldbus_dev *fb, bool online)
{
fb->online = online;
kobject_uevent(&fb->dev->kobj, KOBJ_CHANGE);
}
EXPORT_SYMBOL_GPL(fieldbus_dev_online_changed);
static void __fieldbus_dev_unregister(struct fieldbus_dev *fb)
{
if (!fb)
return;
device_destroy(&fieldbus_class, fb->cdev.dev);
cdev_del(&fb->cdev);
ida_simple_remove(&fieldbus_ida, fb->id);
}
void fieldbus_dev_unregister(struct fieldbus_dev *fb)
{
mutex_lock(&fieldbus_mtx);
__fieldbus_dev_unregister(fb);
mutex_unlock(&fieldbus_mtx);
}
EXPORT_SYMBOL_GPL(fieldbus_dev_unregister);
static int __fieldbus_dev_register(struct fieldbus_dev *fb)
{
dev_t devno;
int err;
if (!fb)
return -EINVAL;
if (!fb->read_area || !fb->write_area || !fb->fieldbus_id_get)
return -EINVAL;
fb->id = ida_simple_get(&fieldbus_ida, 0, MAX_FIELDBUSES, GFP_KERNEL);
if (fb->id < 0)
return fb->id;
devno = MKDEV(MAJOR(fieldbus_devt), fb->id);
init_waitqueue_head(&fb->dc_wq);
cdev_init(&fb->cdev, &fieldbus_fops);
err = cdev_add(&fb->cdev, devno, 1);
if (err) {
pr_err("fieldbus_dev%d unable to add device %d:%d\n",
fb->id, MAJOR(fieldbus_devt), fb->id);
goto err_cdev;
}
fb->dev = device_create(&fieldbus_class, fb->parent, devno, fb,
"fieldbus_dev%d", fb->id);
if (IS_ERR(fb->dev)) {
err = PTR_ERR(fb->dev);
goto err_dev_create;
}
return 0;
err_dev_create:
cdev_del(&fb->cdev);
err_cdev:
ida_simple_remove(&fieldbus_ida, fb->id);
return err;
}
int fieldbus_dev_register(struct fieldbus_dev *fb)
{
int err;
mutex_lock(&fieldbus_mtx);
err = __fieldbus_dev_register(fb);
mutex_unlock(&fieldbus_mtx);
return err;
}
EXPORT_SYMBOL_GPL(fieldbus_dev_register);
static int __init fieldbus_init(void)
{
int err;
err = class_register(&fieldbus_class);
if (err < 0) {
pr_err("fieldbus_dev: could not register class\n");
return err;
}
err = alloc_chrdev_region(&fieldbus_devt, 0,
MAX_FIELDBUSES, "fieldbus_dev");
if (err < 0) {
pr_err("fieldbus_dev: unable to allocate char dev region\n");
goto err_alloc;
}
return 0;
err_alloc:
class_unregister(&fieldbus_class);
return err;
}
static void __exit fieldbus_exit(void)
{
unregister_chrdev_region(fieldbus_devt, MAX_FIELDBUSES);
class_unregister(&fieldbus_class);
ida_destroy(&fieldbus_ida);
}
subsys_initcall(fieldbus_init);
module_exit(fieldbus_exit);
MODULE_AUTHOR("Sven Van Asbroeck <[email protected]>");
MODULE_AUTHOR("Jonathan Stiles <[email protected]>");
MODULE_DESCRIPTION("Fieldbus Device Driver Core");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/staging/fieldbus/dev_core.c |
// SPDX-License-Identifier: GPL-2.0
/*
* HMS Profinet Client Driver
*
* Copyright (C) 2018 Arcx Inc
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
/* move to <linux/fieldbus_dev.h> when taking this out of staging */
#include "../fieldbus_dev.h"
/* move to <linux/anybuss-client.h> when taking this out of staging */
#include "anybuss-client.h"
#define PROFI_DPRAM_SIZE 512
/*
* ---------------------------------------------------------------
* Anybus Profinet mailbox messages - definitions
* ---------------------------------------------------------------
* note that we're depending on the layout of these structures being
* exactly as advertised.
*/
struct msg_mac_addr {
u8 addr[6];
};
struct profi_priv {
struct fieldbus_dev fbdev;
struct anybuss_client *client;
struct mutex enable_lock; /* serializes card enable */
bool power_on;
};
static ssize_t
profi_read_area(struct fieldbus_dev *fbdev, char __user *buf, size_t size,
loff_t *offset)
{
struct profi_priv *priv = container_of(fbdev, struct profi_priv, fbdev);
return anybuss_read_output(priv->client, buf, size, offset);
}
static ssize_t
profi_write_area(struct fieldbus_dev *fbdev, const char __user *buf,
size_t size, loff_t *offset)
{
struct profi_priv *priv = container_of(fbdev, struct profi_priv, fbdev);
return anybuss_write_input(priv->client, buf, size, offset);
}
static int profi_id_get(struct fieldbus_dev *fbdev, char *buf,
size_t max_size)
{
struct profi_priv *priv = container_of(fbdev, struct profi_priv, fbdev);
struct msg_mac_addr response;
int ret;
ret = anybuss_recv_msg(priv->client, 0x0010, &response,
sizeof(response));
if (ret < 0)
return ret;
return snprintf(buf, max_size, "%pM\n", response.addr);
}
static bool profi_enable_get(struct fieldbus_dev *fbdev)
{
struct profi_priv *priv = container_of(fbdev, struct profi_priv, fbdev);
bool power_on;
mutex_lock(&priv->enable_lock);
power_on = priv->power_on;
mutex_unlock(&priv->enable_lock);
return power_on;
}
static int __profi_enable(struct profi_priv *priv)
{
int ret;
struct anybuss_client *client = priv->client;
/* Initialization Sequence, Generic Anybus Mode */
const struct anybuss_memcfg mem_cfg = {
.input_io = 220,
.input_dpram = PROFI_DPRAM_SIZE,
.input_total = PROFI_DPRAM_SIZE,
.output_io = 220,
.output_dpram = PROFI_DPRAM_SIZE,
.output_total = PROFI_DPRAM_SIZE,
.offl_mode = FIELDBUS_DEV_OFFL_MODE_CLEAR,
};
/*
* switch anybus off then on, this ensures we can do a complete
* configuration cycle in case anybus was already on.
*/
anybuss_set_power(client, false);
ret = anybuss_set_power(client, true);
if (ret)
goto err;
ret = anybuss_start_init(client, &mem_cfg);
if (ret)
goto err;
ret = anybuss_finish_init(client);
if (ret)
goto err;
priv->power_on = true;
return 0;
err:
anybuss_set_power(client, false);
priv->power_on = false;
return ret;
}
static int __profi_disable(struct profi_priv *priv)
{
struct anybuss_client *client = priv->client;
anybuss_set_power(client, false);
priv->power_on = false;
return 0;
}
static int profi_simple_enable(struct fieldbus_dev *fbdev, bool enable)
{
int ret;
struct profi_priv *priv = container_of(fbdev, struct profi_priv, fbdev);
mutex_lock(&priv->enable_lock);
if (enable)
ret = __profi_enable(priv);
else
ret = __profi_disable(priv);
mutex_unlock(&priv->enable_lock);
return ret;
}
static void profi_on_area_updated(struct anybuss_client *client)
{
struct profi_priv *priv = anybuss_get_drvdata(client);
fieldbus_dev_area_updated(&priv->fbdev);
}
static void profi_on_online_changed(struct anybuss_client *client, bool online)
{
struct profi_priv *priv = anybuss_get_drvdata(client);
fieldbus_dev_online_changed(&priv->fbdev, online);
}
static int profinet_probe(struct anybuss_client *client)
{
struct profi_priv *priv;
struct device *dev = &client->dev;
int err;
client->on_area_updated = profi_on_area_updated;
client->on_online_changed = profi_on_online_changed;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
mutex_init(&priv->enable_lock);
priv->client = client;
priv->fbdev.read_area_sz = PROFI_DPRAM_SIZE;
priv->fbdev.write_area_sz = PROFI_DPRAM_SIZE;
priv->fbdev.card_name = "HMS Profinet IRT (Anybus-S)";
priv->fbdev.fieldbus_type = FIELDBUS_DEV_TYPE_PROFINET;
priv->fbdev.read_area = profi_read_area;
priv->fbdev.write_area = profi_write_area;
priv->fbdev.fieldbus_id_get = profi_id_get;
priv->fbdev.enable_get = profi_enable_get;
priv->fbdev.simple_enable_set = profi_simple_enable;
priv->fbdev.parent = dev;
err = fieldbus_dev_register(&priv->fbdev);
if (err < 0)
return err;
dev_info(dev, "card detected, registered as %s",
dev_name(priv->fbdev.dev));
anybuss_set_drvdata(client, priv);
return 0;
}
static void profinet_remove(struct anybuss_client *client)
{
struct profi_priv *priv = anybuss_get_drvdata(client);
fieldbus_dev_unregister(&priv->fbdev);
}
static struct anybuss_client_driver profinet_driver = {
.probe = profinet_probe,
.remove = profinet_remove,
.driver = {
.name = "hms-profinet",
.owner = THIS_MODULE,
},
.anybus_id = 0x0089,
};
static int __init profinet_init(void)
{
return anybuss_client_driver_register(&profinet_driver);
}
module_init(profinet_init);
static void __exit profinet_exit(void)
{
return anybuss_client_driver_unregister(&profinet_driver);
}
module_exit(profinet_exit);
MODULE_AUTHOR("Sven Van Asbroeck <[email protected]>");
MODULE_DESCRIPTION("HMS Profinet IRT Driver (Anybus-S)");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/staging/fieldbus/anybuss/hms-profinet.c |
// SPDX-License-Identifier: GPL-2.0
/*
* HMS Anybus-S Host Driver
*
* Copyright (C) 2018 Arcx Inc
*/
/*
* Architecture Overview
* =====================
* This driver (running on the CPU/SoC) and the Anybus-S card communicate
* by reading and writing data to/from the Anybus-S Dual-Port RAM (dpram).
* This is memory connected to both the SoC and Anybus-S card, which both sides
* can access freely and concurrently.
*
* Synchronization happens by means of two registers located in the dpram:
* IND_AB: written exclusively by the Anybus card; and
* IND_AP: written exclusively by this driver.
*
* Communication happens using one of the following mechanisms:
* 1. reserve, read/write, release dpram memory areas:
* using an IND_AB/IND_AP protocol, the driver is able to reserve certain
* memory areas. no dpram memory can be read or written except if reserved.
* (with a few limited exceptions)
* 2. send and receive data structures via a shared mailbox:
* using an IND_AB/IND_AP protocol, the driver and Anybus card are able to
* exchange commands and responses using a shared mailbox.
* 3. receive software interrupts:
* using an IND_AB/IND_AP protocol, the Anybus card is able to notify the
* driver of certain events such as: bus online/offline, data available.
* note that software interrupt event bits are located in a memory area
* which must be reserved before it can be accessed.
*
* The manual[1] is silent on whether these mechanisms can happen concurrently,
* or how they should be synchronized. However, section 13 (Driver Example)
* provides the following suggestion for developing a driver:
* a) an interrupt handler which updates global variables;
* b) a continuously-running task handling area requests (1 above)
* c) a continuously-running task handling mailbox requests (2 above)
* The example conspicuously leaves out software interrupts (3 above), which
* is the thorniest issue to get right (see below).
*
* The naive, straightforward way to implement this would be:
* - create an isr which updates shared variables;
* - create a work_struct which handles software interrupts on a queue;
* - create a function which does reserve/update/unlock in a loop;
* - create a function which does mailbox send/receive in a loop;
* - call the above functions from the driver's read/write/ioctl;
* - synchronize using mutexes/spinlocks:
* + only one area request at a time
* + only one mailbox request at a time
* + protect AB_IND, AB_IND against data hazards (e.g. read-after-write)
*
* Unfortunately, the presence of the software interrupt causes subtle yet
* considerable synchronization issues; especially problematic is the
* requirement to reserve/release the area which contains the status bits.
*
* The driver architecture presented here sidesteps these synchronization issues
* by accessing the dpram from a single kernel thread only. User-space throws
* "tasks" (i.e. 1, 2 above) into a task queue, waits for their completion,
* and the kernel thread runs them to completion.
*
* Each task has a task_function, which is called/run by the queue thread.
* That function communicates with the Anybus card, and returns either
* 0 (OK), a negative error code (error), or -EINPROGRESS (waiting).
* On OK or error, the queue thread completes and dequeues the task,
* which also releases the user space thread which may still be waiting for it.
* On -EINPROGRESS (waiting), the queue thread will leave the task on the queue,
* and revisit (call again) whenever an interrupt event comes in.
*
* Each task has a state machine, which is run by calling its task_function.
* It ensures that the task will go through its various stages over time,
* returning -EINPROGRESS if it wants to wait for an event to happen.
*
* Note that according to the manual's driver example, the following operations
* may run independent of each other:
* - area reserve/read/write/release (point 1 above)
* - mailbox operations (point 2 above)
* - switching power on/off
*
* To allow them to run independently, each operation class gets its own queue.
*
* Userspace processes A, B, C, D post tasks to the appropriate queue,
* and wait for task completion:
*
* process A B C D
* | | | |
* v v v v
* |<----- ========================================
* | | | |
* | v v v-------<-------+
* | +--------------------------------------+ |
* | | power q | mbox q | area q | |
* | |------------|------------|------------| |
* | | task | task | task | |
* | | task | task | task | |
* | | task wait | task wait | task wait | |
* | +--------------------------------------+ |
* | ^ ^ ^ |
* | | | | ^
* | +--------------------------------------+ |
* | | queue thread | |
* | |--------------------------------------| |
* | | single-threaded: | |
* | | loop: | |
* v | for each queue: | |
* | | run task state machine | |
* | | if task waiting: | |
* | | leave on queue | |
* | | if task done: | |
* | | complete task, remove from q | |
* | | if software irq event bits set: | |
* | | notify userspace | |
* | | post clear event bits task------>|>-------+
* | | wait for IND_AB changed event OR |
* | | task added event OR |
* | | timeout |
* | | end loop |
* | +--------------------------------------+
* | + wake up +
* | +--------------------------------------+
* | ^ ^
* | | |
* +-------->------- |
* |
* +--------------------------------------+
* | interrupt service routine |
* |--------------------------------------|
* | wake up queue thread on IND_AB change|
* +--------------------------------------+
*
* Note that the Anybus interrupt is dual-purpose:
* - after a reset, triggered when the card becomes ready;
* - during normal operation, triggered when AB_IND changes.
* This is why the interrupt service routine doesn't just wake up the
* queue thread, but also completes the card_boot completion.
*
* [1] https://www.anybus.com/docs/librariesprovider7/default-document-library/
* manuals-design-guides/hms-hmsi-27-275.pdf
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/atomic.h>
#include <linux/kthread.h>
#include <linux/kfifo.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/random.h>
#include <linux/kref.h>
#include <linux/of_address.h>
/* move to <linux/anybuss-*.h> when taking this out of staging */
#include "anybuss-client.h"
#include "anybuss-controller.h"
#define DPRAM_SIZE 0x800
#define MAX_MBOX_MSG_SZ 0x0FF
#define TIMEOUT (HZ * 2)
#define MAX_DATA_AREA_SZ 0x200
#define MAX_FBCTRL_AREA_SZ 0x1BE
#define REG_BOOTLOADER_V 0x7C0
#define REG_API_V 0x7C2
#define REG_FIELDBUS_V 0x7C4
#define REG_SERIAL_NO 0x7C6
#define REG_FIELDBUS_TYPE 0x7CC
#define REG_MODULE_SW_V 0x7CE
#define REG_IND_AB 0x7FF
#define REG_IND_AP 0x7FE
#define REG_EVENT_CAUSE 0x7ED
#define MBOX_IN_AREA 0x400
#define MBOX_OUT_AREA 0x520
#define DATA_IN_AREA 0x000
#define DATA_OUT_AREA 0x200
#define FBCTRL_AREA 0x640
#define EVENT_CAUSE_DC 0x01
#define EVENT_CAUSE_FBOF 0x02
#define EVENT_CAUSE_FBON 0x04
#define IND_AB_UPDATED 0x08
#define IND_AX_MIN 0x80
#define IND_AX_MOUT 0x40
#define IND_AX_IN 0x04
#define IND_AX_OUT 0x02
#define IND_AX_FBCTRL 0x01
#define IND_AP_LOCK 0x08
#define IND_AP_ACTION 0x10
#define IND_AX_EVNT 0x20
#define IND_AP_ABITS (IND_AX_IN | IND_AX_OUT | \
IND_AX_FBCTRL | \
IND_AP_ACTION | IND_AP_LOCK)
#define INFO_TYPE_FB 0x0002
#define INFO_TYPE_APP 0x0001
#define INFO_COMMAND 0x4000
#define OP_MODE_FBFC 0x0002
#define OP_MODE_FBS 0x0004
#define OP_MODE_CD 0x0200
#define CMD_START_INIT 0x0001
#define CMD_ANYBUS_INIT 0x0002
#define CMD_END_INIT 0x0003
/*
* ---------------------------------------------------------------
* Anybus mailbox messages - definitions
* ---------------------------------------------------------------
* note that we're depending on the layout of these structures being
* exactly as advertised.
*/
struct anybus_mbox_hdr {
__be16 id;
__be16 info;
__be16 cmd_num;
__be16 data_size;
__be16 frame_count;
__be16 frame_num;
__be16 offset_high;
__be16 offset_low;
__be16 extended[8];
};
struct msg_anybus_init {
__be16 input_io_len;
__be16 input_dpram_len;
__be16 input_total_len;
__be16 output_io_len;
__be16 output_dpram_len;
__be16 output_total_len;
__be16 op_mode;
__be16 notif_config;
__be16 wd_val;
};
/* ------------- ref counted tasks ------------- */
struct ab_task;
typedef int (*ab_task_fn_t)(struct anybuss_host *cd,
struct ab_task *t);
typedef void (*ab_done_fn_t)(struct anybuss_host *cd);
struct area_priv {
bool is_write;
u16 flags;
u16 addr;
size_t count;
u8 buf[MAX_DATA_AREA_SZ];
};
struct mbox_priv {
struct anybus_mbox_hdr hdr;
size_t msg_out_sz;
size_t msg_in_sz;
u8 msg[MAX_MBOX_MSG_SZ];
};
struct ab_task {
struct kmem_cache *cache;
struct kref refcount;
ab_task_fn_t task_fn;
ab_done_fn_t done_fn;
int result;
struct completion done;
unsigned long start_jiffies;
union {
struct area_priv area_pd;
struct mbox_priv mbox_pd;
};
};
static struct ab_task *ab_task_create_get(struct kmem_cache *cache,
ab_task_fn_t task_fn)
{
struct ab_task *t;
t = kmem_cache_alloc(cache, GFP_KERNEL);
if (!t)
return NULL;
t->cache = cache;
kref_init(&t->refcount);
t->task_fn = task_fn;
t->done_fn = NULL;
t->result = 0;
init_completion(&t->done);
return t;
}
static void __ab_task_destroy(struct kref *refcount)
{
struct ab_task *t = container_of(refcount, struct ab_task, refcount);
struct kmem_cache *cache = t->cache;
kmem_cache_free(cache, t);
}
static void ab_task_put(struct ab_task *t)
{
kref_put(&t->refcount, __ab_task_destroy);
}
static struct ab_task *__ab_task_get(struct ab_task *t)
{
kref_get(&t->refcount);
return t;
}
static void __ab_task_finish(struct ab_task *t, struct anybuss_host *cd)
{
if (t->done_fn)
t->done_fn(cd);
complete(&t->done);
}
static void
ab_task_dequeue_finish_put(struct kfifo *q, struct anybuss_host *cd)
{
int ret;
struct ab_task *t;
ret = kfifo_out(q, &t, sizeof(t));
WARN_ON(!ret);
__ab_task_finish(t, cd);
ab_task_put(t);
}
static int
ab_task_enqueue(struct ab_task *t, struct kfifo *q, spinlock_t *slock,
wait_queue_head_t *wq)
{
int ret;
t->start_jiffies = jiffies;
__ab_task_get(t);
ret = kfifo_in_spinlocked(q, &t, sizeof(t), slock);
if (!ret) {
ab_task_put(t);
return -ENOMEM;
}
wake_up(wq);
return 0;
}
static int
ab_task_enqueue_wait(struct ab_task *t, struct kfifo *q, spinlock_t *slock,
wait_queue_head_t *wq)
{
int ret;
ret = ab_task_enqueue(t, q, slock, wq);
if (ret)
return ret;
ret = wait_for_completion_interruptible(&t->done);
if (ret)
return ret;
return t->result;
}
/* ------------------------ anybus hardware ------------------------ */
struct anybuss_host {
struct device *dev;
struct anybuss_client *client;
void (*reset)(struct device *dev, bool assert);
struct regmap *regmap;
int irq;
int host_idx;
struct task_struct *qthread;
wait_queue_head_t wq;
struct completion card_boot;
atomic_t ind_ab;
spinlock_t qlock; /* protects IN side of powerq, mboxq, areaq */
struct kmem_cache *qcache;
struct kfifo qs[3];
struct kfifo *powerq;
struct kfifo *mboxq;
struct kfifo *areaq;
bool power_on;
bool softint_pending;
};
static void reset_assert(struct anybuss_host *cd)
{
cd->reset(cd->dev, true);
}
static void reset_deassert(struct anybuss_host *cd)
{
cd->reset(cd->dev, false);
}
static int test_dpram(struct regmap *regmap)
{
int i;
unsigned int val;
for (i = 0; i < DPRAM_SIZE; i++)
regmap_write(regmap, i, (u8)i);
for (i = 0; i < DPRAM_SIZE; i++) {
regmap_read(regmap, i, &val);
if ((u8)val != (u8)i)
return -EIO;
}
return 0;
}
static int read_ind_ab(struct regmap *regmap)
{
unsigned long timeout = jiffies + HZ / 2;
unsigned int a, b, i = 0;
while (time_before_eq(jiffies, timeout)) {
regmap_read(regmap, REG_IND_AB, &a);
regmap_read(regmap, REG_IND_AB, &b);
if (likely(a == b))
return (int)a;
if (i < 10) {
cpu_relax();
i++;
} else {
usleep_range(500, 1000);
}
}
WARN(1, "IND_AB register not stable");
return -ETIMEDOUT;
}
static int write_ind_ap(struct regmap *regmap, unsigned int ind_ap)
{
unsigned long timeout = jiffies + HZ / 2;
unsigned int v, i = 0;
while (time_before_eq(jiffies, timeout)) {
regmap_write(regmap, REG_IND_AP, ind_ap);
regmap_read(regmap, REG_IND_AP, &v);
if (likely(ind_ap == v))
return 0;
if (i < 10) {
cpu_relax();
i++;
} else {
usleep_range(500, 1000);
}
}
WARN(1, "IND_AP register not stable");
return -ETIMEDOUT;
}
static irqreturn_t irq_handler(int irq, void *data)
{
struct anybuss_host *cd = data;
int ind_ab;
/*
* irq handler needs exclusive access to the IND_AB register,
* because the act of reading the register acks the interrupt.
*
* store the register value in cd->ind_ab (an atomic_t), so that the
* queue thread is able to read it without causing an interrupt ack
* side-effect (and without spuriously acking an interrupt).
*/
ind_ab = read_ind_ab(cd->regmap);
if (ind_ab < 0)
return IRQ_NONE;
atomic_set(&cd->ind_ab, ind_ab);
complete(&cd->card_boot);
wake_up(&cd->wq);
return IRQ_HANDLED;
}
/* ------------------------ power on/off tasks --------------------- */
static int task_fn_power_off(struct anybuss_host *cd,
struct ab_task *t)
{
struct anybuss_client *client = cd->client;
if (!cd->power_on)
return 0;
disable_irq(cd->irq);
reset_assert(cd);
atomic_set(&cd->ind_ab, IND_AB_UPDATED);
if (client->on_online_changed)
client->on_online_changed(client, false);
cd->power_on = false;
return 0;
}
static int task_fn_power_on_2(struct anybuss_host *cd,
struct ab_task *t)
{
if (completion_done(&cd->card_boot)) {
cd->power_on = true;
return 0;
}
if (time_after(jiffies, t->start_jiffies + TIMEOUT)) {
disable_irq(cd->irq);
reset_assert(cd);
dev_err(cd->dev, "power on timed out");
return -ETIMEDOUT;
}
return -EINPROGRESS;
}
static int task_fn_power_on(struct anybuss_host *cd,
struct ab_task *t)
{
unsigned int dummy;
if (cd->power_on)
return 0;
/*
* anybus docs: prevent false 'init done' interrupt by
* doing a dummy read of IND_AB register while in reset.
*/
regmap_read(cd->regmap, REG_IND_AB, &dummy);
reinit_completion(&cd->card_boot);
enable_irq(cd->irq);
reset_deassert(cd);
t->task_fn = task_fn_power_on_2;
return -EINPROGRESS;
}
int anybuss_set_power(struct anybuss_client *client, bool power_on)
{
struct anybuss_host *cd = client->host;
struct ab_task *t;
int err;
t = ab_task_create_get(cd->qcache, power_on ?
task_fn_power_on : task_fn_power_off);
if (!t)
return -ENOMEM;
err = ab_task_enqueue_wait(t, cd->powerq, &cd->qlock, &cd->wq);
ab_task_put(t);
return err;
}
EXPORT_SYMBOL_GPL(anybuss_set_power);
/* ---------------------------- area tasks ------------------------ */
static int task_fn_area_3(struct anybuss_host *cd, struct ab_task *t)
{
struct area_priv *pd = &t->area_pd;
if (!cd->power_on)
return -EIO;
if (atomic_read(&cd->ind_ab) & pd->flags) {
/* area not released yet */
if (time_after(jiffies, t->start_jiffies + TIMEOUT))
return -ETIMEDOUT;
return -EINPROGRESS;
}
return 0;
}
static int task_fn_area_2(struct anybuss_host *cd, struct ab_task *t)
{
struct area_priv *pd = &t->area_pd;
unsigned int ind_ap;
int ret;
if (!cd->power_on)
return -EIO;
regmap_read(cd->regmap, REG_IND_AP, &ind_ap);
if (!(atomic_read(&cd->ind_ab) & pd->flags)) {
/* we don't own the area yet */
if (time_after(jiffies, t->start_jiffies + TIMEOUT)) {
dev_warn(cd->dev, "timeout waiting for area");
dump_stack();
return -ETIMEDOUT;
}
return -EINPROGRESS;
}
/* we own the area, do what we're here to do */
if (pd->is_write)
regmap_bulk_write(cd->regmap, pd->addr, pd->buf,
pd->count);
else
regmap_bulk_read(cd->regmap, pd->addr, pd->buf,
pd->count);
/* ask to release the area, must use unlocked release */
ind_ap &= ~IND_AP_ABITS;
ind_ap |= pd->flags;
ret = write_ind_ap(cd->regmap, ind_ap);
if (ret)
return ret;
t->task_fn = task_fn_area_3;
return -EINPROGRESS;
}
static int task_fn_area(struct anybuss_host *cd, struct ab_task *t)
{
struct area_priv *pd = &t->area_pd;
unsigned int ind_ap;
int ret;
if (!cd->power_on)
return -EIO;
regmap_read(cd->regmap, REG_IND_AP, &ind_ap);
/* ask to take the area */
ind_ap &= ~IND_AP_ABITS;
ind_ap |= pd->flags | IND_AP_ACTION | IND_AP_LOCK;
ret = write_ind_ap(cd->regmap, ind_ap);
if (ret)
return ret;
t->task_fn = task_fn_area_2;
return -EINPROGRESS;
}
static struct ab_task *
create_area_reader(struct kmem_cache *qcache, u16 flags, u16 addr,
size_t count)
{
struct ab_task *t;
struct area_priv *ap;
t = ab_task_create_get(qcache, task_fn_area);
if (!t)
return NULL;
ap = &t->area_pd;
ap->flags = flags;
ap->addr = addr;
ap->is_write = false;
ap->count = count;
return t;
}
static struct ab_task *
create_area_writer(struct kmem_cache *qcache, u16 flags, u16 addr,
const void *buf, size_t count)
{
struct ab_task *t;
struct area_priv *ap;
t = ab_task_create_get(qcache, task_fn_area);
if (!t)
return NULL;
ap = &t->area_pd;
ap->flags = flags;
ap->addr = addr;
ap->is_write = true;
ap->count = count;
memcpy(ap->buf, buf, count);
return t;
}
static struct ab_task *
create_area_user_writer(struct kmem_cache *qcache, u16 flags, u16 addr,
const void __user *buf, size_t count)
{
struct ab_task *t;
struct area_priv *ap;
t = ab_task_create_get(qcache, task_fn_area);
if (!t)
return ERR_PTR(-ENOMEM);
ap = &t->area_pd;
ap->flags = flags;
ap->addr = addr;
ap->is_write = true;
ap->count = count;
if (copy_from_user(ap->buf, buf, count)) {
ab_task_put(t);
return ERR_PTR(-EFAULT);
}
return t;
}
static bool area_range_ok(u16 addr, size_t count, u16 area_start,
size_t area_sz)
{
u16 area_end_ex = area_start + area_sz;
u16 addr_end_ex;
if (addr < area_start)
return false;
if (addr >= area_end_ex)
return false;
addr_end_ex = addr + count;
if (addr_end_ex > area_end_ex)
return false;
return true;
}
/* -------------------------- mailbox tasks ----------------------- */
static int task_fn_mbox_2(struct anybuss_host *cd, struct ab_task *t)
{
struct mbox_priv *pd = &t->mbox_pd;
unsigned int ind_ap;
if (!cd->power_on)
return -EIO;
regmap_read(cd->regmap, REG_IND_AP, &ind_ap);
if (((atomic_read(&cd->ind_ab) ^ ind_ap) & IND_AX_MOUT) == 0) {
/* output message not here */
if (time_after(jiffies, t->start_jiffies + TIMEOUT))
return -ETIMEDOUT;
return -EINPROGRESS;
}
/* grab the returned header and msg */
regmap_bulk_read(cd->regmap, MBOX_OUT_AREA, &pd->hdr,
sizeof(pd->hdr));
regmap_bulk_read(cd->regmap, MBOX_OUT_AREA + sizeof(pd->hdr),
pd->msg, pd->msg_in_sz);
/* tell anybus we've consumed the message */
ind_ap ^= IND_AX_MOUT;
return write_ind_ap(cd->regmap, ind_ap);
}
static int task_fn_mbox(struct anybuss_host *cd, struct ab_task *t)
{
struct mbox_priv *pd = &t->mbox_pd;
unsigned int ind_ap;
int ret;
if (!cd->power_on)
return -EIO;
regmap_read(cd->regmap, REG_IND_AP, &ind_ap);
if ((atomic_read(&cd->ind_ab) ^ ind_ap) & IND_AX_MIN) {
/* mbox input area busy */
if (time_after(jiffies, t->start_jiffies + TIMEOUT))
return -ETIMEDOUT;
return -EINPROGRESS;
}
/* write the header and msg to input area */
regmap_bulk_write(cd->regmap, MBOX_IN_AREA, &pd->hdr,
sizeof(pd->hdr));
regmap_bulk_write(cd->regmap, MBOX_IN_AREA + sizeof(pd->hdr),
pd->msg, pd->msg_out_sz);
/* tell anybus we gave it a message */
ind_ap ^= IND_AX_MIN;
ret = write_ind_ap(cd->regmap, ind_ap);
if (ret)
return ret;
t->start_jiffies = jiffies;
t->task_fn = task_fn_mbox_2;
return -EINPROGRESS;
}
static void log_invalid_other(struct device *dev,
struct anybus_mbox_hdr *hdr)
{
size_t ext_offs = ARRAY_SIZE(hdr->extended) - 1;
u16 code = be16_to_cpu(hdr->extended[ext_offs]);
dev_err(dev, " Invalid other: [0x%02X]", code);
}
static const char * const EMSGS[] = {
"Invalid Message ID",
"Invalid Message Type",
"Invalid Command",
"Invalid Data Size",
"Message Header Malformed (offset 008h)",
"Message Header Malformed (offset 00Ah)",
"Message Header Malformed (offset 00Ch - 00Dh)",
"Invalid Address",
"Invalid Response",
"Flash Config Error",
};
static int mbox_cmd_err(struct device *dev, struct mbox_priv *mpriv)
{
int i;
u8 ecode;
struct anybus_mbox_hdr *hdr = &mpriv->hdr;
u16 info = be16_to_cpu(hdr->info);
u8 *phdr = (u8 *)hdr;
u8 *pmsg = mpriv->msg;
if (!(info & 0x8000))
return 0;
ecode = (info >> 8) & 0x0F;
dev_err(dev, "mailbox command failed:");
if (ecode == 0x0F)
log_invalid_other(dev, hdr);
else if (ecode < ARRAY_SIZE(EMSGS))
dev_err(dev, " Error code: %s (0x%02X)",
EMSGS[ecode], ecode);
else
dev_err(dev, " Error code: 0x%02X\n", ecode);
dev_err(dev, "Failed command:");
dev_err(dev, "Message Header:");
for (i = 0; i < sizeof(mpriv->hdr); i += 2)
dev_err(dev, "%02X%02X", phdr[i], phdr[i + 1]);
dev_err(dev, "Message Data:");
for (i = 0; i < mpriv->msg_in_sz; i += 2)
dev_err(dev, "%02X%02X", pmsg[i], pmsg[i + 1]);
dev_err(dev, "Stack dump:");
dump_stack();
return -EIO;
}
static int _anybus_mbox_cmd(struct anybuss_host *cd,
u16 cmd_num, bool is_fb_cmd,
const void *msg_out, size_t msg_out_sz,
void *msg_in, size_t msg_in_sz,
const void *ext, size_t ext_sz)
{
struct ab_task *t;
struct mbox_priv *pd;
struct anybus_mbox_hdr *h;
size_t msg_sz = max(msg_in_sz, msg_out_sz);
u16 info;
int err;
if (msg_sz > MAX_MBOX_MSG_SZ)
return -EINVAL;
if (ext && ext_sz > sizeof(h->extended))
return -EINVAL;
t = ab_task_create_get(cd->qcache, task_fn_mbox);
if (!t)
return -ENOMEM;
pd = &t->mbox_pd;
h = &pd->hdr;
info = is_fb_cmd ? INFO_TYPE_FB : INFO_TYPE_APP;
/*
* prevent uninitialized memory in the header from being sent
* across the anybus
*/
memset(h, 0, sizeof(*h));
h->info = cpu_to_be16(info | INFO_COMMAND);
h->cmd_num = cpu_to_be16(cmd_num);
h->data_size = cpu_to_be16(msg_out_sz);
h->frame_count = cpu_to_be16(1);
h->frame_num = cpu_to_be16(1);
h->offset_high = cpu_to_be16(0);
h->offset_low = cpu_to_be16(0);
if (ext)
memcpy(h->extended, ext, ext_sz);
memcpy(pd->msg, msg_out, msg_out_sz);
pd->msg_out_sz = msg_out_sz;
pd->msg_in_sz = msg_in_sz;
err = ab_task_enqueue_wait(t, cd->powerq, &cd->qlock, &cd->wq);
if (err)
goto out;
/*
* mailbox mechanism worked ok, but maybe the mbox response
* contains an error ?
*/
err = mbox_cmd_err(cd->dev, pd);
if (err)
goto out;
memcpy(msg_in, pd->msg, msg_in_sz);
out:
ab_task_put(t);
return err;
}
/* ------------------------ anybus queues ------------------------ */
static void process_q(struct anybuss_host *cd, struct kfifo *q)
{
struct ab_task *t;
int ret;
ret = kfifo_out_peek(q, &t, sizeof(t));
if (!ret)
return;
t->result = t->task_fn(cd, t);
if (t->result != -EINPROGRESS)
ab_task_dequeue_finish_put(q, cd);
}
static bool qs_have_work(struct kfifo *qs, size_t num)
{
size_t i;
struct ab_task *t;
int ret;
for (i = 0; i < num; i++, qs++) {
ret = kfifo_out_peek(qs, &t, sizeof(t));
if (ret && (t->result != -EINPROGRESS))
return true;
}
return false;
}
static void process_qs(struct anybuss_host *cd)
{
size_t i;
struct kfifo *qs = cd->qs;
size_t nqs = ARRAY_SIZE(cd->qs);
for (i = 0; i < nqs; i++, qs++)
process_q(cd, qs);
}
static void softint_ack(struct anybuss_host *cd)
{
unsigned int ind_ap;
cd->softint_pending = false;
if (!cd->power_on)
return;
regmap_read(cd->regmap, REG_IND_AP, &ind_ap);
ind_ap &= ~IND_AX_EVNT;
ind_ap |= atomic_read(&cd->ind_ab) & IND_AX_EVNT;
write_ind_ap(cd->regmap, ind_ap);
}
static void process_softint(struct anybuss_host *cd)
{
struct anybuss_client *client = cd->client;
static const u8 zero;
int ret;
unsigned int ind_ap, ev;
struct ab_task *t;
if (!cd->power_on)
return;
if (cd->softint_pending)
return;
regmap_read(cd->regmap, REG_IND_AP, &ind_ap);
if (!((atomic_read(&cd->ind_ab) ^ ind_ap) & IND_AX_EVNT))
return;
/* process software interrupt */
regmap_read(cd->regmap, REG_EVENT_CAUSE, &ev);
if (ev & EVENT_CAUSE_FBON) {
if (client->on_online_changed)
client->on_online_changed(client, true);
dev_dbg(cd->dev, "Fieldbus ON");
}
if (ev & EVENT_CAUSE_FBOF) {
if (client->on_online_changed)
client->on_online_changed(client, false);
dev_dbg(cd->dev, "Fieldbus OFF");
}
if (ev & EVENT_CAUSE_DC) {
if (client->on_area_updated)
client->on_area_updated(client);
dev_dbg(cd->dev, "Fieldbus data changed");
}
/*
* reset the event cause bits.
* this must be done while owning the fbctrl area, so we'll
* enqueue a task to do that.
*/
t = create_area_writer(cd->qcache, IND_AX_FBCTRL,
REG_EVENT_CAUSE, &zero, sizeof(zero));
if (!t) {
ret = -ENOMEM;
goto out;
}
t->done_fn = softint_ack;
ret = ab_task_enqueue(t, cd->powerq, &cd->qlock, &cd->wq);
ab_task_put(t);
cd->softint_pending = true;
out:
WARN_ON(ret);
if (ret)
softint_ack(cd);
}
static int qthread_fn(void *data)
{
struct anybuss_host *cd = data;
struct kfifo *qs = cd->qs;
size_t nqs = ARRAY_SIZE(cd->qs);
unsigned int ind_ab;
/*
* this kernel thread has exclusive access to the anybus's memory.
* only exception: the IND_AB register, which is accessed exclusively
* by the interrupt service routine (ISR). This thread must not touch
* the IND_AB register, but it does require access to its value.
*
* the interrupt service routine stores the register's value in
* cd->ind_ab (an atomic_t), where we may safely access it, with the
* understanding that it can be modified by the ISR at any time.
*/
while (!kthread_should_stop()) {
/*
* make a local copy of IND_AB, so we can go around the loop
* again in case it changed while processing queues and softint.
*/
ind_ab = atomic_read(&cd->ind_ab);
process_qs(cd);
process_softint(cd);
wait_event_timeout(cd->wq,
(atomic_read(&cd->ind_ab) != ind_ab) ||
qs_have_work(qs, nqs) ||
kthread_should_stop(),
HZ);
/*
* time out so even 'stuck' tasks will run eventually,
* and can time out.
*/
}
return 0;
}
/* ------------------------ anybus exports ------------------------ */
int anybuss_start_init(struct anybuss_client *client,
const struct anybuss_memcfg *cfg)
{
int ret;
u16 op_mode;
struct anybuss_host *cd = client->host;
struct msg_anybus_init msg = {
.input_io_len = cpu_to_be16(cfg->input_io),
.input_dpram_len = cpu_to_be16(cfg->input_dpram),
.input_total_len = cpu_to_be16(cfg->input_total),
.output_io_len = cpu_to_be16(cfg->output_io),
.output_dpram_len = cpu_to_be16(cfg->output_dpram),
.output_total_len = cpu_to_be16(cfg->output_total),
.notif_config = cpu_to_be16(0x000F),
.wd_val = cpu_to_be16(0),
};
switch (cfg->offl_mode) {
case FIELDBUS_DEV_OFFL_MODE_CLEAR:
op_mode = 0;
break;
case FIELDBUS_DEV_OFFL_MODE_FREEZE:
op_mode = OP_MODE_FBFC;
break;
case FIELDBUS_DEV_OFFL_MODE_SET:
op_mode = OP_MODE_FBS;
break;
default:
return -EINVAL;
}
msg.op_mode = cpu_to_be16(op_mode | OP_MODE_CD);
ret = _anybus_mbox_cmd(cd, CMD_START_INIT, false, NULL, 0,
NULL, 0, NULL, 0);
if (ret)
return ret;
return _anybus_mbox_cmd(cd, CMD_ANYBUS_INIT, false,
&msg, sizeof(msg), NULL, 0, NULL, 0);
}
EXPORT_SYMBOL_GPL(anybuss_start_init);
int anybuss_finish_init(struct anybuss_client *client)
{
struct anybuss_host *cd = client->host;
return _anybus_mbox_cmd(cd, CMD_END_INIT, false, NULL, 0,
NULL, 0, NULL, 0);
}
EXPORT_SYMBOL_GPL(anybuss_finish_init);
int anybuss_read_fbctrl(struct anybuss_client *client, u16 addr,
void *buf, size_t count)
{
struct anybuss_host *cd = client->host;
struct ab_task *t;
int ret;
if (count == 0)
return 0;
if (!area_range_ok(addr, count, FBCTRL_AREA,
MAX_FBCTRL_AREA_SZ))
return -EFAULT;
t = create_area_reader(cd->qcache, IND_AX_FBCTRL, addr, count);
if (!t)
return -ENOMEM;
ret = ab_task_enqueue_wait(t, cd->powerq, &cd->qlock, &cd->wq);
if (ret)
goto out;
memcpy(buf, t->area_pd.buf, count);
out:
ab_task_put(t);
return ret;
}
EXPORT_SYMBOL_GPL(anybuss_read_fbctrl);
int anybuss_write_input(struct anybuss_client *client,
const char __user *buf, size_t size,
loff_t *offset)
{
ssize_t len = min_t(loff_t, MAX_DATA_AREA_SZ - *offset, size);
struct anybuss_host *cd = client->host;
struct ab_task *t;
int ret;
if (len <= 0)
return 0;
t = create_area_user_writer(cd->qcache, IND_AX_IN,
DATA_IN_AREA + *offset, buf, len);
if (IS_ERR(t))
return PTR_ERR(t);
ret = ab_task_enqueue_wait(t, cd->powerq, &cd->qlock, &cd->wq);
ab_task_put(t);
if (ret)
return ret;
/* success */
*offset += len;
return len;
}
EXPORT_SYMBOL_GPL(anybuss_write_input);
int anybuss_read_output(struct anybuss_client *client,
char __user *buf, size_t size,
loff_t *offset)
{
ssize_t len = min_t(loff_t, MAX_DATA_AREA_SZ - *offset, size);
struct anybuss_host *cd = client->host;
struct ab_task *t;
int ret;
if (len <= 0)
return 0;
t = create_area_reader(cd->qcache, IND_AX_OUT,
DATA_OUT_AREA + *offset, len);
if (!t)
return -ENOMEM;
ret = ab_task_enqueue_wait(t, cd->powerq, &cd->qlock, &cd->wq);
if (ret)
goto out;
if (copy_to_user(buf, t->area_pd.buf, len))
ret = -EFAULT;
out:
ab_task_put(t);
if (ret)
return ret;
/* success */
*offset += len;
return len;
}
EXPORT_SYMBOL_GPL(anybuss_read_output);
int anybuss_send_msg(struct anybuss_client *client, u16 cmd_num,
const void *buf, size_t count)
{
struct anybuss_host *cd = client->host;
return _anybus_mbox_cmd(cd, cmd_num, true, buf, count, NULL, 0,
NULL, 0);
}
EXPORT_SYMBOL_GPL(anybuss_send_msg);
int anybuss_send_ext(struct anybuss_client *client, u16 cmd_num,
const void *buf, size_t count)
{
struct anybuss_host *cd = client->host;
return _anybus_mbox_cmd(cd, cmd_num, true, NULL, 0, NULL, 0,
buf, count);
}
EXPORT_SYMBOL_GPL(anybuss_send_ext);
int anybuss_recv_msg(struct anybuss_client *client, u16 cmd_num,
void *buf, size_t count)
{
struct anybuss_host *cd = client->host;
return _anybus_mbox_cmd(cd, cmd_num, true, NULL, 0, buf, count,
NULL, 0);
}
EXPORT_SYMBOL_GPL(anybuss_recv_msg);
/* ------------------------ bus functions ------------------------ */
static int anybus_bus_match(struct device *dev,
struct device_driver *drv)
{
struct anybuss_client_driver *adrv =
to_anybuss_client_driver(drv);
struct anybuss_client *adev =
to_anybuss_client(dev);
return adrv->anybus_id == be16_to_cpu(adev->anybus_id);
}
static int anybus_bus_probe(struct device *dev)
{
struct anybuss_client_driver *adrv =
to_anybuss_client_driver(dev->driver);
struct anybuss_client *adev =
to_anybuss_client(dev);
return adrv->probe(adev);
}
static void anybus_bus_remove(struct device *dev)
{
struct anybuss_client_driver *adrv =
to_anybuss_client_driver(dev->driver);
if (adrv->remove)
adrv->remove(to_anybuss_client(dev));
}
static struct bus_type anybus_bus = {
.name = "anybuss",
.match = anybus_bus_match,
.probe = anybus_bus_probe,
.remove = anybus_bus_remove,
};
int anybuss_client_driver_register(struct anybuss_client_driver *drv)
{
if (!drv->probe)
return -ENODEV;
drv->driver.bus = &anybus_bus;
return driver_register(&drv->driver);
}
EXPORT_SYMBOL_GPL(anybuss_client_driver_register);
void anybuss_client_driver_unregister(struct anybuss_client_driver *drv)
{
return driver_unregister(&drv->driver);
}
EXPORT_SYMBOL_GPL(anybuss_client_driver_unregister);
static void client_device_release(struct device *dev)
{
kfree(to_anybuss_client(dev));
}
static int taskq_alloc(struct device *dev, struct kfifo *q)
{
void *buf;
size_t size = 64 * sizeof(struct ab_task *);
buf = devm_kzalloc(dev, size, GFP_KERNEL);
if (!buf)
return -EIO;
return kfifo_init(q, buf, size);
}
static int anybus_of_get_host_idx(struct device_node *np)
{
const __be32 *host_idx;
host_idx = of_get_address(np, 0, NULL, NULL);
if (!host_idx)
return -ENOENT;
return __be32_to_cpu(*host_idx);
}
static struct device_node *
anybus_of_find_child_device(struct device *dev, int host_idx)
{
struct device_node *node;
if (!dev || !dev->of_node)
return NULL;
for_each_child_of_node(dev->of_node, node) {
if (anybus_of_get_host_idx(node) == host_idx)
return node;
}
return NULL;
}
struct anybuss_host * __must_check
anybuss_host_common_probe(struct device *dev,
const struct anybuss_ops *ops)
{
int ret, i;
u8 val[4];
__be16 fieldbus_type;
struct anybuss_host *cd;
cd = devm_kzalloc(dev, sizeof(*cd), GFP_KERNEL);
if (!cd)
return ERR_PTR(-ENOMEM);
cd->dev = dev;
cd->host_idx = ops->host_idx;
init_completion(&cd->card_boot);
init_waitqueue_head(&cd->wq);
for (i = 0; i < ARRAY_SIZE(cd->qs); i++) {
ret = taskq_alloc(dev, &cd->qs[i]);
if (ret)
return ERR_PTR(ret);
}
if (WARN_ON(ARRAY_SIZE(cd->qs) < 3))
return ERR_PTR(-EINVAL);
cd->powerq = &cd->qs[0];
cd->mboxq = &cd->qs[1];
cd->areaq = &cd->qs[2];
cd->reset = ops->reset;
if (!cd->reset)
return ERR_PTR(-EINVAL);
cd->regmap = ops->regmap;
if (!cd->regmap)
return ERR_PTR(-EINVAL);
spin_lock_init(&cd->qlock);
cd->qcache = kmem_cache_create(dev_name(dev),
sizeof(struct ab_task), 0, 0, NULL);
if (!cd->qcache)
return ERR_PTR(-ENOMEM);
cd->irq = ops->irq;
if (cd->irq <= 0) {
ret = -EINVAL;
goto err_qcache;
}
/*
* use a dpram test to check if a card is present, this is only
* possible while in reset.
*/
reset_assert(cd);
if (test_dpram(cd->regmap)) {
dev_err(dev, "no Anybus-S card in slot");
ret = -ENODEV;
goto err_qcache;
}
ret = devm_request_threaded_irq(dev, cd->irq, NULL, irq_handler,
IRQF_ONESHOT, dev_name(dev), cd);
if (ret) {
dev_err(dev, "could not request irq");
goto err_qcache;
}
/*
* startup sequence:
* a) perform dummy IND_AB read to prevent false 'init done' irq
* (already done by test_dpram() above)
* b) release reset
* c) wait for first interrupt
* d) interrupt came in: ready to go !
*/
reset_deassert(cd);
if (!wait_for_completion_timeout(&cd->card_boot, TIMEOUT)) {
ret = -ETIMEDOUT;
goto err_reset;
}
/*
* according to the anybus docs, we're allowed to read these
* without handshaking / reserving the area
*/
dev_info(dev, "Anybus-S card detected");
regmap_bulk_read(cd->regmap, REG_BOOTLOADER_V, val, 2);
dev_info(dev, "Bootloader version: %02X%02X",
val[0], val[1]);
regmap_bulk_read(cd->regmap, REG_API_V, val, 2);
dev_info(dev, "API version: %02X%02X", val[0], val[1]);
regmap_bulk_read(cd->regmap, REG_FIELDBUS_V, val, 2);
dev_info(dev, "Fieldbus version: %02X%02X", val[0], val[1]);
regmap_bulk_read(cd->regmap, REG_SERIAL_NO, val, 4);
dev_info(dev, "Serial number: %02X%02X%02X%02X",
val[0], val[1], val[2], val[3]);
add_device_randomness(&val, 4);
regmap_bulk_read(cd->regmap, REG_FIELDBUS_TYPE, &fieldbus_type,
sizeof(fieldbus_type));
dev_info(dev, "Fieldbus type: %04X", be16_to_cpu(fieldbus_type));
regmap_bulk_read(cd->regmap, REG_MODULE_SW_V, val, 2);
dev_info(dev, "Module SW version: %02X%02X",
val[0], val[1]);
/* put card back reset until a client driver releases it */
disable_irq(cd->irq);
reset_assert(cd);
atomic_set(&cd->ind_ab, IND_AB_UPDATED);
/* fire up the queue thread */
cd->qthread = kthread_run(qthread_fn, cd, dev_name(dev));
if (IS_ERR(cd->qthread)) {
dev_err(dev, "could not create kthread");
ret = PTR_ERR(cd->qthread);
goto err_reset;
}
/*
* now advertise that we've detected a client device (card).
* the bus infrastructure will match it to a client driver.
*/
cd->client = kzalloc(sizeof(*cd->client), GFP_KERNEL);
if (!cd->client) {
ret = -ENOMEM;
goto err_kthread;
}
cd->client->anybus_id = fieldbus_type;
cd->client->host = cd;
cd->client->dev.bus = &anybus_bus;
cd->client->dev.parent = dev;
cd->client->dev.release = client_device_release;
cd->client->dev.of_node =
anybus_of_find_child_device(dev, cd->host_idx);
dev_set_name(&cd->client->dev, "anybuss.card%d", cd->host_idx);
ret = device_register(&cd->client->dev);
if (ret)
goto err_device;
return cd;
err_device:
put_device(&cd->client->dev);
err_kthread:
kthread_stop(cd->qthread);
err_reset:
reset_assert(cd);
err_qcache:
kmem_cache_destroy(cd->qcache);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(anybuss_host_common_probe);
void anybuss_host_common_remove(struct anybuss_host *host)
{
struct anybuss_host *cd = host;
device_unregister(&cd->client->dev);
kthread_stop(cd->qthread);
reset_assert(cd);
kmem_cache_destroy(cd->qcache);
}
EXPORT_SYMBOL_GPL(anybuss_host_common_remove);
static void host_release(void *res)
{
anybuss_host_common_remove(res);
}
struct anybuss_host * __must_check
devm_anybuss_host_common_probe(struct device *dev,
const struct anybuss_ops *ops)
{
struct anybuss_host *host;
int ret;
host = anybuss_host_common_probe(dev, ops);
if (IS_ERR(host))
return host;
ret = devm_add_action_or_reset(dev, host_release, host);
if (ret)
return ERR_PTR(ret);
return host;
}
EXPORT_SYMBOL_GPL(devm_anybuss_host_common_probe);
static int __init anybus_init(void)
{
int ret;
ret = bus_register(&anybus_bus);
if (ret)
pr_err("could not register Anybus-S bus: %d\n", ret);
return ret;
}
module_init(anybus_init);
static void __exit anybus_exit(void)
{
bus_unregister(&anybus_bus);
}
module_exit(anybus_exit);
MODULE_DESCRIPTION("HMS Anybus-S Host Driver");
MODULE_AUTHOR("Sven Van Asbroeck <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/staging/fieldbus/anybuss/host.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Arcx Anybus-S Controller driver
*
* Copyright (C) 2018 Arcx Inc
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/idr.h>
#include <linux/mutex.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regmap.h>
/* move to <linux/anybuss-controller.h> when taking this out of staging */
#include "anybuss-controller.h"
#define CPLD_STATUS1 0x80
#define CPLD_CONTROL 0x80
#define CPLD_CONTROL_CRST 0x40
#define CPLD_CONTROL_RST1 0x04
#define CPLD_CONTROL_RST2 0x80
#define CPLD_STATUS1_AB 0x02
#define CPLD_STATUS1_CAN_POWER 0x01
#define CPLD_DESIGN_LO 0x81
#define CPLD_DESIGN_HI 0x82
#define CPLD_CAP 0x83
#define CPLD_CAP_COMPAT 0x01
#define CPLD_CAP_SEP_RESETS 0x02
struct controller_priv {
struct device *class_dev;
bool common_reset;
struct gpio_desc *reset_gpiod;
void __iomem *cpld_base;
struct mutex ctrl_lock; /* protects CONTROL register */
u8 control_reg;
char version[3];
u16 design_no;
};
static void do_reset(struct controller_priv *cd, u8 rst_bit, bool reset)
{
mutex_lock(&cd->ctrl_lock);
/*
* CPLD_CONTROL is write-only, so cache its value in
* cd->control_reg
*/
if (reset)
cd->control_reg &= ~rst_bit;
else
cd->control_reg |= rst_bit;
writeb(cd->control_reg, cd->cpld_base + CPLD_CONTROL);
/*
* h/w work-around:
* the hardware is 'too fast', so a reset followed by an immediate
* not-reset will _not_ change the anybus reset line in any way,
* losing the reset. to prevent this from happening, introduce
* a minimum reset duration.
* Verified minimum safe duration required using a scope
* on 14-June-2018: 100 us.
*/
if (reset)
usleep_range(100, 200);
mutex_unlock(&cd->ctrl_lock);
}
static int anybuss_reset(struct controller_priv *cd,
unsigned long id, bool reset)
{
if (id >= 2)
return -EINVAL;
if (cd->common_reset)
do_reset(cd, CPLD_CONTROL_CRST, reset);
else
do_reset(cd, id ? CPLD_CONTROL_RST2 : CPLD_CONTROL_RST1, reset);
return 0;
}
static void export_reset_0(struct device *dev, bool assert)
{
struct controller_priv *cd = dev_get_drvdata(dev);
anybuss_reset(cd, 0, assert);
}
static void export_reset_1(struct device *dev, bool assert)
{
struct controller_priv *cd = dev_get_drvdata(dev);
anybuss_reset(cd, 1, assert);
}
/*
* parallel bus limitation:
*
* the anybus is 8-bit wide. we can't assume that the hardware will translate
* word accesses on the parallel bus to multiple byte-accesses on the anybus.
*
* the imx WEIM bus does not provide this type of translation.
*
* to be safe, we will limit parallel bus accesses to a single byte
* at a time for now.
*/
static const struct regmap_config arcx_regmap_cfg = {
.reg_bits = 16,
.val_bits = 8,
.max_register = 0x7ff,
.use_single_read = true,
.use_single_write = true,
/*
* single-byte parallel bus accesses are atomic, so don't
* require any synchronization.
*/
.disable_locking = true,
};
static struct regmap *create_parallel_regmap(struct platform_device *pdev,
int idx)
{
void __iomem *base;
struct device *dev = &pdev->dev;
base = devm_platform_ioremap_resource(pdev, idx + 1);
if (IS_ERR(base))
return ERR_CAST(base);
return devm_regmap_init_mmio(dev, base, &arcx_regmap_cfg);
}
static struct anybuss_host *
create_anybus_host(struct platform_device *pdev, int idx)
{
struct anybuss_ops ops = {};
switch (idx) {
case 0:
ops.reset = export_reset_0;
break;
case 1:
ops.reset = export_reset_1;
break;
default:
return ERR_PTR(-EINVAL);
}
ops.host_idx = idx;
ops.regmap = create_parallel_regmap(pdev, idx);
if (IS_ERR(ops.regmap))
return ERR_CAST(ops.regmap);
ops.irq = platform_get_irq(pdev, idx);
if (ops.irq < 0)
return ERR_PTR(ops.irq);
return devm_anybuss_host_common_probe(&pdev->dev, &ops);
}
static ssize_t version_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct controller_priv *cd = dev_get_drvdata(dev);
return sprintf(buf, "%s\n", cd->version);
}
static DEVICE_ATTR_RO(version);
static ssize_t design_number_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct controller_priv *cd = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", cd->design_no);
}
static DEVICE_ATTR_RO(design_number);
static struct attribute *controller_attributes[] = {
&dev_attr_version.attr,
&dev_attr_design_number.attr,
NULL,
};
static const struct attribute_group controller_attribute_group = {
.attrs = controller_attributes,
};
static const struct attribute_group *controller_attribute_groups[] = {
&controller_attribute_group,
NULL,
};
static void controller_device_release(struct device *dev)
{
kfree(dev);
}
static int can_power_is_enabled(struct regulator_dev *rdev)
{
struct controller_priv *cd = rdev_get_drvdata(rdev);
return !(readb(cd->cpld_base + CPLD_STATUS1) & CPLD_STATUS1_CAN_POWER);
}
static const struct regulator_ops can_power_ops = {
.is_enabled = can_power_is_enabled,
};
static const struct regulator_desc can_power_desc = {
.name = "regulator-can-power",
.id = -1,
.type = REGULATOR_VOLTAGE,
.owner = THIS_MODULE,
.ops = &can_power_ops,
};
static struct class *controller_class;
static DEFINE_IDA(controller_index_ida);
static int controller_probe(struct platform_device *pdev)
{
struct controller_priv *cd;
struct device *dev = &pdev->dev;
struct regulator_config config = { };
struct regulator_dev *regulator;
int err, id;
struct anybuss_host *host;
u8 status1, cap;
cd = devm_kzalloc(dev, sizeof(*cd), GFP_KERNEL);
if (!cd)
return -ENOMEM;
dev_set_drvdata(dev, cd);
mutex_init(&cd->ctrl_lock);
cd->reset_gpiod = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(cd->reset_gpiod))
return PTR_ERR(cd->reset_gpiod);
/* CPLD control memory, sits at index 0 */
cd->cpld_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(cd->cpld_base)) {
dev_err(dev,
"failed to map cpld base address\n");
err = PTR_ERR(cd->cpld_base);
goto out_reset;
}
/* identify cpld */
status1 = readb(cd->cpld_base + CPLD_STATUS1);
cd->design_no = (readb(cd->cpld_base + CPLD_DESIGN_HI) << 8) |
readb(cd->cpld_base + CPLD_DESIGN_LO);
snprintf(cd->version, sizeof(cd->version), "%c%d",
'A' + ((status1 >> 5) & 0x7),
(status1 >> 2) & 0x7);
dev_info(dev, "design number %d, revision %s\n",
cd->design_no,
cd->version);
cap = readb(cd->cpld_base + CPLD_CAP);
if (!(cap & CPLD_CAP_COMPAT)) {
dev_err(dev, "unsupported controller [cap=0x%02X]", cap);
err = -ENODEV;
goto out_reset;
}
if (status1 & CPLD_STATUS1_AB) {
dev_info(dev, "has anybus-S slot(s)");
cd->common_reset = !(cap & CPLD_CAP_SEP_RESETS);
dev_info(dev, "supports %s", cd->common_reset ?
"a common reset" : "separate resets");
for (id = 0; id < 2; id++) {
host = create_anybus_host(pdev, id);
if (!IS_ERR(host))
continue;
err = PTR_ERR(host);
/* -ENODEV is fine, it just means no card detected */
if (err != -ENODEV)
goto out_reset;
}
}
id = ida_simple_get(&controller_index_ida, 0, 0, GFP_KERNEL);
if (id < 0) {
err = id;
goto out_reset;
}
/* export can power readout as a regulator */
config.dev = dev;
config.driver_data = cd;
regulator = devm_regulator_register(dev, &can_power_desc, &config);
if (IS_ERR(regulator)) {
err = PTR_ERR(regulator);
goto out_ida;
}
/* make controller info visible to userspace */
cd->class_dev = kzalloc(sizeof(*cd->class_dev), GFP_KERNEL);
if (!cd->class_dev) {
err = -ENOMEM;
goto out_ida;
}
cd->class_dev->class = controller_class;
cd->class_dev->groups = controller_attribute_groups;
cd->class_dev->parent = dev;
cd->class_dev->id = id;
cd->class_dev->release = controller_device_release;
dev_set_name(cd->class_dev, "%d", cd->class_dev->id);
dev_set_drvdata(cd->class_dev, cd);
err = device_register(cd->class_dev);
if (err)
goto out_dev;
return 0;
out_dev:
put_device(cd->class_dev);
out_ida:
ida_simple_remove(&controller_index_ida, id);
out_reset:
gpiod_set_value_cansleep(cd->reset_gpiod, 1);
return err;
}
static void controller_remove(struct platform_device *pdev)
{
struct controller_priv *cd = platform_get_drvdata(pdev);
int id = cd->class_dev->id;
device_unregister(cd->class_dev);
ida_simple_remove(&controller_index_ida, id);
gpiod_set_value_cansleep(cd->reset_gpiod, 1);
}
static const struct of_device_id controller_of_match[] = {
{ .compatible = "arcx,anybus-controller" },
{ }
};
MODULE_DEVICE_TABLE(of, controller_of_match);
static struct platform_driver controller_driver = {
.probe = controller_probe,
.remove_new = controller_remove,
.driver = {
.name = "arcx-anybus-controller",
.of_match_table = controller_of_match,
},
};
static int __init controller_init(void)
{
int err;
controller_class = class_create("arcx_anybus_controller");
if (IS_ERR(controller_class))
return PTR_ERR(controller_class);
err = platform_driver_register(&controller_driver);
if (err)
class_destroy(controller_class);
return err;
}
static void __exit controller_exit(void)
{
platform_driver_unregister(&controller_driver);
class_destroy(controller_class);
ida_destroy(&controller_index_ida);
}
module_init(controller_init);
module_exit(controller_exit);
MODULE_DESCRIPTION("Arcx Anybus-S Controller driver");
MODULE_AUTHOR("Sven Van Asbroeck <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/staging/fieldbus/anybuss/arcx-anybus.c |
// SPDX-License-Identifier: GPL-2.0
/*
* dim2.c - MediaLB DIM2 Hardware Dependent Module
*
* Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/printk.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <linux/kthread.h>
#include <linux/most.h>
#include <linux/of.h>
#include "hal.h"
#include "errors.h"
#include "sysfs.h"
#define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */
#define MAX_BUFFERS_PACKET 32
#define MAX_BUFFERS_STREAMING 32
#define MAX_BUF_SIZE_PACKET 2048
#define MAX_BUF_SIZE_STREAMING (8 * 1024)
/*
* The parameter representing the number of frames per sub-buffer for
* synchronous channels. Valid values: [0 .. 6].
*
* The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per
* sub-buffer 1, 2, 4, 8, 16, 32, 64.
*/
static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */
module_param(fcnt, byte, 0000);
MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2");
static DEFINE_SPINLOCK(dim_lock);
/**
* struct hdm_channel - private structure to keep channel specific data
* @name: channel name
* @is_initialized: identifier to know whether the channel is initialized
* @ch: HAL specific channel data
* @reset_dbr_size: reset DBR data buffer size
* @pending_list: list to keep MBO's before starting transfer
* @started_list: list to keep MBO's after starting transfer
* @direction: channel direction (TX or RX)
* @data_type: channel data type
*/
struct hdm_channel {
char name[sizeof "caNNN"];
bool is_initialized;
struct dim_channel ch;
u16 *reset_dbr_size;
struct list_head pending_list; /* before dim_enqueue_buffer() */
struct list_head started_list; /* after dim_enqueue_buffer() */
enum most_channel_direction direction;
enum most_channel_data_type data_type;
};
/*
* struct dim2_hdm - private structure to keep interface specific data
* @hch: an array of channel specific data
* @most_iface: most interface structure
* @capabilities: an array of channel capability data
* @io_base: I/O register base address
* @netinfo_task: thread to deliver network status
* @netinfo_waitq: waitq for the thread to sleep
* @deliver_netinfo: to identify whether network status received
* @mac_addrs: INIC mac address
* @link_state: network link state
* @atx_idx: index of async tx channel
*/
struct dim2_hdm {
struct device dev;
struct hdm_channel hch[DMA_CHANNELS];
struct most_channel_capability capabilities[DMA_CHANNELS];
struct most_interface most_iface;
char name[16 + sizeof "dim2-"];
void __iomem *io_base;
u8 clk_speed;
struct clk *clk;
struct clk *clk_pll;
struct task_struct *netinfo_task;
wait_queue_head_t netinfo_waitq;
int deliver_netinfo;
unsigned char mac_addrs[6];
unsigned char link_state;
int atx_idx;
struct medialb_bus bus;
void (*on_netinfo)(struct most_interface *most_iface,
unsigned char link_state, unsigned char *addrs);
void (*disable_platform)(struct platform_device *pdev);
};
struct dim2_platform_data {
int (*enable)(struct platform_device *pdev);
void (*disable)(struct platform_device *pdev);
u8 fcnt;
};
static inline struct dim2_hdm *iface_to_hdm(struct most_interface *iface)
{
return container_of(iface, struct dim2_hdm, most_iface);
}
/* Macro to identify a network status message */
#define PACKET_IS_NET_INFO(p) \
(((p)[1] == 0x18) && ((p)[2] == 0x05) && ((p)[3] == 0x0C) && \
((p)[13] == 0x3C) && ((p)[14] == 0x00) && ((p)[15] == 0x0A))
static ssize_t state_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
bool state;
unsigned long flags;
spin_lock_irqsave(&dim_lock, flags);
state = dim_get_lock_state();
spin_unlock_irqrestore(&dim_lock, flags);
return sysfs_emit(buf, "%s\n", state ? "locked" : "");
}
static DEVICE_ATTR_RO(state);
static struct attribute *dim2_attrs[] = {
&dev_attr_state.attr,
NULL,
};
ATTRIBUTE_GROUPS(dim2);
/**
* dimcb_on_error - callback from HAL to report miscommunication between
* HDM and HAL
* @error_id: Error ID
* @error_message: Error message. Some text in a free format
*/
void dimcb_on_error(u8 error_id, const char *error_message)
{
pr_err("%s: error_id - %d, error_message - %s\n", __func__, error_id,
error_message);
}
/**
* try_start_dim_transfer - try to transfer a buffer on a channel
* @hdm_ch: channel specific data
*
* Transfer a buffer from pending_list if the channel is ready
*/
static int try_start_dim_transfer(struct hdm_channel *hdm_ch)
{
u16 buf_size;
struct list_head *head = &hdm_ch->pending_list;
struct mbo *mbo;
unsigned long flags;
struct dim_ch_state st;
BUG_ON(!hdm_ch);
BUG_ON(!hdm_ch->is_initialized);
spin_lock_irqsave(&dim_lock, flags);
if (list_empty(head)) {
spin_unlock_irqrestore(&dim_lock, flags);
return -EAGAIN;
}
if (!dim_get_channel_state(&hdm_ch->ch, &st)->ready) {
spin_unlock_irqrestore(&dim_lock, flags);
return -EAGAIN;
}
mbo = list_first_entry(head, struct mbo, list);
buf_size = mbo->buffer_length;
if (dim_dbr_space(&hdm_ch->ch) < buf_size) {
spin_unlock_irqrestore(&dim_lock, flags);
return -EAGAIN;
}
BUG_ON(mbo->bus_address == 0);
if (!dim_enqueue_buffer(&hdm_ch->ch, mbo->bus_address, buf_size)) {
list_del(head->next);
spin_unlock_irqrestore(&dim_lock, flags);
mbo->processed_length = 0;
mbo->status = MBO_E_INVAL;
mbo->complete(mbo);
return -EFAULT;
}
list_move_tail(head->next, &hdm_ch->started_list);
spin_unlock_irqrestore(&dim_lock, flags);
return 0;
}
/**
* deliver_netinfo_thread - thread to deliver network status to mostcore
* @data: private data
*
* Wait for network status and deliver it to mostcore once it is received
*/
static int deliver_netinfo_thread(void *data)
{
struct dim2_hdm *dev = data;
while (!kthread_should_stop()) {
wait_event_interruptible(dev->netinfo_waitq,
dev->deliver_netinfo ||
kthread_should_stop());
if (dev->deliver_netinfo) {
dev->deliver_netinfo--;
if (dev->on_netinfo) {
dev->on_netinfo(&dev->most_iface,
dev->link_state,
dev->mac_addrs);
}
}
}
return 0;
}
/**
* retrieve_netinfo - retrieve network status from received buffer
* @dev: private data
* @mbo: received MBO
*
* Parse the message in buffer and get node address, link state, MAC address.
* Wake up a thread to deliver this status to mostcore
*/
static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo)
{
u8 *data = mbo->virt_address;
pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]);
dev->link_state = data[18];
pr_info("NIState: %d\n", dev->link_state);
memcpy(dev->mac_addrs, data + 19, 6);
dev->deliver_netinfo++;
wake_up_interruptible(&dev->netinfo_waitq);
}
/**
* service_done_flag - handle completed buffers
* @dev: private data
* @ch_idx: channel index
*
* Return back the completed buffers to mostcore, using completion callback
*/
static void service_done_flag(struct dim2_hdm *dev, int ch_idx)
{
struct hdm_channel *hdm_ch = dev->hch + ch_idx;
struct dim_ch_state st;
struct list_head *head;
struct mbo *mbo;
int done_buffers;
unsigned long flags;
u8 *data;
BUG_ON(!hdm_ch);
BUG_ON(!hdm_ch->is_initialized);
spin_lock_irqsave(&dim_lock, flags);
done_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers;
if (!done_buffers) {
spin_unlock_irqrestore(&dim_lock, flags);
return;
}
if (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) {
spin_unlock_irqrestore(&dim_lock, flags);
return;
}
spin_unlock_irqrestore(&dim_lock, flags);
head = &hdm_ch->started_list;
while (done_buffers) {
spin_lock_irqsave(&dim_lock, flags);
if (list_empty(head)) {
spin_unlock_irqrestore(&dim_lock, flags);
pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n");
break;
}
mbo = list_first_entry(head, struct mbo, list);
list_del(head->next);
spin_unlock_irqrestore(&dim_lock, flags);
data = mbo->virt_address;
if (hdm_ch->data_type == MOST_CH_ASYNC &&
hdm_ch->direction == MOST_CH_RX &&
PACKET_IS_NET_INFO(data)) {
retrieve_netinfo(dev, mbo);
spin_lock_irqsave(&dim_lock, flags);
list_add_tail(&mbo->list, &hdm_ch->pending_list);
spin_unlock_irqrestore(&dim_lock, flags);
} else {
if (hdm_ch->data_type == MOST_CH_CONTROL ||
hdm_ch->data_type == MOST_CH_ASYNC) {
u32 const data_size =
(u32)data[0] * 256 + data[1] + 2;
mbo->processed_length =
min_t(u32, data_size,
mbo->buffer_length);
} else {
mbo->processed_length = mbo->buffer_length;
}
mbo->status = MBO_SUCCESS;
mbo->complete(mbo);
}
done_buffers--;
}
}
static struct dim_channel **get_active_channels(struct dim2_hdm *dev,
struct dim_channel **buffer)
{
int idx = 0;
int ch_idx;
for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
if (dev->hch[ch_idx].is_initialized)
buffer[idx++] = &dev->hch[ch_idx].ch;
}
buffer[idx++] = NULL;
return buffer;
}
static irqreturn_t dim2_mlb_isr(int irq, void *_dev)
{
struct dim2_hdm *dev = _dev;
unsigned long flags;
spin_lock_irqsave(&dim_lock, flags);
dim_service_mlb_int_irq();
spin_unlock_irqrestore(&dim_lock, flags);
if (dev->atx_idx >= 0 && dev->hch[dev->atx_idx].is_initialized)
while (!try_start_dim_transfer(dev->hch + dev->atx_idx))
continue;
return IRQ_HANDLED;
}
static irqreturn_t dim2_task_irq(int irq, void *_dev)
{
struct dim2_hdm *dev = _dev;
unsigned long flags;
int ch_idx;
for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
if (!dev->hch[ch_idx].is_initialized)
continue;
spin_lock_irqsave(&dim_lock, flags);
dim_service_channel(&dev->hch[ch_idx].ch);
spin_unlock_irqrestore(&dim_lock, flags);
service_done_flag(dev, ch_idx);
while (!try_start_dim_transfer(dev->hch + ch_idx))
continue;
}
return IRQ_HANDLED;
}
/**
* dim2_ahb_isr - interrupt service routine
* @irq: irq number
* @_dev: private data
*
* Acknowledge the interrupt and service each initialized channel,
* if needed, in task context.
*/
static irqreturn_t dim2_ahb_isr(int irq, void *_dev)
{
struct dim2_hdm *dev = _dev;
struct dim_channel *buffer[DMA_CHANNELS + 1];
unsigned long flags;
spin_lock_irqsave(&dim_lock, flags);
dim_service_ahb_int_irq(get_active_channels(dev, buffer));
spin_unlock_irqrestore(&dim_lock, flags);
return IRQ_WAKE_THREAD;
}
/**
* complete_all_mbos - complete MBO's in a list
* @head: list head
*
* Delete all the entries in list and return back MBO's to mostcore using
* completion call back.
*/
static void complete_all_mbos(struct list_head *head)
{
unsigned long flags;
struct mbo *mbo;
for (;;) {
spin_lock_irqsave(&dim_lock, flags);
if (list_empty(head)) {
spin_unlock_irqrestore(&dim_lock, flags);
break;
}
mbo = list_first_entry(head, struct mbo, list);
list_del(head->next);
spin_unlock_irqrestore(&dim_lock, flags);
mbo->processed_length = 0;
mbo->status = MBO_E_CLOSE;
mbo->complete(mbo);
}
}
/**
* configure_channel - initialize a channel
* @most_iface: interface the channel belongs to
* @ch_idx: channel index to be configured
* @ccfg: structure that holds the configuration information
*
* Receives configuration information from mostcore and initialize
* the corresponding channel. Return 0 on success, negative on failure.
*/
static int configure_channel(struct most_interface *most_iface, int ch_idx,
struct most_channel_config *ccfg)
{
struct dim2_hdm *dev = iface_to_hdm(most_iface);
bool const is_tx = ccfg->direction == MOST_CH_TX;
u16 const sub_size = ccfg->subbuffer_size;
u16 const buf_size = ccfg->buffer_size;
u16 new_size;
unsigned long flags;
u8 hal_ret;
int const ch_addr = ch_idx * 2 + 2;
struct hdm_channel *const hdm_ch = dev->hch + ch_idx;
BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
if (hdm_ch->is_initialized)
return -EPERM;
/* do not reset if the property was set by user, see poison_channel */
hdm_ch->reset_dbr_size = ccfg->dbr_size ? NULL : &ccfg->dbr_size;
/* zero value is default dbr_size, see dim2 hal */
hdm_ch->ch.dbr_size = ccfg->dbr_size;
switch (ccfg->data_type) {
case MOST_CH_CONTROL:
new_size = dim_norm_ctrl_async_buffer_size(buf_size);
if (new_size == 0) {
pr_err("%s: too small buffer size\n", hdm_ch->name);
return -EINVAL;
}
ccfg->buffer_size = new_size;
if (new_size != buf_size)
pr_warn("%s: fixed buffer size (%d -> %d)\n",
hdm_ch->name, buf_size, new_size);
spin_lock_irqsave(&dim_lock, flags);
hal_ret = dim_init_control(&hdm_ch->ch, is_tx, ch_addr,
is_tx ? new_size * 2 : new_size);
break;
case MOST_CH_ASYNC:
new_size = dim_norm_ctrl_async_buffer_size(buf_size);
if (new_size == 0) {
pr_err("%s: too small buffer size\n", hdm_ch->name);
return -EINVAL;
}
ccfg->buffer_size = new_size;
if (new_size != buf_size)
pr_warn("%s: fixed buffer size (%d -> %d)\n",
hdm_ch->name, buf_size, new_size);
spin_lock_irqsave(&dim_lock, flags);
hal_ret = dim_init_async(&hdm_ch->ch, is_tx, ch_addr,
is_tx ? new_size * 2 : new_size);
break;
case MOST_CH_ISOC:
new_size = dim_norm_isoc_buffer_size(buf_size, sub_size);
if (new_size == 0) {
pr_err("%s: invalid sub-buffer size or too small buffer size\n",
hdm_ch->name);
return -EINVAL;
}
ccfg->buffer_size = new_size;
if (new_size != buf_size)
pr_warn("%s: fixed buffer size (%d -> %d)\n",
hdm_ch->name, buf_size, new_size);
spin_lock_irqsave(&dim_lock, flags);
hal_ret = dim_init_isoc(&hdm_ch->ch, is_tx, ch_addr, sub_size);
break;
case MOST_CH_SYNC:
new_size = dim_norm_sync_buffer_size(buf_size, sub_size);
if (new_size == 0) {
pr_err("%s: invalid sub-buffer size or too small buffer size\n",
hdm_ch->name);
return -EINVAL;
}
ccfg->buffer_size = new_size;
if (new_size != buf_size)
pr_warn("%s: fixed buffer size (%d -> %d)\n",
hdm_ch->name, buf_size, new_size);
spin_lock_irqsave(&dim_lock, flags);
hal_ret = dim_init_sync(&hdm_ch->ch, is_tx, ch_addr, sub_size);
break;
default:
pr_err("%s: configure failed, bad channel type: %d\n",
hdm_ch->name, ccfg->data_type);
return -EINVAL;
}
if (hal_ret != DIM_NO_ERROR) {
spin_unlock_irqrestore(&dim_lock, flags);
pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n",
hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx);
return -ENODEV;
}
hdm_ch->data_type = ccfg->data_type;
hdm_ch->direction = ccfg->direction;
hdm_ch->is_initialized = true;
if (hdm_ch->data_type == MOST_CH_ASYNC &&
hdm_ch->direction == MOST_CH_TX &&
dev->atx_idx < 0)
dev->atx_idx = ch_idx;
spin_unlock_irqrestore(&dim_lock, flags);
ccfg->dbr_size = hdm_ch->ch.dbr_size;
return 0;
}
/**
* enqueue - enqueue a buffer for data transfer
* @most_iface: intended interface
* @ch_idx: ID of the channel the buffer is intended for
* @mbo: pointer to the buffer object
*
* Push the buffer into pending_list and try to transfer one buffer from
* pending_list. Return 0 on success, negative on failure.
*/
static int enqueue(struct most_interface *most_iface, int ch_idx,
struct mbo *mbo)
{
struct dim2_hdm *dev = iface_to_hdm(most_iface);
struct hdm_channel *hdm_ch = dev->hch + ch_idx;
unsigned long flags;
BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
if (!hdm_ch->is_initialized)
return -EPERM;
if (mbo->bus_address == 0)
return -EFAULT;
spin_lock_irqsave(&dim_lock, flags);
list_add_tail(&mbo->list, &hdm_ch->pending_list);
spin_unlock_irqrestore(&dim_lock, flags);
(void)try_start_dim_transfer(hdm_ch);
return 0;
}
/**
* request_netinfo - triggers retrieving of network info
* @most_iface: pointer to the interface
* @ch_idx: corresponding channel ID
* @on_netinfo: call-back used to deliver network status to mostcore
*
* Send a command to INIC which triggers retrieving of network info by means of
* "Message exchange over MDP/MEP". Return 0 on success, negative on failure.
*/
static void request_netinfo(struct most_interface *most_iface, int ch_idx,
void (*on_netinfo)(struct most_interface *,
unsigned char, unsigned char *))
{
struct dim2_hdm *dev = iface_to_hdm(most_iface);
struct mbo *mbo;
u8 *data;
dev->on_netinfo = on_netinfo;
if (!on_netinfo)
return;
if (dev->atx_idx < 0) {
pr_err("Async Tx Not initialized\n");
return;
}
mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL);
if (!mbo)
return;
mbo->buffer_length = 5;
data = mbo->virt_address;
data[0] = 0x00; /* PML High byte */
data[1] = 0x03; /* PML Low byte */
data[2] = 0x02; /* PMHL */
data[3] = 0x08; /* FPH */
data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */
most_submit_mbo(mbo);
}
/**
* poison_channel - poison buffers of a channel
* @most_iface: pointer to the interface the channel to be poisoned belongs to
* @ch_idx: corresponding channel ID
*
* Destroy a channel and complete all the buffers in both started_list &
* pending_list. Return 0 on success, negative on failure.
*/
static int poison_channel(struct most_interface *most_iface, int ch_idx)
{
struct dim2_hdm *dev = iface_to_hdm(most_iface);
struct hdm_channel *hdm_ch = dev->hch + ch_idx;
unsigned long flags;
u8 hal_ret;
int ret = 0;
BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
if (!hdm_ch->is_initialized)
return -EPERM;
spin_lock_irqsave(&dim_lock, flags);
hal_ret = dim_destroy_channel(&hdm_ch->ch);
hdm_ch->is_initialized = false;
if (ch_idx == dev->atx_idx)
dev->atx_idx = -1;
spin_unlock_irqrestore(&dim_lock, flags);
if (hal_ret != DIM_NO_ERROR) {
pr_err("HAL Failed to close channel %s\n", hdm_ch->name);
ret = -EFAULT;
}
complete_all_mbos(&hdm_ch->started_list);
complete_all_mbos(&hdm_ch->pending_list);
if (hdm_ch->reset_dbr_size)
*hdm_ch->reset_dbr_size = 0;
return ret;
}
static void *dma_alloc(struct mbo *mbo, u32 size)
{
struct device *dev = mbo->ifp->driver_dev;
return dma_alloc_coherent(dev, size, &mbo->bus_address, GFP_KERNEL);
}
static void dma_free(struct mbo *mbo, u32 size)
{
struct device *dev = mbo->ifp->driver_dev;
dma_free_coherent(dev, size, mbo->virt_address, mbo->bus_address);
}
static const struct of_device_id dim2_of_match[];
static struct {
const char *clock_speed;
u8 clk_speed;
} clk_mt[] = {
{ "256fs", CLK_256FS },
{ "512fs", CLK_512FS },
{ "1024fs", CLK_1024FS },
{ "2048fs", CLK_2048FS },
{ "3072fs", CLK_3072FS },
{ "4096fs", CLK_4096FS },
{ "6144fs", CLK_6144FS },
{ "8192fs", CLK_8192FS },
};
/**
* get_dim2_clk_speed - converts string to DIM2 clock speed value
*
* @clock_speed: string in the format "{NUMBER}fs"
* @val: pointer to get one of the CLK_{NUMBER}FS values
*
* By success stores one of the CLK_{NUMBER}FS in the *val and returns 0,
* otherwise returns -EINVAL.
*/
static int get_dim2_clk_speed(const char *clock_speed, u8 *val)
{
int i;
for (i = 0; i < ARRAY_SIZE(clk_mt); i++) {
if (!strcmp(clock_speed, clk_mt[i].clock_speed)) {
*val = clk_mt[i].clk_speed;
return 0;
}
}
return -EINVAL;
}
static void dim2_release(struct device *d)
{
struct dim2_hdm *dev = container_of(d, struct dim2_hdm, dev);
unsigned long flags;
kthread_stop(dev->netinfo_task);
spin_lock_irqsave(&dim_lock, flags);
dim_shutdown();
spin_unlock_irqrestore(&dim_lock, flags);
if (dev->disable_platform)
dev->disable_platform(to_platform_device(d->parent));
kfree(dev);
}
/*
* dim2_probe - dim2 probe handler
* @pdev: platform device structure
*
* Register the dim2 interface with mostcore and initialize it.
* Return 0 on success, negative on failure.
*/
static int dim2_probe(struct platform_device *pdev)
{
const struct dim2_platform_data *pdata;
const struct of_device_id *of_id;
const char *clock_speed;
struct dim2_hdm *dev;
struct resource *res;
int ret, i;
u8 hal_ret;
u8 dev_fcnt = fcnt;
int irq;
enum { MLB_INT_IDX, AHB0_INT_IDX };
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
dev->atx_idx = -1;
platform_set_drvdata(pdev, dev);
ret = of_property_read_string(pdev->dev.of_node,
"microchip,clock-speed", &clock_speed);
if (ret) {
dev_err(&pdev->dev, "missing dt property clock-speed\n");
goto err_free_dev;
}
ret = get_dim2_clk_speed(clock_speed, &dev->clk_speed);
if (ret) {
dev_err(&pdev->dev, "bad dt property clock-speed\n");
goto err_free_dev;
}
dev->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(dev->io_base)) {
ret = PTR_ERR(dev->io_base);
goto err_free_dev;
}
of_id = of_match_node(dim2_of_match, pdev->dev.of_node);
pdata = of_id->data;
if (pdata) {
if (pdata->enable) {
ret = pdata->enable(pdev);
if (ret)
goto err_free_dev;
}
dev->disable_platform = pdata->disable;
if (pdata->fcnt)
dev_fcnt = pdata->fcnt;
}
dev_info(&pdev->dev, "sync: num of frames per sub-buffer: %u\n",
dev_fcnt);
hal_ret = dim_startup(dev->io_base, dev->clk_speed, dev_fcnt);
if (hal_ret != DIM_NO_ERROR) {
dev_err(&pdev->dev, "dim_startup failed: %d\n", hal_ret);
ret = -ENODEV;
goto err_disable_platform;
}
irq = platform_get_irq(pdev, AHB0_INT_IDX);
if (irq < 0) {
ret = irq;
goto err_shutdown_dim;
}
ret = devm_request_threaded_irq(&pdev->dev, irq, dim2_ahb_isr,
dim2_task_irq, 0, "dim2_ahb0_int", dev);
if (ret) {
dev_err(&pdev->dev, "failed to request ahb0_int irq %d\n", irq);
goto err_shutdown_dim;
}
irq = platform_get_irq(pdev, MLB_INT_IDX);
if (irq < 0) {
ret = irq;
goto err_shutdown_dim;
}
ret = devm_request_irq(&pdev->dev, irq, dim2_mlb_isr, 0,
"dim2_mlb_int", dev);
if (ret) {
dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq);
goto err_shutdown_dim;
}
init_waitqueue_head(&dev->netinfo_waitq);
dev->deliver_netinfo = 0;
dev->netinfo_task = kthread_run(&deliver_netinfo_thread, dev,
"dim2_netinfo");
if (IS_ERR(dev->netinfo_task)) {
ret = PTR_ERR(dev->netinfo_task);
goto err_shutdown_dim;
}
for (i = 0; i < DMA_CHANNELS; i++) {
struct most_channel_capability *cap = dev->capabilities + i;
struct hdm_channel *hdm_ch = dev->hch + i;
INIT_LIST_HEAD(&hdm_ch->pending_list);
INIT_LIST_HEAD(&hdm_ch->started_list);
hdm_ch->is_initialized = false;
snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2);
cap->name_suffix = hdm_ch->name;
cap->direction = MOST_CH_RX | MOST_CH_TX;
cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC |
MOST_CH_ISOC | MOST_CH_SYNC;
cap->num_buffers_packet = MAX_BUFFERS_PACKET;
cap->buffer_size_packet = MAX_BUF_SIZE_PACKET;
cap->num_buffers_streaming = MAX_BUFFERS_STREAMING;
cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING;
}
{
const char *fmt;
if (sizeof(res->start) == sizeof(long long))
fmt = "dim2-%016llx";
else if (sizeof(res->start) == sizeof(long))
fmt = "dim2-%016lx";
else
fmt = "dim2-%016x";
snprintf(dev->name, sizeof(dev->name), fmt, res->start);
}
dev->most_iface.interface = ITYPE_MEDIALB_DIM2;
dev->most_iface.description = dev->name;
dev->most_iface.num_channels = DMA_CHANNELS;
dev->most_iface.channel_vector = dev->capabilities;
dev->most_iface.configure = configure_channel;
dev->most_iface.enqueue = enqueue;
dev->most_iface.dma_alloc = dma_alloc;
dev->most_iface.dma_free = dma_free;
dev->most_iface.poison_channel = poison_channel;
dev->most_iface.request_netinfo = request_netinfo;
dev->most_iface.driver_dev = &pdev->dev;
dev->most_iface.dev = &dev->dev;
dev->dev.init_name = dev->name;
dev->dev.parent = &pdev->dev;
dev->dev.release = dim2_release;
return most_register_interface(&dev->most_iface);
err_shutdown_dim:
dim_shutdown();
err_disable_platform:
if (dev->disable_platform)
dev->disable_platform(pdev);
err_free_dev:
kfree(dev);
return ret;
}
/**
* dim2_remove - dim2 remove handler
* @pdev: platform device structure
*
* Unregister the interface from mostcore
*/
static void dim2_remove(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
most_deregister_interface(&dev->most_iface);
}
/* platform specific functions [[ */
static int fsl_mx6_enable(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
int ret;
dev->clk = devm_clk_get(&pdev->dev, "mlb");
if (IS_ERR_OR_NULL(dev->clk)) {
dev_err(&pdev->dev, "unable to get mlb clock\n");
return -EFAULT;
}
ret = clk_prepare_enable(dev->clk);
if (ret) {
dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
return ret;
}
if (dev->clk_speed >= CLK_2048FS) {
/* enable pll */
dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb");
if (IS_ERR_OR_NULL(dev->clk_pll)) {
dev_err(&pdev->dev, "unable to get mlb pll clock\n");
clk_disable_unprepare(dev->clk);
return -EFAULT;
}
writel(0x888, dev->io_base + 0x38);
clk_prepare_enable(dev->clk_pll);
}
return 0;
}
static void fsl_mx6_disable(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
if (dev->clk_speed >= CLK_2048FS)
clk_disable_unprepare(dev->clk_pll);
clk_disable_unprepare(dev->clk);
}
static int rcar_gen2_enable(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
int ret;
dev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "cannot get clock\n");
return PTR_ERR(dev->clk);
}
ret = clk_prepare_enable(dev->clk);
if (ret) {
dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
return ret;
}
if (dev->clk_speed >= CLK_2048FS) {
/* enable MLP pll and LVDS drivers */
writel(0x03, dev->io_base + 0x600);
/* set bias */
writel(0x888, dev->io_base + 0x38);
} else {
/* PLL */
writel(0x04, dev->io_base + 0x600);
}
/* BBCR = 0b11 */
writel(0x03, dev->io_base + 0x500);
writel(0x0002FF02, dev->io_base + 0x508);
return 0;
}
static void rcar_gen2_disable(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
clk_disable_unprepare(dev->clk);
/* disable PLLs and LVDS drivers */
writel(0x0, dev->io_base + 0x600);
}
static int rcar_gen3_enable(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
u32 enable_512fs = dev->clk_speed == CLK_512FS;
int ret;
dev->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "cannot get clock\n");
return PTR_ERR(dev->clk);
}
ret = clk_prepare_enable(dev->clk);
if (ret) {
dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
return ret;
}
/* PLL */
writel(0x04, dev->io_base + 0x600);
writel(enable_512fs, dev->io_base + 0x604);
/* BBCR = 0b11 */
writel(0x03, dev->io_base + 0x500);
writel(0x0002FF02, dev->io_base + 0x508);
return 0;
}
static void rcar_gen3_disable(struct platform_device *pdev)
{
struct dim2_hdm *dev = platform_get_drvdata(pdev);
clk_disable_unprepare(dev->clk);
/* disable PLLs and LVDS drivers */
writel(0x0, dev->io_base + 0x600);
}
/* ]] platform specific functions */
enum dim2_platforms { FSL_MX6, RCAR_GEN2, RCAR_GEN3 };
static struct dim2_platform_data plat_data[] = {
[FSL_MX6] = {
.enable = fsl_mx6_enable,
.disable = fsl_mx6_disable,
},
[RCAR_GEN2] = {
.enable = rcar_gen2_enable,
.disable = rcar_gen2_disable,
},
[RCAR_GEN3] = {
.enable = rcar_gen3_enable,
.disable = rcar_gen3_disable,
.fcnt = 3,
},
};
static const struct of_device_id dim2_of_match[] = {
{
.compatible = "fsl,imx6q-mlb150",
.data = plat_data + FSL_MX6
},
{
.compatible = "renesas,mlp",
.data = plat_data + RCAR_GEN2
},
{
.compatible = "renesas,rcar-gen3-mlp",
.data = plat_data + RCAR_GEN3
},
{
.compatible = "xlnx,axi4-os62420_3pin-1.00.a",
},
{
.compatible = "xlnx,axi4-os62420_6pin-1.00.a",
},
{},
};
MODULE_DEVICE_TABLE(of, dim2_of_match);
static struct platform_driver dim2_driver = {
.probe = dim2_probe,
.remove_new = dim2_remove,
.driver = {
.name = "hdm_dim2",
.of_match_table = dim2_of_match,
.dev_groups = dim2_groups,
},
};
module_platform_driver(dim2_driver);
MODULE_AUTHOR("Andrey Shvetsov <[email protected]>");
MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module");
MODULE_LICENSE("GPL");
| linux-master | drivers/staging/most/dim2/dim2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* hal.c - DIM2 HAL implementation
* (MediaLB, Device Interface Macro IP, OS62420)
*
* Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
*/
/* Author: Andrey Shvetsov <[email protected]> */
#include "hal.h"
#include "errors.h"
#include "reg.h"
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/io.h>
/*
* Size factor for isochronous DBR buffer.
* Minimal value is 3.
*/
#define ISOC_DBR_FACTOR 3u
/*
* Number of 32-bit units for DBR map.
*
* 1: block size is 512, max allocation is 16K
* 2: block size is 256, max allocation is 8K
* 4: block size is 128, max allocation is 4K
* 8: block size is 64, max allocation is 2K
*
* Min allocated space is block size.
* Max possible allocated space is 32 blocks.
*/
#define DBR_MAP_SIZE 2
/* -------------------------------------------------------------------------- */
/* not configurable area */
#define CDT 0x00
#define ADT 0x40
#define MLB_CAT 0x80
#define AHB_CAT 0x88
#define DBR_SIZE (16 * 1024) /* specified by IP */
#define DBR_BLOCK_SIZE (DBR_SIZE / 32 / DBR_MAP_SIZE)
#define ROUND_UP_TO(x, d) (DIV_ROUND_UP(x, (d)) * (d))
/* -------------------------------------------------------------------------- */
/* generic helper functions and macros */
static inline u32 bit_mask(u8 position)
{
return (u32)1 << position;
}
static inline bool dim_on_error(u8 error_id, const char *error_message)
{
dimcb_on_error(error_id, error_message);
return false;
}
/* -------------------------------------------------------------------------- */
/* types and local variables */
struct async_tx_dbr {
u8 ch_addr;
u16 rpc;
u16 wpc;
u16 rest_size;
u16 sz_queue[CDT0_RPC_MASK + 1];
};
struct lld_global_vars_t {
bool dim_is_initialized;
bool mcm_is_initialized;
struct dim2_regs __iomem *dim2; /* DIM2 core base address */
struct async_tx_dbr atx_dbr;
u32 fcnt;
u32 dbr_map[DBR_MAP_SIZE];
};
static struct lld_global_vars_t g = { false };
/* -------------------------------------------------------------------------- */
static int dbr_get_mask_size(u16 size)
{
int i;
for (i = 0; i < 6; i++)
if (size <= (DBR_BLOCK_SIZE << i))
return 1 << i;
return 0;
}
/**
* alloc_dbr() - Allocates DBR memory.
* @size: Allocating memory size.
* Returns: Offset in DBR memory by success or DBR_SIZE if out of memory.
*/
static int alloc_dbr(u16 size)
{
int mask_size;
int i, block_idx = 0;
if (size <= 0)
return DBR_SIZE; /* out of memory */
mask_size = dbr_get_mask_size(size);
if (mask_size == 0)
return DBR_SIZE; /* out of memory */
for (i = 0; i < DBR_MAP_SIZE; i++) {
u32 const blocks = DIV_ROUND_UP(size, DBR_BLOCK_SIZE);
u32 mask = ~((~(u32)0) << blocks);
do {
if ((g.dbr_map[i] & mask) == 0) {
g.dbr_map[i] |= mask;
return block_idx * DBR_BLOCK_SIZE;
}
block_idx += mask_size;
/* do shift left with 2 steps in case mask_size == 32 */
mask <<= mask_size - 1;
} while ((mask <<= 1) != 0);
}
return DBR_SIZE; /* out of memory */
}
static void free_dbr(int offs, int size)
{
int block_idx = offs / DBR_BLOCK_SIZE;
u32 const blocks = DIV_ROUND_UP(size, DBR_BLOCK_SIZE);
u32 mask = ~((~(u32)0) << blocks);
mask <<= block_idx % 32;
g.dbr_map[block_idx / 32] &= ~mask;
}
/* -------------------------------------------------------------------------- */
static void dim2_transfer_madr(u32 val)
{
writel(val, &g.dim2->MADR);
/* wait for transfer completion */
while ((readl(&g.dim2->MCTL) & 1) != 1)
continue;
writel(0, &g.dim2->MCTL); /* clear transfer complete */
}
static void dim2_clear_dbr(u16 addr, u16 size)
{
enum { MADR_TB_BIT = 30, MADR_WNR_BIT = 31 };
u16 const end_addr = addr + size;
u32 const cmd = bit_mask(MADR_WNR_BIT) | bit_mask(MADR_TB_BIT);
writel(0, &g.dim2->MCTL); /* clear transfer complete */
writel(0, &g.dim2->MDAT0);
for (; addr < end_addr; addr++)
dim2_transfer_madr(cmd | addr);
}
static u32 dim2_read_ctr(u32 ctr_addr, u16 mdat_idx)
{
dim2_transfer_madr(ctr_addr);
return readl((&g.dim2->MDAT0) + mdat_idx);
}
static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value)
{
enum { MADR_WNR_BIT = 31 };
writel(0, &g.dim2->MCTL); /* clear transfer complete */
if (mask[0] != 0)
writel(value[0], &g.dim2->MDAT0);
if (mask[1] != 0)
writel(value[1], &g.dim2->MDAT1);
if (mask[2] != 0)
writel(value[2], &g.dim2->MDAT2);
if (mask[3] != 0)
writel(value[3], &g.dim2->MDAT3);
writel(mask[0], &g.dim2->MDWE0);
writel(mask[1], &g.dim2->MDWE1);
writel(mask[2], &g.dim2->MDWE2);
writel(mask[3], &g.dim2->MDWE3);
dim2_transfer_madr(bit_mask(MADR_WNR_BIT) | ctr_addr);
}
static inline void dim2_write_ctr(u32 ctr_addr, const u32 *value)
{
u32 const mask[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
dim2_write_ctr_mask(ctr_addr, mask, value);
}
static inline void dim2_clear_ctr(u32 ctr_addr)
{
u32 const value[4] = { 0, 0, 0, 0 };
dim2_write_ctr(ctr_addr, value);
}
static void dim2_configure_cat(u8 cat_base, u8 ch_addr, u8 ch_type,
bool read_not_write)
{
bool isoc_fce = ch_type == CAT_CT_VAL_ISOC;
bool sync_mfe = ch_type == CAT_CT_VAL_SYNC;
u16 const cat =
(read_not_write << CAT_RNW_BIT) |
(ch_type << CAT_CT_SHIFT) |
(ch_addr << CAT_CL_SHIFT) |
(isoc_fce << CAT_FCE_BIT) |
(sync_mfe << CAT_MFE_BIT) |
(false << CAT_MT_BIT) |
(true << CAT_CE_BIT);
u8 const ctr_addr = cat_base + ch_addr / 8;
u8 const idx = (ch_addr % 8) / 2;
u8 const shift = (ch_addr % 2) * 16;
u32 mask[4] = { 0, 0, 0, 0 };
u32 value[4] = { 0, 0, 0, 0 };
mask[idx] = (u32)0xFFFF << shift;
value[idx] = cat << shift;
dim2_write_ctr_mask(ctr_addr, mask, value);
}
static void dim2_clear_cat(u8 cat_base, u8 ch_addr)
{
u8 const ctr_addr = cat_base + ch_addr / 8;
u8 const idx = (ch_addr % 8) / 2;
u8 const shift = (ch_addr % 2) * 16;
u32 mask[4] = { 0, 0, 0, 0 };
u32 value[4] = { 0, 0, 0, 0 };
mask[idx] = (u32)0xFFFF << shift;
dim2_write_ctr_mask(ctr_addr, mask, value);
}
static void dim2_configure_cdt(u8 ch_addr, u16 dbr_address, u16 hw_buffer_size,
u16 packet_length)
{
u32 cdt[4] = { 0, 0, 0, 0 };
if (packet_length)
cdt[1] = ((packet_length - 1) << CDT1_BS_ISOC_SHIFT);
cdt[3] =
((hw_buffer_size - 1) << CDT3_BD_SHIFT) |
(dbr_address << CDT3_BA_SHIFT);
dim2_write_ctr(CDT + ch_addr, cdt);
}
static u16 dim2_rpc(u8 ch_addr)
{
u32 cdt0 = dim2_read_ctr(CDT + ch_addr, 0);
return (cdt0 >> CDT0_RPC_SHIFT) & CDT0_RPC_MASK;
}
static void dim2_clear_cdt(u8 ch_addr)
{
u32 cdt[4] = { 0, 0, 0, 0 };
dim2_write_ctr(CDT + ch_addr, cdt);
}
static void dim2_configure_adt(u8 ch_addr)
{
u32 adt[4] = { 0, 0, 0, 0 };
adt[0] =
(true << ADT0_CE_BIT) |
(true << ADT0_LE_BIT) |
(0 << ADT0_PG_BIT);
dim2_write_ctr(ADT + ch_addr, adt);
}
static void dim2_clear_adt(u8 ch_addr)
{
u32 adt[4] = { 0, 0, 0, 0 };
dim2_write_ctr(ADT + ch_addr, adt);
}
static void dim2_start_ctrl_async(u8 ch_addr, u8 idx, u32 buf_addr,
u16 buffer_size)
{
u8 const shift = idx * 16;
u32 mask[4] = { 0, 0, 0, 0 };
u32 adt[4] = { 0, 0, 0, 0 };
mask[1] =
bit_mask(ADT1_PS_BIT + shift) |
bit_mask(ADT1_RDY_BIT + shift) |
(ADT1_CTRL_ASYNC_BD_MASK << (ADT1_BD_SHIFT + shift));
adt[1] =
(true << (ADT1_PS_BIT + shift)) |
(true << (ADT1_RDY_BIT + shift)) |
((buffer_size - 1) << (ADT1_BD_SHIFT + shift));
mask[idx + 2] = 0xFFFFFFFF;
adt[idx + 2] = buf_addr;
dim2_write_ctr_mask(ADT + ch_addr, mask, adt);
}
static void dim2_start_isoc_sync(u8 ch_addr, u8 idx, u32 buf_addr,
u16 buffer_size)
{
u8 const shift = idx * 16;
u32 mask[4] = { 0, 0, 0, 0 };
u32 adt[4] = { 0, 0, 0, 0 };
mask[1] =
bit_mask(ADT1_RDY_BIT + shift) |
(ADT1_ISOC_SYNC_BD_MASK << (ADT1_BD_SHIFT + shift));
adt[1] =
(true << (ADT1_RDY_BIT + shift)) |
((buffer_size - 1) << (ADT1_BD_SHIFT + shift));
mask[idx + 2] = 0xFFFFFFFF;
adt[idx + 2] = buf_addr;
dim2_write_ctr_mask(ADT + ch_addr, mask, adt);
}
static void dim2_clear_ctram(void)
{
u32 ctr_addr;
for (ctr_addr = 0; ctr_addr < 0x90; ctr_addr++)
dim2_clear_ctr(ctr_addr);
}
static void dim2_configure_channel(u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address,
u16 hw_buffer_size, u16 packet_length)
{
dim2_configure_cdt(ch_addr, dbr_address, hw_buffer_size, packet_length);
dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0);
dim2_configure_adt(ch_addr);
dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1);
/* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */
writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
}
static void dim2_clear_channel(u8 ch_addr)
{
/* mask interrupt for used channel, disable mlb_sys_int[0] interrupt */
writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
dim2_clear_cat(AHB_CAT, ch_addr);
dim2_clear_adt(ch_addr);
dim2_clear_cat(MLB_CAT, ch_addr);
dim2_clear_cdt(ch_addr);
/* clear channel status bit */
writel(bit_mask(ch_addr), &g.dim2->ACSR0);
}
/* -------------------------------------------------------------------------- */
/* trace async tx dbr fill state */
static inline u16 norm_pc(u16 pc)
{
return pc & CDT0_RPC_MASK;
}
static void dbrcnt_init(u8 ch_addr, u16 dbr_size)
{
g.atx_dbr.rest_size = dbr_size;
g.atx_dbr.rpc = dim2_rpc(ch_addr);
g.atx_dbr.wpc = g.atx_dbr.rpc;
}
static void dbrcnt_enq(int buf_sz)
{
g.atx_dbr.rest_size -= buf_sz;
g.atx_dbr.sz_queue[norm_pc(g.atx_dbr.wpc)] = buf_sz;
g.atx_dbr.wpc++;
}
u16 dim_dbr_space(struct dim_channel *ch)
{
u16 cur_rpc;
struct async_tx_dbr *dbr = &g.atx_dbr;
if (ch->addr != dbr->ch_addr)
return 0xFFFF;
cur_rpc = dim2_rpc(ch->addr);
while (norm_pc(dbr->rpc) != cur_rpc) {
dbr->rest_size += dbr->sz_queue[norm_pc(dbr->rpc)];
dbr->rpc++;
}
if ((u16)(dbr->wpc - dbr->rpc) >= CDT0_RPC_MASK)
return 0;
return dbr->rest_size;
}
/* -------------------------------------------------------------------------- */
/* channel state helpers */
static void state_init(struct int_ch_state *state)
{
state->request_counter = 0;
state->service_counter = 0;
state->idx1 = 0;
state->idx2 = 0;
state->level = 0;
}
/* -------------------------------------------------------------------------- */
/* macro helper functions */
static inline bool check_channel_address(u32 ch_address)
{
return ch_address > 0 && (ch_address % 2) == 0 &&
(ch_address / 2) <= (u32)CAT_CL_MASK;
}
static inline bool check_packet_length(u32 packet_length)
{
u16 const max_size = ((u16)CDT3_BD_ISOC_MASK + 1u) / ISOC_DBR_FACTOR;
if (packet_length <= 0)
return false; /* too small */
if (packet_length > max_size)
return false; /* too big */
if (packet_length - 1u > (u32)CDT1_BS_ISOC_MASK)
return false; /* too big */
return true;
}
static inline bool check_bytes_per_frame(u32 bytes_per_frame)
{
u16 const bd_factor = g.fcnt + 2;
u16 const max_size = ((u16)CDT3_BD_MASK + 1u) >> bd_factor;
if (bytes_per_frame <= 0)
return false; /* too small */
if (bytes_per_frame > max_size)
return false; /* too big */
return true;
}
u16 dim_norm_ctrl_async_buffer_size(u16 buf_size)
{
u16 const max_size = (u16)ADT1_CTRL_ASYNC_BD_MASK + 1u;
if (buf_size > max_size)
return max_size;
return buf_size;
}
static inline u16 norm_isoc_buffer_size(u16 buf_size, u16 packet_length)
{
u16 n;
u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u;
if (buf_size > max_size)
buf_size = max_size;
n = buf_size / packet_length;
if (n < 2u)
return 0; /* too small buffer for given packet_length */
return packet_length * n;
}
static inline u16 norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame)
{
u16 n;
u16 const max_size = (u16)ADT1_ISOC_SYNC_BD_MASK + 1u;
u32 const unit = bytes_per_frame << g.fcnt;
if (buf_size > max_size)
buf_size = max_size;
n = buf_size / unit;
if (n < 1u)
return 0; /* too small buffer for given bytes_per_frame */
return unit * n;
}
static void dim2_cleanup(void)
{
/* disable MediaLB */
writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
dim2_clear_ctram();
/* disable mlb_int interrupt */
writel(0, &g.dim2->MIEN);
/* clear status for all dma channels */
writel(0xFFFFFFFF, &g.dim2->ACSR0);
writel(0xFFFFFFFF, &g.dim2->ACSR1);
/* mask interrupts for all channels */
writel(0, &g.dim2->ACMR0);
writel(0, &g.dim2->ACMR1);
}
static void dim2_initialize(bool enable_6pin, u8 mlb_clock)
{
dim2_cleanup();
/* configure and enable MediaLB */
writel(enable_6pin << MLBC0_MLBPEN_BIT |
mlb_clock << MLBC0_MLBCLK_SHIFT |
g.fcnt << MLBC0_FCNT_SHIFT |
true << MLBC0_MLBEN_BIT,
&g.dim2->MLBC0);
/* activate all HBI channels */
writel(0xFFFFFFFF, &g.dim2->HCMR0);
writel(0xFFFFFFFF, &g.dim2->HCMR1);
/* enable HBI */
writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);
/* configure DMA */
writel(ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |
true << ACTL_SCE_BIT, &g.dim2->ACTL);
}
static bool dim2_is_mlb_locked(void)
{
u32 const mask0 = bit_mask(MLBC0_MLBLK_BIT);
u32 const mask1 = bit_mask(MLBC1_CLKMERR_BIT) |
bit_mask(MLBC1_LOCKERR_BIT);
u32 const c1 = readl(&g.dim2->MLBC1);
u32 const nda_mask = (u32)MLBC1_NDA_MASK << MLBC1_NDA_SHIFT;
writel(c1 & nda_mask, &g.dim2->MLBC1);
return (readl(&g.dim2->MLBC1) & mask1) == 0 &&
(readl(&g.dim2->MLBC0) & mask0) != 0;
}
/* -------------------------------------------------------------------------- */
/* channel help routines */
static inline bool service_channel(u8 ch_addr, u8 idx)
{
u8 const shift = idx * 16;
u32 const adt1 = dim2_read_ctr(ADT + ch_addr, 1);
u32 mask[4] = { 0, 0, 0, 0 };
u32 adt_w[4] = { 0, 0, 0, 0 };
if (((adt1 >> (ADT1_DNE_BIT + shift)) & 1) == 0)
return false;
mask[1] =
bit_mask(ADT1_DNE_BIT + shift) |
bit_mask(ADT1_ERR_BIT + shift) |
bit_mask(ADT1_RDY_BIT + shift);
dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w);
/* clear channel status bit */
writel(bit_mask(ch_addr), &g.dim2->ACSR0);
return true;
}
/* -------------------------------------------------------------------------- */
/* channel init routines */
static void isoc_init(struct dim_channel *ch, u8 ch_addr, u16 packet_length)
{
state_init(&ch->state);
ch->addr = ch_addr;
ch->packet_length = packet_length;
ch->bytes_per_frame = 0;
ch->done_sw_buffers_number = 0;
}
static void sync_init(struct dim_channel *ch, u8 ch_addr, u16 bytes_per_frame)
{
state_init(&ch->state);
ch->addr = ch_addr;
ch->packet_length = 0;
ch->bytes_per_frame = bytes_per_frame;
ch->done_sw_buffers_number = 0;
}
static void channel_init(struct dim_channel *ch, u8 ch_addr)
{
state_init(&ch->state);
ch->addr = ch_addr;
ch->packet_length = 0;
ch->bytes_per_frame = 0;
ch->done_sw_buffers_number = 0;
}
/* returns true if channel interrupt state is cleared */
static bool channel_service_interrupt(struct dim_channel *ch)
{
struct int_ch_state *const state = &ch->state;
if (!service_channel(ch->addr, state->idx2))
return false;
state->idx2 ^= 1;
state->request_counter++;
return true;
}
static bool channel_start(struct dim_channel *ch, u32 buf_addr, u16 buf_size)
{
struct int_ch_state *const state = &ch->state;
if (buf_size <= 0)
return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE, "Bad buffer size");
if (ch->packet_length == 0 && ch->bytes_per_frame == 0 &&
buf_size != dim_norm_ctrl_async_buffer_size(buf_size))
return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE,
"Bad control/async buffer size");
if (ch->packet_length &&
buf_size != norm_isoc_buffer_size(buf_size, ch->packet_length))
return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE,
"Bad isochronous buffer size");
if (ch->bytes_per_frame &&
buf_size != norm_sync_buffer_size(buf_size, ch->bytes_per_frame))
return dim_on_error(DIM_ERR_BAD_BUFFER_SIZE,
"Bad synchronous buffer size");
if (state->level >= 2u)
return dim_on_error(DIM_ERR_OVERFLOW, "Channel overflow");
++state->level;
if (ch->addr == g.atx_dbr.ch_addr)
dbrcnt_enq(buf_size);
if (ch->packet_length || ch->bytes_per_frame)
dim2_start_isoc_sync(ch->addr, state->idx1, buf_addr, buf_size);
else
dim2_start_ctrl_async(ch->addr, state->idx1, buf_addr,
buf_size);
state->idx1 ^= 1;
return true;
}
static u8 channel_service(struct dim_channel *ch)
{
struct int_ch_state *const state = &ch->state;
if (state->service_counter != state->request_counter) {
state->service_counter++;
if (state->level == 0)
return DIM_ERR_UNDERFLOW;
--state->level;
ch->done_sw_buffers_number++;
}
return DIM_NO_ERROR;
}
static bool channel_detach_buffers(struct dim_channel *ch, u16 buffers_number)
{
if (buffers_number > ch->done_sw_buffers_number)
return dim_on_error(DIM_ERR_UNDERFLOW, "Channel underflow");
ch->done_sw_buffers_number -= buffers_number;
return true;
}
/* -------------------------------------------------------------------------- */
/* API */
u8 dim_startup(struct dim2_regs __iomem *dim_base_address, u32 mlb_clock,
u32 fcnt)
{
g.dim_is_initialized = false;
if (!dim_base_address)
return DIM_INIT_ERR_DIM_ADDR;
/* MediaLB clock: 0 - 256 fs, 1 - 512 fs, 2 - 1024 fs, 3 - 2048 fs */
/* MediaLB clock: 4 - 3072 fs, 5 - 4096 fs, 6 - 6144 fs, 7 - 8192 fs */
if (mlb_clock >= 8)
return DIM_INIT_ERR_MLB_CLOCK;
if (fcnt > MLBC0_FCNT_MAX_VAL)
return DIM_INIT_ERR_MLB_CLOCK;
g.dim2 = dim_base_address;
g.fcnt = fcnt;
g.dbr_map[0] = 0;
g.dbr_map[1] = 0;
dim2_initialize(mlb_clock >= 3, mlb_clock);
g.dim_is_initialized = true;
return DIM_NO_ERROR;
}
void dim_shutdown(void)
{
g.dim_is_initialized = false;
dim2_cleanup();
}
bool dim_get_lock_state(void)
{
return dim2_is_mlb_locked();
}
static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx,
u16 ch_address, u16 hw_buffer_size)
{
if (!g.dim_is_initialized || !ch)
return DIM_ERR_DRIVER_NOT_INITIALIZED;
if (!check_channel_address(ch_address))
return DIM_INIT_ERR_CHANNEL_ADDRESS;
if (!ch->dbr_size)
ch->dbr_size = ROUND_UP_TO(hw_buffer_size, DBR_BLOCK_SIZE);
ch->dbr_addr = alloc_dbr(ch->dbr_size);
if (ch->dbr_addr >= DBR_SIZE)
return DIM_INIT_ERR_OUT_OF_MEMORY;
channel_init(ch, ch_address / 2);
dim2_configure_channel(ch->addr, type, is_tx,
ch->dbr_addr, ch->dbr_size, 0);
return DIM_NO_ERROR;
}
void dim_service_mlb_int_irq(void)
{
writel(0, &g.dim2->MS0);
writel(0, &g.dim2->MS1);
}
/*
* Retrieves maximal possible correct buffer size for isochronous data type
* conform to given packet length and not bigger than given buffer size.
*
* Returns non-zero correct buffer size or zero by error.
*/
u16 dim_norm_isoc_buffer_size(u16 buf_size, u16 packet_length)
{
if (!check_packet_length(packet_length))
return 0;
return norm_isoc_buffer_size(buf_size, packet_length);
}
/*
* Retrieves maximal possible correct buffer size for synchronous data type
* conform to given bytes per frame and not bigger than given buffer size.
*
* Returns non-zero correct buffer size or zero by error.
*/
u16 dim_norm_sync_buffer_size(u16 buf_size, u16 bytes_per_frame)
{
if (!check_bytes_per_frame(bytes_per_frame))
return 0;
return norm_sync_buffer_size(buf_size, bytes_per_frame);
}
u8 dim_init_control(struct dim_channel *ch, u8 is_tx, u16 ch_address,
u16 max_buffer_size)
{
return init_ctrl_async(ch, CAT_CT_VAL_CONTROL, is_tx, ch_address,
max_buffer_size);
}
u8 dim_init_async(struct dim_channel *ch, u8 is_tx, u16 ch_address,
u16 max_buffer_size)
{
u8 ret = init_ctrl_async(ch, CAT_CT_VAL_ASYNC, is_tx, ch_address,
max_buffer_size);
if (is_tx && !g.atx_dbr.ch_addr) {
g.atx_dbr.ch_addr = ch->addr;
dbrcnt_init(ch->addr, ch->dbr_size);
writel(bit_mask(20), &g.dim2->MIEN);
}
return ret;
}
u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address,
u16 packet_length)
{
if (!g.dim_is_initialized || !ch)
return DIM_ERR_DRIVER_NOT_INITIALIZED;
if (!check_channel_address(ch_address))
return DIM_INIT_ERR_CHANNEL_ADDRESS;
if (!check_packet_length(packet_length))
return DIM_ERR_BAD_CONFIG;
if (!ch->dbr_size)
ch->dbr_size = packet_length * ISOC_DBR_FACTOR;
ch->dbr_addr = alloc_dbr(ch->dbr_size);
if (ch->dbr_addr >= DBR_SIZE)
return DIM_INIT_ERR_OUT_OF_MEMORY;
isoc_init(ch, ch_address / 2, packet_length);
dim2_configure_channel(ch->addr, CAT_CT_VAL_ISOC, is_tx, ch->dbr_addr,
ch->dbr_size, packet_length);
return DIM_NO_ERROR;
}
u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address,
u16 bytes_per_frame)
{
u16 bd_factor = g.fcnt + 2;
if (!g.dim_is_initialized || !ch)
return DIM_ERR_DRIVER_NOT_INITIALIZED;
if (!check_channel_address(ch_address))
return DIM_INIT_ERR_CHANNEL_ADDRESS;
if (!check_bytes_per_frame(bytes_per_frame))
return DIM_ERR_BAD_CONFIG;
if (!ch->dbr_size)
ch->dbr_size = bytes_per_frame << bd_factor;
ch->dbr_addr = alloc_dbr(ch->dbr_size);
if (ch->dbr_addr >= DBR_SIZE)
return DIM_INIT_ERR_OUT_OF_MEMORY;
sync_init(ch, ch_address / 2, bytes_per_frame);
dim2_clear_dbr(ch->dbr_addr, ch->dbr_size);
dim2_configure_channel(ch->addr, CAT_CT_VAL_SYNC, is_tx,
ch->dbr_addr, ch->dbr_size, 0);
return DIM_NO_ERROR;
}
u8 dim_destroy_channel(struct dim_channel *ch)
{
if (!g.dim_is_initialized || !ch)
return DIM_ERR_DRIVER_NOT_INITIALIZED;
if (ch->addr == g.atx_dbr.ch_addr) {
writel(0, &g.dim2->MIEN);
g.atx_dbr.ch_addr = 0;
}
dim2_clear_channel(ch->addr);
if (ch->dbr_addr < DBR_SIZE)
free_dbr(ch->dbr_addr, ch->dbr_size);
ch->dbr_addr = DBR_SIZE;
return DIM_NO_ERROR;
}
void dim_service_ahb_int_irq(struct dim_channel *const *channels)
{
bool state_changed;
if (!g.dim_is_initialized) {
dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED,
"DIM is not initialized");
return;
}
if (!channels) {
dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED, "Bad channels");
return;
}
/*
* Use while-loop and a flag to make sure the age is changed back at
* least once, otherwise the interrupt may never come if CPU generates
* interrupt on changing age.
* This cycle runs not more than number of channels, because
* channel_service_interrupt() routine doesn't start the channel again.
*/
do {
struct dim_channel *const *ch = channels;
state_changed = false;
while (*ch) {
state_changed |= channel_service_interrupt(*ch);
++ch;
}
} while (state_changed);
}
u8 dim_service_channel(struct dim_channel *ch)
{
if (!g.dim_is_initialized || !ch)
return DIM_ERR_DRIVER_NOT_INITIALIZED;
return channel_service(ch);
}
struct dim_ch_state *dim_get_channel_state(struct dim_channel *ch,
struct dim_ch_state *state_ptr)
{
if (!ch || !state_ptr)
return NULL;
state_ptr->ready = ch->state.level < 2;
state_ptr->done_buffers = ch->done_sw_buffers_number;
return state_ptr;
}
bool dim_enqueue_buffer(struct dim_channel *ch, u32 buffer_addr,
u16 buffer_size)
{
if (!ch)
return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED,
"Bad channel");
return channel_start(ch, buffer_addr, buffer_size);
}
bool dim_detach_buffers(struct dim_channel *ch, u16 buffers_number)
{
if (!ch)
return dim_on_error(DIM_ERR_DRIVER_NOT_INITIALIZED,
"Bad channel");
return channel_detach_buffers(ch, buffers_number);
}
| linux-master | drivers/staging/most/dim2/hal.c |
// SPDX-License-Identifier: GPL-2.0
/*
* video.c - V4L2 component for Mostcore
*
* Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/suspend.h>
#include <linux/videodev2.h>
#include <linux/mutex.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-event.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-fh.h>
#include <linux/most.h>
#define V4L2_CMP_MAX_INPUT 1
static struct most_component comp;
struct most_video_dev {
struct most_interface *iface;
int ch_idx;
struct list_head list;
bool mute;
struct list_head pending_mbos;
spinlock_t list_lock;
struct v4l2_device v4l2_dev;
atomic_t access_ref;
struct video_device *vdev;
unsigned int ctrl_input;
struct mutex lock;
wait_queue_head_t wait_data;
};
struct comp_fh {
/* must be the first field of this struct! */
struct v4l2_fh fh;
struct most_video_dev *mdev;
u32 offs;
};
static LIST_HEAD(video_devices);
static DEFINE_SPINLOCK(list_lock);
static inline bool data_ready(struct most_video_dev *mdev)
{
return !list_empty(&mdev->pending_mbos);
}
static inline struct mbo *get_top_mbo(struct most_video_dev *mdev)
{
return list_first_entry(&mdev->pending_mbos, struct mbo, list);
}
static int comp_vdev_open(struct file *filp)
{
int ret;
struct video_device *vdev = video_devdata(filp);
struct most_video_dev *mdev = video_drvdata(filp);
struct comp_fh *fh;
switch (vdev->vfl_type) {
case VFL_TYPE_VIDEO:
break;
default:
return -EINVAL;
}
fh = kzalloc(sizeof(*fh), GFP_KERNEL);
if (!fh)
return -ENOMEM;
if (!atomic_inc_and_test(&mdev->access_ref)) {
v4l2_err(&mdev->v4l2_dev, "too many clients\n");
ret = -EBUSY;
goto err_dec;
}
fh->mdev = mdev;
v4l2_fh_init(&fh->fh, vdev);
filp->private_data = fh;
v4l2_fh_add(&fh->fh);
ret = most_start_channel(mdev->iface, mdev->ch_idx, &comp);
if (ret) {
v4l2_err(&mdev->v4l2_dev, "most_start_channel() failed\n");
goto err_rm;
}
return 0;
err_rm:
v4l2_fh_del(&fh->fh);
v4l2_fh_exit(&fh->fh);
err_dec:
atomic_dec(&mdev->access_ref);
kfree(fh);
return ret;
}
static int comp_vdev_close(struct file *filp)
{
struct comp_fh *fh = filp->private_data;
struct most_video_dev *mdev = fh->mdev;
struct mbo *mbo, *tmp;
/*
* We need to put MBOs back before we call most_stop_channel()
* to deallocate MBOs.
* From the other hand mostcore still calling rx_completion()
* to deliver MBOs until most_stop_channel() is called.
* Use mute to work around this issue.
* This must be implemented in core.
*/
spin_lock_irq(&mdev->list_lock);
mdev->mute = true;
list_for_each_entry_safe(mbo, tmp, &mdev->pending_mbos, list) {
list_del(&mbo->list);
spin_unlock_irq(&mdev->list_lock);
most_put_mbo(mbo);
spin_lock_irq(&mdev->list_lock);
}
spin_unlock_irq(&mdev->list_lock);
most_stop_channel(mdev->iface, mdev->ch_idx, &comp);
mdev->mute = false;
v4l2_fh_del(&fh->fh);
v4l2_fh_exit(&fh->fh);
atomic_dec(&mdev->access_ref);
kfree(fh);
return 0;
}
static ssize_t comp_vdev_read(struct file *filp, char __user *buf,
size_t count, loff_t *pos)
{
struct comp_fh *fh = filp->private_data;
struct most_video_dev *mdev = fh->mdev;
int ret = 0;
if (*pos)
return -ESPIPE;
if (!mdev)
return -ENODEV;
/* wait for the first buffer */
if (!(filp->f_flags & O_NONBLOCK)) {
if (wait_event_interruptible(mdev->wait_data, data_ready(mdev)))
return -ERESTARTSYS;
}
if (!data_ready(mdev))
return -EAGAIN;
while (count > 0 && data_ready(mdev)) {
struct mbo *const mbo = get_top_mbo(mdev);
int const rem = mbo->processed_length - fh->offs;
int const cnt = rem < count ? rem : count;
if (copy_to_user(buf, mbo->virt_address + fh->offs, cnt)) {
v4l2_err(&mdev->v4l2_dev, "read: copy_to_user failed\n");
if (!ret)
ret = -EFAULT;
return ret;
}
fh->offs += cnt;
count -= cnt;
buf += cnt;
ret += cnt;
if (cnt >= rem) {
fh->offs = 0;
spin_lock_irq(&mdev->list_lock);
list_del(&mbo->list);
spin_unlock_irq(&mdev->list_lock);
most_put_mbo(mbo);
}
}
return ret;
}
static __poll_t comp_vdev_poll(struct file *filp, poll_table *wait)
{
struct comp_fh *fh = filp->private_data;
struct most_video_dev *mdev = fh->mdev;
__poll_t mask = 0;
/* only wait if no data is available */
if (!data_ready(mdev))
poll_wait(filp, &mdev->wait_data, wait);
if (data_ready(mdev))
mask |= EPOLLIN | EPOLLRDNORM;
return mask;
}
static void comp_set_format_struct(struct v4l2_format *f)
{
f->fmt.pix.width = 8;
f->fmt.pix.height = 8;
f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
f->fmt.pix.bytesperline = 0;
f->fmt.pix.sizeimage = 188 * 2;
f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
f->fmt.pix.field = V4L2_FIELD_NONE;
f->fmt.pix.priv = 0;
}
static int comp_set_format(struct most_video_dev *mdev, unsigned int cmd,
struct v4l2_format *format)
{
if (format->fmt.pix.pixelformat != V4L2_PIX_FMT_MPEG)
return -EINVAL;
if (cmd == VIDIOC_TRY_FMT)
return 0;
comp_set_format_struct(format);
return 0;
}
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct comp_fh *fh = priv;
struct most_video_dev *mdev = fh->mdev;
strscpy(cap->driver, "v4l2_component", sizeof(cap->driver));
strscpy(cap->card, "MOST", sizeof(cap->card));
snprintf(cap->bus_info, sizeof(cap->bus_info),
"%s", mdev->iface->description);
return 0;
}
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
if (f->index)
return -EINVAL;
strscpy(f->description, "MPEG", sizeof(f->description));
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
f->flags = V4L2_FMT_FLAG_COMPRESSED;
f->pixelformat = V4L2_PIX_FMT_MPEG;
return 0;
}
static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
comp_set_format_struct(f);
return 0;
}
static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct comp_fh *fh = priv;
struct most_video_dev *mdev = fh->mdev;
return comp_set_format(mdev, VIDIOC_TRY_FMT, f);
}
static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_format *f)
{
struct comp_fh *fh = priv;
struct most_video_dev *mdev = fh->mdev;
return comp_set_format(mdev, VIDIOC_S_FMT, f);
}
static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *norm)
{
*norm = V4L2_STD_UNKNOWN;
return 0;
}
static int vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *input)
{
struct comp_fh *fh = priv;
struct most_video_dev *mdev = fh->mdev;
if (input->index >= V4L2_CMP_MAX_INPUT)
return -EINVAL;
strscpy(input->name, "MOST Video", sizeof(input->name));
input->type |= V4L2_INPUT_TYPE_CAMERA;
input->audioset = 0;
input->std = mdev->vdev->tvnorms;
return 0;
}
static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
{
struct comp_fh *fh = priv;
struct most_video_dev *mdev = fh->mdev;
*i = mdev->ctrl_input;
return 0;
}
static int vidioc_s_input(struct file *file, void *priv, unsigned int index)
{
struct comp_fh *fh = priv;
struct most_video_dev *mdev = fh->mdev;
if (index >= V4L2_CMP_MAX_INPUT)
return -EINVAL;
mdev->ctrl_input = index;
return 0;
}
static const struct v4l2_file_operations comp_fops = {
.owner = THIS_MODULE,
.open = comp_vdev_open,
.release = comp_vdev_close,
.read = comp_vdev_read,
.poll = comp_vdev_poll,
.unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops video_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
.vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
.vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
.vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
.vidioc_g_std = vidioc_g_std,
.vidioc_enum_input = vidioc_enum_input,
.vidioc_g_input = vidioc_g_input,
.vidioc_s_input = vidioc_s_input,
};
static const struct video_device comp_videodev_template = {
.fops = &comp_fops,
.release = video_device_release,
.ioctl_ops = &video_ioctl_ops,
.tvnorms = V4L2_STD_UNKNOWN,
.device_caps = V4L2_CAP_READWRITE | V4L2_CAP_VIDEO_CAPTURE,
};
/**************************************************************************/
static struct most_video_dev *get_comp_dev(struct most_interface *iface, int channel_idx)
{
struct most_video_dev *mdev;
unsigned long flags;
spin_lock_irqsave(&list_lock, flags);
list_for_each_entry(mdev, &video_devices, list) {
if (mdev->iface == iface && mdev->ch_idx == channel_idx) {
spin_unlock_irqrestore(&list_lock, flags);
return mdev;
}
}
spin_unlock_irqrestore(&list_lock, flags);
return NULL;
}
static int comp_rx_data(struct mbo *mbo)
{
unsigned long flags;
struct most_video_dev *mdev =
get_comp_dev(mbo->ifp, mbo->hdm_channel_id);
if (!mdev)
return -EIO;
spin_lock_irqsave(&mdev->list_lock, flags);
if (unlikely(mdev->mute)) {
spin_unlock_irqrestore(&mdev->list_lock, flags);
return -EIO;
}
list_add_tail(&mbo->list, &mdev->pending_mbos);
spin_unlock_irqrestore(&mdev->list_lock, flags);
wake_up_interruptible(&mdev->wait_data);
return 0;
}
static int comp_register_videodev(struct most_video_dev *mdev)
{
int ret;
init_waitqueue_head(&mdev->wait_data);
/* allocate and fill v4l2 video struct */
mdev->vdev = video_device_alloc();
if (!mdev->vdev)
return -ENOMEM;
/* Fill the video capture device struct */
*mdev->vdev = comp_videodev_template;
mdev->vdev->v4l2_dev = &mdev->v4l2_dev;
mdev->vdev->lock = &mdev->lock;
snprintf(mdev->vdev->name, sizeof(mdev->vdev->name), "MOST: %s",
mdev->v4l2_dev.name);
/* Register the v4l2 device */
video_set_drvdata(mdev->vdev, mdev);
ret = video_register_device(mdev->vdev, VFL_TYPE_VIDEO, -1);
if (ret) {
v4l2_err(&mdev->v4l2_dev, "video_register_device failed (%d)\n",
ret);
video_device_release(mdev->vdev);
}
return ret;
}
static void comp_unregister_videodev(struct most_video_dev *mdev)
{
video_unregister_device(mdev->vdev);
}
static void comp_v4l2_dev_release(struct v4l2_device *v4l2_dev)
{
struct most_video_dev *mdev =
container_of(v4l2_dev, struct most_video_dev, v4l2_dev);
v4l2_device_unregister(v4l2_dev);
kfree(mdev);
}
static int comp_probe_channel(struct most_interface *iface, int channel_idx,
struct most_channel_config *ccfg, char *name,
char *args)
{
int ret;
struct most_video_dev *mdev = get_comp_dev(iface, channel_idx);
if (mdev) {
pr_err("channel already linked\n");
return -EEXIST;
}
if (ccfg->direction != MOST_CH_RX) {
pr_err("wrong direction, expect rx\n");
return -EINVAL;
}
if (ccfg->data_type != MOST_CH_SYNC &&
ccfg->data_type != MOST_CH_ISOC) {
pr_err("wrong channel type, expect sync or isoc\n");
return -EINVAL;
}
mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
if (!mdev)
return -ENOMEM;
mutex_init(&mdev->lock);
atomic_set(&mdev->access_ref, -1);
spin_lock_init(&mdev->list_lock);
INIT_LIST_HEAD(&mdev->pending_mbos);
mdev->iface = iface;
mdev->ch_idx = channel_idx;
mdev->v4l2_dev.release = comp_v4l2_dev_release;
/* Create the v4l2_device */
strscpy(mdev->v4l2_dev.name, name, sizeof(mdev->v4l2_dev.name));
ret = v4l2_device_register(NULL, &mdev->v4l2_dev);
if (ret) {
pr_err("v4l2_device_register() failed\n");
kfree(mdev);
return ret;
}
ret = comp_register_videodev(mdev);
if (ret)
goto err_unreg;
spin_lock_irq(&list_lock);
list_add(&mdev->list, &video_devices);
spin_unlock_irq(&list_lock);
return 0;
err_unreg:
v4l2_device_disconnect(&mdev->v4l2_dev);
v4l2_device_put(&mdev->v4l2_dev);
return ret;
}
static int comp_disconnect_channel(struct most_interface *iface,
int channel_idx)
{
struct most_video_dev *mdev = get_comp_dev(iface, channel_idx);
if (!mdev) {
pr_err("no such channel is linked\n");
return -ENOENT;
}
spin_lock_irq(&list_lock);
list_del(&mdev->list);
spin_unlock_irq(&list_lock);
comp_unregister_videodev(mdev);
v4l2_device_disconnect(&mdev->v4l2_dev);
v4l2_device_put(&mdev->v4l2_dev);
return 0;
}
static struct most_component comp = {
.mod = THIS_MODULE,
.name = "video",
.probe_channel = comp_probe_channel,
.disconnect_channel = comp_disconnect_channel,
.rx_completion = comp_rx_data,
};
static int __init comp_init(void)
{
int err;
err = most_register_component(&comp);
if (err)
return err;
err = most_register_configfs_subsys(&comp);
if (err) {
most_deregister_component(&comp);
return err;
}
return 0;
}
static void __exit comp_exit(void)
{
struct most_video_dev *mdev, *tmp;
/*
* As the mostcore currently doesn't call disconnect_channel()
* for linked channels while we call most_deregister_component()
* we simulate this call here.
* This must be fixed in core.
*/
spin_lock_irq(&list_lock);
list_for_each_entry_safe(mdev, tmp, &video_devices, list) {
list_del(&mdev->list);
spin_unlock_irq(&list_lock);
comp_unregister_videodev(mdev);
v4l2_device_disconnect(&mdev->v4l2_dev);
v4l2_device_put(&mdev->v4l2_dev);
spin_lock_irq(&list_lock);
}
spin_unlock_irq(&list_lock);
most_deregister_configfs_subsys(&comp);
most_deregister_component(&comp);
BUG_ON(!list_empty(&video_devices));
}
module_init(comp_init);
module_exit(comp_exit);
MODULE_DESCRIPTION("V4L2 Component Module for Mostcore");
MODULE_AUTHOR("Andrey Shvetsov <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/staging/most/video/video.c |
// SPDX-License-Identifier: GPL-2.0
/*
* net.c - Networking component for Mostcore
*
* Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/wait.h>
#include <linux/kobject.h>
#include <linux/most.h>
#define MEP_HDR_LEN 8
#define MDP_HDR_LEN 16
#define MAMAC_DATA_LEN (1024 - MDP_HDR_LEN)
#define PMHL 5
#define PMS_TELID_UNSEGM_MAMAC 0x0A
#define PMS_FIFONO_MDP 0x01
#define PMS_FIFONO_MEP 0x04
#define PMS_MSGTYPE_DATA 0x04
#define PMS_DEF_PRIO 0
#define MEP_DEF_RETRY 15
#define PMS_FIFONO_MASK 0x07
#define PMS_FIFONO_SHIFT 3
#define PMS_RETRY_SHIFT 4
#define PMS_TELID_MASK 0x0F
#define PMS_TELID_SHIFT 4
#define HB(value) ((u8)((u16)(value) >> 8))
#define LB(value) ((u8)(value))
#define EXTRACT_BIT_SET(bitset_name, value) \
(((value) >> bitset_name##_SHIFT) & bitset_name##_MASK)
#define PMS_IS_MEP(buf, len) \
((len) > MEP_HDR_LEN && \
EXTRACT_BIT_SET(PMS_FIFONO, (buf)[3]) == PMS_FIFONO_MEP)
static inline bool pms_is_mamac(char *buf, u32 len)
{
return (len > MDP_HDR_LEN &&
EXTRACT_BIT_SET(PMS_FIFONO, buf[3]) == PMS_FIFONO_MDP &&
EXTRACT_BIT_SET(PMS_TELID, buf[14]) == PMS_TELID_UNSEGM_MAMAC);
}
struct net_dev_channel {
bool linked;
int ch_id;
};
struct net_dev_context {
struct most_interface *iface;
bool is_mamac;
struct net_device *dev;
struct net_dev_channel rx;
struct net_dev_channel tx;
struct list_head list;
};
static LIST_HEAD(net_devices);
static DEFINE_MUTEX(probe_disc_mt); /* ch->linked = true, most_nd_open */
static DEFINE_SPINLOCK(list_lock); /* list_head, ch->linked = false, dev_hold */
static struct most_component comp;
static int skb_to_mamac(const struct sk_buff *skb, struct mbo *mbo)
{
u8 *buff = mbo->virt_address;
static const u8 broadcast[] = { 0x03, 0xFF };
const u8 *dest_addr = skb->data + 4;
const u8 *eth_type = skb->data + 12;
unsigned int payload_len = skb->len - ETH_HLEN;
unsigned int mdp_len = payload_len + MDP_HDR_LEN;
if (mdp_len < skb->len) {
pr_err("drop: too large packet! (%u)\n", skb->len);
return -EINVAL;
}
if (mbo->buffer_length < mdp_len) {
pr_err("drop: too small buffer! (%d for %d)\n",
mbo->buffer_length, mdp_len);
return -EINVAL;
}
if (skb->len < ETH_HLEN) {
pr_err("drop: too small packet! (%d)\n", skb->len);
return -EINVAL;
}
if (dest_addr[0] == 0xFF && dest_addr[1] == 0xFF)
dest_addr = broadcast;
*buff++ = HB(mdp_len - 2);
*buff++ = LB(mdp_len - 2);
*buff++ = PMHL;
*buff++ = (PMS_FIFONO_MDP << PMS_FIFONO_SHIFT) | PMS_MSGTYPE_DATA;
*buff++ = PMS_DEF_PRIO;
*buff++ = dest_addr[0];
*buff++ = dest_addr[1];
*buff++ = 0x00;
*buff++ = HB(payload_len + 6);
*buff++ = LB(payload_len + 6);
/* end of FPH here */
*buff++ = eth_type[0];
*buff++ = eth_type[1];
*buff++ = 0;
*buff++ = 0;
*buff++ = PMS_TELID_UNSEGM_MAMAC << 4 | HB(payload_len);
*buff++ = LB(payload_len);
memcpy(buff, skb->data + ETH_HLEN, payload_len);
mbo->buffer_length = mdp_len;
return 0;
}
static int skb_to_mep(const struct sk_buff *skb, struct mbo *mbo)
{
u8 *buff = mbo->virt_address;
unsigned int mep_len = skb->len + MEP_HDR_LEN;
if (mep_len < skb->len) {
pr_err("drop: too large packet! (%u)\n", skb->len);
return -EINVAL;
}
if (mbo->buffer_length < mep_len) {
pr_err("drop: too small buffer! (%d for %d)\n",
mbo->buffer_length, mep_len);
return -EINVAL;
}
*buff++ = HB(mep_len - 2);
*buff++ = LB(mep_len - 2);
*buff++ = PMHL;
*buff++ = (PMS_FIFONO_MEP << PMS_FIFONO_SHIFT) | PMS_MSGTYPE_DATA;
*buff++ = (MEP_DEF_RETRY << PMS_RETRY_SHIFT) | PMS_DEF_PRIO;
*buff++ = 0;
*buff++ = 0;
*buff++ = 0;
memcpy(buff, skb->data, skb->len);
mbo->buffer_length = mep_len;
return 0;
}
static int most_nd_set_mac_address(struct net_device *dev, void *p)
{
struct net_dev_context *nd = netdev_priv(dev);
int err = eth_mac_addr(dev, p);
if (err)
return err;
nd->is_mamac =
(dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0 &&
dev->dev_addr[2] == 0 && dev->dev_addr[3] == 0);
/*
* Set default MTU for the given packet type.
* It is still possible to change MTU using ip tools afterwards.
*/
dev->mtu = nd->is_mamac ? MAMAC_DATA_LEN : ETH_DATA_LEN;
return 0;
}
static void on_netinfo(struct most_interface *iface,
unsigned char link_stat, unsigned char *mac_addr);
static int most_nd_open(struct net_device *dev)
{
struct net_dev_context *nd = netdev_priv(dev);
int ret = 0;
mutex_lock(&probe_disc_mt);
if (most_start_channel(nd->iface, nd->rx.ch_id, &comp)) {
netdev_err(dev, "most_start_channel() failed\n");
ret = -EBUSY;
goto unlock;
}
if (most_start_channel(nd->iface, nd->tx.ch_id, &comp)) {
netdev_err(dev, "most_start_channel() failed\n");
most_stop_channel(nd->iface, nd->rx.ch_id, &comp);
ret = -EBUSY;
goto unlock;
}
netif_carrier_off(dev);
if (is_valid_ether_addr(dev->dev_addr))
netif_dormant_off(dev);
else
netif_dormant_on(dev);
netif_wake_queue(dev);
if (nd->iface->request_netinfo)
nd->iface->request_netinfo(nd->iface, nd->tx.ch_id, on_netinfo);
unlock:
mutex_unlock(&probe_disc_mt);
return ret;
}
static int most_nd_stop(struct net_device *dev)
{
struct net_dev_context *nd = netdev_priv(dev);
netif_stop_queue(dev);
if (nd->iface->request_netinfo)
nd->iface->request_netinfo(nd->iface, nd->tx.ch_id, NULL);
most_stop_channel(nd->iface, nd->rx.ch_id, &comp);
most_stop_channel(nd->iface, nd->tx.ch_id, &comp);
return 0;
}
static netdev_tx_t most_nd_start_xmit(struct sk_buff *skb,
struct net_device *dev)
{
struct net_dev_context *nd = netdev_priv(dev);
struct mbo *mbo;
int ret;
mbo = most_get_mbo(nd->iface, nd->tx.ch_id, &comp);
if (!mbo) {
netif_stop_queue(dev);
dev->stats.tx_fifo_errors++;
return NETDEV_TX_BUSY;
}
if (nd->is_mamac)
ret = skb_to_mamac(skb, mbo);
else
ret = skb_to_mep(skb, mbo);
if (ret) {
most_put_mbo(mbo);
dev->stats.tx_dropped++;
kfree_skb(skb);
return NETDEV_TX_OK;
}
most_submit_mbo(mbo);
dev->stats.tx_packets++;
dev->stats.tx_bytes += skb->len;
kfree_skb(skb);
return NETDEV_TX_OK;
}
static const struct net_device_ops most_nd_ops = {
.ndo_open = most_nd_open,
.ndo_stop = most_nd_stop,
.ndo_start_xmit = most_nd_start_xmit,
.ndo_set_mac_address = most_nd_set_mac_address,
};
static void most_nd_setup(struct net_device *dev)
{
ether_setup(dev);
dev->netdev_ops = &most_nd_ops;
}
static struct net_dev_context *get_net_dev(struct most_interface *iface)
{
struct net_dev_context *nd;
list_for_each_entry(nd, &net_devices, list)
if (nd->iface == iface)
return nd;
return NULL;
}
static struct net_dev_context *get_net_dev_hold(struct most_interface *iface)
{
struct net_dev_context *nd;
unsigned long flags;
spin_lock_irqsave(&list_lock, flags);
nd = get_net_dev(iface);
if (nd && nd->rx.linked && nd->tx.linked)
dev_hold(nd->dev);
else
nd = NULL;
spin_unlock_irqrestore(&list_lock, flags);
return nd;
}
static int comp_probe_channel(struct most_interface *iface, int channel_idx,
struct most_channel_config *ccfg, char *name,
char *args)
{
struct net_dev_context *nd;
struct net_dev_channel *ch;
struct net_device *dev;
unsigned long flags;
int ret = 0;
if (!iface)
return -EINVAL;
if (ccfg->data_type != MOST_CH_ASYNC)
return -EINVAL;
mutex_lock(&probe_disc_mt);
nd = get_net_dev(iface);
if (!nd) {
dev = alloc_netdev(sizeof(struct net_dev_context), "meth%d",
NET_NAME_UNKNOWN, most_nd_setup);
if (!dev) {
ret = -ENOMEM;
goto unlock;
}
nd = netdev_priv(dev);
nd->iface = iface;
nd->dev = dev;
spin_lock_irqsave(&list_lock, flags);
list_add(&nd->list, &net_devices);
spin_unlock_irqrestore(&list_lock, flags);
ch = ccfg->direction == MOST_CH_TX ? &nd->tx : &nd->rx;
} else {
ch = ccfg->direction == MOST_CH_TX ? &nd->tx : &nd->rx;
if (ch->linked) {
pr_err("direction is allocated\n");
ret = -EINVAL;
goto unlock;
}
if (register_netdev(nd->dev)) {
pr_err("register_netdev() failed\n");
ret = -EINVAL;
goto unlock;
}
}
ch->ch_id = channel_idx;
ch->linked = true;
unlock:
mutex_unlock(&probe_disc_mt);
return ret;
}
static int comp_disconnect_channel(struct most_interface *iface,
int channel_idx)
{
struct net_dev_context *nd;
struct net_dev_channel *ch;
unsigned long flags;
int ret = 0;
mutex_lock(&probe_disc_mt);
nd = get_net_dev(iface);
if (!nd) {
ret = -EINVAL;
goto unlock;
}
if (nd->rx.linked && channel_idx == nd->rx.ch_id) {
ch = &nd->rx;
} else if (nd->tx.linked && channel_idx == nd->tx.ch_id) {
ch = &nd->tx;
} else {
ret = -EINVAL;
goto unlock;
}
if (nd->rx.linked && nd->tx.linked) {
spin_lock_irqsave(&list_lock, flags);
ch->linked = false;
spin_unlock_irqrestore(&list_lock, flags);
/*
* do not call most_stop_channel() here, because channels are
* going to be closed in ndo_stop() after unregister_netdev()
*/
unregister_netdev(nd->dev);
} else {
spin_lock_irqsave(&list_lock, flags);
list_del(&nd->list);
spin_unlock_irqrestore(&list_lock, flags);
free_netdev(nd->dev);
}
unlock:
mutex_unlock(&probe_disc_mt);
return ret;
}
static int comp_resume_tx_channel(struct most_interface *iface,
int channel_idx)
{
struct net_dev_context *nd;
nd = get_net_dev_hold(iface);
if (!nd)
return 0;
if (nd->tx.ch_id != channel_idx)
goto put_nd;
netif_wake_queue(nd->dev);
put_nd:
dev_put(nd->dev);
return 0;
}
static int comp_rx_data(struct mbo *mbo)
{
const u32 zero = 0;
struct net_dev_context *nd;
char *buf = mbo->virt_address;
u32 len = mbo->processed_length;
struct sk_buff *skb;
struct net_device *dev;
unsigned int skb_len;
int ret = 0;
nd = get_net_dev_hold(mbo->ifp);
if (!nd)
return -EIO;
if (nd->rx.ch_id != mbo->hdm_channel_id) {
ret = -EIO;
goto put_nd;
}
dev = nd->dev;
if (nd->is_mamac) {
if (!pms_is_mamac(buf, len)) {
ret = -EIO;
goto put_nd;
}
skb = dev_alloc_skb(len - MDP_HDR_LEN + 2 * ETH_ALEN + 2);
} else {
if (!PMS_IS_MEP(buf, len)) {
ret = -EIO;
goto put_nd;
}
skb = dev_alloc_skb(len - MEP_HDR_LEN);
}
if (!skb) {
dev->stats.rx_dropped++;
pr_err_once("drop packet: no memory for skb\n");
goto out;
}
skb->dev = dev;
if (nd->is_mamac) {
/* dest */
ether_addr_copy(skb_put(skb, ETH_ALEN), dev->dev_addr);
/* src */
skb_put_data(skb, &zero, 4);
skb_put_data(skb, buf + 5, 2);
/* eth type */
skb_put_data(skb, buf + 10, 2);
buf += MDP_HDR_LEN;
len -= MDP_HDR_LEN;
} else {
buf += MEP_HDR_LEN;
len -= MEP_HDR_LEN;
}
skb_put_data(skb, buf, len);
skb->protocol = eth_type_trans(skb, dev);
skb_len = skb->len;
if (netif_rx(skb) == NET_RX_SUCCESS) {
dev->stats.rx_packets++;
dev->stats.rx_bytes += skb_len;
} else {
dev->stats.rx_dropped++;
}
out:
most_put_mbo(mbo);
put_nd:
dev_put(nd->dev);
return ret;
}
static struct most_component comp = {
.mod = THIS_MODULE,
.name = "net",
.probe_channel = comp_probe_channel,
.disconnect_channel = comp_disconnect_channel,
.tx_completion = comp_resume_tx_channel,
.rx_completion = comp_rx_data,
};
static int __init most_net_init(void)
{
int err;
err = most_register_component(&comp);
if (err)
return err;
err = most_register_configfs_subsys(&comp);
if (err) {
most_deregister_component(&comp);
return err;
}
return 0;
}
static void __exit most_net_exit(void)
{
most_deregister_configfs_subsys(&comp);
most_deregister_component(&comp);
}
/**
* on_netinfo - callback for HDM to be informed about HW's MAC
* @iface: most interface instance
* @link_stat: link status
* @mac_addr: MAC address
*/
static void on_netinfo(struct most_interface *iface,
unsigned char link_stat, unsigned char *mac_addr)
{
struct net_dev_context *nd;
struct net_device *dev;
const u8 *m = mac_addr;
nd = get_net_dev_hold(iface);
if (!nd)
return;
dev = nd->dev;
if (link_stat)
netif_carrier_on(dev);
else
netif_carrier_off(dev);
if (m && is_valid_ether_addr(m)) {
if (!is_valid_ether_addr(dev->dev_addr)) {
netdev_info(dev, "set mac %pM\n", m);
eth_hw_addr_set(dev, m);
netif_dormant_off(dev);
} else if (!ether_addr_equal(dev->dev_addr, m)) {
netdev_warn(dev, "reject mac %pM\n", m);
}
}
dev_put(nd->dev);
}
module_init(most_net_init);
module_exit(most_net_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Shvetsov <[email protected]>");
MODULE_DESCRIPTION("Networking Component Module for Mostcore");
| linux-master | drivers/staging/most/net/net.c |
// SPDX-License-Identifier: GPL-2.0
/*
* i2c.c - Hardware Dependent Module for I2C Interface
*
* Copyright (C) 2013-2015, Microchip Technology Germany II GmbH & Co. KG
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/most.h>
enum { CH_RX, CH_TX, NUM_CHANNELS };
#define MAX_BUFFERS_CONTROL 32
#define MAX_BUF_SIZE_CONTROL 256
/**
* list_first_mbo - get the first mbo from a list
* @ptr: the list head to take the mbo from.
*/
#define list_first_mbo(ptr) \
list_first_entry(ptr, struct mbo, list)
static unsigned int polling_rate;
module_param(polling_rate, uint, 0644);
MODULE_PARM_DESC(polling_rate, "Polling rate [Hz]. Default = 0 (use IRQ)");
struct hdm_i2c {
struct most_interface most_iface;
struct most_channel_capability capabilities[NUM_CHANNELS];
struct i2c_client *client;
struct rx {
struct delayed_work dwork;
struct list_head list;
bool int_disabled;
unsigned int delay;
} rx;
char name[64];
};
static inline struct hdm_i2c *to_hdm(struct most_interface *iface)
{
return container_of(iface, struct hdm_i2c, most_iface);
}
static irqreturn_t most_irq_handler(int, void *);
static void pending_rx_work(struct work_struct *);
/**
* configure_channel - called from MOST core to configure a channel
* @most_iface: interface the channel belongs to
* @ch_idx: channel to be configured
* @channel_config: structure that holds the configuration information
*
* Return 0 on success, negative on failure.
*
* Receives configuration information from MOST core and initialize the
* corresponding channel.
*/
static int configure_channel(struct most_interface *most_iface,
int ch_idx,
struct most_channel_config *channel_config)
{
int ret;
struct hdm_i2c *dev = to_hdm(most_iface);
unsigned int delay, pr;
BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS);
if (channel_config->data_type != MOST_CH_CONTROL) {
pr_err("bad data type for channel %d\n", ch_idx);
return -EPERM;
}
if (channel_config->direction != dev->capabilities[ch_idx].direction) {
pr_err("bad direction for channel %d\n", ch_idx);
return -EPERM;
}
if (channel_config->direction == MOST_CH_RX) {
if (!polling_rate) {
if (dev->client->irq <= 0) {
pr_err("bad irq: %d\n", dev->client->irq);
return -ENOENT;
}
dev->rx.int_disabled = false;
ret = request_irq(dev->client->irq, most_irq_handler, 0,
dev->client->name, dev);
if (ret) {
pr_err("request_irq(%d) failed: %d\n",
dev->client->irq, ret);
return ret;
}
} else {
delay = msecs_to_jiffies(MSEC_PER_SEC / polling_rate);
dev->rx.delay = delay ? delay : 1;
pr = MSEC_PER_SEC / jiffies_to_msecs(dev->rx.delay);
pr_info("polling rate is %u Hz\n", pr);
}
}
return 0;
}
/**
* enqueue - called from MOST core to enqueue a buffer for data transfer
* @most_iface: intended interface
* @ch_idx: ID of the channel the buffer is intended for
* @mbo: pointer to the buffer object
*
* Return 0 on success, negative on failure.
*
* Transmit the data over I2C if it is a "write" request or push the buffer into
* list if it is an "read" request
*/
static int enqueue(struct most_interface *most_iface,
int ch_idx, struct mbo *mbo)
{
struct hdm_i2c *dev = to_hdm(most_iface);
int ret;
BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS);
if (ch_idx == CH_RX) {
/* RX */
if (!polling_rate)
disable_irq(dev->client->irq);
cancel_delayed_work_sync(&dev->rx.dwork);
list_add_tail(&mbo->list, &dev->rx.list);
if (dev->rx.int_disabled || polling_rate)
pending_rx_work(&dev->rx.dwork.work);
if (!polling_rate)
enable_irq(dev->client->irq);
} else {
/* TX */
ret = i2c_master_send(dev->client, mbo->virt_address,
mbo->buffer_length);
if (ret <= 0) {
mbo->processed_length = 0;
mbo->status = MBO_E_INVAL;
} else {
mbo->processed_length = mbo->buffer_length;
mbo->status = MBO_SUCCESS;
}
mbo->complete(mbo);
}
return 0;
}
/**
* poison_channel - called from MOST core to poison buffers of a channel
* @most_iface: pointer to the interface the channel to be poisoned belongs to
* @ch_idx: corresponding channel ID
*
* Return 0 on success, negative on failure.
*
* If channel direction is RX, complete the buffers in list with
* status MBO_E_CLOSE
*/
static int poison_channel(struct most_interface *most_iface,
int ch_idx)
{
struct hdm_i2c *dev = to_hdm(most_iface);
struct mbo *mbo;
BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS);
if (ch_idx == CH_RX) {
if (!polling_rate)
free_irq(dev->client->irq, dev);
cancel_delayed_work_sync(&dev->rx.dwork);
while (!list_empty(&dev->rx.list)) {
mbo = list_first_mbo(&dev->rx.list);
list_del(&mbo->list);
mbo->processed_length = 0;
mbo->status = MBO_E_CLOSE;
mbo->complete(mbo);
}
}
return 0;
}
static void do_rx_work(struct hdm_i2c *dev)
{
struct mbo *mbo;
unsigned char msg[MAX_BUF_SIZE_CONTROL];
int ret;
u16 pml, data_size;
/* Read PML (2 bytes) */
ret = i2c_master_recv(dev->client, msg, 2);
if (ret <= 0) {
pr_err("Failed to receive PML\n");
return;
}
pml = (msg[0] << 8) | msg[1];
if (!pml)
return;
data_size = pml + 2;
/* Read the whole message, including PML */
ret = i2c_master_recv(dev->client, msg, data_size);
if (ret <= 0) {
pr_err("Failed to receive a Port Message\n");
return;
}
mbo = list_first_mbo(&dev->rx.list);
list_del(&mbo->list);
mbo->processed_length = min(data_size, mbo->buffer_length);
memcpy(mbo->virt_address, msg, mbo->processed_length);
mbo->status = MBO_SUCCESS;
mbo->complete(mbo);
}
/**
* pending_rx_work - Read pending messages through I2C
* @work: definition of this work item
*
* Invoked by the Interrupt Service Routine, most_irq_handler()
*/
static void pending_rx_work(struct work_struct *work)
{
struct hdm_i2c *dev = container_of(work, struct hdm_i2c, rx.dwork.work);
if (list_empty(&dev->rx.list))
return;
do_rx_work(dev);
if (polling_rate) {
schedule_delayed_work(&dev->rx.dwork, dev->rx.delay);
} else {
dev->rx.int_disabled = false;
enable_irq(dev->client->irq);
}
}
/*
* most_irq_handler - Interrupt Service Routine
* @irq: irq number
* @_dev: private data
*
* Schedules a delayed work
*
* By default the interrupt line behavior is Active Low. Once an interrupt is
* generated by the device, until driver clears the interrupt (by reading
* the PMP message), device keeps the interrupt line in low state. Since i2c
* read is done in work queue, the interrupt line must be disabled temporarily
* to avoid ISR being called repeatedly. Re-enable the interrupt in workqueue,
* after reading the message.
*
* Note: If we use the interrupt line in Falling edge mode, there is a
* possibility to miss interrupts when ISR is getting executed.
*
*/
static irqreturn_t most_irq_handler(int irq, void *_dev)
{
struct hdm_i2c *dev = _dev;
disable_irq_nosync(irq);
dev->rx.int_disabled = true;
schedule_delayed_work(&dev->rx.dwork, 0);
return IRQ_HANDLED;
}
/*
* i2c_probe - i2c probe handler
* @client: i2c client device structure
* @id: i2c client device id
*
* Return 0 on success, negative on failure.
*
* Register the i2c client device as a MOST interface
*/
static int i2c_probe(struct i2c_client *client)
{
struct hdm_i2c *dev;
int ret, i;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev)
return -ENOMEM;
/* ID format: i2c-<bus>-<address> */
snprintf(dev->name, sizeof(dev->name), "i2c-%d-%04x",
client->adapter->nr, client->addr);
for (i = 0; i < NUM_CHANNELS; i++) {
dev->capabilities[i].data_type = MOST_CH_CONTROL;
dev->capabilities[i].num_buffers_packet = MAX_BUFFERS_CONTROL;
dev->capabilities[i].buffer_size_packet = MAX_BUF_SIZE_CONTROL;
}
dev->capabilities[CH_RX].direction = MOST_CH_RX;
dev->capabilities[CH_RX].name_suffix = "rx";
dev->capabilities[CH_TX].direction = MOST_CH_TX;
dev->capabilities[CH_TX].name_suffix = "tx";
dev->most_iface.interface = ITYPE_I2C;
dev->most_iface.description = dev->name;
dev->most_iface.num_channels = NUM_CHANNELS;
dev->most_iface.channel_vector = dev->capabilities;
dev->most_iface.configure = configure_channel;
dev->most_iface.enqueue = enqueue;
dev->most_iface.poison_channel = poison_channel;
INIT_LIST_HEAD(&dev->rx.list);
INIT_DELAYED_WORK(&dev->rx.dwork, pending_rx_work);
dev->client = client;
i2c_set_clientdata(client, dev);
ret = most_register_interface(&dev->most_iface);
if (ret) {
pr_err("Failed to register i2c as a MOST interface\n");
kfree(dev);
return ret;
}
return 0;
}
/*
* i2c_remove - i2c remove handler
* @client: i2c client device structure
*
* Return 0 on success.
*
* Unregister the i2c client device as a MOST interface
*/
static void i2c_remove(struct i2c_client *client)
{
struct hdm_i2c *dev = i2c_get_clientdata(client);
most_deregister_interface(&dev->most_iface);
kfree(dev);
}
static const struct i2c_device_id i2c_id[] = {
{ "most_i2c", 0 },
{ }, /* Terminating entry */
};
MODULE_DEVICE_TABLE(i2c, i2c_id);
static struct i2c_driver i2c_driver = {
.driver = {
.name = "hdm_i2c",
},
.probe = i2c_probe,
.remove = i2c_remove,
.id_table = i2c_id,
};
module_i2c_driver(i2c_driver);
MODULE_AUTHOR("Andrey Shvetsov <[email protected]>");
MODULE_DESCRIPTION("I2C Hardware Dependent Module");
MODULE_LICENSE("GPL");
| linux-master | drivers/staging/most/i2c/i2c.c |
// SPDX-License-Identifier: GPL-2.0
#include "ddk750_reg.h"
#include "ddk750_mode.h"
#include "ddk750_chip.h"
/*
* SM750LE only:
* This function takes care extra registers and bit fields required to set
* up a mode in SM750LE
*
* Explanation about Display Control register:
* HW only supports 7 predefined pixel clocks, and clock select is
* in bit 29:27 of Display Control register.
*/
static unsigned long
displayControlAdjust_SM750LE(struct mode_parameter *pModeParam,
unsigned long dispControl)
{
unsigned long x, y;
x = pModeParam->horizontal_display_end;
y = pModeParam->vertical_display_end;
/*
* SM750LE has to set up the top-left and bottom-right
* registers as well.
* Note that normal SM750/SM718 only use those two register for
* auto-centering mode.
*/
poke32(CRT_AUTO_CENTERING_TL, 0);
poke32(CRT_AUTO_CENTERING_BR,
(((y - 1) << CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT) &
CRT_AUTO_CENTERING_BR_BOTTOM_MASK) |
((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK));
/*
* Assume common fields in dispControl have been properly set before
* calling this function.
* This function only sets the extra fields in dispControl.
*/
/* Clear bit 29:27 of display control register */
dispControl &= ~CRT_DISPLAY_CTRL_CLK_MASK;
/* Set bit 29:27 of display control register for the right clock */
/* Note that SM750LE only need to supported 7 resolutions. */
if (x == 800 && y == 600)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL41;
else if (x == 1024 && y == 768)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL65;
else if (x == 1152 && y == 864)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
else if (x == 1280 && y == 768)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL80;
else if (x == 1280 && y == 720)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL74;
else if (x == 1280 && y == 960)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
else if (x == 1280 && y == 1024)
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL108;
else /* default to VGA clock */
dispControl |= CRT_DISPLAY_CTRL_CLK_PLL25;
/* Set bit 25:24 of display controller */
dispControl |= (CRT_DISPLAY_CTRL_CRTSELECT | CRT_DISPLAY_CTRL_RGBBIT);
/* Set bit 14 of display controller */
dispControl |= DISPLAY_CTRL_CLOCK_PHASE;
poke32(CRT_DISPLAY_CTRL, dispControl);
return dispControl;
}
/* only timing related registers will be programed */
static int programModeRegisters(struct mode_parameter *pModeParam,
struct pll_value *pll)
{
int ret = 0;
int cnt = 0;
unsigned int tmp, reg;
if (pll->clock_type == SECONDARY_PLL) {
/* programe secondary pixel clock */
poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll));
tmp = ((pModeParam->horizontal_total - 1) <<
CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
CRT_HORIZONTAL_TOTAL_TOTAL_MASK;
tmp |= (pModeParam->horizontal_display_end - 1) &
CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK;
poke32(CRT_HORIZONTAL_TOTAL, tmp);
tmp = (pModeParam->horizontal_sync_width <<
CRT_HORIZONTAL_SYNC_WIDTH_SHIFT) &
CRT_HORIZONTAL_SYNC_WIDTH_MASK;
tmp |= (pModeParam->horizontal_sync_start - 1) &
CRT_HORIZONTAL_SYNC_START_MASK;
poke32(CRT_HORIZONTAL_SYNC, tmp);
tmp = ((pModeParam->vertical_total - 1) <<
CRT_VERTICAL_TOTAL_TOTAL_SHIFT) &
CRT_VERTICAL_TOTAL_TOTAL_MASK;
tmp |= (pModeParam->vertical_display_end - 1) &
CRT_VERTICAL_TOTAL_DISPLAY_END_MASK;
poke32(CRT_VERTICAL_TOTAL, tmp);
tmp = ((pModeParam->vertical_sync_height <<
CRT_VERTICAL_SYNC_HEIGHT_SHIFT)) &
CRT_VERTICAL_SYNC_HEIGHT_MASK;
tmp |= (pModeParam->vertical_sync_start - 1) &
CRT_VERTICAL_SYNC_START_MASK;
poke32(CRT_VERTICAL_SYNC, tmp);
tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
if (pModeParam->vertical_sync_polarity)
tmp |= DISPLAY_CTRL_VSYNC_PHASE;
if (pModeParam->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE;
if (sm750_get_chip_type() == SM750LE) {
displayControlAdjust_SM750LE(pModeParam, tmp);
} else {
reg = peek32(CRT_DISPLAY_CTRL) &
~(DISPLAY_CTRL_VSYNC_PHASE |
DISPLAY_CTRL_HSYNC_PHASE |
DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE);
poke32(CRT_DISPLAY_CTRL, tmp | reg);
}
} else if (pll->clock_type == PRIMARY_PLL) {
unsigned int reserved;
poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll));
reg = ((pModeParam->horizontal_total - 1) <<
PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT) &
PANEL_HORIZONTAL_TOTAL_TOTAL_MASK;
reg |= ((pModeParam->horizontal_display_end - 1) &
PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK);
poke32(PANEL_HORIZONTAL_TOTAL, reg);
poke32(PANEL_HORIZONTAL_SYNC,
((pModeParam->horizontal_sync_width <<
PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT) &
PANEL_HORIZONTAL_SYNC_WIDTH_MASK) |
((pModeParam->horizontal_sync_start - 1) &
PANEL_HORIZONTAL_SYNC_START_MASK));
poke32(PANEL_VERTICAL_TOTAL,
(((pModeParam->vertical_total - 1) <<
PANEL_VERTICAL_TOTAL_TOTAL_SHIFT) &
PANEL_VERTICAL_TOTAL_TOTAL_MASK) |
((pModeParam->vertical_display_end - 1) &
PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK));
poke32(PANEL_VERTICAL_SYNC,
((pModeParam->vertical_sync_height <<
PANEL_VERTICAL_SYNC_HEIGHT_SHIFT) &
PANEL_VERTICAL_SYNC_HEIGHT_MASK) |
((pModeParam->vertical_sync_start - 1) &
PANEL_VERTICAL_SYNC_START_MASK));
tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
if (pModeParam->vertical_sync_polarity)
tmp |= DISPLAY_CTRL_VSYNC_PHASE;
if (pModeParam->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE;
if (pModeParam->clock_phase_polarity)
tmp |= DISPLAY_CTRL_CLOCK_PHASE;
reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK |
PANEL_DISPLAY_CTRL_VSYNC;
reg = (peek32(PANEL_DISPLAY_CTRL) & ~reserved) &
~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE |
DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING |
DISPLAY_CTRL_PLANE);
/*
* May a hardware bug or just my test chip (not confirmed).
* PANEL_DISPLAY_CTRL register seems requiring few writes
* before a value can be successfully written in.
* Added some masks to mask out the reserved bits.
* Note: This problem happens by design. The hardware will wait
* for the next vertical sync to turn on/off the plane.
*/
poke32(PANEL_DISPLAY_CTRL, tmp | reg);
while ((peek32(PANEL_DISPLAY_CTRL) & ~reserved) !=
(tmp | reg)) {
cnt++;
if (cnt > 1000)
break;
poke32(PANEL_DISPLAY_CTRL, tmp | reg);
}
} else {
ret = -1;
}
return ret;
}
int ddk750_setModeTiming(struct mode_parameter *parm, enum clock_type clock)
{
struct pll_value pll;
pll.input_freq = DEFAULT_INPUT_CLOCK;
pll.clock_type = clock;
sm750_calc_pll_value(parm->pixel_clock, &pll);
if (sm750_get_chip_type() == SM750LE) {
/* set graphic mode via IO method */
outb_p(0x88, 0x3d4);
outb_p(0x06, 0x3d5);
}
programModeRegisters(parm, &pll);
return 0;
}
| linux-master | drivers/staging/sm750fb/ddk750_mode.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
*
* swi2c.c --- SM750/SM718 DDK
* This file contains the source code for I2C using software
* implementation.
*/
#include "ddk750_chip.h"
#include "ddk750_reg.h"
#include "ddk750_swi2c.h"
#include "ddk750_power.h"
/*
* I2C Software Master Driver:
* ===========================
* Each i2c cycle is split into 4 sections. Each of these section marks
* a point in time where the SCL or SDA may be changed.
*
* 1 Cycle == | Section I. | Section 2. | Section 3. | Section 4. |
* +-------------+-------------+-------------+-------------+
* | SCL set LOW |SCL no change| SCL set HIGH|SCL no change|
*
* ____________ _____________
* SCL == XXXX _____________ ____________ /
*
* I.e. the SCL may only be changed in section 1. and section 3. while
* the SDA may only be changed in section 2. and section 4. The table
* below gives the changes for these 2 lines in the varios sections.
*
* Section changes Table:
* ======================
* blank = no change, L = set bit LOW, H = set bit HIGH
*
* | 1.| 2.| 3.| 4.|
* ---------------+---+---+---+---+
* Tx Start SDA | | H | | L |
* SCL | L | | H | |
* ---------------+---+---+---+---+
* Tx Stop SDA | | L | | H |
* SCL | L | | H | |
* ---------------+---+---+---+---+
* Tx bit H SDA | | H | | |
* SCL | L | | H | |
* ---------------+---+---+---+---+
* Tx bit L SDA | | L | | |
* SCL | L | | H | |
* ---------------+---+---+---+---+
*
*/
/* GPIO pins used for this I2C. It ranges from 0 to 63. */
static unsigned char sw_i2c_clk_gpio = DEFAULT_I2C_SCL;
static unsigned char sw_i2c_data_gpio = DEFAULT_I2C_SDA;
/*
* Below is the variable declaration for the GPIO pin register usage
* for the i2c Clock and i2c Data.
*
* Note:
* Notice that the GPIO usage for the i2c clock and i2c Data are
* separated. This is to make this code flexible enough when
* two separate GPIO pins for the clock and data are located
* in two different GPIO register set (worst case).
*/
/* i2c Clock GPIO Register usage */
static unsigned long sw_i2c_clk_gpio_mux_reg = GPIO_MUX;
static unsigned long sw_i2c_clk_gpio_data_reg = GPIO_DATA;
static unsigned long sw_i2c_clk_gpio_data_dir_reg = GPIO_DATA_DIRECTION;
/* i2c Data GPIO Register usage */
static unsigned long sw_i2c_data_gpio_mux_reg = GPIO_MUX;
static unsigned long sw_i2c_data_gpio_data_reg = GPIO_DATA;
static unsigned long sw_i2c_data_gpio_data_dir_reg = GPIO_DATA_DIRECTION;
/*
* This function puts a delay between command
*/
static void sw_i2c_wait(void)
{
/* find a bug:
* peekIO method works well before suspend/resume
* but after suspend, peekIO(0x3ce,0x61) & 0x10
* always be non-zero,which makes the while loop
* never finish.
* use non-ultimate for loop below is safe
*/
/* Change wait algorithm to use PCI bus clock,
* it's more reliable than counter loop ..
* write 0x61 to 0x3ce and read from 0x3cf
*/
int i, tmp;
for (i = 0; i < 600; i++) {
tmp = i;
tmp += i;
}
}
/*
* This function set/reset the SCL GPIO pin
*
* Parameters:
* value - Bit value to set to the SCL or SDA (0 = low, 1 = high)
*
* Notes:
* When setting SCL to high, just set the GPIO as input where the pull up
* resistor will pull the signal up. Do not use software to pull up the
* signal because the i2c will fail when other device try to drive the
* signal due to SM50x will drive the signal to always high.
*/
static void sw_i2c_scl(unsigned char value)
{
unsigned long gpio_data;
unsigned long gpio_dir;
gpio_dir = peek32(sw_i2c_clk_gpio_data_dir_reg);
if (value) { /* High */
/*
* Set direction as input. This will automatically
* pull the signal up.
*/
gpio_dir &= ~(1 << sw_i2c_clk_gpio);
poke32(sw_i2c_clk_gpio_data_dir_reg, gpio_dir);
} else { /* Low */
/* Set the signal down */
gpio_data = peek32(sw_i2c_clk_gpio_data_reg);
gpio_data &= ~(1 << sw_i2c_clk_gpio);
poke32(sw_i2c_clk_gpio_data_reg, gpio_data);
/* Set direction as output */
gpio_dir |= (1 << sw_i2c_clk_gpio);
poke32(sw_i2c_clk_gpio_data_dir_reg, gpio_dir);
}
}
/*
* This function set/reset the SDA GPIO pin
*
* Parameters:
* value - Bit value to set to the SCL or SDA (0 = low, 1 = high)
*
* Notes:
* When setting SCL to high, just set the GPIO as input where the pull up
* resistor will pull the signal up. Do not use software to pull up the
* signal because the i2c will fail when other device try to drive the
* signal due to SM50x will drive the signal to always high.
*/
static void sw_i2c_sda(unsigned char value)
{
unsigned long gpio_data;
unsigned long gpio_dir;
gpio_dir = peek32(sw_i2c_data_gpio_data_dir_reg);
if (value) { /* High */
/*
* Set direction as input. This will automatically
* pull the signal up.
*/
gpio_dir &= ~(1 << sw_i2c_data_gpio);
poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
} else { /* Low */
/* Set the signal down */
gpio_data = peek32(sw_i2c_data_gpio_data_reg);
gpio_data &= ~(1 << sw_i2c_data_gpio);
poke32(sw_i2c_data_gpio_data_reg, gpio_data);
/* Set direction as output */
gpio_dir |= (1 << sw_i2c_data_gpio);
poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
}
}
/*
* This function read the data from the SDA GPIO pin
*
* Return Value:
* The SDA data bit sent by the Slave
*/
static unsigned char sw_i2c_read_sda(void)
{
unsigned long gpio_dir;
unsigned long gpio_data;
unsigned long dir_mask = 1 << sw_i2c_data_gpio;
/* Make sure that the direction is input (High) */
gpio_dir = peek32(sw_i2c_data_gpio_data_dir_reg);
if ((gpio_dir & dir_mask) != ~dir_mask) {
gpio_dir &= ~(1 << sw_i2c_data_gpio);
poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
}
/* Now read the SDA line */
gpio_data = peek32(sw_i2c_data_gpio_data_reg);
if (gpio_data & (1 << sw_i2c_data_gpio))
return 1;
else
return 0;
}
/*
* This function sends ACK signal
*/
static void sw_i2c_ack(void)
{
return; /* Single byte read is ok without it. */
}
/*
* This function sends the start command to the slave device
*/
static void sw_i2c_start(void)
{
/* Start I2C */
sw_i2c_sda(1);
sw_i2c_scl(1);
sw_i2c_sda(0);
}
/*
* This function sends the stop command to the slave device
*/
static void sw_i2c_stop(void)
{
/* Stop the I2C */
sw_i2c_scl(1);
sw_i2c_sda(0);
sw_i2c_sda(1);
}
/*
* This function writes one byte to the slave device
*
* Parameters:
* data - Data to be write to the slave device
*
* Return Value:
* 0 - Success
* -1 - Fail to write byte
*/
static long sw_i2c_write_byte(unsigned char data)
{
unsigned char value = data;
int i;
/* Sending the data bit by bit */
for (i = 0; i < 8; i++) {
/* Set SCL to low */
sw_i2c_scl(0);
/* Send data bit */
if ((value & 0x80) != 0)
sw_i2c_sda(1);
else
sw_i2c_sda(0);
sw_i2c_wait();
/* Toggle clk line to one */
sw_i2c_scl(1);
sw_i2c_wait();
/* Shift byte to be sent */
value = value << 1;
}
/* Set the SCL Low and SDA High (prepare to get input) */
sw_i2c_scl(0);
sw_i2c_sda(1);
/* Set the SCL High for ack */
sw_i2c_wait();
sw_i2c_scl(1);
sw_i2c_wait();
/* Read SDA, until SDA==0 */
for (i = 0; i < 0xff; i++) {
if (!sw_i2c_read_sda())
break;
sw_i2c_scl(0);
sw_i2c_wait();
sw_i2c_scl(1);
sw_i2c_wait();
}
/* Set the SCL Low and SDA High */
sw_i2c_scl(0);
sw_i2c_sda(1);
if (i < 0xff)
return 0;
else
return -1;
}
/*
* This function reads one byte from the slave device
*
* Parameters:
* ack - Flag to indicate either to send the acknowledge
* message to the slave device or not
*
* Return Value:
* One byte data read from the Slave device
*/
static unsigned char sw_i2c_read_byte(unsigned char ack)
{
int i;
unsigned char data = 0;
for (i = 7; i >= 0; i--) {
/* Set the SCL to Low and SDA to High (Input) */
sw_i2c_scl(0);
sw_i2c_sda(1);
sw_i2c_wait();
/* Set the SCL High */
sw_i2c_scl(1);
sw_i2c_wait();
/* Read data bits from SDA */
data |= (sw_i2c_read_sda() << i);
}
if (ack)
sw_i2c_ack();
/* Set the SCL Low and SDA High */
sw_i2c_scl(0);
sw_i2c_sda(1);
return data;
}
/*
* This function initializes GPIO port for SW I2C communication.
*
* Parameters:
* clk_gpio - The GPIO pin to be used as i2c SCL
* data_gpio - The GPIO pin to be used as i2c SDA
*
* Return Value:
* -1 - Fail to initialize the i2c
* 0 - Success
*/
static long sm750le_i2c_init(unsigned char clk_gpio, unsigned char data_gpio)
{
int i;
/* Initialize the GPIO pin for the i2c Clock Register */
sw_i2c_clk_gpio_data_reg = GPIO_DATA_SM750LE;
sw_i2c_clk_gpio_data_dir_reg = GPIO_DATA_DIRECTION_SM750LE;
/* Initialize the Clock GPIO Offset */
sw_i2c_clk_gpio = clk_gpio;
/* Initialize the GPIO pin for the i2c Data Register */
sw_i2c_data_gpio_data_reg = GPIO_DATA_SM750LE;
sw_i2c_data_gpio_data_dir_reg = GPIO_DATA_DIRECTION_SM750LE;
/* Initialize the Data GPIO Offset */
sw_i2c_data_gpio = data_gpio;
/* Note that SM750LE don't have GPIO MUX and power is always on */
/* Clear the i2c lines. */
for (i = 0; i < 9; i++)
sw_i2c_stop();
return 0;
}
/*
* This function initializes the i2c attributes and bus
*
* Parameters:
* clk_gpio - The GPIO pin to be used as i2c SCL
* data_gpio - The GPIO pin to be used as i2c SDA
*
* Return Value:
* -1 - Fail to initialize the i2c
* 0 - Success
*/
long sm750_sw_i2c_init(unsigned char clk_gpio, unsigned char data_gpio)
{
int i;
/*
* Return 0 if the GPIO pins to be used is out of range. The
* range is only from [0..63]
*/
if ((clk_gpio > 31) || (data_gpio > 31))
return -1;
if (sm750_get_chip_type() == SM750LE)
return sm750le_i2c_init(clk_gpio, data_gpio);
/* Initialize the GPIO pin for the i2c Clock Register */
sw_i2c_clk_gpio_mux_reg = GPIO_MUX;
sw_i2c_clk_gpio_data_reg = GPIO_DATA;
sw_i2c_clk_gpio_data_dir_reg = GPIO_DATA_DIRECTION;
/* Initialize the Clock GPIO Offset */
sw_i2c_clk_gpio = clk_gpio;
/* Initialize the GPIO pin for the i2c Data Register */
sw_i2c_data_gpio_mux_reg = GPIO_MUX;
sw_i2c_data_gpio_data_reg = GPIO_DATA;
sw_i2c_data_gpio_data_dir_reg = GPIO_DATA_DIRECTION;
/* Initialize the Data GPIO Offset */
sw_i2c_data_gpio = data_gpio;
/* Enable the GPIO pins for the i2c Clock and Data (GPIO MUX) */
poke32(sw_i2c_clk_gpio_mux_reg,
peek32(sw_i2c_clk_gpio_mux_reg) & ~(1 << sw_i2c_clk_gpio));
poke32(sw_i2c_data_gpio_mux_reg,
peek32(sw_i2c_data_gpio_mux_reg) & ~(1 << sw_i2c_data_gpio));
/* Enable GPIO power */
sm750_enable_gpio(1);
/* Clear the i2c lines. */
for (i = 0; i < 9; i++)
sw_i2c_stop();
return 0;
}
/*
* This function reads the slave device's register
*
* Parameters:
* addr - i2c Slave device address which register
* to be read from
* reg - Slave device's register to be read
*
* Return Value:
* Register value
*/
unsigned char sm750_sw_i2c_read_reg(unsigned char addr, unsigned char reg)
{
unsigned char data;
/* Send the Start signal */
sw_i2c_start();
/* Send the device address */
sw_i2c_write_byte(addr);
/* Send the register index */
sw_i2c_write_byte(reg);
/* Get the bus again and get the data from the device read address */
sw_i2c_start();
sw_i2c_write_byte(addr + 1);
data = sw_i2c_read_byte(1);
/* Stop swI2C and release the bus */
sw_i2c_stop();
return data;
}
/*
* This function writes a value to the slave device's register
*
* Parameters:
* addr - i2c Slave device address which register
* to be written
* reg - Slave device's register to be written
* data - Data to be written to the register
*
* Result:
* 0 - Success
* -1 - Fail
*/
long sm750_sw_i2c_write_reg(unsigned char addr,
unsigned char reg,
unsigned char data)
{
long ret = 0;
/* Send the Start signal */
sw_i2c_start();
/* Send the device address and read the data. All should return success
* in order for the writing processed to be successful
*/
if ((sw_i2c_write_byte(addr) != 0) ||
(sw_i2c_write_byte(reg) != 0) ||
(sw_i2c_write_byte(data) != 0)) {
ret = -1;
}
/* Stop i2c and release the bus */
sw_i2c_stop();
return ret;
}
| linux-master | drivers/staging/sm750fb/ddk750_swi2c.c |
// SPDX-License-Identifier: GPL-2.0
#define USE_HW_I2C
#ifdef USE_HW_I2C
#include "ddk750_chip.h"
#include "ddk750_reg.h"
#include "ddk750_hwi2c.h"
#include "ddk750_power.h"
#define MAX_HWI2C_FIFO 16
#define HWI2C_WAIT_TIMEOUT 0xF0000
int sm750_hw_i2c_init(unsigned char bus_speed_mode)
{
unsigned int value;
/* Enable GPIO 30 & 31 as IIC clock & data */
value = peek32(GPIO_MUX);
value |= (GPIO_MUX_30 | GPIO_MUX_31);
poke32(GPIO_MUX, value);
/*
* Enable Hardware I2C power.
* TODO: Check if we need to enable GPIO power?
*/
sm750_enable_i2c(1);
/* Enable the I2C Controller and set the bus speed mode */
value = peek32(I2C_CTRL) & ~(I2C_CTRL_MODE | I2C_CTRL_EN);
if (bus_speed_mode)
value |= I2C_CTRL_MODE;
value |= I2C_CTRL_EN;
poke32(I2C_CTRL, value);
return 0;
}
void sm750_hw_i2c_close(void)
{
unsigned int value;
/* Disable I2C controller */
value = peek32(I2C_CTRL) & ~I2C_CTRL_EN;
poke32(I2C_CTRL, value);
/* Disable I2C Power */
sm750_enable_i2c(0);
/* Set GPIO 30 & 31 back as GPIO pins */
value = peek32(GPIO_MUX);
value &= ~GPIO_MUX_30;
value &= ~GPIO_MUX_31;
poke32(GPIO_MUX, value);
}
static long hw_i2c_wait_tx_done(void)
{
unsigned int timeout;
/* Wait until the transfer is completed. */
timeout = HWI2C_WAIT_TIMEOUT;
while (!(peek32(I2C_STATUS) & I2C_STATUS_TX) && (timeout != 0))
timeout--;
if (timeout == 0)
return -1;
return 0;
}
/*
* This function writes data to the i2c slave device registers.
*
* Parameters:
* addr - i2c Slave device address
* length - Total number of bytes to be written to the device
* buf - The buffer that contains the data to be written to the
* i2c device.
*
* Return Value:
* Total number of bytes those are actually written.
*/
static unsigned int hw_i2c_write_data(unsigned char addr,
unsigned int length,
unsigned char *buf)
{
unsigned char count, i;
unsigned int total_bytes = 0;
/* Set the Device Address */
poke32(I2C_SLAVE_ADDRESS, addr & ~0x01);
/*
* Write data.
* Note:
* Only 16 byte can be accessed per i2c start instruction.
*/
do {
/*
* Reset I2C by writing 0 to I2C_RESET register to
* clear the previous status.
*/
poke32(I2C_RESET, 0);
/* Set the number of bytes to be written */
if (length < MAX_HWI2C_FIFO)
count = length - 1;
else
count = MAX_HWI2C_FIFO - 1;
poke32(I2C_BYTE_COUNT, count);
/* Move the data to the I2C data register */
for (i = 0; i <= count; i++)
poke32(I2C_DATA0 + i, *buf++);
/* Start the I2C */
poke32(I2C_CTRL, peek32(I2C_CTRL) | I2C_CTRL_CTRL);
/* Wait until the transfer is completed. */
if (hw_i2c_wait_tx_done() != 0)
break;
/* Subtract length */
length -= (count + 1);
/* Total byte written */
total_bytes += (count + 1);
} while (length > 0);
return total_bytes;
}
/*
* This function reads data from the slave device and stores them
* in the given buffer
*
* Parameters:
* addr - i2c Slave device address
* length - Total number of bytes to be read
* buf - Pointer to a buffer to be filled with the data read
* from the slave device. It has to be the same size as the
* length to make sure that it can keep all the data read.
*
* Return Value:
* Total number of actual bytes read from the slave device
*/
static unsigned int hw_i2c_read_data(unsigned char addr,
unsigned int length,
unsigned char *buf)
{
unsigned char count, i;
unsigned int total_bytes = 0;
/* Set the Device Address */
poke32(I2C_SLAVE_ADDRESS, addr | 0x01);
/*
* Read data and save them to the buffer.
* Note:
* Only 16 byte can be accessed per i2c start instruction.
*/
do {
/*
* Reset I2C by writing 0 to I2C_RESET register to
* clear all the status.
*/
poke32(I2C_RESET, 0);
/* Set the number of bytes to be read */
if (length <= MAX_HWI2C_FIFO)
count = length - 1;
else
count = MAX_HWI2C_FIFO - 1;
poke32(I2C_BYTE_COUNT, count);
/* Start the I2C */
poke32(I2C_CTRL, peek32(I2C_CTRL) | I2C_CTRL_CTRL);
/* Wait until transaction done. */
if (hw_i2c_wait_tx_done() != 0)
break;
/* Save the data to the given buffer */
for (i = 0; i <= count; i++)
*buf++ = peek32(I2C_DATA0 + i);
/* Subtract length by 16 */
length -= (count + 1);
/* Number of bytes read. */
total_bytes += (count + 1);
} while (length > 0);
return total_bytes;
}
/*
* This function reads the slave device's register
*
* Parameters:
* deviceAddress - i2c Slave device address which register
* to be read from
* registerIndex - Slave device's register to be read
*
* Return Value:
* Register value
*/
unsigned char sm750_hw_i2c_read_reg(unsigned char addr, unsigned char reg)
{
unsigned char value = 0xFF;
if (hw_i2c_write_data(addr, 1, ®) == 1)
hw_i2c_read_data(addr, 1, &value);
return value;
}
/*
* This function writes a value to the slave device's register
*
* Parameters:
* deviceAddress - i2c Slave device address which register
* to be written
* registerIndex - Slave device's register to be written
* data - Data to be written to the register
*
* Result:
* 0 - Success
* -1 - Fail
*/
int sm750_hw_i2c_write_reg(unsigned char addr,
unsigned char reg,
unsigned char data)
{
unsigned char value[2];
value[0] = reg;
value[1] = data;
if (hw_i2c_write_data(addr, 2, value) == 2)
return 0;
return -1;
}
#endif
| linux-master | drivers/staging/sm750fb/ddk750_hwi2c.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/kernel.h>
#include <linux/sizes.h>
#include "ddk750_reg.h"
#include "ddk750_chip.h"
#include "ddk750_power.h"
#define MHz(x) ((x) * 1000000)
static enum logical_chip_type chip;
enum logical_chip_type sm750_get_chip_type(void)
{
return chip;
}
void sm750_set_chip_type(unsigned short dev_id, u8 rev_id)
{
if (dev_id == 0x718) {
chip = SM718;
} else if (dev_id == 0x750) {
chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */
if (rev_id == SM750LE_REVISION_ID) {
chip = SM750LE;
pr_info("found sm750le\n");
}
} else {
chip = SM_UNKNOWN;
}
}
static unsigned int get_mxclk_freq(void)
{
unsigned int pll_reg;
unsigned int M, N, OD, POD;
if (sm750_get_chip_type() == SM750LE)
return MHz(130);
pll_reg = peek32(MXCLK_PLL_CTRL);
M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_N_SHIFT;
OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT;
POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT;
return DEFAULT_INPUT_CLOCK * M / N / BIT(OD) / BIT(POD);
}
/*
* This function set up the main chip clock.
*
* Input: Frequency to be set.
*/
static void set_chip_clock(unsigned int frequency)
{
struct pll_value pll;
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
if (sm750_get_chip_type() == SM750LE)
return;
if (frequency) {
/*
* Set up PLL structure to hold the value to be set in clocks.
*/
pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
pll.clock_type = MXCLK_PLL;
/*
* Call sm750_calc_pll_value() to fill the other fields
* of the PLL structure. Sometimes, the chip cannot set
* up the exact clock required by the User.
* Return value of sm750_calc_pll_value gives the actual
* possible clock.
*/
sm750_calc_pll_value(frequency, &pll);
/* Master Clock Control: MXCLK_PLL */
poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll));
}
}
static void set_memory_clock(unsigned int frequency)
{
unsigned int reg, divisor;
/*
* Cheok_0509: For SM750LE, the memory clock is fixed.
* Nothing to set.
*/
if (sm750_get_chip_type() == SM750LE)
return;
if (frequency) {
/*
* Set the frequency to the maximum frequency
* that the DDR Memory can take which is 336MHz.
*/
if (frequency > MHz(336))
frequency = MHz(336);
/* Calculate the divisor */
divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
switch (divisor) {
default:
case 1:
reg |= CURRENT_GATE_M2XCLK_DIV_1;
break;
case 2:
reg |= CURRENT_GATE_M2XCLK_DIV_2;
break;
case 3:
reg |= CURRENT_GATE_M2XCLK_DIV_3;
break;
case 4:
reg |= CURRENT_GATE_M2XCLK_DIV_4;
break;
}
sm750_set_current_gate(reg);
}
}
/*
* This function set up the master clock (MCLK).
*
* Input: Frequency to be set.
*
* NOTE:
* The maximum frequency the engine can run is 168MHz.
*/
static void set_master_clock(unsigned int frequency)
{
unsigned int reg, divisor;
/*
* Cheok_0509: For SM750LE, the memory clock is fixed.
* Nothing to set.
*/
if (sm750_get_chip_type() == SM750LE)
return;
if (frequency) {
/*
* Set the frequency to the maximum frequency
* that the SM750 engine can run, which is about 190 MHz.
*/
if (frequency > MHz(190))
frequency = MHz(190);
/* Calculate the divisor */
divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK;
switch (divisor) {
default:
case 3:
reg |= CURRENT_GATE_MCLK_DIV_3;
break;
case 4:
reg |= CURRENT_GATE_MCLK_DIV_4;
break;
case 6:
reg |= CURRENT_GATE_MCLK_DIV_6;
break;
case 8:
reg |= CURRENT_GATE_MCLK_DIV_8;
break;
}
sm750_set_current_gate(reg);
}
}
unsigned int ddk750_get_vm_size(void)
{
unsigned int reg;
unsigned int data;
/* sm750le only use 64 mb memory*/
if (sm750_get_chip_type() == SM750LE)
return SZ_64M;
/* for 750,always use power mode0*/
reg = peek32(MODE0_GATE);
reg |= MODE0_GATE_GPIO;
poke32(MODE0_GATE, reg);
/* get frame buffer size from GPIO */
reg = peek32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK;
switch (reg) {
case MISC_CTRL_LOCALMEM_SIZE_8M:
data = SZ_8M; break; /* 8 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_16M:
data = SZ_16M; break; /* 16 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_32M:
data = SZ_32M; break; /* 32 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_64M:
data = SZ_64M; break; /* 64 Mega byte */
default:
data = 0;
break;
}
return data;
}
int ddk750_init_hw(struct initchip_param *p_init_param)
{
unsigned int reg;
if (p_init_param->power_mode != 0)
p_init_param->power_mode = 0;
sm750_set_power_mode(p_init_param->power_mode);
/* Enable display power gate & LOCALMEM power gate*/
reg = peek32(CURRENT_GATE);
reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
sm750_set_current_gate(reg);
if (sm750_get_chip_type() != SM750LE) {
/* set panel pll and graphic mode via mmio_88 */
reg = peek32(VGA_CONFIGURATION);
reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
poke32(VGA_CONFIGURATION, reg);
} else {
#if defined(__i386__) || defined(__x86_64__)
/* set graphic mode via IO method */
outb_p(0x88, 0x3d4);
outb_p(0x06, 0x3d5);
#endif
}
/* Set the Main Chip Clock */
set_chip_clock(MHz((unsigned int)p_init_param->chip_clock));
/* Set up memory clock. */
set_memory_clock(MHz(p_init_param->mem_clock));
/* Set up master clock */
set_master_clock(MHz(p_init_param->master_clock));
/*
* Reset the memory controller.
* If the memory controller is not reset in SM750,
* the system might hang when sw accesses the memory.
* The memory should be resetted after changing the MXCLK.
*/
if (p_init_param->reset_memory == 1) {
reg = peek32(MISC_CTRL);
reg &= ~MISC_CTRL_LOCALMEM_RESET;
poke32(MISC_CTRL, reg);
reg |= MISC_CTRL_LOCALMEM_RESET;
poke32(MISC_CTRL, reg);
}
if (p_init_param->set_all_eng_off == 1) {
sm750_enable_2d_engine(0);
/* Disable Overlay, if a former application left it on */
reg = peek32(VIDEO_DISPLAY_CTRL);
reg &= ~DISPLAY_CTRL_PLANE;
poke32(VIDEO_DISPLAY_CTRL, reg);
/* Disable video alpha, if a former application left it on */
reg = peek32(VIDEO_ALPHA_DISPLAY_CTRL);
reg &= ~DISPLAY_CTRL_PLANE;
poke32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
/* Disable alpha plane, if a former application left it on */
reg = peek32(ALPHA_DISPLAY_CTRL);
reg &= ~DISPLAY_CTRL_PLANE;
poke32(ALPHA_DISPLAY_CTRL, reg);
/* Disable DMA Channel, if a former application left it on */
reg = peek32(DMA_ABORT_INTERRUPT);
reg |= DMA_ABORT_INTERRUPT_ABORT_1;
poke32(DMA_ABORT_INTERRUPT, reg);
/* Disable DMA Power, if a former application left it on */
sm750_enable_dma(0);
}
/* We can add more initialization as needed. */
return 0;
}
/*
* monk liu @ 4/6/2011:
* re-write the calculatePLL function of ddk750.
* the original version function does not use
* some mathematics tricks and shortcut
* when it doing the calculation of the best N,M,D combination
* I think this version gives a little upgrade in speed
*
* 750 pll clock formular:
* Request Clock = (Input Clock * M )/(N * X)
*
* Input Clock = 14318181 hz
* X = 2 power D
* D ={0,1,2,3,4,5,6}
* M = {1,...,255}
* N = {2,...,15}
*/
unsigned int sm750_calc_pll_value(unsigned int request_orig,
struct pll_value *pll)
{
/*
* as sm750 register definition,
* N located in 2,15 and M located in 1,255
*/
int N, M, X, d;
int mini_diff;
unsigned int RN, quo, rem, fl_quo;
unsigned int input, request;
unsigned int tmp_clock, ret;
const int max_OD = 3;
int max_d = 6;
if (sm750_get_chip_type() == SM750LE) {
/*
* SM750LE don't have
* programmable PLL and M/N values to work on.
* Just return the requested clock.
*/
return request_orig;
}
ret = 0;
mini_diff = ~0;
request = request_orig / 1000;
input = pll->input_freq / 1000;
/*
* for MXCLK register,
* no POD provided, so need be treated differently
*/
if (pll->clock_type == MXCLK_PLL)
max_d = 3;
for (N = 15; N > 1; N--) {
/*
* RN will not exceed maximum long
* if @request <= 285 MHZ (for 32bit cpu)
*/
RN = N * request;
quo = RN / input;
rem = RN % input;/* rem always small than 14318181 */
fl_quo = rem * 10000 / input;
for (d = max_d; d >= 0; d--) {
X = BIT(d);
M = quo * X;
M += fl_quo * X / 10000;
/* round step */
M += (fl_quo * X % 10000) > 5000 ? 1 : 0;
if (M < 256 && M > 0) {
unsigned int diff;
tmp_clock = pll->input_freq * M / N / X;
diff = abs(tmp_clock - request_orig);
if (diff < mini_diff) {
pll->M = M;
pll->N = N;
pll->POD = 0;
if (d > max_OD)
pll->POD = d - max_OD;
pll->OD = d - pll->POD;
mini_diff = diff;
ret = tmp_clock;
}
}
}
}
return ret;
}
unsigned int sm750_format_pll_reg(struct pll_value *p_PLL)
{
#ifndef VALIDATION_CHIP
unsigned int POD = p_PLL->POD;
#endif
unsigned int OD = p_PLL->OD;
unsigned int M = p_PLL->M;
unsigned int N = p_PLL->N;
/*
* Note that all PLL's have the same format. Here, we just use
* Panel PLL parameter to work out the bit fields in the
* register. On returning a 32 bit number, the value can be
* applied to any PLL in the calling function.
*/
return PLL_CTRL_POWER |
#ifndef VALIDATION_CHIP
((POD << PLL_CTRL_POD_SHIFT) & PLL_CTRL_POD_MASK) |
#endif
((OD << PLL_CTRL_OD_SHIFT) & PLL_CTRL_OD_MASK) |
((N << PLL_CTRL_N_SHIFT) & PLL_CTRL_N_MASK) |
((M << PLL_CTRL_M_SHIFT) & PLL_CTRL_M_MASK);
}
| linux-master | drivers/staging/sm750fb/ddk750_chip.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include "sm750.h"
#include "sm750_cursor.h"
#define poke32(addr, data) \
writel((data), cursor->mmio + (addr))
/* cursor control for voyager and 718/750*/
#define HWC_ADDRESS 0x0
#define HWC_ADDRESS_ENABLE BIT(31)
#define HWC_ADDRESS_EXT BIT(27)
#define HWC_ADDRESS_CS BIT(26)
#define HWC_ADDRESS_ADDRESS_MASK 0x3ffffff
#define HWC_LOCATION 0x4
#define HWC_LOCATION_TOP BIT(27)
#define HWC_LOCATION_Y_SHIFT 16
#define HWC_LOCATION_Y_MASK (0x7ff << 16)
#define HWC_LOCATION_LEFT BIT(11)
#define HWC_LOCATION_X_MASK 0x7ff
#define HWC_COLOR_12 0x8
#define HWC_COLOR_12_2_RGB565_SHIFT 16
#define HWC_COLOR_12_2_RGB565_MASK (0xffff << 16)
#define HWC_COLOR_12_1_RGB565_MASK 0xffff
#define HWC_COLOR_3 0xC
#define HWC_COLOR_3_RGB565_MASK 0xffff
/* hw_cursor_xxx works for voyager,718 and 750 */
void sm750_hw_cursor_enable(struct lynx_cursor *cursor)
{
u32 reg;
reg = (cursor->offset & HWC_ADDRESS_ADDRESS_MASK) | HWC_ADDRESS_ENABLE;
poke32(HWC_ADDRESS, reg);
}
void sm750_hw_cursor_disable(struct lynx_cursor *cursor)
{
poke32(HWC_ADDRESS, 0);
}
void sm750_hw_cursor_setSize(struct lynx_cursor *cursor, int w, int h)
{
cursor->w = w;
cursor->h = h;
}
void sm750_hw_cursor_setPos(struct lynx_cursor *cursor, int x, int y)
{
u32 reg;
reg = ((y << HWC_LOCATION_Y_SHIFT) & HWC_LOCATION_Y_MASK) |
(x & HWC_LOCATION_X_MASK);
poke32(HWC_LOCATION, reg);
}
void sm750_hw_cursor_setColor(struct lynx_cursor *cursor, u32 fg, u32 bg)
{
u32 reg = (fg << HWC_COLOR_12_2_RGB565_SHIFT) &
HWC_COLOR_12_2_RGB565_MASK;
poke32(HWC_COLOR_12, reg | (bg & HWC_COLOR_12_1_RGB565_MASK));
poke32(HWC_COLOR_3, 0xffe0);
}
void sm750_hw_cursor_setData(struct lynx_cursor *cursor, u16 rop,
const u8 *pcol, const u8 *pmsk)
{
int i, j, count, pitch, offset;
u8 color, mask, opr;
u16 data;
void __iomem *pbuffer, *pstart;
/* in byte*/
pitch = cursor->w >> 3;
/* in byte */
count = pitch * cursor->h;
/* in byte */
offset = cursor->max_w * 2 / 8;
data = 0;
pstart = cursor->vstart;
pbuffer = pstart;
for (i = 0; i < count; i++) {
color = *pcol++;
mask = *pmsk++;
data = 0;
for (j = 0; j < 8; j++) {
if (mask & (0x80 >> j)) {
if (rop == ROP_XOR)
opr = mask ^ color;
else
opr = mask & color;
/* 2 stands for forecolor and 1 for backcolor */
data |= ((opr & (0x80 >> j)) ? 2 : 1) << (j * 2);
}
}
iowrite16(data, pbuffer);
/* assume pitch is 1,2,4,8,...*/
if ((i + 1) % pitch == 0) {
/* need a return */
pstart += offset;
pbuffer = pstart;
} else {
pbuffer += sizeof(u16);
}
}
}
void sm750_hw_cursor_setData2(struct lynx_cursor *cursor, u16 rop,
const u8 *pcol, const u8 *pmsk)
{
int i, j, count, pitch, offset;
u8 color, mask;
u16 data;
void __iomem *pbuffer, *pstart;
/* in byte*/
pitch = cursor->w >> 3;
/* in byte */
count = pitch * cursor->h;
/* in byte */
offset = cursor->max_w * 2 / 8;
data = 0;
pstart = cursor->vstart;
pbuffer = pstart;
for (i = 0; i < count; i++) {
color = *pcol++;
mask = *pmsk++;
data = 0;
for (j = 0; j < 8; j++) {
if (mask & (1 << j))
data |= ((color & (1 << j)) ? 1 : 2) << (j * 2);
}
iowrite16(data, pbuffer);
/* assume pitch is 1,2,4,8,...*/
if (!(i & (pitch - 1))) {
/* need a return */
pstart += offset;
pbuffer = pstart;
} else {
pbuffer += sizeof(u16);
}
}
}
| linux-master | drivers/staging/sm750fb/sm750_cursor.c |
// SPDX-License-Identifier: GPL-2.0
#include "ddk750_reg.h"
#include "ddk750_chip.h"
#include "ddk750_display.h"
#include "ddk750_power.h"
#include "ddk750_dvi.h"
static void set_display_control(int ctrl, int disp_state)
{
/* state != 0 means turn on both timing & plane en_bit */
unsigned long reg, val, reserved;
int cnt = 0;
if (!ctrl) {
reg = PANEL_DISPLAY_CTRL;
reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
} else {
reg = CRT_DISPLAY_CTRL;
reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
}
val = peek32(reg);
if (disp_state) {
/*
* Timing should be enabled first before enabling the
* plane because changing at the same time does not
* guarantee that the plane will also enabled or
* disabled.
*/
val |= DISPLAY_CTRL_TIMING;
poke32(reg, val);
val |= DISPLAY_CTRL_PLANE;
/*
* Somehow the register value on the plane is not set
* until a few delay. Need to write and read it a
* couple times
*/
do {
cnt++;
poke32(reg, val);
} while ((peek32(reg) & ~reserved) != (val & ~reserved));
pr_debug("Set Plane enbit:after tried %d times\n", cnt);
} else {
/*
* When turning off, there is no rule on the
* programming sequence since whenever the clock is
* off, then it does not matter whether the plane is
* enabled or disabled. Note: Modifying the plane bit
* will take effect on the next vertical sync. Need to
* find out if it is necessary to wait for 1 vsync
* before modifying the timing enable bit.
*/
val &= ~DISPLAY_CTRL_PLANE;
poke32(reg, val);
val &= ~DISPLAY_CTRL_TIMING;
poke32(reg, val);
}
}
static void primary_wait_vertical_sync(int delay)
{
unsigned int status;
/*
* Do not wait when the Primary PLL is off or display control is
* already off. This will prevent the software to wait forever.
*/
if (!(peek32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
!(peek32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING))
return;
while (delay-- > 0) {
/* Wait for end of vsync. */
do {
status = peek32(SYSTEM_CTRL);
} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
do {
status = peek32(SYSTEM_CTRL);
} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
}
}
static void sw_panel_power_sequence(int disp, int delay)
{
unsigned int reg;
/* disp should be 1 to open sequence */
reg = peek32(PANEL_DISPLAY_CTRL);
reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
poke32(PANEL_DISPLAY_CTRL, reg);
primary_wait_vertical_sync(delay);
reg = peek32(PANEL_DISPLAY_CTRL);
reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0);
poke32(PANEL_DISPLAY_CTRL, reg);
primary_wait_vertical_sync(delay);
reg = peek32(PANEL_DISPLAY_CTRL);
reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0);
poke32(PANEL_DISPLAY_CTRL, reg);
primary_wait_vertical_sync(delay);
reg = peek32(PANEL_DISPLAY_CTRL);
reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
poke32(PANEL_DISPLAY_CTRL, reg);
primary_wait_vertical_sync(delay);
}
void ddk750_set_logical_disp_out(enum disp_output output)
{
unsigned int reg;
if (output & PNL_2_USAGE) {
/* set panel path controller select */
reg = peek32(PANEL_DISPLAY_CTRL);
reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK;
reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) <<
PANEL_DISPLAY_CTRL_SELECT_SHIFT);
poke32(PANEL_DISPLAY_CTRL, reg);
}
if (output & CRT_2_USAGE) {
/* set crt path controller select */
reg = peek32(CRT_DISPLAY_CTRL);
reg &= ~CRT_DISPLAY_CTRL_SELECT_MASK;
reg |= (((output & CRT_2_MASK) >> CRT_2_OFFSET) <<
CRT_DISPLAY_CTRL_SELECT_SHIFT);
/*se blank off */
reg &= ~CRT_DISPLAY_CTRL_BLANK;
poke32(CRT_DISPLAY_CTRL, reg);
}
if (output & PRI_TP_USAGE) {
/* set primary timing and plane en_bit */
set_display_control(0, (output & PRI_TP_MASK) >> PRI_TP_OFFSET);
}
if (output & SEC_TP_USAGE) {
/* set secondary timing and plane en_bit*/
set_display_control(1, (output & SEC_TP_MASK) >> SEC_TP_OFFSET);
}
if (output & PNL_SEQ_USAGE) {
/* set panel sequence */
sw_panel_power_sequence((output & PNL_SEQ_MASK) >>
PNL_SEQ_OFFSET, 4);
}
if (output & DAC_USAGE)
set_DAC((output & DAC_MASK) >> DAC_OFFSET);
if (output & DPMS_USAGE)
ddk750_set_dpms((output & DPMS_MASK) >> DPMS_OFFSET);
}
| linux-master | drivers/staging/sm750fb/ddk750_display.c |
// SPDX-License-Identifier: GPL-2.0
#define USE_DVICHIP
#ifdef USE_DVICHIP
#include "ddk750_sii164.h"
#include "ddk750_hwi2c.h"
/* I2C Address of each SII164 chip */
#define SII164_I2C_ADDRESS 0x70
/* Define this definition to use hardware i2c. */
#define USE_HW_I2C
#ifdef USE_HW_I2C
#define i2cWriteReg sm750_hw_i2c_write_reg
#define i2cReadReg sm750_hw_i2c_read_reg
#else
#define i2cWriteReg sm750_sw_i2c_write_reg
#define i2cReadReg sm750_sw_i2c_read_reg
#endif
/* SII164 Vendor and Device ID */
#define SII164_VENDOR_ID 0x0001
#define SII164_DEVICE_ID 0x0006
#ifdef SII164_FULL_FUNCTIONS
/* Name of the DVI Controller chip */
static char *gDviCtrlChipName = "Silicon Image SiI 164";
#endif
/*
* sii164_get_vendor_id
* This function gets the vendor ID of the DVI controller chip.
*
* Output:
* Vendor ID
*/
unsigned short sii164_get_vendor_id(void)
{
unsigned short vendorID;
vendorID = ((unsigned short)i2cReadReg(SII164_I2C_ADDRESS,
SII164_VENDOR_ID_HIGH) << 8) |
(unsigned short)i2cReadReg(SII164_I2C_ADDRESS,
SII164_VENDOR_ID_LOW);
return vendorID;
}
/*
* sii164GetDeviceID
* This function gets the device ID of the DVI controller chip.
*
* Output:
* Device ID
*/
unsigned short sii164GetDeviceID(void)
{
unsigned short deviceID;
deviceID = ((unsigned short)i2cReadReg(SII164_I2C_ADDRESS,
SII164_DEVICE_ID_HIGH) << 8) |
(unsigned short)i2cReadReg(SII164_I2C_ADDRESS,
SII164_DEVICE_ID_LOW);
return deviceID;
}
/*
* DVI.C will handle all SiI164 chip stuffs and try its best to make code
* minimal and useful
*/
/*
* sii164_init_chip
* This function initialize and detect the DVI controller chip.
*
* Input:
* edge_select - Edge Select:
* 0 = Input data is falling edge latched (falling
* edge latched first in dual edge mode)
* 1 = Input data is rising edge latched (rising
* edge latched first in dual edge mode)
* bus_select - Input Bus Select:
* 0 = Input data bus is 12-bits wide
* 1 = Input data bus is 24-bits wide
* dual_edge_clk_select - Dual Edge Clock Select
* 0 = Input data is single edge latched
* 1 = Input data is dual edge latched
* hsync_enable - Horizontal Sync Enable:
* 0 = HSYNC input is transmitted as fixed LOW
* 1 = HSYNC input is transmitted as is
* vsync_enable - Vertical Sync Enable:
* 0 = VSYNC input is transmitted as fixed LOW
* 1 = VSYNC input is transmitted as is
* deskew_enable - De-skewing Enable:
* 0 = De-skew disabled
* 1 = De-skew enabled
* deskew_setting - De-skewing Setting (increment of 260psec)
* 0 = 1 step --> minimum setup / maximum hold
* 1 = 2 step
* 2 = 3 step
* 3 = 4 step
* 4 = 5 step
* 5 = 6 step
* 6 = 7 step
* 7 = 8 step --> maximum setup / minimum hold
* continuous_sync_enable- SYNC Continuous:
* 0 = Disable
* 1 = Enable
* pll_filter_enable - PLL Filter Enable
* 0 = Disable PLL Filter
* 1 = Enable PLL Filter
* pll_filter_value - PLL Filter characteristics:
* 0~7 (recommended value is 4)
*
* Output:
* 0 - Success
* -1 - Fail.
*/
long sii164_init_chip(unsigned char edge_select,
unsigned char bus_select,
unsigned char dual_edge_clk_select,
unsigned char hsync_enable,
unsigned char vsync_enable,
unsigned char deskew_enable,
unsigned char deskew_setting,
unsigned char continuous_sync_enable,
unsigned char pll_filter_enable,
unsigned char pll_filter_value)
{
unsigned char config;
/* Initialize the i2c bus */
#ifdef USE_HW_I2C
/* Use fast mode. */
sm750_hw_i2c_init(1);
#else
sm750_sw_i2c_init(DEFAULT_I2C_SCL, DEFAULT_I2C_SDA);
#endif
/* Check if SII164 Chip exists */
if ((sii164_get_vendor_id() == SII164_VENDOR_ID) &&
(sii164GetDeviceID() == SII164_DEVICE_ID)) {
/*
* Initialize SII164 controller chip.
*/
/* Select the edge */
if (edge_select == 0)
config = SII164_CONFIGURATION_LATCH_FALLING;
else
config = SII164_CONFIGURATION_LATCH_RISING;
/* Select bus wide */
if (bus_select == 0)
config |= SII164_CONFIGURATION_BUS_12BITS;
else
config |= SII164_CONFIGURATION_BUS_24BITS;
/* Select Dual/Single Edge Clock */
if (dual_edge_clk_select == 0)
config |= SII164_CONFIGURATION_CLOCK_SINGLE;
else
config |= SII164_CONFIGURATION_CLOCK_DUAL;
/* Select HSync Enable */
if (hsync_enable == 0)
config |= SII164_CONFIGURATION_HSYNC_FORCE_LOW;
else
config |= SII164_CONFIGURATION_HSYNC_AS_IS;
/* Select VSync Enable */
if (vsync_enable == 0)
config |= SII164_CONFIGURATION_VSYNC_FORCE_LOW;
else
config |= SII164_CONFIGURATION_VSYNC_AS_IS;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
/*
* De-skew enabled with default 111b value.
* This fixes some artifacts problem in some mode on board 2.2.
* Somehow this fix does not affect board 2.1.
*/
if (deskew_enable == 0)
config = SII164_DESKEW_DISABLE;
else
config = SII164_DESKEW_ENABLE;
switch (deskew_setting) {
case 0:
config |= SII164_DESKEW_1_STEP;
break;
case 1:
config |= SII164_DESKEW_2_STEP;
break;
case 2:
config |= SII164_DESKEW_3_STEP;
break;
case 3:
config |= SII164_DESKEW_4_STEP;
break;
case 4:
config |= SII164_DESKEW_5_STEP;
break;
case 5:
config |= SII164_DESKEW_6_STEP;
break;
case 6:
config |= SII164_DESKEW_7_STEP;
break;
case 7:
config |= SII164_DESKEW_8_STEP;
break;
}
i2cWriteReg(SII164_I2C_ADDRESS, SII164_DESKEW, config);
/* Enable/Disable Continuous Sync. */
if (continuous_sync_enable == 0)
config = SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE;
else
config = SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE;
/* Enable/Disable PLL Filter */
if (pll_filter_enable == 0)
config |= SII164_PLL_FILTER_DISABLE;
else
config |= SII164_PLL_FILTER_ENABLE;
/* Set the PLL Filter value */
config |= ((pll_filter_value & 0x07) << 1);
i2cWriteReg(SII164_I2C_ADDRESS, SII164_PLL, config);
/* Recover from Power Down and enable output. */
config = i2cReadReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION);
config |= SII164_CONFIGURATION_POWER_NORMAL;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
return 0;
}
/* Return -1 if initialization fails. */
return -1;
}
/* below sii164 function is not necessary */
#ifdef SII164_FULL_FUNCTIONS
/*
* sii164ResetChip
* This function resets the DVI Controller Chip.
*/
void sii164ResetChip(void)
{
/* Power down */
sii164SetPower(0);
sii164SetPower(1);
}
/*
* sii164GetChipString
* This function returns a char string name of the current DVI Controller
* chip.
*
* It's convenient for application need to display the chip name.
*/
char *sii164GetChipString(void)
{
return gDviCtrlChipName;
}
/*
* sii164SetPower
* This function sets the power configuration of the DVI Controller Chip.
*
* Input:
* powerUp - Flag to set the power down or up
*/
void sii164SetPower(unsigned char powerUp)
{
unsigned char config;
config = i2cReadReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION);
if (powerUp == 1) {
/* Power up the chip */
config &= ~SII164_CONFIGURATION_POWER_MASK;
config |= SII164_CONFIGURATION_POWER_NORMAL;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
} else {
/* Power down the chip */
config &= ~SII164_CONFIGURATION_POWER_MASK;
config |= SII164_CONFIGURATION_POWER_DOWN;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
}
}
/*
* sii164SelectHotPlugDetectionMode
* This function selects the mode of the hot plug detection.
*/
static
void sii164SelectHotPlugDetectionMode(enum sii164_hot_plug_mode hotPlugMode)
{
unsigned char detectReg;
detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) &
~SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG;
switch (hotPlugMode) {
case SII164_HOTPLUG_DISABLE:
detectReg |= SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH;
break;
case SII164_HOTPLUG_USE_MDI:
detectReg &= ~SII164_DETECT_INTERRUPT_MASK;
detectReg |= SII164_DETECT_INTERRUPT_BY_HTPLG_PIN;
detectReg |= SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI;
break;
case SII164_HOTPLUG_USE_RSEN:
detectReg |= SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN;
break;
case SII164_HOTPLUG_USE_HTPLG:
detectReg |= SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG;
break;
}
i2cWriteReg(SII164_I2C_ADDRESS, SII164_DETECT, detectReg);
}
/*
* sii164EnableHotPlugDetection
* This function enables the Hot Plug detection.
*
* enableHotPlug - Enable (=1) / disable (=0) Hot Plug detection
*/
void sii164EnableHotPlugDetection(unsigned char enableHotPlug)
{
unsigned char detectReg;
detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT);
/* Depending on each DVI controller, need to enable the hot plug based
* on each individual chip design.
*/
if (enableHotPlug != 0)
sii164SelectHotPlugDetectionMode(SII164_HOTPLUG_USE_MDI);
else
sii164SelectHotPlugDetectionMode(SII164_HOTPLUG_DISABLE);
}
/*
* sii164IsConnected
* Check if the DVI Monitor is connected.
*
* Output:
* 0 - Not Connected
* 1 - Connected
*/
unsigned char sii164IsConnected(void)
{
unsigned char hotPlugValue;
hotPlugValue = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) &
SII164_DETECT_HOT_PLUG_STATUS_MASK;
if (hotPlugValue == SII164_DETECT_HOT_PLUG_STATUS_ON)
return 1;
else
return 0;
}
/*
* sii164CheckInterrupt
* Checks if interrupt has occurred.
*
* Output:
* 0 - No interrupt
* 1 - Interrupt occurs
*/
unsigned char sii164CheckInterrupt(void)
{
unsigned char detectReg;
detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) &
SII164_DETECT_MONITOR_STATE_MASK;
if (detectReg == SII164_DETECT_MONITOR_STATE_CHANGE)
return 1;
else
return 0;
}
/*
* sii164ClearInterrupt
* Clear the hot plug interrupt.
*/
void sii164ClearInterrupt(void)
{
unsigned char detectReg;
/* Clear the MDI interrupt */
detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT);
i2cWriteReg(SII164_I2C_ADDRESS, SII164_DETECT,
detectReg | SII164_DETECT_MONITOR_STATE_CLEAR);
}
#endif
#endif
| linux-master | drivers/staging/sm750fb/ddk750_sii164.c |
// SPDX-License-Identifier: GPL-2.0
#define USE_DVICHIP
#ifdef USE_DVICHIP
#include "ddk750_chip.h"
#include "ddk750_reg.h"
#include "ddk750_dvi.h"
#include "ddk750_sii164.h"
/*
* This global variable contains all the supported driver and its corresponding
* function API. Please set the function pointer to NULL whenever the function
* is not supported.
*/
static struct dvi_ctrl_device dcft_supported_dvi_controller[] = {
#ifdef DVI_CTRL_SII164
{
.init = sii164_init_chip,
.get_vendor_id = sii164_get_vendor_id,
.get_device_id = sii164GetDeviceID,
#ifdef SII164_FULL_FUNCTIONS
.reset_chip = sii164ResetChip,
.get_chip_string = sii164GetChipString,
.set_power = sii164SetPower,
.enable_hot_plug_detection = sii164EnableHotPlugDetection,
.is_connected = sii164IsConnected,
.check_interrupt = sii164CheckInterrupt,
.clear_interrupt = sii164ClearInterrupt,
#endif
},
#endif
};
int dvi_init(unsigned char edge_select,
unsigned char bus_select,
unsigned char dual_edge_clk_select,
unsigned char hsync_enable,
unsigned char vsync_enable,
unsigned char deskew_enable,
unsigned char deskew_setting,
unsigned char continuous_sync_enable,
unsigned char pll_filter_enable,
unsigned char pll_filter_value)
{
struct dvi_ctrl_device *current_dvi_ctrl;
current_dvi_ctrl = dcft_supported_dvi_controller;
if (current_dvi_ctrl->init) {
return current_dvi_ctrl->init(edge_select,
bus_select,
dual_edge_clk_select,
hsync_enable,
vsync_enable,
deskew_enable,
deskew_setting,
continuous_sync_enable,
pll_filter_enable,
pll_filter_value);
}
return -1; /* error */
}
#endif
| linux-master | drivers/staging/sm750fb/ddk750_dvi.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/console.h>
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
#include <linux/platform_device.h>
#include <linux/sizes.h>
#include "sm750.h"
#include "ddk750.h"
#include "sm750_accel.h"
void __iomem *mmio750;
int hw_sm750_map(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
{
int ret;
ret = 0;
sm750_dev->vidreg_start = pci_resource_start(pdev, 1);
sm750_dev->vidreg_size = SZ_2M;
pr_info("mmio phyAddr = %lx\n", sm750_dev->vidreg_start);
/*
* reserve the vidreg space of smi adaptor
* if you do this, you need to add release region code
* in lynxfb_remove, or memory will not be mapped again
* successfully
*/
ret = pci_request_region(pdev, 1, "sm750fb");
if (ret) {
pr_err("Can not request PCI regions.\n");
goto exit;
}
/* now map mmio and vidmem */
sm750_dev->pvReg =
ioremap(sm750_dev->vidreg_start, sm750_dev->vidreg_size);
if (!sm750_dev->pvReg) {
pr_err("mmio failed\n");
ret = -EFAULT;
goto exit;
} else {
pr_info("mmio virtual addr = %p\n", sm750_dev->pvReg);
}
sm750_dev->accel.dprBase = sm750_dev->pvReg + DE_BASE_ADDR_TYPE1;
sm750_dev->accel.dpPortBase = sm750_dev->pvReg + DE_PORT_ADDR_TYPE1;
mmio750 = sm750_dev->pvReg;
sm750_set_chip_type(sm750_dev->devid, sm750_dev->revid);
sm750_dev->vidmem_start = pci_resource_start(pdev, 0);
/*
* don't use pdev_resource[x].end - resource[x].start to
* calculate the resource size, it's only the maximum available
* size but not the actual size, using
* @ddk750_get_vm_size function can be safe.
*/
sm750_dev->vidmem_size = ddk750_get_vm_size();
pr_info("video memory phyAddr = %lx, size = %u bytes\n",
sm750_dev->vidmem_start, sm750_dev->vidmem_size);
/* reserve the vidmem space of smi adaptor */
sm750_dev->pvMem =
ioremap_wc(sm750_dev->vidmem_start, sm750_dev->vidmem_size);
if (!sm750_dev->pvMem) {
iounmap(sm750_dev->pvReg);
pr_err("Map video memory failed\n");
ret = -EFAULT;
goto exit;
} else {
pr_info("video memory vaddr = %p\n", sm750_dev->pvMem);
}
exit:
return ret;
}
int hw_sm750_inithw(struct sm750_dev *sm750_dev, struct pci_dev *pdev)
{
struct init_status *parm;
parm = &sm750_dev->initParm;
if (parm->chip_clk == 0)
parm->chip_clk = (sm750_get_chip_type() == SM750LE) ?
DEFAULT_SM750LE_CHIP_CLOCK :
DEFAULT_SM750_CHIP_CLOCK;
if (parm->mem_clk == 0)
parm->mem_clk = parm->chip_clk;
if (parm->master_clk == 0)
parm->master_clk = parm->chip_clk / 3;
ddk750_init_hw((struct initchip_param *)&sm750_dev->initParm);
/* for sm718, open pci burst */
if (sm750_dev->devid == 0x718) {
poke32(SYSTEM_CTRL,
peek32(SYSTEM_CTRL) | SYSTEM_CTRL_PCI_BURST);
}
if (sm750_get_chip_type() != SM750LE) {
unsigned int val;
/* does user need CRT? */
if (sm750_dev->nocrt) {
poke32(MISC_CTRL,
peek32(MISC_CTRL) | MISC_CTRL_DAC_POWER_OFF);
/* shut off dpms */
val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
val |= SYSTEM_CTRL_DPMS_VPHN;
poke32(SYSTEM_CTRL, val);
} else {
poke32(MISC_CTRL,
peek32(MISC_CTRL) & ~MISC_CTRL_DAC_POWER_OFF);
/* turn on dpms */
val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
val |= SYSTEM_CTRL_DPMS_VPHP;
poke32(SYSTEM_CTRL, val);
}
val = peek32(PANEL_DISPLAY_CTRL) &
~(PANEL_DISPLAY_CTRL_DUAL_DISPLAY |
PANEL_DISPLAY_CTRL_DOUBLE_PIXEL);
switch (sm750_dev->pnltype) {
case sm750_24TFT:
break;
case sm750_doubleTFT:
val |= PANEL_DISPLAY_CTRL_DOUBLE_PIXEL;
break;
case sm750_dualTFT:
val |= PANEL_DISPLAY_CTRL_DUAL_DISPLAY;
break;
}
poke32(PANEL_DISPLAY_CTRL, val);
} else {
/*
* for 750LE, no DVI chip initialization
* makes Monitor no signal
*
* Set up GPIO for software I2C to program DVI chip in the
* Xilinx SP605 board, in order to have video signal.
*/
sm750_sw_i2c_init(0, 1);
/*
* Customer may NOT use CH7301 DVI chip, which has to be
* initialized differently.
*/
if (sm750_sw_i2c_read_reg(0xec, 0x4a) == 0x95) {
/*
* The following register values for CH7301 are from
* Chrontel app note and our experiment.
*/
pr_info("yes,CH7301 DVI chip found\n");
sm750_sw_i2c_write_reg(0xec, 0x1d, 0x16);
sm750_sw_i2c_write_reg(0xec, 0x21, 0x9);
sm750_sw_i2c_write_reg(0xec, 0x49, 0xC0);
pr_info("okay,CH7301 DVI chip setup done\n");
}
}
/* init 2d engine */
if (!sm750_dev->accel_off)
hw_sm750_initAccel(sm750_dev);
return 0;
}
int hw_sm750_output_setMode(struct lynxfb_output *output,
struct fb_var_screeninfo *var,
struct fb_fix_screeninfo *fix)
{
int ret;
enum disp_output disp_set;
int channel;
ret = 0;
disp_set = 0;
channel = *output->channel;
if (sm750_get_chip_type() != SM750LE) {
if (channel == sm750_primary) {
pr_info("primary channel\n");
if (output->paths & sm750_panel)
disp_set |= do_LCD1_PRI;
if (output->paths & sm750_crt)
disp_set |= do_CRT_PRI;
} else {
pr_info("secondary channel\n");
if (output->paths & sm750_panel)
disp_set |= do_LCD1_SEC;
if (output->paths & sm750_crt)
disp_set |= do_CRT_SEC;
}
ddk750_set_logical_disp_out(disp_set);
} else {
/* just open DISPLAY_CONTROL_750LE register bit 3:0 */
u32 reg;
reg = peek32(DISPLAY_CONTROL_750LE);
reg |= 0xf;
poke32(DISPLAY_CONTROL_750LE, reg);
}
pr_info("ddk setlogicdispout done\n");
return ret;
}
int hw_sm750_crtc_checkMode(struct lynxfb_crtc *crtc,
struct fb_var_screeninfo *var)
{
struct sm750_dev *sm750_dev;
struct lynxfb_par *par = container_of(crtc, struct lynxfb_par, crtc);
sm750_dev = par->dev;
switch (var->bits_per_pixel) {
case 8:
case 16:
break;
case 32:
if (sm750_dev->revid == SM750LE_REVISION_ID) {
pr_debug("750le do not support 32bpp\n");
return -EINVAL;
}
break;
default:
return -EINVAL;
}
return 0;
}
/* set the controller's mode for @crtc charged with @var and @fix parameters */
int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc,
struct fb_var_screeninfo *var,
struct fb_fix_screeninfo *fix)
{
int ret, fmt;
u32 reg;
struct mode_parameter modparm;
enum clock_type clock;
struct sm750_dev *sm750_dev;
struct lynxfb_par *par;
ret = 0;
par = container_of(crtc, struct lynxfb_par, crtc);
sm750_dev = par->dev;
if (!sm750_dev->accel_off) {
/* set 2d engine pixel format according to mode bpp */
switch (var->bits_per_pixel) {
case 8:
fmt = 0;
break;
case 16:
fmt = 1;
break;
case 32:
default:
fmt = 2;
break;
}
sm750_hw_set2dformat(&sm750_dev->accel, fmt);
}
/* set timing */
modparm.pixel_clock = ps_to_hz(var->pixclock);
modparm.vertical_sync_polarity =
(var->sync & FB_SYNC_HOR_HIGH_ACT) ? POS : NEG;
modparm.horizontal_sync_polarity =
(var->sync & FB_SYNC_VERT_HIGH_ACT) ? POS : NEG;
modparm.clock_phase_polarity =
(var->sync & FB_SYNC_COMP_HIGH_ACT) ? POS : NEG;
modparm.horizontal_display_end = var->xres;
modparm.horizontal_sync_width = var->hsync_len;
modparm.horizontal_sync_start = var->xres + var->right_margin;
modparm.horizontal_total = var->xres + var->left_margin +
var->right_margin + var->hsync_len;
modparm.vertical_display_end = var->yres;
modparm.vertical_sync_height = var->vsync_len;
modparm.vertical_sync_start = var->yres + var->lower_margin;
modparm.vertical_total = var->yres + var->upper_margin +
var->lower_margin + var->vsync_len;
/* choose pll */
if (crtc->channel != sm750_secondary)
clock = PRIMARY_PLL;
else
clock = SECONDARY_PLL;
pr_debug("Request pixel clock = %lu\n", modparm.pixel_clock);
ret = ddk750_setModeTiming(&modparm, clock);
if (ret) {
pr_err("Set mode timing failed\n");
goto exit;
}
if (crtc->channel != sm750_secondary) {
/* set pitch, offset, width, start address, etc... */
poke32(PANEL_FB_ADDRESS,
crtc->o_screen & PANEL_FB_ADDRESS_ADDRESS_MASK);
reg = var->xres * (var->bits_per_pixel >> 3);
/*
* crtc->channel is not equal to par->index on numeric,
* be aware of that
*/
reg = ALIGN(reg, crtc->line_pad);
reg = (reg << PANEL_FB_WIDTH_WIDTH_SHIFT) &
PANEL_FB_WIDTH_WIDTH_MASK;
reg |= (fix->line_length & PANEL_FB_WIDTH_OFFSET_MASK);
poke32(PANEL_FB_WIDTH, reg);
reg = ((var->xres - 1) << PANEL_WINDOW_WIDTH_WIDTH_SHIFT) &
PANEL_WINDOW_WIDTH_WIDTH_MASK;
reg |= (var->xoffset & PANEL_WINDOW_WIDTH_X_MASK);
poke32(PANEL_WINDOW_WIDTH, reg);
reg = (var->yres_virtual - 1)
<< PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT;
reg &= PANEL_WINDOW_HEIGHT_HEIGHT_MASK;
reg |= (var->yoffset & PANEL_WINDOW_HEIGHT_Y_MASK);
poke32(PANEL_WINDOW_HEIGHT, reg);
poke32(PANEL_PLANE_TL, 0);
reg = ((var->yres - 1) << PANEL_PLANE_BR_BOTTOM_SHIFT) &
PANEL_PLANE_BR_BOTTOM_MASK;
reg |= ((var->xres - 1) & PANEL_PLANE_BR_RIGHT_MASK);
poke32(PANEL_PLANE_BR, reg);
/* set pixel format */
reg = peek32(PANEL_DISPLAY_CTRL);
poke32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4));
} else {
/* not implemented now */
poke32(CRT_FB_ADDRESS, crtc->o_screen);
reg = var->xres * (var->bits_per_pixel >> 3);
/*
* crtc->channel is not equal to par->index on numeric,
* be aware of that
*/
reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT;
reg &= CRT_FB_WIDTH_WIDTH_MASK;
reg |= (fix->line_length & CRT_FB_WIDTH_OFFSET_MASK);
poke32(CRT_FB_WIDTH, reg);
/* SET PIXEL FORMAT */
reg = peek32(CRT_DISPLAY_CTRL);
reg |= ((var->bits_per_pixel >> 4) &
CRT_DISPLAY_CTRL_FORMAT_MASK);
poke32(CRT_DISPLAY_CTRL, reg);
}
exit:
return ret;
}
int hw_sm750_setColReg(struct lynxfb_crtc *crtc, ushort index, ushort red,
ushort green, ushort blue)
{
static unsigned int add[] = { PANEL_PALETTE_RAM, CRT_PALETTE_RAM };
poke32(add[crtc->channel] + index * 4,
(red << 16) | (green << 8) | blue);
return 0;
}
int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank)
{
int dpms, crtdb;
switch (blank) {
case FB_BLANK_UNBLANK:
dpms = CRT_DISPLAY_CTRL_DPMS_0;
crtdb = 0;
break;
case FB_BLANK_NORMAL:
dpms = CRT_DISPLAY_CTRL_DPMS_0;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
case FB_BLANK_VSYNC_SUSPEND:
dpms = CRT_DISPLAY_CTRL_DPMS_2;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
case FB_BLANK_HSYNC_SUSPEND:
dpms = CRT_DISPLAY_CTRL_DPMS_1;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
case FB_BLANK_POWERDOWN:
dpms = CRT_DISPLAY_CTRL_DPMS_3;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
default:
return -EINVAL;
}
if (output->paths & sm750_crt) {
unsigned int val;
val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
poke32(CRT_DISPLAY_CTRL, val | dpms);
val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
poke32(CRT_DISPLAY_CTRL, val | crtdb);
}
return 0;
}
int hw_sm750_setBLANK(struct lynxfb_output *output, int blank)
{
unsigned int dpms, pps, crtdb;
dpms = 0;
pps = 0;
crtdb = 0;
switch (blank) {
case FB_BLANK_UNBLANK:
pr_debug("flag = FB_BLANK_UNBLANK\n");
dpms = SYSTEM_CTRL_DPMS_VPHP;
pps = PANEL_DISPLAY_CTRL_DATA;
break;
case FB_BLANK_NORMAL:
pr_debug("flag = FB_BLANK_NORMAL\n");
dpms = SYSTEM_CTRL_DPMS_VPHP;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
case FB_BLANK_VSYNC_SUSPEND:
dpms = SYSTEM_CTRL_DPMS_VNHP;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
case FB_BLANK_HSYNC_SUSPEND:
dpms = SYSTEM_CTRL_DPMS_VPHN;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
case FB_BLANK_POWERDOWN:
dpms = SYSTEM_CTRL_DPMS_VNHN;
crtdb = CRT_DISPLAY_CTRL_BLANK;
break;
}
if (output->paths & sm750_crt) {
unsigned int val = peek32(SYSTEM_CTRL) & ~SYSTEM_CTRL_DPMS_MASK;
poke32(SYSTEM_CTRL, val | dpms);
val = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_BLANK;
poke32(CRT_DISPLAY_CTRL, val | crtdb);
}
if (output->paths & sm750_panel) {
unsigned int val = peek32(PANEL_DISPLAY_CTRL);
val &= ~PANEL_DISPLAY_CTRL_DATA;
val |= pps;
poke32(PANEL_DISPLAY_CTRL, val);
}
return 0;
}
void hw_sm750_initAccel(struct sm750_dev *sm750_dev)
{
u32 reg;
sm750_enable_2d_engine(1);
if (sm750_get_chip_type() == SM750LE) {
reg = peek32(DE_STATE1);
reg |= DE_STATE1_DE_ABORT;
poke32(DE_STATE1, reg);
reg = peek32(DE_STATE1);
reg &= ~DE_STATE1_DE_ABORT;
poke32(DE_STATE1, reg);
} else {
/* engine reset */
reg = peek32(SYSTEM_CTRL);
reg |= SYSTEM_CTRL_DE_ABORT;
poke32(SYSTEM_CTRL, reg);
reg = peek32(SYSTEM_CTRL);
reg &= ~SYSTEM_CTRL_DE_ABORT;
poke32(SYSTEM_CTRL, reg);
}
/* call 2d init */
sm750_dev->accel.de_init(&sm750_dev->accel);
}
int hw_sm750le_deWait(void)
{
int i = 0x10000000;
unsigned int mask = DE_STATE2_DE_STATUS_BUSY | DE_STATE2_DE_FIFO_EMPTY |
DE_STATE2_DE_MEM_FIFO_EMPTY;
while (i--) {
unsigned int val = peek32(DE_STATE2);
if ((val & mask) ==
(DE_STATE2_DE_FIFO_EMPTY | DE_STATE2_DE_MEM_FIFO_EMPTY))
return 0;
}
/* timeout error */
return -1;
}
int hw_sm750_deWait(void)
{
int i = 0x10000000;
unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY |
SYSTEM_CTRL_DE_FIFO_EMPTY |
SYSTEM_CTRL_DE_MEM_FIFO_EMPTY;
while (i--) {
unsigned int val = peek32(SYSTEM_CTRL);
if ((val & mask) ==
(SYSTEM_CTRL_DE_FIFO_EMPTY | SYSTEM_CTRL_DE_MEM_FIFO_EMPTY))
return 0;
}
/* timeout error */
return -1;
}
int hw_sm750_pan_display(struct lynxfb_crtc *crtc,
const struct fb_var_screeninfo *var,
const struct fb_info *info)
{
u32 total;
/* check params */
if ((var->xoffset + var->xres > var->xres_virtual) ||
(var->yoffset + var->yres > var->yres_virtual)) {
return -EINVAL;
}
total = var->yoffset * info->fix.line_length +
((var->xoffset * var->bits_per_pixel) >> 3);
total += crtc->o_screen;
if (crtc->channel == sm750_primary) {
poke32(PANEL_FB_ADDRESS,
peek32(PANEL_FB_ADDRESS) |
(total & PANEL_FB_ADDRESS_ADDRESS_MASK));
} else {
poke32(CRT_FB_ADDRESS,
peek32(CRT_FB_ADDRESS) |
(total & CRT_FB_ADDRESS_ADDRESS_MASK));
}
return 0;
}
| linux-master | drivers/staging/sm750fb/sm750_hw.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include "sm750.h"
#include "sm750_accel.h"
static inline void write_dpr(struct lynx_accel *accel, int offset, u32 regValue)
{
writel(regValue, accel->dprBase + offset);
}
static inline u32 read_dpr(struct lynx_accel *accel, int offset)
{
return readl(accel->dprBase + offset);
}
static inline void write_dpPort(struct lynx_accel *accel, u32 data)
{
writel(data, accel->dpPortBase);
}
void sm750_hw_de_init(struct lynx_accel *accel)
{
/* setup 2d engine registers */
u32 reg, clr;
write_dpr(accel, DE_MASKS, 0xFFFFFFFF);
/* dpr1c */
reg = 0x3;
clr = DE_STRETCH_FORMAT_PATTERN_XY |
DE_STRETCH_FORMAT_PATTERN_Y_MASK |
DE_STRETCH_FORMAT_PATTERN_X_MASK |
DE_STRETCH_FORMAT_ADDRESSING_MASK |
DE_STRETCH_FORMAT_SOURCE_HEIGHT_MASK;
/* DE_STRETCH bpp format need be initialized in setMode routine */
write_dpr(accel, DE_STRETCH_FORMAT,
(read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg);
/* disable clipping and transparent */
write_dpr(accel, DE_CLIP_TL, 0); /* dpr2c */
write_dpr(accel, DE_CLIP_BR, 0); /* dpr30 */
write_dpr(accel, DE_COLOR_COMPARE_MASK, 0); /* dpr24 */
write_dpr(accel, DE_COLOR_COMPARE, 0);
clr = DE_CONTROL_TRANSPARENCY | DE_CONTROL_TRANSPARENCY_MATCH |
DE_CONTROL_TRANSPARENCY_SELECT;
/* dpr0c */
write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr);
}
/*
* set2dformat only be called from setmode functions
* but if you need dual framebuffer driver,need call set2dformat
* every time you use 2d function
*/
void sm750_hw_set2dformat(struct lynx_accel *accel, int fmt)
{
u32 reg;
/* fmt=0,1,2 for 8,16,32,bpp on sm718/750/502 */
reg = read_dpr(accel, DE_STRETCH_FORMAT);
reg &= ~DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK;
reg |= ((fmt << DE_STRETCH_FORMAT_PIXEL_FORMAT_SHIFT) &
DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK);
write_dpr(accel, DE_STRETCH_FORMAT, reg);
}
int sm750_hw_fillrect(struct lynx_accel *accel,
u32 base, u32 pitch, u32 Bpp,
u32 x, u32 y, u32 width, u32 height,
u32 color, u32 rop)
{
u32 deCtrl;
if (accel->de_wait() != 0) {
/*
* int time wait and always busy,seems hardware
* got something error
*/
pr_debug("De engine always busy\n");
return -1;
}
write_dpr(accel, DE_WINDOW_DESTINATION_BASE, base); /* dpr40 */
write_dpr(accel, DE_PITCH,
((pitch / Bpp << DE_PITCH_DESTINATION_SHIFT) &
DE_PITCH_DESTINATION_MASK) |
(pitch / Bpp & DE_PITCH_SOURCE_MASK)); /* dpr10 */
write_dpr(accel, DE_WINDOW_WIDTH,
((pitch / Bpp << DE_WINDOW_WIDTH_DST_SHIFT) &
DE_WINDOW_WIDTH_DST_MASK) |
(pitch / Bpp & DE_WINDOW_WIDTH_SRC_MASK)); /* dpr44 */
write_dpr(accel, DE_FOREGROUND, color); /* DPR14 */
write_dpr(accel, DE_DESTINATION,
((x << DE_DESTINATION_X_SHIFT) & DE_DESTINATION_X_MASK) |
(y & DE_DESTINATION_Y_MASK)); /* dpr4 */
write_dpr(accel, DE_DIMENSION,
((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) |
(height & DE_DIMENSION_Y_ET_MASK)); /* dpr8 */
deCtrl = DE_CONTROL_STATUS | DE_CONTROL_LAST_PIXEL |
DE_CONTROL_COMMAND_RECTANGLE_FILL | DE_CONTROL_ROP_SELECT |
(rop & DE_CONTROL_ROP_MASK); /* dpr0xc */
write_dpr(accel, DE_CONTROL, deCtrl);
return 0;
}
/**
* sm750_hw_copyarea
* @accel: Acceleration device data
* @sBase: Address of source: offset in frame buffer
* @sPitch: Pitch value of source surface in BYTE
* @sx: Starting x coordinate of source surface
* @sy: Starting y coordinate of source surface
* @dBase: Address of destination: offset in frame buffer
* @dPitch: Pitch value of destination surface in BYTE
* @Bpp: Color depth of destination surface
* @dx: Starting x coordinate of destination surface
* @dy: Starting y coordinate of destination surface
* @width: width of rectangle in pixel value
* @height: height of rectangle in pixel value
* @rop2: ROP value
*/
int sm750_hw_copyarea(struct lynx_accel *accel,
unsigned int sBase, unsigned int sPitch,
unsigned int sx, unsigned int sy,
unsigned int dBase, unsigned int dPitch,
unsigned int Bpp, unsigned int dx, unsigned int dy,
unsigned int width, unsigned int height,
unsigned int rop2)
{
unsigned int nDirection, de_ctrl;
nDirection = LEFT_TO_RIGHT;
/* Direction of ROP2 operation: 1 = Left to Right, (-1) = Right to Left */
de_ctrl = 0;
/* If source and destination are the same surface, need to check for overlay cases */
if (sBase == dBase && sPitch == dPitch) {
/* Determine direction of operation */
if (sy < dy) {
/* +----------+
* |S |
* | +----------+
* | | | |
* | | | |
* +---|------+ |
* | D|
* +----------+
*/
nDirection = BOTTOM_TO_TOP;
} else if (sy > dy) {
/* +----------+
* |D |
* | +----------+
* | | | |
* | | | |
* +---|------+ |
* | S|
* +----------+
*/
nDirection = TOP_TO_BOTTOM;
} else {
/* sy == dy */
if (sx <= dx) {
/* +------+---+------+
* |S | | D|
* | | | |
* | | | |
* | | | |
* +------+---+------+
*/
nDirection = RIGHT_TO_LEFT;
} else {
/* sx > dx */
/* +------+---+------+
* |D | | S|
* | | | |
* | | | |
* | | | |
* +------+---+------+
*/
nDirection = LEFT_TO_RIGHT;
}
}
}
if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT)) {
sx += width - 1;
sy += height - 1;
dx += width - 1;
dy += height - 1;
}
/*
* Note:
* DE_FOREGROUND and DE_BACKGROUND are don't care.
* DE_COLOR_COMPARE and DE_COLOR_COMPARE_MAKS
* are set by set deSetTransparency().
*/
/*
* 2D Source Base.
* It is an address offset (128 bit aligned)
* from the beginning of frame buffer.
*/
write_dpr(accel, DE_WINDOW_SOURCE_BASE, sBase); /* dpr40 */
/*
* 2D Destination Base.
* It is an address offset (128 bit aligned)
* from the beginning of frame buffer.
*/
write_dpr(accel, DE_WINDOW_DESTINATION_BASE, dBase); /* dpr44 */
/*
* Program pitch (distance between the 1st points of two adjacent lines).
* Note that input pitch is BYTE value, but the 2D Pitch register uses
* pixel values. Need Byte to pixel conversion.
*/
write_dpr(accel, DE_PITCH,
((dPitch / Bpp << DE_PITCH_DESTINATION_SHIFT) &
DE_PITCH_DESTINATION_MASK) |
(sPitch / Bpp & DE_PITCH_SOURCE_MASK)); /* dpr10 */
/*
* Screen Window width in Pixels.
* 2D engine uses this value to calculate the linear address in frame buffer
* for a given point.
*/
write_dpr(accel, DE_WINDOW_WIDTH,
((dPitch / Bpp << DE_WINDOW_WIDTH_DST_SHIFT) &
DE_WINDOW_WIDTH_DST_MASK) |
(sPitch / Bpp & DE_WINDOW_WIDTH_SRC_MASK)); /* dpr3c */
if (accel->de_wait() != 0)
return -1;
write_dpr(accel, DE_SOURCE,
((sx << DE_SOURCE_X_K1_SHIFT) & DE_SOURCE_X_K1_MASK) |
(sy & DE_SOURCE_Y_K2_MASK)); /* dpr0 */
write_dpr(accel, DE_DESTINATION,
((dx << DE_DESTINATION_X_SHIFT) & DE_DESTINATION_X_MASK) |
(dy & DE_DESTINATION_Y_MASK)); /* dpr04 */
write_dpr(accel, DE_DIMENSION,
((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) |
(height & DE_DIMENSION_Y_ET_MASK)); /* dpr08 */
de_ctrl = (rop2 & DE_CONTROL_ROP_MASK) | DE_CONTROL_ROP_SELECT |
((nDirection == RIGHT_TO_LEFT) ? DE_CONTROL_DIRECTION : 0) |
DE_CONTROL_COMMAND_BITBLT | DE_CONTROL_STATUS;
write_dpr(accel, DE_CONTROL, de_ctrl); /* dpr0c */
return 0;
}
static unsigned int deGetTransparency(struct lynx_accel *accel)
{
unsigned int de_ctrl;
de_ctrl = read_dpr(accel, DE_CONTROL);
de_ctrl &= (DE_CONTROL_TRANSPARENCY_MATCH |
DE_CONTROL_TRANSPARENCY_SELECT | DE_CONTROL_TRANSPARENCY);
return de_ctrl;
}
/**
* sm750_hw_imageblit
* @accel: Acceleration device data
* @pSrcbuf: pointer to start of source buffer in system memory
* @srcDelta: Pitch value (in bytes) of the source buffer, +ive means top down
* and -ive mean button up
* @startBit: Mono data can start at any bit in a byte, this value should be
* 0 to 7
* @dBase: Address of destination: offset in frame buffer
* @dPitch: Pitch value of destination surface in BYTE
* @bytePerPixel: Color depth of destination surface
* @dx: Starting x coordinate of destination surface
* @dy: Starting y coordinate of destination surface
* @width: width of rectangle in pixel value
* @height: height of rectangle in pixel value
* @fColor: Foreground color (corresponding to a 1 in the monochrome data
* @bColor: Background color (corresponding to a 0 in the monochrome data
* @rop2: ROP value
*/
int sm750_hw_imageblit(struct lynx_accel *accel, const char *pSrcbuf,
u32 srcDelta, u32 startBit, u32 dBase, u32 dPitch,
u32 bytePerPixel, u32 dx, u32 dy, u32 width,
u32 height, u32 fColor, u32 bColor, u32 rop2)
{
unsigned int ulBytesPerScan;
unsigned int ul4BytesPerScan;
unsigned int ulBytesRemain;
unsigned int de_ctrl = 0;
unsigned char ajRemain[4];
int i, j;
startBit &= 7; /* Just make sure the start bit is within legal range */
ulBytesPerScan = (width + startBit + 7) / 8;
ul4BytesPerScan = ulBytesPerScan & ~3;
ulBytesRemain = ulBytesPerScan & 3;
if (accel->de_wait() != 0)
return -1;
/*
* 2D Source Base.
* Use 0 for HOST Blt.
*/
write_dpr(accel, DE_WINDOW_SOURCE_BASE, 0);
/* 2D Destination Base.
* It is an address offset (128 bit aligned)
* from the beginning of frame buffer.
*/
write_dpr(accel, DE_WINDOW_DESTINATION_BASE, dBase);
/*
* Program pitch (distance between the 1st points of two adjacent
* lines). Note that input pitch is BYTE value, but the 2D Pitch
* register uses pixel values. Need Byte to pixel conversion.
*/
write_dpr(accel, DE_PITCH,
((dPitch / bytePerPixel << DE_PITCH_DESTINATION_SHIFT) &
DE_PITCH_DESTINATION_MASK) |
(dPitch / bytePerPixel & DE_PITCH_SOURCE_MASK)); /* dpr10 */
/*
* Screen Window width in Pixels.
* 2D engine uses this value to calculate the linear address
* in frame buffer for a given point.
*/
write_dpr(accel, DE_WINDOW_WIDTH,
((dPitch / bytePerPixel << DE_WINDOW_WIDTH_DST_SHIFT) &
DE_WINDOW_WIDTH_DST_MASK) |
(dPitch / bytePerPixel & DE_WINDOW_WIDTH_SRC_MASK));
/*
* Note: For 2D Source in Host Write, only X_K1_MONO field is needed,
* and Y_K2 field is not used.
* For mono bitmap, use startBit for X_K1.
*/
write_dpr(accel, DE_SOURCE,
(startBit << DE_SOURCE_X_K1_SHIFT) &
DE_SOURCE_X_K1_MONO_MASK); /* dpr00 */
write_dpr(accel, DE_DESTINATION,
((dx << DE_DESTINATION_X_SHIFT) & DE_DESTINATION_X_MASK) |
(dy & DE_DESTINATION_Y_MASK)); /* dpr04 */
write_dpr(accel, DE_DIMENSION,
((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) |
(height & DE_DIMENSION_Y_ET_MASK)); /* dpr08 */
write_dpr(accel, DE_FOREGROUND, fColor);
write_dpr(accel, DE_BACKGROUND, bColor);
de_ctrl = (rop2 & DE_CONTROL_ROP_MASK) |
DE_CONTROL_ROP_SELECT | DE_CONTROL_COMMAND_HOST_WRITE |
DE_CONTROL_HOST | DE_CONTROL_STATUS;
write_dpr(accel, DE_CONTROL, de_ctrl | deGetTransparency(accel));
/* Write MONO data (line by line) to 2D Engine data port */
for (i = 0; i < height; i++) {
/* For each line, send the data in chunks of 4 bytes */
for (j = 0; j < (ul4BytesPerScan / 4); j++)
write_dpPort(accel, *(unsigned int *)(pSrcbuf + (j * 4)));
if (ulBytesRemain) {
memcpy(ajRemain, pSrcbuf + ul4BytesPerScan,
ulBytesRemain);
write_dpPort(accel, *(unsigned int *)ajRemain);
}
pSrcbuf += srcDelta;
}
return 0;
}
| linux-master | drivers/staging/sm750fb/sm750_accel.c |
// SPDX-License-Identifier: GPL-2.0
#include "ddk750_chip.h"
#include "ddk750_reg.h"
#include "ddk750_power.h"
void ddk750_set_dpms(enum dpms state)
{
unsigned int value;
if (sm750_get_chip_type() == SM750LE) {
value = peek32(CRT_DISPLAY_CTRL) & ~CRT_DISPLAY_CTRL_DPMS_MASK;
value |= (state << CRT_DISPLAY_CTRL_DPMS_SHIFT);
poke32(CRT_DISPLAY_CTRL, value);
} else {
value = peek32(SYSTEM_CTRL);
value = (value & ~SYSTEM_CTRL_DPMS_MASK) | state;
poke32(SYSTEM_CTRL, value);
}
}
static unsigned int get_power_mode(void)
{
if (sm750_get_chip_type() == SM750LE)
return 0;
return peek32(POWER_MODE_CTRL) & POWER_MODE_CTRL_MODE_MASK;
}
/*
* SM50x can operate in one of three modes: 0, 1 or Sleep.
* On hardware reset, power mode 0 is default.
*/
void sm750_set_power_mode(unsigned int mode)
{
unsigned int ctrl = 0;
ctrl = peek32(POWER_MODE_CTRL) & ~POWER_MODE_CTRL_MODE_MASK;
if (sm750_get_chip_type() == SM750LE)
return;
switch (mode) {
case POWER_MODE_CTRL_MODE_MODE0:
ctrl |= POWER_MODE_CTRL_MODE_MODE0;
break;
case POWER_MODE_CTRL_MODE_MODE1:
ctrl |= POWER_MODE_CTRL_MODE_MODE1;
break;
case POWER_MODE_CTRL_MODE_SLEEP:
ctrl |= POWER_MODE_CTRL_MODE_SLEEP;
break;
default:
break;
}
/* Set up other fields in Power Control Register */
if (mode == POWER_MODE_CTRL_MODE_SLEEP) {
ctrl &= ~POWER_MODE_CTRL_OSC_INPUT;
#ifdef VALIDATION_CHIP
ctrl &= ~POWER_MODE_CTRL_336CLK;
#endif
} else {
ctrl |= POWER_MODE_CTRL_OSC_INPUT;
#ifdef VALIDATION_CHIP
ctrl |= POWER_MODE_CTRL_336CLK;
#endif
}
/* Program new power mode. */
poke32(POWER_MODE_CTRL, ctrl);
}
void sm750_set_current_gate(unsigned int gate)
{
if (get_power_mode() == POWER_MODE_CTRL_MODE_MODE1)
poke32(MODE1_GATE, gate);
else
poke32(MODE0_GATE, gate);
}
/*
* This function enable/disable the 2D engine.
*/
void sm750_enable_2d_engine(unsigned int enable)
{
u32 gate;
gate = peek32(CURRENT_GATE);
if (enable)
gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC);
else
gate &= ~(CURRENT_GATE_DE | CURRENT_GATE_CSC);
sm750_set_current_gate(gate);
}
void sm750_enable_dma(unsigned int enable)
{
u32 gate;
/* Enable DMA Gate */
gate = peek32(CURRENT_GATE);
if (enable)
gate |= CURRENT_GATE_DMA;
else
gate &= ~CURRENT_GATE_DMA;
sm750_set_current_gate(gate);
}
/*
* This function enable/disable the GPIO Engine
*/
void sm750_enable_gpio(unsigned int enable)
{
u32 gate;
/* Enable GPIO Gate */
gate = peek32(CURRENT_GATE);
if (enable)
gate |= CURRENT_GATE_GPIO;
else
gate &= ~CURRENT_GATE_GPIO;
sm750_set_current_gate(gate);
}
/*
* This function enable/disable the I2C Engine
*/
void sm750_enable_i2c(unsigned int enable)
{
u32 gate;
/* Enable I2C Gate */
gate = peek32(CURRENT_GATE);
if (enable)
gate |= CURRENT_GATE_I2C;
else
gate &= ~CURRENT_GATE_I2C;
sm750_set_current_gate(gate);
}
| linux-master | drivers/staging/sm750fb/ddk750_power.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/aperture.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/mm_types.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/console.h>
#include "sm750.h"
#include "sm750_accel.h"
#include "sm750_cursor.h"
/*
* #ifdef __BIG_ENDIAN
* ssize_t lynxfb_ops_write(struct fb_info *info, const char __user *buf,
* size_t count, loff_t *ppos);
* ssize_t lynxfb_ops_read(struct fb_info *info, char __user *buf,
* size_t count, loff_t *ppos);
* #endif
*/
/* common var for all device */
static int g_hwcursor = 1;
static int g_noaccel;
static int g_nomtrr;
static const char *g_fbmode[] = {NULL, NULL};
static const char *g_def_fbmode = "1024x768-32@60";
static char *g_settings;
static int g_dualview;
static char *g_option;
static const struct fb_videomode lynx750_ext[] = {
/* 1024x600-60 VESA [1.71:1] */
{NULL, 60, 1024, 600, 20423, 144, 40, 18, 1, 104, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1024x600-70 VESA */
{NULL, 70, 1024, 600, 17211, 152, 48, 21, 1, 104, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1024x600-75 VESA */
{NULL, 75, 1024, 600, 15822, 160, 56, 23, 1, 104, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1024x600-85 VESA */
{NULL, 85, 1024, 600, 13730, 168, 56, 26, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 720x480 */
{NULL, 60, 720, 480, 37427, 88, 16, 13, 1, 72, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1280x720 [1.78:1] */
{NULL, 60, 1280, 720, 13426, 162, 86, 22, 1, 136, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1280x768@60 */
{NULL, 60, 1280, 768, 12579, 192, 64, 20, 3, 128, 7,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1360 x 768 [1.77083:1] */
{NULL, 60, 1360, 768, 11804, 208, 64, 23, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1368 x 768 [1.78:1] */
{NULL, 60, 1368, 768, 11647, 216, 72, 23, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1440 x 900 [16:10] */
{NULL, 60, 1440, 900, 9392, 232, 80, 28, 1, 152, 3,
FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1440x960 [15:10] */
{NULL, 60, 1440, 960, 8733, 240, 88, 30, 1, 152, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
/* 1920x1080 [16:9] */
{NULL, 60, 1920, 1080, 6734, 148, 88, 41, 1, 44, 3,
FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED},
};
/* no hardware cursor supported under version 2.6.10, kernel bug */
static int lynxfb_ops_cursor(struct fb_info *info, struct fb_cursor *fbcursor)
{
struct lynxfb_par *par;
struct lynxfb_crtc *crtc;
struct lynx_cursor *cursor;
par = info->par;
crtc = &par->crtc;
cursor = &crtc->cursor;
if (fbcursor->image.width > cursor->max_w ||
fbcursor->image.height > cursor->max_h ||
fbcursor->image.depth > 1) {
return -ENXIO;
}
sm750_hw_cursor_disable(cursor);
if (fbcursor->set & FB_CUR_SETSIZE)
sm750_hw_cursor_setSize(cursor,
fbcursor->image.width,
fbcursor->image.height);
if (fbcursor->set & FB_CUR_SETPOS)
sm750_hw_cursor_setPos(cursor,
fbcursor->image.dx - info->var.xoffset,
fbcursor->image.dy - info->var.yoffset);
if (fbcursor->set & FB_CUR_SETCMAP) {
/* get the 16bit color of kernel means */
u16 fg, bg;
fg = ((info->cmap.red[fbcursor->image.fg_color] & 0xf800)) |
((info->cmap.green[fbcursor->image.fg_color] & 0xfc00) >> 5) |
((info->cmap.blue[fbcursor->image.fg_color] & 0xf800) >> 11);
bg = ((info->cmap.red[fbcursor->image.bg_color] & 0xf800)) |
((info->cmap.green[fbcursor->image.bg_color] & 0xfc00) >> 5) |
((info->cmap.blue[fbcursor->image.bg_color] & 0xf800) >> 11);
sm750_hw_cursor_setColor(cursor, fg, bg);
}
if (fbcursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
sm750_hw_cursor_setData(cursor,
fbcursor->rop,
fbcursor->image.data,
fbcursor->mask);
}
if (fbcursor->enable)
sm750_hw_cursor_enable(cursor);
return 0;
}
static void lynxfb_ops_fillrect(struct fb_info *info,
const struct fb_fillrect *region)
{
struct lynxfb_par *par;
struct sm750_dev *sm750_dev;
unsigned int base, pitch, Bpp, rop;
u32 color;
if (info->state != FBINFO_STATE_RUNNING)
return;
par = info->par;
sm750_dev = par->dev;
/*
* each time 2d function begin to work,below three variable always need
* be set, seems we can put them together in some place
*/
base = par->crtc.o_screen;
pitch = info->fix.line_length;
Bpp = info->var.bits_per_pixel >> 3;
color = (Bpp == 1) ? region->color :
((u32 *)info->pseudo_palette)[region->color];
rop = (region->rop != ROP_COPY) ? HW_ROP2_XOR : HW_ROP2_COPY;
/*
* If not use spin_lock, system will die if user load driver
* and immediately unload driver frequently (dual)
* since they fb_count could change during the lifetime of
* this lock, we are holding it for all cases.
*/
spin_lock(&sm750_dev->slock);
sm750_dev->accel.de_fillrect(&sm750_dev->accel,
base, pitch, Bpp,
region->dx, region->dy,
region->width, region->height,
color, rop);
spin_unlock(&sm750_dev->slock);
}
static void lynxfb_ops_copyarea(struct fb_info *info,
const struct fb_copyarea *region)
{
struct lynxfb_par *par;
struct sm750_dev *sm750_dev;
unsigned int base, pitch, Bpp;
par = info->par;
sm750_dev = par->dev;
/*
* each time 2d function begin to work,below three variable always need
* be set, seems we can put them together in some place
*/
base = par->crtc.o_screen;
pitch = info->fix.line_length;
Bpp = info->var.bits_per_pixel >> 3;
/*
* If not use spin_lock, system will die if user load driver
* and immediately unload driver frequently (dual)
* since they fb_count could change during the lifetime of
* this lock, we are holding it for all cases.
*/
spin_lock(&sm750_dev->slock);
sm750_dev->accel.de_copyarea(&sm750_dev->accel,
base, pitch, region->sx, region->sy,
base, pitch, Bpp, region->dx, region->dy,
region->width, region->height,
HW_ROP2_COPY);
spin_unlock(&sm750_dev->slock);
}
static void lynxfb_ops_imageblit(struct fb_info *info,
const struct fb_image *image)
{
unsigned int base, pitch, Bpp;
unsigned int fgcol, bgcol;
struct lynxfb_par *par;
struct sm750_dev *sm750_dev;
par = info->par;
sm750_dev = par->dev;
/*
* each time 2d function begin to work,below three variable always need
* be set, seems we can put them together in some place
*/
base = par->crtc.o_screen;
pitch = info->fix.line_length;
Bpp = info->var.bits_per_pixel >> 3;
/* TODO: Implement hardware acceleration for image->depth > 1 */
if (image->depth != 1) {
cfb_imageblit(info, image);
return;
}
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fgcol = ((u32 *)info->pseudo_palette)[image->fg_color];
bgcol = ((u32 *)info->pseudo_palette)[image->bg_color];
} else {
fgcol = image->fg_color;
bgcol = image->bg_color;
}
/*
* If not use spin_lock, system will die if user load driver
* and immediately unload driver frequently (dual)
* since they fb_count could change during the lifetime of
* this lock, we are holding it for all cases.
*/
spin_lock(&sm750_dev->slock);
sm750_dev->accel.de_imageblit(&sm750_dev->accel,
image->data, image->width >> 3, 0,
base, pitch, Bpp,
image->dx, image->dy,
image->width, image->height,
fgcol, bgcol, HW_ROP2_COPY);
spin_unlock(&sm750_dev->slock);
}
static int lynxfb_ops_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct lynxfb_par *par;
struct lynxfb_crtc *crtc;
if (!info)
return -EINVAL;
par = info->par;
crtc = &par->crtc;
return hw_sm750_pan_display(crtc, var, info);
}
static inline void lynxfb_set_visual_mode(struct fb_info *info)
{
switch (info->var.bits_per_pixel) {
case 8:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
case 24:
case 32:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
default:
break;
}
}
static inline int lynxfb_set_color_offsets(struct fb_info *info)
{
lynxfb_set_visual_mode(info);
switch (info->var.bits_per_pixel) {
case 8:
info->var.red.offset = 0;
info->var.red.length = 8;
info->var.green.offset = 0;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->var.transp.length = 0;
info->var.transp.offset = 0;
break;
case 16:
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->var.transp.length = 0;
info->var.transp.offset = 0;
break;
case 24:
case 32:
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
break;
default:
return -EINVAL;
}
return 0;
}
static int lynxfb_ops_set_par(struct fb_info *info)
{
struct lynxfb_par *par;
struct lynxfb_crtc *crtc;
struct lynxfb_output *output;
struct fb_var_screeninfo *var;
struct fb_fix_screeninfo *fix;
int ret;
unsigned int line_length;
if (!info)
return -EINVAL;
ret = 0;
par = info->par;
crtc = &par->crtc;
output = &par->output;
var = &info->var;
fix = &info->fix;
/* fix structure is not so FIX ... */
line_length = var->xres_virtual * var->bits_per_pixel / 8;
line_length = ALIGN(line_length, crtc->line_pad);
fix->line_length = line_length;
pr_info("fix->line_length = %d\n", fix->line_length);
/*
* var->red,green,blue,transp are need to be set by driver
* and these data should be set before setcolreg routine
*/
ret = lynxfb_set_color_offsets(info);
var->height = -1;
var->width = -1;
var->accel_flags = 0;/*FB_ACCELF_TEXT;*/
if (ret) {
pr_err("bpp %d not supported\n", var->bits_per_pixel);
return ret;
}
ret = hw_sm750_crtc_setMode(crtc, var, fix);
if (!ret)
ret = hw_sm750_output_setMode(output, var, fix);
return ret;
}
static inline unsigned int chan_to_field(unsigned int chan,
struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int __maybe_unused lynxfb_suspend(struct device *dev)
{
struct fb_info *info;
struct sm750_dev *sm750_dev;
sm750_dev = dev_get_drvdata(dev);
console_lock();
info = sm750_dev->fbinfo[0];
if (info)
/* 1 means do suspend */
fb_set_suspend(info, 1);
info = sm750_dev->fbinfo[1];
if (info)
/* 1 means do suspend */
fb_set_suspend(info, 1);
console_unlock();
return 0;
}
static int __maybe_unused lynxfb_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct fb_info *info;
struct sm750_dev *sm750_dev;
struct lynxfb_par *par;
struct lynxfb_crtc *crtc;
struct lynx_cursor *cursor;
sm750_dev = pci_get_drvdata(pdev);
console_lock();
hw_sm750_inithw(sm750_dev, pdev);
info = sm750_dev->fbinfo[0];
if (info) {
par = info->par;
crtc = &par->crtc;
cursor = &crtc->cursor;
memset_io(cursor->vstart, 0x0, cursor->size);
memset_io(crtc->v_screen, 0x0, crtc->vidmem_size);
lynxfb_ops_set_par(info);
fb_set_suspend(info, 0);
}
info = sm750_dev->fbinfo[1];
if (info) {
par = info->par;
crtc = &par->crtc;
cursor = &crtc->cursor;
memset_io(cursor->vstart, 0x0, cursor->size);
memset_io(crtc->v_screen, 0x0, crtc->vidmem_size);
lynxfb_ops_set_par(info);
fb_set_suspend(info, 0);
}
pdev->dev.power.power_state.event = PM_EVENT_RESUME;
console_unlock();
return 0;
}
static int lynxfb_ops_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int ret;
struct lynxfb_par *par;
struct lynxfb_crtc *crtc;
resource_size_t request;
ret = 0;
par = info->par;
crtc = &par->crtc;
pr_debug("check var:%dx%d-%d\n",
var->xres,
var->yres,
var->bits_per_pixel);
ret = lynxfb_set_color_offsets(info);
if (ret) {
pr_err("bpp %d not supported\n", var->bits_per_pixel);
return ret;
}
var->height = -1;
var->width = -1;
var->accel_flags = 0;/* FB_ACCELF_TEXT; */
/* check if current fb's video memory big enough to hold the onscreen*/
request = var->xres_virtual * (var->bits_per_pixel >> 3);
/* defaulty crtc->channel go with par->index */
request = ALIGN(request, crtc->line_pad);
request = request * var->yres_virtual;
if (crtc->vidmem_size < request) {
pr_err("not enough video memory for mode\n");
return -ENOMEM;
}
return hw_sm750_crtc_checkMode(crtc, var);
}
static int lynxfb_ops_setcolreg(unsigned int regno,
unsigned int red,
unsigned int green,
unsigned int blue,
unsigned int transp,
struct fb_info *info)
{
struct lynxfb_par *par;
struct lynxfb_crtc *crtc;
struct fb_var_screeninfo *var;
int ret;
par = info->par;
crtc = &par->crtc;
var = &info->var;
ret = 0;
if (regno > 256) {
pr_err("regno = %d\n", regno);
return -EINVAL;
}
if (info->var.grayscale)
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
if (var->bits_per_pixel == 8 &&
info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
red >>= 8;
green >>= 8;
blue >>= 8;
ret = hw_sm750_setColReg(crtc, regno, red, green, blue);
goto exit;
}
if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 256) {
u32 val;
if (var->bits_per_pixel == 16 ||
var->bits_per_pixel == 32 ||
var->bits_per_pixel == 24) {
val = chan_to_field(red, &var->red);
val |= chan_to_field(green, &var->green);
val |= chan_to_field(blue, &var->blue);
par->pseudo_palette[regno] = val;
goto exit;
}
}
ret = -EINVAL;
exit:
return ret;
}
static int lynxfb_ops_blank(int blank, struct fb_info *info)
{
struct lynxfb_par *par;
struct lynxfb_output *output;
pr_debug("blank = %d.\n", blank);
par = info->par;
output = &par->output;
return output->proc_setBLANK(output, blank);
}
static int sm750fb_set_drv(struct lynxfb_par *par)
{
int ret;
struct sm750_dev *sm750_dev;
struct lynxfb_output *output;
struct lynxfb_crtc *crtc;
ret = 0;
sm750_dev = par->dev;
output = &par->output;
crtc = &par->crtc;
crtc->vidmem_size = sm750_dev->vidmem_size;
if (sm750_dev->fb_count > 1)
crtc->vidmem_size >>= 1;
/* setup crtc and output member */
sm750_dev->hwCursor = g_hwcursor;
crtc->line_pad = 16;
crtc->xpanstep = 8;
crtc->ypanstep = 1;
crtc->ywrapstep = 0;
output->proc_setBLANK = (sm750_dev->revid == SM750LE_REVISION_ID) ?
hw_sm750le_setBLANK : hw_sm750_setBLANK;
/* chip specific phase */
sm750_dev->accel.de_wait = (sm750_dev->revid == SM750LE_REVISION_ID) ?
hw_sm750le_deWait : hw_sm750_deWait;
switch (sm750_dev->dataflow) {
case sm750_simul_pri:
output->paths = sm750_pnc;
crtc->channel = sm750_primary;
crtc->o_screen = 0;
crtc->v_screen = sm750_dev->pvMem;
pr_info("use simul primary mode\n");
break;
case sm750_simul_sec:
output->paths = sm750_pnc;
crtc->channel = sm750_secondary;
crtc->o_screen = 0;
crtc->v_screen = sm750_dev->pvMem;
break;
case sm750_dual_normal:
if (par->index == 0) {
output->paths = sm750_panel;
crtc->channel = sm750_primary;
crtc->o_screen = 0;
crtc->v_screen = sm750_dev->pvMem;
} else {
output->paths = sm750_crt;
crtc->channel = sm750_secondary;
/* not consider of padding stuffs for o_screen,need fix */
crtc->o_screen = sm750_dev->vidmem_size >> 1;
crtc->v_screen = sm750_dev->pvMem + crtc->o_screen;
}
break;
case sm750_dual_swap:
if (par->index == 0) {
output->paths = sm750_panel;
crtc->channel = sm750_secondary;
crtc->o_screen = 0;
crtc->v_screen = sm750_dev->pvMem;
} else {
output->paths = sm750_crt;
crtc->channel = sm750_primary;
/* not consider of padding stuffs for o_screen,
* need fix
*/
crtc->o_screen = sm750_dev->vidmem_size >> 1;
crtc->v_screen = sm750_dev->pvMem + crtc->o_screen;
}
break;
default:
ret = -EINVAL;
}
return ret;
}
static struct fb_ops lynxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = lynxfb_ops_check_var,
.fb_set_par = lynxfb_ops_set_par,
.fb_setcolreg = lynxfb_ops_setcolreg,
.fb_blank = lynxfb_ops_blank,
.fb_fillrect = cfb_fillrect,
.fb_imageblit = cfb_imageblit,
.fb_copyarea = cfb_copyarea,
/* cursor */
.fb_cursor = lynxfb_ops_cursor,
};
static int lynxfb_set_fbinfo(struct fb_info *info, int index)
{
int i;
struct lynxfb_par *par;
struct sm750_dev *sm750_dev;
struct lynxfb_crtc *crtc;
struct lynxfb_output *output;
struct fb_var_screeninfo *var;
struct fb_fix_screeninfo *fix;
const struct fb_videomode *pdb[] = {
lynx750_ext, NULL, vesa_modes,
};
int cdb[] = {ARRAY_SIZE(lynx750_ext), 0, VESA_MODEDB_SIZE};
static const char * const mdb_desc[] = {
"driver prepared modes",
"kernel prepared default modedb",
"kernel HELPERS prepared vesa_modes",
};
static const char *fixId[2] = {
"sm750_fb1", "sm750_fb2",
};
int ret, line_length;
ret = 0;
par = (struct lynxfb_par *)info->par;
sm750_dev = par->dev;
crtc = &par->crtc;
output = &par->output;
var = &info->var;
fix = &info->fix;
/* set index */
par->index = index;
output->channel = &crtc->channel;
sm750fb_set_drv(par);
lynxfb_ops.fb_pan_display = lynxfb_ops_pan_display;
/*
* set current cursor variable and proc pointer,
* must be set after crtc member initialized
*/
crtc->cursor.offset = crtc->o_screen + crtc->vidmem_size - 1024;
crtc->cursor.mmio = sm750_dev->pvReg +
0x800f0 + (int)crtc->channel * 0x140;
pr_info("crtc->cursor.mmio = %p\n", crtc->cursor.mmio);
crtc->cursor.max_h = 64;
crtc->cursor.max_w = 64;
crtc->cursor.size = crtc->cursor.max_h * crtc->cursor.max_w * 2 / 8;
crtc->cursor.vstart = sm750_dev->pvMem + crtc->cursor.offset;
memset_io(crtc->cursor.vstart, 0, crtc->cursor.size);
if (!g_hwcursor) {
lynxfb_ops.fb_cursor = NULL;
sm750_hw_cursor_disable(&crtc->cursor);
}
/* set info->fbops, must be set before fb_find_mode */
if (!sm750_dev->accel_off) {
/* use 2d acceleration */
lynxfb_ops.fb_fillrect = lynxfb_ops_fillrect;
lynxfb_ops.fb_copyarea = lynxfb_ops_copyarea;
lynxfb_ops.fb_imageblit = lynxfb_ops_imageblit;
}
info->fbops = &lynxfb_ops;
if (!g_fbmode[index]) {
g_fbmode[index] = g_def_fbmode;
if (index)
g_fbmode[index] = g_fbmode[0];
}
for (i = 0; i < 3; i++) {
ret = fb_find_mode(var, info, g_fbmode[index],
pdb[i], cdb[i], NULL, 8);
if (ret == 1) {
pr_info("success! use specified mode:%s in %s\n",
g_fbmode[index],
mdb_desc[i]);
break;
} else if (ret == 2) {
pr_warn("use specified mode:%s in %s,with an ignored refresh rate\n",
g_fbmode[index],
mdb_desc[i]);
break;
} else if (ret == 3) {
pr_warn("wanna use default mode\n");
/*break;*/
} else if (ret == 4) {
pr_warn("fall back to any valid mode\n");
} else {
pr_warn("ret = %d,fb_find_mode failed,with %s\n",
ret,
mdb_desc[i]);
}
}
/* some member of info->var had been set by fb_find_mode */
pr_info("Member of info->var is :\n"
"xres=%d\n"
"yres=%d\n"
"xres_virtual=%d\n"
"yres_virtual=%d\n"
"xoffset=%d\n"
"yoffset=%d\n"
"bits_per_pixel=%d\n"
" ...\n",
var->xres,
var->yres,
var->xres_virtual,
var->yres_virtual,
var->xoffset,
var->yoffset,
var->bits_per_pixel);
/* set par */
par->info = info;
/* set info */
line_length = ALIGN((var->xres_virtual * var->bits_per_pixel / 8),
crtc->line_pad);
info->pseudo_palette = &par->pseudo_palette[0];
info->screen_base = crtc->v_screen;
pr_debug("screen_base vaddr = %p\n", info->screen_base);
info->screen_size = line_length * var->yres_virtual;
/* set info->fix */
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
fix->xpanstep = crtc->xpanstep;
fix->ypanstep = crtc->ypanstep;
fix->ywrapstep = crtc->ywrapstep;
fix->accel = FB_ACCEL_SMI;
strscpy(fix->id, fixId[index], sizeof(fix->id));
fix->smem_start = crtc->o_screen + sm750_dev->vidmem_start;
pr_info("fix->smem_start = %lx\n", fix->smem_start);
/*
* according to mmap experiment from user space application,
* fix->mmio_len should not larger than virtual size
* (xres_virtual x yres_virtual x ByPP)
* Below line maybe buggy when user mmap fb dev node and write
* data into the bound over virtual size
*/
fix->smem_len = crtc->vidmem_size;
pr_info("fix->smem_len = %x\n", fix->smem_len);
info->screen_size = fix->smem_len;
fix->line_length = line_length;
fix->mmio_start = sm750_dev->vidreg_start;
pr_info("fix->mmio_start = %lx\n", fix->mmio_start);
fix->mmio_len = sm750_dev->vidreg_size;
pr_info("fix->mmio_len = %x\n", fix->mmio_len);
lynxfb_set_visual_mode(info);
/* set var */
var->activate = FB_ACTIVATE_NOW;
var->accel_flags = 0;
var->vmode = FB_VMODE_NONINTERLACED;
pr_debug("#1 show info->cmap :\nstart=%d,len=%d,red=%p,green=%p,blue=%p,transp=%p\n",
info->cmap.start, info->cmap.len,
info->cmap.red, info->cmap.green, info->cmap.blue,
info->cmap.transp);
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret < 0) {
pr_err("Could not allocate memory for cmap.\n");
goto exit;
}
pr_debug("#2 show info->cmap :\nstart=%d,len=%d,red=%p,green=%p,blue=%p,transp=%p\n",
info->cmap.start, info->cmap.len,
info->cmap.red, info->cmap.green, info->cmap.blue,
info->cmap.transp);
exit:
lynxfb_ops_check_var(var, info);
return ret;
}
/* chip specific g_option configuration routine */
static void sm750fb_setup(struct sm750_dev *sm750_dev, char *src)
{
char *opt;
int swap;
swap = 0;
sm750_dev->initParm.chip_clk = 0;
sm750_dev->initParm.mem_clk = 0;
sm750_dev->initParm.master_clk = 0;
sm750_dev->initParm.powerMode = 0;
sm750_dev->initParm.setAllEngOff = 0;
sm750_dev->initParm.resetMemory = 1;
/* defaultly turn g_hwcursor on for both view */
g_hwcursor = 3;
if (!src || !*src) {
dev_warn(&sm750_dev->pdev->dev, "no specific g_option.\n");
goto NO_PARAM;
}
while ((opt = strsep(&src, ":")) != NULL && *opt != 0) {
dev_info(&sm750_dev->pdev->dev, "opt=%s\n", opt);
dev_info(&sm750_dev->pdev->dev, "src=%s\n", src);
if (!strncmp(opt, "swap", strlen("swap"))) {
swap = 1;
} else if (!strncmp(opt, "nocrt", strlen("nocrt"))) {
sm750_dev->nocrt = 1;
} else if (!strncmp(opt, "36bit", strlen("36bit"))) {
sm750_dev->pnltype = sm750_doubleTFT;
} else if (!strncmp(opt, "18bit", strlen("18bit"))) {
sm750_dev->pnltype = sm750_dualTFT;
} else if (!strncmp(opt, "24bit", strlen("24bit"))) {
sm750_dev->pnltype = sm750_24TFT;
} else if (!strncmp(opt, "nohwc0", strlen("nohwc0"))) {
g_hwcursor &= ~0x1;
} else if (!strncmp(opt, "nohwc1", strlen("nohwc1"))) {
g_hwcursor &= ~0x2;
} else if (!strncmp(opt, "nohwc", strlen("nohwc"))) {
g_hwcursor = 0;
} else {
if (!g_fbmode[0]) {
g_fbmode[0] = opt;
dev_info(&sm750_dev->pdev->dev,
"find fbmode0 : %s\n", g_fbmode[0]);
} else if (!g_fbmode[1]) {
g_fbmode[1] = opt;
dev_info(&sm750_dev->pdev->dev,
"find fbmode1 : %s\n", g_fbmode[1]);
} else {
dev_warn(&sm750_dev->pdev->dev, "How many view you wann set?\n");
}
}
}
NO_PARAM:
if (sm750_dev->revid != SM750LE_REVISION_ID) {
if (sm750_dev->fb_count > 1) {
if (swap)
sm750_dev->dataflow = sm750_dual_swap;
else
sm750_dev->dataflow = sm750_dual_normal;
} else {
if (swap)
sm750_dev->dataflow = sm750_simul_sec;
else
sm750_dev->dataflow = sm750_simul_pri;
}
} else {
/* SM750LE only have one crt channel */
sm750_dev->dataflow = sm750_simul_sec;
/* sm750le do not have complex attributes */
sm750_dev->nocrt = 0;
}
}
static void sm750fb_framebuffer_release(struct sm750_dev *sm750_dev)
{
struct fb_info *fb_info;
while (sm750_dev->fb_count) {
fb_info = sm750_dev->fbinfo[sm750_dev->fb_count - 1];
unregister_framebuffer(fb_info);
framebuffer_release(fb_info);
sm750_dev->fb_count--;
}
}
static int sm750fb_framebuffer_alloc(struct sm750_dev *sm750_dev, int fbidx)
{
struct fb_info *fb_info;
struct lynxfb_par *par;
int err;
fb_info = framebuffer_alloc(sizeof(struct lynxfb_par),
&sm750_dev->pdev->dev);
if (!fb_info)
return -ENOMEM;
sm750_dev->fbinfo[fbidx] = fb_info;
par = fb_info->par;
par->dev = sm750_dev;
err = lynxfb_set_fbinfo(fb_info, fbidx);
if (err)
goto release_fb;
err = register_framebuffer(fb_info);
if (err < 0)
goto release_fb;
sm750_dev->fb_count++;
return 0;
release_fb:
framebuffer_release(fb_info);
return err;
}
static int lynxfb_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct sm750_dev *sm750_dev = NULL;
int max_fb;
int fbidx;
int err;
err = aperture_remove_conflicting_pci_devices(pdev, "sm750_fb1");
if (err)
return err;
/* enable device */
err = pcim_enable_device(pdev);
if (err)
return err;
err = -ENOMEM;
sm750_dev = devm_kzalloc(&pdev->dev, sizeof(*sm750_dev), GFP_KERNEL);
if (!sm750_dev)
return err;
sm750_dev->fbinfo[0] = NULL;
sm750_dev->fbinfo[1] = NULL;
sm750_dev->devid = pdev->device;
sm750_dev->revid = pdev->revision;
sm750_dev->pdev = pdev;
sm750_dev->mtrr_off = g_nomtrr;
sm750_dev->mtrr.vram = 0;
sm750_dev->accel_off = g_noaccel;
spin_lock_init(&sm750_dev->slock);
if (!sm750_dev->accel_off) {
/*
* hook deInit and 2d routines, notes that below hw_xxx
* routine can work on most of lynx chips
* if some chip need specific function,
* please hook it in smXXX_set_drv routine
*/
sm750_dev->accel.de_init = sm750_hw_de_init;
sm750_dev->accel.de_fillrect = sm750_hw_fillrect;
sm750_dev->accel.de_copyarea = sm750_hw_copyarea;
sm750_dev->accel.de_imageblit = sm750_hw_imageblit;
}
/* call chip specific setup routine */
sm750fb_setup(sm750_dev, g_settings);
/* call chip specific mmap routine */
err = hw_sm750_map(sm750_dev, pdev);
if (err)
return err;
if (!sm750_dev->mtrr_off)
sm750_dev->mtrr.vram = arch_phys_wc_add(sm750_dev->vidmem_start,
sm750_dev->vidmem_size);
memset_io(sm750_dev->pvMem, 0, sm750_dev->vidmem_size);
pci_set_drvdata(pdev, sm750_dev);
/* call chipInit routine */
hw_sm750_inithw(sm750_dev, pdev);
/* allocate frame buffer info structures according to g_dualview */
max_fb = g_dualview ? 2 : 1;
for (fbidx = 0; fbidx < max_fb; fbidx++) {
err = sm750fb_framebuffer_alloc(sm750_dev, fbidx);
if (err)
goto release_fb;
}
return 0;
release_fb:
sm750fb_framebuffer_release(sm750_dev);
return err;
}
static void lynxfb_pci_remove(struct pci_dev *pdev)
{
struct sm750_dev *sm750_dev;
sm750_dev = pci_get_drvdata(pdev);
sm750fb_framebuffer_release(sm750_dev);
arch_phys_wc_del(sm750_dev->mtrr.vram);
iounmap(sm750_dev->pvReg);
iounmap(sm750_dev->pvMem);
kfree(g_settings);
}
static int __init lynxfb_setup(char *options)
{
int len;
char *opt, *tmp;
if (!options || !*options) {
pr_warn("no options.\n");
return 0;
}
pr_info("options:%s\n", options);
len = strlen(options) + 1;
g_settings = kzalloc(len, GFP_KERNEL);
if (!g_settings)
return -ENOMEM;
tmp = g_settings;
/*
* Notes:
* char * strsep(char **s,const char * ct);
* @s: the string to be searched
* @ct :the characters to search for
*
* strsep() updates @options to pointer after the first found token
* it also returns the pointer ahead the token.
*/
while ((opt = strsep(&options, ":")) != NULL) {
/* options that mean for any lynx chips are configured here */
if (!strncmp(opt, "noaccel", strlen("noaccel"))) {
g_noaccel = 1;
} else if (!strncmp(opt, "nomtrr", strlen("nomtrr"))) {
g_nomtrr = 1;
} else if (!strncmp(opt, "dual", strlen("dual"))) {
g_dualview = 1;
} else {
strcat(tmp, opt);
tmp += strlen(opt);
if (options)
*tmp++ = ':';
else
*tmp++ = 0;
}
}
/* misc g_settings are transport to chip specific routines */
pr_info("parameter left for chip specific analysis:%s\n", g_settings);
return 0;
}
static const struct pci_device_id smi_pci_table[] = {
{ PCI_DEVICE(0x126f, 0x0750), },
{0,}
};
MODULE_DEVICE_TABLE(pci, smi_pci_table);
static SIMPLE_DEV_PM_OPS(lynxfb_pm_ops, lynxfb_suspend, lynxfb_resume);
static struct pci_driver lynxfb_driver = {
.name = "sm750fb",
.id_table = smi_pci_table,
.probe = lynxfb_pci_probe,
.remove = lynxfb_pci_remove,
.driver.pm = &lynxfb_pm_ops,
};
static int __init lynxfb_init(void)
{
char *option;
if (fb_modesetting_disabled("sm750fb"))
return -ENODEV;
#ifdef MODULE
option = g_option;
#else
if (fb_get_options("sm750fb", &option))
return -ENODEV;
#endif
lynxfb_setup(option);
return pci_register_driver(&lynxfb_driver);
}
module_init(lynxfb_init);
static void __exit lynxfb_exit(void)
{
pci_unregister_driver(&lynxfb_driver);
}
module_exit(lynxfb_exit);
module_param(g_option, charp, 0444);
MODULE_PARM_DESC(g_option,
"\n\t\tCommon options:\n"
"\t\tnoaccel:disable 2d capabilities\n"
"\t\tnomtrr:disable MTRR attribute for video memory\n"
"\t\tdualview:dual frame buffer feature enabled\n"
"\t\tnohwc:disable hardware cursor\n"
"\t\tUsual example:\n"
"\t\tinsmod ./sm750fb.ko g_option=\"noaccel,nohwc,1280x1024-8@60\"\n"
);
MODULE_AUTHOR("monk liu <[email protected]>");
MODULE_AUTHOR("Sudip Mukherjee <[email protected]>");
MODULE_DESCRIPTION("Frame buffer driver for SM750 chipset");
MODULE_LICENSE("Dual BSD/GPL");
| linux-master | drivers/staging/sm750fb/sm750.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mainly by David Woodhouse, somewhat modified by Jordan Crouse
*
* Copyright © 2006-2007 Red Hat, Inc.
* Copyright © 2006-2007 Advanced Micro Devices, Inc.
* Copyright © 2009 VIA Technology, Inc.
* Copyright (c) 2010-2011 Andres Salomon <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/console.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/backlight.h>
#include <linux/device.h>
#include <linux/uaccess.h>
#include <linux/ctype.h>
#include <linux/panic_notifier.h>
#include <linux/reboot.h>
#include <linux/olpc-ec.h>
#include <asm/tsc.h>
#include <asm/olpc.h>
#include "olpc_dcon.h"
/* Module definitions */
static ushort resumeline = 898;
module_param(resumeline, ushort, 0444);
static struct dcon_platform_data *pdata;
/* I2C structures */
/* Platform devices */
static struct platform_device *dcon_device;
static unsigned short normal_i2c[] = { 0x0d, I2C_CLIENT_END };
static s32 dcon_write(struct dcon_priv *dcon, u8 reg, u16 val)
{
return i2c_smbus_write_word_data(dcon->client, reg, val);
}
static s32 dcon_read(struct dcon_priv *dcon, u8 reg)
{
return i2c_smbus_read_word_data(dcon->client, reg);
}
/* ===== API functions - these are called by a variety of users ==== */
static int dcon_hw_init(struct dcon_priv *dcon, int is_init)
{
u16 ver;
int rc = 0;
ver = dcon_read(dcon, DCON_REG_ID);
if ((ver >> 8) != 0xDC) {
pr_err("DCON ID not 0xDCxx: 0x%04x instead.\n", ver);
rc = -ENXIO;
goto err;
}
if (is_init) {
pr_info("Discovered DCON version %x\n", ver & 0xFF);
rc = pdata->init(dcon);
if (rc != 0) {
pr_err("Unable to init.\n");
goto err;
}
}
if (ver < 0xdc02) {
dev_err(&dcon->client->dev,
"DCON v1 is unsupported, giving up..\n");
rc = -ENODEV;
goto err;
}
/* SDRAM setup/hold time */
dcon_write(dcon, 0x3a, 0xc040);
dcon_write(dcon, DCON_REG_MEM_OPT_A, 0x0000); /* clear option bits */
dcon_write(dcon, DCON_REG_MEM_OPT_A,
MEM_DLL_CLOCK_DELAY | MEM_POWER_DOWN);
dcon_write(dcon, DCON_REG_MEM_OPT_B, MEM_SOFT_RESET);
/* Colour swizzle, AA, no passthrough, backlight */
if (is_init) {
dcon->disp_mode = MODE_PASSTHRU | MODE_BL_ENABLE |
MODE_CSWIZZLE | MODE_COL_AA;
}
dcon_write(dcon, DCON_REG_MODE, dcon->disp_mode);
/* Set the scanline to interrupt on during resume */
dcon_write(dcon, DCON_REG_SCAN_INT, resumeline);
err:
return rc;
}
/*
* The smbus doesn't always come back due to what is believed to be
* hardware (power rail) bugs. For older models where this is known to
* occur, our solution is to attempt to wait for the bus to stabilize;
* if it doesn't happen, cut power to the dcon, repower it, and wait
* for the bus to stabilize. Rinse, repeat until we have a working
* smbus. For newer models, we simply BUG(); we want to know if this
* still happens despite the power fixes that have been made!
*/
static int dcon_bus_stabilize(struct dcon_priv *dcon, int is_powered_down)
{
unsigned long timeout;
u8 pm;
int x;
power_up:
if (is_powered_down) {
pm = 1;
x = olpc_ec_cmd(EC_DCON_POWER_MODE, &pm, 1, NULL, 0);
if (x) {
pr_warn("unable to force dcon to power up: %d!\n", x);
return x;
}
usleep_range(10000, 11000); /* we'll be conservative */
}
pdata->bus_stabilize_wiggle();
for (x = -1, timeout = 50; timeout && x < 0; timeout--) {
usleep_range(1000, 1100);
x = dcon_read(dcon, DCON_REG_ID);
}
if (x < 0) {
pr_err("unable to stabilize dcon's smbus, reasserting power and praying.\n");
BUG_ON(olpc_board_at_least(olpc_board(0xc2)));
pm = 0;
olpc_ec_cmd(EC_DCON_POWER_MODE, &pm, 1, NULL, 0);
msleep(100);
is_powered_down = 1;
goto power_up; /* argh, stupid hardware.. */
}
if (is_powered_down)
return dcon_hw_init(dcon, 0);
return 0;
}
static void dcon_set_backlight(struct dcon_priv *dcon, u8 level)
{
dcon->bl_val = level;
dcon_write(dcon, DCON_REG_BRIGHT, dcon->bl_val);
/* Purposely turn off the backlight when we go to level 0 */
if (dcon->bl_val == 0) {
dcon->disp_mode &= ~MODE_BL_ENABLE;
dcon_write(dcon, DCON_REG_MODE, dcon->disp_mode);
} else if (!(dcon->disp_mode & MODE_BL_ENABLE)) {
dcon->disp_mode |= MODE_BL_ENABLE;
dcon_write(dcon, DCON_REG_MODE, dcon->disp_mode);
}
}
/* Set the output type to either color or mono */
static int dcon_set_mono_mode(struct dcon_priv *dcon, bool enable_mono)
{
if (dcon->mono == enable_mono)
return 0;
dcon->mono = enable_mono;
if (enable_mono) {
dcon->disp_mode &= ~(MODE_CSWIZZLE | MODE_COL_AA);
dcon->disp_mode |= MODE_MONO_LUMA;
} else {
dcon->disp_mode &= ~(MODE_MONO_LUMA);
dcon->disp_mode |= MODE_CSWIZZLE | MODE_COL_AA;
}
dcon_write(dcon, DCON_REG_MODE, dcon->disp_mode);
return 0;
}
/* For now, this will be really stupid - we need to address how
* DCONLOAD works in a sleep and account for it accordingly
*/
static void dcon_sleep(struct dcon_priv *dcon, bool sleep)
{
int x;
/* Turn off the backlight and put the DCON to sleep */
if (dcon->asleep == sleep)
return;
if (!olpc_board_at_least(olpc_board(0xc2)))
return;
if (sleep) {
u8 pm = 0;
x = olpc_ec_cmd(EC_DCON_POWER_MODE, &pm, 1, NULL, 0);
if (x)
pr_warn("unable to force dcon to power down: %d!\n", x);
else
dcon->asleep = sleep;
} else {
/* Only re-enable the backlight if the backlight value is set */
if (dcon->bl_val != 0)
dcon->disp_mode |= MODE_BL_ENABLE;
x = dcon_bus_stabilize(dcon, 1);
if (x)
pr_warn("unable to reinit dcon hardware: %d!\n", x);
else
dcon->asleep = sleep;
/* Restore backlight */
dcon_set_backlight(dcon, dcon->bl_val);
}
/* We should turn off some stuff in the framebuffer - but what? */
}
/* the DCON seems to get confused if we change DCONLOAD too
* frequently -- i.e., approximately faster than frame time.
* normally we don't change it this fast, so in general we won't
* delay here.
*/
static void dcon_load_holdoff(struct dcon_priv *dcon)
{
ktime_t delta_t, now;
while (1) {
now = ktime_get();
delta_t = ktime_sub(now, dcon->load_time);
if (ktime_to_ns(delta_t) > NSEC_PER_MSEC * 20)
break;
mdelay(4);
}
}
static bool dcon_blank_fb(struct dcon_priv *dcon, bool blank)
{
int err;
console_lock();
lock_fb_info(dcon->fbinfo);
dcon->ignore_fb_events = true;
err = fb_blank(dcon->fbinfo,
blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK);
dcon->ignore_fb_events = false;
unlock_fb_info(dcon->fbinfo);
console_unlock();
if (err) {
dev_err(&dcon->client->dev, "couldn't %sblank framebuffer\n",
blank ? "" : "un");
return false;
}
return true;
}
/* Set the source of the display (CPU or DCON) */
static void dcon_source_switch(struct work_struct *work)
{
struct dcon_priv *dcon = container_of(work, struct dcon_priv,
switch_source);
int source = dcon->pending_src;
if (dcon->curr_src == source)
return;
dcon_load_holdoff(dcon);
dcon->switched = false;
switch (source) {
case DCON_SOURCE_CPU:
pr_info("%s to CPU\n", __func__);
/* Enable the scanline interrupt bit */
if (dcon_write(dcon, DCON_REG_MODE,
dcon->disp_mode | MODE_SCAN_INT))
pr_err("couldn't enable scanline interrupt!\n");
else
/* Wait up to one second for the scanline interrupt */
wait_event_timeout(dcon->waitq, dcon->switched, HZ);
if (!dcon->switched)
pr_err("Timeout entering CPU mode; expect a screen glitch.\n");
/* Turn off the scanline interrupt */
if (dcon_write(dcon, DCON_REG_MODE, dcon->disp_mode))
pr_err("couldn't disable scanline interrupt!\n");
/*
* Ideally we'd like to disable interrupts here so that the
* fb unblanking and DCON turn on happen at a known time value;
* however, we can't do that right now with fb_blank
* messing with semaphores.
*
* For now, we just hope..
*/
if (!dcon_blank_fb(dcon, false)) {
pr_err("Failed to enter CPU mode\n");
dcon->pending_src = DCON_SOURCE_DCON;
return;
}
/* And turn off the DCON */
pdata->set_dconload(1);
dcon->load_time = ktime_get();
pr_info("The CPU has control\n");
break;
case DCON_SOURCE_DCON:
{
ktime_t delta_t;
pr_info("%s to DCON\n", __func__);
/* Clear DCONLOAD - this implies that the DCON is in control */
pdata->set_dconload(0);
dcon->load_time = ktime_get();
wait_event_timeout(dcon->waitq, dcon->switched, HZ / 2);
if (!dcon->switched) {
pr_err("Timeout entering DCON mode; expect a screen glitch.\n");
} else {
/* sometimes the DCON doesn't follow its own rules,
* and doesn't wait for two vsync pulses before
* ack'ing the frame load with an IRQ. the result
* is that the display shows the *previously*
* loaded frame. we can detect this by looking at
* the time between asserting DCONLOAD and the IRQ --
* if it's less than 20msec, then the DCON couldn't
* have seen two VSYNC pulses. in that case we
* deassert and reassert, and hope for the best.
* see http://dev.laptop.org/ticket/9664
*/
delta_t = ktime_sub(dcon->irq_time, dcon->load_time);
if (dcon->switched && ktime_to_ns(delta_t)
< NSEC_PER_MSEC * 20) {
pr_err("missed loading, retrying\n");
pdata->set_dconload(1);
mdelay(41);
pdata->set_dconload(0);
dcon->load_time = ktime_get();
mdelay(41);
}
}
dcon_blank_fb(dcon, true);
pr_info("The DCON has control\n");
break;
}
default:
BUG();
}
dcon->curr_src = source;
}
static void dcon_set_source(struct dcon_priv *dcon, int arg)
{
if (dcon->pending_src == arg)
return;
dcon->pending_src = arg;
if (dcon->curr_src != arg)
schedule_work(&dcon->switch_source);
}
static void dcon_set_source_sync(struct dcon_priv *dcon, int arg)
{
dcon_set_source(dcon, arg);
flush_work(&dcon->switch_source);
}
static ssize_t dcon_mode_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dcon_priv *dcon = dev_get_drvdata(dev);
return sprintf(buf, "%4.4X\n", dcon->disp_mode);
}
static ssize_t dcon_sleep_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dcon_priv *dcon = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", dcon->asleep);
}
static ssize_t dcon_freeze_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dcon_priv *dcon = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", dcon->curr_src == DCON_SOURCE_DCON ? 1 : 0);
}
static ssize_t dcon_mono_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dcon_priv *dcon = dev_get_drvdata(dev);
return sprintf(buf, "%d\n", dcon->mono);
}
static ssize_t dcon_resumeline_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return sprintf(buf, "%d\n", resumeline);
}
static ssize_t dcon_mono_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
unsigned long enable_mono;
int rc;
rc = kstrtoul(buf, 10, &enable_mono);
if (rc)
return rc;
dcon_set_mono_mode(dev_get_drvdata(dev), enable_mono ? true : false);
return count;
}
static ssize_t dcon_freeze_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct dcon_priv *dcon = dev_get_drvdata(dev);
unsigned long output;
int ret;
ret = kstrtoul(buf, 10, &output);
if (ret)
return ret;
switch (output) {
case 0:
dcon_set_source(dcon, DCON_SOURCE_CPU);
break;
case 1:
dcon_set_source_sync(dcon, DCON_SOURCE_DCON);
break;
case 2: /* normally unused */
dcon_set_source(dcon, DCON_SOURCE_DCON);
break;
default:
return -EINVAL;
}
return count;
}
static ssize_t dcon_resumeline_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
unsigned short rl;
int rc;
rc = kstrtou16(buf, 10, &rl);
if (rc)
return rc;
resumeline = rl;
dcon_write(dev_get_drvdata(dev), DCON_REG_SCAN_INT, resumeline);
return count;
}
static ssize_t dcon_sleep_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
unsigned long output;
int ret;
ret = kstrtoul(buf, 10, &output);
if (ret)
return ret;
dcon_sleep(dev_get_drvdata(dev), output ? true : false);
return count;
}
static struct device_attribute dcon_device_files[] = {
__ATTR(mode, 0444, dcon_mode_show, NULL),
__ATTR(sleep, 0644, dcon_sleep_show, dcon_sleep_store),
__ATTR(freeze, 0644, dcon_freeze_show, dcon_freeze_store),
__ATTR(monochrome, 0644, dcon_mono_show, dcon_mono_store),
__ATTR(resumeline, 0644, dcon_resumeline_show, dcon_resumeline_store),
};
static int dcon_bl_update(struct backlight_device *dev)
{
struct dcon_priv *dcon = bl_get_data(dev);
u8 level = backlight_get_brightness(dev) & 0x0F;
if (level != dcon->bl_val)
dcon_set_backlight(dcon, level);
/* power down the DCON when the screen is blanked */
if (!dcon->ignore_fb_events)
dcon_sleep(dcon, !!(dev->props.state & BL_CORE_FBBLANK));
return 0;
}
static int dcon_bl_get(struct backlight_device *dev)
{
struct dcon_priv *dcon = bl_get_data(dev);
return dcon->bl_val;
}
static const struct backlight_ops dcon_bl_ops = {
.update_status = dcon_bl_update,
.get_brightness = dcon_bl_get,
};
static struct backlight_properties dcon_bl_props = {
.max_brightness = 15,
.type = BACKLIGHT_RAW,
.power = FB_BLANK_UNBLANK,
};
static int dcon_reboot_notify(struct notifier_block *nb,
unsigned long foo, void *bar)
{
struct dcon_priv *dcon = container_of(nb, struct dcon_priv, reboot_nb);
if (!dcon || !dcon->client)
return NOTIFY_DONE;
/* Turn off the DCON. Entirely. */
dcon_write(dcon, DCON_REG_MODE, 0x39);
dcon_write(dcon, DCON_REG_MODE, 0x32);
return NOTIFY_DONE;
}
static int unfreeze_on_panic(struct notifier_block *nb,
unsigned long e, void *p)
{
pdata->set_dconload(1);
return NOTIFY_DONE;
}
static struct notifier_block dcon_panic_nb = {
.notifier_call = unfreeze_on_panic,
};
static int dcon_detect(struct i2c_client *client, struct i2c_board_info *info)
{
strscpy(info->type, "olpc_dcon", I2C_NAME_SIZE);
return 0;
}
static int dcon_probe(struct i2c_client *client)
{
struct dcon_priv *dcon;
int rc, i, j;
if (!pdata)
return -ENXIO;
dcon = kzalloc(sizeof(*dcon), GFP_KERNEL);
if (!dcon)
return -ENOMEM;
dcon->client = client;
init_waitqueue_head(&dcon->waitq);
INIT_WORK(&dcon->switch_source, dcon_source_switch);
dcon->reboot_nb.notifier_call = dcon_reboot_notify;
dcon->reboot_nb.priority = -1;
i2c_set_clientdata(client, dcon);
if (num_registered_fb < 1) {
dev_err(&client->dev, "DCON driver requires a registered fb\n");
rc = -EIO;
goto einit;
}
dcon->fbinfo = registered_fb[0];
rc = dcon_hw_init(dcon, 1);
if (rc)
goto einit;
/* Add the DCON device */
dcon_device = platform_device_alloc("dcon", -1);
if (!dcon_device) {
pr_err("Unable to create the DCON device\n");
rc = -ENOMEM;
goto eirq;
}
rc = platform_device_add(dcon_device);
platform_set_drvdata(dcon_device, dcon);
if (rc) {
pr_err("Unable to add the DCON device\n");
goto edev;
}
for (i = 0; i < ARRAY_SIZE(dcon_device_files); i++) {
rc = device_create_file(&dcon_device->dev,
&dcon_device_files[i]);
if (rc) {
dev_err(&dcon_device->dev, "Cannot create sysfs file\n");
goto ecreate;
}
}
dcon->bl_val = dcon_read(dcon, DCON_REG_BRIGHT) & 0x0F;
/* Add the backlight device for the DCON */
dcon_bl_props.brightness = dcon->bl_val;
dcon->bl_dev = backlight_device_register("dcon-bl", &dcon_device->dev,
dcon, &dcon_bl_ops,
&dcon_bl_props);
if (IS_ERR(dcon->bl_dev)) {
dev_err(&client->dev, "cannot register backlight dev (%ld)\n",
PTR_ERR(dcon->bl_dev));
dcon->bl_dev = NULL;
}
register_reboot_notifier(&dcon->reboot_nb);
atomic_notifier_chain_register(&panic_notifier_list, &dcon_panic_nb);
return 0;
ecreate:
for (j = 0; j < i; j++)
device_remove_file(&dcon_device->dev, &dcon_device_files[j]);
platform_device_del(dcon_device);
edev:
platform_device_put(dcon_device);
dcon_device = NULL;
eirq:
free_irq(DCON_IRQ, dcon);
einit:
kfree(dcon);
return rc;
}
static void dcon_remove(struct i2c_client *client)
{
struct dcon_priv *dcon = i2c_get_clientdata(client);
unregister_reboot_notifier(&dcon->reboot_nb);
atomic_notifier_chain_unregister(&panic_notifier_list, &dcon_panic_nb);
free_irq(DCON_IRQ, dcon);
backlight_device_unregister(dcon->bl_dev);
if (dcon_device)
platform_device_unregister(dcon_device);
cancel_work_sync(&dcon->switch_source);
kfree(dcon);
}
#ifdef CONFIG_PM
static int dcon_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct dcon_priv *dcon = i2c_get_clientdata(client);
if (!dcon->asleep) {
/* Set up the DCON to have the source */
dcon_set_source_sync(dcon, DCON_SOURCE_DCON);
}
return 0;
}
static int dcon_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct dcon_priv *dcon = i2c_get_clientdata(client);
if (!dcon->asleep) {
dcon_bus_stabilize(dcon, 0);
dcon_set_source(dcon, DCON_SOURCE_CPU);
}
return 0;
}
#else
#define dcon_suspend NULL
#define dcon_resume NULL
#endif /* CONFIG_PM */
irqreturn_t dcon_interrupt(int irq, void *id)
{
struct dcon_priv *dcon = id;
u8 status;
if (pdata->read_status(&status))
return IRQ_NONE;
switch (status & 3) {
case 3:
pr_debug("DCONLOAD_MISSED interrupt\n");
break;
case 2: /* switch to DCON mode */
case 1: /* switch to CPU mode */
dcon->switched = true;
dcon->irq_time = ktime_get();
wake_up(&dcon->waitq);
break;
case 0:
/* workaround resume case: the DCON (on 1.5) doesn't
* ever assert status 0x01 when switching to CPU mode
* during resume. this is because DCONLOAD is de-asserted
* _immediately_ upon exiting S3, so the actual release
* of the DCON happened long before this point.
* see http://dev.laptop.org/ticket/9869
*/
if (dcon->curr_src != dcon->pending_src && !dcon->switched) {
dcon->switched = true;
dcon->irq_time = ktime_get();
wake_up(&dcon->waitq);
pr_debug("switching w/ status 0/0\n");
} else {
pr_debug("scanline interrupt w/CPU\n");
}
}
return IRQ_HANDLED;
}
static const struct dev_pm_ops dcon_pm_ops = {
.suspend = dcon_suspend,
.resume = dcon_resume,
};
static const struct i2c_device_id dcon_idtable[] = {
{ "olpc_dcon", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, dcon_idtable);
static struct i2c_driver dcon_driver = {
.driver = {
.name = "olpc_dcon",
.pm = &dcon_pm_ops,
},
.class = I2C_CLASS_DDC | I2C_CLASS_HWMON,
.id_table = dcon_idtable,
.probe = dcon_probe,
.remove = dcon_remove,
.detect = dcon_detect,
.address_list = normal_i2c,
};
static int __init olpc_dcon_init(void)
{
/* XO-1.5 */
if (olpc_board_at_least(olpc_board(0xd0)))
pdata = &dcon_pdata_xo_1_5;
else
pdata = &dcon_pdata_xo_1;
return i2c_add_driver(&dcon_driver);
}
static void __exit olpc_dcon_exit(void)
{
i2c_del_driver(&dcon_driver);
}
module_init(olpc_dcon_init);
module_exit(olpc_dcon_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/staging/olpc_dcon/olpc_dcon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mainly by David Woodhouse, somewhat modified by Jordan Crouse
*
* Copyright © 2006-2007 Red Hat, Inc.
* Copyright © 2006-2007 Advanced Micro Devices, Inc.
* Copyright © 2009 VIA Technology, Inc.
* Copyright (c) 2010 Andres Salomon <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/cs5535.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <asm/olpc.h>
#include "olpc_dcon.h"
enum dcon_gpios {
OLPC_DCON_STAT0,
OLPC_DCON_STAT1,
OLPC_DCON_IRQ,
OLPC_DCON_LOAD,
OLPC_DCON_BLANK,
};
static const struct dcon_gpio gpios_asis[] = {
[OLPC_DCON_STAT0] = { .name = "dcon_stat0", .flags = GPIOD_ASIS },
[OLPC_DCON_STAT1] = { .name = "dcon_stat1", .flags = GPIOD_ASIS },
[OLPC_DCON_IRQ] = { .name = "dcon_irq", .flags = GPIOD_ASIS },
[OLPC_DCON_LOAD] = { .name = "dcon_load", .flags = GPIOD_ASIS },
[OLPC_DCON_BLANK] = { .name = "dcon_blank", .flags = GPIOD_ASIS },
};
static struct gpio_desc *gpios[5];
static int dcon_init_xo_1(struct dcon_priv *dcon)
{
unsigned char lob;
int ret, i;
const struct dcon_gpio *pin = &gpios_asis[0];
for (i = 0; i < ARRAY_SIZE(gpios_asis); i++) {
gpios[i] = devm_gpiod_get(&dcon->client->dev, pin[i].name,
pin[i].flags);
if (IS_ERR(gpios[i])) {
ret = PTR_ERR(gpios[i]);
pr_err("failed to request %s GPIO: %d\n", pin[i].name,
ret);
return ret;
}
}
/* Turn off the event enable for GPIO7 just to be safe */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_EVENTS_ENABLE);
/*
* Determine the current state by reading the GPIO bit; earlier
* stages of the boot process have established the state.
*
* Note that we read GPIO_OUTPUT_VAL rather than GPIO_READ_BACK here;
* this is because OFW will disable input for the pin and set a value..
* READ_BACK will only contain a valid value if input is enabled and
* then a value is set. So, future readings of the pin can use
* READ_BACK, but the first one cannot. Awesome, huh?
*/
dcon->curr_src = cs5535_gpio_isset(OLPC_GPIO_DCON_LOAD, GPIO_OUTPUT_VAL)
? DCON_SOURCE_CPU
: DCON_SOURCE_DCON;
dcon->pending_src = dcon->curr_src;
/* Set the directions for the GPIO pins */
gpiod_direction_input(gpios[OLPC_DCON_STAT0]);
gpiod_direction_input(gpios[OLPC_DCON_STAT1]);
gpiod_direction_input(gpios[OLPC_DCON_IRQ]);
gpiod_direction_input(gpios[OLPC_DCON_BLANK]);
gpiod_direction_output(gpios[OLPC_DCON_LOAD],
dcon->curr_src == DCON_SOURCE_CPU);
/* Set up the interrupt mappings */
/* Set the IRQ to pair 2 */
cs5535_gpio_setup_event(OLPC_GPIO_DCON_IRQ, 2, 0);
/* Enable group 2 to trigger the DCON interrupt */
cs5535_gpio_set_irq(2, DCON_IRQ);
/* Select edge level for interrupt (in PIC) */
lob = inb(0x4d0);
lob &= ~(1 << DCON_IRQ);
outb(lob, 0x4d0);
/* Register the interrupt handler */
if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", dcon)) {
pr_err("failed to request DCON's irq\n");
return -EIO;
}
/* Clear INV_EN for GPIO7 (DCONIRQ) */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_INPUT_INVERT);
/* Enable filter for GPIO12 (DCONBLANK) */
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_INPUT_FILTER);
/* Disable filter for GPIO7 */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_INPUT_FILTER);
/* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_INPUT_EVENT_COUNT);
cs5535_gpio_clear(OLPC_GPIO_DCON_BLANK, GPIO_INPUT_EVENT_COUNT);
/* Add GPIO12 to the Filter Event Pair #7 */
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_FE7_SEL);
/* Turn off negative Edge Enable for GPIO12 */
cs5535_gpio_clear(OLPC_GPIO_DCON_BLANK, GPIO_NEGATIVE_EDGE_EN);
/* Enable negative Edge Enable for GPIO7 */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_NEGATIVE_EDGE_EN);
/* Zero the filter amount for Filter Event Pair #7 */
cs5535_gpio_set(0, GPIO_FLTR7_AMOUNT);
/* Clear the negative edge status for GPIO7 and GPIO12 */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_NEGATIVE_EDGE_STS);
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_NEGATIVE_EDGE_STS);
/* FIXME: Clear the positive status as well, just to be sure */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_POSITIVE_EDGE_STS);
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_POSITIVE_EDGE_STS);
/* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_EVENTS_ENABLE);
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_EVENTS_ENABLE);
return 0;
}
static void dcon_wiggle_xo_1(void)
{
int x;
/*
* According to HiMax, when powering the DCON up we should hold
* SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
* state machine to reset to a (sane) initial state. Mitch Bradley
* did some testing and discovered that holding for 16 SMB_CLK cycles
* worked a lot more reliably, so that's what we do here.
*
* According to the cs5536 spec, to set GPIO14 to SMB_CLK we must
* simultaneously set AUX1 IN/OUT to GPIO14; ditto for SMB_DATA and
* GPIO15.
*/
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_VAL);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_ENABLE);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_ENABLE);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX1);
cs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX2);
cs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX2);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_INPUT_AUX1);
cs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);
for (x = 0; x < 16; x++) {
udelay(5);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
udelay(5);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
}
udelay(5);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX1);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_INPUT_AUX1);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);
}
static void dcon_set_dconload_1(int val)
{
gpiod_set_value(gpios[OLPC_DCON_LOAD], val);
}
static int dcon_read_status_xo_1(u8 *status)
{
*status = gpiod_get_value(gpios[OLPC_DCON_STAT0]);
*status |= gpiod_get_value(gpios[OLPC_DCON_STAT1]) << 1;
/* Clear the negative edge status for GPIO7 */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_NEGATIVE_EDGE_STS);
return 0;
}
struct dcon_platform_data dcon_pdata_xo_1 = {
.init = dcon_init_xo_1,
.bus_stabilize_wiggle = dcon_wiggle_xo_1,
.set_dconload = dcon_set_dconload_1,
.read_status = dcon_read_status_xo_1,
};
| linux-master | drivers/staging/olpc_dcon/olpc_dcon_xo_1.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2009,2010 One Laptop per Child
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <asm/olpc.h>
/* TODO: this eventually belongs in linux/vx855.h */
#define NR_VX855_GPI 14
#define NR_VX855_GPO 13
#define NR_VX855_GPIO 15
#define VX855_GPI(n) (n)
#define VX855_GPO(n) (NR_VX855_GPI + (n))
#define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n))
#include "olpc_dcon.h"
/* Hardware setup on the XO 1.5:
* DCONLOAD connects to VX855_GPIO1 (not SMBCK2)
* DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
* DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
* DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
* DCONIRQ connects to VX855_GPIO12
* DCONSMBDATA connects to VX855 graphics CRTSPD
* DCONSMBCLK connects to VX855 graphics CRTSPCLK
*/
#define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */
#define VX855_GPI_STATUS_CHG 0x450 /* PMIO_Rx50 */
#define VX855_GPI_SCI_SMI 0x452 /* PMIO_Rx52 */
#define BIT_GPIO12 0x40
#define PREFIX "OLPC DCON:"
enum dcon_gpios {
OLPC_DCON_STAT0,
OLPC_DCON_STAT1,
OLPC_DCON_LOAD,
};
struct gpiod_lookup_table gpios_table = {
.dev_id = NULL,
.table = {
GPIO_LOOKUP("VX855 South Bridge", VX855_GPIO(1), "dcon_load",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("VX855 South Bridge", VX855_GPI(10), "dcon_stat0",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("VX855 South Bridge", VX855_GPI(11), "dcon_stat1",
GPIO_ACTIVE_LOW),
{ },
},
};
static const struct dcon_gpio gpios_asis[] = {
[OLPC_DCON_STAT0] = { .name = "dcon_stat0", .flags = GPIOD_ASIS },
[OLPC_DCON_STAT1] = { .name = "dcon_stat1", .flags = GPIOD_ASIS },
[OLPC_DCON_LOAD] = { .name = "dcon_load", .flags = GPIOD_ASIS },
};
static struct gpio_desc *gpios[3];
static void dcon_clear_irq(void)
{
/* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
}
static int dcon_was_irq(void)
{
u8 tmp;
/* irq status will appear in PMIO_Rx50[6] on gpio12 */
tmp = inb(VX855_GPI_STATUS_CHG);
return !!(tmp & BIT_GPIO12);
}
static int dcon_init_xo_1_5(struct dcon_priv *dcon)
{
unsigned int irq;
const struct dcon_gpio *pin = &gpios_asis[0];
int i;
int ret;
/* Add GPIO look up table */
gpios_table.dev_id = dev_name(&dcon->client->dev);
gpiod_add_lookup_table(&gpios_table);
/* Get GPIO descriptor */
for (i = 0; i < ARRAY_SIZE(gpios_asis); i++) {
gpios[i] = devm_gpiod_get(&dcon->client->dev, pin[i].name,
pin[i].flags);
if (IS_ERR(gpios[i])) {
ret = PTR_ERR(gpios[i]);
pr_err("failed to request %s GPIO: %d\n", pin[i].name,
ret);
return ret;
}
}
dcon_clear_irq();
/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
outb(inb(VX855_GPI_SCI_SMI) | BIT_GPIO12, VX855_GPI_SCI_SMI);
/* Determine the current state of DCONLOAD, likely set by firmware */
/* GPIO1 */
dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
DCON_SOURCE_CPU : DCON_SOURCE_DCON;
dcon->pending_src = dcon->curr_src;
/* we're sharing the IRQ with ACPI */
irq = acpi_gbl_FADT.sci_interrupt;
if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
pr_err("DCON (IRQ%d) allocation failed\n", irq);
return 1;
}
return 0;
}
static void set_i2c_line(int sda, int scl)
{
unsigned char tmp;
unsigned int port = 0x26;
/* FIXME: This directly accesses the CRT GPIO controller !!! */
outb(port, 0x3c4);
tmp = inb(0x3c5);
if (scl)
tmp |= 0x20;
else
tmp &= ~0x20;
if (sda)
tmp |= 0x10;
else
tmp &= ~0x10;
tmp |= 0x01;
outb(port, 0x3c4);
outb(tmp, 0x3c5);
}
static void dcon_wiggle_xo_1_5(void)
{
int x;
/*
* According to HiMax, when powering the DCON up we should hold
* SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
* state machine to reset to a (sane) initial state. Mitch Bradley
* did some testing and discovered that holding for 16 SMB_CLK cycles
* worked a lot more reliably, so that's what we do here.
*/
set_i2c_line(1, 1);
for (x = 0; x < 16; x++) {
udelay(5);
set_i2c_line(1, 0);
udelay(5);
set_i2c_line(1, 1);
}
udelay(5);
/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
outb(inb(VX855_GPI_SCI_SMI) | BIT_GPIO12, VX855_GPI_SCI_SMI);
}
static void dcon_set_dconload_xo_1_5(int val)
{
gpiod_set_value(gpios[OLPC_DCON_LOAD], val);
}
static int dcon_read_status_xo_1_5(u8 *status)
{
if (!dcon_was_irq())
return -1;
/* i believe this is the same as "inb(0x44b) & 3" */
*status = gpiod_get_value(gpios[OLPC_DCON_STAT0]);
*status |= gpiod_get_value(gpios[OLPC_DCON_STAT1]) << 1;
dcon_clear_irq();
return 0;
}
struct dcon_platform_data dcon_pdata_xo_1_5 = {
.init = dcon_init_xo_1_5,
.bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
.set_dconload = dcon_set_dconload_xo_1_5,
.read_status = dcon_read_status_xo_1_5,
};
| linux-master | drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c |
// SPDX-License-Identifier: (GPL-2.0 OR MPL-1.1)
/*
*
* Request/Indication/MacMgmt interface handling functions
*
* Copyright (C) 1999 AbsoluteValue Systems, Inc. All Rights Reserved.
* --------------------------------------------------------------------
*
* linux-wlan
*
* --------------------------------------------------------------------
*
* Inquiries regarding the linux-wlan Open Source project can be
* made directly to:
*
* AbsoluteValue Systems Inc.
* [email protected]
* http://www.linux-wlan.com
*
* --------------------------------------------------------------------
*
* Portions of the development of this software were funded by
* Intersil Corporation as part of PRISM(R) chipset product development.
*
* --------------------------------------------------------------------
*
* This file contains the functions, types, and macros to support the
* MLME request interface that's implemented via the device ioctls.
*
* --------------------------------------------------------------------
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/skbuff.h>
#include <linux/wireless.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <net/sock.h>
#include <linux/netlink.h>
#include "p80211types.h"
#include "p80211hdr.h"
#include "p80211mgmt.h"
#include "p80211conv.h"
#include "p80211msg.h"
#include "p80211netdev.h"
#include "p80211ioctl.h"
#include "p80211metadef.h"
#include "p80211metastruct.h"
#include "p80211req.h"
static void p80211req_handlemsg(struct wlandevice *wlandev,
struct p80211msg *msg);
static void p80211req_mibset_mibget(struct wlandevice *wlandev,
struct p80211msg_dot11req_mibget *mib_msg,
int isget);
static void p80211req_handle_action(struct wlandevice *wlandev, u32 *data,
int isget, u32 flag)
{
if (isget) {
if (wlandev->hostwep & flag)
*data = P80211ENUM_truth_true;
else
*data = P80211ENUM_truth_false;
} else {
wlandev->hostwep &= ~flag;
if (*data == P80211ENUM_truth_true)
wlandev->hostwep |= flag;
}
}
/*----------------------------------------------------------------
* p80211req_dorequest
*
* Handles an MLME request/confirm message.
*
* Arguments:
* wlandev WLAN device struct
* msgbuf Buffer containing a request message
*
* Returns:
* 0 on success, an errno otherwise
*
* Call context:
* Potentially blocks the caller, so it's a good idea to
* not call this function from an interrupt context.
*----------------------------------------------------------------
*/
int p80211req_dorequest(struct wlandevice *wlandev, u8 *msgbuf)
{
struct p80211msg *msg = (struct p80211msg *)msgbuf;
/* Check to make sure the MSD is running */
if (!((wlandev->msdstate == WLAN_MSD_HWPRESENT &&
msg->msgcode == DIDMSG_LNXREQ_IFSTATE) ||
wlandev->msdstate == WLAN_MSD_RUNNING ||
wlandev->msdstate == WLAN_MSD_FWLOAD)) {
return -ENODEV;
}
/* Check Permissions */
if (!capable(CAP_NET_ADMIN) &&
(msg->msgcode != DIDMSG_DOT11REQ_MIBGET)) {
netdev_err(wlandev->netdev,
"%s: only dot11req_mibget allowed for non-root.\n",
wlandev->name);
return -EPERM;
}
/* Check for busy status */
if (test_and_set_bit(1, &wlandev->request_pending))
return -EBUSY;
/* Allow p80211 to look at msg and handle if desired. */
/* So far, all p80211 msgs are immediate, no waitq/timer necessary */
/* This may change. */
p80211req_handlemsg(wlandev, msg);
/* Pass it down to wlandev via wlandev->mlmerequest */
if (wlandev->mlmerequest)
wlandev->mlmerequest(wlandev, msg);
clear_bit(1, &wlandev->request_pending);
return 0; /* if result==0, msg->status still may contain an err */
}
/*----------------------------------------------------------------
* p80211req_handlemsg
*
* p80211 message handler. Primarily looks for messages that
* belong to p80211 and then dispatches the appropriate response.
* TODO: we don't do anything yet. Once the linuxMIB is better
* defined we'll need a get/set handler.
*
* Arguments:
* wlandev WLAN device struct
* msg message structure
*
* Returns:
* nothing (any results are set in the status field of the msg)
*
* Call context:
* Process thread
*----------------------------------------------------------------
*/
static void p80211req_handlemsg(struct wlandevice *wlandev,
struct p80211msg *msg)
{
switch (msg->msgcode) {
case DIDMSG_LNXREQ_HOSTWEP: {
struct p80211msg_lnxreq_hostwep *req =
(struct p80211msg_lnxreq_hostwep *)msg;
wlandev->hostwep &=
~(HOSTWEP_DECRYPT | HOSTWEP_ENCRYPT);
if (req->decrypt.data == P80211ENUM_truth_true)
wlandev->hostwep |= HOSTWEP_DECRYPT;
if (req->encrypt.data == P80211ENUM_truth_true)
wlandev->hostwep |= HOSTWEP_ENCRYPT;
break;
}
case DIDMSG_DOT11REQ_MIBGET:
case DIDMSG_DOT11REQ_MIBSET: {
int isget = (msg->msgcode == DIDMSG_DOT11REQ_MIBGET);
struct p80211msg_dot11req_mibget *mib_msg =
(struct p80211msg_dot11req_mibget *)msg;
p80211req_mibset_mibget(wlandev, mib_msg, isget);
break;
}
} /* switch msg->msgcode */
}
static void p80211req_mibset_mibget(struct wlandevice *wlandev,
struct p80211msg_dot11req_mibget *mib_msg,
int isget)
{
struct p80211itemd *mibitem =
(struct p80211itemd *)mib_msg->mibattribute.data;
struct p80211pstrd *pstr = (struct p80211pstrd *)mibitem->data;
u8 *key = mibitem->data + sizeof(struct p80211pstrd);
switch (mibitem->did) {
case didmib_dot11smt_wepdefaultkeystable_key(1):
case didmib_dot11smt_wepdefaultkeystable_key(2):
case didmib_dot11smt_wepdefaultkeystable_key(3):
case didmib_dot11smt_wepdefaultkeystable_key(4):
if (!isget)
wep_change_key(wlandev,
P80211DID_ITEM(mibitem->did) - 1,
key, pstr->len);
break;
case DIDMIB_DOT11SMT_PRIVACYTABLE_WEPDEFAULTKEYID: {
u32 *data = (u32 *)mibitem->data;
if (isget) {
*data = wlandev->hostwep & HOSTWEP_DEFAULTKEY_MASK;
} else {
wlandev->hostwep &= ~(HOSTWEP_DEFAULTKEY_MASK);
wlandev->hostwep |= (*data & HOSTWEP_DEFAULTKEY_MASK);
}
break;
}
case DIDMIB_DOT11SMT_PRIVACYTABLE_PRIVACYINVOKED: {
u32 *data = (u32 *)mibitem->data;
p80211req_handle_action(wlandev, data, isget,
HOSTWEP_PRIVACYINVOKED);
break;
}
case DIDMIB_DOT11SMT_PRIVACYTABLE_EXCLUDEUNENCRYPTED: {
u32 *data = (u32 *)mibitem->data;
p80211req_handle_action(wlandev, data, isget,
HOSTWEP_EXCLUDEUNENCRYPTED);
break;
}
}
}
| linux-master | drivers/staging/wlan-ng/p80211req.c |
// SPDX-License-Identifier: (GPL-2.0 OR MPL-1.1)
/*
*
* Management request handler functions.
*
* Copyright (C) 1999 AbsoluteValue Systems, Inc. All Rights Reserved.
* --------------------------------------------------------------------
*
* linux-wlan
*
* --------------------------------------------------------------------
*
* Inquiries regarding the linux-wlan Open Source project can be
* made directly to:
*
* AbsoluteValue Systems Inc.
* [email protected]
* http://www.linux-wlan.com
*
* --------------------------------------------------------------------
*
* Portions of the development of this software were funded by
* Intersil Corporation as part of PRISM(R) chipset product development.
*
* --------------------------------------------------------------------
*
* The functions in this file handle management requests sent from
* user mode.
*
* Most of these functions have two separate blocks of code that are
* conditional on whether this is a station or an AP. This is used
* to separate out the STA and AP responses to these management primitives.
* It's a choice (good, bad, indifferent?) to have the code in the same
* place so it's clear that the same primitive is implemented in both
* cases but has different behavior.
*
* --------------------------------------------------------------------
*/
#include <linux/if_arp.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/wireless.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/byteorder.h>
#include <linux/random.h>
#include <linux/usb.h>
#include <linux/bitops.h>
#include "p80211types.h"
#include "p80211hdr.h"
#include "p80211mgmt.h"
#include "p80211conv.h"
#include "p80211msg.h"
#include "p80211netdev.h"
#include "p80211metadef.h"
#include "p80211metastruct.h"
#include "hfa384x.h"
#include "prism2mgmt.h"
/* Converts 802.11 format rate specifications to prism2 */
static inline u16 p80211rate_to_p2bit(u32 rate)
{
switch (rate & ~BIT(7)) {
case 2:
return BIT(0);
case 4:
return BIT(1);
case 11:
return BIT(2);
case 22:
return BIT(3);
default:
return 0;
}
}
/*----------------------------------------------------------------
* prism2mgmt_scan
*
* Initiate a scan for BSSs.
*
* This function corresponds to MLME-scan.request and part of
* MLME-scan.confirm. As far as I can tell in the standard, there
* are no restrictions on when a scan.request may be issued. We have
* to handle in whatever state the driver/MAC happen to be.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
* interrupt
*----------------------------------------------------------------
*/
int prism2mgmt_scan(struct wlandevice *wlandev, void *msgp)
{
int result = 0;
struct hfa384x *hw = wlandev->priv;
struct p80211msg_dot11req_scan *msg = msgp;
u16 roamingmode, word;
int i, timeout;
int istmpenable = 0;
struct hfa384x_host_scan_request_data scanreq;
/* gatekeeper check */
if (HFA384x_FIRMWARE_VERSION(hw->ident_sta_fw.major,
hw->ident_sta_fw.minor,
hw->ident_sta_fw.variant) <
HFA384x_FIRMWARE_VERSION(1, 3, 2)) {
netdev_err(wlandev->netdev,
"HostScan not supported with current firmware (<1.3.2).\n");
result = 1;
msg->resultcode.data = P80211ENUM_resultcode_not_supported;
goto exit;
}
memset(&scanreq, 0, sizeof(scanreq));
/* save current roaming mode */
result = hfa384x_drvr_getconfig16(hw,
HFA384x_RID_CNFROAMINGMODE,
&roamingmode);
if (result) {
netdev_err(wlandev->netdev,
"getconfig(ROAMMODE) failed. result=%d\n", result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
/* drop into mode 3 for the scan */
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFROAMINGMODE,
HFA384x_ROAMMODE_HOSTSCAN_HOSTROAM);
if (result) {
netdev_err(wlandev->netdev,
"setconfig(ROAMINGMODE) failed. result=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
/* active or passive? */
if (HFA384x_FIRMWARE_VERSION(hw->ident_sta_fw.major,
hw->ident_sta_fw.minor,
hw->ident_sta_fw.variant) >
HFA384x_FIRMWARE_VERSION(1, 5, 0)) {
if (msg->scantype.data != P80211ENUM_scantype_active)
word = msg->maxchanneltime.data;
else
word = 0;
result =
hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFPASSIVESCANCTRL,
word);
if (result) {
netdev_warn(wlandev->netdev,
"Passive scan not supported with current firmware. (<1.5.1)\n");
}
}
/* set up the txrate to be 2MBPS. Should be fastest basicrate... */
word = HFA384x_RATEBIT_2;
scanreq.tx_rate = cpu_to_le16(word);
/* set up the channel list */
word = 0;
for (i = 0; i < msg->channellist.data.len; i++) {
u8 channel = msg->channellist.data.data[i];
if (channel > 14)
continue;
/* channel 1 is BIT 0 ... channel 14 is BIT 13 */
word |= (1 << (channel - 1));
}
scanreq.channel_list = cpu_to_le16(word);
/* set up the ssid, if present. */
scanreq.ssid.len = cpu_to_le16(msg->ssid.data.len);
memcpy(scanreq.ssid.data, msg->ssid.data.data, msg->ssid.data.len);
/* Enable the MAC port if it's not already enabled */
result = hfa384x_drvr_getconfig16(hw, HFA384x_RID_PORTSTATUS, &word);
if (result) {
netdev_err(wlandev->netdev,
"getconfig(PORTSTATUS) failed. result=%d\n", result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
if (word == HFA384x_PORTSTATUS_DISABLED) {
__le16 wordbuf[17];
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFROAMINGMODE,
HFA384x_ROAMMODE_HOSTSCAN_HOSTROAM);
if (result) {
netdev_err(wlandev->netdev,
"setconfig(ROAMINGMODE) failed. result=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
/* Construct a bogus SSID and assign it to OwnSSID and
* DesiredSSID
*/
wordbuf[0] = cpu_to_le16(WLAN_SSID_MAXLEN);
get_random_bytes(&wordbuf[1], WLAN_SSID_MAXLEN);
result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFOWNSSID,
wordbuf,
HFA384x_RID_CNFOWNSSID_LEN);
if (result) {
netdev_err(wlandev->netdev, "Failed to set OwnSSID.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFDESIREDSSID,
wordbuf,
HFA384x_RID_CNFDESIREDSSID_LEN);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set DesiredSSID.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
/* bsstype */
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFPORTTYPE,
HFA384x_PORTTYPE_IBSS);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set CNFPORTTYPE.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
/* ibss options */
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CREATEIBSS,
HFA384x_CREATEIBSS_JOINCREATEIBSS);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set CREATEIBSS.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
result = hfa384x_drvr_enable(hw, 0);
if (result) {
netdev_err(wlandev->netdev,
"drvr_enable(0) failed. result=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
istmpenable = 1;
}
/* Figure out our timeout first Kus, then HZ */
timeout = msg->channellist.data.len * msg->maxchanneltime.data;
timeout = (timeout * HZ) / 1000;
/* Issue the scan request */
hw->scanflag = 0;
result = hfa384x_drvr_setconfig(hw,
HFA384x_RID_HOSTSCAN, &scanreq,
sizeof(scanreq));
if (result) {
netdev_err(wlandev->netdev,
"setconfig(SCANREQUEST) failed. result=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
/* sleep until info frame arrives */
wait_event_interruptible_timeout(hw->cmdq, hw->scanflag, timeout);
msg->numbss.status = P80211ENUM_msgitem_status_data_ok;
if (hw->scanflag == -1)
hw->scanflag = 0;
msg->numbss.data = hw->scanflag;
hw->scanflag = 0;
/* Disable port if we temporarily enabled it. */
if (istmpenable) {
result = hfa384x_drvr_disable(hw, 0);
if (result) {
netdev_err(wlandev->netdev,
"drvr_disable(0) failed. result=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
}
/* restore original roaming mode */
result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFROAMINGMODE,
roamingmode);
if (result) {
netdev_err(wlandev->netdev,
"setconfig(ROAMMODE) failed. result=%d\n", result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
goto exit;
}
result = 0;
msg->resultcode.data = P80211ENUM_resultcode_success;
exit:
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
return result;
}
/*----------------------------------------------------------------
* prism2mgmt_scan_results
*
* Retrieve the BSS description for one of the BSSs identified in
* a scan.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
* interrupt
*----------------------------------------------------------------
*/
int prism2mgmt_scan_results(struct wlandevice *wlandev, void *msgp)
{
int result = 0;
struct p80211msg_dot11req_scan_results *req;
struct hfa384x *hw = wlandev->priv;
struct hfa384x_hscan_result_sub *item = NULL;
int count;
req = msgp;
req->resultcode.status = P80211ENUM_msgitem_status_data_ok;
if (!hw->scanresults) {
netdev_err(wlandev->netdev,
"dot11req_scan_results can only be used after a successful dot11req_scan.\n");
result = 2;
req->resultcode.data = P80211ENUM_resultcode_invalid_parameters;
goto exit;
}
count = (hw->scanresults->framelen - 3) / 32;
if (count > HFA384x_SCANRESULT_MAX)
count = HFA384x_SCANRESULT_MAX;
if (req->bssindex.data >= count) {
netdev_dbg(wlandev->netdev,
"requested index (%d) out of range (%d)\n",
req->bssindex.data, count);
result = 2;
req->resultcode.data = P80211ENUM_resultcode_invalid_parameters;
goto exit;
}
item = &hw->scanresults->info.hscanresult.result[req->bssindex.data];
/* signal and noise */
req->signal.status = P80211ENUM_msgitem_status_data_ok;
req->noise.status = P80211ENUM_msgitem_status_data_ok;
req->signal.data = le16_to_cpu(item->sl);
req->noise.data = le16_to_cpu(item->anl);
/* BSSID */
req->bssid.status = P80211ENUM_msgitem_status_data_ok;
req->bssid.data.len = WLAN_BSSID_LEN;
memcpy(req->bssid.data.data, item->bssid, WLAN_BSSID_LEN);
/* SSID */
req->ssid.status = P80211ENUM_msgitem_status_data_ok;
req->ssid.data.len = le16_to_cpu(item->ssid.len);
req->ssid.data.len = min_t(u16, req->ssid.data.len, WLAN_SSID_MAXLEN);
memcpy(req->ssid.data.data, item->ssid.data, req->ssid.data.len);
/* supported rates */
for (count = 0; count < 10; count++)
if (item->supprates[count] == 0)
break;
for (int i = 0; i < 8; i++) {
if (count > i &&
DOT11_RATE5_ISBASIC_GET(item->supprates[i])) {
req->basicrate[i].data = item->supprates[i];
req->basicrate[i].status =
P80211ENUM_msgitem_status_data_ok;
}
}
for (int i = 0; i < 8; i++) {
if (count > i) {
req->supprate[i].data = item->supprates[i];
req->supprate[i].status =
P80211ENUM_msgitem_status_data_ok;
}
}
/* beacon period */
req->beaconperiod.status = P80211ENUM_msgitem_status_data_ok;
req->beaconperiod.data = le16_to_cpu(item->bcnint);
/* timestamps */
req->timestamp.status = P80211ENUM_msgitem_status_data_ok;
req->timestamp.data = jiffies;
req->localtime.status = P80211ENUM_msgitem_status_data_ok;
req->localtime.data = jiffies;
/* atim window */
req->ibssatimwindow.status = P80211ENUM_msgitem_status_data_ok;
req->ibssatimwindow.data = le16_to_cpu(item->atim);
/* Channel */
req->dschannel.status = P80211ENUM_msgitem_status_data_ok;
req->dschannel.data = le16_to_cpu(item->chid);
/* capinfo bits */
count = le16_to_cpu(item->capinfo);
req->capinfo.status = P80211ENUM_msgitem_status_data_ok;
req->capinfo.data = count;
/* privacy flag */
req->privacy.status = P80211ENUM_msgitem_status_data_ok;
req->privacy.data = WLAN_GET_MGMT_CAP_INFO_PRIVACY(count);
/* cfpollable */
req->cfpollable.status = P80211ENUM_msgitem_status_data_ok;
req->cfpollable.data = WLAN_GET_MGMT_CAP_INFO_CFPOLLABLE(count);
/* cfpollreq */
req->cfpollreq.status = P80211ENUM_msgitem_status_data_ok;
req->cfpollreq.data = WLAN_GET_MGMT_CAP_INFO_CFPOLLREQ(count);
/* bsstype */
req->bsstype.status = P80211ENUM_msgitem_status_data_ok;
req->bsstype.data = (WLAN_GET_MGMT_CAP_INFO_ESS(count)) ?
P80211ENUM_bsstype_infrastructure : P80211ENUM_bsstype_independent;
result = 0;
req->resultcode.data = P80211ENUM_resultcode_success;
exit:
return result;
}
/*----------------------------------------------------------------
* prism2mgmt_start
*
* Start a BSS. Any station can do this for IBSS, only AP for ESS.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
* interrupt
*----------------------------------------------------------------
*/
int prism2mgmt_start(struct wlandevice *wlandev, void *msgp)
{
int result = 0;
struct hfa384x *hw = wlandev->priv;
struct p80211msg_dot11req_start *msg = msgp;
struct p80211pstrd *pstr;
u8 bytebuf[80];
struct hfa384x_bytestr *p2bytestr = (struct hfa384x_bytestr *)bytebuf;
u16 word;
wlandev->macmode = WLAN_MACMODE_NONE;
/* Set the SSID */
memcpy(&wlandev->ssid, &msg->ssid.data, sizeof(msg->ssid.data));
/*** ADHOC IBSS ***/
/* see if current f/w is less than 8c3 */
if (HFA384x_FIRMWARE_VERSION(hw->ident_sta_fw.major,
hw->ident_sta_fw.minor,
hw->ident_sta_fw.variant) <
HFA384x_FIRMWARE_VERSION(0, 8, 3)) {
/* Ad-Hoc not quite supported on Prism2 */
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
msg->resultcode.data = P80211ENUM_resultcode_not_supported;
goto done;
}
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
/*** STATION ***/
/* Set the REQUIRED config items */
/* SSID */
pstr = (struct p80211pstrd *)&msg->ssid.data;
prism2mgmt_pstr2bytestr(p2bytestr, pstr);
result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFOWNSSID,
bytebuf, HFA384x_RID_CNFOWNSSID_LEN);
if (result) {
netdev_err(wlandev->netdev, "Failed to set CnfOwnSSID\n");
goto failed;
}
result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFDESIREDSSID,
bytebuf,
HFA384x_RID_CNFDESIREDSSID_LEN);
if (result) {
netdev_err(wlandev->netdev, "Failed to set CnfDesiredSSID\n");
goto failed;
}
/* bsstype - we use the default in the ap firmware */
/* IBSS port */
hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFPORTTYPE, 0);
/* beacon period */
word = msg->beaconperiod.data;
result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFAPBCNINT, word);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set beacon period=%d.\n", word);
goto failed;
}
/* dschannel */
word = msg->dschannel.data;
result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFOWNCHANNEL, word);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set channel=%d.\n", word);
goto failed;
}
/* Basic rates */
word = p80211rate_to_p2bit(msg->basicrate1.data);
if (msg->basicrate2.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate2.data);
if (msg->basicrate3.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate3.data);
if (msg->basicrate4.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate4.data);
if (msg->basicrate5.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate5.data);
if (msg->basicrate6.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate6.data);
if (msg->basicrate7.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate7.data);
if (msg->basicrate8.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->basicrate8.data);
result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFBASICRATES, word);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set basicrates=%d.\n", word);
goto failed;
}
/* Operational rates (supprates and txratecontrol) */
word = p80211rate_to_p2bit(msg->operationalrate1.data);
if (msg->operationalrate2.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate2.data);
if (msg->operationalrate3.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate3.data);
if (msg->operationalrate4.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate4.data);
if (msg->operationalrate5.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate5.data);
if (msg->operationalrate6.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate6.data);
if (msg->operationalrate7.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate7.data);
if (msg->operationalrate8.status == P80211ENUM_msgitem_status_data_ok)
word |= p80211rate_to_p2bit(msg->operationalrate8.data);
result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFSUPPRATES, word);
if (result) {
netdev_err(wlandev->netdev,
"Failed to set supprates=%d.\n", word);
goto failed;
}
result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_TXRATECNTL, word);
if (result) {
netdev_err(wlandev->netdev, "Failed to set txrates=%d.\n",
word);
goto failed;
}
/* Set the macmode so the frame setup code knows what to do */
if (msg->bsstype.data == P80211ENUM_bsstype_independent) {
wlandev->macmode = WLAN_MACMODE_IBSS_STA;
/* lets extend the data length a bit */
hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFMAXDATALEN, 2304);
}
/* Enable the Port */
result = hfa384x_drvr_enable(hw, 0);
if (result) {
netdev_err(wlandev->netdev,
"Enable macport failed, result=%d.\n", result);
goto failed;
}
msg->resultcode.data = P80211ENUM_resultcode_success;
goto done;
failed:
netdev_dbg(wlandev->netdev,
"Failed to set a config option, result=%d\n", result);
msg->resultcode.data = P80211ENUM_resultcode_invalid_parameters;
done:
return 0;
}
/*----------------------------------------------------------------
* prism2mgmt_readpda
*
* Collect the PDA data and put it in the message.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
*----------------------------------------------------------------
*/
int prism2mgmt_readpda(struct wlandevice *wlandev, void *msgp)
{
struct hfa384x *hw = wlandev->priv;
struct p80211msg_p2req_readpda *msg = msgp;
int result;
/* We only support collecting the PDA when in the FWLOAD
* state.
*/
if (wlandev->msdstate != WLAN_MSD_FWLOAD) {
netdev_err(wlandev->netdev,
"PDA may only be read in the fwload state.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
} else {
/* Call drvr_readpda(), it handles the auxport enable
* and validating the returned PDA.
*/
result = hfa384x_drvr_readpda(hw,
msg->pda.data,
HFA384x_PDA_LEN_MAX);
if (result) {
netdev_err(wlandev->netdev,
"hfa384x_drvr_readpda() failed, result=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
msg->resultcode.status =
P80211ENUM_msgitem_status_data_ok;
return 0;
}
msg->pda.status = P80211ENUM_msgitem_status_data_ok;
msg->resultcode.data = P80211ENUM_resultcode_success;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
}
return 0;
}
/*----------------------------------------------------------------
* prism2mgmt_ramdl_state
*
* Establishes the beginning/end of a card RAM download session.
*
* It is expected that the ramdl_write() function will be called
* one or more times between the 'enable' and 'disable' calls to
* this function.
*
* Note: This function should not be called when a mac comm port
* is active.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
*----------------------------------------------------------------
*/
int prism2mgmt_ramdl_state(struct wlandevice *wlandev, void *msgp)
{
struct hfa384x *hw = wlandev->priv;
struct p80211msg_p2req_ramdl_state *msg = msgp;
if (wlandev->msdstate != WLAN_MSD_FWLOAD) {
netdev_err(wlandev->netdev,
"ramdl_state(): may only be called in the fwload state.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
return 0;
}
/*
** Note: Interrupts are locked out if this is an AP and are NOT
** locked out if this is a station.
*/
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
if (msg->enable.data == P80211ENUM_truth_true) {
if (hfa384x_drvr_ramdl_enable(hw, msg->exeaddr.data)) {
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
} else {
msg->resultcode.data = P80211ENUM_resultcode_success;
}
} else {
hfa384x_drvr_ramdl_disable(hw);
msg->resultcode.data = P80211ENUM_resultcode_success;
}
return 0;
}
/*----------------------------------------------------------------
* prism2mgmt_ramdl_write
*
* Writes a buffer to the card RAM using the download state. This
* is for writing code to card RAM. To just read or write raw data
* use the aux functions.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
*----------------------------------------------------------------
*/
int prism2mgmt_ramdl_write(struct wlandevice *wlandev, void *msgp)
{
struct hfa384x *hw = wlandev->priv;
struct p80211msg_p2req_ramdl_write *msg = msgp;
u32 addr;
u32 len;
u8 *buf;
if (wlandev->msdstate != WLAN_MSD_FWLOAD) {
netdev_err(wlandev->netdev,
"ramdl_write(): may only be called in the fwload state.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
return 0;
}
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
/* first validate the length */
if (msg->len.data > sizeof(msg->data.data)) {
msg->resultcode.status =
P80211ENUM_resultcode_invalid_parameters;
return 0;
}
/* call the hfa384x function to do the write */
addr = msg->addr.data;
len = msg->len.data;
buf = msg->data.data;
if (hfa384x_drvr_ramdl_write(hw, addr, buf, len))
msg->resultcode.data = P80211ENUM_resultcode_refused;
msg->resultcode.data = P80211ENUM_resultcode_success;
return 0;
}
/*----------------------------------------------------------------
* prism2mgmt_flashdl_state
*
* Establishes the beginning/end of a card Flash download session.
*
* It is expected that the flashdl_write() function will be called
* one or more times between the 'enable' and 'disable' calls to
* this function.
*
* Note: This function should not be called when a mac comm port
* is active.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
*----------------------------------------------------------------
*/
int prism2mgmt_flashdl_state(struct wlandevice *wlandev, void *msgp)
{
int result = 0;
struct hfa384x *hw = wlandev->priv;
struct p80211msg_p2req_flashdl_state *msg = msgp;
if (wlandev->msdstate != WLAN_MSD_FWLOAD) {
netdev_err(wlandev->netdev,
"flashdl_state(): may only be called in the fwload state.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
return 0;
}
/*
** Note: Interrupts are locked out if this is an AP and are NOT
** locked out if this is a station.
*/
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
if (msg->enable.data == P80211ENUM_truth_true) {
if (hfa384x_drvr_flashdl_enable(hw)) {
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
} else {
msg->resultcode.data = P80211ENUM_resultcode_success;
}
} else {
hfa384x_drvr_flashdl_disable(hw);
msg->resultcode.data = P80211ENUM_resultcode_success;
/* NOTE: At this point, the MAC is in the post-reset
* state and the driver is in the fwload state.
* We need to get the MAC back into the fwload
* state. To do this, we set the nsdstate to HWPRESENT
* and then call the ifstate function to redo everything
* that got us into the fwload state.
*/
wlandev->msdstate = WLAN_MSD_HWPRESENT;
result = prism2sta_ifstate(wlandev, P80211ENUM_ifstate_fwload);
if (result != P80211ENUM_resultcode_success) {
netdev_err(wlandev->netdev,
"prism2sta_ifstate(fwload) failed, P80211ENUM_resultcode=%d\n",
result);
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
result = -1;
}
}
return result;
}
/*----------------------------------------------------------------
* prism2mgmt_flashdl_write
*
*
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
*----------------------------------------------------------------
*/
int prism2mgmt_flashdl_write(struct wlandevice *wlandev, void *msgp)
{
struct hfa384x *hw = wlandev->priv;
struct p80211msg_p2req_flashdl_write *msg = msgp;
u32 addr;
u32 len;
u8 *buf;
if (wlandev->msdstate != WLAN_MSD_FWLOAD) {
netdev_err(wlandev->netdev,
"flashdl_write(): may only be called in the fwload state.\n");
msg->resultcode.data =
P80211ENUM_resultcode_implementation_failure;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
return 0;
}
/*
** Note: Interrupts are locked out if this is an AP and are NOT
** locked out if this is a station.
*/
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
/* first validate the length */
if (msg->len.data > sizeof(msg->data.data)) {
msg->resultcode.status =
P80211ENUM_resultcode_invalid_parameters;
return 0;
}
/* call the hfa384x function to do the write */
addr = msg->addr.data;
len = msg->len.data;
buf = msg->data.data;
if (hfa384x_drvr_flashdl_write(hw, addr, buf, len))
msg->resultcode.data = P80211ENUM_resultcode_refused;
msg->resultcode.data = P80211ENUM_resultcode_success;
return 0;
}
/*----------------------------------------------------------------
* prism2mgmt_autojoin
*
* Associate with an ESS.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
* interrupt
*----------------------------------------------------------------
*/
int prism2mgmt_autojoin(struct wlandevice *wlandev, void *msgp)
{
struct hfa384x *hw = wlandev->priv;
int result = 0;
u16 reg;
u16 port_type;
struct p80211msg_lnxreq_autojoin *msg = msgp;
struct p80211pstrd *pstr;
u8 bytebuf[256];
struct hfa384x_bytestr *p2bytestr = (struct hfa384x_bytestr *)bytebuf;
wlandev->macmode = WLAN_MACMODE_NONE;
/* Set the SSID */
memcpy(&wlandev->ssid, &msg->ssid.data, sizeof(msg->ssid.data));
/* Disable the Port */
hfa384x_drvr_disable(hw, 0);
/*** STATION ***/
/* Set the TxRates */
hfa384x_drvr_setconfig16(hw, HFA384x_RID_TXRATECNTL, 0x000f);
/* Set the auth type */
if (msg->authtype.data == P80211ENUM_authalg_sharedkey)
reg = HFA384x_CNFAUTHENTICATION_SHAREDKEY;
else
reg = HFA384x_CNFAUTHENTICATION_OPENSYSTEM;
hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFAUTHENTICATION, reg);
/* Set the ssid */
memset(bytebuf, 0, 256);
pstr = (struct p80211pstrd *)&msg->ssid.data;
prism2mgmt_pstr2bytestr(p2bytestr, pstr);
result = hfa384x_drvr_setconfig(hw, HFA384x_RID_CNFDESIREDSSID,
bytebuf,
HFA384x_RID_CNFDESIREDSSID_LEN);
port_type = HFA384x_PORTTYPE_BSS;
/* Set the PortType */
hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFPORTTYPE, port_type);
/* Enable the Port */
hfa384x_drvr_enable(hw, 0);
/* Set the resultcode */
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
msg->resultcode.data = P80211ENUM_resultcode_success;
return result;
}
/*----------------------------------------------------------------
* prism2mgmt_wlansniff
*
* Start or stop sniffing.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* 0 success and done
* <0 success, but we're waiting for something to finish.
* >0 an error occurred while handling the message.
* Side effects:
*
* Call context:
* process thread (usually)
* interrupt
*----------------------------------------------------------------
*/
int prism2mgmt_wlansniff(struct wlandevice *wlandev, void *msgp)
{
int result = 0;
struct p80211msg_lnxreq_wlansniff *msg = msgp;
struct hfa384x *hw = wlandev->priv;
u16 word;
msg->resultcode.status = P80211ENUM_msgitem_status_data_ok;
switch (msg->enable.data) {
case P80211ENUM_truth_false:
/* Confirm that we're in monitor mode */
if (wlandev->netdev->type == ARPHRD_ETHER) {
msg->resultcode.data =
P80211ENUM_resultcode_invalid_parameters;
return 0;
}
/* Disable monitor mode */
result = hfa384x_cmd_monitor(hw, HFA384x_MONITOR_DISABLE);
if (result) {
netdev_dbg(wlandev->netdev,
"failed to disable monitor mode, result=%d\n",
result);
goto failed;
}
/* Disable port 0 */
result = hfa384x_drvr_disable(hw, 0);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to disable port 0 after sniffing, result=%d\n",
result);
goto failed;
}
/* Clear the driver state */
wlandev->netdev->type = ARPHRD_ETHER;
/* Restore the wepflags */
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFWEPFLAGS,
hw->presniff_wepflags);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to restore wepflags=0x%04x, result=%d\n",
hw->presniff_wepflags, result);
goto failed;
}
/* Set the port to its prior type and enable (if necessary) */
if (hw->presniff_port_type != 0) {
word = hw->presniff_port_type;
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFPORTTYPE,
word);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to restore porttype, result=%d\n",
result);
goto failed;
}
/* Enable the port */
result = hfa384x_drvr_enable(hw, 0);
if (result) {
netdev_dbg(wlandev->netdev,
"failed to enable port to presniff setting, result=%d\n",
result);
goto failed;
}
} else {
result = hfa384x_drvr_disable(hw, 0);
}
netdev_info(wlandev->netdev, "monitor mode disabled\n");
msg->resultcode.data = P80211ENUM_resultcode_success;
return 0;
case P80211ENUM_truth_true:
/* Disable the port (if enabled), only check Port 0 */
if (hw->port_enabled[0]) {
if (wlandev->netdev->type == ARPHRD_ETHER) {
/* Save macport 0 state */
result = hfa384x_drvr_getconfig16(hw,
HFA384x_RID_CNFPORTTYPE,
&hw->presniff_port_type);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to read porttype, result=%d\n",
result);
goto failed;
}
/* Save the wepflags state */
result = hfa384x_drvr_getconfig16(hw,
HFA384x_RID_CNFWEPFLAGS,
&hw->presniff_wepflags);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to read wepflags, result=%d\n",
result);
goto failed;
}
hfa384x_drvr_stop(hw);
result = hfa384x_drvr_start(hw);
if (result) {
netdev_dbg(wlandev->netdev,
"failed to restart the card for sniffing, result=%d\n",
result);
goto failed;
}
} else {
/* Disable the port */
result = hfa384x_drvr_disable(hw, 0);
if (result) {
netdev_dbg(wlandev->netdev,
"failed to enable port for sniffing, result=%d\n",
result);
goto failed;
}
}
} else {
hw->presniff_port_type = 0;
}
/* Set the channel we wish to sniff */
word = msg->channel.data;
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFOWNCHANNEL,
word);
hw->sniff_channel = word;
if (result) {
netdev_dbg(wlandev->netdev,
"failed to set channel %d, result=%d\n",
word, result);
goto failed;
}
/* Now if we're already sniffing, we can skip the rest */
if (wlandev->netdev->type != ARPHRD_ETHER) {
/* Set the port type to pIbss */
word = HFA384x_PORTTYPE_PSUEDOIBSS;
result = hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFPORTTYPE,
word);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to set porttype %d, result=%d\n",
word, result);
goto failed;
}
if ((msg->keepwepflags.status ==
P80211ENUM_msgitem_status_data_ok) &&
(msg->keepwepflags.data != P80211ENUM_truth_true)) {
/* Set the wepflags for no decryption */
word = HFA384x_WEPFLAGS_DISABLE_TXCRYPT |
HFA384x_WEPFLAGS_DISABLE_RXCRYPT;
result =
hfa384x_drvr_setconfig16(hw,
HFA384x_RID_CNFWEPFLAGS,
word);
}
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to set wepflags=0x%04x, result=%d\n",
word, result);
goto failed;
}
}
/* Do we want to strip the FCS in monitor mode? */
if ((msg->stripfcs.status ==
P80211ENUM_msgitem_status_data_ok) &&
(msg->stripfcs.data == P80211ENUM_truth_true)) {
hw->sniff_fcs = 0;
} else {
hw->sniff_fcs = 1;
}
/* Do we want to truncate the packets? */
if (msg->packet_trunc.status ==
P80211ENUM_msgitem_status_data_ok) {
hw->sniff_truncate = msg->packet_trunc.data;
} else {
hw->sniff_truncate = 0;
}
/* Enable the port */
result = hfa384x_drvr_enable(hw, 0);
if (result) {
netdev_dbg
(wlandev->netdev,
"failed to enable port for sniffing, result=%d\n",
result);
goto failed;
}
/* Enable monitor mode */
result = hfa384x_cmd_monitor(hw, HFA384x_MONITOR_ENABLE);
if (result) {
netdev_dbg(wlandev->netdev,
"failed to enable monitor mode, result=%d\n",
result);
goto failed;
}
if (wlandev->netdev->type == ARPHRD_ETHER)
netdev_info(wlandev->netdev, "monitor mode enabled\n");
/* Set the driver state */
/* Do we want the prism2 header? */
if ((msg->prismheader.status ==
P80211ENUM_msgitem_status_data_ok) &&
(msg->prismheader.data == P80211ENUM_truth_true)) {
hw->sniffhdr = 0;
wlandev->netdev->type = ARPHRD_IEEE80211_PRISM;
} else if ((msg->wlanheader.status ==
P80211ENUM_msgitem_status_data_ok) &&
(msg->wlanheader.data == P80211ENUM_truth_true)) {
hw->sniffhdr = 1;
wlandev->netdev->type = ARPHRD_IEEE80211_PRISM;
} else {
wlandev->netdev->type = ARPHRD_IEEE80211;
}
msg->resultcode.data = P80211ENUM_resultcode_success;
return 0;
default:
msg->resultcode.data = P80211ENUM_resultcode_invalid_parameters;
return 0;
}
failed:
msg->resultcode.data = P80211ENUM_resultcode_refused;
return 0;
}
| linux-master | drivers/staging/wlan-ng/prism2mgmt.c |
// SPDX-License-Identifier: GPL-2.0
/* cfg80211 Interface for prism2_usb module */
#include "hfa384x.h"
#include "prism2mgmt.h"
/* Prism2 channel/frequency/bitrate declarations */
static const struct ieee80211_channel prism2_channels[] = {
{ .center_freq = 2412 },
{ .center_freq = 2417 },
{ .center_freq = 2422 },
{ .center_freq = 2427 },
{ .center_freq = 2432 },
{ .center_freq = 2437 },
{ .center_freq = 2442 },
{ .center_freq = 2447 },
{ .center_freq = 2452 },
{ .center_freq = 2457 },
{ .center_freq = 2462 },
{ .center_freq = 2467 },
{ .center_freq = 2472 },
{ .center_freq = 2484 },
};
static const struct ieee80211_rate prism2_rates[] = {
{ .bitrate = 10 },
{ .bitrate = 20 },
{ .bitrate = 55 },
{ .bitrate = 110 }
};
#define PRISM2_NUM_CIPHER_SUITES 2
static const u32 prism2_cipher_suites[PRISM2_NUM_CIPHER_SUITES] = {
WLAN_CIPHER_SUITE_WEP40,
WLAN_CIPHER_SUITE_WEP104
};
/* prism2 device private data */
struct prism2_wiphy_private {
struct wlandevice *wlandev;
struct ieee80211_supported_band band;
struct ieee80211_channel channels[ARRAY_SIZE(prism2_channels)];
struct ieee80211_rate rates[ARRAY_SIZE(prism2_rates)];
struct cfg80211_scan_request *scan_request;
};
static const void * const prism2_wiphy_privid = &prism2_wiphy_privid;
/* Helper Functions */
static int prism2_result2err(int prism2_result)
{
int err = 0;
switch (prism2_result) {
case P80211ENUM_resultcode_invalid_parameters:
err = -EINVAL;
break;
case P80211ENUM_resultcode_implementation_failure:
err = -EIO;
break;
case P80211ENUM_resultcode_not_supported:
err = -EOPNOTSUPP;
break;
default:
err = 0;
break;
}
return err;
}
static int prism2_domibset_uint32(struct wlandevice *wlandev,
u32 did, u32 data)
{
struct p80211msg_dot11req_mibset msg;
struct p80211item_uint32 *mibitem =
(struct p80211item_uint32 *)&msg.mibattribute.data;
msg.msgcode = DIDMSG_DOT11REQ_MIBSET;
mibitem->did = did;
mibitem->data = data;
return p80211req_dorequest(wlandev, (u8 *)&msg);
}
static int prism2_domibset_pstr32(struct wlandevice *wlandev,
u32 did, u8 len, const u8 *data)
{
struct p80211msg_dot11req_mibset msg;
struct p80211item_pstr32 *mibitem =
(struct p80211item_pstr32 *)&msg.mibattribute.data;
msg.msgcode = DIDMSG_DOT11REQ_MIBSET;
mibitem->did = did;
mibitem->data.len = len;
memcpy(mibitem->data.data, data, len);
return p80211req_dorequest(wlandev, (u8 *)&msg);
}
/* The interface functions, called by the cfg80211 layer */
static int prism2_change_virtual_intf(struct wiphy *wiphy,
struct net_device *dev,
enum nl80211_iftype type,
struct vif_params *params)
{
struct wlandevice *wlandev = dev->ml_priv;
u32 data;
int result;
int err = 0;
switch (type) {
case NL80211_IFTYPE_ADHOC:
if (wlandev->macmode == WLAN_MACMODE_IBSS_STA)
goto exit;
wlandev->macmode = WLAN_MACMODE_IBSS_STA;
data = 0;
break;
case NL80211_IFTYPE_STATION:
if (wlandev->macmode == WLAN_MACMODE_ESS_STA)
goto exit;
wlandev->macmode = WLAN_MACMODE_ESS_STA;
data = 1;
break;
default:
netdev_warn(dev, "Operation mode: %d not support\n", type);
return -EOPNOTSUPP;
}
/* Set Operation mode to the PORT TYPE RID */
result = prism2_domibset_uint32(wlandev,
DIDMIB_P2_STATIC_CNFPORTTYPE,
data);
if (result)
err = -EFAULT;
dev->ieee80211_ptr->iftype = type;
exit:
return err;
}
static int prism2_add_key(struct wiphy *wiphy, struct net_device *dev,
int link_id, u8 key_index, bool pairwise,
const u8 *mac_addr, struct key_params *params)
{
struct wlandevice *wlandev = dev->ml_priv;
u32 did;
if (key_index >= NUM_WEPKEYS)
return -EINVAL;
if (params->cipher != WLAN_CIPHER_SUITE_WEP40 &&
params->cipher != WLAN_CIPHER_SUITE_WEP104) {
pr_debug("Unsupported cipher suite\n");
return -EFAULT;
}
if (prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_WEPDEFAULTKEYID,
key_index))
return -EFAULT;
/* send key to driver */
did = didmib_dot11smt_wepdefaultkeystable_key(key_index + 1);
if (prism2_domibset_pstr32(wlandev, did, params->key_len, params->key))
return -EFAULT;
return 0;
}
static int prism2_get_key(struct wiphy *wiphy, struct net_device *dev,
int link_id, u8 key_index, bool pairwise,
const u8 *mac_addr, void *cookie,
void (*callback)(void *cookie, struct key_params*))
{
struct wlandevice *wlandev = dev->ml_priv;
struct key_params params;
int len;
if (key_index >= NUM_WEPKEYS)
return -EINVAL;
len = wlandev->wep_keylens[key_index];
memset(¶ms, 0, sizeof(params));
if (len == 13)
params.cipher = WLAN_CIPHER_SUITE_WEP104;
else if (len == 5)
params.cipher = WLAN_CIPHER_SUITE_WEP104;
else
return -ENOENT;
params.key_len = len;
params.key = wlandev->wep_keys[key_index];
params.seq_len = 0;
callback(cookie, ¶ms);
return 0;
}
static int prism2_del_key(struct wiphy *wiphy, struct net_device *dev,
int link_id, u8 key_index, bool pairwise,
const u8 *mac_addr)
{
struct wlandevice *wlandev = dev->ml_priv;
u32 did;
int err = 0;
int result = 0;
/* There is no direct way in the hardware (AFAIK) of removing
* a key, so we will cheat by setting the key to a bogus value
*/
if (key_index >= NUM_WEPKEYS)
return -EINVAL;
/* send key to driver */
did = didmib_dot11smt_wepdefaultkeystable_key(key_index + 1);
result = prism2_domibset_pstr32(wlandev, did, 13, "0000000000000");
if (result)
err = -EFAULT;
return err;
}
static int prism2_set_default_key(struct wiphy *wiphy, struct net_device *dev,
int link_id, u8 key_index, bool unicast,
bool multicast)
{
struct wlandevice *wlandev = dev->ml_priv;
return prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_WEPDEFAULTKEYID,
key_index);
}
static int prism2_get_station(struct wiphy *wiphy, struct net_device *dev,
const u8 *mac, struct station_info *sinfo)
{
struct wlandevice *wlandev = dev->ml_priv;
struct p80211msg_lnxreq_commsquality quality;
int result;
memset(sinfo, 0, sizeof(*sinfo));
if (!wlandev || (wlandev->msdstate != WLAN_MSD_RUNNING))
return -EOPNOTSUPP;
/* build request message */
quality.msgcode = DIDMSG_LNXREQ_COMMSQUALITY;
quality.dbm.data = P80211ENUM_truth_true;
quality.dbm.status = P80211ENUM_msgitem_status_data_ok;
/* send message to nsd */
if (!wlandev->mlmerequest)
return -EOPNOTSUPP;
result = wlandev->mlmerequest(wlandev, (struct p80211msg *)&quality);
if (result == 0) {
sinfo->txrate.legacy = quality.txrate.data;
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
sinfo->signal = quality.level.data;
sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL);
}
return result;
}
static int prism2_scan(struct wiphy *wiphy,
struct cfg80211_scan_request *request)
{
struct net_device *dev;
struct prism2_wiphy_private *priv = wiphy_priv(wiphy);
struct wlandevice *wlandev;
struct p80211msg_dot11req_scan msg1;
struct p80211msg_dot11req_scan_results *msg2;
struct cfg80211_bss *bss;
struct cfg80211_scan_info info = {};
int result;
int err = 0;
int numbss = 0;
int i = 0;
u8 ie_buf[46];
int ie_len;
if (!request)
return -EINVAL;
dev = request->wdev->netdev;
wlandev = dev->ml_priv;
if (priv->scan_request && priv->scan_request != request)
return -EBUSY;
if (wlandev->macmode == WLAN_MACMODE_ESS_AP) {
netdev_err(dev, "Can't scan in AP mode\n");
return -EOPNOTSUPP;
}
msg2 = kzalloc(sizeof(*msg2), GFP_KERNEL);
if (!msg2)
return -ENOMEM;
priv->scan_request = request;
memset(&msg1, 0x00, sizeof(msg1));
msg1.msgcode = DIDMSG_DOT11REQ_SCAN;
msg1.bsstype.data = P80211ENUM_bsstype_any;
memset(&msg1.bssid.data.data, 0xFF, sizeof(msg1.bssid.data.data));
msg1.bssid.data.len = 6;
if (request->n_ssids > 0) {
msg1.scantype.data = P80211ENUM_scantype_active;
msg1.ssid.data.len = request->ssids->ssid_len;
memcpy(msg1.ssid.data.data,
request->ssids->ssid, request->ssids->ssid_len);
} else {
msg1.scantype.data = 0;
}
msg1.probedelay.data = 0;
for (i = 0;
(i < request->n_channels) && i < ARRAY_SIZE(prism2_channels);
i++)
msg1.channellist.data.data[i] =
ieee80211_frequency_to_channel(request->channels[i]->center_freq);
msg1.channellist.data.len = request->n_channels;
msg1.maxchanneltime.data = 250;
msg1.minchanneltime.data = 200;
result = p80211req_dorequest(wlandev, (u8 *)&msg1);
if (result) {
err = prism2_result2err(msg1.resultcode.data);
goto exit;
}
/* Now retrieve scan results */
numbss = msg1.numbss.data;
for (i = 0; i < numbss; i++) {
int freq;
msg2->msgcode = DIDMSG_DOT11REQ_SCAN_RESULTS;
msg2->bssindex.data = i;
result = p80211req_dorequest(wlandev, (u8 *)&msg2);
if ((result != 0) ||
(msg2->resultcode.data != P80211ENUM_resultcode_success)) {
break;
}
ie_buf[0] = WLAN_EID_SSID;
ie_buf[1] = msg2->ssid.data.len;
ie_len = ie_buf[1] + 2;
memcpy(&ie_buf[2], &msg2->ssid.data.data, msg2->ssid.data.len);
freq = ieee80211_channel_to_frequency(msg2->dschannel.data,
NL80211_BAND_2GHZ);
bss = cfg80211_inform_bss(wiphy,
ieee80211_get_channel(wiphy, freq),
CFG80211_BSS_FTYPE_UNKNOWN,
(const u8 *)&msg2->bssid.data.data,
msg2->timestamp.data, msg2->capinfo.data,
msg2->beaconperiod.data,
ie_buf,
ie_len,
(msg2->signal.data - 65536) * 100, /* Conversion to signed type */
GFP_KERNEL);
if (!bss) {
err = -ENOMEM;
goto exit;
}
cfg80211_put_bss(wiphy, bss);
}
if (result)
err = prism2_result2err(msg2->resultcode.data);
exit:
info.aborted = !!(err);
cfg80211_scan_done(request, &info);
priv->scan_request = NULL;
kfree(msg2);
return err;
}
static int prism2_set_wiphy_params(struct wiphy *wiphy, u32 changed)
{
struct prism2_wiphy_private *priv = wiphy_priv(wiphy);
struct wlandevice *wlandev = priv->wlandev;
u32 data;
int result;
int err = 0;
if (changed & WIPHY_PARAM_RTS_THRESHOLD) {
if (wiphy->rts_threshold == -1)
data = 2347;
else
data = wiphy->rts_threshold;
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11MAC_OPERATIONTABLE_RTSTHRESHOLD,
data);
if (result) {
err = -EFAULT;
goto exit;
}
}
if (changed & WIPHY_PARAM_FRAG_THRESHOLD) {
if (wiphy->frag_threshold == -1)
data = 2346;
else
data = wiphy->frag_threshold;
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11MAC_OPERATIONTABLE_FRAGMENTATIONTHRESHOLD,
data);
if (result) {
err = -EFAULT;
goto exit;
}
}
exit:
return err;
}
static int prism2_connect(struct wiphy *wiphy, struct net_device *dev,
struct cfg80211_connect_params *sme)
{
struct wlandevice *wlandev = dev->ml_priv;
struct ieee80211_channel *channel = sme->channel;
struct p80211msg_lnxreq_autojoin msg_join;
u32 did;
int length = sme->ssid_len;
int chan = -1;
int is_wep = (sme->crypto.cipher_group == WLAN_CIPHER_SUITE_WEP40) ||
(sme->crypto.cipher_group == WLAN_CIPHER_SUITE_WEP104);
int result;
int err = 0;
/* Set the channel */
if (channel) {
chan = ieee80211_frequency_to_channel(channel->center_freq);
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11PHY_DSSSTABLE_CURRENTCHANNEL,
chan);
if (result)
goto exit;
}
/* Set the authorization */
if ((sme->auth_type == NL80211_AUTHTYPE_OPEN_SYSTEM) ||
((sme->auth_type == NL80211_AUTHTYPE_AUTOMATIC) && !is_wep))
msg_join.authtype.data = P80211ENUM_authalg_opensystem;
else if ((sme->auth_type == NL80211_AUTHTYPE_SHARED_KEY) ||
((sme->auth_type == NL80211_AUTHTYPE_AUTOMATIC) && is_wep))
msg_join.authtype.data = P80211ENUM_authalg_sharedkey;
else
netdev_warn(dev,
"Unhandled authorisation type for connect (%d)\n",
sme->auth_type);
/* Set the encryption - we only support wep */
if (is_wep) {
if (sme->key) {
if (sme->key_idx >= NUM_WEPKEYS)
return -EINVAL;
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_WEPDEFAULTKEYID,
sme->key_idx);
if (result)
goto exit;
/* send key to driver */
did = didmib_dot11smt_wepdefaultkeystable_key(sme->key_idx + 1);
result = prism2_domibset_pstr32(wlandev,
did, sme->key_len,
(u8 *)sme->key);
if (result)
goto exit;
}
/* Assume we should set privacy invoked and exclude unencrypted
* We could possible use sme->privacy here, but the assumption
* seems reasonable anyways
*/
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_PRIVACYINVOKED,
P80211ENUM_truth_true);
if (result)
goto exit;
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_EXCLUDEUNENCRYPTED,
P80211ENUM_truth_true);
if (result)
goto exit;
} else {
/* Assume we should unset privacy invoked
* and exclude unencrypted
*/
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_PRIVACYINVOKED,
P80211ENUM_truth_false);
if (result)
goto exit;
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11SMT_PRIVACYTABLE_EXCLUDEUNENCRYPTED,
P80211ENUM_truth_false);
if (result)
goto exit;
}
/* Now do the actual join. Note there is no way that I can
* see to request a specific bssid
*/
msg_join.msgcode = DIDMSG_LNXREQ_AUTOJOIN;
memcpy(msg_join.ssid.data.data, sme->ssid, length);
msg_join.ssid.data.len = length;
result = p80211req_dorequest(wlandev, (u8 *)&msg_join);
exit:
if (result)
err = -EFAULT;
return err;
}
static int prism2_disconnect(struct wiphy *wiphy, struct net_device *dev,
u16 reason_code)
{
struct wlandevice *wlandev = dev->ml_priv;
struct p80211msg_lnxreq_autojoin msg_join;
int result;
int err = 0;
/* Do a join, with a bogus ssid. Thats the only way I can think of */
msg_join.msgcode = DIDMSG_LNXREQ_AUTOJOIN;
memcpy(msg_join.ssid.data.data, "---", 3);
msg_join.ssid.data.len = 3;
result = p80211req_dorequest(wlandev, (u8 *)&msg_join);
if (result)
err = -EFAULT;
return err;
}
static int prism2_join_ibss(struct wiphy *wiphy, struct net_device *dev,
struct cfg80211_ibss_params *params)
{
return -EOPNOTSUPP;
}
static int prism2_leave_ibss(struct wiphy *wiphy, struct net_device *dev)
{
return -EOPNOTSUPP;
}
static int prism2_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
enum nl80211_tx_power_setting type, int mbm)
{
struct prism2_wiphy_private *priv = wiphy_priv(wiphy);
struct wlandevice *wlandev = priv->wlandev;
u32 data;
int result;
int err = 0;
if (type == NL80211_TX_POWER_AUTOMATIC)
data = 30;
else
data = MBM_TO_DBM(mbm);
result = prism2_domibset_uint32(wlandev,
DIDMIB_DOT11PHY_TXPOWERTABLE_CURRENTTXPOWERLEVEL,
data);
if (result) {
err = -EFAULT;
goto exit;
}
exit:
return err;
}
static int prism2_get_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
int *dbm)
{
struct prism2_wiphy_private *priv = wiphy_priv(wiphy);
struct wlandevice *wlandev = priv->wlandev;
struct p80211msg_dot11req_mibget msg;
struct p80211item_uint32 *mibitem;
int result;
int err = 0;
mibitem = (struct p80211item_uint32 *)&msg.mibattribute.data;
msg.msgcode = DIDMSG_DOT11REQ_MIBGET;
mibitem->did = DIDMIB_DOT11PHY_TXPOWERTABLE_CURRENTTXPOWERLEVEL;
result = p80211req_dorequest(wlandev, (u8 *)&msg);
if (result) {
err = -EFAULT;
goto exit;
}
*dbm = mibitem->data;
exit:
return err;
}
/* Interface callback functions, passing data back up to the cfg80211 layer */
void prism2_connect_result(struct wlandevice *wlandev, u8 failed)
{
u16 status = failed ?
WLAN_STATUS_UNSPECIFIED_FAILURE : WLAN_STATUS_SUCCESS;
cfg80211_connect_result(wlandev->netdev, wlandev->bssid,
NULL, 0, NULL, 0, status, GFP_KERNEL);
}
void prism2_disconnected(struct wlandevice *wlandev)
{
cfg80211_disconnected(wlandev->netdev, 0, NULL,
0, false, GFP_KERNEL);
}
void prism2_roamed(struct wlandevice *wlandev)
{
struct cfg80211_roam_info roam_info = {
.links[0].bssid = wlandev->bssid,
};
cfg80211_roamed(wlandev->netdev, &roam_info, GFP_KERNEL);
}
/* Structures for declaring wiphy interface */
static const struct cfg80211_ops prism2_usb_cfg_ops = {
.change_virtual_intf = prism2_change_virtual_intf,
.add_key = prism2_add_key,
.get_key = prism2_get_key,
.del_key = prism2_del_key,
.set_default_key = prism2_set_default_key,
.get_station = prism2_get_station,
.scan = prism2_scan,
.set_wiphy_params = prism2_set_wiphy_params,
.connect = prism2_connect,
.disconnect = prism2_disconnect,
.join_ibss = prism2_join_ibss,
.leave_ibss = prism2_leave_ibss,
.set_tx_power = prism2_set_tx_power,
.get_tx_power = prism2_get_tx_power,
};
/* Functions to create/free wiphy interface */
static struct wiphy *wlan_create_wiphy(struct device *dev,
struct wlandevice *wlandev)
{
struct wiphy *wiphy;
struct prism2_wiphy_private *priv;
wiphy = wiphy_new(&prism2_usb_cfg_ops, sizeof(*priv));
if (!wiphy)
return NULL;
priv = wiphy_priv(wiphy);
priv->wlandev = wlandev;
memcpy(priv->channels, prism2_channels, sizeof(prism2_channels));
memcpy(priv->rates, prism2_rates, sizeof(prism2_rates));
priv->band.channels = priv->channels;
priv->band.n_channels = ARRAY_SIZE(prism2_channels);
priv->band.bitrates = priv->rates;
priv->band.n_bitrates = ARRAY_SIZE(prism2_rates);
priv->band.band = NL80211_BAND_2GHZ;
priv->band.ht_cap.ht_supported = false;
wiphy->bands[NL80211_BAND_2GHZ] = &priv->band;
set_wiphy_dev(wiphy, dev);
wiphy->privid = prism2_wiphy_privid;
wiphy->max_scan_ssids = 1;
wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION)
| BIT(NL80211_IFTYPE_ADHOC);
wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
wiphy->n_cipher_suites = PRISM2_NUM_CIPHER_SUITES;
wiphy->cipher_suites = prism2_cipher_suites;
if (wiphy_register(wiphy) < 0) {
wiphy_free(wiphy);
return NULL;
}
return wiphy;
}
static void wlan_free_wiphy(struct wiphy *wiphy)
{
wiphy_unregister(wiphy);
wiphy_free(wiphy);
}
| linux-master | drivers/staging/wlan-ng/cfg80211.c |
// SPDX-License-Identifier: (GPL-2.0 OR MPL-1.1)
/*
*
* Implements the station functionality for prism2
*
* Copyright (C) 1999 AbsoluteValue Systems, Inc. All Rights Reserved.
* --------------------------------------------------------------------
*
* linux-wlan
*
* --------------------------------------------------------------------
*
* Inquiries regarding the linux-wlan Open Source project can be
* made directly to:
*
* AbsoluteValue Systems Inc.
* [email protected]
* http://www.linux-wlan.com
*
* --------------------------------------------------------------------
*
* Portions of the development of this software were funded by
* Intersil Corporation as part of PRISM(R) chipset product development.
*
* --------------------------------------------------------------------
*
* This file implements the module and linux pcmcia routines for the
* prism2 driver.
*
* --------------------------------------------------------------------
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/wireless.h>
#include <linux/netdevice.h>
#include <linux/workqueue.h>
#include <linux/byteorder/generic.h>
#include <linux/etherdevice.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/bitops.h>
#include "p80211types.h"
#include "p80211hdr.h"
#include "p80211mgmt.h"
#include "p80211conv.h"
#include "p80211msg.h"
#include "p80211netdev.h"
#include "p80211req.h"
#include "p80211metadef.h"
#include "p80211metastruct.h"
#include "hfa384x.h"
#include "prism2mgmt.h"
static char *dev_info = "prism2_usb";
static struct wlandevice *create_wlan(void);
int prism2_reset_holdtime = 30; /* Reset hold time in ms */
int prism2_reset_settletime = 100; /* Reset settle time in ms */
static int prism2_doreset; /* Do a reset at init? */
module_param(prism2_doreset, int, 0644);
MODULE_PARM_DESC(prism2_doreset, "Issue a reset on initialization");
module_param(prism2_reset_holdtime, int, 0644);
MODULE_PARM_DESC(prism2_reset_holdtime, "reset hold time in ms");
module_param(prism2_reset_settletime, int, 0644);
MODULE_PARM_DESC(prism2_reset_settletime, "reset settle time in ms");
MODULE_LICENSE("Dual MPL/GPL");
static int prism2sta_open(struct wlandevice *wlandev);
static int prism2sta_close(struct wlandevice *wlandev);
static void prism2sta_reset(struct wlandevice *wlandev);
static int prism2sta_txframe(struct wlandevice *wlandev, struct sk_buff *skb,
struct p80211_hdr *p80211_hdr,
struct p80211_metawep *p80211_wep);
static int prism2sta_mlmerequest(struct wlandevice *wlandev,
struct p80211msg *msg);
static int prism2sta_getcardinfo(struct wlandevice *wlandev);
static int prism2sta_globalsetup(struct wlandevice *wlandev);
static int prism2sta_setmulticast(struct wlandevice *wlandev,
struct net_device *dev);
static void prism2sta_inf_handover(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_tallies(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_hostscanresults(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_scanresults(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_chinforesults(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_linkstatus(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_assocstatus(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_authreq(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_authreq_defer(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
static void prism2sta_inf_psusercnt(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf);
/*
* prism2sta_open
*
* WLAN device open method. Called from p80211netdev when kernel
* device open (start) method is called in response to the
* SIOCSIIFFLAGS ioctl changing the flags bit IFF_UP
* from clear to set.
*
* Arguments:
* wlandev wlan device structure
*
* Returns:
* 0 success
* >0 f/w reported error
* <0 driver reported error
*
* Side effects:
*
* Call context:
* process thread
*/
static int prism2sta_open(struct wlandevice *wlandev)
{
/* We don't currently have to do anything else.
* The setup of the MAC should be subsequently completed via
* the mlme commands.
* Higher layers know we're ready from dev->start==1 and
* dev->tbusy==0. Our rx path knows to pass up received/
* frames because of dev->flags&IFF_UP is true.
*/
return 0;
}
/*
* prism2sta_close
*
* WLAN device close method. Called from p80211netdev when kernel
* device close method is called in response to the
* SIOCSIIFFLAGS ioctl changing the flags bit IFF_UP
* from set to clear.
*
* Arguments:
* wlandev wlan device structure
*
* Returns:
* 0 success
* >0 f/w reported error
* <0 driver reported error
*
* Side effects:
*
* Call context:
* process thread
*/
static int prism2sta_close(struct wlandevice *wlandev)
{
/* We don't currently have to do anything else.
* Higher layers know we're not ready from dev->start==0 and
* dev->tbusy==1. Our rx path knows to not pass up received
* frames because of dev->flags&IFF_UP is false.
*/
return 0;
}
/*
* prism2sta_reset
*
* Currently not implemented.
*
* Arguments:
* wlandev wlan device structure
* none
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* process thread
*/
static void prism2sta_reset(struct wlandevice *wlandev)
{
}
/*
* prism2sta_txframe
*
* Takes a frame from p80211 and queues it for transmission.
*
* Arguments:
* wlandev wlan device structure
* pb packet buffer struct. Contains an 802.11
* data frame.
* p80211_hdr points to the 802.11 header for the packet.
* Returns:
* 0 Success and more buffs available
* 1 Success but no more buffs
* 2 Allocation failure
* 4 Buffer full or queue busy
*
* Side effects:
*
* Call context:
* process thread
*/
static int prism2sta_txframe(struct wlandevice *wlandev, struct sk_buff *skb,
struct p80211_hdr *p80211_hdr,
struct p80211_metawep *p80211_wep)
{
struct hfa384x *hw = wlandev->priv;
/* If necessary, set the 802.11 WEP bit */
if ((wlandev->hostwep & (HOSTWEP_PRIVACYINVOKED | HOSTWEP_ENCRYPT)) ==
HOSTWEP_PRIVACYINVOKED) {
p80211_hdr->frame_control |= cpu_to_le16(WLAN_SET_FC_ISWEP(1));
}
return hfa384x_drvr_txframe(hw, skb, p80211_hdr, p80211_wep);
}
/*
* prism2sta_mlmerequest
*
* wlan command message handler. All we do here is pass the message
* over to the prism2sta_mgmt_handler.
*
* Arguments:
* wlandev wlan device structure
* msg wlan command message
* Returns:
* 0 success
* <0 successful acceptance of message, but we're
* waiting for an async process to finish before
* we're done with the msg. When the asynch
* process is done, we'll call the p80211
* function p80211req_confirm() .
* >0 An error occurred while we were handling
* the message.
*
* Side effects:
*
* Call context:
* process thread
*/
static int prism2sta_mlmerequest(struct wlandevice *wlandev,
struct p80211msg *msg)
{
struct hfa384x *hw = wlandev->priv;
int result = 0;
switch (msg->msgcode) {
case DIDMSG_DOT11REQ_MIBGET:
pr_debug("Received mibget request\n");
result = prism2mgmt_mibset_mibget(wlandev, msg);
break;
case DIDMSG_DOT11REQ_MIBSET:
pr_debug("Received mibset request\n");
result = prism2mgmt_mibset_mibget(wlandev, msg);
break;
case DIDMSG_DOT11REQ_SCAN:
pr_debug("Received scan request\n");
result = prism2mgmt_scan(wlandev, msg);
break;
case DIDMSG_DOT11REQ_SCAN_RESULTS:
pr_debug("Received scan_results request\n");
result = prism2mgmt_scan_results(wlandev, msg);
break;
case DIDMSG_DOT11REQ_START:
pr_debug("Received mlme start request\n");
result = prism2mgmt_start(wlandev, msg);
break;
/*
* Prism2 specific messages
*/
case DIDMSG_P2REQ_READPDA:
pr_debug("Received mlme readpda request\n");
result = prism2mgmt_readpda(wlandev, msg);
break;
case DIDMSG_P2REQ_RAMDL_STATE:
pr_debug("Received mlme ramdl_state request\n");
result = prism2mgmt_ramdl_state(wlandev, msg);
break;
case DIDMSG_P2REQ_RAMDL_WRITE:
pr_debug("Received mlme ramdl_write request\n");
result = prism2mgmt_ramdl_write(wlandev, msg);
break;
case DIDMSG_P2REQ_FLASHDL_STATE:
pr_debug("Received mlme flashdl_state request\n");
result = prism2mgmt_flashdl_state(wlandev, msg);
break;
case DIDMSG_P2REQ_FLASHDL_WRITE:
pr_debug("Received mlme flashdl_write request\n");
result = prism2mgmt_flashdl_write(wlandev, msg);
break;
/*
* Linux specific messages
*/
case DIDMSG_LNXREQ_HOSTWEP:
break; /* ignore me. */
case DIDMSG_LNXREQ_IFSTATE: {
struct p80211msg_lnxreq_ifstate *ifstatemsg;
pr_debug("Received mlme ifstate request\n");
ifstatemsg = (struct p80211msg_lnxreq_ifstate *)msg;
result = prism2sta_ifstate(wlandev,
ifstatemsg->ifstate.data);
ifstatemsg->resultcode.status =
P80211ENUM_msgitem_status_data_ok;
ifstatemsg->resultcode.data = result;
result = 0;
break;
}
case DIDMSG_LNXREQ_WLANSNIFF:
pr_debug("Received mlme wlansniff request\n");
result = prism2mgmt_wlansniff(wlandev, msg);
break;
case DIDMSG_LNXREQ_AUTOJOIN:
pr_debug("Received mlme autojoin request\n");
result = prism2mgmt_autojoin(wlandev, msg);
break;
case DIDMSG_LNXREQ_COMMSQUALITY: {
struct p80211msg_lnxreq_commsquality *qualmsg;
pr_debug("Received commsquality request\n");
qualmsg = (struct p80211msg_lnxreq_commsquality *)msg;
qualmsg->link.status = P80211ENUM_msgitem_status_data_ok;
qualmsg->level.status = P80211ENUM_msgitem_status_data_ok;
qualmsg->noise.status = P80211ENUM_msgitem_status_data_ok;
qualmsg->link.data = le16_to_cpu(hw->qual.cq_curr_bss);
qualmsg->level.data = le16_to_cpu(hw->qual.asl_curr_bss);
qualmsg->noise.data = le16_to_cpu(hw->qual.anl_curr_fc);
qualmsg->txrate.data = hw->txrate;
break;
}
default:
netdev_warn(wlandev->netdev,
"Unknown mgmt request message 0x%08x",
msg->msgcode);
break;
}
return result;
}
/*
* prism2sta_ifstate
*
* Interface state. This is the primary WLAN interface enable/disable
* handler. Following the driver/load/deviceprobe sequence, this
* function must be called with a state of "enable" before any other
* commands will be accepted.
*
* Arguments:
* wlandev wlan device structure
* msgp ptr to msg buffer
*
* Returns:
* A p80211 message resultcode value.
*
* Side effects:
*
* Call context:
* process thread (usually)
* interrupt
*/
u32 prism2sta_ifstate(struct wlandevice *wlandev, u32 ifstate)
{
struct hfa384x *hw = wlandev->priv;
u32 result;
result = P80211ENUM_resultcode_implementation_failure;
pr_debug("Current MSD state(%d), requesting(%d)\n",
wlandev->msdstate, ifstate);
switch (ifstate) {
case P80211ENUM_ifstate_fwload:
switch (wlandev->msdstate) {
case WLAN_MSD_HWPRESENT:
wlandev->msdstate = WLAN_MSD_FWLOAD_PENDING;
/*
* Initialize the device+driver sufficiently
* for firmware loading.
*/
result = hfa384x_drvr_start(hw);
if (result) {
netdev_err(wlandev->netdev,
"hfa384x_drvr_start() failed,result=%d\n",
(int)result);
result =
P80211ENUM_resultcode_implementation_failure;
wlandev->msdstate = WLAN_MSD_HWPRESENT;
break;
}
wlandev->msdstate = WLAN_MSD_FWLOAD;
result = P80211ENUM_resultcode_success;
break;
case WLAN_MSD_FWLOAD:
hfa384x_cmd_initialize(hw);
result = P80211ENUM_resultcode_success;
break;
case WLAN_MSD_RUNNING:
netdev_warn(wlandev->netdev,
"Cannot enter fwload state from enable state, you must disable first.\n");
result = P80211ENUM_resultcode_invalid_parameters;
break;
case WLAN_MSD_HWFAIL:
default:
/* probe() had a problem or the msdstate contains
* an unrecognized value, there's nothing we can do.
*/
result = P80211ENUM_resultcode_implementation_failure;
break;
}
break;
case P80211ENUM_ifstate_enable:
switch (wlandev->msdstate) {
case WLAN_MSD_HWPRESENT:
case WLAN_MSD_FWLOAD:
wlandev->msdstate = WLAN_MSD_RUNNING_PENDING;
/* Initialize the device+driver for full
* operation. Note that this might me an FWLOAD
* to RUNNING transition so we must not do a chip
* or board level reset. Note that on failure,
* the MSD state is set to HWPRESENT because we
* can't make any assumptions about the state
* of the hardware or a previous firmware load.
*/
result = hfa384x_drvr_start(hw);
if (result) {
netdev_err(wlandev->netdev,
"hfa384x_drvr_start() failed,result=%d\n",
(int)result);
result =
P80211ENUM_resultcode_implementation_failure;
wlandev->msdstate = WLAN_MSD_HWPRESENT;
break;
}
result = prism2sta_getcardinfo(wlandev);
if (result) {
netdev_err(wlandev->netdev,
"prism2sta_getcardinfo() failed,result=%d\n",
(int)result);
result =
P80211ENUM_resultcode_implementation_failure;
hfa384x_drvr_stop(hw);
wlandev->msdstate = WLAN_MSD_HWPRESENT;
break;
}
result = prism2sta_globalsetup(wlandev);
if (result) {
netdev_err(wlandev->netdev,
"prism2sta_globalsetup() failed,result=%d\n",
(int)result);
result =
P80211ENUM_resultcode_implementation_failure;
hfa384x_drvr_stop(hw);
wlandev->msdstate = WLAN_MSD_HWPRESENT;
break;
}
wlandev->msdstate = WLAN_MSD_RUNNING;
hw->join_ap = 0;
hw->join_retries = 60;
result = P80211ENUM_resultcode_success;
break;
case WLAN_MSD_RUNNING:
/* Do nothing, we're already in this state. */
result = P80211ENUM_resultcode_success;
break;
case WLAN_MSD_HWFAIL:
default:
/* probe() had a problem or the msdstate contains
* an unrecognized value, there's nothing we can do.
*/
result = P80211ENUM_resultcode_implementation_failure;
break;
}
break;
case P80211ENUM_ifstate_disable:
switch (wlandev->msdstate) {
case WLAN_MSD_HWPRESENT:
/* Do nothing, we're already in this state. */
result = P80211ENUM_resultcode_success;
break;
case WLAN_MSD_FWLOAD:
case WLAN_MSD_RUNNING:
wlandev->msdstate = WLAN_MSD_HWPRESENT_PENDING;
/*
* TODO: Shut down the MAC completely. Here a chip
* or board level reset is probably called for.
* After a "disable" _all_ results are lost, even
* those from a fwload.
*/
if (!wlandev->hwremoved)
netif_carrier_off(wlandev->netdev);
hfa384x_drvr_stop(hw);
wlandev->macmode = WLAN_MACMODE_NONE;
wlandev->msdstate = WLAN_MSD_HWPRESENT;
result = P80211ENUM_resultcode_success;
break;
case WLAN_MSD_HWFAIL:
default:
/* probe() had a problem or the msdstate contains
* an unrecognized value, there's nothing we can do.
*/
result = P80211ENUM_resultcode_implementation_failure;
break;
}
break;
default:
result = P80211ENUM_resultcode_invalid_parameters;
break;
}
return result;
}
/*
* prism2sta_getcardinfo
*
* Collect the NICID, firmware version and any other identifiers
* we'd like to have in host-side data structures.
*
* Arguments:
* wlandev wlan device structure
*
* Returns:
* 0 success
* >0 f/w reported error
* <0 driver reported error
*
* Side effects:
*
* Call context:
* Either.
*/
static int prism2sta_getcardinfo(struct wlandevice *wlandev)
{
int result = 0;
struct hfa384x *hw = wlandev->priv;
u16 temp;
u8 snum[HFA384x_RID_NICSERIALNUMBER_LEN];
u8 addr[ETH_ALEN];
/* Collect version and compatibility info */
/* Some are critical, some are not */
/* NIC identity */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_NICIDENTITY,
&hw->ident_nic,
sizeof(struct hfa384x_compident));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve NICIDENTITY\n");
goto failed;
}
/* get all the nic id fields in host byte order */
le16_to_cpus(&hw->ident_nic.id);
le16_to_cpus(&hw->ident_nic.variant);
le16_to_cpus(&hw->ident_nic.major);
le16_to_cpus(&hw->ident_nic.minor);
netdev_info(wlandev->netdev, "ident: nic h/w: id=0x%02x %d.%d.%d\n",
hw->ident_nic.id, hw->ident_nic.major,
hw->ident_nic.minor, hw->ident_nic.variant);
/* Primary f/w identity */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_PRIIDENTITY,
&hw->ident_pri_fw,
sizeof(struct hfa384x_compident));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve PRIIDENTITY\n");
goto failed;
}
/* get all the private fw id fields in host byte order */
le16_to_cpus(&hw->ident_pri_fw.id);
le16_to_cpus(&hw->ident_pri_fw.variant);
le16_to_cpus(&hw->ident_pri_fw.major);
le16_to_cpus(&hw->ident_pri_fw.minor);
netdev_info(wlandev->netdev, "ident: pri f/w: id=0x%02x %d.%d.%d\n",
hw->ident_pri_fw.id, hw->ident_pri_fw.major,
hw->ident_pri_fw.minor, hw->ident_pri_fw.variant);
/* Station (Secondary?) f/w identity */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STAIDENTITY,
&hw->ident_sta_fw,
sizeof(struct hfa384x_compident));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve STAIDENTITY\n");
goto failed;
}
if (hw->ident_nic.id < 0x8000) {
netdev_err(wlandev->netdev,
"FATAL: Card is not an Intersil Prism2/2.5/3\n");
result = -1;
goto failed;
}
/* get all the station fw id fields in host byte order */
le16_to_cpus(&hw->ident_sta_fw.id);
le16_to_cpus(&hw->ident_sta_fw.variant);
le16_to_cpus(&hw->ident_sta_fw.major);
le16_to_cpus(&hw->ident_sta_fw.minor);
/* strip out the 'special' variant bits */
hw->mm_mods = hw->ident_sta_fw.variant & GENMASK(15, 14);
hw->ident_sta_fw.variant &= ~((u16)GENMASK(15, 14));
if (hw->ident_sta_fw.id == 0x1f) {
netdev_info(wlandev->netdev,
"ident: sta f/w: id=0x%02x %d.%d.%d\n",
hw->ident_sta_fw.id, hw->ident_sta_fw.major,
hw->ident_sta_fw.minor, hw->ident_sta_fw.variant);
} else {
netdev_info(wlandev->netdev,
"ident: ap f/w: id=0x%02x %d.%d.%d\n",
hw->ident_sta_fw.id, hw->ident_sta_fw.major,
hw->ident_sta_fw.minor, hw->ident_sta_fw.variant);
netdev_err(wlandev->netdev, "Unsupported Tertiary AP firmware loaded!\n");
goto failed;
}
/* Compatibility range, Modem supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_MFISUPRANGE,
&hw->cap_sup_mfi,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve MFISUPRANGE\n");
goto failed;
}
/* get all the Compatibility range, modem interface supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_sup_mfi.role);
le16_to_cpus(&hw->cap_sup_mfi.id);
le16_to_cpus(&hw->cap_sup_mfi.variant);
le16_to_cpus(&hw->cap_sup_mfi.bottom);
le16_to_cpus(&hw->cap_sup_mfi.top);
netdev_info(wlandev->netdev,
"MFI:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_sup_mfi.role, hw->cap_sup_mfi.id,
hw->cap_sup_mfi.variant, hw->cap_sup_mfi.bottom,
hw->cap_sup_mfi.top);
/* Compatibility range, Controller supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_CFISUPRANGE,
&hw->cap_sup_cfi,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve CFISUPRANGE\n");
goto failed;
}
/* get all the Compatibility range, controller interface supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_sup_cfi.role);
le16_to_cpus(&hw->cap_sup_cfi.id);
le16_to_cpus(&hw->cap_sup_cfi.variant);
le16_to_cpus(&hw->cap_sup_cfi.bottom);
le16_to_cpus(&hw->cap_sup_cfi.top);
netdev_info(wlandev->netdev,
"CFI:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_sup_cfi.role, hw->cap_sup_cfi.id,
hw->cap_sup_cfi.variant, hw->cap_sup_cfi.bottom,
hw->cap_sup_cfi.top);
/* Compatibility range, Primary f/w supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_PRISUPRANGE,
&hw->cap_sup_pri,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve PRISUPRANGE\n");
goto failed;
}
/* get all the Compatibility range, primary firmware supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_sup_pri.role);
le16_to_cpus(&hw->cap_sup_pri.id);
le16_to_cpus(&hw->cap_sup_pri.variant);
le16_to_cpus(&hw->cap_sup_pri.bottom);
le16_to_cpus(&hw->cap_sup_pri.top);
netdev_info(wlandev->netdev,
"PRI:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_sup_pri.role, hw->cap_sup_pri.id,
hw->cap_sup_pri.variant, hw->cap_sup_pri.bottom,
hw->cap_sup_pri.top);
/* Compatibility range, Station f/w supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STASUPRANGE,
&hw->cap_sup_sta,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve STASUPRANGE\n");
goto failed;
}
/* get all the Compatibility range, station firmware supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_sup_sta.role);
le16_to_cpus(&hw->cap_sup_sta.id);
le16_to_cpus(&hw->cap_sup_sta.variant);
le16_to_cpus(&hw->cap_sup_sta.bottom);
le16_to_cpus(&hw->cap_sup_sta.top);
if (hw->cap_sup_sta.id == 0x04) {
netdev_info(wlandev->netdev,
"STA:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_sup_sta.role, hw->cap_sup_sta.id,
hw->cap_sup_sta.variant, hw->cap_sup_sta.bottom,
hw->cap_sup_sta.top);
} else {
netdev_info(wlandev->netdev,
"AP:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_sup_sta.role, hw->cap_sup_sta.id,
hw->cap_sup_sta.variant, hw->cap_sup_sta.bottom,
hw->cap_sup_sta.top);
}
/* Compatibility range, primary f/w actor, CFI supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_PRI_CFIACTRANGES,
&hw->cap_act_pri_cfi,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve PRI_CFIACTRANGES\n");
goto failed;
}
/* get all the Compatibility range, primary f/w actor, CFI supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_act_pri_cfi.role);
le16_to_cpus(&hw->cap_act_pri_cfi.id);
le16_to_cpus(&hw->cap_act_pri_cfi.variant);
le16_to_cpus(&hw->cap_act_pri_cfi.bottom);
le16_to_cpus(&hw->cap_act_pri_cfi.top);
netdev_info(wlandev->netdev,
"PRI-CFI:ACT:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_act_pri_cfi.role, hw->cap_act_pri_cfi.id,
hw->cap_act_pri_cfi.variant, hw->cap_act_pri_cfi.bottom,
hw->cap_act_pri_cfi.top);
/* Compatibility range, sta f/w actor, CFI supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STA_CFIACTRANGES,
&hw->cap_act_sta_cfi,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve STA_CFIACTRANGES\n");
goto failed;
}
/* get all the Compatibility range, station f/w actor, CFI supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_act_sta_cfi.role);
le16_to_cpus(&hw->cap_act_sta_cfi.id);
le16_to_cpus(&hw->cap_act_sta_cfi.variant);
le16_to_cpus(&hw->cap_act_sta_cfi.bottom);
le16_to_cpus(&hw->cap_act_sta_cfi.top);
netdev_info(wlandev->netdev,
"STA-CFI:ACT:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_act_sta_cfi.role, hw->cap_act_sta_cfi.id,
hw->cap_act_sta_cfi.variant, hw->cap_act_sta_cfi.bottom,
hw->cap_act_sta_cfi.top);
/* Compatibility range, sta f/w actor, MFI supplier */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_STA_MFIACTRANGES,
&hw->cap_act_sta_mfi,
sizeof(struct hfa384x_caplevel));
if (result) {
netdev_err(wlandev->netdev, "Failed to retrieve STA_MFIACTRANGES\n");
goto failed;
}
/* get all the Compatibility range, station f/w actor, MFI supplier
* fields in byte order
*/
le16_to_cpus(&hw->cap_act_sta_mfi.role);
le16_to_cpus(&hw->cap_act_sta_mfi.id);
le16_to_cpus(&hw->cap_act_sta_mfi.variant);
le16_to_cpus(&hw->cap_act_sta_mfi.bottom);
le16_to_cpus(&hw->cap_act_sta_mfi.top);
netdev_info(wlandev->netdev,
"STA-MFI:ACT:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n",
hw->cap_act_sta_mfi.role, hw->cap_act_sta_mfi.id,
hw->cap_act_sta_mfi.variant, hw->cap_act_sta_mfi.bottom,
hw->cap_act_sta_mfi.top);
/* Serial Number */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_NICSERIALNUMBER,
snum, HFA384x_RID_NICSERIALNUMBER_LEN);
if (!result) {
netdev_info(wlandev->netdev, "Prism2 card SN: %*pE\n",
HFA384x_RID_NICSERIALNUMBER_LEN, snum);
} else {
netdev_err(wlandev->netdev, "Failed to retrieve Prism2 Card SN\n");
goto failed;
}
/* Collect the MAC address */
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_CNFOWNMACADDR,
addr, ETH_ALEN);
if (result != 0) {
netdev_err(wlandev->netdev, "Failed to retrieve mac address\n");
goto failed;
}
eth_hw_addr_set(wlandev->netdev, addr);
/* short preamble is always implemented */
wlandev->nsdcaps |= P80211_NSDCAP_SHORT_PREAMBLE;
/* find out if hardware wep is implemented */
hfa384x_drvr_getconfig16(hw, HFA384x_RID_PRIVACYOPTIMP, &temp);
if (temp)
wlandev->nsdcaps |= P80211_NSDCAP_HARDWAREWEP;
/* get the dBm Scaling constant */
hfa384x_drvr_getconfig16(hw, HFA384x_RID_CNFDBMADJUST, &temp);
hw->dbmadjust = temp;
/* Only enable scan by default on newer firmware */
if (HFA384x_FIRMWARE_VERSION(hw->ident_sta_fw.major,
hw->ident_sta_fw.minor,
hw->ident_sta_fw.variant) <
HFA384x_FIRMWARE_VERSION(1, 5, 5)) {
wlandev->nsdcaps |= P80211_NSDCAP_NOSCAN;
}
/* TODO: Set any internally managed config items */
goto done;
failed:
netdev_err(wlandev->netdev, "Failed, result=%d\n", result);
done:
return result;
}
/*
* prism2sta_globalsetup
*
* Set any global RIDs that we want to set at device activation.
*
* Arguments:
* wlandev wlan device structure
*
* Returns:
* 0 success
* >0 f/w reported error
* <0 driver reported error
*
* Side effects:
*
* Call context:
* process thread
*/
static int prism2sta_globalsetup(struct wlandevice *wlandev)
{
struct hfa384x *hw = wlandev->priv;
/* Set the maximum frame size */
return hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFMAXDATALEN,
WLAN_DATA_MAXLEN);
}
static int prism2sta_setmulticast(struct wlandevice *wlandev,
struct net_device *dev)
{
int result = 0;
struct hfa384x *hw = wlandev->priv;
u16 promisc;
/* If we're not ready, what's the point? */
if (hw->state != HFA384x_STATE_RUNNING)
goto exit;
if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
promisc = P80211ENUM_truth_true;
else
promisc = P80211ENUM_truth_false;
result =
hfa384x_drvr_setconfig16_async(hw, HFA384x_RID_PROMISCMODE,
promisc);
exit:
return result;
}
/*
* prism2sta_inf_handover
*
* Handles the receipt of a Handover info frame. Should only be present
* in APs only.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_handover(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
pr_debug("received infoframe:HANDOVER (unhandled)\n");
}
/*
* prism2sta_inf_tallies
*
* Handles the receipt of a CommTallies info frame.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_tallies(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
__le16 *src16;
u32 *dst;
__le32 *src32;
int i;
int cnt;
/*
* Determine if these are 16-bit or 32-bit tallies, based on the
* record length of the info record.
*/
cnt = sizeof(struct hfa384x_comm_tallies_32) / sizeof(u32);
if (inf->framelen > 22) {
dst = (u32 *)&hw->tallies;
src32 = (__le32 *)&inf->info.commtallies32;
for (i = 0; i < cnt; i++, dst++, src32++)
*dst += le32_to_cpu(*src32);
} else {
dst = (u32 *)&hw->tallies;
src16 = (__le16 *)&inf->info.commtallies16;
for (i = 0; i < cnt; i++, dst++, src16++)
*dst += le16_to_cpu(*src16);
}
}
/*
* prism2sta_inf_scanresults
*
* Handles the receipt of a Scan Results info frame.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_scanresults(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
int nbss;
struct hfa384x_scan_result *sr = &inf->info.scanresult;
int i;
struct hfa384x_join_request_data joinreq;
int result;
/* Get the number of results, first in bytes, then in results */
nbss = (inf->framelen * sizeof(u16)) -
sizeof(inf->infotype) - sizeof(inf->info.scanresult.scanreason);
nbss /= sizeof(struct hfa384x_scan_result_sub);
/* Print em */
pr_debug("rx scanresults, reason=%d, nbss=%d:\n",
inf->info.scanresult.scanreason, nbss);
for (i = 0; i < nbss; i++) {
pr_debug("chid=%d anl=%d sl=%d bcnint=%d\n",
sr->result[i].chid,
sr->result[i].anl,
sr->result[i].sl, sr->result[i].bcnint);
pr_debug(" capinfo=0x%04x proberesp_rate=%d\n",
sr->result[i].capinfo, sr->result[i].proberesp_rate);
}
/* issue a join request */
joinreq.channel = sr->result[0].chid;
memcpy(joinreq.bssid, sr->result[0].bssid, WLAN_BSSID_LEN);
result = hfa384x_drvr_setconfig(hw,
HFA384x_RID_JOINREQUEST,
&joinreq, HFA384x_RID_JOINREQUEST_LEN);
if (result) {
netdev_err(wlandev->netdev, "setconfig(joinreq) failed, result=%d\n",
result);
}
}
/*
* prism2sta_inf_hostscanresults
*
* Handles the receipt of a Scan Results info frame.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_hostscanresults(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
int nbss;
nbss = (inf->framelen - 3) / 32;
pr_debug("Received %d hostscan results\n", nbss);
if (nbss > 32)
nbss = 32;
kfree(hw->scanresults);
hw->scanresults = kmemdup(inf, sizeof(*inf), GFP_ATOMIC);
if (nbss == 0)
nbss = -1;
/* Notify/wake the sleeping caller. */
hw->scanflag = nbss;
wake_up_interruptible(&hw->cmdq);
};
/*
* prism2sta_inf_chinforesults
*
* Handles the receipt of a Channel Info Results info frame.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_chinforesults(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
unsigned int i, n;
hw->channel_info.results.scanchannels =
inf->info.chinforesult.scanchannels;
for (i = 0, n = 0; i < HFA384x_CHINFORESULT_MAX; i++) {
struct hfa384x_ch_info_result_sub *result;
struct hfa384x_ch_info_result_sub *chinforesult;
int chan;
if (!(hw->channel_info.results.scanchannels & (1 << i)))
continue;
result = &inf->info.chinforesult.result[n];
chan = result->chid - 1;
if (chan < 0 || chan >= HFA384x_CHINFORESULT_MAX)
continue;
chinforesult = &hw->channel_info.results.result[chan];
chinforesult->chid = chan;
chinforesult->anl = result->anl;
chinforesult->pnl = result->pnl;
chinforesult->active = result->active;
pr_debug("chinfo: channel %d, %s level (avg/peak)=%d/%d dB, pcf %d\n",
chan + 1,
(chinforesult->active & HFA384x_CHINFORESULT_BSSACTIVE)
? "signal" : "noise",
chinforesult->anl, chinforesult->pnl,
(chinforesult->active & HFA384x_CHINFORESULT_PCFACTIVE)
? 1 : 0);
n++;
}
atomic_set(&hw->channel_info.done, 2);
hw->channel_info.count = n;
}
void prism2sta_processing_defer(struct work_struct *data)
{
struct hfa384x *hw = container_of(data, struct hfa384x, link_bh);
struct wlandevice *wlandev = hw->wlandev;
struct hfa384x_bytestr32 ssid;
int result;
/* First let's process the auth frames */
{
struct sk_buff *skb;
struct hfa384x_inf_frame *inf;
while ((skb = skb_dequeue(&hw->authq))) {
inf = (struct hfa384x_inf_frame *)skb->data;
prism2sta_inf_authreq_defer(wlandev, inf);
}
}
/* Now let's handle the linkstatus stuff */
if (hw->link_status == hw->link_status_new)
return;
hw->link_status = hw->link_status_new;
switch (hw->link_status) {
case HFA384x_LINK_NOTCONNECTED:
/* I'm currently assuming that this is the initial link
* state. It should only be possible immediately
* following an Enable command.
* Response:
* Block Transmits, Ignore receives of data frames
*/
netif_carrier_off(wlandev->netdev);
netdev_info(wlandev->netdev, "linkstatus=NOTCONNECTED (unhandled)\n");
break;
case HFA384x_LINK_CONNECTED:
/* This one indicates a successful scan/join/auth/assoc.
* When we have the full MLME complement, this event will
* signify successful completion of both mlme_authenticate
* and mlme_associate. State management will get a little
* ugly here.
* Response:
* Indicate authentication and/or association
* Enable Transmits, Receives and pass up data frames
*/
netif_carrier_on(wlandev->netdev);
/* If we are joining a specific AP, set our
* state and reset retries
*/
if (hw->join_ap == 1)
hw->join_ap = 2;
hw->join_retries = 60;
/* Don't call this in monitor mode */
if (wlandev->netdev->type == ARPHRD_ETHER) {
u16 portstatus;
netdev_info(wlandev->netdev, "linkstatus=CONNECTED\n");
/* For non-usb devices, we can use the sync versions */
/* Collect the BSSID, and set state to allow tx */
result = hfa384x_drvr_getconfig(hw,
HFA384x_RID_CURRENTBSSID,
wlandev->bssid,
WLAN_BSSID_LEN);
if (result) {
pr_debug
("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_CURRENTBSSID, result);
return;
}
result = hfa384x_drvr_getconfig(hw,
HFA384x_RID_CURRENTSSID,
&ssid, sizeof(ssid));
if (result) {
pr_debug
("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_CURRENTSSID, result);
return;
}
prism2mgmt_bytestr2pstr((struct hfa384x_bytestr *)&ssid,
(struct p80211pstrd *)&wlandev->ssid);
/* Collect the port status */
result = hfa384x_drvr_getconfig16(hw,
HFA384x_RID_PORTSTATUS,
&portstatus);
if (result) {
pr_debug
("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_PORTSTATUS, result);
return;
}
wlandev->macmode =
(portstatus == HFA384x_PSTATUS_CONN_IBSS) ?
WLAN_MACMODE_IBSS_STA : WLAN_MACMODE_ESS_STA;
/* signal back up to cfg80211 layer */
prism2_connect_result(wlandev, P80211ENUM_truth_false);
/* Get the ball rolling on the comms quality stuff */
prism2sta_commsqual_defer(&hw->commsqual_bh);
}
break;
case HFA384x_LINK_DISCONNECTED:
/* This one indicates that our association is gone. We've
* lost connection with the AP and/or been disassociated.
* This indicates that the MAC has completely cleared it's
* associated state. We * should send a deauth indication
* (implying disassoc) up * to the MLME.
* Response:
* Indicate Deauthentication
* Block Transmits, Ignore receives of data frames
*/
if (wlandev->netdev->type == ARPHRD_ETHER)
netdev_info(wlandev->netdev,
"linkstatus=DISCONNECTED (unhandled)\n");
wlandev->macmode = WLAN_MACMODE_NONE;
netif_carrier_off(wlandev->netdev);
/* signal back up to cfg80211 layer */
prism2_disconnected(wlandev);
break;
case HFA384x_LINK_AP_CHANGE:
/* This one indicates that the MAC has decided to and
* successfully completed a change to another AP. We
* should probably implement a reassociation indication
* in response to this one. I'm thinking that the
* p80211 layer needs to be notified in case of
* buffering/queueing issues. User mode also needs to be
* notified so that any BSS dependent elements can be
* updated.
* associated state. We * should send a deauth indication
* (implying disassoc) up * to the MLME.
* Response:
* Indicate Reassociation
* Enable Transmits, Receives and pass up data frames
*/
netdev_info(wlandev->netdev, "linkstatus=AP_CHANGE\n");
result = hfa384x_drvr_getconfig(hw,
HFA384x_RID_CURRENTBSSID,
wlandev->bssid, WLAN_BSSID_LEN);
if (result) {
pr_debug("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_CURRENTBSSID, result);
return;
}
result = hfa384x_drvr_getconfig(hw,
HFA384x_RID_CURRENTSSID,
&ssid, sizeof(ssid));
if (result) {
pr_debug("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_CURRENTSSID, result);
return;
}
prism2mgmt_bytestr2pstr((struct hfa384x_bytestr *)&ssid,
(struct p80211pstrd *)&wlandev->ssid);
hw->link_status = HFA384x_LINK_CONNECTED;
netif_carrier_on(wlandev->netdev);
/* signal back up to cfg80211 layer */
prism2_roamed(wlandev);
break;
case HFA384x_LINK_AP_OUTOFRANGE:
/* This one indicates that the MAC has decided that the
* AP is out of range, but hasn't found a better candidate
* so the MAC maintains its "associated" state in case
* we get back in range. We should block transmits and
* receives in this state. Do we need an indication here?
* Probably not since a polling user-mode element would
* get this status from p2PortStatus(FD40). What about
* p80211?
* Response:
* Block Transmits, Ignore receives of data frames
*/
netdev_info(wlandev->netdev, "linkstatus=AP_OUTOFRANGE (unhandled)\n");
netif_carrier_off(wlandev->netdev);
break;
case HFA384x_LINK_AP_INRANGE:
/* This one indicates that the MAC has decided that the
* AP is back in range. We continue working with our
* existing association.
* Response:
* Enable Transmits, Receives and pass up data frames
*/
netdev_info(wlandev->netdev, "linkstatus=AP_INRANGE\n");
hw->link_status = HFA384x_LINK_CONNECTED;
netif_carrier_on(wlandev->netdev);
break;
case HFA384x_LINK_ASSOCFAIL:
/* This one is actually a peer to CONNECTED. We've
* requested a join for a given SSID and optionally BSSID.
* We can use this one to indicate authentication and
* association failures. The trick is going to be
* 1) identifying the failure, and 2) state management.
* Response:
* Disable Transmits, Ignore receives of data frames
*/
if (hw->join_ap && --hw->join_retries > 0) {
struct hfa384x_join_request_data joinreq;
joinreq = hw->joinreq;
/* Send the join request */
hfa384x_drvr_setconfig(hw,
HFA384x_RID_JOINREQUEST,
&joinreq,
HFA384x_RID_JOINREQUEST_LEN);
netdev_info(wlandev->netdev,
"linkstatus=ASSOCFAIL (re-submitting join)\n");
} else {
netdev_info(wlandev->netdev, "linkstatus=ASSOCFAIL (unhandled)\n");
}
netif_carrier_off(wlandev->netdev);
/* signal back up to cfg80211 layer */
prism2_connect_result(wlandev, P80211ENUM_truth_true);
break;
default:
/* This is bad, IO port problems? */
netdev_warn(wlandev->netdev,
"unknown linkstatus=0x%02x\n", hw->link_status);
return;
}
wlandev->linkstatus = (hw->link_status == HFA384x_LINK_CONNECTED);
}
/*
* prism2sta_inf_linkstatus
*
* Handles the receipt of a Link Status info frame.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_linkstatus(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
hw->link_status_new = le16_to_cpu(inf->info.linkstatus.linkstatus);
schedule_work(&hw->link_bh);
}
/*
* prism2sta_inf_assocstatus
*
* Handles the receipt of an Association Status info frame. Should
* be present in APs only.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_assocstatus(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
struct hfa384x_assoc_status rec;
int i;
memcpy(&rec, &inf->info.assocstatus, sizeof(rec));
le16_to_cpus(&rec.assocstatus);
le16_to_cpus(&rec.reason);
/*
* Find the address in the list of authenticated stations.
* If it wasn't found, then this address has not been previously
* authenticated and something weird has happened if this is
* anything other than an "authentication failed" message.
* If the address was found, then set the "associated" flag for
* that station, based on whether the station is associating or
* losing its association. Something weird has also happened
* if we find the address in the list of authenticated stations
* but we are getting an "authentication failed" message.
*/
for (i = 0; i < hw->authlist.cnt; i++)
if (ether_addr_equal(rec.sta_addr, hw->authlist.addr[i]))
break;
if (i >= hw->authlist.cnt) {
if (rec.assocstatus != HFA384x_ASSOCSTATUS_AUTHFAIL)
netdev_warn(wlandev->netdev,
"assocstatus info frame received for non-authenticated station.\n");
} else {
hw->authlist.assoc[i] =
(rec.assocstatus == HFA384x_ASSOCSTATUS_STAASSOC ||
rec.assocstatus == HFA384x_ASSOCSTATUS_REASSOC);
if (rec.assocstatus == HFA384x_ASSOCSTATUS_AUTHFAIL)
netdev_warn(wlandev->netdev,
"authfail assocstatus info frame received for authenticated station.\n");
}
}
/*
* prism2sta_inf_authreq
*
* Handles the receipt of an Authentication Request info frame. Should
* be present in APs only.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*
*/
static void prism2sta_inf_authreq(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
struct sk_buff *skb;
skb = dev_alloc_skb(sizeof(*inf));
if (skb) {
skb_put(skb, sizeof(*inf));
memcpy(skb->data, inf, sizeof(*inf));
skb_queue_tail(&hw->authq, skb);
schedule_work(&hw->link_bh);
}
}
static void prism2sta_inf_authreq_defer(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
struct hfa384x_authenticate_station_data rec;
int i, added, result, cnt;
u8 *addr;
/*
* Build the AuthenticateStation record. Initialize it for denying
* authentication.
*/
ether_addr_copy(rec.address, inf->info.authreq.sta_addr);
rec.status = cpu_to_le16(P80211ENUM_status_unspec_failure);
/*
* Authenticate based on the access mode.
*/
switch (hw->accessmode) {
case WLAN_ACCESS_NONE:
/*
* Deny all new authentications. However, if a station
* is ALREADY authenticated, then accept it.
*/
for (i = 0; i < hw->authlist.cnt; i++)
if (ether_addr_equal(rec.address,
hw->authlist.addr[i])) {
rec.status = cpu_to_le16(P80211ENUM_status_successful);
break;
}
break;
case WLAN_ACCESS_ALL:
/*
* Allow all authentications.
*/
rec.status = cpu_to_le16(P80211ENUM_status_successful);
break;
case WLAN_ACCESS_ALLOW:
/*
* Only allow the authentication if the MAC address
* is in the list of allowed addresses.
*
* Since this is the interrupt handler, we may be here
* while the access list is in the middle of being
* updated. Choose the list which is currently okay.
* See "prism2mib_priv_accessallow()" for details.
*/
if (hw->allow.modify == 0) {
cnt = hw->allow.cnt;
addr = hw->allow.addr[0];
} else {
cnt = hw->allow.cnt1;
addr = hw->allow.addr1[0];
}
for (i = 0; i < cnt; i++, addr += ETH_ALEN)
if (ether_addr_equal(rec.address, addr)) {
rec.status = cpu_to_le16(P80211ENUM_status_successful);
break;
}
break;
case WLAN_ACCESS_DENY:
/*
* Allow the authentication UNLESS the MAC address is
* in the list of denied addresses.
*
* Since this is the interrupt handler, we may be here
* while the access list is in the middle of being
* updated. Choose the list which is currently okay.
* See "prism2mib_priv_accessdeny()" for details.
*/
if (hw->deny.modify == 0) {
cnt = hw->deny.cnt;
addr = hw->deny.addr[0];
} else {
cnt = hw->deny.cnt1;
addr = hw->deny.addr1[0];
}
rec.status = cpu_to_le16(P80211ENUM_status_successful);
for (i = 0; i < cnt; i++, addr += ETH_ALEN)
if (ether_addr_equal(rec.address, addr)) {
rec.status = cpu_to_le16(P80211ENUM_status_unspec_failure);
break;
}
break;
}
/*
* If the authentication is okay, then add the MAC address to the
* list of authenticated stations. Don't add the address if it
* is already in the list. (802.11b does not seem to disallow
* a station from issuing an authentication request when the
* station is already authenticated. Does this sort of thing
* ever happen? We might as well do the check just in case.)
*/
added = 0;
if (rec.status == cpu_to_le16(P80211ENUM_status_successful)) {
for (i = 0; i < hw->authlist.cnt; i++)
if (ether_addr_equal(rec.address,
hw->authlist.addr[i]))
break;
if (i >= hw->authlist.cnt) {
if (hw->authlist.cnt >= WLAN_AUTH_MAX) {
rec.status = cpu_to_le16(P80211ENUM_status_ap_full);
} else {
ether_addr_copy(hw->authlist.addr[hw->authlist.cnt],
rec.address);
hw->authlist.cnt++;
added = 1;
}
}
}
/*
* Send back the results of the authentication. If this doesn't work,
* then make sure to remove the address from the authenticated list if
* it was added.
*/
rec.algorithm = inf->info.authreq.algorithm;
result = hfa384x_drvr_setconfig(hw, HFA384x_RID_AUTHENTICATESTA,
&rec, sizeof(rec));
if (result) {
if (added)
hw->authlist.cnt--;
netdev_err(wlandev->netdev,
"setconfig(authenticatestation) failed, result=%d\n",
result);
}
}
/*
* prism2sta_inf_psusercnt
*
* Handles the receipt of a PowerSaveUserCount info frame. Should
* be present in APs only.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to info frame (contents in hfa384x order)
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
static void prism2sta_inf_psusercnt(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
struct hfa384x *hw = wlandev->priv;
hw->psusercount = le16_to_cpu(inf->info.psusercnt.usercnt);
}
/*
* prism2sta_ev_info
*
* Handles the Info event.
*
* Arguments:
* wlandev wlan device structure
* inf ptr to a generic info frame
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
void prism2sta_ev_info(struct wlandevice *wlandev,
struct hfa384x_inf_frame *inf)
{
le16_to_cpus(&inf->infotype);
/* Dispatch */
switch (inf->infotype) {
case HFA384x_IT_HANDOVERADDR:
prism2sta_inf_handover(wlandev, inf);
break;
case HFA384x_IT_COMMTALLIES:
prism2sta_inf_tallies(wlandev, inf);
break;
case HFA384x_IT_HOSTSCANRESULTS:
prism2sta_inf_hostscanresults(wlandev, inf);
break;
case HFA384x_IT_SCANRESULTS:
prism2sta_inf_scanresults(wlandev, inf);
break;
case HFA384x_IT_CHINFORESULTS:
prism2sta_inf_chinforesults(wlandev, inf);
break;
case HFA384x_IT_LINKSTATUS:
prism2sta_inf_linkstatus(wlandev, inf);
break;
case HFA384x_IT_ASSOCSTATUS:
prism2sta_inf_assocstatus(wlandev, inf);
break;
case HFA384x_IT_AUTHREQ:
prism2sta_inf_authreq(wlandev, inf);
break;
case HFA384x_IT_PSUSERCNT:
prism2sta_inf_psusercnt(wlandev, inf);
break;
case HFA384x_IT_KEYIDCHANGED:
netdev_warn(wlandev->netdev, "Unhandled IT_KEYIDCHANGED\n");
break;
case HFA384x_IT_ASSOCREQ:
netdev_warn(wlandev->netdev, "Unhandled IT_ASSOCREQ\n");
break;
case HFA384x_IT_MICFAILURE:
netdev_warn(wlandev->netdev, "Unhandled IT_MICFAILURE\n");
break;
default:
netdev_warn(wlandev->netdev,
"Unknown info type=0x%02x\n", inf->infotype);
break;
}
}
/*
* prism2sta_ev_txexc
*
* Handles the TxExc event. A Transmit Exception event indicates
* that the MAC's TX process was unsuccessful - so the packet did
* not get transmitted.
*
* Arguments:
* wlandev wlan device structure
* status tx frame status word
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
void prism2sta_ev_txexc(struct wlandevice *wlandev, u16 status)
{
pr_debug("TxExc status=0x%x.\n", status);
}
/*
* prism2sta_ev_tx
*
* Handles the Tx event.
*
* Arguments:
* wlandev wlan device structure
* status tx frame status word
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
void prism2sta_ev_tx(struct wlandevice *wlandev, u16 status)
{
pr_debug("Tx Complete, status=0x%04x\n", status);
/* update linux network stats */
wlandev->netdev->stats.tx_packets++;
}
/*
* prism2sta_ev_alloc
*
* Handles the Alloc event.
*
* Arguments:
* wlandev wlan device structure
*
* Returns:
* nothing
*
* Side effects:
*
* Call context:
* interrupt
*/
void prism2sta_ev_alloc(struct wlandevice *wlandev)
{
netif_wake_queue(wlandev->netdev);
}
/*
* create_wlan
*
* Called at module init time. This creates the struct wlandevice structure
* and initializes it with relevant bits.
*
* Arguments:
* none
*
* Returns:
* the created struct wlandevice structure.
*
* Side effects:
* also allocates the priv/hw structures.
*
* Call context:
* process thread
*
*/
static struct wlandevice *create_wlan(void)
{
struct wlandevice *wlandev = NULL;
struct hfa384x *hw = NULL;
/* Alloc our structures */
wlandev = kzalloc(sizeof(*wlandev), GFP_KERNEL);
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
if (!wlandev || !hw) {
kfree(wlandev);
kfree(hw);
return NULL;
}
/* Initialize the network device object. */
wlandev->nsdname = dev_info;
wlandev->msdstate = WLAN_MSD_HWPRESENT_PENDING;
wlandev->priv = hw;
wlandev->open = prism2sta_open;
wlandev->close = prism2sta_close;
wlandev->reset = prism2sta_reset;
wlandev->txframe = prism2sta_txframe;
wlandev->mlmerequest = prism2sta_mlmerequest;
wlandev->set_multicast_list = prism2sta_setmulticast;
wlandev->tx_timeout = hfa384x_tx_timeout;
wlandev->nsdcaps = P80211_NSDCAP_HWFRAGMENT | P80211_NSDCAP_AUTOJOIN;
/* Initialize the device private data structure. */
hw->dot11_desired_bss_type = 1;
return wlandev;
}
void prism2sta_commsqual_defer(struct work_struct *data)
{
struct hfa384x *hw = container_of(data, struct hfa384x, commsqual_bh);
struct wlandevice *wlandev = hw->wlandev;
struct hfa384x_bytestr32 ssid;
struct p80211msg_dot11req_mibget msg;
struct p80211item_uint32 *mibitem = (struct p80211item_uint32 *)
&msg.mibattribute.data;
int result = 0;
if (hw->wlandev->hwremoved)
return;
/* we don't care if we're in AP mode */
if ((wlandev->macmode == WLAN_MACMODE_NONE) ||
(wlandev->macmode == WLAN_MACMODE_ESS_AP)) {
return;
}
/* It only makes sense to poll these in non-IBSS */
if (wlandev->macmode != WLAN_MACMODE_IBSS_STA) {
result = hfa384x_drvr_getconfig(hw, HFA384x_RID_DBMCOMMSQUALITY,
&hw->qual, HFA384x_RID_DBMCOMMSQUALITY_LEN);
if (result) {
netdev_err(wlandev->netdev, "error fetching commsqual\n");
return;
}
pr_debug("commsqual %d %d %d\n",
le16_to_cpu(hw->qual.cq_curr_bss),
le16_to_cpu(hw->qual.asl_curr_bss),
le16_to_cpu(hw->qual.anl_curr_fc));
}
/* Get the signal rate */
msg.msgcode = DIDMSG_DOT11REQ_MIBGET;
mibitem->did = DIDMIB_P2_MAC_CURRENTTXRATE;
result = p80211req_dorequest(wlandev, (u8 *)&msg);
if (result) {
pr_debug("get signal rate failed, result = %d\n",
result);
return;
}
switch (mibitem->data) {
case HFA384x_RATEBIT_1:
hw->txrate = 10;
break;
case HFA384x_RATEBIT_2:
hw->txrate = 20;
break;
case HFA384x_RATEBIT_5dot5:
hw->txrate = 55;
break;
case HFA384x_RATEBIT_11:
hw->txrate = 110;
break;
default:
pr_debug("Bad ratebit (%d)\n", mibitem->data);
}
/* Lastly, we need to make sure the BSSID didn't change on us */
result = hfa384x_drvr_getconfig(hw,
HFA384x_RID_CURRENTBSSID,
wlandev->bssid, WLAN_BSSID_LEN);
if (result) {
pr_debug("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_CURRENTBSSID, result);
return;
}
result = hfa384x_drvr_getconfig(hw,
HFA384x_RID_CURRENTSSID,
&ssid, sizeof(ssid));
if (result) {
pr_debug("getconfig(0x%02x) failed, result = %d\n",
HFA384x_RID_CURRENTSSID, result);
return;
}
prism2mgmt_bytestr2pstr((struct hfa384x_bytestr *)&ssid,
(struct p80211pstrd *)&wlandev->ssid);
/* Reschedule timer */
mod_timer(&hw->commsqual_timer, jiffies + HZ);
}
void prism2sta_commsqual_timer(struct timer_list *t)
{
struct hfa384x *hw = from_timer(hw, t, commsqual_timer);
schedule_work(&hw->commsqual_bh);
}
| linux-master | drivers/staging/wlan-ng/prism2sta.c |
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