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// SPDX-License-Identifier: GPL-2.0
#include "util/debug.h"
#include "util/dso.h"
#include "util/event.h"
#include "util/map.h"
#include "util/symbol.h"
#include "util/sort.h"
#include "util/evsel.h"
#include "util/evlist.h"
#include "util/machine.h"
#include "util/thread.h"
#include "util/parse-events.h"
#include "tests/tests.h"
#include "tests/hists_common.h"
#include <linux/kernel.h>
struct sample {
u32 cpu;
u32 pid;
u64 ip;
struct thread *thread;
struct map *map;
struct symbol *sym;
};
/* For the numbers, see hists_common.c */
static struct sample fake_samples[] = {
/* perf [kernel] schedule() */
{ .cpu = 0, .pid = FAKE_PID_PERF1, .ip = FAKE_IP_KERNEL_SCHEDULE, },
/* perf [perf] main() */
{ .cpu = 1, .pid = FAKE_PID_PERF1, .ip = FAKE_IP_PERF_MAIN, },
/* perf [perf] cmd_record() */
{ .cpu = 1, .pid = FAKE_PID_PERF1, .ip = FAKE_IP_PERF_CMD_RECORD, },
/* perf [libc] malloc() */
{ .cpu = 1, .pid = FAKE_PID_PERF1, .ip = FAKE_IP_LIBC_MALLOC, },
/* perf [libc] free() */
{ .cpu = 2, .pid = FAKE_PID_PERF1, .ip = FAKE_IP_LIBC_FREE, },
/* perf [perf] main() */
{ .cpu = 2, .pid = FAKE_PID_PERF2, .ip = FAKE_IP_PERF_MAIN, },
/* perf [kernel] page_fault() */
{ .cpu = 2, .pid = FAKE_PID_PERF2, .ip = FAKE_IP_KERNEL_PAGE_FAULT, },
/* bash [bash] main() */
{ .cpu = 3, .pid = FAKE_PID_BASH, .ip = FAKE_IP_BASH_MAIN, },
/* bash [bash] xmalloc() */
{ .cpu = 0, .pid = FAKE_PID_BASH, .ip = FAKE_IP_BASH_XMALLOC, },
/* bash [kernel] page_fault() */
{ .cpu = 1, .pid = FAKE_PID_BASH, .ip = FAKE_IP_KERNEL_PAGE_FAULT, },
};
static int add_hist_entries(struct hists *hists, struct machine *machine)
{
struct addr_location al;
struct evsel *evsel = hists_to_evsel(hists);
struct perf_sample sample = { .period = 100, };
size_t i;
addr_location__init(&al);
for (i = 0; i < ARRAY_SIZE(fake_samples); i++) {
struct hist_entry_iter iter = {
.evsel = evsel,
.sample = &sample,
.ops = &hist_iter_normal,
.hide_unresolved = false,
};
sample.cpumode = PERF_RECORD_MISC_USER;
sample.cpu = fake_samples[i].cpu;
sample.pid = fake_samples[i].pid;
sample.tid = fake_samples[i].pid;
sample.ip = fake_samples[i].ip;
if (machine__resolve(machine, &al, &sample) < 0)
goto out;
if (hist_entry_iter__add(&iter, &al, sysctl_perf_event_max_stack,
NULL) < 0) {
goto out;
}
fake_samples[i].thread = al.thread;
map__put(fake_samples[i].map);
fake_samples[i].map = map__get(al.map);
fake_samples[i].sym = al.sym;
}
addr_location__exit(&al);
return TEST_OK;
out:
pr_debug("Not enough memory for adding a hist entry\n");
addr_location__exit(&al);
return TEST_FAIL;
}
static void del_hist_entries(struct hists *hists)
{
struct hist_entry *he;
struct rb_root_cached *root_in;
struct rb_root_cached *root_out;
struct rb_node *node;
if (hists__has(hists, need_collapse))
root_in = &hists->entries_collapsed;
else
root_in = hists->entries_in;
root_out = &hists->entries;
while (!RB_EMPTY_ROOT(&root_out->rb_root)) {
node = rb_first_cached(root_out);
he = rb_entry(node, struct hist_entry, rb_node);
rb_erase_cached(node, root_out);
rb_erase_cached(&he->rb_node_in, root_in);
hist_entry__delete(he);
}
}
static void put_fake_samples(void)
{
size_t i;
for (i = 0; i < ARRAY_SIZE(fake_samples); i++) {
map__put(fake_samples[i].map);
fake_samples[i].map = NULL;
}
}
typedef int (*test_fn_t)(struct evsel *, struct machine *);
#define COMM(he) (thread__comm_str(he->thread))
#define DSO(he) (map__dso(he->ms.map)->short_name)
#define SYM(he) (he->ms.sym->name)
#define CPU(he) (he->cpu)
#define PID(he) (thread__tid(he->thread))
/* default sort keys (no field) */
static int test1(struct evsel *evsel, struct machine *machine)
{
int err;
struct hists *hists = evsel__hists(evsel);
struct hist_entry *he;
struct rb_root_cached *root;
struct rb_node *node;
field_order = NULL;
sort_order = NULL; /* equivalent to sort_order = "comm,dso,sym" */
setup_sorting(NULL);
/*
* expected output:
*
* Overhead Command Shared Object Symbol
* ======== ======= ============= ==============
* 20.00% perf perf [.] main
* 10.00% bash [kernel] [k] page_fault
* 10.00% bash bash [.] main
* 10.00% bash bash [.] xmalloc
* 10.00% perf [kernel] [k] page_fault
* 10.00% perf [kernel] [k] schedule
* 10.00% perf libc [.] free
* 10.00% perf libc [.] malloc
* 10.00% perf perf [.] cmd_record
*/
err = add_hist_entries(hists, machine);
if (err < 0)
goto out;
hists__collapse_resort(hists, NULL);
evsel__output_resort(evsel, NULL);
if (verbose > 2) {
pr_info("[fields = %s, sort = %s]\n", field_order, sort_order);
print_hists_out(hists);
}
root = &hists->entries;
node = rb_first_cached(root);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "perf") &&
!strcmp(SYM(he), "main") && he->stat.period == 200);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "[kernel]") &&
!strcmp(SYM(he), "page_fault") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "bash") &&
!strcmp(SYM(he), "main") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "bash") &&
!strcmp(SYM(he), "xmalloc") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "[kernel]") &&
!strcmp(SYM(he), "page_fault") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "[kernel]") &&
!strcmp(SYM(he), "schedule") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "libc") &&
!strcmp(SYM(he), "free") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "libc") &&
!strcmp(SYM(he), "malloc") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "perf") &&
!strcmp(SYM(he), "cmd_record") && he->stat.period == 100);
out:
del_hist_entries(hists);
reset_output_field();
return err;
}
/* mixed fields and sort keys */
static int test2(struct evsel *evsel, struct machine *machine)
{
int err;
struct hists *hists = evsel__hists(evsel);
struct hist_entry *he;
struct rb_root_cached *root;
struct rb_node *node;
field_order = "overhead,cpu";
sort_order = "pid";
setup_sorting(NULL);
/*
* expected output:
*
* Overhead CPU Command: Pid
* ======== === =============
* 30.00% 1 perf : 100
* 10.00% 0 perf : 100
* 10.00% 2 perf : 100
* 20.00% 2 perf : 200
* 10.00% 0 bash : 300
* 10.00% 1 bash : 300
* 10.00% 3 bash : 300
*/
err = add_hist_entries(hists, machine);
if (err < 0)
goto out;
hists__collapse_resort(hists, NULL);
evsel__output_resort(evsel, NULL);
if (verbose > 2) {
pr_info("[fields = %s, sort = %s]\n", field_order, sort_order);
print_hists_out(hists);
}
root = &hists->entries;
node = rb_first_cached(root);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 1 && PID(he) == 100 && he->stat.period == 300);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 0 && PID(he) == 100 && he->stat.period == 100);
out:
del_hist_entries(hists);
reset_output_field();
return err;
}
/* fields only (no sort key) */
static int test3(struct evsel *evsel, struct machine *machine)
{
int err;
struct hists *hists = evsel__hists(evsel);
struct hist_entry *he;
struct rb_root_cached *root;
struct rb_node *node;
field_order = "comm,overhead,dso";
sort_order = NULL;
setup_sorting(NULL);
/*
* expected output:
*
* Command Overhead Shared Object
* ======= ======== =============
* bash 20.00% bash
* bash 10.00% [kernel]
* perf 30.00% perf
* perf 20.00% [kernel]
* perf 20.00% libc
*/
err = add_hist_entries(hists, machine);
if (err < 0)
goto out;
hists__collapse_resort(hists, NULL);
evsel__output_resort(evsel, NULL);
if (verbose > 2) {
pr_info("[fields = %s, sort = %s]\n", field_order, sort_order);
print_hists_out(hists);
}
root = &hists->entries;
node = rb_first_cached(root);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "bash") &&
he->stat.period == 200);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "[kernel]") &&
he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "perf") &&
he->stat.period == 300);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "[kernel]") &&
he->stat.period == 200);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "libc") &&
he->stat.period == 200);
out:
del_hist_entries(hists);
reset_output_field();
return err;
}
/* handle duplicate 'dso' field */
static int test4(struct evsel *evsel, struct machine *machine)
{
int err;
struct hists *hists = evsel__hists(evsel);
struct hist_entry *he;
struct rb_root_cached *root;
struct rb_node *node;
field_order = "dso,sym,comm,overhead,dso";
sort_order = "sym";
setup_sorting(NULL);
/*
* expected output:
*
* Shared Object Symbol Command Overhead
* ============= ============== ======= ========
* perf [.] cmd_record perf 10.00%
* libc [.] free perf 10.00%
* bash [.] main bash 10.00%
* perf [.] main perf 20.00%
* libc [.] malloc perf 10.00%
* [kernel] [k] page_fault bash 10.00%
* [kernel] [k] page_fault perf 10.00%
* [kernel] [k] schedule perf 10.00%
* bash [.] xmalloc bash 10.00%
*/
err = add_hist_entries(hists, machine);
if (err < 0)
goto out;
hists__collapse_resort(hists, NULL);
evsel__output_resort(evsel, NULL);
if (verbose > 2) {
pr_info("[fields = %s, sort = %s]\n", field_order, sort_order);
print_hists_out(hists);
}
root = &hists->entries;
node = rb_first_cached(root);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "perf") && !strcmp(SYM(he), "cmd_record") &&
!strcmp(COMM(he), "perf") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "libc") && !strcmp(SYM(he), "free") &&
!strcmp(COMM(he), "perf") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "bash") && !strcmp(SYM(he), "main") &&
!strcmp(COMM(he), "bash") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "perf") && !strcmp(SYM(he), "main") &&
!strcmp(COMM(he), "perf") && he->stat.period == 200);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "libc") && !strcmp(SYM(he), "malloc") &&
!strcmp(COMM(he), "perf") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "[kernel]") && !strcmp(SYM(he), "page_fault") &&
!strcmp(COMM(he), "bash") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "[kernel]") && !strcmp(SYM(he), "page_fault") &&
!strcmp(COMM(he), "perf") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "[kernel]") && !strcmp(SYM(he), "schedule") &&
!strcmp(COMM(he), "perf") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
!strcmp(DSO(he), "bash") && !strcmp(SYM(he), "xmalloc") &&
!strcmp(COMM(he), "bash") && he->stat.period == 100);
out:
del_hist_entries(hists);
reset_output_field();
return err;
}
/* full sort keys w/o overhead field */
static int test5(struct evsel *evsel, struct machine *machine)
{
int err;
struct hists *hists = evsel__hists(evsel);
struct hist_entry *he;
struct rb_root_cached *root;
struct rb_node *node;
field_order = "cpu,pid,comm,dso,sym";
sort_order = "dso,pid";
setup_sorting(NULL);
/*
* expected output:
*
* CPU Command: Pid Command Shared Object Symbol
* === ============= ======= ============= ==============
* 0 perf: 100 perf [kernel] [k] schedule
* 2 perf: 200 perf [kernel] [k] page_fault
* 1 bash: 300 bash [kernel] [k] page_fault
* 0 bash: 300 bash bash [.] xmalloc
* 3 bash: 300 bash bash [.] main
* 1 perf: 100 perf libc [.] malloc
* 2 perf: 100 perf libc [.] free
* 1 perf: 100 perf perf [.] cmd_record
* 1 perf: 100 perf perf [.] main
* 2 perf: 200 perf perf [.] main
*/
err = add_hist_entries(hists, machine);
if (err < 0)
goto out;
hists__collapse_resort(hists, NULL);
evsel__output_resort(evsel, NULL);
if (verbose > 2) {
pr_info("[fields = %s, sort = %s]\n", field_order, sort_order);
print_hists_out(hists);
}
root = &hists->entries;
node = rb_first_cached(root);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 0 && PID(he) == 100 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "[kernel]") &&
!strcmp(SYM(he), "schedule") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 2 && PID(he) == 200 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "[kernel]") &&
!strcmp(SYM(he), "page_fault") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 1 && PID(he) == 300 &&
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "[kernel]") &&
!strcmp(SYM(he), "page_fault") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 0 && PID(he) == 300 &&
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "bash") &&
!strcmp(SYM(he), "xmalloc") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 3 && PID(he) == 300 &&
!strcmp(COMM(he), "bash") && !strcmp(DSO(he), "bash") &&
!strcmp(SYM(he), "main") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 1 && PID(he) == 100 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "libc") &&
!strcmp(SYM(he), "malloc") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 2 && PID(he) == 100 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "libc") &&
!strcmp(SYM(he), "free") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 1 && PID(he) == 100 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "perf") &&
!strcmp(SYM(he), "cmd_record") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 1 && PID(he) == 100 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "perf") &&
!strcmp(SYM(he), "main") && he->stat.period == 100);
node = rb_next(node);
he = rb_entry(node, struct hist_entry, rb_node);
TEST_ASSERT_VAL("Invalid hist entry",
CPU(he) == 2 && PID(he) == 200 &&
!strcmp(COMM(he), "perf") && !strcmp(DSO(he), "perf") &&
!strcmp(SYM(he), "main") && he->stat.period == 100);
out:
del_hist_entries(hists);
reset_output_field();
return err;
}
static int test__hists_output(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int err = TEST_FAIL;
struct machines machines;
struct machine *machine;
struct evsel *evsel;
struct evlist *evlist = evlist__new();
size_t i;
test_fn_t testcases[] = {
test1,
test2,
test3,
test4,
test5,
};
TEST_ASSERT_VAL("No memory", evlist);
err = parse_event(evlist, "cpu-clock");
if (err)
goto out;
err = TEST_FAIL;
machines__init(&machines);
/* setup threads/dso/map/symbols also */
machine = setup_fake_machine(&machines);
if (!machine)
goto out;
if (verbose > 1)
machine__fprintf(machine, stderr);
evsel = evlist__first(evlist);
for (i = 0; i < ARRAY_SIZE(testcases); i++) {
err = testcases[i](evsel, machine);
if (err < 0)
break;
}
out:
/* tear down everything */
evlist__delete(evlist);
machines__exit(&machines);
put_fake_samples();
return err;
}
DEFINE_SUITE("Sort output of hist entries", hists_output);
| linux-master | tools/perf/tests/hists_output.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
#include <linux/time64.h>
#include <inttypes.h>
#include <string.h>
#include "time-utils.h"
#include "evlist.h"
#include "session.h"
#include "debug.h"
#include "tests.h"
static bool test__parse_nsec_time(const char *str, u64 expected)
{
u64 ptime;
int err;
pr_debug("\nparse_nsec_time(\"%s\")\n", str);
err = parse_nsec_time(str, &ptime);
if (err) {
pr_debug("error %d\n", err);
return false;
}
if (ptime != expected) {
pr_debug("Failed. ptime %" PRIu64 " expected %" PRIu64 "\n",
ptime, expected);
return false;
}
pr_debug("%" PRIu64 "\n", ptime);
return true;
}
static bool test__perf_time__parse_str(const char *ostr, u64 start, u64 end)
{
struct perf_time_interval ptime;
int err;
pr_debug("\nperf_time__parse_str(\"%s\")\n", ostr);
err = perf_time__parse_str(&ptime, ostr);
if (err) {
pr_debug("Error %d\n", err);
return false;
}
if (ptime.start != start || ptime.end != end) {
pr_debug("Failed. Expected %" PRIu64 " to %" PRIu64 "\n",
start, end);
return false;
}
return true;
}
#define TEST_MAX 64
struct test_data {
const char *str;
u64 first;
u64 last;
struct perf_time_interval ptime[TEST_MAX];
int num;
u64 skip[TEST_MAX];
u64 noskip[TEST_MAX];
};
static bool test__perf_time__parse_for_ranges(struct test_data *d)
{
struct evlist evlist = {
.first_sample_time = d->first,
.last_sample_time = d->last,
};
struct perf_session session = { .evlist = &evlist };
struct perf_time_interval *ptime = NULL;
int range_size, range_num;
bool pass = false;
int i, err;
pr_debug("\nperf_time__parse_for_ranges(\"%s\")\n", d->str);
if (strchr(d->str, '%'))
pr_debug("first_sample_time %" PRIu64 " last_sample_time %" PRIu64 "\n",
d->first, d->last);
err = perf_time__parse_for_ranges(d->str, &session, &ptime, &range_size,
&range_num);
if (err) {
pr_debug("error %d\n", err);
goto out;
}
if (range_size < d->num || range_num != d->num) {
pr_debug("bad size: range_size %d range_num %d expected num %d\n",
range_size, range_num, d->num);
goto out;
}
for (i = 0; i < d->num; i++) {
if (ptime[i].start != d->ptime[i].start ||
ptime[i].end != d->ptime[i].end) {
pr_debug("bad range %d expected %" PRIu64 " to %" PRIu64 "\n",
i, d->ptime[i].start, d->ptime[i].end);
goto out;
}
}
if (perf_time__ranges_skip_sample(ptime, d->num, 0)) {
pr_debug("failed to keep 0\n");
goto out;
}
for (i = 0; i < TEST_MAX; i++) {
if (d->skip[i] &&
!perf_time__ranges_skip_sample(ptime, d->num, d->skip[i])) {
pr_debug("failed to skip %" PRIu64 "\n", d->skip[i]);
goto out;
}
if (d->noskip[i] &&
perf_time__ranges_skip_sample(ptime, d->num, d->noskip[i])) {
pr_debug("failed to keep %" PRIu64 "\n", d->noskip[i]);
goto out;
}
}
pass = true;
out:
free(ptime);
return pass;
}
static int test__time_utils(struct test_suite *t __maybe_unused, int subtest __maybe_unused)
{
bool pass = true;
pass &= test__parse_nsec_time("0", 0);
pass &= test__parse_nsec_time("1", 1000000000ULL);
pass &= test__parse_nsec_time("0.000000001", 1);
pass &= test__parse_nsec_time("1.000000001", 1000000001ULL);
pass &= test__parse_nsec_time("123456.123456", 123456123456000ULL);
pass &= test__parse_nsec_time("1234567.123456789", 1234567123456789ULL);
pass &= test__parse_nsec_time("18446744073.709551615",
0xFFFFFFFFFFFFFFFFULL);
pass &= test__perf_time__parse_str("1234567.123456789,1234567.123456789",
1234567123456789ULL, 1234567123456789ULL);
pass &= test__perf_time__parse_str("1234567.123456789,1234567.123456790",
1234567123456789ULL, 1234567123456790ULL);
pass &= test__perf_time__parse_str("1234567.123456789,",
1234567123456789ULL, 0);
pass &= test__perf_time__parse_str(",1234567.123456789",
0, 1234567123456789ULL);
pass &= test__perf_time__parse_str("0,1234567.123456789",
0, 1234567123456789ULL);
{
u64 b = 1234567123456789ULL;
struct test_data d = {
.str = "1234567.123456789,1234567.123456790",
.ptime = { {b, b + 1}, },
.num = 1,
.skip = { b - 1, b + 2, },
.noskip = { b, b + 1, },
};
pass &= test__perf_time__parse_for_ranges(&d);
}
{
u64 b = 1234567123456789ULL;
u64 c = 7654321987654321ULL;
u64 e = 8000000000000000ULL;
struct test_data d = {
.str = "1234567.123456789,1234567.123456790 "
"7654321.987654321,7654321.987654444 "
"8000000,8000000.000000005",
.ptime = { {b, b + 1}, {c, c + 123}, {e, e + 5}, },
.num = 3,
.skip = { b - 1, b + 2, c - 1, c + 124, e - 1, e + 6 },
.noskip = { b, b + 1, c, c + 123, e, e + 5 },
};
pass &= test__perf_time__parse_for_ranges(&d);
}
{
u64 b = 7654321ULL * NSEC_PER_SEC;
struct test_data d = {
.str = "10%/1",
.first = b,
.last = b + 100,
.ptime = { {b, b + 9}, },
.num = 1,
.skip = { b - 1, b + 10, },
.noskip = { b, b + 9, },
};
pass &= test__perf_time__parse_for_ranges(&d);
}
{
u64 b = 7654321ULL * NSEC_PER_SEC;
struct test_data d = {
.str = "10%/2",
.first = b,
.last = b + 100,
.ptime = { {b + 10, b + 19}, },
.num = 1,
.skip = { b + 9, b + 20, },
.noskip = { b + 10, b + 19, },
};
pass &= test__perf_time__parse_for_ranges(&d);
}
{
u64 b = 11223344ULL * NSEC_PER_SEC;
struct test_data d = {
.str = "10%/1,10%/2",
.first = b,
.last = b + 100,
.ptime = { {b, b + 9}, {b + 10, b + 19}, },
.num = 2,
.skip = { b - 1, b + 20, },
.noskip = { b, b + 8, b + 9, b + 10, b + 11, b + 12, b + 19, },
};
pass &= test__perf_time__parse_for_ranges(&d);
}
{
u64 b = 11223344ULL * NSEC_PER_SEC;
struct test_data d = {
.str = "10%/1,10%/3,10%/10",
.first = b,
.last = b + 100,
.ptime = { {b, b + 9}, {b + 20, b + 29}, { b + 90, b + 100}, },
.num = 3,
.skip = { b - 1, b + 10, b + 19, b + 30, b + 89, b + 101 },
.noskip = { b, b + 9, b + 20, b + 29, b + 90, b + 100},
};
pass &= test__perf_time__parse_for_ranges(&d);
}
pr_debug("\n");
return pass ? 0 : TEST_FAIL;
}
DEFINE_SUITE("time utils", time_utils);
| linux-master | tools/perf/tests/time-utils-test.c |
// SPDX-License-Identifier: GPL-2.0
#include <sys/time.h>
#include <sys/prctl.h>
#include <errno.h>
#include <limits.h>
#include <time.h>
#include <stdlib.h>
#include <linux/zalloc.h>
#include <linux/err.h>
#include <perf/cpumap.h>
#include <perf/evlist.h>
#include <perf/mmap.h>
#include "debug.h"
#include "parse-events.h"
#include "evlist.h"
#include "evsel.h"
#include "thread_map.h"
#include "record.h"
#include "tests.h"
#include "util/mmap.h"
#include "util/sample.h"
#include "pmus.h"
static int spin_sleep(void)
{
struct timeval start, now, diff, maxtime;
struct timespec ts;
int err, i;
maxtime.tv_sec = 0;
maxtime.tv_usec = 50000;
err = gettimeofday(&start, NULL);
if (err)
return err;
/* Spin for 50ms */
while (1) {
for (i = 0; i < 1000; i++)
barrier();
err = gettimeofday(&now, NULL);
if (err)
return err;
timersub(&now, &start, &diff);
if (timercmp(&diff, &maxtime, > /* For checkpatch */))
break;
}
ts.tv_nsec = 50 * 1000 * 1000;
ts.tv_sec = 0;
/* Sleep for 50ms */
err = nanosleep(&ts, NULL);
if (err == EINTR)
err = 0;
return err;
}
struct switch_tracking {
struct evsel *switch_evsel;
struct evsel *cycles_evsel;
pid_t *tids;
int nr_tids;
int comm_seen[4];
int cycles_before_comm_1;
int cycles_between_comm_2_and_comm_3;
int cycles_after_comm_4;
};
static int check_comm(struct switch_tracking *switch_tracking,
union perf_event *event, const char *comm, int nr)
{
if (event->header.type == PERF_RECORD_COMM &&
(pid_t)event->comm.pid == getpid() &&
(pid_t)event->comm.tid == getpid() &&
strcmp(event->comm.comm, comm) == 0) {
if (switch_tracking->comm_seen[nr]) {
pr_debug("Duplicate comm event\n");
return -1;
}
switch_tracking->comm_seen[nr] = 1;
pr_debug3("comm event: %s nr: %d\n", event->comm.comm, nr);
return 1;
}
return 0;
}
static int check_cpu(struct switch_tracking *switch_tracking, int cpu)
{
int i, nr = cpu + 1;
if (cpu < 0)
return -1;
if (!switch_tracking->tids) {
switch_tracking->tids = calloc(nr, sizeof(pid_t));
if (!switch_tracking->tids)
return -1;
for (i = 0; i < nr; i++)
switch_tracking->tids[i] = -1;
switch_tracking->nr_tids = nr;
return 0;
}
if (cpu >= switch_tracking->nr_tids) {
void *addr;
addr = realloc(switch_tracking->tids, nr * sizeof(pid_t));
if (!addr)
return -1;
switch_tracking->tids = addr;
for (i = switch_tracking->nr_tids; i < nr; i++)
switch_tracking->tids[i] = -1;
switch_tracking->nr_tids = nr;
return 0;
}
return 0;
}
static int process_sample_event(struct evlist *evlist,
union perf_event *event,
struct switch_tracking *switch_tracking)
{
struct perf_sample sample;
struct evsel *evsel;
pid_t next_tid, prev_tid;
int cpu, err;
if (evlist__parse_sample(evlist, event, &sample)) {
pr_debug("evlist__parse_sample failed\n");
return -1;
}
evsel = evlist__id2evsel(evlist, sample.id);
if (evsel == switch_tracking->switch_evsel) {
next_tid = evsel__intval(evsel, &sample, "next_pid");
prev_tid = evsel__intval(evsel, &sample, "prev_pid");
cpu = sample.cpu;
pr_debug3("sched_switch: cpu: %d prev_tid %d next_tid %d\n",
cpu, prev_tid, next_tid);
err = check_cpu(switch_tracking, cpu);
if (err)
return err;
/*
* Check for no missing sched_switch events i.e. that the
* evsel->core.system_wide flag has worked.
*/
if (switch_tracking->tids[cpu] != -1 &&
switch_tracking->tids[cpu] != prev_tid) {
pr_debug("Missing sched_switch events\n");
return -1;
}
switch_tracking->tids[cpu] = next_tid;
}
if (evsel == switch_tracking->cycles_evsel) {
pr_debug3("cycles event\n");
if (!switch_tracking->comm_seen[0])
switch_tracking->cycles_before_comm_1 = 1;
if (switch_tracking->comm_seen[1] &&
!switch_tracking->comm_seen[2])
switch_tracking->cycles_between_comm_2_and_comm_3 = 1;
if (switch_tracking->comm_seen[3])
switch_tracking->cycles_after_comm_4 = 1;
}
return 0;
}
static int process_event(struct evlist *evlist, union perf_event *event,
struct switch_tracking *switch_tracking)
{
if (event->header.type == PERF_RECORD_SAMPLE)
return process_sample_event(evlist, event, switch_tracking);
if (event->header.type == PERF_RECORD_COMM) {
int err, done = 0;
err = check_comm(switch_tracking, event, "Test COMM 1", 0);
if (err < 0)
return -1;
done += err;
err = check_comm(switch_tracking, event, "Test COMM 2", 1);
if (err < 0)
return -1;
done += err;
err = check_comm(switch_tracking, event, "Test COMM 3", 2);
if (err < 0)
return -1;
done += err;
err = check_comm(switch_tracking, event, "Test COMM 4", 3);
if (err < 0)
return -1;
done += err;
if (done != 1) {
pr_debug("Unexpected comm event\n");
return -1;
}
}
return 0;
}
struct event_node {
struct list_head list;
union perf_event *event;
u64 event_time;
};
static int add_event(struct evlist *evlist, struct list_head *events,
union perf_event *event)
{
struct perf_sample sample;
struct event_node *node;
node = malloc(sizeof(struct event_node));
if (!node) {
pr_debug("malloc failed\n");
return -1;
}
node->event = event;
list_add(&node->list, events);
if (evlist__parse_sample(evlist, event, &sample)) {
pr_debug("evlist__parse_sample failed\n");
return -1;
}
if (!sample.time) {
pr_debug("event with no time\n");
return -1;
}
node->event_time = sample.time;
return 0;
}
static void free_event_nodes(struct list_head *events)
{
struct event_node *node;
while (!list_empty(events)) {
node = list_entry(events->next, struct event_node, list);
list_del_init(&node->list);
free(node);
}
}
static int compar(const void *a, const void *b)
{
const struct event_node *nodea = a;
const struct event_node *nodeb = b;
s64 cmp = nodea->event_time - nodeb->event_time;
return cmp;
}
static int process_events(struct evlist *evlist,
struct switch_tracking *switch_tracking)
{
union perf_event *event;
unsigned pos, cnt = 0;
LIST_HEAD(events);
struct event_node *events_array, *node;
struct mmap *md;
int i, ret;
for (i = 0; i < evlist->core.nr_mmaps; i++) {
md = &evlist->mmap[i];
if (perf_mmap__read_init(&md->core) < 0)
continue;
while ((event = perf_mmap__read_event(&md->core)) != NULL) {
cnt += 1;
ret = add_event(evlist, &events, event);
perf_mmap__consume(&md->core);
if (ret < 0)
goto out_free_nodes;
}
perf_mmap__read_done(&md->core);
}
events_array = calloc(cnt, sizeof(struct event_node));
if (!events_array) {
pr_debug("calloc failed\n");
ret = -1;
goto out_free_nodes;
}
pos = 0;
list_for_each_entry(node, &events, list)
events_array[pos++] = *node;
qsort(events_array, cnt, sizeof(struct event_node), compar);
for (pos = 0; pos < cnt; pos++) {
ret = process_event(evlist, events_array[pos].event,
switch_tracking);
if (ret < 0)
goto out_free;
}
ret = 0;
out_free:
pr_debug("%u events recorded\n", cnt);
free(events_array);
out_free_nodes:
free_event_nodes(&events);
return ret;
}
/**
* test__switch_tracking - test using sched_switch and tracking events.
*
* This function implements a test that checks that sched_switch events and
* tracking events can be recorded for a workload (current process) using the
* evsel->core.system_wide and evsel->tracking flags (respectively) with other events
* sometimes enabled or disabled.
*/
static int test__switch_tracking(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
const char *sched_switch = "sched:sched_switch";
const char *cycles = "cycles:u";
struct switch_tracking switch_tracking = { .tids = NULL, };
struct record_opts opts = {
.mmap_pages = UINT_MAX,
.user_freq = UINT_MAX,
.user_interval = ULLONG_MAX,
.freq = 4000,
.target = {
.uses_mmap = true,
},
};
struct perf_thread_map *threads = NULL;
struct perf_cpu_map *cpus = NULL;
struct evlist *evlist = NULL;
struct evsel *evsel, *cpu_clocks_evsel, *cycles_evsel;
struct evsel *switch_evsel, *tracking_evsel;
const char *comm;
int err = -1;
threads = thread_map__new(-1, getpid(), UINT_MAX);
if (!threads) {
pr_debug("thread_map__new failed!\n");
goto out_err;
}
cpus = perf_cpu_map__new(NULL);
if (!cpus) {
pr_debug("perf_cpu_map__new failed!\n");
goto out_err;
}
evlist = evlist__new();
if (!evlist) {
pr_debug("evlist__new failed!\n");
goto out_err;
}
perf_evlist__set_maps(&evlist->core, cpus, threads);
/* First event */
err = parse_event(evlist, "cpu-clock:u");
if (err) {
pr_debug("Failed to parse event dummy:u\n");
goto out_err;
}
cpu_clocks_evsel = evlist__last(evlist);
/* Second event */
err = parse_event(evlist, cycles);
if (err) {
pr_debug("Failed to parse event %s\n", cycles);
goto out_err;
}
cycles_evsel = evlist__last(evlist);
/* Third event */
if (!evlist__can_select_event(evlist, sched_switch)) {
pr_debug("No sched_switch\n");
err = 0;
goto out;
}
switch_evsel = evlist__add_sched_switch(evlist, true);
if (IS_ERR(switch_evsel)) {
err = PTR_ERR(switch_evsel);
pr_debug("Failed to create event %s\n", sched_switch);
goto out_err;
}
switch_evsel->immediate = true;
/* Test moving an event to the front */
if (cycles_evsel == evlist__first(evlist)) {
pr_debug("cycles event already at front");
goto out_err;
}
evlist__to_front(evlist, cycles_evsel);
if (cycles_evsel != evlist__first(evlist)) {
pr_debug("Failed to move cycles event to front");
goto out_err;
}
evsel__set_sample_bit(cycles_evsel, CPU);
evsel__set_sample_bit(cycles_evsel, TIME);
/* Fourth event */
err = parse_event(evlist, "dummy:u");
if (err) {
pr_debug("Failed to parse event dummy:u\n");
goto out_err;
}
tracking_evsel = evlist__last(evlist);
evlist__set_tracking_event(evlist, tracking_evsel);
tracking_evsel->core.attr.freq = 0;
tracking_evsel->core.attr.sample_period = 1;
evsel__set_sample_bit(tracking_evsel, TIME);
/* Config events */
evlist__config(evlist, &opts, NULL);
/* Check moved event is still at the front */
if (cycles_evsel != evlist__first(evlist)) {
pr_debug("Front event no longer at front");
goto out_err;
}
/* Check tracking event is tracking */
if (!tracking_evsel->core.attr.mmap || !tracking_evsel->core.attr.comm) {
pr_debug("Tracking event not tracking\n");
goto out_err;
}
/* Check non-tracking events are not tracking */
evlist__for_each_entry(evlist, evsel) {
if (evsel != tracking_evsel) {
if (evsel->core.attr.mmap || evsel->core.attr.comm) {
pr_debug("Non-tracking event is tracking\n");
goto out_err;
}
}
}
if (evlist__open(evlist) < 0) {
pr_debug("Not supported\n");
err = 0;
goto out;
}
err = evlist__mmap(evlist, UINT_MAX);
if (err) {
pr_debug("evlist__mmap failed!\n");
goto out_err;
}
evlist__enable(evlist);
err = evsel__disable(cpu_clocks_evsel);
if (err) {
pr_debug("perf_evlist__disable_event failed!\n");
goto out_err;
}
err = spin_sleep();
if (err) {
pr_debug("spin_sleep failed!\n");
goto out_err;
}
comm = "Test COMM 1";
err = prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0);
if (err) {
pr_debug("PR_SET_NAME failed!\n");
goto out_err;
}
err = evsel__disable(cycles_evsel);
if (err) {
pr_debug("perf_evlist__disable_event failed!\n");
goto out_err;
}
comm = "Test COMM 2";
err = prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0);
if (err) {
pr_debug("PR_SET_NAME failed!\n");
goto out_err;
}
err = spin_sleep();
if (err) {
pr_debug("spin_sleep failed!\n");
goto out_err;
}
comm = "Test COMM 3";
err = prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0);
if (err) {
pr_debug("PR_SET_NAME failed!\n");
goto out_err;
}
err = evsel__enable(cycles_evsel);
if (err) {
pr_debug("perf_evlist__disable_event failed!\n");
goto out_err;
}
comm = "Test COMM 4";
err = prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0);
if (err) {
pr_debug("PR_SET_NAME failed!\n");
goto out_err;
}
err = spin_sleep();
if (err) {
pr_debug("spin_sleep failed!\n");
goto out_err;
}
evlist__disable(evlist);
switch_tracking.switch_evsel = switch_evsel;
switch_tracking.cycles_evsel = cycles_evsel;
err = process_events(evlist, &switch_tracking);
zfree(&switch_tracking.tids);
if (err)
goto out_err;
/* Check all 4 comm events were seen i.e. that evsel->tracking works */
if (!switch_tracking.comm_seen[0] || !switch_tracking.comm_seen[1] ||
!switch_tracking.comm_seen[2] || !switch_tracking.comm_seen[3]) {
pr_debug("Missing comm events\n");
goto out_err;
}
/* Check cycles event got enabled */
if (!switch_tracking.cycles_before_comm_1) {
pr_debug("Missing cycles events\n");
goto out_err;
}
/* Check cycles event got disabled */
if (switch_tracking.cycles_between_comm_2_and_comm_3) {
pr_debug("cycles events even though event was disabled\n");
goto out_err;
}
/* Check cycles event got enabled again */
if (!switch_tracking.cycles_after_comm_4) {
pr_debug("Missing cycles events\n");
goto out_err;
}
out:
if (evlist) {
evlist__disable(evlist);
evlist__delete(evlist);
}
perf_cpu_map__put(cpus);
perf_thread_map__put(threads);
return err;
out_err:
err = -1;
goto out;
}
DEFINE_SUITE("Track with sched_switch", switch_tracking);
| linux-master | tools/perf/tests/switch-tracking.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Basic test for sigtrap support.
*
* Copyright (C) 2021, Google LLC.
*/
#include <errno.h>
#include <stdint.h>
#include <stdlib.h>
#include <linux/hw_breakpoint.h>
#include <linux/string.h>
#include <pthread.h>
#include <signal.h>
#include <sys/ioctl.h>
#include <sys/syscall.h>
#include <unistd.h>
#include "cloexec.h"
#include "debug.h"
#include "event.h"
#include "tests.h"
#include "../perf-sys.h"
#define NUM_THREADS 5
static struct {
int tids_want_signal; /* Which threads still want a signal. */
int signal_count; /* Sanity check number of signals received. */
volatile int iterate_on; /* Variable to set breakpoint on. */
siginfo_t first_siginfo; /* First observed siginfo_t. */
} ctx;
#define TEST_SIG_DATA (~(unsigned long)(&ctx.iterate_on))
static struct perf_event_attr make_event_attr(void)
{
struct perf_event_attr attr = {
.type = PERF_TYPE_BREAKPOINT,
.size = sizeof(attr),
.sample_period = 1,
.disabled = 1,
.bp_addr = (unsigned long)&ctx.iterate_on,
.bp_type = HW_BREAKPOINT_RW,
.bp_len = HW_BREAKPOINT_LEN_1,
.inherit = 1, /* Children inherit events ... */
.inherit_thread = 1, /* ... but only cloned with CLONE_THREAD. */
.remove_on_exec = 1, /* Required by sigtrap. */
.sigtrap = 1, /* Request synchronous SIGTRAP on event. */
.sig_data = TEST_SIG_DATA,
.exclude_kernel = 1, /* To allow */
.exclude_hv = 1, /* running as !root */
};
return attr;
}
#ifdef HAVE_BPF_SKEL
#include <bpf/btf.h>
static bool attr_has_sigtrap(void)
{
bool ret = false;
struct btf *btf;
const struct btf_type *t;
const struct btf_member *m;
const char *name;
int i, id;
btf = btf__load_vmlinux_btf();
if (btf == NULL) {
/* should be an old kernel */
return false;
}
id = btf__find_by_name_kind(btf, "perf_event_attr", BTF_KIND_STRUCT);
if (id < 0)
goto out;
t = btf__type_by_id(btf, id);
for (i = 0, m = btf_members(t); i < btf_vlen(t); i++, m++) {
name = btf__name_by_offset(btf, m->name_off);
if (!strcmp(name, "sigtrap")) {
ret = true;
break;
}
}
out:
btf__free(btf);
return ret;
}
#else /* !HAVE_BPF_SKEL */
static bool attr_has_sigtrap(void)
{
struct perf_event_attr attr = {
.type = PERF_TYPE_SOFTWARE,
.config = PERF_COUNT_SW_DUMMY,
.size = sizeof(attr),
.remove_on_exec = 1, /* Required by sigtrap. */
.sigtrap = 1, /* Request synchronous SIGTRAP on event. */
};
int fd;
bool ret = false;
fd = sys_perf_event_open(&attr, 0, -1, -1, perf_event_open_cloexec_flag());
if (fd >= 0) {
ret = true;
close(fd);
}
return ret;
}
#endif /* HAVE_BPF_SKEL */
static void
sigtrap_handler(int signum __maybe_unused, siginfo_t *info, void *ucontext __maybe_unused)
{
if (!__atomic_fetch_add(&ctx.signal_count, 1, __ATOMIC_RELAXED))
ctx.first_siginfo = *info;
__atomic_fetch_sub(&ctx.tids_want_signal, syscall(SYS_gettid), __ATOMIC_RELAXED);
}
static void *test_thread(void *arg)
{
pthread_barrier_t *barrier = (pthread_barrier_t *)arg;
pid_t tid = syscall(SYS_gettid);
int i;
pthread_barrier_wait(barrier);
__atomic_fetch_add(&ctx.tids_want_signal, tid, __ATOMIC_RELAXED);
for (i = 0; i < ctx.iterate_on - 1; i++)
__atomic_fetch_add(&ctx.tids_want_signal, tid, __ATOMIC_RELAXED);
return NULL;
}
static int run_test_threads(pthread_t *threads, pthread_barrier_t *barrier)
{
int i;
pthread_barrier_wait(barrier);
for (i = 0; i < NUM_THREADS; i++)
TEST_ASSERT_EQUAL("pthread_join() failed", pthread_join(threads[i], NULL), 0);
return TEST_OK;
}
static int run_stress_test(int fd, pthread_t *threads, pthread_barrier_t *barrier)
{
int ret;
ctx.iterate_on = 3000;
TEST_ASSERT_EQUAL("misfired signal?", ctx.signal_count, 0);
TEST_ASSERT_EQUAL("enable failed", ioctl(fd, PERF_EVENT_IOC_ENABLE, 0), 0);
ret = run_test_threads(threads, barrier);
TEST_ASSERT_EQUAL("disable failed", ioctl(fd, PERF_EVENT_IOC_DISABLE, 0), 0);
TEST_ASSERT_EQUAL("unexpected sigtraps", ctx.signal_count, NUM_THREADS * ctx.iterate_on);
TEST_ASSERT_EQUAL("missing signals or incorrectly delivered", ctx.tids_want_signal, 0);
TEST_ASSERT_VAL("unexpected si_addr", ctx.first_siginfo.si_addr == &ctx.iterate_on);
#if 0 /* FIXME: enable when libc's signal.h has si_perf_{type,data} */
TEST_ASSERT_EQUAL("unexpected si_perf_type", ctx.first_siginfo.si_perf_type,
PERF_TYPE_BREAKPOINT);
TEST_ASSERT_EQUAL("unexpected si_perf_data", ctx.first_siginfo.si_perf_data,
TEST_SIG_DATA);
#endif
return ret;
}
static int test__sigtrap(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_event_attr attr = make_event_attr();
struct sigaction action = {};
struct sigaction oldact;
pthread_t threads[NUM_THREADS];
pthread_barrier_t barrier;
char sbuf[STRERR_BUFSIZE];
int i, fd, ret = TEST_FAIL;
if (!BP_SIGNAL_IS_SUPPORTED) {
pr_debug("Test not supported on this architecture");
return TEST_SKIP;
}
pthread_barrier_init(&barrier, NULL, NUM_THREADS + 1);
action.sa_flags = SA_SIGINFO | SA_NODEFER;
action.sa_sigaction = sigtrap_handler;
sigemptyset(&action.sa_mask);
if (sigaction(SIGTRAP, &action, &oldact)) {
pr_debug("FAILED sigaction(): %s\n", str_error_r(errno, sbuf, sizeof(sbuf)));
goto out;
}
fd = sys_perf_event_open(&attr, 0, -1, -1, perf_event_open_cloexec_flag());
if (fd < 0) {
if (attr_has_sigtrap()) {
pr_debug("FAILED sys_perf_event_open(): %s\n",
str_error_r(errno, sbuf, sizeof(sbuf)));
} else {
pr_debug("perf_event_attr doesn't have sigtrap\n");
ret = TEST_SKIP;
}
goto out_restore_sigaction;
}
for (i = 0; i < NUM_THREADS; i++) {
if (pthread_create(&threads[i], NULL, test_thread, &barrier)) {
pr_debug("FAILED pthread_create(): %s\n", str_error_r(errno, sbuf, sizeof(sbuf)));
goto out_close_perf_event;
}
}
ret = run_stress_test(fd, threads, &barrier);
out_close_perf_event:
close(fd);
out_restore_sigaction:
sigaction(SIGTRAP, &oldact, NULL);
out:
pthread_barrier_destroy(&barrier);
return ret;
}
DEFINE_SUITE("Sigtrap", sigtrap);
| linux-master | tools/perf/tests/sigtrap.c |
// SPDX-License-Identifier: GPL-2.0
#include "tests.h"
#include "debug.h"
#include "symbol.h"
#include "sort.h"
#include "evsel.h"
#include "evlist.h"
#include "machine.h"
#include "map.h"
#include "parse-events.h"
#include "thread.h"
#include "hists_common.h"
#include "util/mmap.h"
#include <errno.h>
#include <linux/kernel.h>
struct sample {
u32 pid;
u64 ip;
struct thread *thread;
struct map *map;
struct symbol *sym;
};
/* For the numbers, see hists_common.c */
static struct sample fake_common_samples[] = {
/* perf [kernel] schedule() */
{ .pid = FAKE_PID_PERF1, .ip = FAKE_IP_KERNEL_SCHEDULE, },
/* perf [perf] main() */
{ .pid = FAKE_PID_PERF2, .ip = FAKE_IP_PERF_MAIN, },
/* perf [perf] cmd_record() */
{ .pid = FAKE_PID_PERF2, .ip = FAKE_IP_PERF_CMD_RECORD, },
/* bash [bash] xmalloc() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_BASH_XMALLOC, },
/* bash [libc] malloc() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_LIBC_MALLOC, },
};
static struct sample fake_samples[][5] = {
{
/* perf [perf] run_command() */
{ .pid = FAKE_PID_PERF1, .ip = FAKE_IP_PERF_RUN_COMMAND, },
/* perf [libc] malloc() */
{ .pid = FAKE_PID_PERF1, .ip = FAKE_IP_LIBC_MALLOC, },
/* perf [kernel] page_fault() */
{ .pid = FAKE_PID_PERF1, .ip = FAKE_IP_KERNEL_PAGE_FAULT, },
/* perf [kernel] sys_perf_event_open() */
{ .pid = FAKE_PID_PERF2, .ip = FAKE_IP_KERNEL_SYS_PERF_EVENT_OPEN, },
/* bash [libc] free() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_LIBC_FREE, },
},
{
/* perf [libc] free() */
{ .pid = FAKE_PID_PERF2, .ip = FAKE_IP_LIBC_FREE, },
/* bash [libc] malloc() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_LIBC_MALLOC, }, /* will be merged */
/* bash [bash] xfee() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_BASH_XFREE, },
/* bash [libc] realloc() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_LIBC_REALLOC, },
/* bash [kernel] page_fault() */
{ .pid = FAKE_PID_BASH, .ip = FAKE_IP_KERNEL_PAGE_FAULT, },
},
};
static int add_hist_entries(struct evlist *evlist, struct machine *machine)
{
struct evsel *evsel;
struct addr_location al;
struct hist_entry *he;
struct perf_sample sample = { .period = 1, .weight = 1, };
size_t i = 0, k;
addr_location__init(&al);
/*
* each evsel will have 10 samples - 5 common and 5 distinct.
* However the second evsel also has a collapsed entry for
* "bash [libc] malloc" so total 9 entries will be in the tree.
*/
evlist__for_each_entry(evlist, evsel) {
struct hists *hists = evsel__hists(evsel);
for (k = 0; k < ARRAY_SIZE(fake_common_samples); k++) {
sample.cpumode = PERF_RECORD_MISC_USER;
sample.pid = fake_common_samples[k].pid;
sample.tid = fake_common_samples[k].pid;
sample.ip = fake_common_samples[k].ip;
if (machine__resolve(machine, &al, &sample) < 0)
goto out;
he = hists__add_entry(hists, &al, NULL,
NULL, NULL, NULL, &sample, true);
if (he == NULL) {
goto out;
}
thread__put(fake_common_samples[k].thread);
fake_common_samples[k].thread = thread__get(al.thread);
map__put(fake_common_samples[k].map);
fake_common_samples[k].map = map__get(al.map);
fake_common_samples[k].sym = al.sym;
}
for (k = 0; k < ARRAY_SIZE(fake_samples[i]); k++) {
sample.pid = fake_samples[i][k].pid;
sample.tid = fake_samples[i][k].pid;
sample.ip = fake_samples[i][k].ip;
if (machine__resolve(machine, &al, &sample) < 0)
goto out;
he = hists__add_entry(hists, &al, NULL,
NULL, NULL, NULL, &sample, true);
if (he == NULL) {
goto out;
}
thread__put(fake_samples[i][k].thread);
fake_samples[i][k].thread = thread__get(al.thread);
map__put(fake_samples[i][k].map);
fake_samples[i][k].map = map__get(al.map);
fake_samples[i][k].sym = al.sym;
}
i++;
}
addr_location__exit(&al);
return 0;
out:
addr_location__exit(&al);
pr_debug("Not enough memory for adding a hist entry\n");
return -1;
}
static void put_fake_samples(void)
{
size_t i, j;
for (i = 0; i < ARRAY_SIZE(fake_common_samples); i++)
map__put(fake_common_samples[i].map);
for (i = 0; i < ARRAY_SIZE(fake_samples); i++) {
for (j = 0; j < ARRAY_SIZE(fake_samples[0]); j++)
map__put(fake_samples[i][j].map);
}
}
static int find_sample(struct sample *samples, size_t nr_samples,
struct thread *t, struct map *m, struct symbol *s)
{
while (nr_samples--) {
if (RC_CHK_ACCESS(samples->thread) == RC_CHK_ACCESS(t) &&
RC_CHK_ACCESS(samples->map) == RC_CHK_ACCESS(m) &&
samples->sym == s)
return 1;
samples++;
}
return 0;
}
static int __validate_match(struct hists *hists)
{
size_t count = 0;
struct rb_root_cached *root;
struct rb_node *node;
/*
* Only entries from fake_common_samples should have a pair.
*/
if (hists__has(hists, need_collapse))
root = &hists->entries_collapsed;
else
root = hists->entries_in;
node = rb_first_cached(root);
while (node) {
struct hist_entry *he;
he = rb_entry(node, struct hist_entry, rb_node_in);
if (hist_entry__has_pairs(he)) {
if (find_sample(fake_common_samples,
ARRAY_SIZE(fake_common_samples),
he->thread, he->ms.map, he->ms.sym)) {
count++;
} else {
pr_debug("Can't find the matched entry\n");
return -1;
}
}
node = rb_next(node);
}
if (count != ARRAY_SIZE(fake_common_samples)) {
pr_debug("Invalid count for matched entries: %zd of %zd\n",
count, ARRAY_SIZE(fake_common_samples));
return -1;
}
return 0;
}
static int validate_match(struct hists *leader, struct hists *other)
{
return __validate_match(leader) || __validate_match(other);
}
static int __validate_link(struct hists *hists, int idx)
{
size_t count = 0;
size_t count_pair = 0;
size_t count_dummy = 0;
struct rb_root_cached *root;
struct rb_node *node;
/*
* Leader hists (idx = 0) will have dummy entries from other,
* and some entries will have no pair. However every entry
* in other hists should have (dummy) pair.
*/
if (hists__has(hists, need_collapse))
root = &hists->entries_collapsed;
else
root = hists->entries_in;
node = rb_first_cached(root);
while (node) {
struct hist_entry *he;
he = rb_entry(node, struct hist_entry, rb_node_in);
if (hist_entry__has_pairs(he)) {
if (!find_sample(fake_common_samples,
ARRAY_SIZE(fake_common_samples),
he->thread, he->ms.map, he->ms.sym) &&
!find_sample(fake_samples[idx],
ARRAY_SIZE(fake_samples[idx]),
he->thread, he->ms.map, he->ms.sym)) {
count_dummy++;
}
count_pair++;
} else if (idx) {
pr_debug("A entry from the other hists should have pair\n");
return -1;
}
count++;
node = rb_next(node);
}
/*
* Note that we have a entry collapsed in the other (idx = 1) hists.
*/
if (idx == 0) {
if (count_dummy != ARRAY_SIZE(fake_samples[1]) - 1) {
pr_debug("Invalid count of dummy entries: %zd of %zd\n",
count_dummy, ARRAY_SIZE(fake_samples[1]) - 1);
return -1;
}
if (count != count_pair + ARRAY_SIZE(fake_samples[0])) {
pr_debug("Invalid count of total leader entries: %zd of %zd\n",
count, count_pair + ARRAY_SIZE(fake_samples[0]));
return -1;
}
} else {
if (count != count_pair) {
pr_debug("Invalid count of total other entries: %zd of %zd\n",
count, count_pair);
return -1;
}
if (count_dummy > 0) {
pr_debug("Other hists should not have dummy entries: %zd\n",
count_dummy);
return -1;
}
}
return 0;
}
static int validate_link(struct hists *leader, struct hists *other)
{
return __validate_link(leader, 0) || __validate_link(other, 1);
}
static int test__hists_link(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int err = -1;
struct hists *hists, *first_hists;
struct machines machines;
struct machine *machine = NULL;
struct evsel *evsel, *first;
struct evlist *evlist = evlist__new();
if (evlist == NULL)
return -ENOMEM;
err = parse_event(evlist, "cpu-clock");
if (err)
goto out;
err = parse_event(evlist, "task-clock");
if (err)
goto out;
err = TEST_FAIL;
/* default sort order (comm,dso,sym) will be used */
if (setup_sorting(NULL) < 0)
goto out;
machines__init(&machines);
/* setup threads/dso/map/symbols also */
machine = setup_fake_machine(&machines);
if (!machine)
goto out;
if (verbose > 1)
machine__fprintf(machine, stderr);
/* process sample events */
err = add_hist_entries(evlist, machine);
if (err < 0)
goto out;
evlist__for_each_entry(evlist, evsel) {
hists = evsel__hists(evsel);
hists__collapse_resort(hists, NULL);
if (verbose > 2)
print_hists_in(hists);
}
first = evlist__first(evlist);
evsel = evlist__last(evlist);
first_hists = evsel__hists(first);
hists = evsel__hists(evsel);
/* match common entries */
hists__match(first_hists, hists);
err = validate_match(first_hists, hists);
if (err)
goto out;
/* link common and/or dummy entries */
hists__link(first_hists, hists);
err = validate_link(first_hists, hists);
if (err)
goto out;
err = 0;
out:
/* tear down everything */
evlist__delete(evlist);
reset_output_field();
machines__exit(&machines);
put_fake_samples();
return err;
}
DEFINE_SUITE("Match and link multiple hists", hists_link);
| linux-master | tools/perf/tests/hists_link.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
#include <linux/kernel.h>
#include "tests.h"
#include "debug.h"
#include "print_binary.h"
static int test__is_printable_array(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
char buf1[] = { 'k', 'r', 4, 'v', 'a', 0 };
char buf2[] = { 'k', 'r', 'a', 'v', 4, 0 };
struct {
char *buf;
unsigned int len;
int ret;
} t[] = {
{ (char *) "krava", sizeof("krava"), 1 },
{ (char *) "krava", sizeof("krava") - 1, 0 },
{ (char *) "", sizeof(""), 1 },
{ (char *) "", 0, 0 },
{ NULL, 0, 0 },
{ buf1, sizeof(buf1), 0 },
{ buf2, sizeof(buf2), 0 },
};
unsigned int i;
for (i = 0; i < ARRAY_SIZE(t); i++) {
int ret;
ret = is_printable_array((char *) t[i].buf, t[i].len);
if (ret != t[i].ret) {
pr_err("failed: test %u\n", i);
return TEST_FAIL;
}
}
return TEST_OK;
}
DEFINE_SUITE("is_printable_array", is_printable_array);
| linux-master | tools/perf/tests/is_printable_array.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Test backward bit in event attribute, read ring buffer from end to
* beginning
*/
#include <evlist.h>
#include <sys/prctl.h>
#include "record.h"
#include "tests.h"
#include "debug.h"
#include "parse-events.h"
#include "util/mmap.h"
#include <errno.h>
#include <linux/string.h>
#include <perf/mmap.h>
#define NR_ITERS 111
static void testcase(void)
{
int i;
for (i = 0; i < NR_ITERS; i++) {
char proc_name[15];
snprintf(proc_name, sizeof(proc_name), "p:%d\n", i);
prctl(PR_SET_NAME, proc_name);
}
}
static int count_samples(struct evlist *evlist, int *sample_count,
int *comm_count)
{
int i;
for (i = 0; i < evlist->core.nr_mmaps; i++) {
struct mmap *map = &evlist->overwrite_mmap[i];
union perf_event *event;
perf_mmap__read_init(&map->core);
while ((event = perf_mmap__read_event(&map->core)) != NULL) {
const u32 type = event->header.type;
switch (type) {
case PERF_RECORD_SAMPLE:
(*sample_count)++;
break;
case PERF_RECORD_COMM:
(*comm_count)++;
break;
default:
pr_err("Unexpected record of type %d\n", type);
return TEST_FAIL;
}
}
perf_mmap__read_done(&map->core);
}
return TEST_OK;
}
static int do_test(struct evlist *evlist, int mmap_pages,
int *sample_count, int *comm_count)
{
int err;
char sbuf[STRERR_BUFSIZE];
err = evlist__mmap(evlist, mmap_pages);
if (err < 0) {
pr_debug("evlist__mmap: %s\n",
str_error_r(errno, sbuf, sizeof(sbuf)));
return TEST_FAIL;
}
evlist__enable(evlist);
testcase();
evlist__disable(evlist);
err = count_samples(evlist, sample_count, comm_count);
evlist__munmap(evlist);
return err;
}
static int test__backward_ring_buffer(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int ret = TEST_SKIP, err, sample_count = 0, comm_count = 0;
char pid[16], sbuf[STRERR_BUFSIZE];
struct evlist *evlist;
struct evsel *evsel __maybe_unused;
struct parse_events_error parse_error;
struct record_opts opts = {
.target = {
.uid = UINT_MAX,
.uses_mmap = true,
},
.freq = 0,
.mmap_pages = 256,
.default_interval = 1,
};
snprintf(pid, sizeof(pid), "%d", getpid());
pid[sizeof(pid) - 1] = '\0';
opts.target.tid = opts.target.pid = pid;
evlist = evlist__new();
if (!evlist) {
pr_debug("Not enough memory to create evlist\n");
return TEST_FAIL;
}
err = evlist__create_maps(evlist, &opts.target);
if (err < 0) {
pr_debug("Not enough memory to create thread/cpu maps\n");
goto out_delete_evlist;
}
parse_events_error__init(&parse_error);
/*
* Set backward bit, ring buffer should be writing from end. Record
* it in aux evlist
*/
err = parse_events(evlist, "syscalls:sys_enter_prctl/overwrite/", &parse_error);
parse_events_error__exit(&parse_error);
if (err) {
pr_debug("Failed to parse tracepoint event, try use root\n");
ret = TEST_SKIP;
goto out_delete_evlist;
}
evlist__config(evlist, &opts, NULL);
err = evlist__open(evlist);
if (err < 0) {
pr_debug("perf_evlist__open: %s\n",
str_error_r(errno, sbuf, sizeof(sbuf)));
goto out_delete_evlist;
}
ret = TEST_FAIL;
err = do_test(evlist, opts.mmap_pages, &sample_count,
&comm_count);
if (err != TEST_OK)
goto out_delete_evlist;
if ((sample_count != NR_ITERS) || (comm_count != NR_ITERS)) {
pr_err("Unexpected counter: sample_count=%d, comm_count=%d\n",
sample_count, comm_count);
goto out_delete_evlist;
}
evlist__close(evlist);
err = evlist__open(evlist);
if (err < 0) {
pr_debug("perf_evlist__open: %s\n",
str_error_r(errno, sbuf, sizeof(sbuf)));
goto out_delete_evlist;
}
err = do_test(evlist, 1, &sample_count, &comm_count);
if (err != TEST_OK)
goto out_delete_evlist;
ret = TEST_OK;
out_delete_evlist:
evlist__delete(evlist);
return ret;
}
DEFINE_SUITE("Read backward ring buffer", backward_ring_buffer);
| linux-master | tools/perf/tests/backward-ring-buffer.c |
#include <linux/kernel.h>
#include <linux/types.h>
#include <stddef.h>
#include "tests.h"
#include "event.h"
#include "evlist.h"
#include "header.h"
#include "debug.h"
#include "util/sample.h"
static int process_event(struct evlist **pevlist, union perf_event *event)
{
struct perf_sample sample;
if (event->header.type == PERF_RECORD_HEADER_ATTR) {
if (perf_event__process_attr(NULL, event, pevlist)) {
pr_debug("perf_event__process_attr failed\n");
return -1;
}
return 0;
}
if (event->header.type >= PERF_RECORD_USER_TYPE_START)
return -1;
if (!*pevlist)
return -1;
if (evlist__parse_sample(*pevlist, event, &sample)) {
pr_debug("evlist__parse_sample failed\n");
return -1;
}
return 0;
}
static int process_events(union perf_event **events, size_t count)
{
struct evlist *evlist = NULL;
int err = 0;
size_t i;
for (i = 0; i < count && !err; i++)
err = process_event(&evlist, events[i]);
evlist__delete(evlist);
return err;
}
struct test_attr_event {
struct perf_event_header header;
struct perf_event_attr attr;
u64 id;
};
/**
* test__parse_no_sample_id_all - test parsing with no sample_id_all bit set.
*
* This function tests parsing data produced on kernel's that do not support the
* sample_id_all bit. Without the sample_id_all bit, non-sample events (such as
* mmap events) do not have an id sample appended, and consequently logic
* designed to determine the id will not work. That case happens when there is
* more than one selected event, so this test processes three events: 2
* attributes representing the selected events and one mmap event.
*
* Return: %0 on success, %-1 if the test fails.
*/
static int test__parse_no_sample_id_all(struct test_suite *test __maybe_unused,
int subtest __maybe_unused)
{
int err;
struct test_attr_event event1 = {
.header = {
.type = PERF_RECORD_HEADER_ATTR,
.size = sizeof(struct test_attr_event),
},
.id = 1,
};
struct test_attr_event event2 = {
.header = {
.type = PERF_RECORD_HEADER_ATTR,
.size = sizeof(struct test_attr_event),
},
.id = 2,
};
struct perf_record_mmap event3 = {
.header = {
.type = PERF_RECORD_MMAP,
.size = sizeof(struct perf_record_mmap),
},
};
union perf_event *events[] = {
(union perf_event *)&event1,
(union perf_event *)&event2,
(union perf_event *)&event3,
};
err = process_events(events, ARRAY_SIZE(events));
if (err)
return -1;
return 0;
}
DEFINE_SUITE("Parse with no sample_id_all bit set", parse_no_sample_id_all);
| linux-master | tools/perf/tests/parse-no-sample-id-all.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include <inttypes.h>
/* For the CPU_* macros */
#include <sched.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <api/fs/fs.h>
#include <linux/err.h>
#include <linux/string.h>
#include <api/fs/tracing_path.h>
#include "evsel.h"
#include "tests.h"
#include "thread_map.h"
#include <perf/cpumap.h>
#include "debug.h"
#include "stat.h"
#include "util/counts.h"
static int test__openat_syscall_event_on_all_cpus(struct test_suite *test __maybe_unused,
int subtest __maybe_unused)
{
int err = TEST_FAIL, fd, idx;
struct perf_cpu cpu;
struct perf_cpu_map *cpus;
struct evsel *evsel;
unsigned int nr_openat_calls = 111, i;
cpu_set_t cpu_set;
struct perf_thread_map *threads = thread_map__new(-1, getpid(), UINT_MAX);
char sbuf[STRERR_BUFSIZE];
char errbuf[BUFSIZ];
if (threads == NULL) {
pr_debug("thread_map__new\n");
return -1;
}
cpus = perf_cpu_map__new(NULL);
if (cpus == NULL) {
pr_debug("perf_cpu_map__new\n");
goto out_thread_map_delete;
}
CPU_ZERO(&cpu_set);
evsel = evsel__newtp("syscalls", "sys_enter_openat");
if (IS_ERR(evsel)) {
tracing_path__strerror_open_tp(errno, errbuf, sizeof(errbuf), "syscalls", "sys_enter_openat");
pr_debug("%s\n", errbuf);
err = TEST_SKIP;
goto out_cpu_map_delete;
}
if (evsel__open(evsel, cpus, threads) < 0) {
pr_debug("failed to open counter: %s, "
"tweak /proc/sys/kernel/perf_event_paranoid?\n",
str_error_r(errno, sbuf, sizeof(sbuf)));
err = TEST_SKIP;
goto out_evsel_delete;
}
perf_cpu_map__for_each_cpu(cpu, idx, cpus) {
unsigned int ncalls = nr_openat_calls + idx;
/*
* XXX eventually lift this restriction in a way that
* keeps perf building on older glibc installations
* without CPU_ALLOC. 1024 cpus in 2010 still seems
* a reasonable upper limit tho :-)
*/
if (cpu.cpu >= CPU_SETSIZE) {
pr_debug("Ignoring CPU %d\n", cpu.cpu);
continue;
}
CPU_SET(cpu.cpu, &cpu_set);
if (sched_setaffinity(0, sizeof(cpu_set), &cpu_set) < 0) {
pr_debug("sched_setaffinity() failed on CPU %d: %s ",
cpu.cpu,
str_error_r(errno, sbuf, sizeof(sbuf)));
goto out_close_fd;
}
for (i = 0; i < ncalls; ++i) {
fd = openat(0, "/etc/passwd", O_RDONLY);
close(fd);
}
CPU_CLR(cpu.cpu, &cpu_set);
}
evsel->core.cpus = perf_cpu_map__get(cpus);
err = TEST_OK;
perf_cpu_map__for_each_cpu(cpu, idx, cpus) {
unsigned int expected;
if (cpu.cpu >= CPU_SETSIZE)
continue;
if (evsel__read_on_cpu(evsel, idx, 0) < 0) {
pr_debug("evsel__read_on_cpu\n");
err = TEST_FAIL;
break;
}
expected = nr_openat_calls + idx;
if (perf_counts(evsel->counts, idx, 0)->val != expected) {
pr_debug("evsel__read_on_cpu: expected to intercept %d calls on cpu %d, got %" PRIu64 "\n",
expected, cpu.cpu, perf_counts(evsel->counts, idx, 0)->val);
err = TEST_FAIL;
}
}
evsel__free_counts(evsel);
out_close_fd:
perf_evsel__close_fd(&evsel->core);
out_evsel_delete:
evsel__delete(evsel);
out_cpu_map_delete:
perf_cpu_map__put(cpus);
out_thread_map_delete:
perf_thread_map__put(threads);
return err;
}
static struct test_case tests__openat_syscall_event_on_all_cpus[] = {
TEST_CASE_REASON("Detect openat syscall event on all cpus",
openat_syscall_event_on_all_cpus,
"permissions"),
{ .name = NULL, }
};
struct test_suite suite__openat_syscall_event_on_all_cpus = {
.desc = "Detect openat syscall event on all cpus",
.test_cases = tests__openat_syscall_event_on_all_cpus,
};
| linux-master | tools/perf/tests/openat-syscall-all-cpus.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include <unistd.h>
#include <stdio.h>
#include "linux/perf_event.h"
#include "tests.h"
#include "debug.h"
#include "pmu.h"
#include "pmus.h"
#include "header.h"
#include "../perf-sys.h"
/* hw: cycles, sw: context-switch, uncore: [arch dependent] */
static int types[] = {0, 1, -1};
static unsigned long configs[] = {0, 3, 0};
#define NR_UNCORE_PMUS 5
/* Uncore pmus that support more than 3 counters */
static struct uncore_pmus {
const char *name;
__u64 config;
} uncore_pmus[NR_UNCORE_PMUS] = {
{ "amd_l3", 0x0 },
{ "amd_df", 0x0 },
{ "uncore_imc_0", 0x1 }, /* Intel */
{ "core_imc", 0x318 }, /* PowerPC: core_imc/CPM_STCX_FIN/ */
{ "hv_24x7", 0x22000000003 }, /* PowerPC: hv_24x7/CPM_STCX_FIN/ */
};
static int event_open(int type, unsigned long config, int group_fd)
{
struct perf_event_attr attr;
memset(&attr, 0, sizeof(struct perf_event_attr));
attr.type = type;
attr.size = sizeof(struct perf_event_attr);
attr.config = config;
/*
* When creating an event group, typically the group leader is
* initialized with disabled set to 1 and any child events are
* initialized with disabled set to 0. Despite disabled being 0,
* the child events will not start until the group leader is
* enabled.
*/
attr.disabled = group_fd == -1 ? 1 : 0;
return sys_perf_event_open(&attr, -1, 0, group_fd, 0);
}
static int setup_uncore_event(void)
{
struct perf_pmu *pmu = NULL;
int i, fd;
while ((pmu = perf_pmus__scan(pmu)) != NULL) {
for (i = 0; i < NR_UNCORE_PMUS; i++) {
if (!strcmp(uncore_pmus[i].name, pmu->name)) {
pr_debug("Using %s for uncore pmu event\n", pmu->name);
types[2] = pmu->type;
configs[2] = uncore_pmus[i].config;
/*
* Check if the chosen uncore pmu event can be
* used in the test. For example, incase of accessing
* hv_24x7 pmu counters, partition should have
* additional permissions. If not, event open will
* fail. So check if the event open succeeds
* before proceeding.
*/
fd = event_open(types[2], configs[2], -1);
if (fd < 0)
return -1;
close(fd);
return 0;
}
}
}
return -1;
}
static int run_test(int i, int j, int k)
{
int erroneous = ((((1 << i) | (1 << j) | (1 << k)) & 5) == 5);
int group_fd, sibling_fd1, sibling_fd2;
group_fd = event_open(types[i], configs[i], -1);
if (group_fd == -1)
return -1;
sibling_fd1 = event_open(types[j], configs[j], group_fd);
if (sibling_fd1 == -1) {
close(group_fd);
return erroneous ? 0 : -1;
}
sibling_fd2 = event_open(types[k], configs[k], group_fd);
if (sibling_fd2 == -1) {
close(sibling_fd1);
close(group_fd);
return erroneous ? 0 : -1;
}
close(sibling_fd2);
close(sibling_fd1);
close(group_fd);
return erroneous ? -1 : 0;
}
static int test__event_groups(struct test_suite *text __maybe_unused, int subtest __maybe_unused)
{
int i, j, k;
int ret;
int r;
ret = setup_uncore_event();
if (ret || types[2] == -1)
return TEST_SKIP;
ret = TEST_OK;
for (i = 0; i < 3; i++) {
for (j = 0; j < 3; j++) {
for (k = 0; k < 3; k++) {
r = run_test(i, j, k);
if (r)
ret = TEST_FAIL;
pr_debug("0x%x 0x%lx, 0x%x 0x%lx, 0x%x 0x%lx: %s\n",
types[i], configs[i], types[j], configs[j],
types[k], configs[k], r ? "Fail" : "Pass");
}
}
}
return ret;
}
DEFINE_SUITE("Event groups", event_groups);
| linux-master | tools/perf/tests/event_groups.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
#include <perf/cpumap.h>
#include <string.h>
#include "cpumap.h"
#include "evlist.h"
#include "evsel.h"
#include "header.h"
#include "machine.h"
#include "util/synthetic-events.h"
#include "tool.h"
#include "tests.h"
#include "debug.h"
static int process_event_unit(struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct perf_record_event_update *ev = (struct perf_record_event_update *)event;
TEST_ASSERT_VAL("wrong id", ev->id == 123);
TEST_ASSERT_VAL("wrong id", ev->type == PERF_EVENT_UPDATE__UNIT);
TEST_ASSERT_VAL("wrong unit", !strcmp(ev->unit, "KRAVA"));
return 0;
}
static int process_event_scale(struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct perf_record_event_update *ev = (struct perf_record_event_update *)event;
TEST_ASSERT_VAL("wrong id", ev->id == 123);
TEST_ASSERT_VAL("wrong id", ev->type == PERF_EVENT_UPDATE__SCALE);
TEST_ASSERT_VAL("wrong scale", ev->scale.scale == 0.123);
return 0;
}
struct event_name {
struct perf_tool tool;
const char *name;
};
static int process_event_name(struct perf_tool *tool,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct event_name *tmp = container_of(tool, struct event_name, tool);
struct perf_record_event_update *ev = (struct perf_record_event_update *)event;
TEST_ASSERT_VAL("wrong id", ev->id == 123);
TEST_ASSERT_VAL("wrong id", ev->type == PERF_EVENT_UPDATE__NAME);
TEST_ASSERT_VAL("wrong name", !strcmp(ev->name, tmp->name));
return 0;
}
static int process_event_cpus(struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct perf_record_event_update *ev = (struct perf_record_event_update *)event;
struct perf_cpu_map *map;
map = cpu_map__new_data(&ev->cpus.cpus);
TEST_ASSERT_VAL("wrong id", ev->id == 123);
TEST_ASSERT_VAL("wrong type", ev->type == PERF_EVENT_UPDATE__CPUS);
TEST_ASSERT_VAL("wrong cpus", perf_cpu_map__nr(map) == 3);
TEST_ASSERT_VAL("wrong cpus", perf_cpu_map__cpu(map, 0).cpu == 1);
TEST_ASSERT_VAL("wrong cpus", perf_cpu_map__cpu(map, 1).cpu == 2);
TEST_ASSERT_VAL("wrong cpus", perf_cpu_map__cpu(map, 2).cpu == 3);
perf_cpu_map__put(map);
return 0;
}
static int test__event_update(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct evsel *evsel;
struct event_name tmp;
struct evlist *evlist = evlist__new_default();
TEST_ASSERT_VAL("failed to get evlist", evlist);
evsel = evlist__first(evlist);
TEST_ASSERT_VAL("failed to allocate ids",
!perf_evsel__alloc_id(&evsel->core, 1, 1));
perf_evlist__id_add(&evlist->core, &evsel->core, 0, 0, 123);
free((char *)evsel->unit);
evsel->unit = strdup("KRAVA");
TEST_ASSERT_VAL("failed to synthesize attr update unit",
!perf_event__synthesize_event_update_unit(NULL, evsel, process_event_unit));
evsel->scale = 0.123;
TEST_ASSERT_VAL("failed to synthesize attr update scale",
!perf_event__synthesize_event_update_scale(NULL, evsel, process_event_scale));
tmp.name = evsel__name(evsel);
TEST_ASSERT_VAL("failed to synthesize attr update name",
!perf_event__synthesize_event_update_name(&tmp.tool, evsel, process_event_name));
evsel->core.own_cpus = perf_cpu_map__new("1,2,3");
TEST_ASSERT_VAL("failed to synthesize attr update cpus",
!perf_event__synthesize_event_update_cpus(&tmp.tool, evsel, process_event_cpus));
evlist__delete(evlist);
return 0;
}
DEFINE_SUITE("Synthesize attr update", event_update);
| linux-master | tools/perf/tests/event_update.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include "tests.h"
#include "session.h"
#include "debug.h"
#include "demangle-ocaml.h"
static int test__demangle_ocaml(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int ret = TEST_OK;
char *buf = NULL;
size_t i;
struct {
const char *mangled, *demangled;
} test_cases[] = {
{ "main",
NULL },
{ "camlStdlib__array__map_154",
"Stdlib.array.map_154" },
{ "camlStdlib__anon_fn$5bstdlib$2eml$3a334$2c0$2d$2d54$5d_1453",
"Stdlib.anon_fn[stdlib.ml:334,0--54]_1453" },
{ "camlStdlib__bytes__$2b$2b_2205",
"Stdlib.bytes.++_2205" },
};
for (i = 0; i < ARRAY_SIZE(test_cases); i++) {
buf = ocaml_demangle_sym(test_cases[i].mangled);
if ((buf == NULL && test_cases[i].demangled != NULL)
|| (buf != NULL && test_cases[i].demangled == NULL)
|| (buf != NULL && strcmp(buf, test_cases[i].demangled))) {
pr_debug("FAILED: %s: %s != %s\n", test_cases[i].mangled,
buf == NULL ? "(null)" : buf,
test_cases[i].demangled == NULL ? "(null)" : test_cases[i].demangled);
ret = TEST_FAIL;
}
free(buf);
}
return ret;
}
DEFINE_SUITE("Demangle OCaml", demangle_ocaml);
| linux-master | tools/perf/tests/demangle-ocaml-test.c |
// SPDX-License-Identifier: GPL-2.0
#include <signal.h>
#include <stdlib.h>
#include "tests.h"
#include "debug.h"
#include "perf-hooks.h"
static void sigsegv_handler(int sig __maybe_unused)
{
pr_debug("SIGSEGV is observed as expected, try to recover.\n");
perf_hooks__recover();
signal(SIGSEGV, SIG_DFL);
raise(SIGSEGV);
exit(-1);
}
static void the_hook(void *_hook_flags)
{
int *hook_flags = _hook_flags;
*hook_flags = 1234;
/* Generate a segfault, test perf_hooks__recover */
raise(SIGSEGV);
}
static int test__perf_hooks(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int hook_flags = 0;
signal(SIGSEGV, sigsegv_handler);
perf_hooks__set_hook("test", the_hook, &hook_flags);
perf_hooks__invoke_test();
/* hook is triggered? */
if (hook_flags != 1234) {
pr_debug("Setting failed: %d (%p)\n", hook_flags, &hook_flags);
return TEST_FAIL;
}
/* the buggy hook is removed? */
if (perf_hooks__get_hook("test"))
return TEST_FAIL;
return TEST_OK;
}
DEFINE_SUITE("perf hooks", perf_hooks);
| linux-master | tools/perf/tests/perf-hooks.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Inspired by breakpoint overflow test done by
* Vince Weaver <[email protected]> for perf_event_tests
* (git://github.com/deater/perf_event_tests)
*/
/*
* Powerpc needs __SANE_USERSPACE_TYPES__ before <linux/types.h> to select
* 'int-ll64.h' and avoid compile warnings when printing __u64 with %llu.
*/
#define __SANE_USERSPACE_TYPES__
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <sys/ioctl.h>
#include <time.h>
#include <fcntl.h>
#include <signal.h>
#include <sys/mman.h>
#include <linux/compiler.h>
#include <linux/hw_breakpoint.h>
#include "tests.h"
#include "debug.h"
#include "event.h"
#include "perf-sys.h"
#include "cloexec.h"
static int fd1;
static int fd2;
static int fd3;
static int overflows;
static int overflows_2;
volatile long the_var;
/*
* Use ASM to ensure watchpoint and breakpoint can be triggered
* at one instruction.
*/
#if defined (__x86_64__)
extern void __test_function(volatile long *ptr);
asm (
".pushsection .text;"
".globl __test_function\n"
".type __test_function, @function;"
"__test_function:\n"
"incq (%rdi)\n"
"ret\n"
".popsection\n");
#else
static void __test_function(volatile long *ptr)
{
*ptr = 0x1234;
}
#endif
static noinline int test_function(void)
{
__test_function(&the_var);
the_var++;
return time(NULL);
}
static void sig_handler_2(int signum __maybe_unused,
siginfo_t *oh __maybe_unused,
void *uc __maybe_unused)
{
overflows_2++;
if (overflows_2 > 10) {
ioctl(fd1, PERF_EVENT_IOC_DISABLE, 0);
ioctl(fd2, PERF_EVENT_IOC_DISABLE, 0);
ioctl(fd3, PERF_EVENT_IOC_DISABLE, 0);
}
}
static void sig_handler(int signum __maybe_unused,
siginfo_t *oh __maybe_unused,
void *uc __maybe_unused)
{
overflows++;
if (overflows > 10) {
/*
* This should be executed only once during
* this test, if we are here for the 10th
* time, consider this the recursive issue.
*
* We can get out of here by disable events,
* so no new SIGIO is delivered.
*/
ioctl(fd1, PERF_EVENT_IOC_DISABLE, 0);
ioctl(fd2, PERF_EVENT_IOC_DISABLE, 0);
ioctl(fd3, PERF_EVENT_IOC_DISABLE, 0);
}
}
static int __event(bool is_x, void *addr, int sig)
{
struct perf_event_attr pe;
int fd;
memset(&pe, 0, sizeof(struct perf_event_attr));
pe.type = PERF_TYPE_BREAKPOINT;
pe.size = sizeof(struct perf_event_attr);
pe.config = 0;
pe.bp_type = is_x ? HW_BREAKPOINT_X : HW_BREAKPOINT_W;
pe.bp_addr = (unsigned long) addr;
pe.bp_len = sizeof(long);
pe.sample_period = 1;
pe.sample_type = PERF_SAMPLE_IP;
pe.wakeup_events = 1;
pe.disabled = 1;
pe.exclude_kernel = 1;
pe.exclude_hv = 1;
fd = sys_perf_event_open(&pe, 0, -1, -1,
perf_event_open_cloexec_flag());
if (fd < 0) {
pr_debug("failed opening event %llx\n", pe.config);
return TEST_FAIL;
}
fcntl(fd, F_SETFL, O_RDWR|O_NONBLOCK|O_ASYNC);
fcntl(fd, F_SETSIG, sig);
fcntl(fd, F_SETOWN, getpid());
ioctl(fd, PERF_EVENT_IOC_RESET, 0);
return fd;
}
static int bp_event(void *addr, int sig)
{
return __event(true, addr, sig);
}
static int wp_event(void *addr, int sig)
{
return __event(false, addr, sig);
}
static long long bp_count(int fd)
{
long long count;
int ret;
ret = read(fd, &count, sizeof(long long));
if (ret != sizeof(long long)) {
pr_debug("failed to read: %d\n", ret);
return TEST_FAIL;
}
return count;
}
static int test__bp_signal(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct sigaction sa;
long long count1, count2, count3;
if (!BP_SIGNAL_IS_SUPPORTED) {
pr_debug("Test not supported on this architecture");
return TEST_SKIP;
}
/* setup SIGIO signal handler */
memset(&sa, 0, sizeof(struct sigaction));
sa.sa_sigaction = (void *) sig_handler;
sa.sa_flags = SA_SIGINFO;
if (sigaction(SIGIO, &sa, NULL) < 0) {
pr_debug("failed setting up signal handler\n");
return TEST_FAIL;
}
sa.sa_sigaction = (void *) sig_handler_2;
if (sigaction(SIGUSR1, &sa, NULL) < 0) {
pr_debug("failed setting up signal handler 2\n");
return TEST_FAIL;
}
/*
* We create following events:
*
* fd1 - breakpoint event on __test_function with SIGIO
* signal configured. We should get signal
* notification each time the breakpoint is hit
*
* fd2 - breakpoint event on sig_handler with SIGUSR1
* configured. We should get SIGUSR1 each time when
* breakpoint is hit
*
* fd3 - watchpoint event on __test_function with SIGIO
* configured.
*
* Following processing should happen:
* Exec: Action: Result:
* incq (%rdi) - fd1 event breakpoint hit -> count1 == 1
* - SIGIO is delivered
* sig_handler - fd2 event breakpoint hit -> count2 == 1
* - SIGUSR1 is delivered
* sig_handler_2 -> overflows_2 == 1 (nested signal)
* sys_rt_sigreturn - return from sig_handler_2
* overflows++ -> overflows = 1
* sys_rt_sigreturn - return from sig_handler
* incq (%rdi) - fd3 event watchpoint hit -> count3 == 1 (wp and bp in one insn)
* - SIGIO is delivered
* sig_handler - fd2 event breakpoint hit -> count2 == 2
* - SIGUSR1 is delivered
* sig_handler_2 -> overflows_2 == 2 (nested signal)
* sys_rt_sigreturn - return from sig_handler_2
* overflows++ -> overflows = 2
* sys_rt_sigreturn - return from sig_handler
* the_var++ - fd3 event watchpoint hit -> count3 == 2 (standalone watchpoint)
* - SIGIO is delivered
* sig_handler - fd2 event breakpoint hit -> count2 == 3
* - SIGUSR1 is delivered
* sig_handler_2 -> overflows_2 == 3 (nested signal)
* sys_rt_sigreturn - return from sig_handler_2
* overflows++ -> overflows == 3
* sys_rt_sigreturn - return from sig_handler
*
* The test case check following error conditions:
* - we get stuck in signal handler because of debug
* exception being triggered recursively due to
* the wrong RF EFLAG management
*
* - we never trigger the sig_handler breakpoint due
* to the wrong RF EFLAG management
*
*/
fd1 = bp_event(__test_function, SIGIO);
fd2 = bp_event(sig_handler, SIGUSR1);
fd3 = wp_event((void *)&the_var, SIGIO);
ioctl(fd1, PERF_EVENT_IOC_ENABLE, 0);
ioctl(fd2, PERF_EVENT_IOC_ENABLE, 0);
ioctl(fd3, PERF_EVENT_IOC_ENABLE, 0);
/*
* Kick off the test by triggering 'fd1'
* breakpoint.
*/
test_function();
ioctl(fd1, PERF_EVENT_IOC_DISABLE, 0);
ioctl(fd2, PERF_EVENT_IOC_DISABLE, 0);
ioctl(fd3, PERF_EVENT_IOC_DISABLE, 0);
count1 = bp_count(fd1);
count2 = bp_count(fd2);
count3 = bp_count(fd3);
close(fd1);
close(fd2);
close(fd3);
pr_debug("count1 %lld, count2 %lld, count3 %lld, overflow %d, overflows_2 %d\n",
count1, count2, count3, overflows, overflows_2);
if (count1 != 1) {
if (count1 == 11)
pr_debug("failed: RF EFLAG recursion issue detected\n");
else
pr_debug("failed: wrong count for bp1: %lld, expected 1\n", count1);
}
if (overflows != 3)
pr_debug("failed: wrong overflow (%d) hit, expected 3\n", overflows);
if (overflows_2 != 3)
pr_debug("failed: wrong overflow_2 (%d) hit, expected 3\n", overflows_2);
if (count2 != 3)
pr_debug("failed: wrong count for bp2 (%lld), expected 3\n", count2);
if (count3 != 2)
pr_debug("failed: wrong count for bp3 (%lld), expected 2\n", count3);
return count1 == 1 && overflows == 3 && count2 == 3 && overflows_2 == 3 && count3 == 2 ?
TEST_OK : TEST_FAIL;
}
DEFINE_SUITE("Breakpoint overflow signal handler", bp_signal);
| linux-master | tools/perf/tests/bp_signal.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <linux/compiler.h>
#include "debug.h"
#include "tests.h"
#ifdef HAVE_JITDUMP
#include <libelf.h>
#include "../util/genelf.h"
#endif
#define TEMPL "/tmp/perf-test-XXXXXX"
static int test__jit_write_elf(struct test_suite *test __maybe_unused,
int subtest __maybe_unused)
{
#ifdef HAVE_JITDUMP
static unsigned char x86_code[] = {
0xBB, 0x2A, 0x00, 0x00, 0x00, /* movl $42, %ebx */
0xB8, 0x01, 0x00, 0x00, 0x00, /* movl $1, %eax */
0xCD, 0x80 /* int $0x80 */
};
char path[PATH_MAX];
int fd, ret;
strcpy(path, TEMPL);
fd = mkstemp(path);
if (fd < 0) {
perror("mkstemp failed");
return TEST_FAIL;
}
pr_info("Writing jit code to: %s\n", path);
ret = jit_write_elf(fd, 0, "main", x86_code, sizeof(x86_code),
NULL, 0, NULL, 0, 0);
close(fd);
unlink(path);
return ret ? TEST_FAIL : 0;
#else
return TEST_SKIP;
#endif
}
DEFINE_SUITE("Test jit_write_elf", jit_write_elf);
| linux-master | tools/perf/tests/genelf.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
#include <string.h>
#include <perf/cpumap.h>
#include <perf/evlist.h>
#include "metricgroup.h"
#include "tests.h"
#include "pmu-events/pmu-events.h"
#include "evlist.h"
#include "rblist.h"
#include "debug.h"
#include "expr.h"
#include "stat.h"
#include "pmus.h"
struct value {
const char *event;
u64 val;
};
static u64 find_value(const char *name, struct value *values)
{
struct value *v = values;
while (v->event) {
if (!strcmp(name, v->event))
return v->val;
v++;
}
return 0;
}
static void load_runtime_stat(struct evlist *evlist, struct value *vals)
{
struct evsel *evsel;
u64 count;
evlist__alloc_aggr_stats(evlist, 1);
evlist__for_each_entry(evlist, evsel) {
count = find_value(evsel->name, vals);
evsel->supported = true;
evsel->stats->aggr->counts.val = count;
if (evsel__name_is(evsel, "duration_time"))
update_stats(&walltime_nsecs_stats, count);
}
}
static double compute_single(struct rblist *metric_events, struct evlist *evlist,
const char *name)
{
struct metric_expr *mexp;
struct metric_event *me;
struct evsel *evsel;
evlist__for_each_entry(evlist, evsel) {
me = metricgroup__lookup(metric_events, evsel, false);
if (me != NULL) {
list_for_each_entry (mexp, &me->head, nd) {
if (strcmp(mexp->metric_name, name))
continue;
return test_generic_metric(mexp, 0);
}
}
}
return 0.;
}
static int __compute_metric(const char *name, struct value *vals,
const char *name1, double *ratio1,
const char *name2, double *ratio2)
{
struct rblist metric_events = {
.nr_entries = 0,
};
const struct pmu_metrics_table *pme_test;
struct perf_cpu_map *cpus;
struct evlist *evlist;
int err;
/*
* We need to prepare evlist for stat mode running on CPU 0
* because that's where all the stats are going to be created.
*/
evlist = evlist__new();
if (!evlist)
return -ENOMEM;
cpus = perf_cpu_map__new("0");
if (!cpus) {
evlist__delete(evlist);
return -ENOMEM;
}
perf_evlist__set_maps(&evlist->core, cpus, NULL);
/* Parse the metric into metric_events list. */
pme_test = find_core_metrics_table("testarch", "testcpu");
err = metricgroup__parse_groups_test(evlist, pme_test, name,
&metric_events);
if (err)
goto out;
err = evlist__alloc_stats(/*config=*/NULL, evlist, /*alloc_raw=*/false);
if (err)
goto out;
/* Load the runtime stats with given numbers for events. */
load_runtime_stat(evlist, vals);
/* And execute the metric */
if (name1 && ratio1)
*ratio1 = compute_single(&metric_events, evlist, name1);
if (name2 && ratio2)
*ratio2 = compute_single(&metric_events, evlist, name2);
out:
/* ... cleanup. */
metricgroup__rblist_exit(&metric_events);
evlist__free_stats(evlist);
perf_cpu_map__put(cpus);
evlist__delete(evlist);
return err;
}
static int compute_metric(const char *name, struct value *vals, double *ratio)
{
return __compute_metric(name, vals, name, ratio, NULL, NULL);
}
static int compute_metric_group(const char *name, struct value *vals,
const char *name1, double *ratio1,
const char *name2, double *ratio2)
{
return __compute_metric(name, vals, name1, ratio1, name2, ratio2);
}
static int test_ipc(void)
{
double ratio;
struct value vals[] = {
{ .event = "inst_retired.any", .val = 300 },
{ .event = "cpu_clk_unhalted.thread", .val = 200 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to compute metric",
compute_metric("IPC", vals, &ratio) == 0);
TEST_ASSERT_VAL("IPC failed, wrong ratio",
ratio == 1.5);
return 0;
}
static int test_frontend(void)
{
double ratio;
struct value vals[] = {
{ .event = "idq_uops_not_delivered.core", .val = 300 },
{ .event = "cpu_clk_unhalted.thread", .val = 200 },
{ .event = "cpu_clk_unhalted.one_thread_active", .val = 400 },
{ .event = "cpu_clk_unhalted.ref_xclk", .val = 600 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to compute metric",
compute_metric("Frontend_Bound_SMT", vals, &ratio) == 0);
TEST_ASSERT_VAL("Frontend_Bound_SMT failed, wrong ratio",
ratio == 0.45);
return 0;
}
static int test_cache_miss_cycles(void)
{
double ratio;
struct value vals[] = {
{ .event = "l1d-loads-misses", .val = 300 },
{ .event = "l1i-loads-misses", .val = 200 },
{ .event = "inst_retired.any", .val = 400 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to compute metric",
compute_metric("cache_miss_cycles", vals, &ratio) == 0);
TEST_ASSERT_VAL("cache_miss_cycles failed, wrong ratio",
ratio == 1.25);
return 0;
}
/*
* DCache_L2_All_Hits = l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hi
* DCache_L2_All_Miss = max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) +
* l2_rqsts.pf_miss + l2_rqsts.rfo_miss
* DCache_L2_All = dcache_l2_all_hits + dcache_l2_all_miss
* DCache_L2_Hits = d_ratio(dcache_l2_all_hits, dcache_l2_all)
* DCache_L2_Misses = d_ratio(dcache_l2_all_miss, dcache_l2_all)
*
* l2_rqsts.demand_data_rd_hit = 100
* l2_rqsts.pf_hit = 200
* l2_rqsts.rfo_hi = 300
* l2_rqsts.all_demand_data_rd = 400
* l2_rqsts.pf_miss = 500
* l2_rqsts.rfo_miss = 600
*
* DCache_L2_All_Hits = 600
* DCache_L2_All_Miss = MAX(400 - 100, 0) + 500 + 600 = 1400
* DCache_L2_All = 600 + 1400 = 2000
* DCache_L2_Hits = 600 / 2000 = 0.3
* DCache_L2_Misses = 1400 / 2000 = 0.7
*/
static int test_dcache_l2(void)
{
double ratio;
struct value vals[] = {
{ .event = "l2_rqsts.demand_data_rd_hit", .val = 100 },
{ .event = "l2_rqsts.pf_hit", .val = 200 },
{ .event = "l2_rqsts.rfo_hit", .val = 300 },
{ .event = "l2_rqsts.all_demand_data_rd", .val = 400 },
{ .event = "l2_rqsts.pf_miss", .val = 500 },
{ .event = "l2_rqsts.rfo_miss", .val = 600 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to compute metric",
compute_metric("DCache_L2_Hits", vals, &ratio) == 0);
TEST_ASSERT_VAL("DCache_L2_Hits failed, wrong ratio",
ratio == 0.3);
TEST_ASSERT_VAL("failed to compute metric",
compute_metric("DCache_L2_Misses", vals, &ratio) == 0);
TEST_ASSERT_VAL("DCache_L2_Misses failed, wrong ratio",
ratio == 0.7);
return 0;
}
static int test_recursion_fail(void)
{
double ratio;
struct value vals[] = {
{ .event = "inst_retired.any", .val = 300 },
{ .event = "cpu_clk_unhalted.thread", .val = 200 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to find recursion",
compute_metric("M1", vals, &ratio) == -1);
TEST_ASSERT_VAL("failed to find recursion",
compute_metric("M3", vals, &ratio) == -1);
return 0;
}
static int test_memory_bandwidth(void)
{
double ratio;
struct value vals[] = {
{ .event = "l1d.replacement", .val = 4000000 },
{ .event = "duration_time", .val = 200000000 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to compute metric",
compute_metric("L1D_Cache_Fill_BW", vals, &ratio) == 0);
TEST_ASSERT_VAL("L1D_Cache_Fill_BW, wrong ratio",
1.28 == ratio);
return 0;
}
static int test_metric_group(void)
{
double ratio1, ratio2;
struct value vals[] = {
{ .event = "cpu_clk_unhalted.thread", .val = 200 },
{ .event = "l1d-loads-misses", .val = 300 },
{ .event = "l1i-loads-misses", .val = 200 },
{ .event = "inst_retired.any", .val = 400 },
{ .event = NULL, },
};
TEST_ASSERT_VAL("failed to find recursion",
compute_metric_group("group1", vals,
"IPC", &ratio1,
"cache_miss_cycles", &ratio2) == 0);
TEST_ASSERT_VAL("group IPC failed, wrong ratio",
ratio1 == 2.0);
TEST_ASSERT_VAL("group cache_miss_cycles failed, wrong ratio",
ratio2 == 1.25);
return 0;
}
static int test__parse_metric(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
TEST_ASSERT_VAL("IPC failed", test_ipc() == 0);
TEST_ASSERT_VAL("frontend failed", test_frontend() == 0);
TEST_ASSERT_VAL("DCache_L2 failed", test_dcache_l2() == 0);
TEST_ASSERT_VAL("recursion fail failed", test_recursion_fail() == 0);
TEST_ASSERT_VAL("Memory bandwidth", test_memory_bandwidth() == 0);
TEST_ASSERT_VAL("cache_miss_cycles failed", test_cache_miss_cycles() == 0);
TEST_ASSERT_VAL("test metric group", test_metric_group() == 0);
return 0;
}
DEFINE_SUITE("Parse and process metrics", parse_metric);
| linux-master | tools/perf/tests/parse-metric.c |
// SPDX-License-Identifier: GPL-2.0
#include "util/cputopo.h"
#include "util/debug.h"
#include "util/expr.h"
#include "util/hashmap.h"
#include "util/header.h"
#include "util/smt.h"
#include "tests.h"
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <linux/zalloc.h>
static int test_ids_union(void)
{
struct hashmap *ids1, *ids2;
/* Empty union. */
ids1 = ids__new();
TEST_ASSERT_VAL("ids__new", ids1);
ids2 = ids__new();
TEST_ASSERT_VAL("ids__new", ids2);
ids1 = ids__union(ids1, ids2);
TEST_ASSERT_EQUAL("union", (int)hashmap__size(ids1), 0);
/* Union {foo, bar} against {}. */
ids2 = ids__new();
TEST_ASSERT_VAL("ids__new", ids2);
TEST_ASSERT_EQUAL("ids__insert", ids__insert(ids1, strdup("foo")), 0);
TEST_ASSERT_EQUAL("ids__insert", ids__insert(ids1, strdup("bar")), 0);
ids1 = ids__union(ids1, ids2);
TEST_ASSERT_EQUAL("union", (int)hashmap__size(ids1), 2);
/* Union {foo, bar} against {foo}. */
ids2 = ids__new();
TEST_ASSERT_VAL("ids__new", ids2);
TEST_ASSERT_EQUAL("ids__insert", ids__insert(ids2, strdup("foo")), 0);
ids1 = ids__union(ids1, ids2);
TEST_ASSERT_EQUAL("union", (int)hashmap__size(ids1), 2);
/* Union {foo, bar} against {bar,baz}. */
ids2 = ids__new();
TEST_ASSERT_VAL("ids__new", ids2);
TEST_ASSERT_EQUAL("ids__insert", ids__insert(ids2, strdup("bar")), 0);
TEST_ASSERT_EQUAL("ids__insert", ids__insert(ids2, strdup("baz")), 0);
ids1 = ids__union(ids1, ids2);
TEST_ASSERT_EQUAL("union", (int)hashmap__size(ids1), 3);
ids__free(ids1);
return 0;
}
static int test(struct expr_parse_ctx *ctx, const char *e, double val2)
{
double val;
if (expr__parse(&val, ctx, e))
TEST_ASSERT_VAL("parse test failed", 0);
TEST_ASSERT_VAL("unexpected value", val == val2);
return 0;
}
static int test__expr(struct test_suite *t __maybe_unused, int subtest __maybe_unused)
{
struct expr_id_data *val_ptr;
const char *p;
double val, num_cpus_online, num_cpus, num_cores, num_dies, num_packages;
int ret;
struct expr_parse_ctx *ctx;
bool is_intel = false;
char buf[128];
if (!get_cpuid(buf, sizeof(buf)))
is_intel = strstr(buf, "Intel") != NULL;
TEST_ASSERT_EQUAL("ids_union", test_ids_union(), 0);
ctx = expr__ctx_new();
TEST_ASSERT_VAL("expr__ctx_new", ctx);
expr__add_id_val(ctx, strdup("FOO"), 1);
expr__add_id_val(ctx, strdup("BAR"), 2);
ret = test(ctx, "1+1", 2);
ret |= test(ctx, "FOO+BAR", 3);
ret |= test(ctx, "(BAR/2)%2", 1);
ret |= test(ctx, "1 - -4", 5);
ret |= test(ctx, "(FOO-1)*2 + (BAR/2)%2 - -4", 5);
ret |= test(ctx, "1-1 | 1", 1);
ret |= test(ctx, "1-1 & 1", 0);
ret |= test(ctx, "min(1,2) + 1", 2);
ret |= test(ctx, "max(1,2) + 1", 3);
ret |= test(ctx, "1+1 if 3*4 else 0", 2);
ret |= test(ctx, "100 if 1 else 200 if 1 else 300", 100);
ret |= test(ctx, "100 if 0 else 200 if 1 else 300", 200);
ret |= test(ctx, "100 if 1 else 200 if 0 else 300", 100);
ret |= test(ctx, "100 if 0 else 200 if 0 else 300", 300);
ret |= test(ctx, "1.1 + 2.1", 3.2);
ret |= test(ctx, ".1 + 2.", 2.1);
ret |= test(ctx, "d_ratio(1, 2)", 0.5);
ret |= test(ctx, "d_ratio(2.5, 0)", 0);
ret |= test(ctx, "1.1 < 2.2", 1);
ret |= test(ctx, "2.2 > 1.1", 1);
ret |= test(ctx, "1.1 < 1.1", 0);
ret |= test(ctx, "2.2 > 2.2", 0);
ret |= test(ctx, "2.2 < 1.1", 0);
ret |= test(ctx, "1.1 > 2.2", 0);
ret |= test(ctx, "1.1e10 < 1.1e100", 1);
ret |= test(ctx, "1.1e2 > 1.1e-2", 1);
if (ret) {
expr__ctx_free(ctx);
return ret;
}
p = "FOO/0";
ret = expr__parse(&val, ctx, p);
TEST_ASSERT_VAL("division by zero", ret == 0);
TEST_ASSERT_VAL("division by zero", isnan(val));
p = "BAR/";
ret = expr__parse(&val, ctx, p);
TEST_ASSERT_VAL("missing operand", ret == -1);
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("FOO + BAR + BAZ + BOZO", "FOO",
ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 3);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "BAR", &val_ptr));
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "BAZ", &val_ptr));
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "BOZO", &val_ptr));
expr__ctx_clear(ctx);
ctx->sctx.runtime = 3;
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1\\,param\\=?@ + EVENT2\\,param\\=?@",
NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 2);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "EVENT1,param=3@", &val_ptr));
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "EVENT2,param=3@", &val_ptr));
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("dash\\-event1 - dash\\-event2",
NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 2);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "dash-event1", &val_ptr));
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "dash-event2", &val_ptr));
/* Only EVENT1 or EVENT2 need be measured depending on the value of smt_on. */
{
bool smton = smt_on();
bool corewide = core_wide(/*system_wide=*/false,
/*user_requested_cpus=*/false);
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1 if #smt_on else EVENT2",
NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids,
smton ? "EVENT1" : "EVENT2",
&val_ptr));
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1 if #core_wide else EVENT2",
NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids,
corewide ? "EVENT1" : "EVENT2",
&val_ptr));
}
/* The expression is a constant 1.0 without needing to evaluate EVENT1. */
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("1.0 if EVENT1 > 100.0 else 1.0",
NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 0);
/* The expression is a constant 0.0 without needing to evaluate EVENT1. */
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("0 & EVENT1 > 0", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 0);
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1 > 0 & 0", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 0);
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("1 & EVENT1 > 0", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "EVENT1", &val_ptr));
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1 > 0 & 1", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "EVENT1", &val_ptr));
/* The expression is a constant 1.0 without needing to evaluate EVENT1. */
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("1 | EVENT1 > 0", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 0);
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1 > 0 | 1", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 0);
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("0 | EVENT1 > 0", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "EVENT1", &val_ptr));
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("find ids",
expr__find_ids("EVENT1 > 0 | 0", NULL, ctx) == 0);
TEST_ASSERT_VAL("find ids", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("find ids", hashmap__find(ctx->ids, "EVENT1", &val_ptr));
/* Test toplogy constants appear well ordered. */
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("#num_cpus_online",
expr__parse(&num_cpus_online, ctx, "#num_cpus_online") == 0);
TEST_ASSERT_VAL("#num_cpus", expr__parse(&num_cpus, ctx, "#num_cpus") == 0);
TEST_ASSERT_VAL("#num_cpus >= #num_cpus_online", num_cpus >= num_cpus_online);
TEST_ASSERT_VAL("#num_cores", expr__parse(&num_cores, ctx, "#num_cores") == 0);
TEST_ASSERT_VAL("#num_cpus >= #num_cores", num_cpus >= num_cores);
TEST_ASSERT_VAL("#num_dies", expr__parse(&num_dies, ctx, "#num_dies") == 0);
TEST_ASSERT_VAL("#num_cores >= #num_dies", num_cores >= num_dies);
TEST_ASSERT_VAL("#num_packages", expr__parse(&num_packages, ctx, "#num_packages") == 0);
if (num_dies) // Some platforms do not have CPU die support, for example s390
TEST_ASSERT_VAL("#num_dies >= #num_packages", num_dies >= num_packages);
TEST_ASSERT_VAL("#system_tsc_freq", expr__parse(&val, ctx, "#system_tsc_freq") == 0);
if (is_intel)
TEST_ASSERT_VAL("#system_tsc_freq > 0", val > 0);
else
TEST_ASSERT_VAL("#system_tsc_freq == 0", fpclassify(val) == FP_ZERO);
/*
* Source count returns the number of events aggregating in a leader
* event including the leader. Check parsing yields an id.
*/
expr__ctx_clear(ctx);
TEST_ASSERT_VAL("source count",
expr__find_ids("source_count(EVENT1)",
NULL, ctx) == 0);
TEST_ASSERT_VAL("source count", hashmap__size(ctx->ids) == 1);
TEST_ASSERT_VAL("source count", hashmap__find(ctx->ids, "EVENT1", &val_ptr));
/* has_event returns 1 when an event exists. */
expr__add_id_val(ctx, strdup("cycles"), 2);
ret = test(ctx, "has_event(cycles)", 1);
expr__ctx_free(ctx);
return 0;
}
DEFINE_SUITE("Simple expression parser", expr);
| linux-master | tools/perf/tests/expr.c |
// SPDX-License-Identifier: GPL-2.0
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
#include "tests.h"
#include "dso.h"
#include "debug.h"
#include "event.h"
static int test(const char *path, bool alloc_name, bool kmod,
int comp, const char *name)
{
struct kmod_path m;
memset(&m, 0x0, sizeof(m));
TEST_ASSERT_VAL("kmod_path__parse",
!__kmod_path__parse(&m, path, alloc_name));
pr_debug("%s - alloc name %d, kmod %d, comp %d, name '%s'\n",
path, alloc_name, m.kmod, m.comp, m.name);
TEST_ASSERT_VAL("wrong kmod", m.kmod == kmod);
TEST_ASSERT_VAL("wrong comp", m.comp == comp);
if (name)
TEST_ASSERT_VAL("wrong name", m.name && !strcmp(name, m.name));
else
TEST_ASSERT_VAL("wrong name", !m.name);
free(m.name);
return 0;
}
static int test_is_kernel_module(const char *path, int cpumode, bool expect)
{
TEST_ASSERT_VAL("is_kernel_module",
(!!is_kernel_module(path, cpumode)) == (!!expect));
pr_debug("%s (cpumode: %d) - is_kernel_module: %s\n",
path, cpumode, expect ? "true" : "false");
return 0;
}
#define T(path, an, k, c, n) \
TEST_ASSERT_VAL("failed", !test(path, an, k, c, n))
#define M(path, c, e) \
TEST_ASSERT_VAL("failed", !test_is_kernel_module(path, c, e))
static int test__kmod_path__parse(struct test_suite *t __maybe_unused, int subtest __maybe_unused)
{
/* path alloc_name kmod comp name */
T("/xxxx/xxxx/x-x.ko", true , true, 0 , "[x_x]");
T("/xxxx/xxxx/x-x.ko", false , true, 0 , NULL );
T("/xxxx/xxxx/x-x.ko", true , true, 0 , "[x_x]");
T("/xxxx/xxxx/x-x.ko", false , true, 0 , NULL );
M("/xxxx/xxxx/x-x.ko", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
M("/xxxx/xxxx/x-x.ko", PERF_RECORD_MISC_KERNEL, true);
M("/xxxx/xxxx/x-x.ko", PERF_RECORD_MISC_USER, false);
#ifdef HAVE_ZLIB_SUPPORT
/* path alloc_name kmod comp name */
T("/xxxx/xxxx/x.ko.gz", true , true, 1 , "[x]");
T("/xxxx/xxxx/x.ko.gz", false , true, 1 , NULL );
T("/xxxx/xxxx/x.ko.gz", true , true, 1 , "[x]");
T("/xxxx/xxxx/x.ko.gz", false , true, 1 , NULL );
M("/xxxx/xxxx/x.ko.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
M("/xxxx/xxxx/x.ko.gz", PERF_RECORD_MISC_KERNEL, true);
M("/xxxx/xxxx/x.ko.gz", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("/xxxx/xxxx/x.gz", true , false, 1 , "x.gz");
T("/xxxx/xxxx/x.gz", false , false, 1 , NULL );
T("/xxxx/xxxx/x.gz", true , false, 1 , "x.gz");
T("/xxxx/xxxx/x.gz", false , false, 1 , NULL );
M("/xxxx/xxxx/x.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("/xxxx/xxxx/x.gz", PERF_RECORD_MISC_KERNEL, false);
M("/xxxx/xxxx/x.gz", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("x.gz", true , false, 1 , "x.gz");
T("x.gz", false , false, 1 , NULL );
T("x.gz", true , false, 1 , "x.gz");
T("x.gz", false , false, 1 , NULL );
M("x.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("x.gz", PERF_RECORD_MISC_KERNEL, false);
M("x.gz", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("x.ko.gz", true , true, 1 , "[x]");
T("x.ko.gz", false , true, 1 , NULL );
T("x.ko.gz", true , true, 1 , "[x]");
T("x.ko.gz", false , true, 1 , NULL );
M("x.ko.gz", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
M("x.ko.gz", PERF_RECORD_MISC_KERNEL, true);
M("x.ko.gz", PERF_RECORD_MISC_USER, false);
#endif
/* path alloc_name kmod comp name */
T("[test_module]", true , true, false, "[test_module]");
T("[test_module]", false , true, false, NULL );
T("[test_module]", true , true, false, "[test_module]");
T("[test_module]", false , true, false, NULL );
M("[test_module]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
M("[test_module]", PERF_RECORD_MISC_KERNEL, true);
M("[test_module]", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("[test.module]", true , true, false, "[test.module]");
T("[test.module]", false , true, false, NULL );
T("[test.module]", true , true, false, "[test.module]");
T("[test.module]", false , true, false, NULL );
M("[test.module]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, true);
M("[test.module]", PERF_RECORD_MISC_KERNEL, true);
M("[test.module]", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("[vdso]", true , false, false, "[vdso]");
T("[vdso]", false , false, false, NULL );
T("[vdso]", true , false, false, "[vdso]");
T("[vdso]", false , false, false, NULL );
M("[vdso]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("[vdso]", PERF_RECORD_MISC_KERNEL, false);
M("[vdso]", PERF_RECORD_MISC_USER, false);
T("[vdso32]", true , false, false, "[vdso32]");
T("[vdso32]", false , false, false, NULL );
T("[vdso32]", true , false, false, "[vdso32]");
T("[vdso32]", false , false, false, NULL );
M("[vdso32]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("[vdso32]", PERF_RECORD_MISC_KERNEL, false);
M("[vdso32]", PERF_RECORD_MISC_USER, false);
T("[vdsox32]", true , false, false, "[vdsox32]");
T("[vdsox32]", false , false, false, NULL );
T("[vdsox32]", true , false, false, "[vdsox32]");
T("[vdsox32]", false , false, false, NULL );
M("[vdsox32]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("[vdsox32]", PERF_RECORD_MISC_KERNEL, false);
M("[vdsox32]", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("[vsyscall]", true , false, false, "[vsyscall]");
T("[vsyscall]", false , false, false, NULL );
T("[vsyscall]", true , false, false, "[vsyscall]");
T("[vsyscall]", false , false, false, NULL );
M("[vsyscall]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("[vsyscall]", PERF_RECORD_MISC_KERNEL, false);
M("[vsyscall]", PERF_RECORD_MISC_USER, false);
/* path alloc_name kmod comp name */
T("[kernel.kallsyms]", true , false, false, "[kernel.kallsyms]");
T("[kernel.kallsyms]", false , false, false, NULL );
T("[kernel.kallsyms]", true , false, false, "[kernel.kallsyms]");
T("[kernel.kallsyms]", false , false, false, NULL );
M("[kernel.kallsyms]", PERF_RECORD_MISC_CPUMODE_UNKNOWN, false);
M("[kernel.kallsyms]", PERF_RECORD_MISC_KERNEL, false);
M("[kernel.kallsyms]", PERF_RECORD_MISC_USER, false);
return 0;
}
DEFINE_SUITE("kmod_path__parse", kmod_path__parse);
| linux-master | tools/perf/tests/kmod-path.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <limits.h>
#include <unistd.h>
#include <sys/prctl.h>
#include <perf/cpumap.h>
#include <perf/evlist.h>
#include <perf/mmap.h>
#include "debug.h"
#include "parse-events.h"
#include "evlist.h"
#include "evsel.h"
#include "record.h"
#include "thread_map.h"
#include "tests.h"
#include "util/mmap.h"
#define CHECK__(x) { \
while ((x) < 0) { \
pr_debug(#x " failed!\n"); \
goto out_err; \
} \
}
#define CHECK_NOT_NULL__(x) { \
while ((x) == NULL) { \
pr_debug(#x " failed!\n"); \
goto out_err; \
} \
}
static int find_comm(struct evlist *evlist, const char *comm)
{
union perf_event *event;
struct mmap *md;
int i, found;
found = 0;
for (i = 0; i < evlist->core.nr_mmaps; i++) {
md = &evlist->mmap[i];
if (perf_mmap__read_init(&md->core) < 0)
continue;
while ((event = perf_mmap__read_event(&md->core)) != NULL) {
if (event->header.type == PERF_RECORD_COMM &&
(pid_t)event->comm.pid == getpid() &&
(pid_t)event->comm.tid == getpid() &&
strcmp(event->comm.comm, comm) == 0)
found += 1;
perf_mmap__consume(&md->core);
}
perf_mmap__read_done(&md->core);
}
return found;
}
/**
* test__keep_tracking - test using a dummy software event to keep tracking.
*
* This function implements a test that checks that tracking events continue
* when an event is disabled but a dummy software event is not disabled. If the
* test passes %0 is returned, otherwise %-1 is returned.
*/
static int test__keep_tracking(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct record_opts opts = {
.mmap_pages = UINT_MAX,
.user_freq = UINT_MAX,
.user_interval = ULLONG_MAX,
.target = {
.uses_mmap = true,
},
};
struct perf_thread_map *threads = NULL;
struct perf_cpu_map *cpus = NULL;
struct evlist *evlist = NULL;
struct evsel *evsel = NULL;
int found, err = -1;
const char *comm;
threads = thread_map__new(-1, getpid(), UINT_MAX);
CHECK_NOT_NULL__(threads);
cpus = perf_cpu_map__new(NULL);
CHECK_NOT_NULL__(cpus);
evlist = evlist__new();
CHECK_NOT_NULL__(evlist);
perf_evlist__set_maps(&evlist->core, cpus, threads);
CHECK__(parse_event(evlist, "dummy:u"));
CHECK__(parse_event(evlist, "cycles:u"));
evlist__config(evlist, &opts, NULL);
evsel = evlist__first(evlist);
evsel->core.attr.comm = 1;
evsel->core.attr.disabled = 1;
evsel->core.attr.enable_on_exec = 0;
if (evlist__open(evlist) < 0) {
pr_debug("Unable to open dummy and cycles event\n");
err = TEST_SKIP;
goto out_err;
}
CHECK__(evlist__mmap(evlist, UINT_MAX));
/*
* First, test that a 'comm' event can be found when the event is
* enabled.
*/
evlist__enable(evlist);
comm = "Test COMM 1";
CHECK__(prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0));
evlist__disable(evlist);
found = find_comm(evlist, comm);
if (found != 1) {
pr_debug("First time, failed to find tracking event.\n");
goto out_err;
}
/*
* Secondly, test that a 'comm' event can be found when the event is
* disabled with the dummy event still enabled.
*/
evlist__enable(evlist);
evsel = evlist__last(evlist);
CHECK__(evsel__disable(evsel));
comm = "Test COMM 2";
CHECK__(prctl(PR_SET_NAME, (unsigned long)comm, 0, 0, 0));
evlist__disable(evlist);
found = find_comm(evlist, comm);
if (found != 1) {
pr_debug("Second time, failed to find tracking event.\n");
goto out_err;
}
err = 0;
out_err:
if (evlist) {
evlist__disable(evlist);
evlist__delete(evlist);
}
perf_cpu_map__put(cpus);
perf_thread_map__put(threads);
return err;
}
DEFINE_SUITE("Use a dummy software event to keep tracking", keep_tracking);
| linux-master | tools/perf/tests/keep-tracking.c |
// SPDX-License-Identifier: GPL-2.0
#include "tests.h"
#include <stdio.h>
#include "cpumap.h"
#include "event.h"
#include "util/synthetic-events.h"
#include <string.h>
#include <linux/bitops.h>
#include <internal/cpumap.h>
#include "debug.h"
struct machine;
static int process_event_mask(struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct perf_record_cpu_map *map_event = &event->cpu_map;
struct perf_record_cpu_map_data *data;
struct perf_cpu_map *map;
unsigned int long_size;
data = &map_event->data;
TEST_ASSERT_VAL("wrong type", data->type == PERF_CPU_MAP__MASK);
long_size = data->mask32_data.long_size;
TEST_ASSERT_VAL("wrong long_size", long_size == 4 || long_size == 8);
TEST_ASSERT_VAL("wrong nr", data->mask32_data.nr == 1);
TEST_ASSERT_VAL("wrong cpu", perf_record_cpu_map_data__test_bit(0, data));
TEST_ASSERT_VAL("wrong cpu", !perf_record_cpu_map_data__test_bit(1, data));
for (int i = 2; i <= 20; i++)
TEST_ASSERT_VAL("wrong cpu", perf_record_cpu_map_data__test_bit(i, data));
map = cpu_map__new_data(data);
TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 20);
TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 0).cpu == 0);
for (int i = 2; i <= 20; i++)
TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, i - 1).cpu == i);
perf_cpu_map__put(map);
return 0;
}
static int process_event_cpus(struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct perf_record_cpu_map *map_event = &event->cpu_map;
struct perf_record_cpu_map_data *data;
struct perf_cpu_map *map;
data = &map_event->data;
TEST_ASSERT_VAL("wrong type", data->type == PERF_CPU_MAP__CPUS);
TEST_ASSERT_VAL("wrong nr", data->cpus_data.nr == 2);
TEST_ASSERT_VAL("wrong cpu", data->cpus_data.cpu[0] == 1);
TEST_ASSERT_VAL("wrong cpu", data->cpus_data.cpu[1] == 256);
map = cpu_map__new_data(data);
TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 2);
TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 0).cpu == 1);
TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 1).cpu == 256);
TEST_ASSERT_VAL("wrong refcnt", refcount_read(perf_cpu_map__refcnt(map)) == 1);
perf_cpu_map__put(map);
return 0;
}
static int process_event_range_cpus(struct perf_tool *tool __maybe_unused,
union perf_event *event,
struct perf_sample *sample __maybe_unused,
struct machine *machine __maybe_unused)
{
struct perf_record_cpu_map *map_event = &event->cpu_map;
struct perf_record_cpu_map_data *data;
struct perf_cpu_map *map;
data = &map_event->data;
TEST_ASSERT_VAL("wrong type", data->type == PERF_CPU_MAP__RANGE_CPUS);
TEST_ASSERT_VAL("wrong any_cpu", data->range_cpu_data.any_cpu == 0);
TEST_ASSERT_VAL("wrong start_cpu", data->range_cpu_data.start_cpu == 1);
TEST_ASSERT_VAL("wrong end_cpu", data->range_cpu_data.end_cpu == 256);
map = cpu_map__new_data(data);
TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 256);
TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 0).cpu == 1);
TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__max(map).cpu == 256);
TEST_ASSERT_VAL("wrong refcnt", refcount_read(perf_cpu_map__refcnt(map)) == 1);
perf_cpu_map__put(map);
return 0;
}
static int test__cpu_map_synthesize(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_cpu_map *cpus;
/* This one is better stored in a mask. */
cpus = perf_cpu_map__new("0,2-20");
TEST_ASSERT_VAL("failed to synthesize map",
!perf_event__synthesize_cpu_map(NULL, cpus, process_event_mask, NULL));
perf_cpu_map__put(cpus);
/* This one is better stored in cpu values. */
cpus = perf_cpu_map__new("1,256");
TEST_ASSERT_VAL("failed to synthesize map",
!perf_event__synthesize_cpu_map(NULL, cpus, process_event_cpus, NULL));
perf_cpu_map__put(cpus);
/* This one is better stored as a range. */
cpus = perf_cpu_map__new("1-256");
TEST_ASSERT_VAL("failed to synthesize map",
!perf_event__synthesize_cpu_map(NULL, cpus, process_event_range_cpus, NULL));
perf_cpu_map__put(cpus);
return 0;
}
static int cpu_map_print(const char *str)
{
struct perf_cpu_map *map = perf_cpu_map__new(str);
char buf[100];
if (!map)
return -1;
cpu_map__snprint(map, buf, sizeof(buf));
perf_cpu_map__put(map);
return !strcmp(buf, str);
}
static int test__cpu_map_print(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1,5"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1,3,5,7,9,11,13,15,17,19,21-40"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("2-5"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1,3-6,8-10,24,35-37"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1,3-6,8-10,24,35-37"));
TEST_ASSERT_VAL("failed to convert map", cpu_map_print("1-10,12-20,22-30,32-40"));
return 0;
}
static int test__cpu_map_merge(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_cpu_map *a = perf_cpu_map__new("4,2,1");
struct perf_cpu_map *b = perf_cpu_map__new("4,5,7");
struct perf_cpu_map *c = perf_cpu_map__merge(a, b);
char buf[100];
TEST_ASSERT_VAL("failed to merge map: bad nr", perf_cpu_map__nr(c) == 5);
cpu_map__snprint(c, buf, sizeof(buf));
TEST_ASSERT_VAL("failed to merge map: bad result", !strcmp(buf, "1-2,4-5,7"));
perf_cpu_map__put(b);
perf_cpu_map__put(c);
return 0;
}
static int __test__cpu_map_intersect(const char *lhs, const char *rhs, int nr, const char *expected)
{
struct perf_cpu_map *a = perf_cpu_map__new(lhs);
struct perf_cpu_map *b = perf_cpu_map__new(rhs);
struct perf_cpu_map *c = perf_cpu_map__intersect(a, b);
char buf[100];
TEST_ASSERT_EQUAL("failed to intersect map: bad nr", perf_cpu_map__nr(c), nr);
cpu_map__snprint(c, buf, sizeof(buf));
TEST_ASSERT_VAL("failed to intersect map: bad result", !strcmp(buf, expected));
perf_cpu_map__put(a);
perf_cpu_map__put(b);
perf_cpu_map__put(c);
return 0;
}
static int test__cpu_map_intersect(struct test_suite *test __maybe_unused,
int subtest __maybe_unused)
{
int ret;
ret = __test__cpu_map_intersect("4,2,1", "4,5,7", 1, "4");
if (ret)
return ret;
ret = __test__cpu_map_intersect("1-8", "6-9", 3, "6-8");
if (ret)
return ret;
ret = __test__cpu_map_intersect("1-8,12-20", "6-9,15", 4, "6-8,15");
if (ret)
return ret;
ret = __test__cpu_map_intersect("4,2,1", "1", 1, "1");
if (ret)
return ret;
ret = __test__cpu_map_intersect("1", "4,2,1", 1, "1");
if (ret)
return ret;
ret = __test__cpu_map_intersect("1", "1", 1, "1");
return ret;
}
static int test__cpu_map_equal(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct perf_cpu_map *any = perf_cpu_map__dummy_new();
struct perf_cpu_map *one = perf_cpu_map__new("1");
struct perf_cpu_map *two = perf_cpu_map__new("2");
struct perf_cpu_map *empty = perf_cpu_map__intersect(one, two);
struct perf_cpu_map *pair = perf_cpu_map__new("1-2");
struct perf_cpu_map *tmp;
struct perf_cpu_map *maps[] = {empty, any, one, two, pair};
for (size_t i = 0; i < ARRAY_SIZE(maps); i++) {
/* Maps equal themself. */
TEST_ASSERT_VAL("equal", perf_cpu_map__equal(maps[i], maps[i]));
for (size_t j = 0; j < ARRAY_SIZE(maps); j++) {
/* Maps dont't equal each other. */
if (i == j)
continue;
TEST_ASSERT_VAL("not equal", !perf_cpu_map__equal(maps[i], maps[j]));
}
}
/* Maps equal made maps. */
tmp = perf_cpu_map__merge(perf_cpu_map__get(one), two);
TEST_ASSERT_VAL("pair", perf_cpu_map__equal(pair, tmp));
perf_cpu_map__put(tmp);
tmp = perf_cpu_map__intersect(pair, one);
TEST_ASSERT_VAL("one", perf_cpu_map__equal(one, tmp));
perf_cpu_map__put(tmp);
for (size_t i = 0; i < ARRAY_SIZE(maps); i++)
perf_cpu_map__put(maps[i]);
return TEST_OK;
}
static struct test_case tests__cpu_map[] = {
TEST_CASE("Synthesize cpu map", cpu_map_synthesize),
TEST_CASE("Print cpu map", cpu_map_print),
TEST_CASE("Merge cpu map", cpu_map_merge),
TEST_CASE("Intersect cpu map", cpu_map_intersect),
TEST_CASE("Equal cpu map", cpu_map_equal),
{ .name = NULL, }
};
struct test_suite suite__cpu_map = {
.desc = "CPU map",
.test_cases = tests__cpu_map,
};
| linux-master | tools/perf/tests/cpumap.c |
// SPDX-License-Identifier: GPL-2.0
// Carsten Haitzler <[email protected]>, 2021
// define this for gettid()
#define _GNU_SOURCE
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <pthread.h>
#include <sys/syscall.h>
#ifndef SYS_gettid
// gettid is 178 on arm64
# define SYS_gettid 178
#endif
#define gettid() syscall(SYS_gettid)
struct args {
unsigned int loops;
pthread_t th;
void *ret;
};
static void *thrfn(void *arg)
{
struct args *a = arg;
int i = 0, len = a->loops;
if (getenv("SHOW_TID")) {
unsigned long long tid = gettid();
printf("%llu\n", tid);
}
asm volatile(
"loop:\n"
"add %[i], %[i], #1\n"
"cmp %[i], %[len]\n"
"blt loop\n"
: /* out */
: /* in */ [i] "r" (i), [len] "r" (len)
: /* clobber */
);
return (void *)(long)i;
}
static pthread_t new_thr(void *(*fn) (void *arg), void *arg)
{
pthread_t t;
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_create(&t, &attr, fn, arg);
return t;
}
int main(int argc, char **argv)
{
unsigned int i, len, thr;
pthread_t threads[256];
struct args args[256];
if (argc < 3) {
printf("ERR: %s [numthreads] [numloops (millions)]\n", argv[0]);
exit(1);
}
thr = atoi(argv[1]);
if ((thr < 1) || (thr > 256)) {
printf("ERR: threads 1-256\n");
exit(1);
}
len = atoi(argv[2]);
if ((len < 1) || (len > 4000)) {
printf("ERR: max loops 4000 (millions)\n");
exit(1);
}
len *= 1000000;
for (i = 0; i < thr; i++) {
args[i].loops = len;
args[i].th = new_thr(thrfn, &(args[i]));
}
for (i = 0; i < thr; i++)
pthread_join(args[i].th, &(args[i].ret));
return 0;
}
| linux-master | tools/perf/tests/shell/coresight/thread_loop/thread_loop.c |
// SPDX-License-Identifier: GPL-2.0
// Carsten Haitzler <[email protected]>, 2021
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <pthread.h>
struct args {
pthread_t th;
unsigned int in;
void *ret;
};
static void *thrfn(void *arg)
{
struct args *a = arg;
unsigned int i, in = a->in;
for (i = 0; i < 10000; i++) {
asm volatile (
// force an unroll of thia add instruction so we can test long runs of code
#define SNIP1 "add %[in], %[in], #1\n"
// 10
#define SNIP2 SNIP1 SNIP1 SNIP1 SNIP1 SNIP1 SNIP1 SNIP1 SNIP1 SNIP1 SNIP1
// 100
#define SNIP3 SNIP2 SNIP2 SNIP2 SNIP2 SNIP2 SNIP2 SNIP2 SNIP2 SNIP2 SNIP2
// 1000
#define SNIP4 SNIP3 SNIP3 SNIP3 SNIP3 SNIP3 SNIP3 SNIP3 SNIP3 SNIP3 SNIP3
// 10000
#define SNIP5 SNIP4 SNIP4 SNIP4 SNIP4 SNIP4 SNIP4 SNIP4 SNIP4 SNIP4 SNIP4
// 100000
SNIP5 SNIP5 SNIP5 SNIP5 SNIP5 SNIP5 SNIP5 SNIP5 SNIP5 SNIP5
: /* out */
: /* in */ [in] "r" (in)
: /* clobber */
);
}
}
static pthread_t new_thr(void *(*fn) (void *arg), void *arg)
{
pthread_t t;
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_create(&t, &attr, fn, arg);
return t;
}
int main(int argc, char **argv)
{
unsigned int i, thr;
pthread_t threads[256];
struct args args[256];
if (argc < 2) {
printf("ERR: %s [numthreads]\n", argv[0]);
exit(1);
}
thr = atoi(argv[1]);
if ((thr > 256) || (thr < 1)) {
printf("ERR: threads 1-256\n");
exit(1);
}
for (i = 0; i < thr; i++) {
args[i].in = rand();
args[i].th = new_thr(thrfn, &(args[i]));
}
for (i = 0; i < thr; i++)
pthread_join(args[i].th, &(args[i].ret));
return 0;
}
| linux-master | tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c |
// SPDX-License-Identifier: GPL-2.0
// Carsten Haitzler <[email protected]>, 2021
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <pthread.h>
struct args {
unsigned long loops;
unsigned long size;
pthread_t th;
void *ret;
};
static void *thrfn(void *arg)
{
struct args *a = arg;
unsigned long i, len = a->loops;
unsigned char *src, *dst;
src = malloc(a->size * 1024);
dst = malloc(a->size * 1024);
if ((!src) || (!dst)) {
printf("ERR: Can't allocate memory\n");
exit(1);
}
for (i = 0; i < len; i++)
memcpy(dst, src, a->size * 1024);
}
static pthread_t new_thr(void *(*fn) (void *arg), void *arg)
{
pthread_t t;
pthread_attr_t attr;
pthread_attr_init(&attr);
pthread_create(&t, &attr, fn, arg);
return t;
}
int main(int argc, char **argv)
{
unsigned long i, len, size, thr;
pthread_t threads[256];
struct args args[256];
long long v;
if (argc < 4) {
printf("ERR: %s [copysize Kb] [numthreads] [numloops (hundreds)]\n", argv[0]);
exit(1);
}
v = atoll(argv[1]);
if ((v < 1) || (v > (1024 * 1024))) {
printf("ERR: max memory 1GB (1048576 KB)\n");
exit(1);
}
size = v;
thr = atol(argv[2]);
if ((thr < 1) || (thr > 256)) {
printf("ERR: threads 1-256\n");
exit(1);
}
v = atoll(argv[3]);
if ((v < 1) || (v > 40000000000ll)) {
printf("ERR: loops 1-40000000000 (hundreds)\n");
exit(1);
}
len = v * 100;
for (i = 0; i < thr; i++) {
args[i].loops = len;
args[i].size = size;
args[i].th = new_thr(thrfn, &(args[i]));
}
for (i = 0; i < thr; i++)
pthread_join(args[i].th, &(args[i].ret));
return 0;
}
| linux-master | tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c |
/* SPDX-License-Identifier: GPL-2.0 */
#include <pthread.h>
#include <stdlib.h>
#include <signal.h>
#include <unistd.h>
#include <linux/compiler.h>
#include "../tests.h"
static volatile sig_atomic_t done;
static volatile unsigned count;
/* We want to check this symbol in perf report */
noinline void test_loop(void);
static void sighandler(int sig __maybe_unused)
{
done = 1;
}
noinline void test_loop(void)
{
while (!done)
__atomic_fetch_add(&count, 1, __ATOMIC_RELAXED);
}
static void *thfunc(void *arg)
{
void (*loop_fn)(void) = arg;
loop_fn();
return NULL;
}
static int thloop(int argc, const char **argv)
{
int sec = 1;
pthread_t th;
if (argc > 0)
sec = atoi(argv[0]);
signal(SIGINT, sighandler);
signal(SIGALRM, sighandler);
alarm(sec);
pthread_create(&th, NULL, thfunc, test_loop);
test_loop();
pthread_join(th, NULL);
return 0;
}
DEFINE_WORKLOAD(thloop);
| linux-master | tools/perf/tests/workloads/thloop.c |
/* SPDX-License-Identifier: GPL-2.0 */
#include <stdlib.h>
#include "../tests.h"
#define BENCH_RUNS 999999
static volatile int cnt;
static void brstack_bar(void) {
} /* return */
static void brstack_foo(void) {
brstack_bar(); /* call */
} /* return */
static void brstack_bench(void) {
void (*brstack_foo_ind)(void) = brstack_foo;
if ((cnt++) % 3) /* branch (cond) */
brstack_foo(); /* call */
brstack_bar(); /* call */
brstack_foo_ind(); /* call (ind) */
}
static int brstack(int argc, const char **argv)
{
int num_loops = BENCH_RUNS;
if (argc > 0)
num_loops = atoi(argv[0]);
while (1) {
if ((cnt++) > num_loops)
break;
brstack_bench();/* call */
} /* branch (uncond) */
return 0;
}
DEFINE_WORKLOAD(brstack);
| linux-master | tools/perf/tests/workloads/brstack.c |
/* SPDX-License-Identifier: GPL-2.0 */
#include <math.h>
#include <signal.h>
#include <stdlib.h>
#include <unistd.h>
#include <linux/compiler.h>
#include <sys/wait.h>
#include "../tests.h"
static volatile sig_atomic_t done;
static void sighandler(int sig __maybe_unused)
{
done = 1;
}
static int __sqrtloop(int sec)
{
signal(SIGALRM, sighandler);
alarm(sec);
while (!done)
(void)sqrt(rand());
return 0;
}
static int sqrtloop(int argc, const char **argv)
{
int sec = 1;
if (argc > 0)
sec = atoi(argv[0]);
switch (fork()) {
case 0:
return __sqrtloop(sec);
case -1:
return -1;
default:
wait(NULL);
}
return 0;
}
DEFINE_WORKLOAD(sqrtloop);
| linux-master | tools/perf/tests/workloads/sqrtloop.c |
/* SPDX-License-Identifier: GPL-2.0 */
#include <stdlib.h>
#include <linux/compiler.h>
#include "../tests.h"
/* We want to check these symbols in perf script */
noinline void leaf(volatile int b);
noinline void parent(volatile int b);
static volatile int a;
noinline void leaf(volatile int b)
{
for (;;)
a += b;
}
noinline void parent(volatile int b)
{
leaf(b);
}
static int leafloop(int argc, const char **argv)
{
int c = 1;
if (argc > 0)
c = atoi(argv[0]);
parent(c);
return 0;
}
DEFINE_WORKLOAD(leafloop);
| linux-master | tools/perf/tests/workloads/leafloop.c |
#include <linux/compiler.h>
#include "../tests.h"
typedef struct _buf {
char data1;
char reserved[55];
char data2;
} buf __attribute__((aligned(64)));
static buf buf1 = {
/* to have this in the data section */
.reserved[0] = 1,
};
static int datasym(int argc __maybe_unused, const char **argv __maybe_unused)
{
for (;;) {
buf1.data1++;
buf1.data2 += buf1.data1;
}
return 0;
}
DEFINE_WORKLOAD(datasym);
| linux-master | tools/perf/tests/workloads/datasym.c |
/* SPDX-License-Identifier: GPL-2.0 */
#include <stdlib.h>
#include <signal.h>
#include <unistd.h>
#include <linux/compiler.h>
#include "../tests.h"
static volatile sig_atomic_t done;
static void sighandler(int sig __maybe_unused)
{
done = 1;
}
static int noploop(int argc, const char **argv)
{
int sec = 1;
if (argc > 0)
sec = atoi(argv[0]);
signal(SIGINT, sighandler);
signal(SIGALRM, sighandler);
alarm(sec);
while (!done)
continue;
return 0;
}
DEFINE_WORKLOAD(noploop);
| linux-master | tools/perf/tests/workloads/noploop.c |
// SPDX-License-Identifier: GPL-2.0
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "common.h"
#include "../util/env.h"
#include "../util/debug.h"
#include <linux/zalloc.h>
const char *const arc_triplets[] = {
"arc-linux-",
"arc-snps-linux-uclibc-",
"arc-snps-linux-gnu-",
NULL
};
const char *const arm_triplets[] = {
"arm-eabi-",
"arm-linux-androideabi-",
"arm-unknown-linux-",
"arm-unknown-linux-gnu-",
"arm-unknown-linux-gnueabi-",
"arm-linux-gnu-",
"arm-linux-gnueabihf-",
"arm-none-eabi-",
NULL
};
const char *const arm64_triplets[] = {
"aarch64-linux-android-",
"aarch64-linux-gnu-",
NULL
};
const char *const powerpc_triplets[] = {
"powerpc-unknown-linux-gnu-",
"powerpc-linux-gnu-",
"powerpc64-unknown-linux-gnu-",
"powerpc64-linux-gnu-",
"powerpc64le-linux-gnu-",
NULL
};
const char *const riscv32_triplets[] = {
"riscv32-unknown-linux-gnu-",
"riscv32-linux-android-",
"riscv32-linux-gnu-",
NULL
};
const char *const riscv64_triplets[] = {
"riscv64-unknown-linux-gnu-",
"riscv64-linux-android-",
"riscv64-linux-gnu-",
NULL
};
const char *const s390_triplets[] = {
"s390-ibm-linux-",
"s390x-linux-gnu-",
NULL
};
const char *const sh_triplets[] = {
"sh-unknown-linux-gnu-",
"sh-linux-gnu-",
NULL
};
const char *const sparc_triplets[] = {
"sparc-unknown-linux-gnu-",
"sparc64-unknown-linux-gnu-",
"sparc64-linux-gnu-",
NULL
};
const char *const x86_triplets[] = {
"x86_64-pc-linux-gnu-",
"x86_64-unknown-linux-gnu-",
"i686-pc-linux-gnu-",
"i586-pc-linux-gnu-",
"i486-pc-linux-gnu-",
"i386-pc-linux-gnu-",
"i686-linux-android-",
"i686-android-linux-",
"x86_64-linux-gnu-",
"i586-linux-gnu-",
NULL
};
const char *const mips_triplets[] = {
"mips-unknown-linux-gnu-",
"mipsel-linux-android-",
"mips-linux-gnu-",
"mips64-linux-gnu-",
"mips64el-linux-gnuabi64-",
"mips64-linux-gnuabi64-",
"mipsel-linux-gnu-",
NULL
};
static bool lookup_path(char *name)
{
bool found = false;
char *path, *tmp = NULL;
char buf[PATH_MAX];
char *env = getenv("PATH");
if (!env)
return false;
env = strdup(env);
if (!env)
return false;
path = strtok_r(env, ":", &tmp);
while (path) {
scnprintf(buf, sizeof(buf), "%s/%s", path, name);
if (access(buf, F_OK) == 0) {
found = true;
break;
}
path = strtok_r(NULL, ":", &tmp);
}
free(env);
return found;
}
static int lookup_triplets(const char *const *triplets, const char *name)
{
int i;
char buf[PATH_MAX];
for (i = 0; triplets[i] != NULL; i++) {
scnprintf(buf, sizeof(buf), "%s%s", triplets[i], name);
if (lookup_path(buf))
return i;
}
return -1;
}
static int perf_env__lookup_binutils_path(struct perf_env *env,
const char *name, char **path)
{
int idx;
const char *arch = perf_env__arch(env), *cross_env;
const char *const *path_list;
char *buf = NULL;
/*
* We don't need to try to find objdump path for native system.
* Just use default binutils path (e.g.: "objdump").
*/
if (!strcmp(perf_env__arch(NULL), arch))
goto out;
cross_env = getenv("CROSS_COMPILE");
if (cross_env) {
if (asprintf(&buf, "%s%s", cross_env, name) < 0)
goto out_error;
if (buf[0] == '/') {
if (access(buf, F_OK) == 0)
goto out;
goto out_error;
}
if (lookup_path(buf))
goto out;
zfree(&buf);
}
if (!strcmp(arch, "arc"))
path_list = arc_triplets;
else if (!strcmp(arch, "arm"))
path_list = arm_triplets;
else if (!strcmp(arch, "arm64"))
path_list = arm64_triplets;
else if (!strcmp(arch, "powerpc"))
path_list = powerpc_triplets;
else if (!strcmp(arch, "riscv32"))
path_list = riscv32_triplets;
else if (!strcmp(arch, "riscv64"))
path_list = riscv64_triplets;
else if (!strcmp(arch, "sh"))
path_list = sh_triplets;
else if (!strcmp(arch, "s390"))
path_list = s390_triplets;
else if (!strcmp(arch, "sparc"))
path_list = sparc_triplets;
else if (!strcmp(arch, "x86"))
path_list = x86_triplets;
else if (!strcmp(arch, "mips"))
path_list = mips_triplets;
else {
ui__error("binutils for %s not supported.\n", arch);
goto out_error;
}
idx = lookup_triplets(path_list, name);
if (idx < 0) {
ui__error("Please install %s for %s.\n"
"You can add it to PATH, set CROSS_COMPILE or "
"override the default using --%s.\n",
name, arch, name);
goto out_error;
}
if (asprintf(&buf, "%s%s", path_list[idx], name) < 0)
goto out_error;
out:
*path = buf;
return 0;
out_error:
free(buf);
*path = NULL;
return -1;
}
int perf_env__lookup_objdump(struct perf_env *env, char **path)
{
/*
* For live mode, env->arch will be NULL and we can use
* the native objdump tool.
*/
if (env->arch == NULL)
return 0;
return perf_env__lookup_binutils_path(env, "objdump", path);
}
/*
* Some architectures have a single address space for kernel and user addresses,
* which makes it possible to determine if an address is in kernel space or user
* space.
*/
bool perf_env__single_address_space(struct perf_env *env)
{
return strcmp(perf_env__arch(env), "sparc");
}
| linux-master | tools/perf/arch/common.c |
// SPDX-License-Identifier: GPL-2.0
static
struct ins_ops *riscv64__associate_ins_ops(struct arch *arch, const char *name)
{
struct ins_ops *ops = NULL;
if (!strncmp(name, "jal", 3) ||
!strncmp(name, "jr", 2) ||
!strncmp(name, "call", 4))
ops = &call_ops;
else if (!strncmp(name, "ret", 3))
ops = &ret_ops;
else if (name[0] == 'j' || name[0] == 'b')
ops = &jump_ops;
else
return NULL;
arch__associate_ins_ops(arch, name, ops);
return ops;
}
static
int riscv64__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
{
if (!arch->initialized) {
arch->associate_instruction_ops = riscv64__associate_ins_ops;
arch->initialized = true;
arch->objdump.comment_char = '#';
}
return 0;
}
| linux-master | tools/perf/arch/riscv64/annotate/instructions.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Mapping of DWARF debug register numbers into register names.
*
* Copyright (c) 2015 Cadence Design Systems Inc.
*/
#include <stddef.h>
#include <dwarf-regs.h>
#define XTENSA_MAX_REGS 16
const char *xtensa_regs_table[XTENSA_MAX_REGS] = {
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
"a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15",
};
const char *get_arch_regstr(unsigned int n)
{
return n < XTENSA_MAX_REGS ? xtensa_regs_table[n] : NULL;
}
| linux-master | tools/perf/arch/xtensa/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2015 Naveen N. Rao, IBM Corporation
*/
#include "dso.h"
#include "symbol.h"
#include "map.h"
#include "probe-event.h"
#include "probe-file.h"
int arch__choose_best_symbol(struct symbol *syma,
struct symbol *symb __maybe_unused)
{
char *sym = syma->name;
#if !defined(_CALL_ELF) || _CALL_ELF != 2
/* Skip over any initial dot */
if (*sym == '.')
sym++;
#endif
/* Avoid "SyS" kernel syscall aliases */
if (strlen(sym) >= 3 && !strncmp(sym, "SyS", 3))
return SYMBOL_B;
if (strlen(sym) >= 10 && !strncmp(sym, "compat_SyS", 10))
return SYMBOL_B;
return SYMBOL_A;
}
#if !defined(_CALL_ELF) || _CALL_ELF != 2
/* Allow matching against dot variants */
int arch__compare_symbol_names(const char *namea, const char *nameb)
{
/* Skip over initial dot */
if (*namea == '.')
namea++;
if (*nameb == '.')
nameb++;
return strcmp(namea, nameb);
}
int arch__compare_symbol_names_n(const char *namea, const char *nameb,
unsigned int n)
{
/* Skip over initial dot */
if (*namea == '.')
namea++;
if (*nameb == '.')
nameb++;
return strncmp(namea, nameb, n);
}
const char *arch__normalize_symbol_name(const char *name)
{
/* Skip over initial dot */
if (name && *name == '.')
name++;
return name;
}
#endif
#if defined(_CALL_ELF) && _CALL_ELF == 2
#ifdef HAVE_LIBELF_SUPPORT
void arch__sym_update(struct symbol *s, GElf_Sym *sym)
{
s->arch_sym = sym->st_other;
}
#endif
#define PPC64LE_LEP_OFFSET 8
void arch__fix_tev_from_maps(struct perf_probe_event *pev,
struct probe_trace_event *tev, struct map *map,
struct symbol *sym)
{
int lep_offset;
/*
* When probing at a function entry point, we normally always want the
* LEP since that catches calls to the function through both the GEP and
* the LEP. Hence, we would like to probe at an offset of 8 bytes if
* the user only specified the function entry.
*
* However, if the user specifies an offset, we fall back to using the
* GEP since all userspace applications (objdump/readelf) show function
* disassembly with offsets from the GEP.
*/
if (pev->point.offset || !map || !sym)
return;
/* For kretprobes, add an offset only if the kernel supports it */
if (!pev->uprobes && pev->point.retprobe) {
#ifdef HAVE_LIBELF_SUPPORT
if (!kretprobe_offset_is_supported())
#endif
return;
}
lep_offset = PPC64_LOCAL_ENTRY_OFFSET(sym->arch_sym);
if (map__dso(map)->symtab_type == DSO_BINARY_TYPE__KALLSYMS)
tev->point.offset += PPC64LE_LEP_OFFSET;
else if (lep_offset) {
if (pev->uprobes)
tev->point.address += lep_offset;
else
tev->point.offset += lep_offset;
}
}
#ifdef HAVE_LIBELF_SUPPORT
void arch__post_process_probe_trace_events(struct perf_probe_event *pev,
int ntevs)
{
struct probe_trace_event *tev;
struct map *map;
struct symbol *sym = NULL;
struct rb_node *tmp;
int i = 0;
map = get_target_map(pev->target, pev->nsi, pev->uprobes);
if (!map || map__load(map) < 0)
return;
for (i = 0; i < ntevs; i++) {
tev = &pev->tevs[i];
map__for_each_symbol(map, sym, tmp) {
if (map__unmap_ip(map, sym->start) == tev->point.address) {
arch__fix_tev_from_maps(pev, tev, map, sym);
break;
}
}
}
}
#endif /* HAVE_LIBELF_SUPPORT */
#endif
| linux-master | tools/perf/arch/powerpc/util/sym-handling.c |
// SPDX-License-Identifier: GPL-2.0
#include "map_symbol.h"
#include "mem-events.h"
/* PowerPC does not support 'ldlat' parameter. */
const char *perf_mem_events__name(int i, const char *pmu_name __maybe_unused)
{
if (i == PERF_MEM_EVENTS__LOAD)
return "cpu/mem-loads/";
return "cpu/mem-stores/";
}
| linux-master | tools/perf/arch/powerpc/util/mem-events.c |
// SPDX-License-Identifier: GPL-2.0
#include <elfutils/libdwfl.h>
#include <linux/kernel.h>
#include "perf_regs.h"
#include "../../../util/unwind-libdw.h"
#include "../../../util/perf_regs.h"
#include "../../../util/sample.h"
/* See backends/ppc_initreg.c and backends/ppc_regs.c in elfutils. */
static const int special_regs[3][2] = {
{ 65, PERF_REG_POWERPC_LINK },
{ 101, PERF_REG_POWERPC_XER },
{ 109, PERF_REG_POWERPC_CTR },
};
bool libdw__arch_set_initial_registers(Dwfl_Thread *thread, void *arg)
{
struct unwind_info *ui = arg;
struct regs_dump *user_regs = &ui->sample->user_regs;
Dwarf_Word dwarf_regs[32], dwarf_nip;
size_t i;
#define REG(r) ({ \
Dwarf_Word val = 0; \
perf_reg_value(&val, user_regs, PERF_REG_POWERPC_##r); \
val; \
})
dwarf_regs[0] = REG(R0);
dwarf_regs[1] = REG(R1);
dwarf_regs[2] = REG(R2);
dwarf_regs[3] = REG(R3);
dwarf_regs[4] = REG(R4);
dwarf_regs[5] = REG(R5);
dwarf_regs[6] = REG(R6);
dwarf_regs[7] = REG(R7);
dwarf_regs[8] = REG(R8);
dwarf_regs[9] = REG(R9);
dwarf_regs[10] = REG(R10);
dwarf_regs[11] = REG(R11);
dwarf_regs[12] = REG(R12);
dwarf_regs[13] = REG(R13);
dwarf_regs[14] = REG(R14);
dwarf_regs[15] = REG(R15);
dwarf_regs[16] = REG(R16);
dwarf_regs[17] = REG(R17);
dwarf_regs[18] = REG(R18);
dwarf_regs[19] = REG(R19);
dwarf_regs[20] = REG(R20);
dwarf_regs[21] = REG(R21);
dwarf_regs[22] = REG(R22);
dwarf_regs[23] = REG(R23);
dwarf_regs[24] = REG(R24);
dwarf_regs[25] = REG(R25);
dwarf_regs[26] = REG(R26);
dwarf_regs[27] = REG(R27);
dwarf_regs[28] = REG(R28);
dwarf_regs[29] = REG(R29);
dwarf_regs[30] = REG(R30);
dwarf_regs[31] = REG(R31);
if (!dwfl_thread_state_registers(thread, 0, 32, dwarf_regs))
return false;
dwarf_nip = REG(NIP);
dwfl_thread_state_register_pc(thread, dwarf_nip);
for (i = 0; i < ARRAY_SIZE(special_regs); i++) {
Dwarf_Word val = 0;
perf_reg_value(&val, user_regs, special_regs[i][1]);
if (!dwfl_thread_state_registers(thread,
special_regs[i][0], 1,
&val))
return false;
}
return true;
}
| linux-master | tools/perf/arch/powerpc/util/unwind-libdw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Use DWARF Debug information to skip unnecessary callchain entries.
*
* Copyright (C) 2014 Sukadev Bhattiprolu, IBM Corporation.
* Copyright (C) 2014 Ulrich Weigand, IBM Corporation.
*/
#include <inttypes.h>
#include <dwarf.h>
#include <elfutils/libdwfl.h>
#include "util/thread.h"
#include "util/callchain.h"
#include "util/debug.h"
#include "util/dso.h"
#include "util/event.h" // struct ip_callchain
#include "util/map.h"
#include "util/symbol.h"
/*
* When saving the callchain on Power, the kernel conservatively saves
* excess entries in the callchain. A few of these entries are needed
* in some cases but not others. If the unnecessary entries are not
* ignored, we end up with duplicate arcs in the call-graphs. Use
* DWARF debug information to skip over any unnecessary callchain
* entries.
*
* See function header for arch_adjust_callchain() below for more details.
*
* The libdwfl code in this file is based on code from elfutils
* (libdwfl/argp-std.c, libdwfl/tests/addrcfi.c, etc).
*/
static char *debuginfo_path;
static const Dwfl_Callbacks offline_callbacks = {
.debuginfo_path = &debuginfo_path,
.find_debuginfo = dwfl_standard_find_debuginfo,
.section_address = dwfl_offline_section_address,
};
/*
* Use the DWARF expression for the Call-frame-address and determine
* if return address is in LR and if a new frame was allocated.
*/
static int check_return_reg(int ra_regno, Dwarf_Frame *frame)
{
Dwarf_Op ops_mem[3];
Dwarf_Op dummy;
Dwarf_Op *ops = &dummy;
size_t nops;
int result;
result = dwarf_frame_register(frame, ra_regno, ops_mem, &ops, &nops);
if (result < 0) {
pr_debug("dwarf_frame_register() %s\n", dwarf_errmsg(-1));
return -1;
}
/*
* Check if return address is on the stack. If return address
* is in a register (typically R0), it is yet to be saved on
* the stack.
*/
if ((nops != 0 || ops != NULL) &&
!(nops == 1 && ops[0].atom == DW_OP_regx &&
ops[0].number2 == 0 && ops[0].offset == 0))
return 0;
/*
* Return address is in LR. Check if a frame was allocated
* but not-yet used.
*/
result = dwarf_frame_cfa(frame, &ops, &nops);
if (result < 0) {
pr_debug("dwarf_frame_cfa() returns %d, %s\n", result,
dwarf_errmsg(-1));
return -1;
}
/*
* If call frame address is in r1, no new frame was allocated.
*/
if (nops == 1 && ops[0].atom == DW_OP_bregx && ops[0].number == 1 &&
ops[0].number2 == 0)
return 1;
/*
* A new frame was allocated but has not yet been used.
*/
return 2;
}
/*
* Get the DWARF frame from the .eh_frame section.
*/
static Dwarf_Frame *get_eh_frame(Dwfl_Module *mod, Dwarf_Addr pc)
{
int result;
Dwarf_Addr bias;
Dwarf_CFI *cfi;
Dwarf_Frame *frame;
cfi = dwfl_module_eh_cfi(mod, &bias);
if (!cfi) {
pr_debug("%s(): no CFI - %s\n", __func__, dwfl_errmsg(-1));
return NULL;
}
result = dwarf_cfi_addrframe(cfi, pc-bias, &frame);
if (result) {
pr_debug("%s(): %s\n", __func__, dwfl_errmsg(-1));
return NULL;
}
return frame;
}
/*
* Get the DWARF frame from the .debug_frame section.
*/
static Dwarf_Frame *get_dwarf_frame(Dwfl_Module *mod, Dwarf_Addr pc)
{
Dwarf_CFI *cfi;
Dwarf_Addr bias;
Dwarf_Frame *frame;
int result;
cfi = dwfl_module_dwarf_cfi(mod, &bias);
if (!cfi) {
pr_debug("%s(): no CFI - %s\n", __func__, dwfl_errmsg(-1));
return NULL;
}
result = dwarf_cfi_addrframe(cfi, pc-bias, &frame);
if (result) {
pr_debug("%s(): %s\n", __func__, dwfl_errmsg(-1));
return NULL;
}
return frame;
}
/*
* Return:
* 0 if return address for the program counter @pc is on stack
* 1 if return address is in LR and no new stack frame was allocated
* 2 if return address is in LR and a new frame was allocated (but not
* yet used)
* -1 in case of errors
*/
static int check_return_addr(struct dso *dso, u64 map_start, Dwarf_Addr pc)
{
int rc = -1;
Dwfl *dwfl;
Dwfl_Module *mod;
Dwarf_Frame *frame;
int ra_regno;
Dwarf_Addr start = pc;
Dwarf_Addr end = pc;
bool signalp;
const char *exec_file = dso->long_name;
dwfl = dso->dwfl;
if (!dwfl) {
dwfl = dwfl_begin(&offline_callbacks);
if (!dwfl) {
pr_debug("dwfl_begin() failed: %s\n", dwarf_errmsg(-1));
return -1;
}
mod = dwfl_report_elf(dwfl, exec_file, exec_file, -1,
map_start, false);
if (!mod) {
pr_debug("dwfl_report_elf() failed %s\n",
dwarf_errmsg(-1));
/*
* We normally cache the DWARF debug info and never
* call dwfl_end(). But to prevent fd leak, free in
* case of error.
*/
dwfl_end(dwfl);
goto out;
}
dso->dwfl = dwfl;
}
mod = dwfl_addrmodule(dwfl, pc);
if (!mod) {
pr_debug("dwfl_addrmodule() failed, %s\n", dwarf_errmsg(-1));
goto out;
}
/*
* To work with split debug info files (eg: glibc), check both
* .eh_frame and .debug_frame sections of the ELF header.
*/
frame = get_eh_frame(mod, pc);
if (!frame) {
frame = get_dwarf_frame(mod, pc);
if (!frame)
goto out;
}
ra_regno = dwarf_frame_info(frame, &start, &end, &signalp);
if (ra_regno < 0) {
pr_debug("Return address register unavailable: %s\n",
dwarf_errmsg(-1));
goto out;
}
rc = check_return_reg(ra_regno, frame);
out:
return rc;
}
/*
* The callchain saved by the kernel always includes the link register (LR).
*
* 0: PERF_CONTEXT_USER
* 1: Program counter (Next instruction pointer)
* 2: LR value
* 3: Caller's caller
* 4: ...
*
* The value in LR is only needed when it holds a return address. If the
* return address is on the stack, we should ignore the LR value.
*
* Further, when the return address is in the LR, if a new frame was just
* allocated but the LR was not saved into it, then the LR contains the
* caller, slot 4: contains the caller's caller and the contents of slot 3:
* (chain->ips[3]) is undefined and must be ignored.
*
* Use DWARF debug information to determine if any entries need to be skipped.
*
* Return:
* index: of callchain entry that needs to be ignored (if any)
* -1 if no entry needs to be ignored or in case of errors
*/
int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain)
{
struct addr_location al;
struct dso *dso = NULL;
int rc;
u64 ip;
u64 skip_slot = -1;
if (!chain || chain->nr < 3)
return skip_slot;
addr_location__init(&al);
ip = chain->ips[1];
thread__find_symbol(thread, PERF_RECORD_MISC_USER, ip, &al);
if (al.map)
dso = map__dso(al.map);
if (!dso) {
pr_debug("%" PRIx64 " dso is NULL\n", ip);
addr_location__exit(&al);
return skip_slot;
}
rc = check_return_addr(dso, map__start(al.map), ip);
pr_debug("[DSO %s, sym %s, ip 0x%" PRIx64 "] rc %d\n",
dso->long_name, al.sym->name, ip, rc);
if (rc == 0) {
/*
* Return address on stack. Ignore LR value in callchain
*/
skip_slot = 2;
} else if (rc == 2) {
/*
* New frame allocated but return address still in LR.
* Ignore the caller's caller entry in callchain.
*/
skip_slot = 3;
}
addr_location__exit(&al);
return skip_slot;
}
| linux-master | tools/perf/arch/powerpc/util/skip-callchain-idx.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include "util/kvm-stat.h"
#include "util/parse-events.h"
#include "util/debug.h"
#include "util/evsel.h"
#include "util/evlist.h"
#include "util/pmus.h"
#include "book3s_hv_exits.h"
#include "book3s_hcalls.h"
#include <subcmd/parse-options.h>
#define NR_TPS 4
const char *vcpu_id_str = "vcpu_id";
const char *kvm_entry_trace = "kvm_hv:kvm_guest_enter";
const char *kvm_exit_trace = "kvm_hv:kvm_guest_exit";
define_exit_reasons_table(hv_exit_reasons, kvm_trace_symbol_exit);
define_exit_reasons_table(hcall_reasons, kvm_trace_symbol_hcall);
/* Tracepoints specific to ppc_book3s_hv */
const char *ppc_book3s_hv_kvm_tp[] = {
"kvm_hv:kvm_guest_enter",
"kvm_hv:kvm_guest_exit",
"kvm_hv:kvm_hcall_enter",
"kvm_hv:kvm_hcall_exit",
NULL,
};
/* 1 extra placeholder for NULL */
const char *kvm_events_tp[NR_TPS + 1];
const char *kvm_exit_reason;
static void hcall_event_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
key->info = 0;
key->key = evsel__intval(evsel, sample, "req");
}
static const char *get_hcall_exit_reason(u64 exit_code)
{
struct exit_reasons_table *tbl = hcall_reasons;
while (tbl->reason != NULL) {
if (tbl->exit_code == exit_code)
return tbl->reason;
tbl++;
}
pr_debug("Unknown hcall code: %lld\n",
(unsigned long long)exit_code);
return "UNKNOWN";
}
static bool hcall_event_end(struct evsel *evsel,
struct perf_sample *sample __maybe_unused,
struct event_key *key __maybe_unused)
{
return (evsel__name_is(evsel, kvm_events_tp[3]));
}
static bool hcall_event_begin(struct evsel *evsel,
struct perf_sample *sample, struct event_key *key)
{
if (evsel__name_is(evsel, kvm_events_tp[2])) {
hcall_event_get_key(evsel, sample, key);
return true;
}
return false;
}
static void hcall_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused,
struct event_key *key,
char *decode)
{
const char *hcall_reason = get_hcall_exit_reason(key->key);
scnprintf(decode, KVM_EVENT_NAME_LEN, "%s", hcall_reason);
}
static struct kvm_events_ops hcall_events = {
.is_begin_event = hcall_event_begin,
.is_end_event = hcall_event_end,
.decode_key = hcall_event_decode_key,
.name = "HCALL-EVENT",
};
static struct kvm_events_ops exit_events = {
.is_begin_event = exit_event_begin,
.is_end_event = exit_event_end,
.decode_key = exit_event_decode_key,
.name = "VM-EXIT"
};
struct kvm_reg_events_ops kvm_reg_events_ops[] = {
{ .name = "vmexit", .ops = &exit_events },
{ .name = "hcall", .ops = &hcall_events },
{ NULL, NULL },
};
const char * const kvm_skip_events[] = {
NULL,
};
static int is_tracepoint_available(const char *str, struct evlist *evlist)
{
struct parse_events_error err;
int ret;
parse_events_error__init(&err);
ret = parse_events(evlist, str, &err);
if (err.str)
parse_events_error__print(&err, "tracepoint");
parse_events_error__exit(&err);
return ret;
}
static int ppc__setup_book3s_hv(struct perf_kvm_stat *kvm,
struct evlist *evlist)
{
const char **events_ptr;
int i, nr_tp = 0, err = -1;
/* Check for book3s_hv tracepoints */
for (events_ptr = ppc_book3s_hv_kvm_tp; *events_ptr; events_ptr++) {
err = is_tracepoint_available(*events_ptr, evlist);
if (err)
return -1;
nr_tp++;
}
for (i = 0; i < nr_tp; i++)
kvm_events_tp[i] = ppc_book3s_hv_kvm_tp[i];
kvm_events_tp[i] = NULL;
kvm_exit_reason = "trap";
kvm->exit_reasons = hv_exit_reasons;
kvm->exit_reasons_isa = "HV";
return 0;
}
/* Wrapper to setup kvm tracepoints */
static int ppc__setup_kvm_tp(struct perf_kvm_stat *kvm)
{
struct evlist *evlist = evlist__new();
if (evlist == NULL)
return -ENOMEM;
/* Right now, only supported on book3s_hv */
return ppc__setup_book3s_hv(kvm, evlist);
}
int setup_kvm_events_tp(struct perf_kvm_stat *kvm)
{
return ppc__setup_kvm_tp(kvm);
}
int cpu_isa_init(struct perf_kvm_stat *kvm, const char *cpuid __maybe_unused)
{
int ret;
ret = ppc__setup_kvm_tp(kvm);
if (ret) {
kvm->exit_reasons = NULL;
kvm->exit_reasons_isa = NULL;
}
return ret;
}
/*
* In case of powerpc architecture, pmu registers are programmable
* by guest kernel. So monitoring guest via host may not provide
* valid samples with default 'cycles' event. It is better to use
* 'trace_imc/trace_cycles' event for guest profiling, since it
* can track the guest instruction pointer in the trace-record.
*
* Function to parse the arguments and return appropriate values.
*/
int kvm_add_default_arch_event(int *argc, const char **argv)
{
const char **tmp;
bool event = false;
int i, j = *argc;
const struct option event_options[] = {
OPT_BOOLEAN('e', "event", &event, NULL),
OPT_END()
};
tmp = calloc(j + 1, sizeof(char *));
if (!tmp)
return -EINVAL;
for (i = 0; i < j; i++)
tmp[i] = argv[i];
parse_options(j, tmp, event_options, NULL, PARSE_OPT_KEEP_UNKNOWN);
if (!event) {
if (perf_pmus__have_event("trace_imc", "trace_cycles")) {
argv[j++] = strdup("-e");
argv[j++] = strdup("trace_imc/trace_cycles/");
*argc += 2;
} else {
free(tmp);
return -EINVAL;
}
}
free(tmp);
return 0;
}
| linux-master | tools/perf/arch/powerpc/util/kvm-stat.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Mapping of DWARF debug register numbers into register names.
*
* Copyright (C) 2010 Ian Munsie, IBM Corporation.
*/
#include <stddef.h>
#include <errno.h>
#include <string.h>
#include <dwarf-regs.h>
#include <linux/ptrace.h>
#include <linux/kernel.h>
#include <linux/stringify.h>
struct pt_regs_dwarfnum {
const char *name;
unsigned int dwarfnum;
unsigned int ptregs_offset;
};
#define REG_DWARFNUM_NAME(r, num) \
{.name = __stringify(%)__stringify(r), .dwarfnum = num, \
.ptregs_offset = offsetof(struct pt_regs, r)}
#define GPR_DWARFNUM_NAME(num) \
{.name = __stringify(%gpr##num), .dwarfnum = num, \
.ptregs_offset = offsetof(struct pt_regs, gpr[num])}
#define REG_DWARFNUM_END {.name = NULL, .dwarfnum = 0, .ptregs_offset = 0}
/*
* Reference:
* http://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html
*/
static const struct pt_regs_dwarfnum regdwarfnum_table[] = {
GPR_DWARFNUM_NAME(0),
GPR_DWARFNUM_NAME(1),
GPR_DWARFNUM_NAME(2),
GPR_DWARFNUM_NAME(3),
GPR_DWARFNUM_NAME(4),
GPR_DWARFNUM_NAME(5),
GPR_DWARFNUM_NAME(6),
GPR_DWARFNUM_NAME(7),
GPR_DWARFNUM_NAME(8),
GPR_DWARFNUM_NAME(9),
GPR_DWARFNUM_NAME(10),
GPR_DWARFNUM_NAME(11),
GPR_DWARFNUM_NAME(12),
GPR_DWARFNUM_NAME(13),
GPR_DWARFNUM_NAME(14),
GPR_DWARFNUM_NAME(15),
GPR_DWARFNUM_NAME(16),
GPR_DWARFNUM_NAME(17),
GPR_DWARFNUM_NAME(18),
GPR_DWARFNUM_NAME(19),
GPR_DWARFNUM_NAME(20),
GPR_DWARFNUM_NAME(21),
GPR_DWARFNUM_NAME(22),
GPR_DWARFNUM_NAME(23),
GPR_DWARFNUM_NAME(24),
GPR_DWARFNUM_NAME(25),
GPR_DWARFNUM_NAME(26),
GPR_DWARFNUM_NAME(27),
GPR_DWARFNUM_NAME(28),
GPR_DWARFNUM_NAME(29),
GPR_DWARFNUM_NAME(30),
GPR_DWARFNUM_NAME(31),
REG_DWARFNUM_NAME(msr, 66),
REG_DWARFNUM_NAME(ctr, 109),
REG_DWARFNUM_NAME(link, 108),
REG_DWARFNUM_NAME(xer, 101),
REG_DWARFNUM_NAME(dar, 119),
REG_DWARFNUM_NAME(dsisr, 118),
REG_DWARFNUM_END,
};
/**
* get_arch_regstr() - lookup register name from it's DWARF register number
* @n: the DWARF register number
*
* get_arch_regstr() returns the name of the register in struct
* regdwarfnum_table from it's DWARF register number. If the register is not
* found in the table, this returns NULL;
*/
const char *get_arch_regstr(unsigned int n)
{
const struct pt_regs_dwarfnum *roff;
for (roff = regdwarfnum_table; roff->name != NULL; roff++)
if (roff->dwarfnum == n)
return roff->name;
return NULL;
}
int regs_query_register_offset(const char *name)
{
const struct pt_regs_dwarfnum *roff;
for (roff = regdwarfnum_table; roff->name != NULL; roff++)
if (!strcmp(roff->name, name))
return roff->ptregs_offset;
return -EINVAL;
}
| linux-master | tools/perf/arch/powerpc/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <linux/string.h>
#include <linux/zalloc.h>
#include "../../../util/event.h"
#include "../../../util/synthetic-events.h"
#include "../../../util/machine.h"
#include "../../../util/tool.h"
#include "../../../util/map.h"
#include "../../../util/debug.h"
#include "../../../util/sample.h"
void arch_perf_parse_sample_weight(struct perf_sample *data,
const __u64 *array, u64 type)
{
union perf_sample_weight weight;
weight.full = *array;
if (type & PERF_SAMPLE_WEIGHT)
data->weight = weight.full;
else {
data->weight = weight.var1_dw;
data->ins_lat = weight.var2_w;
data->p_stage_cyc = weight.var3_w;
}
}
void arch_perf_synthesize_sample_weight(const struct perf_sample *data,
__u64 *array, u64 type)
{
*array = data->weight;
if (type & PERF_SAMPLE_WEIGHT_STRUCT) {
*array &= 0xffffffff;
*array |= ((u64)data->ins_lat << 32);
}
}
const char *arch_perf_header_entry(const char *se_header)
{
if (!strcmp(se_header, "Local INSTR Latency"))
return "Finish Cyc";
else if (!strcmp(se_header, "INSTR Latency"))
return "Global Finish_cyc";
else if (!strcmp(se_header, "Local Pipeline Stage Cycle"))
return "Dispatch Cyc";
else if (!strcmp(se_header, "Pipeline Stage Cycle"))
return "Global Dispatch_cyc";
return se_header;
}
int arch_support_sort_key(const char *sort_key)
{
if (!strcmp(sort_key, "p_stage_cyc"))
return 1;
if (!strcmp(sort_key, "local_p_stage_cyc"))
return 1;
return 0;
}
| linux-master | tools/perf/arch/powerpc/util/event.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2016 Chandan Kumar, IBM Corporation.
*/
#include <errno.h>
#include <libunwind.h>
#include <asm/perf_regs.h>
#include "../../util/unwind.h"
#include "../../util/debug.h"
int libunwind__arch_reg_id(int regnum)
{
switch (regnum) {
case UNW_PPC64_R0:
return PERF_REG_POWERPC_R0;
case UNW_PPC64_R1:
return PERF_REG_POWERPC_R1;
case UNW_PPC64_R2:
return PERF_REG_POWERPC_R2;
case UNW_PPC64_R3:
return PERF_REG_POWERPC_R3;
case UNW_PPC64_R4:
return PERF_REG_POWERPC_R4;
case UNW_PPC64_R5:
return PERF_REG_POWERPC_R5;
case UNW_PPC64_R6:
return PERF_REG_POWERPC_R6;
case UNW_PPC64_R7:
return PERF_REG_POWERPC_R7;
case UNW_PPC64_R8:
return PERF_REG_POWERPC_R8;
case UNW_PPC64_R9:
return PERF_REG_POWERPC_R9;
case UNW_PPC64_R10:
return PERF_REG_POWERPC_R10;
case UNW_PPC64_R11:
return PERF_REG_POWERPC_R11;
case UNW_PPC64_R12:
return PERF_REG_POWERPC_R12;
case UNW_PPC64_R13:
return PERF_REG_POWERPC_R13;
case UNW_PPC64_R14:
return PERF_REG_POWERPC_R14;
case UNW_PPC64_R15:
return PERF_REG_POWERPC_R15;
case UNW_PPC64_R16:
return PERF_REG_POWERPC_R16;
case UNW_PPC64_R17:
return PERF_REG_POWERPC_R17;
case UNW_PPC64_R18:
return PERF_REG_POWERPC_R18;
case UNW_PPC64_R19:
return PERF_REG_POWERPC_R19;
case UNW_PPC64_R20:
return PERF_REG_POWERPC_R20;
case UNW_PPC64_R21:
return PERF_REG_POWERPC_R21;
case UNW_PPC64_R22:
return PERF_REG_POWERPC_R22;
case UNW_PPC64_R23:
return PERF_REG_POWERPC_R23;
case UNW_PPC64_R24:
return PERF_REG_POWERPC_R24;
case UNW_PPC64_R25:
return PERF_REG_POWERPC_R25;
case UNW_PPC64_R26:
return PERF_REG_POWERPC_R26;
case UNW_PPC64_R27:
return PERF_REG_POWERPC_R27;
case UNW_PPC64_R28:
return PERF_REG_POWERPC_R28;
case UNW_PPC64_R29:
return PERF_REG_POWERPC_R29;
case UNW_PPC64_R30:
return PERF_REG_POWERPC_R30;
case UNW_PPC64_R31:
return PERF_REG_POWERPC_R31;
case UNW_PPC64_LR:
return PERF_REG_POWERPC_LINK;
case UNW_PPC64_CTR:
return PERF_REG_POWERPC_CTR;
case UNW_PPC64_XER:
return PERF_REG_POWERPC_XER;
case UNW_PPC64_NIP:
return PERF_REG_POWERPC_NIP;
default:
pr_err("unwind: invalid reg id %d\n", regnum);
return -EINVAL;
}
return -EINVAL;
}
| linux-master | tools/perf/arch/powerpc/util/unwind-libunwind.c |
// SPDX-License-Identifier: GPL-2.0
#include <sys/types.h>
#include <errno.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <linux/stringify.h>
#include "header.h"
#include "utils_header.h"
#include "metricgroup.h"
#include <api/fs/fs.h>
int
get_cpuid(char *buffer, size_t sz)
{
unsigned long pvr;
int nb;
pvr = mfspr(SPRN_PVR);
nb = scnprintf(buffer, sz, "%lu,%lu$", PVR_VER(pvr), PVR_REV(pvr));
/* look for end marker to ensure the entire data fit */
if (strchr(buffer, '$')) {
buffer[nb-1] = '\0';
return 0;
}
return ENOBUFS;
}
char *
get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
{
char *bufp;
if (asprintf(&bufp, "%.8lx", mfspr(SPRN_PVR)) < 0)
bufp = NULL;
return bufp;
}
int arch_get_runtimeparam(const struct pmu_metric *pm)
{
int count;
char path[PATH_MAX] = "/devices/hv_24x7/interface/";
strcat(path, pm->aggr_mode == PerChip ? "sockets" : "coresperchip");
return sysfs__read_int(path, &count) < 0 ? 1 : count;
}
| linux-master | tools/perf/arch/powerpc/util/header.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include <string.h>
#include <regex.h>
#include <linux/zalloc.h>
#include "perf_regs.h"
#include "../../../util/perf_regs.h"
#include "../../../util/debug.h"
#include "../../../util/event.h"
#include "../../../util/header.h"
#include "../../../perf-sys.h"
#include "utils_header.h"
#include <linux/kernel.h>
#define PVR_POWER9 0x004E
#define PVR_POWER10 0x0080
const struct sample_reg sample_reg_masks[] = {
SMPL_REG(r0, PERF_REG_POWERPC_R0),
SMPL_REG(r1, PERF_REG_POWERPC_R1),
SMPL_REG(r2, PERF_REG_POWERPC_R2),
SMPL_REG(r3, PERF_REG_POWERPC_R3),
SMPL_REG(r4, PERF_REG_POWERPC_R4),
SMPL_REG(r5, PERF_REG_POWERPC_R5),
SMPL_REG(r6, PERF_REG_POWERPC_R6),
SMPL_REG(r7, PERF_REG_POWERPC_R7),
SMPL_REG(r8, PERF_REG_POWERPC_R8),
SMPL_REG(r9, PERF_REG_POWERPC_R9),
SMPL_REG(r10, PERF_REG_POWERPC_R10),
SMPL_REG(r11, PERF_REG_POWERPC_R11),
SMPL_REG(r12, PERF_REG_POWERPC_R12),
SMPL_REG(r13, PERF_REG_POWERPC_R13),
SMPL_REG(r14, PERF_REG_POWERPC_R14),
SMPL_REG(r15, PERF_REG_POWERPC_R15),
SMPL_REG(r16, PERF_REG_POWERPC_R16),
SMPL_REG(r17, PERF_REG_POWERPC_R17),
SMPL_REG(r18, PERF_REG_POWERPC_R18),
SMPL_REG(r19, PERF_REG_POWERPC_R19),
SMPL_REG(r20, PERF_REG_POWERPC_R20),
SMPL_REG(r21, PERF_REG_POWERPC_R21),
SMPL_REG(r22, PERF_REG_POWERPC_R22),
SMPL_REG(r23, PERF_REG_POWERPC_R23),
SMPL_REG(r24, PERF_REG_POWERPC_R24),
SMPL_REG(r25, PERF_REG_POWERPC_R25),
SMPL_REG(r26, PERF_REG_POWERPC_R26),
SMPL_REG(r27, PERF_REG_POWERPC_R27),
SMPL_REG(r28, PERF_REG_POWERPC_R28),
SMPL_REG(r29, PERF_REG_POWERPC_R29),
SMPL_REG(r30, PERF_REG_POWERPC_R30),
SMPL_REG(r31, PERF_REG_POWERPC_R31),
SMPL_REG(nip, PERF_REG_POWERPC_NIP),
SMPL_REG(msr, PERF_REG_POWERPC_MSR),
SMPL_REG(orig_r3, PERF_REG_POWERPC_ORIG_R3),
SMPL_REG(ctr, PERF_REG_POWERPC_CTR),
SMPL_REG(link, PERF_REG_POWERPC_LINK),
SMPL_REG(xer, PERF_REG_POWERPC_XER),
SMPL_REG(ccr, PERF_REG_POWERPC_CCR),
SMPL_REG(softe, PERF_REG_POWERPC_SOFTE),
SMPL_REG(trap, PERF_REG_POWERPC_TRAP),
SMPL_REG(dar, PERF_REG_POWERPC_DAR),
SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),
SMPL_REG(sier, PERF_REG_POWERPC_SIER),
SMPL_REG(mmcra, PERF_REG_POWERPC_MMCRA),
SMPL_REG(mmcr0, PERF_REG_POWERPC_MMCR0),
SMPL_REG(mmcr1, PERF_REG_POWERPC_MMCR1),
SMPL_REG(mmcr2, PERF_REG_POWERPC_MMCR2),
SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3),
SMPL_REG(sier2, PERF_REG_POWERPC_SIER2),
SMPL_REG(sier3, PERF_REG_POWERPC_SIER3),
SMPL_REG(pmc1, PERF_REG_POWERPC_PMC1),
SMPL_REG(pmc2, PERF_REG_POWERPC_PMC2),
SMPL_REG(pmc3, PERF_REG_POWERPC_PMC3),
SMPL_REG(pmc4, PERF_REG_POWERPC_PMC4),
SMPL_REG(pmc5, PERF_REG_POWERPC_PMC5),
SMPL_REG(pmc6, PERF_REG_POWERPC_PMC6),
SMPL_REG(sdar, PERF_REG_POWERPC_SDAR),
SMPL_REG(siar, PERF_REG_POWERPC_SIAR),
SMPL_REG_END
};
/* REG or %rREG */
#define SDT_OP_REGEX1 "^(%r)?([1-2]?[0-9]|3[0-1])$"
/* -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) */
#define SDT_OP_REGEX2 "^(\\-)?([0-9]+)\\((%r)?([1-2]?[0-9]|3[0-1])\\)$"
static regex_t sdt_op_regex1, sdt_op_regex2;
static int sdt_init_op_regex(void)
{
static int initialized;
int ret = 0;
if (initialized)
return 0;
ret = regcomp(&sdt_op_regex1, SDT_OP_REGEX1, REG_EXTENDED);
if (ret)
goto error;
ret = regcomp(&sdt_op_regex2, SDT_OP_REGEX2, REG_EXTENDED);
if (ret)
goto free_regex1;
initialized = 1;
return 0;
free_regex1:
regfree(&sdt_op_regex1);
error:
pr_debug4("Regex compilation error.\n");
return ret;
}
/*
* Parse OP and convert it into uprobe format, which is, +/-NUM(%gprREG).
* Possible variants of OP are:
* Format Example
* -------------------------
* NUM(REG) 48(18)
* -NUM(REG) -48(18)
* NUM(%rREG) 48(%r18)
* -NUM(%rREG) -48(%r18)
* REG 18
* %rREG %r18
* iNUM i0
* i-NUM i-1
*
* SDT marker arguments on Powerpc uses %rREG form with -mregnames flag
* and REG form with -mno-regnames. Here REG is general purpose register,
* which is in 0 to 31 range.
*/
int arch_sdt_arg_parse_op(char *old_op, char **new_op)
{
int ret, new_len;
regmatch_t rm[5];
char prefix;
/* Constant argument. Uprobe does not support it */
if (old_op[0] == 'i') {
pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
return SDT_ARG_SKIP;
}
ret = sdt_init_op_regex();
if (ret < 0)
return ret;
if (!regexec(&sdt_op_regex1, old_op, 3, rm, 0)) {
/* REG or %rREG --> %gprREG */
new_len = 5; /* % g p r NULL */
new_len += (int)(rm[2].rm_eo - rm[2].rm_so);
*new_op = zalloc(new_len);
if (!*new_op)
return -ENOMEM;
scnprintf(*new_op, new_len, "%%gpr%.*s",
(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so);
} else if (!regexec(&sdt_op_regex2, old_op, 5, rm, 0)) {
/*
* -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) -->
* +/-NUM(%gprREG)
*/
prefix = (rm[1].rm_so == -1) ? '+' : '-';
new_len = 8; /* +/- ( % g p r ) NULL */
new_len += (int)(rm[2].rm_eo - rm[2].rm_so);
new_len += (int)(rm[4].rm_eo - rm[4].rm_so);
*new_op = zalloc(new_len);
if (!*new_op)
return -ENOMEM;
scnprintf(*new_op, new_len, "%c%.*s(%%gpr%.*s)", prefix,
(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so,
(int)(rm[4].rm_eo - rm[4].rm_so), old_op + rm[4].rm_so);
} else {
pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
return SDT_ARG_SKIP;
}
return SDT_ARG_VALID;
}
uint64_t arch__intr_reg_mask(void)
{
struct perf_event_attr attr = {
.type = PERF_TYPE_HARDWARE,
.config = PERF_COUNT_HW_CPU_CYCLES,
.sample_type = PERF_SAMPLE_REGS_INTR,
.precise_ip = 1,
.disabled = 1,
.exclude_kernel = 1,
};
int fd;
u32 version;
u64 extended_mask = 0, mask = PERF_REGS_MASK;
/*
* Get the PVR value to set the extended
* mask specific to platform.
*/
version = (((mfspr(SPRN_PVR)) >> 16) & 0xFFFF);
if (version == PVR_POWER9)
extended_mask = PERF_REG_PMU_MASK_300;
else if (version == PVR_POWER10)
extended_mask = PERF_REG_PMU_MASK_31;
else
return mask;
attr.sample_regs_intr = extended_mask;
attr.sample_period = 1;
event_attr_init(&attr);
/*
* check if the pmu supports perf extended regs, before
* returning the register mask to sample.
*/
fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
if (fd != -1) {
close(fd);
mask |= extended_mask;
}
return mask;
}
uint64_t arch__user_reg_mask(void)
{
return PERF_REGS_MASK;
}
| linux-master | tools/perf/arch/powerpc/util/perf_regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <stdio.h>
#include "util/evsel.h"
void arch_evsel__set_sample_weight(struct evsel *evsel)
{
evsel__set_sample_bit(evsel, WEIGHT_STRUCT);
}
| linux-master | tools/perf/arch/powerpc/util/evsel.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include "tests/tests.h"
#include "arch-tests.h"
struct test_suite *arch_tests[] = {
#ifdef HAVE_DWARF_UNWIND_SUPPORT
&suite__dwarf_unwind,
#endif
NULL,
};
| linux-master | tools/perf/arch/powerpc/tests/arch-tests.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include "perf_regs.h"
#include "thread.h"
#include "map.h"
#include "maps.h"
#include "event.h"
#include "debug.h"
#include "tests/tests.h"
#define STACK_SIZE 8192
static int sample_ustack(struct perf_sample *sample,
struct thread *thread, u64 *regs)
{
struct stack_dump *stack = &sample->user_stack;
struct map *map;
unsigned long sp;
u64 stack_size, *buf;
buf = malloc(STACK_SIZE);
if (!buf) {
pr_debug("failed to allocate sample uregs data\n");
return -1;
}
sp = (unsigned long) regs[PERF_REG_POWERPC_R1];
map = maps__find(thread__maps(thread), (u64)sp);
if (!map) {
pr_debug("failed to get stack map\n");
free(buf);
return -1;
}
stack_size = map__end(map) - sp;
stack_size = stack_size > STACK_SIZE ? STACK_SIZE : stack_size;
memcpy(buf, (void *) sp, stack_size);
stack->data = (char *) buf;
stack->size = stack_size;
return 0;
}
int test__arch_unwind_sample(struct perf_sample *sample,
struct thread *thread)
{
struct regs_dump *regs = &sample->user_regs;
u64 *buf;
buf = calloc(1, sizeof(u64) * PERF_REGS_MAX);
if (!buf) {
pr_debug("failed to allocate sample uregs data\n");
return -1;
}
perf_regs_load(buf);
regs->abi = PERF_SAMPLE_REGS_ABI;
regs->regs = buf;
regs->mask = PERF_REGS_MASK;
return sample_ustack(sample, thread, buf);
}
| linux-master | tools/perf/arch/powerpc/tests/dwarf-unwind.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
static struct ins_ops *powerpc__associate_instruction_ops(struct arch *arch, const char *name)
{
int i;
struct ins_ops *ops;
/*
* - Interested only if instruction starts with 'b'.
* - Few start with 'b', but aren't branch instructions.
*/
if (name[0] != 'b' ||
!strncmp(name, "bcd", 3) ||
!strncmp(name, "brinc", 5) ||
!strncmp(name, "bper", 4))
return NULL;
ops = &jump_ops;
i = strlen(name) - 1;
if (i < 0)
return NULL;
/* ignore optional hints at the end of the instructions */
if (name[i] == '+' || name[i] == '-')
i--;
if (name[i] == 'l' || (name[i] == 'a' && name[i-1] == 'l')) {
/*
* if the instruction ends up with 'l' or 'la', then
* those are considered 'calls' since they update LR.
* ... except for 'bnl' which is branch if not less than
* and the absolute form of the same.
*/
if (strcmp(name, "bnl") && strcmp(name, "bnl+") &&
strcmp(name, "bnl-") && strcmp(name, "bnla") &&
strcmp(name, "bnla+") && strcmp(name, "bnla-"))
ops = &call_ops;
}
if (name[i] == 'r' && name[i-1] == 'l')
/*
* instructions ending with 'lr' are considered to be
* return instructions
*/
ops = &ret_ops;
arch__associate_ins_ops(arch, name, ops);
return ops;
}
static int powerpc__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
{
if (!arch->initialized) {
arch->initialized = true;
arch->associate_instruction_ops = powerpc__associate_instruction_ops;
arch->objdump.comment_char = '#';
}
return 0;
}
| linux-master | tools/perf/arch/powerpc/annotate/instructions.c |
#include <stdbool.h>
#include <stdlib.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/log2.h>
#include <linux/zalloc.h>
#include "../../util/evlist.h"
#include "../../util/auxtrace.h"
#include "../../util/evsel.h"
#include "../../util/record.h"
#define PERF_EVENT_CPUM_SF 0xB0000 /* Event: Basic-sampling */
#define PERF_EVENT_CPUM_SF_DIAG 0xBD000 /* Event: Combined-sampling */
#define DEFAULT_AUX_PAGES 128
#define DEFAULT_FREQ 4000
static void cpumsf_free(struct auxtrace_record *itr)
{
free(itr);
}
static size_t cpumsf_info_priv_size(struct auxtrace_record *itr __maybe_unused,
struct evlist *evlist __maybe_unused)
{
return 0;
}
static int
cpumsf_info_fill(struct auxtrace_record *itr __maybe_unused,
struct perf_session *session __maybe_unused,
struct perf_record_auxtrace_info *auxtrace_info __maybe_unused,
size_t priv_size __maybe_unused)
{
auxtrace_info->type = PERF_AUXTRACE_S390_CPUMSF;
return 0;
}
static unsigned long
cpumsf_reference(struct auxtrace_record *itr __maybe_unused)
{
return 0;
}
static int
cpumsf_recording_options(struct auxtrace_record *ar __maybe_unused,
struct evlist *evlist __maybe_unused,
struct record_opts *opts)
{
unsigned int factor = 1;
unsigned int pages;
opts->full_auxtrace = true;
/*
* The AUX buffer size should be set properly to avoid
* overflow of samples if it is not set explicitly.
* DEFAULT_AUX_PAGES is an proper size when sampling frequency
* is DEFAULT_FREQ. It is expected to hold about 1/2 second
* of sampling data. The size used for AUX buffer will scale
* according to the specified frequency and DEFAULT_FREQ.
*/
if (!opts->auxtrace_mmap_pages) {
if (opts->user_freq != UINT_MAX)
factor = (opts->user_freq + DEFAULT_FREQ
- 1) / DEFAULT_FREQ;
pages = DEFAULT_AUX_PAGES * factor;
opts->auxtrace_mmap_pages = roundup_pow_of_two(pages);
}
return 0;
}
static int
cpumsf_parse_snapshot_options(struct auxtrace_record *itr __maybe_unused,
struct record_opts *opts __maybe_unused,
const char *str __maybe_unused)
{
return 0;
}
/*
* auxtrace_record__init is called when perf record
* check if the event really need auxtrace
*/
struct auxtrace_record *auxtrace_record__init(struct evlist *evlist,
int *err)
{
struct auxtrace_record *aux;
struct evsel *pos;
int diagnose = 0;
*err = 0;
if (evlist->core.nr_entries == 0)
return NULL;
evlist__for_each_entry(evlist, pos) {
if (pos->core.attr.config == PERF_EVENT_CPUM_SF_DIAG) {
diagnose = 1;
pos->needs_auxtrace_mmap = true;
break;
}
}
if (!diagnose)
return NULL;
/* sampling in diagnose mode. alloc aux buffer */
aux = zalloc(sizeof(*aux));
if (aux == NULL) {
*err = -ENOMEM;
return NULL;
}
aux->parse_snapshot_options = cpumsf_parse_snapshot_options;
aux->recording_options = cpumsf_recording_options;
aux->info_priv_size = cpumsf_info_priv_size;
aux->info_fill = cpumsf_info_fill;
aux->free = cpumsf_free;
aux->reference = cpumsf_reference;
return aux;
}
| linux-master | tools/perf/arch/s390/util/auxtrace.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright IBM Corp. 2023
* Author(s): Thomas Richter <[email protected]>
*/
#include <string.h>
#include "../../../util/pmu.h"
#define S390_PMUPAI_CRYPTO "pai_crypto"
#define S390_PMUPAI_EXT "pai_ext"
#define S390_PMUCPUM_CF "cpum_cf"
struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu)
{
if (!strcmp(pmu->name, S390_PMUPAI_CRYPTO) ||
!strcmp(pmu->name, S390_PMUPAI_EXT) ||
!strcmp(pmu->name, S390_PMUCPUM_CF))
pmu->selectable = true;
return NULL;
}
| linux-master | tools/perf/arch/s390/util/pmu.c |
#include <linux/kernel.h>
#include <elfutils/libdwfl.h>
#include "../../util/unwind-libdw.h"
#include "../../util/perf_regs.h"
#include "../../util/event.h"
#include "../../util/sample.h"
#include "dwarf-regs-table.h"
#include "perf_regs.h"
bool libdw__arch_set_initial_registers(Dwfl_Thread *thread, void *arg)
{
struct unwind_info *ui = arg;
struct regs_dump *user_regs = &ui->sample->user_regs;
Dwarf_Word dwarf_regs[ARRAY_SIZE(s390_dwarf_regs)];
#define REG(r) ({ \
Dwarf_Word val = 0; \
perf_reg_value(&val, user_regs, PERF_REG_S390_##r); \
val; \
})
/*
* For DWARF register mapping details,
* see also perf/arch/s390/include/dwarf-regs-table.h
*/
dwarf_regs[0] = REG(R0);
dwarf_regs[1] = REG(R1);
dwarf_regs[2] = REG(R2);
dwarf_regs[3] = REG(R3);
dwarf_regs[4] = REG(R4);
dwarf_regs[5] = REG(R5);
dwarf_regs[6] = REG(R6);
dwarf_regs[7] = REG(R7);
dwarf_regs[8] = REG(R8);
dwarf_regs[9] = REG(R9);
dwarf_regs[10] = REG(R10);
dwarf_regs[11] = REG(R11);
dwarf_regs[12] = REG(R12);
dwarf_regs[13] = REG(R13);
dwarf_regs[14] = REG(R14);
dwarf_regs[15] = REG(R15);
dwarf_regs[16] = REG(FP0);
dwarf_regs[17] = REG(FP2);
dwarf_regs[18] = REG(FP4);
dwarf_regs[19] = REG(FP6);
dwarf_regs[20] = REG(FP1);
dwarf_regs[21] = REG(FP3);
dwarf_regs[22] = REG(FP5);
dwarf_regs[23] = REG(FP7);
dwarf_regs[24] = REG(FP8);
dwarf_regs[25] = REG(FP10);
dwarf_regs[26] = REG(FP12);
dwarf_regs[27] = REG(FP14);
dwarf_regs[28] = REG(FP9);
dwarf_regs[29] = REG(FP11);
dwarf_regs[30] = REG(FP13);
dwarf_regs[31] = REG(FP15);
dwarf_regs[64] = REG(MASK);
dwarf_regs[65] = REG(PC);
dwfl_thread_state_register_pc(thread, dwarf_regs[65]);
return dwfl_thread_state_registers(thread, 0, 32, dwarf_regs);
}
| linux-master | tools/perf/arch/s390/util/unwind-libdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Arch specific functions for perf kvm stat.
*
* Copyright 2014 IBM Corp.
* Author(s): Alexander Yarygin <[email protected]>
*/
#include <errno.h>
#include <string.h>
#include "../../util/kvm-stat.h"
#include "../../util/evsel.h"
#include <asm/sie.h>
define_exit_reasons_table(sie_exit_reasons, sie_intercept_code);
define_exit_reasons_table(sie_icpt_insn_codes, icpt_insn_codes);
define_exit_reasons_table(sie_sigp_order_codes, sigp_order_codes);
define_exit_reasons_table(sie_diagnose_codes, diagnose_codes);
define_exit_reasons_table(sie_icpt_prog_codes, icpt_prog_codes);
const char *vcpu_id_str = "id";
const char *kvm_exit_reason = "icptcode";
const char *kvm_entry_trace = "kvm:kvm_s390_sie_enter";
const char *kvm_exit_trace = "kvm:kvm_s390_sie_exit";
static void event_icpt_insn_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
unsigned long insn;
insn = evsel__intval(evsel, sample, "instruction");
key->key = icpt_insn_decoder(insn);
key->exit_reasons = sie_icpt_insn_codes;
}
static void event_sigp_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
key->key = evsel__intval(evsel, sample, "order_code");
key->exit_reasons = sie_sigp_order_codes;
}
static void event_diag_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
key->key = evsel__intval(evsel, sample, "code");
key->exit_reasons = sie_diagnose_codes;
}
static void event_icpt_prog_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
key->key = evsel__intval(evsel, sample, "code");
key->exit_reasons = sie_icpt_prog_codes;
}
static struct child_event_ops child_events[] = {
{ .name = "kvm:kvm_s390_intercept_instruction",
.get_key = event_icpt_insn_get_key },
{ .name = "kvm:kvm_s390_handle_sigp",
.get_key = event_sigp_get_key },
{ .name = "kvm:kvm_s390_handle_diag",
.get_key = event_diag_get_key },
{ .name = "kvm:kvm_s390_intercept_prog",
.get_key = event_icpt_prog_get_key },
{ NULL, NULL },
};
static struct kvm_events_ops exit_events = {
.is_begin_event = exit_event_begin,
.is_end_event = exit_event_end,
.child_ops = child_events,
.decode_key = exit_event_decode_key,
.name = "VM-EXIT"
};
const char *kvm_events_tp[] = {
"kvm:kvm_s390_sie_enter",
"kvm:kvm_s390_sie_exit",
"kvm:kvm_s390_intercept_instruction",
"kvm:kvm_s390_handle_sigp",
"kvm:kvm_s390_handle_diag",
"kvm:kvm_s390_intercept_prog",
NULL,
};
struct kvm_reg_events_ops kvm_reg_events_ops[] = {
{ .name = "vmexit", .ops = &exit_events },
{ NULL, NULL },
};
const char * const kvm_skip_events[] = {
"Wait state",
NULL,
};
int cpu_isa_init(struct perf_kvm_stat *kvm, const char *cpuid)
{
if (strstr(cpuid, "IBM")) {
kvm->exit_reasons = sie_exit_reasons;
kvm->exit_reasons_isa = "SIE";
} else
return -ENOTSUP;
return 0;
}
| linux-master | tools/perf/arch/s390/util/kvm-stat.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mapping of DWARF debug register numbers into register names.
*
* Copyright IBM Corp. 2010, 2017
* Author(s): Hendrik Brueckner <[email protected]>
*
*/
#include <errno.h>
#include <stddef.h>
#include <stdlib.h>
#include <linux/kernel.h>
#include <asm/ptrace.h>
#include <string.h>
#include <dwarf-regs.h>
#include "dwarf-regs-table.h"
const char *get_arch_regstr(unsigned int n)
{
return (n >= ARRAY_SIZE(s390_dwarf_regs)) ? NULL : s390_dwarf_regs[n];
}
/*
* Convert the register name into an offset to struct pt_regs (kernel).
* This is required by the BPF prologue generator. The BPF
* program is called in the BPF overflow handler in the perf
* core.
*/
int regs_query_register_offset(const char *name)
{
unsigned long gpr;
if (!name || strncmp(name, "%r", 2))
return -EINVAL;
errno = 0;
gpr = strtoul(name + 2, NULL, 10);
if (errno || gpr >= 16)
return -EINVAL;
return offsetof(user_pt_regs, gprs) + 8 * gpr;
}
| linux-master | tools/perf/arch/s390/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <inttypes.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>
#include <internal/lib.h> // page_size
#include "machine.h"
#include "api/fs/fs.h"
#include "debug.h"
#include "symbol.h"
int arch__fix_module_text_start(u64 *start, u64 *size, const char *name)
{
u64 m_start = *start;
char path[PATH_MAX];
snprintf(path, PATH_MAX, "module/%.*s/sections/.text",
(int)strlen(name) - 2, name + 1);
if (sysfs__read_ull(path, (unsigned long long *)start) < 0) {
pr_debug2("Using module %s start:%#lx\n", path, m_start);
*start = m_start;
} else {
/* Successful read of the modules segment text start address.
* Calculate difference between module start address
* in memory and module text segment start address.
* For example module load address is 0x3ff8011b000
* (from /proc/modules) and module text segment start
* address is 0x3ff8011b870 (from file above).
*
* Adjust the module size and subtract the GOT table
* size located at the beginning of the module.
*/
*size -= (*start - m_start);
}
return 0;
}
| linux-master | tools/perf/arch/s390/util/machine.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Implementation of get_cpuid().
*
* Copyright IBM Corp. 2014, 2018
* Author(s): Alexander Yarygin <[email protected]>
* Thomas Richter <[email protected]>
*/
#include <sys/types.h>
#include <errno.h>
#include <unistd.h>
#include <stdio.h>
#include <string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/zalloc.h>
#include "../../util/header.h"
#define SYSINFO_MANU "Manufacturer:"
#define SYSINFO_TYPE "Type:"
#define SYSINFO_MODEL "Model:"
#define SRVLVL_CPUMF "CPU-MF:"
#define SRVLVL_VERSION "version="
#define SRVLVL_AUTHORIZATION "authorization="
#define SYSINFO "/proc/sysinfo"
#define SRVLVL "/proc/service_levels"
int get_cpuid(char *buffer, size_t sz)
{
char *cp, *line = NULL, *line2;
char type[8], model[33], version[8], manufacturer[32], authorization[8];
int tpsize = 0, mdsize = 0, vssize = 0, mfsize = 0, atsize = 0;
int read;
unsigned long line_sz;
size_t nbytes;
FILE *sysinfo;
/*
* Scan /proc/sysinfo line by line and read out values for
* Manufacturer:, Type: and Model:, for example:
* Manufacturer: IBM
* Type: 2964
* Model: 702 N96
* The first word is the Model Capacity and the second word is
* Model (can be omitted). Both words have a maximum size of 16
* bytes.
*/
memset(manufacturer, 0, sizeof(manufacturer));
memset(type, 0, sizeof(type));
memset(model, 0, sizeof(model));
memset(version, 0, sizeof(version));
memset(authorization, 0, sizeof(authorization));
sysinfo = fopen(SYSINFO, "r");
if (sysinfo == NULL)
return errno;
while ((read = getline(&line, &line_sz, sysinfo)) != -1) {
if (!strncmp(line, SYSINFO_MANU, strlen(SYSINFO_MANU))) {
line2 = line + strlen(SYSINFO_MANU);
while ((cp = strtok_r(line2, "\n ", &line2))) {
mfsize += scnprintf(manufacturer + mfsize,
sizeof(manufacturer) - mfsize, "%s", cp);
}
}
if (!strncmp(line, SYSINFO_TYPE, strlen(SYSINFO_TYPE))) {
line2 = line + strlen(SYSINFO_TYPE);
while ((cp = strtok_r(line2, "\n ", &line2))) {
tpsize += scnprintf(type + tpsize,
sizeof(type) - tpsize, "%s", cp);
}
}
if (!strncmp(line, SYSINFO_MODEL, strlen(SYSINFO_MODEL))) {
line2 = line + strlen(SYSINFO_MODEL);
while ((cp = strtok_r(line2, "\n ", &line2))) {
mdsize += scnprintf(model + mdsize, sizeof(model) - mdsize,
"%s%s", model[0] ? "," : "", cp);
}
break;
}
}
fclose(sysinfo);
/* Missing manufacturer, type or model information should not happen */
if (!manufacturer[0] || !type[0] || !model[0])
return EINVAL;
/*
* Scan /proc/service_levels and return the CPU-MF counter facility
* version number and authorization level.
* Optional, does not exist on z/VM guests.
*/
sysinfo = fopen(SRVLVL, "r");
if (sysinfo == NULL)
goto skip_sysinfo;
while ((read = getline(&line, &line_sz, sysinfo)) != -1) {
if (strncmp(line, SRVLVL_CPUMF, strlen(SRVLVL_CPUMF)))
continue;
line2 = line + strlen(SRVLVL_CPUMF);
while ((cp = strtok_r(line2, "\n ", &line2))) {
if (!strncmp(cp, SRVLVL_VERSION,
strlen(SRVLVL_VERSION))) {
char *sep = strchr(cp, '=');
vssize += scnprintf(version + vssize,
sizeof(version) - vssize, "%s", sep + 1);
}
if (!strncmp(cp, SRVLVL_AUTHORIZATION,
strlen(SRVLVL_AUTHORIZATION))) {
char *sep = strchr(cp, '=');
atsize += scnprintf(authorization + atsize,
sizeof(authorization) - atsize, "%s", sep + 1);
}
}
}
fclose(sysinfo);
skip_sysinfo:
free(line);
if (version[0] && authorization[0] )
nbytes = snprintf(buffer, sz, "%s,%s,%s,%s,%s",
manufacturer, type, model, version,
authorization);
else
nbytes = snprintf(buffer, sz, "%s,%s,%s", manufacturer, type,
model);
return (nbytes >= sz) ? ENOBUFS : 0;
}
char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
{
char *buf = malloc(128);
if (buf && get_cpuid(buf, 128))
zfree(&buf);
return buf;
}
| linux-master | tools/perf/arch/s390/util/header.c |
// SPDX-License-Identifier: GPL-2.0
#include "perf_regs.h"
#include "../../util/perf_regs.h"
const struct sample_reg sample_reg_masks[] = {
SMPL_REG_END
};
uint64_t arch__intr_reg_mask(void)
{
return PERF_REGS_MASK;
}
uint64_t arch__user_reg_mask(void)
{
return PERF_REGS_MASK;
}
| linux-master | tools/perf/arch/s390/util/perf_regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
static int s390_call__parse(struct arch *arch, struct ins_operands *ops,
struct map_symbol *ms)
{
char *endptr, *tok, *name;
struct map *map = ms->map;
struct addr_map_symbol target = {
.ms = { .map = map, },
};
tok = strchr(ops->raw, ',');
if (!tok)
return -1;
ops->target.addr = strtoull(tok + 1, &endptr, 16);
name = strchr(endptr, '<');
if (name == NULL)
return -1;
name++;
if (arch->objdump.skip_functions_char &&
strchr(name, arch->objdump.skip_functions_char))
return -1;
tok = strchr(name, '>');
if (tok == NULL)
return -1;
*tok = '\0';
ops->target.name = strdup(name);
*tok = '>';
if (ops->target.name == NULL)
return -1;
target.addr = map__objdump_2mem(map, ops->target.addr);
if (maps__find_ams(ms->maps, &target) == 0 &&
map__rip_2objdump(target.ms.map, map__map_ip(target.ms.map, target.addr)) == ops->target.addr)
ops->target.sym = target.ms.sym;
return 0;
}
static struct ins_ops s390_call_ops = {
.parse = s390_call__parse,
.scnprintf = call__scnprintf,
};
static int s390_mov__parse(struct arch *arch __maybe_unused,
struct ins_operands *ops,
struct map_symbol *ms __maybe_unused)
{
char *s = strchr(ops->raw, ','), *target, *endptr;
if (s == NULL)
return -1;
*s = '\0';
ops->source.raw = strdup(ops->raw);
*s = ',';
if (ops->source.raw == NULL)
return -1;
target = ++s;
ops->target.raw = strdup(target);
if (ops->target.raw == NULL)
goto out_free_source;
ops->target.addr = strtoull(target, &endptr, 16);
if (endptr == target)
goto out_free_target;
s = strchr(endptr, '<');
if (s == NULL)
goto out_free_target;
endptr = strchr(s + 1, '>');
if (endptr == NULL)
goto out_free_target;
*endptr = '\0';
ops->target.name = strdup(s + 1);
*endptr = '>';
if (ops->target.name == NULL)
goto out_free_target;
return 0;
out_free_target:
zfree(&ops->target.raw);
out_free_source:
zfree(&ops->source.raw);
return -1;
}
static struct ins_ops s390_mov_ops = {
.parse = s390_mov__parse,
.scnprintf = mov__scnprintf,
};
static struct ins_ops *s390__associate_ins_ops(struct arch *arch, const char *name)
{
struct ins_ops *ops = NULL;
/* catch all kind of jumps */
if (strchr(name, 'j') ||
!strncmp(name, "bct", 3) ||
!strncmp(name, "br", 2))
ops = &jump_ops;
/* override call/returns */
if (!strcmp(name, "bras") ||
!strcmp(name, "brasl") ||
!strcmp(name, "basr"))
ops = &s390_call_ops;
if (!strcmp(name, "br"))
ops = &ret_ops;
/* override load/store relative to PC */
if (!strcmp(name, "lrl") ||
!strcmp(name, "lgrl") ||
!strcmp(name, "lgfrl") ||
!strcmp(name, "llgfrl") ||
!strcmp(name, "strl") ||
!strcmp(name, "stgrl"))
ops = &s390_mov_ops;
if (ops)
arch__associate_ins_ops(arch, name, ops);
return ops;
}
static int s390__cpuid_parse(struct arch *arch, char *cpuid)
{
unsigned int family;
char model[16], model_c[16], cpumf_v[16], cpumf_a[16];
int ret;
/*
* cpuid string format:
* "IBM,family,model-capacity,model[,cpum_cf-version,cpum_cf-authorization]"
*/
ret = sscanf(cpuid, "%*[^,],%u,%[^,],%[^,],%[^,],%s", &family, model_c,
model, cpumf_v, cpumf_a);
if (ret >= 2) {
arch->family = family;
arch->model = 0;
return 0;
}
return -1;
}
static int s390__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
{
int err = 0;
if (!arch->initialized) {
arch->initialized = true;
arch->associate_instruction_ops = s390__associate_ins_ops;
if (cpuid) {
if (s390__cpuid_parse(arch, cpuid))
err = SYMBOL_ANNOTATE_ERRNO__ARCH_INIT_CPUID_PARSING;
}
}
return err;
}
| linux-master | tools/perf/arch/s390/annotate/instructions.c |
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2020-2023 Loongson Technology Corporation Limited */
#include <elfutils/libdwfl.h>
#include "perf_regs.h"
#include "../../util/unwind-libdw.h"
#include "../../util/perf_regs.h"
#include "../../util/sample.h"
bool libdw__arch_set_initial_registers(Dwfl_Thread *thread, void *arg)
{
struct unwind_info *ui = arg;
struct regs_dump *user_regs = &ui->sample->user_regs;
Dwarf_Word dwarf_regs[PERF_REG_LOONGARCH_MAX];
#define REG(r) ({ \
Dwarf_Word val = 0; \
perf_reg_value(&val, user_regs, PERF_REG_LOONGARCH_##r); \
val; \
})
dwarf_regs[0] = 0;
dwarf_regs[1] = REG(R1);
dwarf_regs[2] = REG(R2);
dwarf_regs[3] = REG(R3);
dwarf_regs[4] = REG(R4);
dwarf_regs[5] = REG(R5);
dwarf_regs[6] = REG(R6);
dwarf_regs[7] = REG(R7);
dwarf_regs[8] = REG(R8);
dwarf_regs[9] = REG(R9);
dwarf_regs[10] = REG(R10);
dwarf_regs[11] = REG(R11);
dwarf_regs[12] = REG(R12);
dwarf_regs[13] = REG(R13);
dwarf_regs[14] = REG(R14);
dwarf_regs[15] = REG(R15);
dwarf_regs[16] = REG(R16);
dwarf_regs[17] = REG(R17);
dwarf_regs[18] = REG(R18);
dwarf_regs[19] = REG(R19);
dwarf_regs[20] = REG(R20);
dwarf_regs[21] = REG(R21);
dwarf_regs[22] = REG(R22);
dwarf_regs[23] = REG(R23);
dwarf_regs[24] = REG(R24);
dwarf_regs[25] = REG(R25);
dwarf_regs[26] = REG(R26);
dwarf_regs[27] = REG(R27);
dwarf_regs[28] = REG(R28);
dwarf_regs[29] = REG(R29);
dwarf_regs[30] = REG(R30);
dwarf_regs[31] = REG(R31);
dwfl_thread_state_register_pc(thread, REG(PC));
return dwfl_thread_state_registers(thread, 0, PERF_REG_LOONGARCH_MAX, dwarf_regs);
}
| linux-master | tools/perf/arch/loongarch/util/unwind-libdw.c |
// SPDX-License-Identifier: GPL-2.0
/*
* dwarf-regs.c : Mapping of DWARF debug register numbers into register names.
*
* Copyright (C) 2020-2023 Loongson Technology Corporation Limited
*/
#include <stdio.h>
#include <errno.h> /* for EINVAL */
#include <string.h> /* for strcmp */
#include <dwarf-regs.h>
struct pt_regs_dwarfnum {
const char *name;
unsigned int dwarfnum;
};
static struct pt_regs_dwarfnum loongarch_gpr_table[] = {
{"%r0", 0}, {"%r1", 1}, {"%r2", 2}, {"%r3", 3},
{"%r4", 4}, {"%r5", 5}, {"%r6", 6}, {"%r7", 7},
{"%r8", 8}, {"%r9", 9}, {"%r10", 10}, {"%r11", 11},
{"%r12", 12}, {"%r13", 13}, {"%r14", 14}, {"%r15", 15},
{"%r16", 16}, {"%r17", 17}, {"%r18", 18}, {"%r19", 19},
{"%r20", 20}, {"%r21", 21}, {"%r22", 22}, {"%r23", 23},
{"%r24", 24}, {"%r25", 25}, {"%r26", 26}, {"%r27", 27},
{"%r28", 28}, {"%r29", 29}, {"%r30", 30}, {"%r31", 31},
{NULL, 0}
};
const char *get_arch_regstr(unsigned int n)
{
n %= 32;
return loongarch_gpr_table[n].name;
}
int regs_query_register_offset(const char *name)
{
const struct pt_regs_dwarfnum *roff;
for (roff = loongarch_gpr_table; roff->name != NULL; roff++)
if (!strcmp(roff->name, name))
return roff->dwarfnum;
return -EINVAL;
}
| linux-master | tools/perf/arch/loongarch/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include <libunwind.h>
#include "perf_regs.h"
#include "../../util/unwind.h"
#include "util/debug.h"
int libunwind__arch_reg_id(int regnum)
{
switch (regnum) {
case UNW_LOONGARCH64_R1:
return PERF_REG_LOONGARCH_R1;
case UNW_LOONGARCH64_R2:
return PERF_REG_LOONGARCH_R2;
case UNW_LOONGARCH64_R3:
return PERF_REG_LOONGARCH_R3;
case UNW_LOONGARCH64_R4:
return PERF_REG_LOONGARCH_R4;
case UNW_LOONGARCH64_R5:
return PERF_REG_LOONGARCH_R5;
case UNW_LOONGARCH64_R6:
return PERF_REG_LOONGARCH_R6;
case UNW_LOONGARCH64_R7:
return PERF_REG_LOONGARCH_R7;
case UNW_LOONGARCH64_R8:
return PERF_REG_LOONGARCH_R8;
case UNW_LOONGARCH64_R9:
return PERF_REG_LOONGARCH_R9;
case UNW_LOONGARCH64_R10:
return PERF_REG_LOONGARCH_R10;
case UNW_LOONGARCH64_R11:
return PERF_REG_LOONGARCH_R11;
case UNW_LOONGARCH64_R12:
return PERF_REG_LOONGARCH_R12;
case UNW_LOONGARCH64_R13:
return PERF_REG_LOONGARCH_R13;
case UNW_LOONGARCH64_R14:
return PERF_REG_LOONGARCH_R14;
case UNW_LOONGARCH64_R15:
return PERF_REG_LOONGARCH_R15;
case UNW_LOONGARCH64_R16:
return PERF_REG_LOONGARCH_R16;
case UNW_LOONGARCH64_R17:
return PERF_REG_LOONGARCH_R17;
case UNW_LOONGARCH64_R18:
return PERF_REG_LOONGARCH_R18;
case UNW_LOONGARCH64_R19:
return PERF_REG_LOONGARCH_R19;
case UNW_LOONGARCH64_R20:
return PERF_REG_LOONGARCH_R20;
case UNW_LOONGARCH64_R21:
return PERF_REG_LOONGARCH_R21;
case UNW_LOONGARCH64_R22:
return PERF_REG_LOONGARCH_R22;
case UNW_LOONGARCH64_R23:
return PERF_REG_LOONGARCH_R23;
case UNW_LOONGARCH64_R24:
return PERF_REG_LOONGARCH_R24;
case UNW_LOONGARCH64_R25:
return PERF_REG_LOONGARCH_R25;
case UNW_LOONGARCH64_R26:
return PERF_REG_LOONGARCH_R26;
case UNW_LOONGARCH64_R27:
return PERF_REG_LOONGARCH_R27;
case UNW_LOONGARCH64_R28:
return PERF_REG_LOONGARCH_R28;
case UNW_LOONGARCH64_R29:
return PERF_REG_LOONGARCH_R29;
case UNW_LOONGARCH64_R30:
return PERF_REG_LOONGARCH_R30;
case UNW_LOONGARCH64_R31:
return PERF_REG_LOONGARCH_R31;
case UNW_LOONGARCH64_PC:
return PERF_REG_LOONGARCH_PC;
default:
pr_err("unwind: invalid reg id %d\n", regnum);
return -EINVAL;
}
return -EINVAL;
}
| linux-master | tools/perf/arch/loongarch/util/unwind-libunwind.c |
// SPDX-License-Identifier: GPL-2.0
#include "perf_regs.h"
#include "../../../util/perf_regs.h"
const struct sample_reg sample_reg_masks[] = {
SMPL_REG_END
};
uint64_t arch__intr_reg_mask(void)
{
return PERF_REGS_MASK;
}
uint64_t arch__user_reg_mask(void)
{
return PERF_REGS_MASK;
}
| linux-master | tools/perf/arch/loongarch/util/perf_regs.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Perf annotate functions.
*
* Copyright (C) 2020-2023 Loongson Technology Corporation Limited
*/
static int loongarch_call__parse(struct arch *arch, struct ins_operands *ops, struct map_symbol *ms)
{
char *c, *endptr, *tok, *name;
struct map *map = ms->map;
struct addr_map_symbol target = {
.ms = { .map = map, },
};
c = strchr(ops->raw, '#');
if (c++ == NULL)
return -1;
ops->target.addr = strtoull(c, &endptr, 16);
name = strchr(endptr, '<');
name++;
if (arch->objdump.skip_functions_char &&
strchr(name, arch->objdump.skip_functions_char))
return -1;
tok = strchr(name, '>');
if (tok == NULL)
return -1;
*tok = '\0';
ops->target.name = strdup(name);
*tok = '>';
if (ops->target.name == NULL)
return -1;
target.addr = map__objdump_2mem(map, ops->target.addr);
if (maps__find_ams(ms->maps, &target) == 0 &&
map__rip_2objdump(target.ms.map, map__map_ip(target.ms.map, target.addr)) == ops->target.addr)
ops->target.sym = target.ms.sym;
return 0;
}
static struct ins_ops loongarch_call_ops = {
.parse = loongarch_call__parse,
.scnprintf = call__scnprintf,
};
static int loongarch_jump__parse(struct arch *arch, struct ins_operands *ops, struct map_symbol *ms)
{
struct map *map = ms->map;
struct symbol *sym = ms->sym;
struct addr_map_symbol target = {
.ms = { .map = map, },
};
const char *c = strchr(ops->raw, '#');
u64 start, end;
ops->raw_comment = strchr(ops->raw, arch->objdump.comment_char);
ops->raw_func_start = strchr(ops->raw, '<');
if (ops->raw_func_start && c > ops->raw_func_start)
c = NULL;
if (c++ != NULL)
ops->target.addr = strtoull(c, NULL, 16);
else
ops->target.addr = strtoull(ops->raw, NULL, 16);
target.addr = map__objdump_2mem(map, ops->target.addr);
start = map__unmap_ip(map, sym->start);
end = map__unmap_ip(map, sym->end);
ops->target.outside = target.addr < start || target.addr > end;
if (maps__find_ams(ms->maps, &target) == 0 &&
map__rip_2objdump(target.ms.map, map__map_ip(target.ms.map, target.addr)) == ops->target.addr)
ops->target.sym = target.ms.sym;
if (!ops->target.outside) {
ops->target.offset = target.addr - start;
ops->target.offset_avail = true;
} else {
ops->target.offset_avail = false;
}
return 0;
}
static struct ins_ops loongarch_jump_ops = {
.parse = loongarch_jump__parse,
.scnprintf = jump__scnprintf,
};
static
struct ins_ops *loongarch__associate_ins_ops(struct arch *arch, const char *name)
{
struct ins_ops *ops = NULL;
if (!strcmp(name, "bl"))
ops = &loongarch_call_ops;
else if (!strcmp(name, "jirl"))
ops = &ret_ops;
else if (!strcmp(name, "b") ||
!strncmp(name, "beq", 3) ||
!strncmp(name, "bne", 3) ||
!strncmp(name, "blt", 3) ||
!strncmp(name, "bge", 3) ||
!strncmp(name, "bltu", 4) ||
!strncmp(name, "bgeu", 4))
ops = &loongarch_jump_ops;
else
return NULL;
arch__associate_ins_ops(arch, name, ops);
return ops;
}
static
int loongarch__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
{
if (!arch->initialized) {
arch->associate_instruction_ops = loongarch__associate_ins_ops;
arch->initialized = true;
arch->objdump.comment_char = '#';
}
return 0;
}
| linux-master | tools/perf/arch/loongarch/annotate/instructions.c |
// SPDX-License-Identifier: GPL-2.0
/*
* dwarf-regs.c : Mapping of DWARF debug register numbers into register names.
*
* Copyright (C) 2013 Cavium, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <stdio.h>
#include <dwarf-regs.h>
static const char *mips_gpr_names[32] = {
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9",
"$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19",
"$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29",
"$30", "$31"
};
const char *get_arch_regstr(unsigned int n)
{
if (n < 32)
return mips_gpr_names[n];
if (n == 64)
return "hi";
if (n == 65)
return "lo";
return NULL;
}
| linux-master | tools/perf/arch/mips/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include <libunwind.h>
#include "perf_regs.h"
#include "../../util/unwind.h"
#include "util/debug.h"
int libunwind__arch_reg_id(int regnum)
{
switch (regnum) {
case UNW_MIPS_R1 ... UNW_MIPS_R25:
return regnum - UNW_MIPS_R1 + PERF_REG_MIPS_R1;
case UNW_MIPS_R28 ... UNW_MIPS_R31:
return regnum - UNW_MIPS_R28 + PERF_REG_MIPS_R28;
case UNW_MIPS_PC:
return PERF_REG_MIPS_PC;
default:
pr_err("unwind: invalid reg id %d\n", regnum);
return -EINVAL;
}
}
| linux-master | tools/perf/arch/mips/util/unwind-libunwind.c |
// SPDX-License-Identifier: GPL-2.0
#include "perf_regs.h"
#include "../../util/perf_regs.h"
const struct sample_reg sample_reg_masks[] = {
SMPL_REG_END
};
uint64_t arch__intr_reg_mask(void)
{
return PERF_REGS_MASK;
}
uint64_t arch__user_reg_mask(void)
{
return PERF_REGS_MASK;
}
| linux-master | tools/perf/arch/mips/util/perf_regs.c |
// SPDX-License-Identifier: GPL-2.0
static
struct ins_ops *mips__associate_ins_ops(struct arch *arch, const char *name)
{
struct ins_ops *ops = NULL;
if (!strncmp(name, "bal", 3) ||
!strncmp(name, "bgezal", 6) ||
!strncmp(name, "bltzal", 6) ||
!strncmp(name, "bgtzal", 6) ||
!strncmp(name, "blezal", 6) ||
!strncmp(name, "beqzal", 6) ||
!strncmp(name, "bnezal", 6) ||
!strncmp(name, "bgtzl", 5) ||
!strncmp(name, "bltzl", 5) ||
!strncmp(name, "bgezl", 5) ||
!strncmp(name, "blezl", 5) ||
!strncmp(name, "jialc", 5) ||
!strncmp(name, "beql", 4) ||
!strncmp(name, "bnel", 4) ||
!strncmp(name, "jal", 3))
ops = &call_ops;
else if (!strncmp(name, "jr", 2))
ops = &ret_ops;
else if (name[0] == 'j' || name[0] == 'b')
ops = &jump_ops;
else
return NULL;
arch__associate_ins_ops(arch, name, ops);
return ops;
}
static
int mips__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
{
if (!arch->initialized) {
arch->associate_instruction_ops = mips__associate_ins_ops;
arch->initialized = true;
arch->objdump.comment_char = '#';
}
return 0;
}
| linux-master | tools/perf/arch/mips/annotate/instructions.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Mapping of DWARF debug register numbers into register names.
*
* Copyright (C) 2010 Matt Fleming <[email protected]>
*/
#include <stddef.h>
#include <dwarf-regs.h>
/*
* Generic dwarf analysis helpers
*/
#define SH_MAX_REGS 18
const char *sh_regs_table[SH_MAX_REGS] = {
"r0",
"r1",
"r2",
"r3",
"r4",
"r5",
"r6",
"r7",
"r8",
"r9",
"r10",
"r11",
"r12",
"r13",
"r14",
"r15",
"pc",
"pr",
};
/* Return architecture dependent register string (for kprobe-tracer) */
const char *get_arch_regstr(unsigned int n)
{
return (n < SH_MAX_REGS) ? sh_regs_table[n] : NULL;
}
| linux-master | tools/perf/arch/sh/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* auxtrace.c: AUX area tracing support
* Copyright (c) 2013-2014, Intel Corporation.
*/
#include <errno.h>
#include <stdbool.h>
#include "../../../util/header.h"
#include "../../../util/debug.h"
#include "../../../util/pmu.h"
#include "../../../util/pmus.h"
#include "../../../util/auxtrace.h"
#include "../../../util/intel-pt.h"
#include "../../../util/intel-bts.h"
#include "../../../util/evlist.h"
static
struct auxtrace_record *auxtrace_record__init_intel(struct evlist *evlist,
int *err)
{
struct perf_pmu *intel_pt_pmu;
struct perf_pmu *intel_bts_pmu;
struct evsel *evsel;
bool found_pt = false;
bool found_bts = false;
intel_pt_pmu = perf_pmus__find(INTEL_PT_PMU_NAME);
intel_bts_pmu = perf_pmus__find(INTEL_BTS_PMU_NAME);
evlist__for_each_entry(evlist, evsel) {
if (intel_pt_pmu && evsel->core.attr.type == intel_pt_pmu->type)
found_pt = true;
if (intel_bts_pmu && evsel->core.attr.type == intel_bts_pmu->type)
found_bts = true;
}
if (found_pt && found_bts) {
pr_err("intel_pt and intel_bts may not be used together\n");
*err = -EINVAL;
return NULL;
}
if (found_pt)
return intel_pt_recording_init(err);
if (found_bts)
return intel_bts_recording_init(err);
return NULL;
}
struct auxtrace_record *auxtrace_record__init(struct evlist *evlist,
int *err)
{
char buffer[64];
int ret;
*err = 0;
ret = get_cpuid(buffer, sizeof(buffer));
if (ret) {
*err = ret;
return NULL;
}
if (!strncmp(buffer, "GenuineIntel,", 13))
return auxtrace_record__init_intel(evlist, err);
return NULL;
}
| linux-master | tools/perf/arch/x86/util/auxtrace.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include <stdio.h>
#include <sys/types.h>
#include <dirent.h>
#include <fcntl.h>
#include <linux/stddef.h>
#include <linux/perf_event.h>
#include <linux/zalloc.h>
#include <api/fs/fs.h>
#include <errno.h>
#include "../../../util/intel-pt.h"
#include "../../../util/intel-bts.h"
#include "../../../util/pmu.h"
#include "../../../util/fncache.h"
#include "../../../util/pmus.h"
#include "env.h"
struct pmu_alias {
char *name;
char *alias;
struct list_head list;
};
static LIST_HEAD(pmu_alias_name_list);
static bool cached_list;
struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused)
{
#ifdef HAVE_AUXTRACE_SUPPORT
if (!strcmp(pmu->name, INTEL_PT_PMU_NAME)) {
pmu->auxtrace = true;
return intel_pt_pmu_default_config(pmu);
}
if (!strcmp(pmu->name, INTEL_BTS_PMU_NAME)) {
pmu->auxtrace = true;
pmu->selectable = true;
}
#endif
return NULL;
}
static void pmu_alias__delete(struct pmu_alias *pmu_alias)
{
if (!pmu_alias)
return;
zfree(&pmu_alias->name);
zfree(&pmu_alias->alias);
free(pmu_alias);
}
static struct pmu_alias *pmu_alias__new(char *name, char *alias)
{
struct pmu_alias *pmu_alias = zalloc(sizeof(*pmu_alias));
if (pmu_alias) {
pmu_alias->name = strdup(name);
if (!pmu_alias->name)
goto out_delete;
pmu_alias->alias = strdup(alias);
if (!pmu_alias->alias)
goto out_delete;
}
return pmu_alias;
out_delete:
pmu_alias__delete(pmu_alias);
return NULL;
}
static int setup_pmu_alias_list(void)
{
int fd, dirfd;
DIR *dir;
struct dirent *dent;
struct pmu_alias *pmu_alias;
char buf[MAX_PMU_NAME_LEN];
FILE *file;
int ret = -ENOMEM;
dirfd = perf_pmu__event_source_devices_fd();
if (dirfd < 0)
return -1;
dir = fdopendir(dirfd);
if (!dir)
return -errno;
while ((dent = readdir(dir))) {
if (!strcmp(dent->d_name, ".") ||
!strcmp(dent->d_name, ".."))
continue;
fd = perf_pmu__pathname_fd(dirfd, dent->d_name, "alias", O_RDONLY);
if (fd < 0)
continue;
file = fdopen(fd, "r");
if (!file)
continue;
if (!fgets(buf, sizeof(buf), file)) {
fclose(file);
continue;
}
fclose(file);
/* Remove the last '\n' */
buf[strlen(buf) - 1] = 0;
pmu_alias = pmu_alias__new(dent->d_name, buf);
if (!pmu_alias)
goto close_dir;
list_add_tail(&pmu_alias->list, &pmu_alias_name_list);
}
ret = 0;
close_dir:
closedir(dir);
return ret;
}
static const char *__pmu_find_real_name(const char *name)
{
struct pmu_alias *pmu_alias;
list_for_each_entry(pmu_alias, &pmu_alias_name_list, list) {
if (!strcmp(name, pmu_alias->alias))
return pmu_alias->name;
}
return name;
}
const char *pmu_find_real_name(const char *name)
{
if (cached_list)
return __pmu_find_real_name(name);
setup_pmu_alias_list();
cached_list = true;
return __pmu_find_real_name(name);
}
static const char *__pmu_find_alias_name(const char *name)
{
struct pmu_alias *pmu_alias;
list_for_each_entry(pmu_alias, &pmu_alias_name_list, list) {
if (!strcmp(name, pmu_alias->name))
return pmu_alias->alias;
}
return NULL;
}
const char *pmu_find_alias_name(const char *name)
{
if (cached_list)
return __pmu_find_alias_name(name);
setup_pmu_alias_list();
cached_list = true;
return __pmu_find_alias_name(name);
}
int perf_pmus__num_mem_pmus(void)
{
/* AMD uses IBS OP pmu and not a core PMU for perf mem/c2c */
if (x86__is_amd_cpu())
return 1;
/* Intel uses core pmus for perf mem/c2c */
return perf_pmus__num_core_pmus();
}
| linux-master | tools/perf/arch/x86/util/pmu.c |
// SPDX-License-Identifier: GPL-2.0
#include "archinsn.h"
#include "event.h"
#include "machine.h"
#include "thread.h"
#include "symbol.h"
#include "../../../../arch/x86/include/asm/insn.h"
void arch_fetch_insn(struct perf_sample *sample,
struct thread *thread,
struct machine *machine)
{
struct insn insn;
int len, ret;
bool is64bit = false;
if (!sample->ip)
return;
len = thread__memcpy(thread, machine, sample->insn, sample->ip, sizeof(sample->insn), &is64bit);
if (len <= 0)
return;
ret = insn_decode(&insn, sample->insn, len,
is64bit ? INSN_MODE_64 : INSN_MODE_32);
if (ret >= 0 && insn.length <= len)
sample->insn_len = insn.length;
}
| linux-master | tools/perf/arch/x86/util/archinsn.c |
// SPDX-License-Identifier: GPL-2.0
/*
* perf iostat
*
* Copyright (C) 2020, Intel Corporation
*
* Authors: Alexander Antonov <[email protected]>
*/
#include <api/fs/fs.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/zalloc.h>
#include <limits.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <dirent.h>
#include <unistd.h>
#include <stdlib.h>
#include <regex.h>
#include "util/cpumap.h"
#include "util/debug.h"
#include "util/iostat.h"
#include "util/counts.h"
#include "path.h"
#ifndef MAX_PATH
#define MAX_PATH 1024
#endif
#define UNCORE_IIO_PMU_PATH "devices/uncore_iio_%d"
#define SYSFS_UNCORE_PMU_PATH "%s/"UNCORE_IIO_PMU_PATH
#define PLATFORM_MAPPING_PATH UNCORE_IIO_PMU_PATH"/die%d"
/*
* Each metric requiries one IIO event which increments at every 4B transfer
* in corresponding direction. The formulas to compute metrics are generic:
* #EventCount * 4B / (1024 * 1024)
*/
static const char * const iostat_metrics[] = {
"Inbound Read(MB)",
"Inbound Write(MB)",
"Outbound Read(MB)",
"Outbound Write(MB)",
};
static inline int iostat_metrics_count(void)
{
return sizeof(iostat_metrics) / sizeof(char *);
}
static const char *iostat_metric_by_idx(int idx)
{
return *(iostat_metrics + idx % iostat_metrics_count());
}
struct iio_root_port {
u32 domain;
u8 bus;
u8 die;
u8 pmu_idx;
int idx;
};
struct iio_root_ports_list {
struct iio_root_port **rps;
int nr_entries;
};
static struct iio_root_ports_list *root_ports;
static void iio_root_port_show(FILE *output,
const struct iio_root_port * const rp)
{
if (output && rp)
fprintf(output, "S%d-uncore_iio_%d<%04x:%02x>\n",
rp->die, rp->pmu_idx, rp->domain, rp->bus);
}
static struct iio_root_port *iio_root_port_new(u32 domain, u8 bus,
u8 die, u8 pmu_idx)
{
struct iio_root_port *p = calloc(1, sizeof(*p));
if (p) {
p->domain = domain;
p->bus = bus;
p->die = die;
p->pmu_idx = pmu_idx;
}
return p;
}
static void iio_root_ports_list_free(struct iio_root_ports_list *list)
{
int idx;
if (list) {
for (idx = 0; idx < list->nr_entries; idx++)
zfree(&list->rps[idx]);
zfree(&list->rps);
free(list);
}
}
static struct iio_root_port *iio_root_port_find_by_notation(
const struct iio_root_ports_list * const list, u32 domain, u8 bus)
{
int idx;
struct iio_root_port *rp;
if (list) {
for (idx = 0; idx < list->nr_entries; idx++) {
rp = list->rps[idx];
if (rp && rp->domain == domain && rp->bus == bus)
return rp;
}
}
return NULL;
}
static int iio_root_ports_list_insert(struct iio_root_ports_list *list,
struct iio_root_port * const rp)
{
struct iio_root_port **tmp_buf;
if (list && rp) {
rp->idx = list->nr_entries++;
tmp_buf = realloc(list->rps,
list->nr_entries * sizeof(*list->rps));
if (!tmp_buf) {
pr_err("Failed to realloc memory\n");
return -ENOMEM;
}
tmp_buf[rp->idx] = rp;
list->rps = tmp_buf;
}
return 0;
}
static int iio_mapping(u8 pmu_idx, struct iio_root_ports_list * const list)
{
char *buf;
char path[MAX_PATH];
u32 domain;
u8 bus;
struct iio_root_port *rp;
size_t size;
int ret;
for (int die = 0; die < cpu__max_node(); die++) {
scnprintf(path, MAX_PATH, PLATFORM_MAPPING_PATH, pmu_idx, die);
if (sysfs__read_str(path, &buf, &size) < 0) {
if (pmu_idx)
goto out;
pr_err("Mode iostat is not supported\n");
return -1;
}
ret = sscanf(buf, "%04x:%02hhx", &domain, &bus);
free(buf);
if (ret != 2) {
pr_err("Invalid mapping data: iio_%d; die%d\n",
pmu_idx, die);
return -1;
}
rp = iio_root_port_new(domain, bus, die, pmu_idx);
if (!rp || iio_root_ports_list_insert(list, rp)) {
free(rp);
return -ENOMEM;
}
}
out:
return 0;
}
static u8 iio_pmu_count(void)
{
u8 pmu_idx = 0;
char path[MAX_PATH];
const char *sysfs = sysfs__mountpoint();
if (sysfs) {
for (;; pmu_idx++) {
snprintf(path, sizeof(path), SYSFS_UNCORE_PMU_PATH,
sysfs, pmu_idx);
if (access(path, F_OK) != 0)
break;
}
}
return pmu_idx;
}
static int iio_root_ports_scan(struct iio_root_ports_list **list)
{
int ret = -ENOMEM;
struct iio_root_ports_list *tmp_list;
u8 pmu_count = iio_pmu_count();
if (!pmu_count) {
pr_err("Unsupported uncore pmu configuration\n");
return -1;
}
tmp_list = calloc(1, sizeof(*tmp_list));
if (!tmp_list)
goto err;
for (u8 pmu_idx = 0; pmu_idx < pmu_count; pmu_idx++) {
ret = iio_mapping(pmu_idx, tmp_list);
if (ret)
break;
}
err:
if (!ret)
*list = tmp_list;
else
iio_root_ports_list_free(tmp_list);
return ret;
}
static int iio_root_port_parse_str(u32 *domain, u8 *bus, char *str)
{
int ret;
regex_t regex;
/*
* Expected format domain:bus:
* Valid domain range [0:ffff]
* Valid bus range [0:ff]
* Example: 0000:af, 0:3d, 01:7
*/
regcomp(®ex, "^([a-f0-9A-F]{1,}):([a-f0-9A-F]{1,2})", REG_EXTENDED);
ret = regexec(®ex, str, 0, NULL, 0);
if (ret || sscanf(str, "%08x:%02hhx", domain, bus) != 2)
pr_warning("Unrecognized root port format: %s\n"
"Please use the following format:\n"
"\t [domain]:[bus]\n"
"\t for example: 0000:3d\n", str);
regfree(®ex);
return ret;
}
static int iio_root_ports_list_filter(struct iio_root_ports_list **list,
const char *filter)
{
char *tok, *tmp, *filter_copy = NULL;
struct iio_root_port *rp;
u32 domain;
u8 bus;
int ret = -ENOMEM;
struct iio_root_ports_list *tmp_list = calloc(1, sizeof(*tmp_list));
if (!tmp_list)
goto err;
filter_copy = strdup(filter);
if (!filter_copy)
goto err;
for (tok = strtok_r(filter_copy, ",", &tmp); tok;
tok = strtok_r(NULL, ",", &tmp)) {
if (!iio_root_port_parse_str(&domain, &bus, tok)) {
rp = iio_root_port_find_by_notation(*list, domain, bus);
if (rp) {
(*list)->rps[rp->idx] = NULL;
ret = iio_root_ports_list_insert(tmp_list, rp);
if (ret) {
free(rp);
goto err;
}
} else if (!iio_root_port_find_by_notation(tmp_list,
domain, bus))
pr_warning("Root port %04x:%02x were not found\n",
domain, bus);
}
}
if (tmp_list->nr_entries == 0) {
pr_err("Requested root ports were not found\n");
ret = -EINVAL;
}
err:
iio_root_ports_list_free(*list);
if (ret)
iio_root_ports_list_free(tmp_list);
else
*list = tmp_list;
free(filter_copy);
return ret;
}
static int iostat_event_group(struct evlist *evl,
struct iio_root_ports_list *list)
{
int ret;
int idx;
const char *iostat_cmd_template =
"{uncore_iio_%x/event=0x83,umask=0x04,ch_mask=0xF,fc_mask=0x07/,\
uncore_iio_%x/event=0x83,umask=0x01,ch_mask=0xF,fc_mask=0x07/,\
uncore_iio_%x/event=0xc0,umask=0x04,ch_mask=0xF,fc_mask=0x07/,\
uncore_iio_%x/event=0xc0,umask=0x01,ch_mask=0xF,fc_mask=0x07/}";
const int len_template = strlen(iostat_cmd_template) + 1;
struct evsel *evsel = NULL;
int metrics_count = iostat_metrics_count();
char *iostat_cmd = calloc(len_template, 1);
if (!iostat_cmd)
return -ENOMEM;
for (idx = 0; idx < list->nr_entries; idx++) {
sprintf(iostat_cmd, iostat_cmd_template,
list->rps[idx]->pmu_idx, list->rps[idx]->pmu_idx,
list->rps[idx]->pmu_idx, list->rps[idx]->pmu_idx);
ret = parse_event(evl, iostat_cmd);
if (ret)
goto err;
}
evlist__for_each_entry(evl, evsel) {
evsel->priv = list->rps[evsel->core.idx / metrics_count];
}
list->nr_entries = 0;
err:
iio_root_ports_list_free(list);
free(iostat_cmd);
return ret;
}
int iostat_prepare(struct evlist *evlist, struct perf_stat_config *config)
{
if (evlist->core.nr_entries > 0) {
pr_warning("The -e and -M options are not supported."
"All chosen events/metrics will be dropped\n");
evlist__delete(evlist);
evlist = evlist__new();
if (!evlist)
return -ENOMEM;
}
config->metric_only = true;
config->aggr_mode = AGGR_GLOBAL;
return iostat_event_group(evlist, root_ports);
}
int iostat_parse(const struct option *opt, const char *str,
int unset __maybe_unused)
{
int ret;
struct perf_stat_config *config = (struct perf_stat_config *)opt->data;
ret = iio_root_ports_scan(&root_ports);
if (!ret) {
config->iostat_run = true;
if (!str)
iostat_mode = IOSTAT_RUN;
else if (!strcmp(str, "list"))
iostat_mode = IOSTAT_LIST;
else {
iostat_mode = IOSTAT_RUN;
ret = iio_root_ports_list_filter(&root_ports, str);
}
}
return ret;
}
void iostat_list(struct evlist *evlist, struct perf_stat_config *config)
{
struct evsel *evsel;
struct iio_root_port *rp = NULL;
evlist__for_each_entry(evlist, evsel) {
if (rp != evsel->priv) {
rp = evsel->priv;
iio_root_port_show(config->output, rp);
}
}
}
void iostat_release(struct evlist *evlist)
{
struct evsel *evsel;
struct iio_root_port *rp = NULL;
evlist__for_each_entry(evlist, evsel) {
if (rp != evsel->priv) {
rp = evsel->priv;
zfree(&evsel->priv);
}
}
}
void iostat_prefix(struct evlist *evlist,
struct perf_stat_config *config,
char *prefix, struct timespec *ts)
{
struct iio_root_port *rp = evlist->selected->priv;
if (rp) {
if (ts)
sprintf(prefix, "%6lu.%09lu%s%04x:%02x%s",
ts->tv_sec, ts->tv_nsec,
config->csv_sep, rp->domain, rp->bus,
config->csv_sep);
else
sprintf(prefix, "%04x:%02x%s", rp->domain, rp->bus,
config->csv_sep);
}
}
void iostat_print_header_prefix(struct perf_stat_config *config)
{
if (config->csv_output)
fputs("port,", config->output);
else if (config->interval)
fprintf(config->output, "# time port ");
else
fprintf(config->output, " port ");
}
void iostat_print_metric(struct perf_stat_config *config, struct evsel *evsel,
struct perf_stat_output_ctx *out)
{
double iostat_value = 0;
u64 prev_count_val = 0;
const char *iostat_metric = iostat_metric_by_idx(evsel->core.idx);
u8 die = ((struct iio_root_port *)evsel->priv)->die;
struct perf_counts_values *count = perf_counts(evsel->counts, die, 0);
if (count && count->run && count->ena) {
if (evsel->prev_raw_counts && !out->force_header) {
struct perf_counts_values *prev_count =
perf_counts(evsel->prev_raw_counts, die, 0);
prev_count_val = prev_count->val;
prev_count->val = count->val;
}
iostat_value = (count->val - prev_count_val) /
((double) count->run / count->ena);
}
out->print_metric(config, out->ctx, NULL, "%8.0f", iostat_metric,
iostat_value / (256 * 1024));
}
void iostat_print_counters(struct evlist *evlist,
struct perf_stat_config *config, struct timespec *ts,
char *prefix, iostat_print_counter_t print_cnt_cb, void *arg)
{
void *perf_device = NULL;
struct evsel *counter = evlist__first(evlist);
evlist__set_selected(evlist, counter);
iostat_prefix(evlist, config, prefix, ts);
fprintf(config->output, "%s", prefix);
evlist__for_each_entry(evlist, counter) {
perf_device = evlist->selected->priv;
if (perf_device && perf_device != counter->priv) {
evlist__set_selected(evlist, counter);
iostat_prefix(evlist, config, prefix, ts);
fprintf(config->output, "\n%s", prefix);
}
print_cnt_cb(config, counter, arg);
}
fputc('\n', config->output);
}
| linux-master | tools/perf/arch/x86/util/iostat.c |
// SPDX-License-Identifier: GPL-2.0
#include "util/pmu.h"
#include "util/pmus.h"
#include "util/env.h"
#include "map_symbol.h"
#include "mem-events.h"
#include "linux/string.h"
#include "env.h"
static char mem_loads_name[100];
static bool mem_loads_name__init;
static char mem_stores_name[100];
#define MEM_LOADS_AUX 0x8203
#define MEM_LOADS_AUX_NAME "{%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P"
#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s }
static struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX] = {
E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads"),
E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores"),
E(NULL, NULL, NULL),
};
static struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = {
E(NULL, NULL, NULL),
E(NULL, NULL, NULL),
E("mem-ldst", "ibs_op//", "ibs_op"),
};
struct perf_mem_event *perf_mem_events__ptr(int i)
{
if (i >= PERF_MEM_EVENTS__MAX)
return NULL;
if (x86__is_amd_cpu())
return &perf_mem_events_amd[i];
return &perf_mem_events_intel[i];
}
bool is_mem_loads_aux_event(struct evsel *leader)
{
struct perf_pmu *pmu = perf_pmus__find("cpu");
if (!pmu)
pmu = perf_pmus__find("cpu_core");
if (pmu && !perf_pmu__have_event(pmu, "mem-loads-aux"))
return false;
return leader->core.attr.config == MEM_LOADS_AUX;
}
const char *perf_mem_events__name(int i, const char *pmu_name)
{
struct perf_mem_event *e = perf_mem_events__ptr(i);
if (!e)
return NULL;
if (i == PERF_MEM_EVENTS__LOAD) {
if (mem_loads_name__init && !pmu_name)
return mem_loads_name;
if (!pmu_name) {
mem_loads_name__init = true;
pmu_name = "cpu";
}
if (perf_pmus__have_event(pmu_name, "mem-loads-aux")) {
scnprintf(mem_loads_name, sizeof(mem_loads_name),
MEM_LOADS_AUX_NAME, pmu_name, pmu_name,
perf_mem_events__loads_ldlat);
} else {
scnprintf(mem_loads_name, sizeof(mem_loads_name),
e->name, pmu_name,
perf_mem_events__loads_ldlat);
}
return mem_loads_name;
}
if (i == PERF_MEM_EVENTS__STORE) {
if (!pmu_name)
pmu_name = "cpu";
scnprintf(mem_stores_name, sizeof(mem_stores_name),
e->name, pmu_name);
return mem_stores_name;
}
return e->name;
}
| linux-master | tools/perf/arch/x86/util/mem-events.c |
// SPDX-License-Identifier: GPL-2.0
#include <elfutils/libdwfl.h>
#include "perf_regs.h"
#include "../../../util/unwind-libdw.h"
#include "../../../util/perf_regs.h"
#include "util/sample.h"
bool libdw__arch_set_initial_registers(Dwfl_Thread *thread, void *arg)
{
struct unwind_info *ui = arg;
struct regs_dump *user_regs = &ui->sample->user_regs;
Dwarf_Word dwarf_regs[17];
unsigned nregs;
#define REG(r) ({ \
Dwarf_Word val = 0; \
perf_reg_value(&val, user_regs, PERF_REG_X86_##r); \
val; \
})
if (user_regs->abi == PERF_SAMPLE_REGS_ABI_32) {
dwarf_regs[0] = REG(AX);
dwarf_regs[1] = REG(CX);
dwarf_regs[2] = REG(DX);
dwarf_regs[3] = REG(BX);
dwarf_regs[4] = REG(SP);
dwarf_regs[5] = REG(BP);
dwarf_regs[6] = REG(SI);
dwarf_regs[7] = REG(DI);
dwarf_regs[8] = REG(IP);
nregs = 9;
} else {
dwarf_regs[0] = REG(AX);
dwarf_regs[1] = REG(DX);
dwarf_regs[2] = REG(CX);
dwarf_regs[3] = REG(BX);
dwarf_regs[4] = REG(SI);
dwarf_regs[5] = REG(DI);
dwarf_regs[6] = REG(BP);
dwarf_regs[7] = REG(SP);
dwarf_regs[8] = REG(R8);
dwarf_regs[9] = REG(R9);
dwarf_regs[10] = REG(R10);
dwarf_regs[11] = REG(R11);
dwarf_regs[12] = REG(R12);
dwarf_regs[13] = REG(R13);
dwarf_regs[14] = REG(R14);
dwarf_regs[15] = REG(R15);
dwarf_regs[16] = REG(IP);
nregs = 17;
}
return dwfl_thread_state_registers(thread, 0, nregs, dwarf_regs);
}
| linux-master | tools/perf/arch/x86/util/unwind-libdw.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* intel_pt.c: Intel Processor Trace support
* Copyright (c) 2013-2015, Intel Corporation.
*/
#include <errno.h>
#include <stdbool.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/log2.h>
#include <linux/zalloc.h>
#include <linux/err.h>
#include <cpuid.h>
#include "../../../util/session.h"
#include "../../../util/event.h"
#include "../../../util/evlist.h"
#include "../../../util/evsel.h"
#include "../../../util/evsel_config.h"
#include "../../../util/cpumap.h"
#include "../../../util/mmap.h"
#include <subcmd/parse-options.h>
#include "../../../util/parse-events.h"
#include "../../../util/pmus.h"
#include "../../../util/debug.h"
#include "../../../util/auxtrace.h"
#include "../../../util/perf_api_probe.h"
#include "../../../util/record.h"
#include "../../../util/target.h"
#include "../../../util/tsc.h"
#include <internal/lib.h> // page_size
#include "../../../util/intel-pt.h"
#define KiB(x) ((x) * 1024)
#define MiB(x) ((x) * 1024 * 1024)
#define KiB_MASK(x) (KiB(x) - 1)
#define MiB_MASK(x) (MiB(x) - 1)
#define INTEL_PT_PSB_PERIOD_NEAR 256
struct intel_pt_snapshot_ref {
void *ref_buf;
size_t ref_offset;
bool wrapped;
};
struct intel_pt_recording {
struct auxtrace_record itr;
struct perf_pmu *intel_pt_pmu;
int have_sched_switch;
struct evlist *evlist;
bool snapshot_mode;
bool snapshot_init_done;
size_t snapshot_size;
size_t snapshot_ref_buf_size;
int snapshot_ref_cnt;
struct intel_pt_snapshot_ref *snapshot_refs;
size_t priv_size;
};
static int intel_pt_parse_terms_with_default(struct perf_pmu *pmu,
const char *str,
u64 *config)
{
struct list_head *terms;
struct perf_event_attr attr = { .size = 0, };
int err;
terms = malloc(sizeof(struct list_head));
if (!terms)
return -ENOMEM;
INIT_LIST_HEAD(terms);
err = parse_events_terms(terms, str, /*input=*/ NULL);
if (err)
goto out_free;
attr.config = *config;
err = perf_pmu__config_terms(pmu, &attr, terms, /*zero=*/true, /*err=*/NULL);
if (err)
goto out_free;
*config = attr.config;
out_free:
parse_events_terms__delete(terms);
return err;
}
static int intel_pt_parse_terms(struct perf_pmu *pmu, const char *str, u64 *config)
{
*config = 0;
return intel_pt_parse_terms_with_default(pmu, str, config);
}
static u64 intel_pt_masked_bits(u64 mask, u64 bits)
{
const u64 top_bit = 1ULL << 63;
u64 res = 0;
int i;
for (i = 0; i < 64; i++) {
if (mask & top_bit) {
res <<= 1;
if (bits & top_bit)
res |= 1;
}
mask <<= 1;
bits <<= 1;
}
return res;
}
static int intel_pt_read_config(struct perf_pmu *intel_pt_pmu, const char *str,
struct evlist *evlist, u64 *res)
{
struct evsel *evsel;
u64 mask;
*res = 0;
mask = perf_pmu__format_bits(intel_pt_pmu, str);
if (!mask)
return -EINVAL;
evlist__for_each_entry(evlist, evsel) {
if (evsel->core.attr.type == intel_pt_pmu->type) {
*res = intel_pt_masked_bits(mask, evsel->core.attr.config);
return 0;
}
}
return -EINVAL;
}
static size_t intel_pt_psb_period(struct perf_pmu *intel_pt_pmu,
struct evlist *evlist)
{
u64 val;
int err, topa_multiple_entries;
size_t psb_period;
if (perf_pmu__scan_file(intel_pt_pmu, "caps/topa_multiple_entries",
"%d", &topa_multiple_entries) != 1)
topa_multiple_entries = 0;
/*
* Use caps/topa_multiple_entries to indicate early hardware that had
* extra frequent PSBs.
*/
if (!topa_multiple_entries) {
psb_period = 256;
goto out;
}
err = intel_pt_read_config(intel_pt_pmu, "psb_period", evlist, &val);
if (err)
val = 0;
psb_period = 1 << (val + 11);
out:
pr_debug2("%s psb_period %zu\n", intel_pt_pmu->name, psb_period);
return psb_period;
}
static int intel_pt_pick_bit(int bits, int target)
{
int pos, pick = -1;
for (pos = 0; bits; bits >>= 1, pos++) {
if (bits & 1) {
if (pos <= target || pick < 0)
pick = pos;
if (pos >= target)
break;
}
}
return pick;
}
static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu)
{
char buf[256];
int mtc, mtc_periods = 0, mtc_period;
int psb_cyc, psb_periods, psb_period;
int pos = 0;
u64 config;
char c;
int dirfd;
dirfd = perf_pmu__event_source_devices_fd();
pos += scnprintf(buf + pos, sizeof(buf) - pos, "tsc");
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/mtc", "%d",
&mtc) != 1)
mtc = 1;
if (mtc) {
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/mtc_periods", "%x",
&mtc_periods) != 1)
mtc_periods = 0;
if (mtc_periods) {
mtc_period = intel_pt_pick_bit(mtc_periods, 3);
pos += scnprintf(buf + pos, sizeof(buf) - pos,
",mtc,mtc_period=%d", mtc_period);
}
}
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/psb_cyc", "%d",
&psb_cyc) != 1)
psb_cyc = 1;
if (psb_cyc && mtc_periods) {
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/psb_periods", "%x",
&psb_periods) != 1)
psb_periods = 0;
if (psb_periods) {
psb_period = intel_pt_pick_bit(psb_periods, 3);
pos += scnprintf(buf + pos, sizeof(buf) - pos,
",psb_period=%d", psb_period);
}
}
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "format/pt", "%c", &c) == 1 &&
perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "format/branch", "%c", &c) == 1)
pos += scnprintf(buf + pos, sizeof(buf) - pos, ",pt,branch");
pr_debug2("%s default config: %s\n", intel_pt_pmu->name, buf);
intel_pt_parse_terms(intel_pt_pmu, buf, &config);
close(dirfd);
return config;
}
static int intel_pt_parse_snapshot_options(struct auxtrace_record *itr,
struct record_opts *opts,
const char *str)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
unsigned long long snapshot_size = 0;
char *endptr;
if (str) {
snapshot_size = strtoull(str, &endptr, 0);
if (*endptr || snapshot_size > SIZE_MAX)
return -1;
}
opts->auxtrace_snapshot_mode = true;
opts->auxtrace_snapshot_size = snapshot_size;
ptr->snapshot_size = snapshot_size;
return 0;
}
struct perf_event_attr *
intel_pt_pmu_default_config(struct perf_pmu *intel_pt_pmu)
{
struct perf_event_attr *attr;
attr = zalloc(sizeof(struct perf_event_attr));
if (!attr)
return NULL;
attr->config = intel_pt_default_config(intel_pt_pmu);
intel_pt_pmu->selectable = true;
return attr;
}
static const char *intel_pt_find_filter(struct evlist *evlist,
struct perf_pmu *intel_pt_pmu)
{
struct evsel *evsel;
evlist__for_each_entry(evlist, evsel) {
if (evsel->core.attr.type == intel_pt_pmu->type)
return evsel->filter;
}
return NULL;
}
static size_t intel_pt_filter_bytes(const char *filter)
{
size_t len = filter ? strlen(filter) : 0;
return len ? roundup(len + 1, 8) : 0;
}
static size_t
intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
const char *filter = intel_pt_find_filter(evlist, ptr->intel_pt_pmu);
ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_MAX * sizeof(u64)) +
intel_pt_filter_bytes(filter);
ptr->priv_size += sizeof(u64); /* Cap Event Trace */
return ptr->priv_size;
}
static void intel_pt_tsc_ctc_ratio(u32 *n, u32 *d)
{
unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0;
__get_cpuid(0x15, &eax, &ebx, &ecx, &edx);
*n = ebx;
*d = eax;
}
static int intel_pt_info_fill(struct auxtrace_record *itr,
struct perf_session *session,
struct perf_record_auxtrace_info *auxtrace_info,
size_t priv_size)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
struct perf_pmu *intel_pt_pmu = ptr->intel_pt_pmu;
struct perf_event_mmap_page *pc;
struct perf_tsc_conversion tc = { .time_mult = 0, };
bool cap_user_time_zero = false, per_cpu_mmaps;
u64 tsc_bit, mtc_bit, mtc_freq_bits, cyc_bit, noretcomp_bit;
u32 tsc_ctc_ratio_n, tsc_ctc_ratio_d;
unsigned long max_non_turbo_ratio;
size_t filter_str_len;
const char *filter;
int event_trace;
__u64 *info;
int err;
if (priv_size != ptr->priv_size)
return -EINVAL;
intel_pt_parse_terms(intel_pt_pmu, "tsc", &tsc_bit);
intel_pt_parse_terms(intel_pt_pmu, "noretcomp", &noretcomp_bit);
intel_pt_parse_terms(intel_pt_pmu, "mtc", &mtc_bit);
mtc_freq_bits = perf_pmu__format_bits(intel_pt_pmu, "mtc_period");
intel_pt_parse_terms(intel_pt_pmu, "cyc", &cyc_bit);
intel_pt_tsc_ctc_ratio(&tsc_ctc_ratio_n, &tsc_ctc_ratio_d);
if (perf_pmu__scan_file(intel_pt_pmu, "max_nonturbo_ratio",
"%lu", &max_non_turbo_ratio) != 1)
max_non_turbo_ratio = 0;
if (perf_pmu__scan_file(intel_pt_pmu, "caps/event_trace",
"%d", &event_trace) != 1)
event_trace = 0;
filter = intel_pt_find_filter(session->evlist, ptr->intel_pt_pmu);
filter_str_len = filter ? strlen(filter) : 0;
if (!session->evlist->core.nr_mmaps)
return -EINVAL;
pc = session->evlist->mmap[0].core.base;
if (pc) {
err = perf_read_tsc_conversion(pc, &tc);
if (err) {
if (err != -EOPNOTSUPP)
return err;
} else {
cap_user_time_zero = tc.time_mult != 0;
}
if (!cap_user_time_zero)
ui__warning("Intel Processor Trace: TSC not available\n");
}
per_cpu_mmaps = !perf_cpu_map__empty(session->evlist->core.user_requested_cpus);
auxtrace_info->type = PERF_AUXTRACE_INTEL_PT;
auxtrace_info->priv[INTEL_PT_PMU_TYPE] = intel_pt_pmu->type;
auxtrace_info->priv[INTEL_PT_TIME_SHIFT] = tc.time_shift;
auxtrace_info->priv[INTEL_PT_TIME_MULT] = tc.time_mult;
auxtrace_info->priv[INTEL_PT_TIME_ZERO] = tc.time_zero;
auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO] = cap_user_time_zero;
auxtrace_info->priv[INTEL_PT_TSC_BIT] = tsc_bit;
auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT] = noretcomp_bit;
auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH] = ptr->have_sched_switch;
auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE] = ptr->snapshot_mode;
auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS] = per_cpu_mmaps;
auxtrace_info->priv[INTEL_PT_MTC_BIT] = mtc_bit;
auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS] = mtc_freq_bits;
auxtrace_info->priv[INTEL_PT_TSC_CTC_N] = tsc_ctc_ratio_n;
auxtrace_info->priv[INTEL_PT_TSC_CTC_D] = tsc_ctc_ratio_d;
auxtrace_info->priv[INTEL_PT_CYC_BIT] = cyc_bit;
auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO] = max_non_turbo_ratio;
auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] = filter_str_len;
info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
if (filter_str_len) {
size_t len = intel_pt_filter_bytes(filter);
strncpy((char *)info, filter, len);
info += len >> 3;
}
*info++ = event_trace;
return 0;
}
#ifdef HAVE_LIBTRACEEVENT
static int intel_pt_track_switches(struct evlist *evlist)
{
const char *sched_switch = "sched:sched_switch";
struct evsel *evsel;
int err;
if (!evlist__can_select_event(evlist, sched_switch))
return -EPERM;
evsel = evlist__add_sched_switch(evlist, true);
if (IS_ERR(evsel)) {
err = PTR_ERR(evsel);
pr_debug2("%s: failed to create %s, error = %d\n",
__func__, sched_switch, err);
return err;
}
evsel->immediate = true;
return 0;
}
#endif
static void intel_pt_valid_str(char *str, size_t len, u64 valid)
{
unsigned int val, last = 0, state = 1;
int p = 0;
str[0] = '\0';
for (val = 0; val <= 64; val++, valid >>= 1) {
if (valid & 1) {
last = val;
switch (state) {
case 0:
p += scnprintf(str + p, len - p, ",");
/* Fall through */
case 1:
p += scnprintf(str + p, len - p, "%u", val);
state = 2;
break;
case 2:
state = 3;
break;
case 3:
state = 4;
break;
default:
break;
}
} else {
switch (state) {
case 3:
p += scnprintf(str + p, len - p, ",%u", last);
state = 0;
break;
case 4:
p += scnprintf(str + p, len - p, "-%u", last);
state = 0;
break;
default:
break;
}
if (state != 1)
state = 0;
}
}
}
static int intel_pt_val_config_term(struct perf_pmu *intel_pt_pmu, int dirfd,
const char *caps, const char *name,
const char *supported, u64 config)
{
char valid_str[256];
unsigned int shift;
unsigned long long valid;
u64 bits;
int ok;
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, caps, "%llx", &valid) != 1)
valid = 0;
if (supported &&
perf_pmu__scan_file_at(intel_pt_pmu, dirfd, supported, "%d", &ok) == 1 && !ok)
valid = 0;
valid |= 1;
bits = perf_pmu__format_bits(intel_pt_pmu, name);
config &= bits;
for (shift = 0; bits && !(bits & 1); shift++)
bits >>= 1;
config >>= shift;
if (config > 63)
goto out_err;
if (valid & (1 << config))
return 0;
out_err:
intel_pt_valid_str(valid_str, sizeof(valid_str), valid);
pr_err("Invalid %s for %s. Valid values are: %s\n",
name, INTEL_PT_PMU_NAME, valid_str);
return -EINVAL;
}
static int intel_pt_validate_config(struct perf_pmu *intel_pt_pmu,
struct evsel *evsel)
{
int err, dirfd;
char c;
if (!evsel)
return 0;
dirfd = perf_pmu__event_source_devices_fd();
if (dirfd < 0)
return dirfd;
/*
* If supported, force pass-through config term (pt=1) even if user
* sets pt=0, which avoids senseless kernel errors.
*/
if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "format/pt", "%c", &c) == 1 &&
!(evsel->core.attr.config & 1)) {
pr_warning("pt=0 doesn't make sense, forcing pt=1\n");
evsel->core.attr.config |= 1;
}
err = intel_pt_val_config_term(intel_pt_pmu, dirfd, "caps/cycle_thresholds",
"cyc_thresh", "caps/psb_cyc",
evsel->core.attr.config);
if (err)
goto out;
err = intel_pt_val_config_term(intel_pt_pmu, dirfd, "caps/mtc_periods",
"mtc_period", "caps/mtc",
evsel->core.attr.config);
if (err)
goto out;
err = intel_pt_val_config_term(intel_pt_pmu, dirfd, "caps/psb_periods",
"psb_period", "caps/psb_cyc",
evsel->core.attr.config);
out:
close(dirfd);
return err;
}
static void intel_pt_min_max_sample_sz(struct evlist *evlist,
size_t *min_sz, size_t *max_sz)
{
struct evsel *evsel;
evlist__for_each_entry(evlist, evsel) {
size_t sz = evsel->core.attr.aux_sample_size;
if (!sz)
continue;
if (min_sz && (sz < *min_sz || !*min_sz))
*min_sz = sz;
if (max_sz && sz > *max_sz)
*max_sz = sz;
}
}
/*
* Currently, there is not enough information to disambiguate different PEBS
* events, so only allow one.
*/
static bool intel_pt_too_many_aux_output(struct evlist *evlist)
{
struct evsel *evsel;
int aux_output_cnt = 0;
evlist__for_each_entry(evlist, evsel)
aux_output_cnt += !!evsel->core.attr.aux_output;
if (aux_output_cnt > 1) {
pr_err(INTEL_PT_PMU_NAME " supports at most one event with aux-output\n");
return true;
}
return false;
}
static int intel_pt_recording_options(struct auxtrace_record *itr,
struct evlist *evlist,
struct record_opts *opts)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
struct perf_pmu *intel_pt_pmu = ptr->intel_pt_pmu;
bool have_timing_info, need_immediate = false;
struct evsel *evsel, *intel_pt_evsel = NULL;
const struct perf_cpu_map *cpus = evlist->core.user_requested_cpus;
bool privileged = perf_event_paranoid_check(-1);
u64 tsc_bit;
int err;
ptr->evlist = evlist;
ptr->snapshot_mode = opts->auxtrace_snapshot_mode;
evlist__for_each_entry(evlist, evsel) {
if (evsel->core.attr.type == intel_pt_pmu->type) {
if (intel_pt_evsel) {
pr_err("There may be only one " INTEL_PT_PMU_NAME " event\n");
return -EINVAL;
}
evsel->core.attr.freq = 0;
evsel->core.attr.sample_period = 1;
evsel->no_aux_samples = true;
evsel->needs_auxtrace_mmap = true;
intel_pt_evsel = evsel;
opts->full_auxtrace = true;
}
}
if (opts->auxtrace_snapshot_mode && !opts->full_auxtrace) {
pr_err("Snapshot mode (-S option) requires " INTEL_PT_PMU_NAME " PMU event (-e " INTEL_PT_PMU_NAME ")\n");
return -EINVAL;
}
if (opts->auxtrace_snapshot_mode && opts->auxtrace_sample_mode) {
pr_err("Snapshot mode (" INTEL_PT_PMU_NAME " PMU) and sample trace cannot be used together\n");
return -EINVAL;
}
if (opts->use_clockid) {
pr_err("Cannot use clockid (-k option) with " INTEL_PT_PMU_NAME "\n");
return -EINVAL;
}
if (intel_pt_too_many_aux_output(evlist))
return -EINVAL;
if (!opts->full_auxtrace)
return 0;
if (opts->auxtrace_sample_mode)
evsel__set_config_if_unset(intel_pt_pmu, intel_pt_evsel,
"psb_period", 0);
err = intel_pt_validate_config(intel_pt_pmu, intel_pt_evsel);
if (err)
return err;
/* Set default sizes for snapshot mode */
if (opts->auxtrace_snapshot_mode) {
size_t psb_period = intel_pt_psb_period(intel_pt_pmu, evlist);
if (!opts->auxtrace_snapshot_size && !opts->auxtrace_mmap_pages) {
if (privileged) {
opts->auxtrace_mmap_pages = MiB(4) / page_size;
} else {
opts->auxtrace_mmap_pages = KiB(128) / page_size;
if (opts->mmap_pages == UINT_MAX)
opts->mmap_pages = KiB(256) / page_size;
}
} else if (!opts->auxtrace_mmap_pages && !privileged &&
opts->mmap_pages == UINT_MAX) {
opts->mmap_pages = KiB(256) / page_size;
}
if (!opts->auxtrace_snapshot_size)
opts->auxtrace_snapshot_size =
opts->auxtrace_mmap_pages * (size_t)page_size;
if (!opts->auxtrace_mmap_pages) {
size_t sz = opts->auxtrace_snapshot_size;
sz = round_up(sz, page_size) / page_size;
opts->auxtrace_mmap_pages = roundup_pow_of_two(sz);
}
if (opts->auxtrace_snapshot_size >
opts->auxtrace_mmap_pages * (size_t)page_size) {
pr_err("Snapshot size %zu must not be greater than AUX area tracing mmap size %zu\n",
opts->auxtrace_snapshot_size,
opts->auxtrace_mmap_pages * (size_t)page_size);
return -EINVAL;
}
if (!opts->auxtrace_snapshot_size || !opts->auxtrace_mmap_pages) {
pr_err("Failed to calculate default snapshot size and/or AUX area tracing mmap pages\n");
return -EINVAL;
}
pr_debug2("Intel PT snapshot size: %zu\n",
opts->auxtrace_snapshot_size);
if (psb_period &&
opts->auxtrace_snapshot_size <= psb_period +
INTEL_PT_PSB_PERIOD_NEAR)
ui__warning("Intel PT snapshot size (%zu) may be too small for PSB period (%zu)\n",
opts->auxtrace_snapshot_size, psb_period);
}
/* Set default sizes for sample mode */
if (opts->auxtrace_sample_mode) {
size_t psb_period = intel_pt_psb_period(intel_pt_pmu, evlist);
size_t min_sz = 0, max_sz = 0;
intel_pt_min_max_sample_sz(evlist, &min_sz, &max_sz);
if (!opts->auxtrace_mmap_pages && !privileged &&
opts->mmap_pages == UINT_MAX)
opts->mmap_pages = KiB(256) / page_size;
if (!opts->auxtrace_mmap_pages) {
size_t sz = round_up(max_sz, page_size) / page_size;
opts->auxtrace_mmap_pages = roundup_pow_of_two(sz);
}
if (max_sz > opts->auxtrace_mmap_pages * (size_t)page_size) {
pr_err("Sample size %zu must not be greater than AUX area tracing mmap size %zu\n",
max_sz,
opts->auxtrace_mmap_pages * (size_t)page_size);
return -EINVAL;
}
pr_debug2("Intel PT min. sample size: %zu max. sample size: %zu\n",
min_sz, max_sz);
if (psb_period &&
min_sz <= psb_period + INTEL_PT_PSB_PERIOD_NEAR)
ui__warning("Intel PT sample size (%zu) may be too small for PSB period (%zu)\n",
min_sz, psb_period);
}
/* Set default sizes for full trace mode */
if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) {
if (privileged) {
opts->auxtrace_mmap_pages = MiB(4) / page_size;
} else {
opts->auxtrace_mmap_pages = KiB(128) / page_size;
if (opts->mmap_pages == UINT_MAX)
opts->mmap_pages = KiB(256) / page_size;
}
}
/* Validate auxtrace_mmap_pages */
if (opts->auxtrace_mmap_pages) {
size_t sz = opts->auxtrace_mmap_pages * (size_t)page_size;
size_t min_sz;
if (opts->auxtrace_snapshot_mode || opts->auxtrace_sample_mode)
min_sz = KiB(4);
else
min_sz = KiB(8);
if (sz < min_sz || !is_power_of_2(sz)) {
pr_err("Invalid mmap size for Intel Processor Trace: must be at least %zuKiB and a power of 2\n",
min_sz / 1024);
return -EINVAL;
}
}
if (!opts->auxtrace_snapshot_mode && !opts->auxtrace_sample_mode) {
u32 aux_watermark = opts->auxtrace_mmap_pages * page_size / 4;
intel_pt_evsel->core.attr.aux_watermark = aux_watermark;
}
intel_pt_parse_terms(intel_pt_pmu, "tsc", &tsc_bit);
if (opts->full_auxtrace && (intel_pt_evsel->core.attr.config & tsc_bit))
have_timing_info = true;
else
have_timing_info = false;
/*
* Per-cpu recording needs sched_switch events to distinguish different
* threads.
*/
if (have_timing_info && !perf_cpu_map__empty(cpus) &&
!record_opts__no_switch_events(opts)) {
if (perf_can_record_switch_events()) {
bool cpu_wide = !target__none(&opts->target) &&
!target__has_task(&opts->target);
if (!cpu_wide && perf_can_record_cpu_wide()) {
struct evsel *switch_evsel;
switch_evsel = evlist__add_dummy_on_all_cpus(evlist);
if (!switch_evsel)
return -ENOMEM;
switch_evsel->core.attr.context_switch = 1;
switch_evsel->immediate = true;
evsel__set_sample_bit(switch_evsel, TID);
evsel__set_sample_bit(switch_evsel, TIME);
evsel__set_sample_bit(switch_evsel, CPU);
evsel__reset_sample_bit(switch_evsel, BRANCH_STACK);
opts->record_switch_events = false;
ptr->have_sched_switch = 3;
} else {
opts->record_switch_events = true;
need_immediate = true;
if (cpu_wide)
ptr->have_sched_switch = 3;
else
ptr->have_sched_switch = 2;
}
} else {
#ifdef HAVE_LIBTRACEEVENT
err = intel_pt_track_switches(evlist);
if (err == -EPERM)
pr_debug2("Unable to select sched:sched_switch\n");
else if (err)
return err;
else
ptr->have_sched_switch = 1;
#endif
}
}
if (have_timing_info && !intel_pt_evsel->core.attr.exclude_kernel &&
perf_can_record_text_poke_events() && perf_can_record_cpu_wide())
opts->text_poke = true;
if (intel_pt_evsel) {
/*
* To obtain the auxtrace buffer file descriptor, the auxtrace
* event must come first.
*/
evlist__to_front(evlist, intel_pt_evsel);
/*
* In the case of per-cpu mmaps, we need the CPU on the
* AUX event.
*/
if (!perf_cpu_map__empty(cpus))
evsel__set_sample_bit(intel_pt_evsel, CPU);
}
/* Add dummy event to keep tracking */
if (opts->full_auxtrace) {
bool need_system_wide_tracking;
struct evsel *tracking_evsel;
/*
* User space tasks can migrate between CPUs, so when tracing
* selected CPUs, sideband for all CPUs is still needed.
*/
need_system_wide_tracking = opts->target.cpu_list &&
!intel_pt_evsel->core.attr.exclude_user;
tracking_evsel = evlist__add_aux_dummy(evlist, need_system_wide_tracking);
if (!tracking_evsel)
return -ENOMEM;
evlist__set_tracking_event(evlist, tracking_evsel);
if (need_immediate)
tracking_evsel->immediate = true;
/* In per-cpu case, always need the time of mmap events etc */
if (!perf_cpu_map__empty(cpus)) {
evsel__set_sample_bit(tracking_evsel, TIME);
/* And the CPU for switch events */
evsel__set_sample_bit(tracking_evsel, CPU);
}
evsel__reset_sample_bit(tracking_evsel, BRANCH_STACK);
}
/*
* Warn the user when we do not have enough information to decode i.e.
* per-cpu with no sched_switch (except workload-only).
*/
if (!ptr->have_sched_switch && !perf_cpu_map__empty(cpus) &&
!target__none(&opts->target) &&
!intel_pt_evsel->core.attr.exclude_user)
ui__warning("Intel Processor Trace decoding will not be possible except for kernel tracing!\n");
return 0;
}
static int intel_pt_snapshot_start(struct auxtrace_record *itr)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
struct evsel *evsel;
evlist__for_each_entry(ptr->evlist, evsel) {
if (evsel->core.attr.type == ptr->intel_pt_pmu->type)
return evsel__disable(evsel);
}
return -EINVAL;
}
static int intel_pt_snapshot_finish(struct auxtrace_record *itr)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
struct evsel *evsel;
evlist__for_each_entry(ptr->evlist, evsel) {
if (evsel->core.attr.type == ptr->intel_pt_pmu->type)
return evsel__enable(evsel);
}
return -EINVAL;
}
static int intel_pt_alloc_snapshot_refs(struct intel_pt_recording *ptr, int idx)
{
const size_t sz = sizeof(struct intel_pt_snapshot_ref);
int cnt = ptr->snapshot_ref_cnt, new_cnt = cnt * 2;
struct intel_pt_snapshot_ref *refs;
if (!new_cnt)
new_cnt = 16;
while (new_cnt <= idx)
new_cnt *= 2;
refs = calloc(new_cnt, sz);
if (!refs)
return -ENOMEM;
memcpy(refs, ptr->snapshot_refs, cnt * sz);
ptr->snapshot_refs = refs;
ptr->snapshot_ref_cnt = new_cnt;
return 0;
}
static void intel_pt_free_snapshot_refs(struct intel_pt_recording *ptr)
{
int i;
for (i = 0; i < ptr->snapshot_ref_cnt; i++)
zfree(&ptr->snapshot_refs[i].ref_buf);
zfree(&ptr->snapshot_refs);
}
static void intel_pt_recording_free(struct auxtrace_record *itr)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
intel_pt_free_snapshot_refs(ptr);
free(ptr);
}
static int intel_pt_alloc_snapshot_ref(struct intel_pt_recording *ptr, int idx,
size_t snapshot_buf_size)
{
size_t ref_buf_size = ptr->snapshot_ref_buf_size;
void *ref_buf;
ref_buf = zalloc(ref_buf_size);
if (!ref_buf)
return -ENOMEM;
ptr->snapshot_refs[idx].ref_buf = ref_buf;
ptr->snapshot_refs[idx].ref_offset = snapshot_buf_size - ref_buf_size;
return 0;
}
static size_t intel_pt_snapshot_ref_buf_size(struct intel_pt_recording *ptr,
size_t snapshot_buf_size)
{
const size_t max_size = 256 * 1024;
size_t buf_size = 0, psb_period;
if (ptr->snapshot_size <= 64 * 1024)
return 0;
psb_period = intel_pt_psb_period(ptr->intel_pt_pmu, ptr->evlist);
if (psb_period)
buf_size = psb_period * 2;
if (!buf_size || buf_size > max_size)
buf_size = max_size;
if (buf_size >= snapshot_buf_size)
return 0;
if (buf_size >= ptr->snapshot_size / 2)
return 0;
return buf_size;
}
static int intel_pt_snapshot_init(struct intel_pt_recording *ptr,
size_t snapshot_buf_size)
{
if (ptr->snapshot_init_done)
return 0;
ptr->snapshot_init_done = true;
ptr->snapshot_ref_buf_size = intel_pt_snapshot_ref_buf_size(ptr,
snapshot_buf_size);
return 0;
}
/**
* intel_pt_compare_buffers - compare bytes in a buffer to a circular buffer.
* @buf1: first buffer
* @compare_size: number of bytes to compare
* @buf2: second buffer (a circular buffer)
* @offs2: offset in second buffer
* @buf2_size: size of second buffer
*
* The comparison allows for the possibility that the bytes to compare in the
* circular buffer are not contiguous. It is assumed that @compare_size <=
* @buf2_size. This function returns %false if the bytes are identical, %true
* otherwise.
*/
static bool intel_pt_compare_buffers(void *buf1, size_t compare_size,
void *buf2, size_t offs2, size_t buf2_size)
{
size_t end2 = offs2 + compare_size, part_size;
if (end2 <= buf2_size)
return memcmp(buf1, buf2 + offs2, compare_size);
part_size = end2 - buf2_size;
if (memcmp(buf1, buf2 + offs2, part_size))
return true;
compare_size -= part_size;
return memcmp(buf1 + part_size, buf2, compare_size);
}
static bool intel_pt_compare_ref(void *ref_buf, size_t ref_offset,
size_t ref_size, size_t buf_size,
void *data, size_t head)
{
size_t ref_end = ref_offset + ref_size;
if (ref_end > buf_size) {
if (head > ref_offset || head < ref_end - buf_size)
return true;
} else if (head > ref_offset && head < ref_end) {
return true;
}
return intel_pt_compare_buffers(ref_buf, ref_size, data, ref_offset,
buf_size);
}
static void intel_pt_copy_ref(void *ref_buf, size_t ref_size, size_t buf_size,
void *data, size_t head)
{
if (head >= ref_size) {
memcpy(ref_buf, data + head - ref_size, ref_size);
} else {
memcpy(ref_buf, data, head);
ref_size -= head;
memcpy(ref_buf + head, data + buf_size - ref_size, ref_size);
}
}
static bool intel_pt_wrapped(struct intel_pt_recording *ptr, int idx,
struct auxtrace_mmap *mm, unsigned char *data,
u64 head)
{
struct intel_pt_snapshot_ref *ref = &ptr->snapshot_refs[idx];
bool wrapped;
wrapped = intel_pt_compare_ref(ref->ref_buf, ref->ref_offset,
ptr->snapshot_ref_buf_size, mm->len,
data, head);
intel_pt_copy_ref(ref->ref_buf, ptr->snapshot_ref_buf_size, mm->len,
data, head);
return wrapped;
}
static bool intel_pt_first_wrap(u64 *data, size_t buf_size)
{
int i, a, b;
b = buf_size >> 3;
a = b - 512;
if (a < 0)
a = 0;
for (i = a; i < b; i++) {
if (data[i])
return true;
}
return false;
}
static int intel_pt_find_snapshot(struct auxtrace_record *itr, int idx,
struct auxtrace_mmap *mm, unsigned char *data,
u64 *head, u64 *old)
{
struct intel_pt_recording *ptr =
container_of(itr, struct intel_pt_recording, itr);
bool wrapped;
int err;
pr_debug3("%s: mmap index %d old head %zu new head %zu\n",
__func__, idx, (size_t)*old, (size_t)*head);
err = intel_pt_snapshot_init(ptr, mm->len);
if (err)
goto out_err;
if (idx >= ptr->snapshot_ref_cnt) {
err = intel_pt_alloc_snapshot_refs(ptr, idx);
if (err)
goto out_err;
}
if (ptr->snapshot_ref_buf_size) {
if (!ptr->snapshot_refs[idx].ref_buf) {
err = intel_pt_alloc_snapshot_ref(ptr, idx, mm->len);
if (err)
goto out_err;
}
wrapped = intel_pt_wrapped(ptr, idx, mm, data, *head);
} else {
wrapped = ptr->snapshot_refs[idx].wrapped;
if (!wrapped && intel_pt_first_wrap((u64 *)data, mm->len)) {
ptr->snapshot_refs[idx].wrapped = true;
wrapped = true;
}
}
/*
* In full trace mode 'head' continually increases. However in snapshot
* mode 'head' is an offset within the buffer. Here 'old' and 'head'
* are adjusted to match the full trace case which expects that 'old' is
* always less than 'head'.
*/
if (wrapped) {
*old = *head;
*head += mm->len;
} else {
if (mm->mask)
*old &= mm->mask;
else
*old %= mm->len;
if (*old > *head)
*head += mm->len;
}
pr_debug3("%s: wrap-around %sdetected, adjusted old head %zu adjusted new head %zu\n",
__func__, wrapped ? "" : "not ", (size_t)*old, (size_t)*head);
return 0;
out_err:
pr_err("%s: failed, error %d\n", __func__, err);
return err;
}
static u64 intel_pt_reference(struct auxtrace_record *itr __maybe_unused)
{
return rdtsc();
}
struct auxtrace_record *intel_pt_recording_init(int *err)
{
struct perf_pmu *intel_pt_pmu = perf_pmus__find(INTEL_PT_PMU_NAME);
struct intel_pt_recording *ptr;
if (!intel_pt_pmu)
return NULL;
if (setenv("JITDUMP_USE_ARCH_TIMESTAMP", "1", 1)) {
*err = -errno;
return NULL;
}
ptr = zalloc(sizeof(struct intel_pt_recording));
if (!ptr) {
*err = -ENOMEM;
return NULL;
}
ptr->intel_pt_pmu = intel_pt_pmu;
ptr->itr.pmu = intel_pt_pmu;
ptr->itr.recording_options = intel_pt_recording_options;
ptr->itr.info_priv_size = intel_pt_info_priv_size;
ptr->itr.info_fill = intel_pt_info_fill;
ptr->itr.free = intel_pt_recording_free;
ptr->itr.snapshot_start = intel_pt_snapshot_start;
ptr->itr.snapshot_finish = intel_pt_snapshot_finish;
ptr->itr.find_snapshot = intel_pt_find_snapshot;
ptr->itr.parse_snapshot_options = intel_pt_parse_snapshot_options;
ptr->itr.reference = intel_pt_reference;
ptr->itr.read_finish = auxtrace_record__read_finish;
/*
* Decoding starts at a PSB packet. Minimum PSB period is 2K so 4K
* should give at least 1 PSB per sample.
*/
ptr->itr.default_aux_sample_size = 4096;
return &ptr->itr;
}
| linux-master | tools/perf/arch/x86/util/intel-pt.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include <string.h>
#include "../../../util/kvm-stat.h"
#include "../../../util/evsel.h"
#include <asm/svm.h>
#include <asm/vmx.h>
#include <asm/kvm.h>
define_exit_reasons_table(vmx_exit_reasons, VMX_EXIT_REASONS);
define_exit_reasons_table(svm_exit_reasons, SVM_EXIT_REASONS);
static struct kvm_events_ops exit_events = {
.is_begin_event = exit_event_begin,
.is_end_event = exit_event_end,
.decode_key = exit_event_decode_key,
.name = "VM-EXIT"
};
const char *vcpu_id_str = "vcpu_id";
const char *kvm_exit_reason = "exit_reason";
const char *kvm_entry_trace = "kvm:kvm_entry";
const char *kvm_exit_trace = "kvm:kvm_exit";
/*
* For the mmio events, we treat:
* the time of MMIO write: kvm_mmio(KVM_TRACE_MMIO_WRITE...) -> kvm_entry
* the time of MMIO read: kvm_exit -> kvm_mmio(KVM_TRACE_MMIO_READ...).
*/
static void mmio_event_get_key(struct evsel *evsel, struct perf_sample *sample,
struct event_key *key)
{
key->key = evsel__intval(evsel, sample, "gpa");
key->info = evsel__intval(evsel, sample, "type");
}
#define KVM_TRACE_MMIO_READ_UNSATISFIED 0
#define KVM_TRACE_MMIO_READ 1
#define KVM_TRACE_MMIO_WRITE 2
static bool mmio_event_begin(struct evsel *evsel,
struct perf_sample *sample, struct event_key *key)
{
/* MMIO read begin event in kernel. */
if (kvm_exit_event(evsel))
return true;
/* MMIO write begin event in kernel. */
if (evsel__name_is(evsel, "kvm:kvm_mmio") &&
evsel__intval(evsel, sample, "type") == KVM_TRACE_MMIO_WRITE) {
mmio_event_get_key(evsel, sample, key);
return true;
}
return false;
}
static bool mmio_event_end(struct evsel *evsel, struct perf_sample *sample,
struct event_key *key)
{
/* MMIO write end event in kernel. */
if (kvm_entry_event(evsel))
return true;
/* MMIO read end event in kernel.*/
if (evsel__name_is(evsel, "kvm:kvm_mmio") &&
evsel__intval(evsel, sample, "type") == KVM_TRACE_MMIO_READ) {
mmio_event_get_key(evsel, sample, key);
return true;
}
return false;
}
static void mmio_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused,
struct event_key *key,
char *decode)
{
scnprintf(decode, KVM_EVENT_NAME_LEN, "%#lx:%s",
(unsigned long)key->key,
key->info == KVM_TRACE_MMIO_WRITE ? "W" : "R");
}
static struct kvm_events_ops mmio_events = {
.is_begin_event = mmio_event_begin,
.is_end_event = mmio_event_end,
.decode_key = mmio_event_decode_key,
.name = "MMIO Access"
};
/* The time of emulation pio access is from kvm_pio to kvm_entry. */
static void ioport_event_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
key->key = evsel__intval(evsel, sample, "port");
key->info = evsel__intval(evsel, sample, "rw");
}
static bool ioport_event_begin(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
if (evsel__name_is(evsel, "kvm:kvm_pio")) {
ioport_event_get_key(evsel, sample, key);
return true;
}
return false;
}
static bool ioport_event_end(struct evsel *evsel,
struct perf_sample *sample __maybe_unused,
struct event_key *key __maybe_unused)
{
return kvm_entry_event(evsel);
}
static void ioport_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused,
struct event_key *key,
char *decode)
{
scnprintf(decode, KVM_EVENT_NAME_LEN, "%#llx:%s",
(unsigned long long)key->key,
key->info ? "POUT" : "PIN");
}
static struct kvm_events_ops ioport_events = {
.is_begin_event = ioport_event_begin,
.is_end_event = ioport_event_end,
.decode_key = ioport_event_decode_key,
.name = "IO Port Access"
};
/* The time of emulation msr is from kvm_msr to kvm_entry. */
static void msr_event_get_key(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
key->key = evsel__intval(evsel, sample, "ecx");
key->info = evsel__intval(evsel, sample, "write");
}
static bool msr_event_begin(struct evsel *evsel,
struct perf_sample *sample,
struct event_key *key)
{
if (evsel__name_is(evsel, "kvm:kvm_msr")) {
msr_event_get_key(evsel, sample, key);
return true;
}
return false;
}
static bool msr_event_end(struct evsel *evsel,
struct perf_sample *sample __maybe_unused,
struct event_key *key __maybe_unused)
{
return kvm_entry_event(evsel);
}
static void msr_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused,
struct event_key *key,
char *decode)
{
scnprintf(decode, KVM_EVENT_NAME_LEN, "%#llx:%s",
(unsigned long long)key->key,
key->info ? "W" : "R");
}
static struct kvm_events_ops msr_events = {
.is_begin_event = msr_event_begin,
.is_end_event = msr_event_end,
.decode_key = msr_event_decode_key,
.name = "MSR Access"
};
const char *kvm_events_tp[] = {
"kvm:kvm_entry",
"kvm:kvm_exit",
"kvm:kvm_mmio",
"kvm:kvm_pio",
"kvm:kvm_msr",
NULL,
};
struct kvm_reg_events_ops kvm_reg_events_ops[] = {
{ .name = "vmexit", .ops = &exit_events },
{ .name = "mmio", .ops = &mmio_events },
{ .name = "ioport", .ops = &ioport_events },
{ .name = "msr", .ops = &msr_events },
{ NULL, NULL },
};
const char * const kvm_skip_events[] = {
"HLT",
NULL,
};
int cpu_isa_init(struct perf_kvm_stat *kvm, const char *cpuid)
{
if (strstr(cpuid, "Intel")) {
kvm->exit_reasons = vmx_exit_reasons;
kvm->exit_reasons_isa = "VMX";
} else if (strstr(cpuid, "AMD") || strstr(cpuid, "Hygon")) {
kvm->exit_reasons = svm_exit_reasons;
kvm->exit_reasons_isa = "SVM";
} else
return -ENOTSUP;
return 0;
}
| linux-master | tools/perf/arch/x86/util/kvm-stat.c |
// SPDX-License-Identifier: GPL-2.0
#include "api/fs/fs.h"
#include "util/evsel.h"
#include "util/pmu.h"
#include "util/pmus.h"
#include "util/topdown.h"
#include "topdown.h"
#include "evsel.h"
/* Check whether there is a PMU which supports the perf metrics. */
bool topdown_sys_has_perf_metrics(void)
{
static bool has_perf_metrics;
static bool cached;
struct perf_pmu *pmu;
if (cached)
return has_perf_metrics;
/*
* The perf metrics feature is a core PMU feature.
* The PERF_TYPE_RAW type is the type of a core PMU.
* The slots event is only available when the core PMU
* supports the perf metrics feature.
*/
pmu = perf_pmus__find_by_type(PERF_TYPE_RAW);
if (pmu && perf_pmu__have_event(pmu, "slots"))
has_perf_metrics = true;
cached = true;
return has_perf_metrics;
}
#define TOPDOWN_SLOTS 0x0400
/*
* Check whether a topdown group supports sample-read.
*
* Only Topdown metric supports sample-read. The slots
* event must be the leader of the topdown group.
*/
bool arch_topdown_sample_read(struct evsel *leader)
{
if (!evsel__sys_has_perf_metrics(leader))
return false;
if (leader->core.attr.config == TOPDOWN_SLOTS)
return true;
return false;
}
| linux-master | tools/perf/arch/x86/util/topdown.c |
// SPDX-License-Identifier: GPL-2.0
#include "linux/string.h"
#include "util/env.h"
#include "env.h"
bool x86__is_amd_cpu(void)
{
struct perf_env env = { .total_mem = 0, };
static int is_amd; /* 0: Uninitialized, 1: Yes, -1: No */
if (is_amd)
goto ret;
perf_env__cpuid(&env);
is_amd = env.cpuid && strstarts(env.cpuid, "AuthenticAMD") ? 1 : -1;
perf_env__exit(&env);
ret:
return is_amd >= 1 ? true : false;
}
| linux-master | tools/perf/arch/x86/util/env.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* intel-bts.c: Intel Processor Trace support
* Copyright (c) 2013-2015, Intel Corporation.
*/
#include <errno.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/log2.h>
#include <linux/zalloc.h>
#include "../../../util/cpumap.h"
#include "../../../util/event.h"
#include "../../../util/evsel.h"
#include "../../../util/evlist.h"
#include "../../../util/mmap.h"
#include "../../../util/session.h"
#include "../../../util/pmus.h"
#include "../../../util/debug.h"
#include "../../../util/record.h"
#include "../../../util/tsc.h"
#include "../../../util/auxtrace.h"
#include "../../../util/intel-bts.h"
#include <internal/lib.h> // page_size
#define KiB(x) ((x) * 1024)
#define MiB(x) ((x) * 1024 * 1024)
#define KiB_MASK(x) (KiB(x) - 1)
#define MiB_MASK(x) (MiB(x) - 1)
struct intel_bts_snapshot_ref {
void *ref_buf;
size_t ref_offset;
bool wrapped;
};
struct intel_bts_recording {
struct auxtrace_record itr;
struct perf_pmu *intel_bts_pmu;
struct evlist *evlist;
bool snapshot_mode;
size_t snapshot_size;
int snapshot_ref_cnt;
struct intel_bts_snapshot_ref *snapshot_refs;
};
struct branch {
u64 from;
u64 to;
u64 misc;
};
static size_t
intel_bts_info_priv_size(struct auxtrace_record *itr __maybe_unused,
struct evlist *evlist __maybe_unused)
{
return INTEL_BTS_AUXTRACE_PRIV_SIZE;
}
static int intel_bts_info_fill(struct auxtrace_record *itr,
struct perf_session *session,
struct perf_record_auxtrace_info *auxtrace_info,
size_t priv_size)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
struct perf_pmu *intel_bts_pmu = btsr->intel_bts_pmu;
struct perf_event_mmap_page *pc;
struct perf_tsc_conversion tc = { .time_mult = 0, };
bool cap_user_time_zero = false;
int err;
if (priv_size != INTEL_BTS_AUXTRACE_PRIV_SIZE)
return -EINVAL;
if (!session->evlist->core.nr_mmaps)
return -EINVAL;
pc = session->evlist->mmap[0].core.base;
if (pc) {
err = perf_read_tsc_conversion(pc, &tc);
if (err) {
if (err != -EOPNOTSUPP)
return err;
} else {
cap_user_time_zero = tc.time_mult != 0;
}
if (!cap_user_time_zero)
ui__warning("Intel BTS: TSC not available\n");
}
auxtrace_info->type = PERF_AUXTRACE_INTEL_BTS;
auxtrace_info->priv[INTEL_BTS_PMU_TYPE] = intel_bts_pmu->type;
auxtrace_info->priv[INTEL_BTS_TIME_SHIFT] = tc.time_shift;
auxtrace_info->priv[INTEL_BTS_TIME_MULT] = tc.time_mult;
auxtrace_info->priv[INTEL_BTS_TIME_ZERO] = tc.time_zero;
auxtrace_info->priv[INTEL_BTS_CAP_USER_TIME_ZERO] = cap_user_time_zero;
auxtrace_info->priv[INTEL_BTS_SNAPSHOT_MODE] = btsr->snapshot_mode;
return 0;
}
static int intel_bts_recording_options(struct auxtrace_record *itr,
struct evlist *evlist,
struct record_opts *opts)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
struct perf_pmu *intel_bts_pmu = btsr->intel_bts_pmu;
struct evsel *evsel, *intel_bts_evsel = NULL;
const struct perf_cpu_map *cpus = evlist->core.user_requested_cpus;
bool privileged = perf_event_paranoid_check(-1);
if (opts->auxtrace_sample_mode) {
pr_err("Intel BTS does not support AUX area sampling\n");
return -EINVAL;
}
btsr->evlist = evlist;
btsr->snapshot_mode = opts->auxtrace_snapshot_mode;
evlist__for_each_entry(evlist, evsel) {
if (evsel->core.attr.type == intel_bts_pmu->type) {
if (intel_bts_evsel) {
pr_err("There may be only one " INTEL_BTS_PMU_NAME " event\n");
return -EINVAL;
}
evsel->core.attr.freq = 0;
evsel->core.attr.sample_period = 1;
evsel->needs_auxtrace_mmap = true;
intel_bts_evsel = evsel;
opts->full_auxtrace = true;
}
}
if (opts->auxtrace_snapshot_mode && !opts->full_auxtrace) {
pr_err("Snapshot mode (-S option) requires " INTEL_BTS_PMU_NAME " PMU event (-e " INTEL_BTS_PMU_NAME ")\n");
return -EINVAL;
}
if (!opts->full_auxtrace)
return 0;
if (opts->full_auxtrace && !perf_cpu_map__empty(cpus)) {
pr_err(INTEL_BTS_PMU_NAME " does not support per-cpu recording\n");
return -EINVAL;
}
/* Set default sizes for snapshot mode */
if (opts->auxtrace_snapshot_mode) {
if (!opts->auxtrace_snapshot_size && !opts->auxtrace_mmap_pages) {
if (privileged) {
opts->auxtrace_mmap_pages = MiB(4) / page_size;
} else {
opts->auxtrace_mmap_pages = KiB(128) / page_size;
if (opts->mmap_pages == UINT_MAX)
opts->mmap_pages = KiB(256) / page_size;
}
} else if (!opts->auxtrace_mmap_pages && !privileged &&
opts->mmap_pages == UINT_MAX) {
opts->mmap_pages = KiB(256) / page_size;
}
if (!opts->auxtrace_snapshot_size)
opts->auxtrace_snapshot_size =
opts->auxtrace_mmap_pages * (size_t)page_size;
if (!opts->auxtrace_mmap_pages) {
size_t sz = opts->auxtrace_snapshot_size;
sz = round_up(sz, page_size) / page_size;
opts->auxtrace_mmap_pages = roundup_pow_of_two(sz);
}
if (opts->auxtrace_snapshot_size >
opts->auxtrace_mmap_pages * (size_t)page_size) {
pr_err("Snapshot size %zu must not be greater than AUX area tracing mmap size %zu\n",
opts->auxtrace_snapshot_size,
opts->auxtrace_mmap_pages * (size_t)page_size);
return -EINVAL;
}
if (!opts->auxtrace_snapshot_size || !opts->auxtrace_mmap_pages) {
pr_err("Failed to calculate default snapshot size and/or AUX area tracing mmap pages\n");
return -EINVAL;
}
pr_debug2("Intel BTS snapshot size: %zu\n",
opts->auxtrace_snapshot_size);
}
/* Set default sizes for full trace mode */
if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) {
if (privileged) {
opts->auxtrace_mmap_pages = MiB(4) / page_size;
} else {
opts->auxtrace_mmap_pages = KiB(128) / page_size;
if (opts->mmap_pages == UINT_MAX)
opts->mmap_pages = KiB(256) / page_size;
}
}
/* Validate auxtrace_mmap_pages */
if (opts->auxtrace_mmap_pages) {
size_t sz = opts->auxtrace_mmap_pages * (size_t)page_size;
size_t min_sz;
if (opts->auxtrace_snapshot_mode)
min_sz = KiB(4);
else
min_sz = KiB(8);
if (sz < min_sz || !is_power_of_2(sz)) {
pr_err("Invalid mmap size for Intel BTS: must be at least %zuKiB and a power of 2\n",
min_sz / 1024);
return -EINVAL;
}
}
if (intel_bts_evsel) {
/*
* To obtain the auxtrace buffer file descriptor, the auxtrace event
* must come first.
*/
evlist__to_front(evlist, intel_bts_evsel);
/*
* In the case of per-cpu mmaps, we need the CPU on the
* AUX event.
*/
if (!perf_cpu_map__empty(cpus))
evsel__set_sample_bit(intel_bts_evsel, CPU);
}
/* Add dummy event to keep tracking */
if (opts->full_auxtrace) {
struct evsel *tracking_evsel;
int err;
err = parse_event(evlist, "dummy:u");
if (err)
return err;
tracking_evsel = evlist__last(evlist);
evlist__set_tracking_event(evlist, tracking_evsel);
tracking_evsel->core.attr.freq = 0;
tracking_evsel->core.attr.sample_period = 1;
}
return 0;
}
static int intel_bts_parse_snapshot_options(struct auxtrace_record *itr,
struct record_opts *opts,
const char *str)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
unsigned long long snapshot_size = 0;
char *endptr;
if (str) {
snapshot_size = strtoull(str, &endptr, 0);
if (*endptr || snapshot_size > SIZE_MAX)
return -1;
}
opts->auxtrace_snapshot_mode = true;
opts->auxtrace_snapshot_size = snapshot_size;
btsr->snapshot_size = snapshot_size;
return 0;
}
static u64 intel_bts_reference(struct auxtrace_record *itr __maybe_unused)
{
return rdtsc();
}
static int intel_bts_alloc_snapshot_refs(struct intel_bts_recording *btsr,
int idx)
{
const size_t sz = sizeof(struct intel_bts_snapshot_ref);
int cnt = btsr->snapshot_ref_cnt, new_cnt = cnt * 2;
struct intel_bts_snapshot_ref *refs;
if (!new_cnt)
new_cnt = 16;
while (new_cnt <= idx)
new_cnt *= 2;
refs = calloc(new_cnt, sz);
if (!refs)
return -ENOMEM;
memcpy(refs, btsr->snapshot_refs, cnt * sz);
btsr->snapshot_refs = refs;
btsr->snapshot_ref_cnt = new_cnt;
return 0;
}
static void intel_bts_free_snapshot_refs(struct intel_bts_recording *btsr)
{
int i;
for (i = 0; i < btsr->snapshot_ref_cnt; i++)
zfree(&btsr->snapshot_refs[i].ref_buf);
zfree(&btsr->snapshot_refs);
}
static void intel_bts_recording_free(struct auxtrace_record *itr)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
intel_bts_free_snapshot_refs(btsr);
free(btsr);
}
static int intel_bts_snapshot_start(struct auxtrace_record *itr)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
struct evsel *evsel;
evlist__for_each_entry(btsr->evlist, evsel) {
if (evsel->core.attr.type == btsr->intel_bts_pmu->type)
return evsel__disable(evsel);
}
return -EINVAL;
}
static int intel_bts_snapshot_finish(struct auxtrace_record *itr)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
struct evsel *evsel;
evlist__for_each_entry(btsr->evlist, evsel) {
if (evsel->core.attr.type == btsr->intel_bts_pmu->type)
return evsel__enable(evsel);
}
return -EINVAL;
}
static bool intel_bts_first_wrap(u64 *data, size_t buf_size)
{
int i, a, b;
b = buf_size >> 3;
a = b - 512;
if (a < 0)
a = 0;
for (i = a; i < b; i++) {
if (data[i])
return true;
}
return false;
}
static int intel_bts_find_snapshot(struct auxtrace_record *itr, int idx,
struct auxtrace_mmap *mm, unsigned char *data,
u64 *head, u64 *old)
{
struct intel_bts_recording *btsr =
container_of(itr, struct intel_bts_recording, itr);
bool wrapped;
int err;
pr_debug3("%s: mmap index %d old head %zu new head %zu\n",
__func__, idx, (size_t)*old, (size_t)*head);
if (idx >= btsr->snapshot_ref_cnt) {
err = intel_bts_alloc_snapshot_refs(btsr, idx);
if (err)
goto out_err;
}
wrapped = btsr->snapshot_refs[idx].wrapped;
if (!wrapped && intel_bts_first_wrap((u64 *)data, mm->len)) {
btsr->snapshot_refs[idx].wrapped = true;
wrapped = true;
}
/*
* In full trace mode 'head' continually increases. However in snapshot
* mode 'head' is an offset within the buffer. Here 'old' and 'head'
* are adjusted to match the full trace case which expects that 'old' is
* always less than 'head'.
*/
if (wrapped) {
*old = *head;
*head += mm->len;
} else {
if (mm->mask)
*old &= mm->mask;
else
*old %= mm->len;
if (*old > *head)
*head += mm->len;
}
pr_debug3("%s: wrap-around %sdetected, adjusted old head %zu adjusted new head %zu\n",
__func__, wrapped ? "" : "not ", (size_t)*old, (size_t)*head);
return 0;
out_err:
pr_err("%s: failed, error %d\n", __func__, err);
return err;
}
struct auxtrace_record *intel_bts_recording_init(int *err)
{
struct perf_pmu *intel_bts_pmu = perf_pmus__find(INTEL_BTS_PMU_NAME);
struct intel_bts_recording *btsr;
if (!intel_bts_pmu)
return NULL;
if (setenv("JITDUMP_USE_ARCH_TIMESTAMP", "1", 1)) {
*err = -errno;
return NULL;
}
btsr = zalloc(sizeof(struct intel_bts_recording));
if (!btsr) {
*err = -ENOMEM;
return NULL;
}
btsr->intel_bts_pmu = intel_bts_pmu;
btsr->itr.pmu = intel_bts_pmu;
btsr->itr.recording_options = intel_bts_recording_options;
btsr->itr.info_priv_size = intel_bts_info_priv_size;
btsr->itr.info_fill = intel_bts_info_fill;
btsr->itr.free = intel_bts_recording_free;
btsr->itr.snapshot_start = intel_bts_snapshot_start;
btsr->itr.snapshot_finish = intel_bts_snapshot_finish;
btsr->itr.find_snapshot = intel_bts_find_snapshot;
btsr->itr.parse_snapshot_options = intel_bts_parse_snapshot_options;
btsr->itr.reference = intel_bts_reference;
btsr->itr.read_finish = auxtrace_record__read_finish;
btsr->itr.alignment = sizeof(struct branch);
return &btsr->itr;
}
| linux-master | tools/perf/arch/x86/util/intel-bts.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* dwarf-regs.c : Mapping of DWARF debug register numbers into register names.
* Extracted from probe-finder.c
*
* Written by Masami Hiramatsu <[email protected]>
*/
#include <stddef.h>
#include <errno.h> /* for EINVAL */
#include <string.h> /* for strcmp */
#include <linux/ptrace.h> /* for struct pt_regs */
#include <linux/kernel.h> /* for offsetof */
#include <dwarf-regs.h>
/*
* See arch/x86/kernel/ptrace.c.
* Different from it:
*
* - Since struct pt_regs is defined differently for user and kernel,
* but we want to use 'ax, bx' instead of 'rax, rbx' (which is struct
* field name of user's pt_regs), we make REG_OFFSET_NAME to accept
* both string name and reg field name.
*
* - Since accessing x86_32's pt_regs from x86_64 building is difficult
* and vise versa, we simply fill offset with -1, so
* get_arch_regstr() still works but regs_query_register_offset()
* returns error.
* The only inconvenience caused by it now is that we are not allowed
* to generate BPF prologue for a x86_64 kernel if perf is built for
* x86_32. This is really a rare usecase.
*
* - Order is different from kernel's ptrace.c for get_arch_regstr(). Use
* the order defined by dwarf.
*/
struct pt_regs_offset {
const char *name;
int offset;
};
#define REG_OFFSET_END {.name = NULL, .offset = 0}
#ifdef __x86_64__
# define REG_OFFSET_NAME_64(n, r) {.name = n, .offset = offsetof(struct pt_regs, r)}
# define REG_OFFSET_NAME_32(n, r) {.name = n, .offset = -1}
#else
# define REG_OFFSET_NAME_64(n, r) {.name = n, .offset = -1}
# define REG_OFFSET_NAME_32(n, r) {.name = n, .offset = offsetof(struct pt_regs, r)}
#endif
/* TODO: switching by dwarf address size */
#ifndef __x86_64__
static const struct pt_regs_offset x86_32_regoffset_table[] = {
REG_OFFSET_NAME_32("%ax", eax),
REG_OFFSET_NAME_32("%cx", ecx),
REG_OFFSET_NAME_32("%dx", edx),
REG_OFFSET_NAME_32("%bx", ebx),
REG_OFFSET_NAME_32("$stack", esp), /* Stack address instead of %sp */
REG_OFFSET_NAME_32("%bp", ebp),
REG_OFFSET_NAME_32("%si", esi),
REG_OFFSET_NAME_32("%di", edi),
REG_OFFSET_END,
};
#define regoffset_table x86_32_regoffset_table
#else
static const struct pt_regs_offset x86_64_regoffset_table[] = {
REG_OFFSET_NAME_64("%ax", rax),
REG_OFFSET_NAME_64("%dx", rdx),
REG_OFFSET_NAME_64("%cx", rcx),
REG_OFFSET_NAME_64("%bx", rbx),
REG_OFFSET_NAME_64("%si", rsi),
REG_OFFSET_NAME_64("%di", rdi),
REG_OFFSET_NAME_64("%bp", rbp),
REG_OFFSET_NAME_64("%sp", rsp),
REG_OFFSET_NAME_64("%r8", r8),
REG_OFFSET_NAME_64("%r9", r9),
REG_OFFSET_NAME_64("%r10", r10),
REG_OFFSET_NAME_64("%r11", r11),
REG_OFFSET_NAME_64("%r12", r12),
REG_OFFSET_NAME_64("%r13", r13),
REG_OFFSET_NAME_64("%r14", r14),
REG_OFFSET_NAME_64("%r15", r15),
REG_OFFSET_END,
};
#define regoffset_table x86_64_regoffset_table
#endif
/* Minus 1 for the ending REG_OFFSET_END */
#define ARCH_MAX_REGS ((sizeof(regoffset_table) / sizeof(regoffset_table[0])) - 1)
/* Return architecture dependent register string (for kprobe-tracer) */
const char *get_arch_regstr(unsigned int n)
{
return (n < ARCH_MAX_REGS) ? regoffset_table[n].name : NULL;
}
/* Reuse code from arch/x86/kernel/ptrace.c */
/**
* regs_query_register_offset() - query register offset from its name
* @name: the name of a register
*
* regs_query_register_offset() returns the offset of a register in struct
* pt_regs from its name. If the name is invalid, this returns -EINVAL;
*/
int regs_query_register_offset(const char *name)
{
const struct pt_regs_offset *roff;
for (roff = regoffset_table; roff->name != NULL; roff++)
if (!strcmp(roff->name, name))
return roff->offset;
return -EINVAL;
}
| linux-master | tools/perf/arch/x86/util/dwarf-regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <linux/string.h>
#include <linux/zalloc.h>
#include <stdlib.h>
#include "../../../util/event.h"
#include "../../../util/synthetic-events.h"
#include "../../../util/machine.h"
#include "../../../util/tool.h"
#include "../../../util/map.h"
#include "../../../util/debug.h"
#include "util/sample.h"
#if defined(__x86_64__)
int perf_event__synthesize_extra_kmaps(struct perf_tool *tool,
perf_event__handler_t process,
struct machine *machine)
{
int rc = 0;
struct map_rb_node *pos;
struct maps *kmaps = machine__kernel_maps(machine);
union perf_event *event = zalloc(sizeof(event->mmap) +
machine->id_hdr_size);
if (!event) {
pr_debug("Not enough memory synthesizing mmap event "
"for extra kernel maps\n");
return -1;
}
maps__for_each_entry(kmaps, pos) {
struct kmap *kmap;
size_t size;
struct map *map = pos->map;
if (!__map__is_extra_kernel_map(map))
continue;
kmap = map__kmap(map);
size = sizeof(event->mmap) - sizeof(event->mmap.filename) +
PERF_ALIGN(strlen(kmap->name) + 1, sizeof(u64)) +
machine->id_hdr_size;
memset(event, 0, size);
event->mmap.header.type = PERF_RECORD_MMAP;
/*
* kernel uses 0 for user space maps, see kernel/perf_event.c
* __perf_event_mmap
*/
if (machine__is_host(machine))
event->header.misc = PERF_RECORD_MISC_KERNEL;
else
event->header.misc = PERF_RECORD_MISC_GUEST_KERNEL;
event->mmap.header.size = size;
event->mmap.start = map__start(map);
event->mmap.len = map__size(map);
event->mmap.pgoff = map__pgoff(map);
event->mmap.pid = machine->pid;
strlcpy(event->mmap.filename, kmap->name, PATH_MAX);
if (perf_tool__process_synth_event(tool, event, machine,
process) != 0) {
rc = -1;
break;
}
}
free(event);
return rc;
}
#endif
void arch_perf_parse_sample_weight(struct perf_sample *data,
const __u64 *array, u64 type)
{
union perf_sample_weight weight;
weight.full = *array;
if (type & PERF_SAMPLE_WEIGHT)
data->weight = weight.full;
else {
data->weight = weight.var1_dw;
data->ins_lat = weight.var2_w;
data->retire_lat = weight.var3_w;
}
}
void arch_perf_synthesize_sample_weight(const struct perf_sample *data,
__u64 *array, u64 type)
{
*array = data->weight;
if (type & PERF_SAMPLE_WEIGHT_STRUCT) {
*array &= 0xffffffff;
*array |= ((u64)data->ins_lat << 32);
*array |= ((u64)data->retire_lat << 48);
}
}
const char *arch_perf_header_entry(const char *se_header)
{
if (!strcmp(se_header, "Local Pipeline Stage Cycle"))
return "Local Retire Latency";
else if (!strcmp(se_header, "Pipeline Stage Cycle"))
return "Retire Latency";
return se_header;
}
int arch_support_sort_key(const char *sort_key)
{
if (!strcmp(sort_key, "p_stage_cyc"))
return 1;
if (!strcmp(sort_key, "local_p_stage_cyc"))
return 1;
return 0;
}
| linux-master | tools/perf/arch/x86/util/event.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <linux/string.h>
#include <limits.h>
#include <stdlib.h>
#include <internal/lib.h> // page_size
#include "../../../util/machine.h"
#include "../../../util/map.h"
#include "../../../util/symbol.h"
#include <linux/ctype.h>
#include <symbol/kallsyms.h>
#if defined(__x86_64__)
struct extra_kernel_map_info {
int cnt;
int max_cnt;
struct extra_kernel_map *maps;
bool get_entry_trampolines;
u64 entry_trampoline;
};
static int add_extra_kernel_map(struct extra_kernel_map_info *mi, u64 start,
u64 end, u64 pgoff, const char *name)
{
if (mi->cnt >= mi->max_cnt) {
void *buf;
size_t sz;
mi->max_cnt = mi->max_cnt ? mi->max_cnt * 2 : 32;
sz = sizeof(struct extra_kernel_map) * mi->max_cnt;
buf = realloc(mi->maps, sz);
if (!buf)
return -1;
mi->maps = buf;
}
mi->maps[mi->cnt].start = start;
mi->maps[mi->cnt].end = end;
mi->maps[mi->cnt].pgoff = pgoff;
strlcpy(mi->maps[mi->cnt].name, name, KMAP_NAME_LEN);
mi->cnt += 1;
return 0;
}
static int find_extra_kernel_maps(void *arg, const char *name, char type,
u64 start)
{
struct extra_kernel_map_info *mi = arg;
if (!mi->entry_trampoline && kallsyms2elf_binding(type) == STB_GLOBAL &&
!strcmp(name, "_entry_trampoline")) {
mi->entry_trampoline = start;
return 0;
}
if (is_entry_trampoline(name)) {
u64 end = start + page_size;
return add_extra_kernel_map(mi, start, end, 0, name);
}
return 0;
}
int machine__create_extra_kernel_maps(struct machine *machine,
struct dso *kernel)
{
struct extra_kernel_map_info mi = { .cnt = 0, };
char filename[PATH_MAX];
int ret;
int i;
machine__get_kallsyms_filename(machine, filename, PATH_MAX);
if (symbol__restricted_filename(filename, "/proc/kallsyms"))
return 0;
ret = kallsyms__parse(filename, &mi, find_extra_kernel_maps);
if (ret)
goto out_free;
if (!mi.entry_trampoline)
goto out_free;
for (i = 0; i < mi.cnt; i++) {
struct extra_kernel_map *xm = &mi.maps[i];
xm->pgoff = mi.entry_trampoline;
ret = machine__create_extra_kernel_map(machine, kernel, xm);
if (ret)
goto out_free;
}
machine->trampolines_mapped = mi.cnt;
out_free:
free(mi.maps);
return ret;
}
#endif
| linux-master | tools/perf/arch/x86/util/machine.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include "../../util/debug.h"
#ifndef REMOTE_UNWIND_LIBUNWIND
#include <libunwind.h>
#include "perf_regs.h"
#include "../../util/unwind.h"
#endif
#ifdef HAVE_ARCH_X86_64_SUPPORT
int LIBUNWIND__ARCH_REG_ID(int regnum)
{
int id;
switch (regnum) {
case UNW_X86_64_RAX:
id = PERF_REG_X86_AX;
break;
case UNW_X86_64_RDX:
id = PERF_REG_X86_DX;
break;
case UNW_X86_64_RCX:
id = PERF_REG_X86_CX;
break;
case UNW_X86_64_RBX:
id = PERF_REG_X86_BX;
break;
case UNW_X86_64_RSI:
id = PERF_REG_X86_SI;
break;
case UNW_X86_64_RDI:
id = PERF_REG_X86_DI;
break;
case UNW_X86_64_RBP:
id = PERF_REG_X86_BP;
break;
case UNW_X86_64_RSP:
id = PERF_REG_X86_SP;
break;
case UNW_X86_64_R8:
id = PERF_REG_X86_R8;
break;
case UNW_X86_64_R9:
id = PERF_REG_X86_R9;
break;
case UNW_X86_64_R10:
id = PERF_REG_X86_R10;
break;
case UNW_X86_64_R11:
id = PERF_REG_X86_R11;
break;
case UNW_X86_64_R12:
id = PERF_REG_X86_R12;
break;
case UNW_X86_64_R13:
id = PERF_REG_X86_R13;
break;
case UNW_X86_64_R14:
id = PERF_REG_X86_R14;
break;
case UNW_X86_64_R15:
id = PERF_REG_X86_R15;
break;
case UNW_X86_64_RIP:
id = PERF_REG_X86_IP;
break;
default:
pr_err("unwind: invalid reg id %d\n", regnum);
return -EINVAL;
}
return id;
}
#else
int LIBUNWIND__ARCH_REG_ID(int regnum)
{
int id;
switch (regnum) {
case UNW_X86_EAX:
id = PERF_REG_X86_AX;
break;
case UNW_X86_EDX:
id = PERF_REG_X86_DX;
break;
case UNW_X86_ECX:
id = PERF_REG_X86_CX;
break;
case UNW_X86_EBX:
id = PERF_REG_X86_BX;
break;
case UNW_X86_ESI:
id = PERF_REG_X86_SI;
break;
case UNW_X86_EDI:
id = PERF_REG_X86_DI;
break;
case UNW_X86_EBP:
id = PERF_REG_X86_BP;
break;
case UNW_X86_ESP:
id = PERF_REG_X86_SP;
break;
case UNW_X86_EIP:
id = PERF_REG_X86_IP;
break;
default:
pr_err("unwind: invalid reg id %d\n", regnum);
return -EINVAL;
}
return id;
}
#endif /* HAVE_ARCH_X86_64_SUPPORT */
| linux-master | tools/perf/arch/x86/util/unwind-libunwind.c |
// SPDX-License-Identifier: GPL-2.0
#include <sys/types.h>
#include <errno.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <regex.h>
#include "../../../util/debug.h"
#include "../../../util/header.h"
#include "cpuid.h"
void get_cpuid_0(char *vendor, unsigned int *lvl)
{
unsigned int b, c, d;
cpuid(0, 0, lvl, &b, &c, &d);
strncpy(&vendor[0], (char *)(&b), 4);
strncpy(&vendor[4], (char *)(&d), 4);
strncpy(&vendor[8], (char *)(&c), 4);
vendor[12] = '\0';
}
static int
__get_cpuid(char *buffer, size_t sz, const char *fmt)
{
unsigned int a, b, c, d, lvl;
int family = -1, model = -1, step = -1;
int nb;
char vendor[16];
get_cpuid_0(vendor, &lvl);
if (lvl >= 1) {
cpuid(1, 0, &a, &b, &c, &d);
family = (a >> 8) & 0xf; /* bits 11 - 8 */
model = (a >> 4) & 0xf; /* Bits 7 - 4 */
step = a & 0xf;
/* extended family */
if (family == 0xf)
family += (a >> 20) & 0xff;
/* extended model */
if (family >= 0x6)
model += ((a >> 16) & 0xf) << 4;
}
nb = scnprintf(buffer, sz, fmt, vendor, family, model, step);
/* look for end marker to ensure the entire data fit */
if (strchr(buffer, '$')) {
buffer[nb-1] = '\0';
return 0;
}
return ENOBUFS;
}
int
get_cpuid(char *buffer, size_t sz)
{
return __get_cpuid(buffer, sz, "%s,%u,%u,%u$");
}
char *
get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
{
char *buf = malloc(128);
if (buf && __get_cpuid(buf, 128, "%s-%u-%X-%X$") < 0) {
free(buf);
return NULL;
}
return buf;
}
/* Full CPUID format for x86 is vendor-family-model-stepping */
static bool is_full_cpuid(const char *id)
{
const char *tmp = id;
int count = 0;
while ((tmp = strchr(tmp, '-')) != NULL) {
count++;
tmp++;
}
if (count == 3)
return true;
return false;
}
int strcmp_cpuid_str(const char *mapcpuid, const char *id)
{
regex_t re;
regmatch_t pmatch[1];
int match;
bool full_mapcpuid = is_full_cpuid(mapcpuid);
bool full_cpuid = is_full_cpuid(id);
/*
* Full CPUID format is required to identify a platform.
* Error out if the cpuid string is incomplete.
*/
if (full_mapcpuid && !full_cpuid) {
pr_info("Invalid CPUID %s. Full CPUID is required, "
"vendor-family-model-stepping\n", id);
return 1;
}
if (regcomp(&re, mapcpuid, REG_EXTENDED) != 0) {
/* Warn unable to generate match particular string. */
pr_info("Invalid regular expression %s\n", mapcpuid);
return 1;
}
match = !regexec(&re, id, 1, pmatch, 0);
regfree(&re);
if (match) {
size_t match_len = (pmatch[0].rm_eo - pmatch[0].rm_so);
size_t cpuid_len;
/* If the full CPUID format isn't required,
* ignoring the stepping.
*/
if (!full_mapcpuid && full_cpuid)
cpuid_len = strrchr(id, '-') - id;
else
cpuid_len = strlen(id);
/* Verify the entire string matched. */
if (match_len == cpuid_len)
return 0;
}
return 1;
}
| linux-master | tools/perf/arch/x86/util/header.c |
// SPDX-License-Identifier: GPL-2.0
#include <errno.h>
#include <string.h>
#include <regex.h>
#include <linux/kernel.h>
#include <linux/zalloc.h>
#include "perf_regs.h"
#include "../../../perf-sys.h"
#include "../../../util/perf_regs.h"
#include "../../../util/debug.h"
#include "../../../util/event.h"
#include "../../../util/pmu.h"
#include "../../../util/pmus.h"
const struct sample_reg sample_reg_masks[] = {
SMPL_REG(AX, PERF_REG_X86_AX),
SMPL_REG(BX, PERF_REG_X86_BX),
SMPL_REG(CX, PERF_REG_X86_CX),
SMPL_REG(DX, PERF_REG_X86_DX),
SMPL_REG(SI, PERF_REG_X86_SI),
SMPL_REG(DI, PERF_REG_X86_DI),
SMPL_REG(BP, PERF_REG_X86_BP),
SMPL_REG(SP, PERF_REG_X86_SP),
SMPL_REG(IP, PERF_REG_X86_IP),
SMPL_REG(FLAGS, PERF_REG_X86_FLAGS),
SMPL_REG(CS, PERF_REG_X86_CS),
SMPL_REG(SS, PERF_REG_X86_SS),
#ifdef HAVE_ARCH_X86_64_SUPPORT
SMPL_REG(R8, PERF_REG_X86_R8),
SMPL_REG(R9, PERF_REG_X86_R9),
SMPL_REG(R10, PERF_REG_X86_R10),
SMPL_REG(R11, PERF_REG_X86_R11),
SMPL_REG(R12, PERF_REG_X86_R12),
SMPL_REG(R13, PERF_REG_X86_R13),
SMPL_REG(R14, PERF_REG_X86_R14),
SMPL_REG(R15, PERF_REG_X86_R15),
#endif
SMPL_REG2(XMM0, PERF_REG_X86_XMM0),
SMPL_REG2(XMM1, PERF_REG_X86_XMM1),
SMPL_REG2(XMM2, PERF_REG_X86_XMM2),
SMPL_REG2(XMM3, PERF_REG_X86_XMM3),
SMPL_REG2(XMM4, PERF_REG_X86_XMM4),
SMPL_REG2(XMM5, PERF_REG_X86_XMM5),
SMPL_REG2(XMM6, PERF_REG_X86_XMM6),
SMPL_REG2(XMM7, PERF_REG_X86_XMM7),
SMPL_REG2(XMM8, PERF_REG_X86_XMM8),
SMPL_REG2(XMM9, PERF_REG_X86_XMM9),
SMPL_REG2(XMM10, PERF_REG_X86_XMM10),
SMPL_REG2(XMM11, PERF_REG_X86_XMM11),
SMPL_REG2(XMM12, PERF_REG_X86_XMM12),
SMPL_REG2(XMM13, PERF_REG_X86_XMM13),
SMPL_REG2(XMM14, PERF_REG_X86_XMM14),
SMPL_REG2(XMM15, PERF_REG_X86_XMM15),
SMPL_REG_END
};
struct sdt_name_reg {
const char *sdt_name;
const char *uprobe_name;
};
#define SDT_NAME_REG(n, m) {.sdt_name = "%" #n, .uprobe_name = "%" #m}
#define SDT_NAME_REG_END {.sdt_name = NULL, .uprobe_name = NULL}
static const struct sdt_name_reg sdt_reg_tbl[] = {
SDT_NAME_REG(eax, ax),
SDT_NAME_REG(rax, ax),
SDT_NAME_REG(al, ax),
SDT_NAME_REG(ah, ax),
SDT_NAME_REG(ebx, bx),
SDT_NAME_REG(rbx, bx),
SDT_NAME_REG(bl, bx),
SDT_NAME_REG(bh, bx),
SDT_NAME_REG(ecx, cx),
SDT_NAME_REG(rcx, cx),
SDT_NAME_REG(cl, cx),
SDT_NAME_REG(ch, cx),
SDT_NAME_REG(edx, dx),
SDT_NAME_REG(rdx, dx),
SDT_NAME_REG(dl, dx),
SDT_NAME_REG(dh, dx),
SDT_NAME_REG(esi, si),
SDT_NAME_REG(rsi, si),
SDT_NAME_REG(sil, si),
SDT_NAME_REG(edi, di),
SDT_NAME_REG(rdi, di),
SDT_NAME_REG(dil, di),
SDT_NAME_REG(ebp, bp),
SDT_NAME_REG(rbp, bp),
SDT_NAME_REG(bpl, bp),
SDT_NAME_REG(rsp, sp),
SDT_NAME_REG(esp, sp),
SDT_NAME_REG(spl, sp),
/* rNN registers */
SDT_NAME_REG(r8b, r8),
SDT_NAME_REG(r8w, r8),
SDT_NAME_REG(r8d, r8),
SDT_NAME_REG(r9b, r9),
SDT_NAME_REG(r9w, r9),
SDT_NAME_REG(r9d, r9),
SDT_NAME_REG(r10b, r10),
SDT_NAME_REG(r10w, r10),
SDT_NAME_REG(r10d, r10),
SDT_NAME_REG(r11b, r11),
SDT_NAME_REG(r11w, r11),
SDT_NAME_REG(r11d, r11),
SDT_NAME_REG(r12b, r12),
SDT_NAME_REG(r12w, r12),
SDT_NAME_REG(r12d, r12),
SDT_NAME_REG(r13b, r13),
SDT_NAME_REG(r13w, r13),
SDT_NAME_REG(r13d, r13),
SDT_NAME_REG(r14b, r14),
SDT_NAME_REG(r14w, r14),
SDT_NAME_REG(r14d, r14),
SDT_NAME_REG(r15b, r15),
SDT_NAME_REG(r15w, r15),
SDT_NAME_REG(r15d, r15),
SDT_NAME_REG_END,
};
/*
* Perf only supports OP which is in +/-NUM(REG) form.
* Here plus-minus sign, NUM and parenthesis are optional,
* only REG is mandatory.
*
* SDT events also supports indirect addressing mode with a
* symbol as offset, scaled mode and constants in OP. But
* perf does not support them yet. Below are few examples.
*
* OP with scaled mode:
* (%rax,%rsi,8)
* 10(%ras,%rsi,8)
*
* OP with indirect addressing mode:
* check_action(%rip)
* mp_+52(%rip)
* 44+mp_(%rip)
*
* OP with constant values:
* $0
* $123
* $-1
*/
#define SDT_OP_REGEX "^([+\\-]?)([0-9]*)(\\(?)(%[a-z][a-z0-9]+)(\\)?)$"
static regex_t sdt_op_regex;
static int sdt_init_op_regex(void)
{
static int initialized;
int ret = 0;
if (initialized)
return 0;
ret = regcomp(&sdt_op_regex, SDT_OP_REGEX, REG_EXTENDED);
if (ret < 0) {
pr_debug4("Regex compilation error.\n");
return ret;
}
initialized = 1;
return 0;
}
/*
* Max x86 register name length is 5(ex: %r15d). So, 6th char
* should always contain NULL. This helps to find register name
* length using strlen, instead of maintaining one more variable.
*/
#define SDT_REG_NAME_SIZE 6
/*
* The uprobe parser does not support all gas register names;
* so, we have to replace them (ex. for x86_64: %rax -> %ax).
* Note: If register does not require renaming, just copy
* paste as it is, but don't leave it empty.
*/
static void sdt_rename_register(char *sdt_reg, int sdt_len, char *uprobe_reg)
{
int i = 0;
for (i = 0; sdt_reg_tbl[i].sdt_name != NULL; i++) {
if (!strncmp(sdt_reg_tbl[i].sdt_name, sdt_reg, sdt_len)) {
strcpy(uprobe_reg, sdt_reg_tbl[i].uprobe_name);
return;
}
}
strncpy(uprobe_reg, sdt_reg, sdt_len);
}
int arch_sdt_arg_parse_op(char *old_op, char **new_op)
{
char new_reg[SDT_REG_NAME_SIZE] = {0};
int new_len = 0, ret;
/*
* rm[0]: +/-NUM(REG)
* rm[1]: +/-
* rm[2]: NUM
* rm[3]: (
* rm[4]: REG
* rm[5]: )
*/
regmatch_t rm[6];
/*
* Max prefix length is 2 as it may contains sign(+/-)
* and displacement 0 (Both sign and displacement 0 are
* optional so it may be empty). Use one more character
* to hold last NULL so that strlen can be used to find
* prefix length, instead of maintaining one more variable.
*/
char prefix[3] = {0};
ret = sdt_init_op_regex();
if (ret < 0)
return ret;
/*
* If unsupported OR does not match with regex OR
* register name too long, skip it.
*/
if (strchr(old_op, ',') || strchr(old_op, '$') ||
regexec(&sdt_op_regex, old_op, 6, rm, 0) ||
rm[4].rm_eo - rm[4].rm_so > SDT_REG_NAME_SIZE) {
pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);
return SDT_ARG_SKIP;
}
/*
* Prepare prefix.
* If SDT OP has parenthesis but does not provide
* displacement, add 0 for displacement.
* SDT Uprobe Prefix
* -----------------------------
* +24(%rdi) +24(%di) +
* 24(%rdi) +24(%di) +
* %rdi %di
* (%rdi) +0(%di) +0
* -80(%rbx) -80(%bx) -
*/
if (rm[3].rm_so != rm[3].rm_eo) {
if (rm[1].rm_so != rm[1].rm_eo)
prefix[0] = *(old_op + rm[1].rm_so);
else if (rm[2].rm_so != rm[2].rm_eo)
prefix[0] = '+';
else
scnprintf(prefix, sizeof(prefix), "+0");
}
/* Rename register */
sdt_rename_register(old_op + rm[4].rm_so, rm[4].rm_eo - rm[4].rm_so,
new_reg);
/* Prepare final OP which should be valid for uprobe_events */
new_len = strlen(prefix) +
(rm[2].rm_eo - rm[2].rm_so) +
(rm[3].rm_eo - rm[3].rm_so) +
strlen(new_reg) +
(rm[5].rm_eo - rm[5].rm_so) +
1; /* NULL */
*new_op = zalloc(new_len);
if (!*new_op)
return -ENOMEM;
scnprintf(*new_op, new_len, "%.*s%.*s%.*s%.*s%.*s",
strlen(prefix), prefix,
(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so,
(int)(rm[3].rm_eo - rm[3].rm_so), old_op + rm[3].rm_so,
strlen(new_reg), new_reg,
(int)(rm[5].rm_eo - rm[5].rm_so), old_op + rm[5].rm_so);
return SDT_ARG_VALID;
}
uint64_t arch__intr_reg_mask(void)
{
struct perf_event_attr attr = {
.type = PERF_TYPE_HARDWARE,
.config = PERF_COUNT_HW_CPU_CYCLES,
.sample_type = PERF_SAMPLE_REGS_INTR,
.sample_regs_intr = PERF_REG_EXTENDED_MASK,
.precise_ip = 1,
.disabled = 1,
.exclude_kernel = 1,
};
int fd;
/*
* In an unnamed union, init it here to build on older gcc versions
*/
attr.sample_period = 1;
if (perf_pmus__num_core_pmus() > 1) {
struct perf_pmu *pmu = NULL;
__u64 type = PERF_TYPE_RAW;
/*
* The same register set is supported among different hybrid PMUs.
* Only check the first available one.
*/
while ((pmu = perf_pmus__scan_core(pmu)) != NULL) {
type = pmu->type;
break;
}
attr.config |= type << PERF_PMU_TYPE_SHIFT;
}
event_attr_init(&attr);
fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
if (fd != -1) {
close(fd);
return (PERF_REG_EXTENDED_MASK | PERF_REGS_MASK);
}
return PERF_REGS_MASK;
}
uint64_t arch__user_reg_mask(void)
{
return PERF_REGS_MASK;
}
| linux-master | tools/perf/arch/x86/util/perf_regs.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include "../../../util/debug.h"
#include "../../../util/tsc.h"
#include "cpuid.h"
u64 rdtsc(void)
{
unsigned int low, high;
asm volatile("rdtsc" : "=a" (low), "=d" (high));
return low | ((u64)high) << 32;
}
/*
* Derive the TSC frequency in Hz from the /proc/cpuinfo, for example:
* ...
* model name : Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz
* ...
* will return 3000000000.
*/
static double cpuinfo_tsc_freq(void)
{
double result = 0;
FILE *cpuinfo;
char *line = NULL;
size_t len = 0;
cpuinfo = fopen("/proc/cpuinfo", "r");
if (!cpuinfo) {
pr_err("Failed to read /proc/cpuinfo for TSC frequency");
return NAN;
}
while (getline(&line, &len, cpuinfo) > 0) {
if (!strncmp(line, "model name", 10)) {
char *pos = strstr(line + 11, " @ ");
if (pos && sscanf(pos, " @ %lfGHz", &result) == 1) {
result *= 1000000000;
goto out;
}
}
}
out:
if (fpclassify(result) == FP_ZERO)
pr_err("Failed to find TSC frequency in /proc/cpuinfo");
free(line);
fclose(cpuinfo);
return result;
}
double arch_get_tsc_freq(void)
{
unsigned int a, b, c, d, lvl;
static bool cached;
static double tsc;
char vendor[16];
if (cached)
return tsc;
cached = true;
get_cpuid_0(vendor, &lvl);
if (!strstr(vendor, "Intel"))
return 0;
/*
* Don't support Time Stamp Counter and
* Nominal Core Crystal Clock Information Leaf.
*/
if (lvl < 0x15) {
tsc = cpuinfo_tsc_freq();
return tsc;
}
cpuid(0x15, 0, &a, &b, &c, &d);
/* TSC frequency is not enumerated */
if (!a || !b || !c) {
tsc = cpuinfo_tsc_freq();
return tsc;
}
tsc = (double)c * (double)b / (double)a;
return tsc;
}
| linux-master | tools/perf/arch/x86/util/tsc.c |
// SPDX-License-Identifier: GPL-2.0
#include <stdio.h>
#include "util/pmu.h"
#include "util/pmus.h"
#include "util/evlist.h"
#include "util/parse-events.h"
#include "util/event.h"
#include "topdown.h"
#include "evsel.h"
static int ___evlist__add_default_attrs(struct evlist *evlist,
struct perf_event_attr *attrs,
size_t nr_attrs)
{
LIST_HEAD(head);
size_t i = 0;
for (i = 0; i < nr_attrs; i++)
event_attr_init(attrs + i);
if (perf_pmus__num_core_pmus() == 1)
return evlist__add_attrs(evlist, attrs, nr_attrs);
for (i = 0; i < nr_attrs; i++) {
struct perf_pmu *pmu = NULL;
if (attrs[i].type == PERF_TYPE_SOFTWARE) {
struct evsel *evsel = evsel__new(attrs + i);
if (evsel == NULL)
goto out_delete_partial_list;
list_add_tail(&evsel->core.node, &head);
continue;
}
while ((pmu = perf_pmus__scan_core(pmu)) != NULL) {
struct perf_cpu_map *cpus;
struct evsel *evsel;
evsel = evsel__new(attrs + i);
if (evsel == NULL)
goto out_delete_partial_list;
evsel->core.attr.config |= (__u64)pmu->type << PERF_PMU_TYPE_SHIFT;
cpus = perf_cpu_map__get(pmu->cpus);
evsel->core.cpus = cpus;
evsel->core.own_cpus = perf_cpu_map__get(cpus);
evsel->pmu_name = strdup(pmu->name);
list_add_tail(&evsel->core.node, &head);
}
}
evlist__splice_list_tail(evlist, &head);
return 0;
out_delete_partial_list:
{
struct evsel *evsel, *n;
__evlist__for_each_entry_safe(&head, n, evsel)
evsel__delete(evsel);
}
return -1;
}
int arch_evlist__add_default_attrs(struct evlist *evlist,
struct perf_event_attr *attrs,
size_t nr_attrs)
{
if (!nr_attrs)
return 0;
return ___evlist__add_default_attrs(evlist, attrs, nr_attrs);
}
int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs)
{
if (topdown_sys_has_perf_metrics() &&
(arch_evsel__must_be_in_group(lhs) || arch_evsel__must_be_in_group(rhs))) {
/* Ensure the topdown slots comes first. */
if (strcasestr(lhs->name, "slots") && !strcasestr(lhs->name, "uops_retired.slots"))
return -1;
if (strcasestr(rhs->name, "slots") && !strcasestr(rhs->name, "uops_retired.slots"))
return 1;
/* Followed by topdown events. */
if (strcasestr(lhs->name, "topdown") && !strcasestr(rhs->name, "topdown"))
return -1;
if (!strcasestr(lhs->name, "topdown") && strcasestr(rhs->name, "topdown"))
return 1;
}
/* Default ordering by insertion index. */
return lhs->core.idx - rhs->core.idx;
}
| linux-master | tools/perf/arch/x86/util/evlist.c |
// SPDX-License-Identifier: GPL-2.0
#include <stdio.h>
#include <stdlib.h>
#include "util/evsel.h"
#include "util/env.h"
#include "util/pmu.h"
#include "util/pmus.h"
#include "linux/string.h"
#include "evsel.h"
#include "util/debug.h"
#include "env.h"
#define IBS_FETCH_L3MISSONLY (1ULL << 59)
#define IBS_OP_L3MISSONLY (1ULL << 16)
void arch_evsel__set_sample_weight(struct evsel *evsel)
{
evsel__set_sample_bit(evsel, WEIGHT_STRUCT);
}
/* Check whether the evsel's PMU supports the perf metrics */
bool evsel__sys_has_perf_metrics(const struct evsel *evsel)
{
const char *pmu_name = evsel->pmu_name ? evsel->pmu_name : "cpu";
/*
* The PERF_TYPE_RAW type is the core PMU type, e.g., "cpu" PMU
* on a non-hybrid machine, "cpu_core" PMU on a hybrid machine.
* The slots event is only available for the core PMU, which
* supports the perf metrics feature.
* Checking both the PERF_TYPE_RAW type and the slots event
* should be good enough to detect the perf metrics feature.
*/
if ((evsel->core.attr.type == PERF_TYPE_RAW) &&
perf_pmus__have_event(pmu_name, "slots"))
return true;
return false;
}
bool arch_evsel__must_be_in_group(const struct evsel *evsel)
{
if (!evsel__sys_has_perf_metrics(evsel) || !evsel->name ||
strcasestr(evsel->name, "uops_retired.slots"))
return false;
return strcasestr(evsel->name, "topdown") || strcasestr(evsel->name, "slots");
}
int arch_evsel__hw_name(struct evsel *evsel, char *bf, size_t size)
{
u64 event = evsel->core.attr.config & PERF_HW_EVENT_MASK;
u64 pmu = evsel->core.attr.config >> PERF_PMU_TYPE_SHIFT;
const char *event_name;
if (event < PERF_COUNT_HW_MAX && evsel__hw_names[event])
event_name = evsel__hw_names[event];
else
event_name = "unknown-hardware";
/* The PMU type is not required for the non-hybrid platform. */
if (!pmu)
return scnprintf(bf, size, "%s", event_name);
return scnprintf(bf, size, "%s/%s/",
evsel->pmu_name ? evsel->pmu_name : "cpu",
event_name);
}
static void ibs_l3miss_warn(void)
{
pr_warning(
"WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled\n"
"and tagged operation does not cause L3 Miss. This causes sampling period skew.\n");
}
void arch__post_evsel_config(struct evsel *evsel, struct perf_event_attr *attr)
{
struct perf_pmu *evsel_pmu, *ibs_fetch_pmu, *ibs_op_pmu;
static int warned_once;
if (warned_once || !x86__is_amd_cpu())
return;
evsel_pmu = evsel__find_pmu(evsel);
if (!evsel_pmu)
return;
ibs_fetch_pmu = perf_pmus__find("ibs_fetch");
ibs_op_pmu = perf_pmus__find("ibs_op");
if (ibs_fetch_pmu && ibs_fetch_pmu->type == evsel_pmu->type) {
if (attr->config & IBS_FETCH_L3MISSONLY) {
ibs_l3miss_warn();
warned_once = 1;
}
} else if (ibs_op_pmu && ibs_op_pmu->type == evsel_pmu->type) {
if (attr->config & IBS_OP_L3MISSONLY) {
ibs_l3miss_warn();
warned_once = 1;
}
}
}
int arch_evsel__open_strerror(struct evsel *evsel, char *msg, size_t size)
{
if (!x86__is_amd_cpu())
return 0;
if (!evsel->core.attr.precise_ip &&
!(evsel->pmu_name && !strncmp(evsel->pmu_name, "ibs", 3)))
return 0;
/* More verbose IBS errors. */
if (evsel->core.attr.exclude_kernel || evsel->core.attr.exclude_user ||
evsel->core.attr.exclude_hv || evsel->core.attr.exclude_idle ||
evsel->core.attr.exclude_host || evsel->core.attr.exclude_guest) {
return scnprintf(msg, size, "AMD IBS doesn't support privilege filtering. Try "
"again without the privilege modifiers (like 'k') at the end.");
}
return 0;
}
| linux-master | tools/perf/arch/x86/util/evsel.c |
// SPDX-License-Identifier: GPL-2.0
#include "tests/tests.h"
#include "cloexec.h"
#include "debug.h"
#include "evlist.h"
#include "evsel.h"
#include "arch-tests.h"
#include <internal/lib.h> // page_size
#include <signal.h>
#include <sys/mman.h>
#include <sys/wait.h>
#include <errno.h>
#include <string.h>
static pid_t spawn(void)
{
pid_t pid;
pid = fork();
if (pid)
return pid;
while(1)
sleep(5);
return 0;
}
/*
* Create an event group that contains both a sampled hardware
* (cpu-cycles) and software (intel_cqm/llc_occupancy/) event. We then
* wait for the hardware perf counter to overflow and generate a PMI,
* which triggers an event read for both of the events in the group.
*
* Since reading Intel CQM event counters requires sending SMP IPIs, the
* CQM pmu needs to handle the above situation gracefully, and return
* the last read counter value to avoid triggering a WARN_ON_ONCE() in
* smp_call_function_many() caused by sending IPIs from NMI context.
*/
int test__intel_cqm_count_nmi_context(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
struct evlist *evlist = NULL;
struct evsel *evsel = NULL;
struct perf_event_attr pe;
int i, fd[2], flag, ret;
size_t mmap_len;
void *event;
pid_t pid;
int err = TEST_FAIL;
flag = perf_event_open_cloexec_flag();
evlist = evlist__new();
if (!evlist) {
pr_debug("evlist__new failed\n");
return TEST_FAIL;
}
ret = parse_event(evlist, "intel_cqm/llc_occupancy/");
if (ret) {
pr_debug("parse_events failed, is \"intel_cqm/llc_occupancy/\" available?\n");
err = TEST_SKIP;
goto out;
}
evsel = evlist__first(evlist);
if (!evsel) {
pr_debug("evlist__first failed\n");
goto out;
}
memset(&pe, 0, sizeof(pe));
pe.size = sizeof(pe);
pe.type = PERF_TYPE_HARDWARE;
pe.config = PERF_COUNT_HW_CPU_CYCLES;
pe.read_format = PERF_FORMAT_GROUP;
pe.sample_period = 128;
pe.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_READ;
pid = spawn();
fd[0] = sys_perf_event_open(&pe, pid, -1, -1, flag);
if (fd[0] < 0) {
pr_debug("failed to open event\n");
goto out;
}
memset(&pe, 0, sizeof(pe));
pe.size = sizeof(pe);
pe.type = evsel->attr.type;
pe.config = evsel->attr.config;
fd[1] = sys_perf_event_open(&pe, pid, -1, fd[0], flag);
if (fd[1] < 0) {
pr_debug("failed to open event\n");
goto out;
}
/*
* Pick a power-of-two number of pages + 1 for the meta-data
* page (struct perf_event_mmap_page). See tools/perf/design.txt.
*/
mmap_len = page_size * 65;
event = mmap(NULL, mmap_len, PROT_READ, MAP_SHARED, fd[0], 0);
if (event == (void *)(-1)) {
pr_debug("failed to mmap %d\n", errno);
goto out;
}
sleep(1);
err = TEST_OK;
munmap(event, mmap_len);
for (i = 0; i < 2; i++)
close(fd[i]);
kill(pid, SIGKILL);
wait(NULL);
out:
evlist__delete(evlist);
return err;
}
| linux-master | tools/perf/arch/x86/tests/intel-cqm.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <stdbool.h>
#include <inttypes.h>
#include <stdlib.h>
#include <string.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "event.h"
#include "evsel.h"
#include "debug.h"
#include "util/sample.h"
#include "util/synthetic-events.h"
#include "tests/tests.h"
#include "arch-tests.h"
#define COMP(m) do { \
if (s1->m != s2->m) { \
pr_debug("Samples differ at '"#m"'\n"); \
return false; \
} \
} while (0)
static bool samples_same(const struct perf_sample *s1,
const struct perf_sample *s2,
u64 type)
{
if (type & PERF_SAMPLE_WEIGHT_STRUCT) {
COMP(ins_lat);
COMP(retire_lat);
}
return true;
}
static int do_test(u64 sample_type)
{
struct evsel evsel = {
.needs_swap = false,
.core = {
. attr = {
.sample_type = sample_type,
.read_format = 0,
},
},
};
union perf_event *event;
struct perf_sample sample = {
.weight = 101,
.ins_lat = 102,
.retire_lat = 103,
};
struct perf_sample sample_out;
size_t i, sz, bufsz;
int err, ret = -1;
sz = perf_event__sample_event_size(&sample, sample_type, 0);
bufsz = sz + 4096; /* Add a bit for overrun checking */
event = malloc(bufsz);
if (!event) {
pr_debug("malloc failed\n");
return -1;
}
memset(event, 0xff, bufsz);
event->header.type = PERF_RECORD_SAMPLE;
event->header.misc = 0;
event->header.size = sz;
err = perf_event__synthesize_sample(event, sample_type, 0, &sample);
if (err) {
pr_debug("%s failed for sample_type %#"PRIx64", error %d\n",
"perf_event__synthesize_sample", sample_type, err);
goto out_free;
}
/* The data does not contain 0xff so we use that to check the size */
for (i = bufsz; i > 0; i--) {
if (*(i - 1 + (u8 *)event) != 0xff)
break;
}
if (i != sz) {
pr_debug("Event size mismatch: actual %zu vs expected %zu\n",
i, sz);
goto out_free;
}
evsel.sample_size = __evsel__sample_size(sample_type);
err = evsel__parse_sample(&evsel, event, &sample_out);
if (err) {
pr_debug("%s failed for sample_type %#"PRIx64", error %d\n",
"evsel__parse_sample", sample_type, err);
goto out_free;
}
if (!samples_same(&sample, &sample_out, sample_type)) {
pr_debug("parsing failed for sample_type %#"PRIx64"\n",
sample_type);
goto out_free;
}
ret = 0;
out_free:
free(event);
return ret;
}
/**
* test__x86_sample_parsing - test X86 specific sample parsing
*
* This function implements a test that synthesizes a sample event, parses it
* and then checks that the parsed sample matches the original sample. If the
* test passes %0 is returned, otherwise %-1 is returned.
*
* For now, the PERF_SAMPLE_WEIGHT_STRUCT is the only X86 specific sample type.
* The test only checks the PERF_SAMPLE_WEIGHT_STRUCT type.
*/
int test__x86_sample_parsing(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
return do_test(PERF_SAMPLE_WEIGHT_STRUCT);
}
| linux-master | tools/perf/arch/x86/tests/sample-parsing.c |
// SPDX-License-Identifier: GPL-2.0
/*
* This file contains instructions for testing by the test titled:
*
* "Test x86 instruction decoder - new instructions"
*
* Note that the 'Expecting' comment lines are consumed by the
* gen-insn-x86-dat.awk script and have the format:
*
* Expecting: <op> <branch> <rel>
*
* If this file is changed, remember to run the gen-insn-x86-dat.sh
* script and commit the result.
*
* Refer to insn-x86.c for more details.
*/
int main(void)
{
/* Following line is a marker for the awk script - do not change */
asm volatile("rdtsc"); /* Start here */
/* Test fix for vcvtph2ps in x86-opcode-map.txt */
asm volatile("vcvtph2ps %xmm3,%ymm5");
#ifdef __x86_64__
/* AVX-512: Instructions with the same op codes as Mask Instructions */
asm volatile("cmovno %rax,%rbx");
asm volatile("cmovno 0x12345678(%rax),%rcx");
asm volatile("cmovno 0x12345678(%rax),%cx");
asm volatile("cmove %rax,%rbx");
asm volatile("cmove 0x12345678(%rax),%rcx");
asm volatile("cmove 0x12345678(%rax),%cx");
asm volatile("seto 0x12345678(%rax)");
asm volatile("setno 0x12345678(%rax)");
asm volatile("setb 0x12345678(%rax)");
asm volatile("setc 0x12345678(%rax)");
asm volatile("setnae 0x12345678(%rax)");
asm volatile("setae 0x12345678(%rax)");
asm volatile("setnb 0x12345678(%rax)");
asm volatile("setnc 0x12345678(%rax)");
asm volatile("sets 0x12345678(%rax)");
asm volatile("setns 0x12345678(%rax)");
/* AVX-512: Mask Instructions */
asm volatile("kandw %k7,%k6,%k5");
asm volatile("kandq %k7,%k6,%k5");
asm volatile("kandb %k7,%k6,%k5");
asm volatile("kandd %k7,%k6,%k5");
asm volatile("kandnw %k7,%k6,%k5");
asm volatile("kandnq %k7,%k6,%k5");
asm volatile("kandnb %k7,%k6,%k5");
asm volatile("kandnd %k7,%k6,%k5");
asm volatile("knotw %k7,%k6");
asm volatile("knotq %k7,%k6");
asm volatile("knotb %k7,%k6");
asm volatile("knotd %k7,%k6");
asm volatile("korw %k7,%k6,%k5");
asm volatile("korq %k7,%k6,%k5");
asm volatile("korb %k7,%k6,%k5");
asm volatile("kord %k7,%k6,%k5");
asm volatile("kxnorw %k7,%k6,%k5");
asm volatile("kxnorq %k7,%k6,%k5");
asm volatile("kxnorb %k7,%k6,%k5");
asm volatile("kxnord %k7,%k6,%k5");
asm volatile("kxorw %k7,%k6,%k5");
asm volatile("kxorq %k7,%k6,%k5");
asm volatile("kxorb %k7,%k6,%k5");
asm volatile("kxord %k7,%k6,%k5");
asm volatile("kaddw %k7,%k6,%k5");
asm volatile("kaddq %k7,%k6,%k5");
asm volatile("kaddb %k7,%k6,%k5");
asm volatile("kaddd %k7,%k6,%k5");
asm volatile("kunpckbw %k7,%k6,%k5");
asm volatile("kunpckwd %k7,%k6,%k5");
asm volatile("kunpckdq %k7,%k6,%k5");
asm volatile("kmovw %k6,%k5");
asm volatile("kmovw (%rcx),%k5");
asm volatile("kmovw 0x123(%rax,%r14,8),%k5");
asm volatile("kmovw %k5,(%rcx)");
asm volatile("kmovw %k5,0x123(%rax,%r14,8)");
asm volatile("kmovw %eax,%k5");
asm volatile("kmovw %ebp,%k5");
asm volatile("kmovw %r13d,%k5");
asm volatile("kmovw %k5,%eax");
asm volatile("kmovw %k5,%ebp");
asm volatile("kmovw %k5,%r13d");
asm volatile("kmovq %k6,%k5");
asm volatile("kmovq (%rcx),%k5");
asm volatile("kmovq 0x123(%rax,%r14,8),%k5");
asm volatile("kmovq %k5,(%rcx)");
asm volatile("kmovq %k5,0x123(%rax,%r14,8)");
asm volatile("kmovq %rax,%k5");
asm volatile("kmovq %rbp,%k5");
asm volatile("kmovq %r13,%k5");
asm volatile("kmovq %k5,%rax");
asm volatile("kmovq %k5,%rbp");
asm volatile("kmovq %k5,%r13");
asm volatile("kmovb %k6,%k5");
asm volatile("kmovb (%rcx),%k5");
asm volatile("kmovb 0x123(%rax,%r14,8),%k5");
asm volatile("kmovb %k5,(%rcx)");
asm volatile("kmovb %k5,0x123(%rax,%r14,8)");
asm volatile("kmovb %eax,%k5");
asm volatile("kmovb %ebp,%k5");
asm volatile("kmovb %r13d,%k5");
asm volatile("kmovb %k5,%eax");
asm volatile("kmovb %k5,%ebp");
asm volatile("kmovb %k5,%r13d");
asm volatile("kmovd %k6,%k5");
asm volatile("kmovd (%rcx),%k5");
asm volatile("kmovd 0x123(%rax,%r14,8),%k5");
asm volatile("kmovd %k5,(%rcx)");
asm volatile("kmovd %k5,0x123(%rax,%r14,8)");
asm volatile("kmovd %eax,%k5");
asm volatile("kmovd %ebp,%k5");
asm volatile("kmovd %r13d,%k5");
asm volatile("kmovd %k5,%eax");
asm volatile("kmovd %k5,%ebp");
asm volatile("kmovd %k5,%r13d");
asm volatile("kortestw %k6,%k5");
asm volatile("kortestq %k6,%k5");
asm volatile("kortestb %k6,%k5");
asm volatile("kortestd %k6,%k5");
asm volatile("ktestw %k6,%k5");
asm volatile("ktestq %k6,%k5");
asm volatile("ktestb %k6,%k5");
asm volatile("ktestd %k6,%k5");
asm volatile("kshiftrw $0x12,%k6,%k5");
asm volatile("kshiftrq $0x5b,%k6,%k5");
asm volatile("kshiftlw $0x12,%k6,%k5");
asm volatile("kshiftlq $0x5b,%k6,%k5");
/* AVX-512: Op code 0f 5b */
asm volatile("vcvtdq2ps %xmm5,%xmm6");
asm volatile("vcvtqq2ps %zmm29,%ymm6{%k7}");
asm volatile("vcvtps2dq %xmm5,%xmm6");
asm volatile("vcvttps2dq %xmm5,%xmm6");
/* AVX-512: Op code 0f 6f */
asm volatile("movq %mm0,%mm4");
asm volatile("vmovdqa %ymm4,%ymm6");
asm volatile("vmovdqa32 %zmm25,%zmm26");
asm volatile("vmovdqa64 %zmm25,%zmm26");
asm volatile("vmovdqu %ymm4,%ymm6");
asm volatile("vmovdqu32 %zmm29,%zmm30");
asm volatile("vmovdqu64 %zmm25,%zmm26");
asm volatile("vmovdqu8 %zmm29,%zmm30");
asm volatile("vmovdqu16 %zmm25,%zmm26");
/* AVX-512: Op code 0f 78 */
asm volatile("vmread %rax,%rbx");
asm volatile("vcvttps2udq %zmm25,%zmm26");
asm volatile("vcvttpd2udq %zmm29,%ymm6{%k7}");
asm volatile("vcvttsd2usi %xmm6,%rax");
asm volatile("vcvttss2usi %xmm6,%rax");
asm volatile("vcvttps2uqq %ymm5,%zmm26{%k7}");
asm volatile("vcvttpd2uqq %zmm29,%zmm30");
/* AVX-512: Op code 0f 79 */
asm volatile("vmwrite %rax,%rbx");
asm volatile("vcvtps2udq %zmm25,%zmm26");
asm volatile("vcvtpd2udq %zmm29,%ymm6{%k7}");
asm volatile("vcvtsd2usi %xmm6,%rax");
asm volatile("vcvtss2usi %xmm6,%rax");
asm volatile("vcvtps2uqq %ymm5,%zmm26{%k7}");
asm volatile("vcvtpd2uqq %zmm29,%zmm30");
/* AVX-512: Op code 0f 7a */
asm volatile("vcvtudq2pd %ymm5,%zmm29{%k7}");
asm volatile("vcvtuqq2pd %zmm25,%zmm26");
asm volatile("vcvtudq2ps %zmm29,%zmm30");
asm volatile("vcvtuqq2ps %zmm25,%ymm26{%k7}");
asm volatile("vcvttps2qq %ymm25,%zmm26{%k7}");
asm volatile("vcvttpd2qq %zmm29,%zmm30");
/* AVX-512: Op code 0f 7b */
asm volatile("vcvtusi2sd %eax,%xmm5,%xmm6");
asm volatile("vcvtusi2ss %eax,%xmm5,%xmm6");
asm volatile("vcvtps2qq %ymm5,%zmm26{%k7}");
asm volatile("vcvtpd2qq %zmm29,%zmm30");
/* AVX-512: Op code 0f 7f */
asm volatile("movq.s %mm0,%mm4");
asm volatile("vmovdqa %ymm8,%ymm6");
asm volatile("vmovdqa32.s %zmm25,%zmm26");
asm volatile("vmovdqa64.s %zmm25,%zmm26");
asm volatile("vmovdqu %ymm8,%ymm6");
asm volatile("vmovdqu32.s %zmm25,%zmm26");
asm volatile("vmovdqu64.s %zmm25,%zmm26");
asm volatile("vmovdqu8.s %zmm30,(%rcx)");
asm volatile("vmovdqu16.s %zmm25,%zmm26");
/* AVX-512: Op code 0f db */
asm volatile("pand %mm1,%mm2");
asm volatile("pand %xmm1,%xmm2");
asm volatile("vpand %ymm4,%ymm6,%ymm2");
asm volatile("vpandd %zmm24,%zmm25,%zmm26");
asm volatile("vpandq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f df */
asm volatile("pandn %mm1,%mm2");
asm volatile("pandn %xmm1,%xmm2");
asm volatile("vpandn %ymm4,%ymm6,%ymm2");
asm volatile("vpandnd %zmm24,%zmm25,%zmm26");
asm volatile("vpandnq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f e6 */
asm volatile("vcvttpd2dq %xmm1,%xmm2");
asm volatile("vcvtdq2pd %xmm5,%xmm6");
asm volatile("vcvtdq2pd %ymm5,%zmm26{%k7}");
asm volatile("vcvtqq2pd %zmm25,%zmm26");
asm volatile("vcvtpd2dq %xmm1,%xmm2");
/* AVX-512: Op code 0f eb */
asm volatile("por %mm4,%mm6");
asm volatile("vpor %ymm4,%ymm6,%ymm2");
asm volatile("vpord %zmm24,%zmm25,%zmm26");
asm volatile("vporq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f ef */
asm volatile("pxor %mm4,%mm6");
asm volatile("vpxor %ymm4,%ymm6,%ymm2");
asm volatile("vpxord %zmm24,%zmm25,%zmm26");
asm volatile("vpxorq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 10 */
asm volatile("pblendvb %xmm1,%xmm0");
asm volatile("vpsrlvw %zmm27,%zmm28,%zmm29");
asm volatile("vpmovuswb %zmm28,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 11 */
asm volatile("vpmovusdb %zmm28,%xmm6{%k7}");
asm volatile("vpsravw %zmm27,%zmm28,%zmm29");
/* AVX-512: Op code 0f 38 12 */
asm volatile("vpmovusqb %zmm27,%xmm6{%k7}");
asm volatile("vpsllvw %zmm27,%zmm28,%zmm29");
/* AVX-512: Op code 0f 38 13 */
asm volatile("vcvtph2ps %xmm3,%ymm5");
asm volatile("vcvtph2ps %ymm5,%zmm27{%k7}");
asm volatile("vpmovusdw %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 14 */
asm volatile("blendvps %xmm1,%xmm0");
asm volatile("vpmovusqw %zmm27,%xmm6{%k7}");
asm volatile("vprorvd %zmm27,%zmm28,%zmm29");
asm volatile("vprorvq %zmm27,%zmm28,%zmm29");
/* AVX-512: Op code 0f 38 15 */
asm volatile("blendvpd %xmm1,%xmm0");
asm volatile("vpmovusqd %zmm27,%ymm6{%k7}");
asm volatile("vprolvd %zmm27,%zmm28,%zmm29");
asm volatile("vprolvq %zmm27,%zmm28,%zmm29");
/* AVX-512: Op code 0f 38 16 */
asm volatile("vpermps %ymm4,%ymm6,%ymm2");
asm volatile("vpermps %ymm24,%ymm26,%ymm22{%k7}");
asm volatile("vpermpd %ymm24,%ymm26,%ymm22{%k7}");
/* AVX-512: Op code 0f 38 19 */
asm volatile("vbroadcastsd %xmm4,%ymm6");
asm volatile("vbroadcastf32x2 %xmm27,%zmm26");
/* AVX-512: Op code 0f 38 1a */
asm volatile("vbroadcastf128 (%rcx),%ymm4");
asm volatile("vbroadcastf32x4 (%rcx),%zmm26");
asm volatile("vbroadcastf64x2 (%rcx),%zmm26");
/* AVX-512: Op code 0f 38 1b */
asm volatile("vbroadcastf32x8 (%rcx),%zmm27");
asm volatile("vbroadcastf64x4 (%rcx),%zmm26");
/* AVX-512: Op code 0f 38 1f */
asm volatile("vpabsq %zmm27,%zmm28");
/* AVX-512: Op code 0f 38 20 */
asm volatile("vpmovsxbw %xmm4,%xmm5");
asm volatile("vpmovswb %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 21 */
asm volatile("vpmovsxbd %xmm4,%ymm6");
asm volatile("vpmovsdb %zmm27,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 22 */
asm volatile("vpmovsxbq %xmm4,%ymm4");
asm volatile("vpmovsqb %zmm27,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 23 */
asm volatile("vpmovsxwd %xmm4,%ymm4");
asm volatile("vpmovsdw %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 24 */
asm volatile("vpmovsxwq %xmm4,%ymm6");
asm volatile("vpmovsqw %zmm27,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 25 */
asm volatile("vpmovsxdq %xmm4,%ymm4");
asm volatile("vpmovsqd %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 26 */
asm volatile("vptestmb %zmm27,%zmm28,%k5");
asm volatile("vptestmw %zmm27,%zmm28,%k5");
asm volatile("vptestnmb %zmm26,%zmm27,%k5");
asm volatile("vptestnmw %zmm26,%zmm27,%k5");
/* AVX-512: Op code 0f 38 27 */
asm volatile("vptestmd %zmm27,%zmm28,%k5");
asm volatile("vptestmq %zmm27,%zmm28,%k5");
asm volatile("vptestnmd %zmm26,%zmm27,%k5");
asm volatile("vptestnmq %zmm26,%zmm27,%k5");
/* AVX-512: Op code 0f 38 28 */
asm volatile("vpmuldq %ymm4,%ymm6,%ymm2");
asm volatile("vpmovm2b %k5,%zmm28");
asm volatile("vpmovm2w %k5,%zmm28");
/* AVX-512: Op code 0f 38 29 */
asm volatile("vpcmpeqq %ymm4,%ymm6,%ymm2");
asm volatile("vpmovb2m %zmm28,%k5");
asm volatile("vpmovw2m %zmm28,%k5");
/* AVX-512: Op code 0f 38 2a */
asm volatile("vmovntdqa (%rcx),%ymm4");
asm volatile("vpbroadcastmb2q %k6,%zmm30");
/* AVX-512: Op code 0f 38 2c */
asm volatile("vmaskmovps (%rcx),%ymm4,%ymm6");
asm volatile("vscalefps %zmm24,%zmm25,%zmm26");
asm volatile("vscalefpd %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 2d */
asm volatile("vmaskmovpd (%rcx),%ymm4,%ymm6");
asm volatile("vscalefss %xmm24,%xmm25,%xmm26{%k7}");
asm volatile("vscalefsd %xmm24,%xmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 38 30 */
asm volatile("vpmovzxbw %xmm4,%ymm4");
asm volatile("vpmovwb %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 31 */
asm volatile("vpmovzxbd %xmm4,%ymm6");
asm volatile("vpmovdb %zmm27,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 32 */
asm volatile("vpmovzxbq %xmm4,%ymm4");
asm volatile("vpmovqb %zmm27,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 33 */
asm volatile("vpmovzxwd %xmm4,%ymm4");
asm volatile("vpmovdw %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 34 */
asm volatile("vpmovzxwq %xmm4,%ymm6");
asm volatile("vpmovqw %zmm27,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 35 */
asm volatile("vpmovzxdq %xmm4,%ymm4");
asm volatile("vpmovqd %zmm27,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 38 */
asm volatile("vpermd %ymm4,%ymm6,%ymm2");
asm volatile("vpermd %ymm24,%ymm26,%ymm22{%k7}");
asm volatile("vpermq %ymm24,%ymm26,%ymm22{%k7}");
/* AVX-512: Op code 0f 38 38 */
asm volatile("vpminsb %ymm4,%ymm6,%ymm2");
asm volatile("vpmovm2d %k5,%zmm28");
asm volatile("vpmovm2q %k5,%zmm28");
/* AVX-512: Op code 0f 38 39 */
asm volatile("vpminsd %xmm1,%xmm2,%xmm3");
asm volatile("vpminsd %zmm24,%zmm25,%zmm26");
asm volatile("vpminsq %zmm24,%zmm25,%zmm26");
asm volatile("vpmovd2m %zmm28,%k5");
asm volatile("vpmovq2m %zmm28,%k5");
/* AVX-512: Op code 0f 38 3a */
asm volatile("vpminuw %ymm4,%ymm6,%ymm2");
asm volatile("vpbroadcastmw2d %k6,%zmm28");
/* AVX-512: Op code 0f 38 3b */
asm volatile("vpminud %ymm4,%ymm6,%ymm2");
asm volatile("vpminud %zmm24,%zmm25,%zmm26");
asm volatile("vpminuq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 3d */
asm volatile("vpmaxsd %ymm4,%ymm6,%ymm2");
asm volatile("vpmaxsd %zmm24,%zmm25,%zmm26");
asm volatile("vpmaxsq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 3f */
asm volatile("vpmaxud %ymm4,%ymm6,%ymm2");
asm volatile("vpmaxud %zmm24,%zmm25,%zmm26");
asm volatile("vpmaxuq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 42 */
asm volatile("vpmulld %ymm4,%ymm6,%ymm2");
asm volatile("vpmulld %zmm24,%zmm25,%zmm26");
asm volatile("vpmullq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 42 */
asm volatile("vgetexpps %zmm25,%zmm26");
asm volatile("vgetexppd %zmm27,%zmm28");
/* AVX-512: Op code 0f 38 43 */
asm volatile("vgetexpss %xmm24,%xmm25,%xmm26{%k7}");
asm volatile("vgetexpsd %xmm28,%xmm29,%xmm30{%k7}");
/* AVX-512: Op code 0f 38 44 */
asm volatile("vplzcntd %zmm27,%zmm28");
asm volatile("vplzcntq %zmm27,%zmm28");
/* AVX-512: Op code 0f 38 46 */
asm volatile("vpsravd %ymm4,%ymm6,%ymm2");
asm volatile("vpsravd %zmm24,%zmm25,%zmm26");
asm volatile("vpsravq %zmm24,%zmm25,%zmm26");
/* AVX-512: Op code 0f 38 4c */
asm volatile("vrcp14ps %zmm25,%zmm26");
asm volatile("vrcp14pd %zmm27,%zmm28");
/* AVX-512: Op code 0f 38 4d */
asm volatile("vrcp14ss %xmm24,%xmm25,%xmm26{%k7}");
asm volatile("vrcp14sd %xmm24,%xmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 38 4e */
asm volatile("vrsqrt14ps %zmm25,%zmm26");
asm volatile("vrsqrt14pd %zmm27,%zmm28");
/* AVX-512: Op code 0f 38 4f */
asm volatile("vrsqrt14ss %xmm24,%xmm25,%xmm26{%k7}");
asm volatile("vrsqrt14sd %xmm24,%xmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 38 50 */
asm volatile("vpdpbusd %xmm1, %xmm2, %xmm3");
asm volatile("vpdpbusd %ymm1, %ymm2, %ymm3");
asm volatile("vpdpbusd %zmm1, %zmm2, %zmm3");
asm volatile("vpdpbusd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 51 */
asm volatile("vpdpbusds %xmm1, %xmm2, %xmm3");
asm volatile("vpdpbusds %ymm1, %ymm2, %ymm3");
asm volatile("vpdpbusds %zmm1, %zmm2, %zmm3");
asm volatile("vpdpbusds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 52 */
asm volatile("vdpbf16ps %xmm1, %xmm2, %xmm3");
asm volatile("vdpbf16ps %ymm1, %ymm2, %ymm3");
asm volatile("vdpbf16ps %zmm1, %zmm2, %zmm3");
asm volatile("vdpbf16ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vpdpwssd %xmm1, %xmm2, %xmm3");
asm volatile("vpdpwssd %ymm1, %ymm2, %ymm3");
asm volatile("vpdpwssd %zmm1, %zmm2, %zmm3");
asm volatile("vpdpwssd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vp4dpwssd (%rax), %zmm0, %zmm4");
asm volatile("vp4dpwssd (%eax), %zmm0, %zmm4");
asm volatile("vp4dpwssd 0x12345678(%rax,%rcx,8),%zmm0,%zmm4");
asm volatile("vp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 53 */
asm volatile("vpdpwssds %xmm1, %xmm2, %xmm3");
asm volatile("vpdpwssds %ymm1, %ymm2, %ymm3");
asm volatile("vpdpwssds %zmm1, %zmm2, %zmm3");
asm volatile("vpdpwssds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vp4dpwssds (%rax), %zmm0, %zmm4");
asm volatile("vp4dpwssds (%eax), %zmm0, %zmm4");
asm volatile("vp4dpwssds 0x12345678(%rax,%rcx,8),%zmm0,%zmm4");
asm volatile("vp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 54 */
asm volatile("vpopcntb %xmm1, %xmm2");
asm volatile("vpopcntb %ymm1, %ymm2");
asm volatile("vpopcntb %zmm1, %zmm2");
asm volatile("vpopcntb 0x12345678(%rax,%rcx,8),%zmm2");
asm volatile("vpopcntb 0x12345678(%eax,%ecx,8),%zmm2");
asm volatile("vpopcntw %xmm1, %xmm2");
asm volatile("vpopcntw %ymm1, %ymm2");
asm volatile("vpopcntw %zmm1, %zmm2");
asm volatile("vpopcntw 0x12345678(%rax,%rcx,8),%zmm2");
asm volatile("vpopcntw 0x12345678(%eax,%ecx,8),%zmm2");
/* AVX-512: Op code 0f 38 55 */
asm volatile("vpopcntd %xmm1, %xmm2");
asm volatile("vpopcntd %ymm1, %ymm2");
asm volatile("vpopcntd %zmm1, %zmm2");
asm volatile("vpopcntd 0x12345678(%rax,%rcx,8),%zmm2");
asm volatile("vpopcntd 0x12345678(%eax,%ecx,8),%zmm2");
asm volatile("vpopcntq %xmm1, %xmm2");
asm volatile("vpopcntq %ymm1, %ymm2");
asm volatile("vpopcntq %zmm1, %zmm2");
asm volatile("vpopcntq 0x12345678(%rax,%rcx,8),%zmm2");
asm volatile("vpopcntq 0x12345678(%eax,%ecx,8),%zmm2");
/* AVX-512: Op code 0f 38 59 */
asm volatile("vpbroadcastq %xmm4,%xmm6");
asm volatile("vbroadcasti32x2 %xmm27,%zmm26");
/* AVX-512: Op code 0f 38 5a */
asm volatile("vbroadcasti128 (%rcx),%ymm4");
asm volatile("vbroadcasti32x4 (%rcx),%zmm26");
asm volatile("vbroadcasti64x2 (%rcx),%zmm26");
/* AVX-512: Op code 0f 38 5b */
asm volatile("vbroadcasti32x8 (%rcx),%zmm28");
asm volatile("vbroadcasti64x4 (%rcx),%zmm26");
/* AVX-512: Op code 0f 38 62 */
asm volatile("vpexpandb %xmm1, %xmm2");
asm volatile("vpexpandb %ymm1, %ymm2");
asm volatile("vpexpandb %zmm1, %zmm2");
asm volatile("vpexpandb 0x12345678(%rax,%rcx,8),%zmm2");
asm volatile("vpexpandb 0x12345678(%eax,%ecx,8),%zmm2");
asm volatile("vpexpandw %xmm1, %xmm2");
asm volatile("vpexpandw %ymm1, %ymm2");
asm volatile("vpexpandw %zmm1, %zmm2");
asm volatile("vpexpandw 0x12345678(%rax,%rcx,8),%zmm2");
asm volatile("vpexpandw 0x12345678(%eax,%ecx,8),%zmm2");
/* AVX-512: Op code 0f 38 63 */
asm volatile("vpcompressb %xmm1, %xmm2");
asm volatile("vpcompressb %ymm1, %ymm2");
asm volatile("vpcompressb %zmm1, %zmm2");
asm volatile("vpcompressb %zmm2,0x12345678(%rax,%rcx,8)");
asm volatile("vpcompressb %zmm2,0x12345678(%eax,%ecx,8)");
asm volatile("vpcompressw %xmm1, %xmm2");
asm volatile("vpcompressw %ymm1, %ymm2");
asm volatile("vpcompressw %zmm1, %zmm2");
asm volatile("vpcompressw %zmm2,0x12345678(%rax,%rcx,8)");
asm volatile("vpcompressw %zmm2,0x12345678(%eax,%ecx,8)");
/* AVX-512: Op code 0f 38 64 */
asm volatile("vpblendmd %zmm26,%zmm27,%zmm28");
asm volatile("vpblendmq %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 65 */
asm volatile("vblendmps %zmm24,%zmm25,%zmm26");
asm volatile("vblendmpd %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 66 */
asm volatile("vpblendmb %zmm26,%zmm27,%zmm28");
asm volatile("vpblendmw %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 68 */
asm volatile("vp2intersectd %xmm1, %xmm2, %k3");
asm volatile("vp2intersectd %ymm1, %ymm2, %k3");
asm volatile("vp2intersectd %zmm1, %zmm2, %k3");
asm volatile("vp2intersectd 0x12345678(%rax,%rcx,8),%zmm2,%k3");
asm volatile("vp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3");
asm volatile("vp2intersectq %xmm1, %xmm2, %k3");
asm volatile("vp2intersectq %ymm1, %ymm2, %k3");
asm volatile("vp2intersectq %zmm1, %zmm2, %k3");
asm volatile("vp2intersectq 0x12345678(%rax,%rcx,8),%zmm2,%k3");
asm volatile("vp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3");
/* AVX-512: Op code 0f 38 70 */
asm volatile("vpshldvw %xmm1, %xmm2, %xmm3");
asm volatile("vpshldvw %ymm1, %ymm2, %ymm3");
asm volatile("vpshldvw %zmm1, %zmm2, %zmm3");
asm volatile("vpshldvw 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 71 */
asm volatile("vpshldvd %xmm1, %xmm2, %xmm3");
asm volatile("vpshldvd %ymm1, %ymm2, %ymm3");
asm volatile("vpshldvd %zmm1, %zmm2, %zmm3");
asm volatile("vpshldvd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vpshldvq %xmm1, %xmm2, %xmm3");
asm volatile("vpshldvq %ymm1, %ymm2, %ymm3");
asm volatile("vpshldvq %zmm1, %zmm2, %zmm3");
asm volatile("vpshldvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 72 */
asm volatile("vcvtne2ps2bf16 %xmm1, %xmm2, %xmm3");
asm volatile("vcvtne2ps2bf16 %ymm1, %ymm2, %ymm3");
asm volatile("vcvtne2ps2bf16 %zmm1, %zmm2, %zmm3");
asm volatile("vcvtne2ps2bf16 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vcvtneps2bf16 %xmm1, %xmm2");
asm volatile("vcvtneps2bf16 %ymm1, %xmm2");
asm volatile("vcvtneps2bf16 %zmm1, %ymm2");
asm volatile("vcvtneps2bf16 0x12345678(%rax,%rcx,8),%ymm2");
asm volatile("vcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2");
asm volatile("vpshrdvw %xmm1, %xmm2, %xmm3");
asm volatile("vpshrdvw %ymm1, %ymm2, %ymm3");
asm volatile("vpshrdvw %zmm1, %zmm2, %zmm3");
asm volatile("vpshrdvw 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 73 */
asm volatile("vpshrdvd %xmm1, %xmm2, %xmm3");
asm volatile("vpshrdvd %ymm1, %ymm2, %ymm3");
asm volatile("vpshrdvd %zmm1, %zmm2, %zmm3");
asm volatile("vpshrdvd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vpshrdvq %xmm1, %xmm2, %xmm3");
asm volatile("vpshrdvq %ymm1, %ymm2, %ymm3");
asm volatile("vpshrdvq %zmm1, %zmm2, %zmm3");
asm volatile("vpshrdvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 75 */
asm volatile("vpermi2b %zmm24,%zmm25,%zmm26");
asm volatile("vpermi2w %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 76 */
asm volatile("vpermi2d %zmm26,%zmm27,%zmm28");
asm volatile("vpermi2q %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 77 */
asm volatile("vpermi2ps %zmm26,%zmm27,%zmm28");
asm volatile("vpermi2pd %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 7a */
asm volatile("vpbroadcastb %eax,%xmm30");
/* AVX-512: Op code 0f 38 7b */
asm volatile("vpbroadcastw %eax,%xmm30");
/* AVX-512: Op code 0f 38 7c */
asm volatile("vpbroadcastd %eax,%xmm30");
asm volatile("vpbroadcastq %rax,%zmm30");
/* AVX-512: Op code 0f 38 7d */
asm volatile("vpermt2b %zmm26,%zmm27,%zmm28");
asm volatile("vpermt2w %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 7e */
asm volatile("vpermt2d %zmm26,%zmm27,%zmm28");
asm volatile("vpermt2q %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 7f */
asm volatile("vpermt2ps %zmm26,%zmm27,%zmm28");
asm volatile("vpermt2pd %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 83 */
asm volatile("vpmultishiftqb %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 88 */
asm volatile("vexpandps (%rcx),%zmm26");
asm volatile("vexpandpd (%rcx),%zmm28");
/* AVX-512: Op code 0f 38 89 */
asm volatile("vpexpandd (%rcx),%zmm28");
asm volatile("vpexpandq (%rcx),%zmm26");
/* AVX-512: Op code 0f 38 8a */
asm volatile("vcompressps %zmm28,(%rcx)");
asm volatile("vcompresspd %zmm28,(%rcx)");
/* AVX-512: Op code 0f 38 8b */
asm volatile("vpcompressd %zmm28,(%rcx)");
asm volatile("vpcompressq %zmm26,(%rcx)");
/* AVX-512: Op code 0f 38 8d */
asm volatile("vpermb %zmm26,%zmm27,%zmm28");
asm volatile("vpermw %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 8f */
asm volatile("vpshufbitqmb %xmm1, %xmm2, %k3");
asm volatile("vpshufbitqmb %ymm1, %ymm2, %k3");
asm volatile("vpshufbitqmb %zmm1, %zmm2, %k3");
asm volatile("vpshufbitqmb 0x12345678(%rax,%rcx,8),%zmm2,%k3");
asm volatile("vpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3");
/* AVX-512: Op code 0f 38 90 */
asm volatile("vpgatherdd %xmm2,0x02(%rbp,%xmm7,2),%xmm1");
asm volatile("vpgatherdq %xmm2,0x04(%rbp,%xmm7,2),%xmm1");
asm volatile("vpgatherdd 0x7b(%rbp,%zmm27,8),%zmm26{%k1}");
asm volatile("vpgatherdq 0x7b(%rbp,%ymm27,8),%zmm26{%k1}");
/* AVX-512: Op code 0f 38 91 */
asm volatile("vpgatherqd %xmm2,0x02(%rbp,%xmm7,2),%xmm1");
asm volatile("vpgatherqq %xmm2,0x02(%rbp,%xmm7,2),%xmm1");
asm volatile("vpgatherqd 0x7b(%rbp,%zmm27,8),%ymm26{%k1}");
asm volatile("vpgatherqq 0x7b(%rbp,%zmm27,8),%zmm26{%k1}");
/* AVX-512: Op code 0f 38 9a */
asm volatile("vfmsub132ps %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132ps %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub132ps %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub132ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vfmsub132ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vfmsub132pd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132pd %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub132pd %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub132pd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vfmsub132pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("v4fmaddps (%rax), %zmm0, %zmm4");
asm volatile("v4fmaddps (%eax), %zmm0, %zmm4");
asm volatile("v4fmaddps 0x12345678(%rax,%rcx,8),%zmm0,%zmm4");
asm volatile("v4fmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 9b */
asm volatile("vfmsub132ss %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132ss 0x12345678(%rax,%rcx,8),%xmm2,%xmm3");
asm volatile("vfmsub132ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("vfmsub132sd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132sd 0x12345678(%rax,%rcx,8),%xmm2,%xmm3");
asm volatile("vfmsub132sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("v4fmaddss (%rax), %xmm0, %xmm4");
asm volatile("v4fmaddss (%eax), %xmm0, %xmm4");
asm volatile("v4fmaddss 0x12345678(%rax,%rcx,8),%xmm0,%xmm4");
asm volatile("v4fmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4");
/* AVX-512: Op code 0f 38 a0 */
asm volatile("vpscatterdd %zmm28,0x7b(%rbp,%zmm29,8){%k1}");
asm volatile("vpscatterdq %zmm26,0x7b(%rbp,%ymm27,8){%k1}");
/* AVX-512: Op code 0f 38 a1 */
asm volatile("vpscatterqd %ymm6,0x7b(%rbp,%zmm29,8){%k1}");
asm volatile("vpscatterqq %ymm6,0x7b(%rbp,%ymm27,8){%k1}");
/* AVX-512: Op code 0f 38 a2 */
asm volatile("vscatterdps %zmm28,0x7b(%rbp,%zmm29,8){%k1}");
asm volatile("vscatterdpd %zmm28,0x7b(%rbp,%ymm27,8){%k1}");
/* AVX-512: Op code 0f 38 a3 */
asm volatile("vscatterqps %ymm6,0x7b(%rbp,%zmm29,8){%k1}");
asm volatile("vscatterqpd %zmm28,0x7b(%rbp,%zmm29,8){%k1}");
/* AVX-512: Op code 0f 38 aa */
asm volatile("vfmsub213ps %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213ps %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub213ps %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub213ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vfmsub213ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vfmsub213pd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213pd %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub213pd %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub213pd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vfmsub213pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("v4fnmaddps (%rax), %zmm0, %zmm4");
asm volatile("v4fnmaddps (%eax), %zmm0, %zmm4");
asm volatile("v4fnmaddps 0x12345678(%rax,%rcx,8),%zmm0,%zmm4");
asm volatile("v4fnmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 ab */
asm volatile("vfmsub213ss %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213ss 0x12345678(%rax,%rcx,8),%xmm2,%xmm3");
asm volatile("vfmsub213ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("vfmsub213sd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213sd 0x12345678(%rax,%rcx,8),%xmm2,%xmm3");
asm volatile("vfmsub213sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("v4fnmaddss (%rax), %xmm0, %xmm4");
asm volatile("v4fnmaddss (%eax), %xmm0, %xmm4");
asm volatile("v4fnmaddss 0x12345678(%rax,%rcx,8),%xmm0,%xmm4");
asm volatile("v4fnmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4");
/* AVX-512: Op code 0f 38 b4 */
asm volatile("vpmadd52luq %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 b5 */
asm volatile("vpmadd52huq %zmm26,%zmm27,%zmm28");
/* AVX-512: Op code 0f 38 c4 */
asm volatile("vpconflictd %zmm26,%zmm27");
asm volatile("vpconflictq %zmm26,%zmm27");
/* AVX-512: Op code 0f 38 c8 */
asm volatile("vexp2ps %zmm29,%zmm30");
asm volatile("vexp2pd %zmm26,%zmm27");
/* AVX-512: Op code 0f 38 ca */
asm volatile("vrcp28ps %zmm29,%zmm30");
asm volatile("vrcp28pd %zmm26,%zmm27");
/* AVX-512: Op code 0f 38 cb */
asm volatile("vrcp28ss %xmm28,%xmm29,%xmm30{%k7}");
asm volatile("vrcp28sd %xmm25,%xmm26,%xmm27{%k7}");
/* AVX-512: Op code 0f 38 cc */
asm volatile("vrsqrt28ps %zmm29,%zmm30");
asm volatile("vrsqrt28pd %zmm26,%zmm27");
/* AVX-512: Op code 0f 38 cd */
asm volatile("vrsqrt28ss %xmm28,%xmm29,%xmm30{%k7}");
asm volatile("vrsqrt28sd %xmm25,%xmm26,%xmm27{%k7}");
/* AVX-512: Op code 0f 38 cf */
asm volatile("gf2p8mulb %xmm1, %xmm3");
asm volatile("gf2p8mulb 0x12345678(%rax,%rcx,8),%xmm3");
asm volatile("gf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3");
asm volatile("vgf2p8mulb %xmm1, %xmm2, %xmm3");
asm volatile("vgf2p8mulb %ymm1, %ymm2, %ymm3");
asm volatile("vgf2p8mulb %zmm1, %zmm2, %zmm3");
asm volatile("vgf2p8mulb 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 dc */
asm volatile("vaesenc %xmm1, %xmm2, %xmm3");
asm volatile("vaesenc %ymm1, %ymm2, %ymm3");
asm volatile("vaesenc %zmm1, %zmm2, %zmm3");
asm volatile("vaesenc 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 dd */
asm volatile("vaesenclast %xmm1, %xmm2, %xmm3");
asm volatile("vaesenclast %ymm1, %ymm2, %ymm3");
asm volatile("vaesenclast %zmm1, %zmm2, %zmm3");
asm volatile("vaesenclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 de */
asm volatile("vaesdec %xmm1, %xmm2, %xmm3");
asm volatile("vaesdec %ymm1, %ymm2, %ymm3");
asm volatile("vaesdec %zmm1, %zmm2, %zmm3");
asm volatile("vaesdec 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 df */
asm volatile("vaesdeclast %xmm1, %xmm2, %xmm3");
asm volatile("vaesdeclast %ymm1, %ymm2, %ymm3");
asm volatile("vaesdeclast %zmm1, %zmm2, %zmm3");
asm volatile("vaesdeclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3");
asm volatile("vaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a 03 */
asm volatile("valignd $0x12,%zmm28,%zmm29,%zmm30");
asm volatile("valignq $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 08 */
asm volatile("vroundps $0x5,%ymm6,%ymm2");
asm volatile("vrndscaleps $0x12,%zmm25,%zmm26");
/* AVX-512: Op code 0f 3a 09 */
asm volatile("vroundpd $0x5,%ymm6,%ymm2");
asm volatile("vrndscalepd $0x12,%zmm25,%zmm26");
/* AVX-512: Op code 0f 3a 1a */
asm volatile("vroundss $0x5,%xmm4,%xmm6,%xmm2");
asm volatile("vrndscaless $0x12,%xmm24,%xmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 3a 0b */
asm volatile("vroundsd $0x5,%xmm4,%xmm6,%xmm2");
asm volatile("vrndscalesd $0x12,%xmm24,%xmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 3a 18 */
asm volatile("vinsertf128 $0x5,%xmm4,%ymm4,%ymm6");
asm volatile("vinsertf32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}");
asm volatile("vinsertf64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}");
/* AVX-512: Op code 0f 3a 19 */
asm volatile("vextractf128 $0x5,%ymm4,%xmm4");
asm volatile("vextractf32x4 $0x12,%zmm25,%xmm26{%k7}");
asm volatile("vextractf64x2 $0x12,%zmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 3a 1a */
asm volatile("vinsertf32x8 $0x12,%ymm25,%zmm26,%zmm27{%k7}");
asm volatile("vinsertf64x4 $0x12,%ymm28,%zmm29,%zmm30{%k7}");
/* AVX-512: Op code 0f 3a 1b */
asm volatile("vextractf32x8 $0x12,%zmm29,%ymm30{%k7}");
asm volatile("vextractf64x4 $0x12,%zmm26,%ymm27{%k7}");
/* AVX-512: Op code 0f 3a 1e */
asm volatile("vpcmpud $0x12,%zmm29,%zmm30,%k5");
asm volatile("vpcmpuq $0x12,%zmm26,%zmm27,%k5");
/* AVX-512: Op code 0f 3a 1f */
asm volatile("vpcmpd $0x12,%zmm29,%zmm30,%k5");
asm volatile("vpcmpq $0x12,%zmm26,%zmm27,%k5");
/* AVX-512: Op code 0f 3a 23 */
asm volatile("vshuff32x4 $0x12,%zmm28,%zmm29,%zmm30");
asm volatile("vshuff64x2 $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 25 */
asm volatile("vpternlogd $0x12,%zmm28,%zmm29,%zmm30");
asm volatile("vpternlogq $0x12,%zmm28,%zmm29,%zmm30");
/* AVX-512: Op code 0f 3a 26 */
asm volatile("vgetmantps $0x12,%zmm26,%zmm27");
asm volatile("vgetmantpd $0x12,%zmm29,%zmm30");
/* AVX-512: Op code 0f 3a 27 */
asm volatile("vgetmantss $0x12,%xmm25,%xmm26,%xmm27{%k7}");
asm volatile("vgetmantsd $0x12,%xmm28,%xmm29,%xmm30{%k7}");
/* AVX-512: Op code 0f 3a 38 */
asm volatile("vinserti128 $0x5,%xmm4,%ymm4,%ymm6");
asm volatile("vinserti32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}");
asm volatile("vinserti64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}");
/* AVX-512: Op code 0f 3a 39 */
asm volatile("vextracti128 $0x5,%ymm4,%xmm6");
asm volatile("vextracti32x4 $0x12,%zmm25,%xmm26{%k7}");
asm volatile("vextracti64x2 $0x12,%zmm25,%xmm26{%k7}");
/* AVX-512: Op code 0f 3a 3a */
asm volatile("vinserti32x8 $0x12,%ymm28,%zmm29,%zmm30{%k7}");
asm volatile("vinserti64x4 $0x12,%ymm25,%zmm26,%zmm27{%k7}");
/* AVX-512: Op code 0f 3a 3b */
asm volatile("vextracti32x8 $0x12,%zmm29,%ymm30{%k7}");
asm volatile("vextracti64x4 $0x12,%zmm26,%ymm27{%k7}");
/* AVX-512: Op code 0f 3a 3e */
asm volatile("vpcmpub $0x12,%zmm29,%zmm30,%k5");
asm volatile("vpcmpuw $0x12,%zmm26,%zmm27,%k5");
/* AVX-512: Op code 0f 3a 3f */
asm volatile("vpcmpb $0x12,%zmm29,%zmm30,%k5");
asm volatile("vpcmpw $0x12,%zmm26,%zmm27,%k5");
/* AVX-512: Op code 0f 3a 43 */
asm volatile("vmpsadbw $0x5,%ymm4,%ymm6,%ymm2");
asm volatile("vdbpsadbw $0x12,%zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 3a 43 */
asm volatile("vshufi32x4 $0x12,%zmm25,%zmm26,%zmm27");
asm volatile("vshufi64x2 $0x12,%zmm28,%zmm29,%zmm30");
/* AVX-512: Op code 0f 3a 44 */
asm volatile("vpclmulqdq $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpclmulqdq $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpclmulqdq $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpclmulqdq $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 50 */
asm volatile("vrangeps $0x12,%zmm25,%zmm26,%zmm27");
asm volatile("vrangepd $0x12,%zmm28,%zmm29,%zmm30");
/* AVX-512: Op code 0f 3a 51 */
asm volatile("vrangess $0x12,%xmm25,%xmm26,%xmm27");
asm volatile("vrangesd $0x12,%xmm28,%xmm29,%xmm30");
/* AVX-512: Op code 0f 3a 54 */
asm volatile("vfixupimmps $0x12,%zmm28,%zmm29,%zmm30");
asm volatile("vfixupimmpd $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 55 */
asm volatile("vfixupimmss $0x12,%xmm28,%xmm29,%xmm30{%k7}");
asm volatile("vfixupimmsd $0x12,%xmm25,%xmm26,%xmm27{%k7}");
/* AVX-512: Op code 0f 3a 56 */
asm volatile("vreduceps $0x12,%zmm26,%zmm27");
asm volatile("vreducepd $0x12,%zmm29,%zmm30");
/* AVX-512: Op code 0f 3a 57 */
asm volatile("vreducess $0x12,%xmm25,%xmm26,%xmm27");
asm volatile("vreducesd $0x12,%xmm28,%xmm29,%xmm30");
/* AVX-512: Op code 0f 3a 66 */
asm volatile("vfpclassps $0x12,%zmm27,%k5");
asm volatile("vfpclasspd $0x12,%zmm30,%k5");
/* AVX-512: Op code 0f 3a 67 */
asm volatile("vfpclassss $0x12,%xmm27,%k5");
asm volatile("vfpclasssd $0x12,%xmm30,%k5");
/* AVX-512: Op code 0f 3a 70 */
asm volatile("vpshldw $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshldw $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshldw $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshldw $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 71 */
asm volatile("vpshldd $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshldd $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshldd $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshldd $0x12,%zmm25,%zmm26,%zmm27");
asm volatile("vpshldq $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshldq $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshldq $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshldq $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 72 */
asm volatile("vpshrdw $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshrdw $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshrdw $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshrdw $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a 73 */
asm volatile("vpshrdd $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshrdd $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshrdd $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshrdd $0x12,%zmm25,%zmm26,%zmm27");
asm volatile("vpshrdq $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshrdq $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshrdq $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshrdq $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a ce */
asm volatile("gf2p8affineqb $0x12,%xmm1,%xmm3");
asm volatile("vgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vgf2p8affineqb $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 3a cf */
asm volatile("gf2p8affineinvqb $0x12,%xmm1,%xmm3");
asm volatile("vgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vgf2p8affineinvqb $0x12,%zmm25,%zmm26,%zmm27");
/* AVX-512: Op code 0f 72 (Grp13) */
asm volatile("vprord $0x12,%zmm25,%zmm26");
asm volatile("vprorq $0x12,%zmm25,%zmm26");
asm volatile("vprold $0x12,%zmm29,%zmm30");
asm volatile("vprolq $0x12,%zmm29,%zmm30");
asm volatile("psrad $0x2,%mm6");
asm volatile("vpsrad $0x5,%ymm6,%ymm2");
asm volatile("vpsrad $0x5,%zmm26,%zmm22");
asm volatile("vpsraq $0x5,%zmm26,%zmm22");
/* AVX-512: Op code 0f 38 c6 (Grp18) */
asm volatile("vgatherpf0dps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vgatherpf0dpd 0x7b(%r14,%ymm31,8){%k1}");
asm volatile("vgatherpf1dps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vgatherpf1dpd 0x7b(%r14,%ymm31,8){%k1}");
asm volatile("vscatterpf0dps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vscatterpf0dpd 0x7b(%r14,%ymm31,8){%k1}");
asm volatile("vscatterpf1dps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vscatterpf1dpd 0x7b(%r14,%ymm31,8){%k1}");
/* AVX-512: Op code 0f 38 c7 (Grp19) */
asm volatile("vgatherpf0qps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vgatherpf0qpd 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vgatherpf1qps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vgatherpf1qpd 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vscatterpf0qps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vscatterpf0qpd 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vscatterpf1qps 0x7b(%r14,%zmm31,8){%k1}");
asm volatile("vscatterpf1qpd 0x7b(%r14,%zmm31,8){%k1}");
/* AVX-512: Examples */
asm volatile("vaddpd %zmm28,%zmm29,%zmm30");
asm volatile("vaddpd %zmm28,%zmm29,%zmm30{%k7}");
asm volatile("vaddpd %zmm28,%zmm29,%zmm30{%k7}{z}");
asm volatile("vaddpd {rn-sae},%zmm28,%zmm29,%zmm30");
asm volatile("vaddpd {ru-sae},%zmm28,%zmm29,%zmm30");
asm volatile("vaddpd {rd-sae},%zmm28,%zmm29,%zmm30");
asm volatile("vaddpd {rz-sae},%zmm28,%zmm29,%zmm30");
asm volatile("vaddpd (%rcx),%zmm29,%zmm30");
asm volatile("vaddpd 0x123(%rax,%r14,8),%zmm29,%zmm30");
asm volatile("vaddpd (%rcx){1to8},%zmm29,%zmm30");
asm volatile("vaddpd 0x1fc0(%rdx),%zmm29,%zmm30");
asm volatile("vaddpd 0x3f8(%rdx){1to8},%zmm29,%zmm30");
asm volatile("vcmpeq_uqps 0x1fc(%rdx){1to16},%zmm30,%k5");
asm volatile("vcmpltsd 0x123(%rax,%r14,8),%xmm29,%k5{%k7}");
asm volatile("vcmplesd {sae},%xmm28,%xmm29,%k5{%k7}");
asm volatile("vgetmantss $0x5b,0x123(%rax,%r14,8),%xmm29,%xmm30{%k7}");
/* bndmk m64, bnd */
asm volatile("bndmk (%rax), %bnd0");
asm volatile("bndmk (%r8), %bnd0");
asm volatile("bndmk (0x12345678), %bnd0");
asm volatile("bndmk (%rax), %bnd3");
asm volatile("bndmk (%rcx,%rax,1), %bnd0");
asm volatile("bndmk 0x12345678(,%rax,1), %bnd0");
asm volatile("bndmk (%rax,%rcx,1), %bnd0");
asm volatile("bndmk (%rax,%rcx,8), %bnd0");
asm volatile("bndmk 0x12(%rax), %bnd0");
asm volatile("bndmk 0x12(%rbp), %bnd0");
asm volatile("bndmk 0x12(%rcx,%rax,1), %bnd0");
asm volatile("bndmk 0x12(%rbp,%rax,1), %bnd0");
asm volatile("bndmk 0x12(%rax,%rcx,1), %bnd0");
asm volatile("bndmk 0x12(%rax,%rcx,8), %bnd0");
asm volatile("bndmk 0x12345678(%rax), %bnd0");
asm volatile("bndmk 0x12345678(%rbp), %bnd0");
asm volatile("bndmk 0x12345678(%rcx,%rax,1), %bnd0");
asm volatile("bndmk 0x12345678(%rbp,%rax,1), %bnd0");
asm volatile("bndmk 0x12345678(%rax,%rcx,1), %bnd0");
asm volatile("bndmk 0x12345678(%rax,%rcx,8), %bnd0");
/* bndcl r/m64, bnd */
asm volatile("bndcl (%rax), %bnd0");
asm volatile("bndcl (%r8), %bnd0");
asm volatile("bndcl (0x12345678), %bnd0");
asm volatile("bndcl (%rax), %bnd3");
asm volatile("bndcl (%rcx,%rax,1), %bnd0");
asm volatile("bndcl 0x12345678(,%rax,1), %bnd0");
asm volatile("bndcl (%rax,%rcx,1), %bnd0");
asm volatile("bndcl (%rax,%rcx,8), %bnd0");
asm volatile("bndcl 0x12(%rax), %bnd0");
asm volatile("bndcl 0x12(%rbp), %bnd0");
asm volatile("bndcl 0x12(%rcx,%rax,1), %bnd0");
asm volatile("bndcl 0x12(%rbp,%rax,1), %bnd0");
asm volatile("bndcl 0x12(%rax,%rcx,1), %bnd0");
asm volatile("bndcl 0x12(%rax,%rcx,8), %bnd0");
asm volatile("bndcl 0x12345678(%rax), %bnd0");
asm volatile("bndcl 0x12345678(%rbp), %bnd0");
asm volatile("bndcl 0x12345678(%rcx,%rax,1), %bnd0");
asm volatile("bndcl 0x12345678(%rbp,%rax,1), %bnd0");
asm volatile("bndcl 0x12345678(%rax,%rcx,1), %bnd0");
asm volatile("bndcl 0x12345678(%rax,%rcx,8), %bnd0");
asm volatile("bndcl %rax, %bnd0");
/* bndcu r/m64, bnd */
asm volatile("bndcu (%rax), %bnd0");
asm volatile("bndcu (%r8), %bnd0");
asm volatile("bndcu (0x12345678), %bnd0");
asm volatile("bndcu (%rax), %bnd3");
asm volatile("bndcu (%rcx,%rax,1), %bnd0");
asm volatile("bndcu 0x12345678(,%rax,1), %bnd0");
asm volatile("bndcu (%rax,%rcx,1), %bnd0");
asm volatile("bndcu (%rax,%rcx,8), %bnd0");
asm volatile("bndcu 0x12(%rax), %bnd0");
asm volatile("bndcu 0x12(%rbp), %bnd0");
asm volatile("bndcu 0x12(%rcx,%rax,1), %bnd0");
asm volatile("bndcu 0x12(%rbp,%rax,1), %bnd0");
asm volatile("bndcu 0x12(%rax,%rcx,1), %bnd0");
asm volatile("bndcu 0x12(%rax,%rcx,8), %bnd0");
asm volatile("bndcu 0x12345678(%rax), %bnd0");
asm volatile("bndcu 0x12345678(%rbp), %bnd0");
asm volatile("bndcu 0x12345678(%rcx,%rax,1), %bnd0");
asm volatile("bndcu 0x12345678(%rbp,%rax,1), %bnd0");
asm volatile("bndcu 0x12345678(%rax,%rcx,1), %bnd0");
asm volatile("bndcu 0x12345678(%rax,%rcx,8), %bnd0");
asm volatile("bndcu %rax, %bnd0");
/* bndcn r/m64, bnd */
asm volatile("bndcn (%rax), %bnd0");
asm volatile("bndcn (%r8), %bnd0");
asm volatile("bndcn (0x12345678), %bnd0");
asm volatile("bndcn (%rax), %bnd3");
asm volatile("bndcn (%rcx,%rax,1), %bnd0");
asm volatile("bndcn 0x12345678(,%rax,1), %bnd0");
asm volatile("bndcn (%rax,%rcx,1), %bnd0");
asm volatile("bndcn (%rax,%rcx,8), %bnd0");
asm volatile("bndcn 0x12(%rax), %bnd0");
asm volatile("bndcn 0x12(%rbp), %bnd0");
asm volatile("bndcn 0x12(%rcx,%rax,1), %bnd0");
asm volatile("bndcn 0x12(%rbp,%rax,1), %bnd0");
asm volatile("bndcn 0x12(%rax,%rcx,1), %bnd0");
asm volatile("bndcn 0x12(%rax,%rcx,8), %bnd0");
asm volatile("bndcn 0x12345678(%rax), %bnd0");
asm volatile("bndcn 0x12345678(%rbp), %bnd0");
asm volatile("bndcn 0x12345678(%rcx,%rax,1), %bnd0");
asm volatile("bndcn 0x12345678(%rbp,%rax,1), %bnd0");
asm volatile("bndcn 0x12345678(%rax,%rcx,1), %bnd0");
asm volatile("bndcn 0x12345678(%rax,%rcx,8), %bnd0");
asm volatile("bndcn %rax, %bnd0");
/* bndmov m128, bnd */
asm volatile("bndmov (%rax), %bnd0");
asm volatile("bndmov (%r8), %bnd0");
asm volatile("bndmov (0x12345678), %bnd0");
asm volatile("bndmov (%rax), %bnd3");
asm volatile("bndmov (%rcx,%rax,1), %bnd0");
asm volatile("bndmov 0x12345678(,%rax,1), %bnd0");
asm volatile("bndmov (%rax,%rcx,1), %bnd0");
asm volatile("bndmov (%rax,%rcx,8), %bnd0");
asm volatile("bndmov 0x12(%rax), %bnd0");
asm volatile("bndmov 0x12(%rbp), %bnd0");
asm volatile("bndmov 0x12(%rcx,%rax,1), %bnd0");
asm volatile("bndmov 0x12(%rbp,%rax,1), %bnd0");
asm volatile("bndmov 0x12(%rax,%rcx,1), %bnd0");
asm volatile("bndmov 0x12(%rax,%rcx,8), %bnd0");
asm volatile("bndmov 0x12345678(%rax), %bnd0");
asm volatile("bndmov 0x12345678(%rbp), %bnd0");
asm volatile("bndmov 0x12345678(%rcx,%rax,1), %bnd0");
asm volatile("bndmov 0x12345678(%rbp,%rax,1), %bnd0");
asm volatile("bndmov 0x12345678(%rax,%rcx,1), %bnd0");
asm volatile("bndmov 0x12345678(%rax,%rcx,8), %bnd0");
/* bndmov bnd, m128 */
asm volatile("bndmov %bnd0, (%rax)");
asm volatile("bndmov %bnd0, (%r8)");
asm volatile("bndmov %bnd0, (0x12345678)");
asm volatile("bndmov %bnd3, (%rax)");
asm volatile("bndmov %bnd0, (%rcx,%rax,1)");
asm volatile("bndmov %bnd0, 0x12345678(,%rax,1)");
asm volatile("bndmov %bnd0, (%rax,%rcx,1)");
asm volatile("bndmov %bnd0, (%rax,%rcx,8)");
asm volatile("bndmov %bnd0, 0x12(%rax)");
asm volatile("bndmov %bnd0, 0x12(%rbp)");
asm volatile("bndmov %bnd0, 0x12(%rcx,%rax,1)");
asm volatile("bndmov %bnd0, 0x12(%rbp,%rax,1)");
asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,1)");
asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,8)");
asm volatile("bndmov %bnd0, 0x12345678(%rax)");
asm volatile("bndmov %bnd0, 0x12345678(%rbp)");
asm volatile("bndmov %bnd0, 0x12345678(%rcx,%rax,1)");
asm volatile("bndmov %bnd0, 0x12345678(%rbp,%rax,1)");
asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,1)");
asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,8)");
/* bndmov bnd2, bnd1 */
asm volatile("bndmov %bnd0, %bnd1");
asm volatile("bndmov %bnd1, %bnd0");
/* bndldx mib, bnd */
asm volatile("bndldx (%rax), %bnd0");
asm volatile("bndldx (%r8), %bnd0");
asm volatile("bndldx (0x12345678), %bnd0");
asm volatile("bndldx (%rax), %bnd3");
asm volatile("bndldx (%rcx,%rax,1), %bnd0");
asm volatile("bndldx 0x12345678(,%rax,1), %bnd0");
asm volatile("bndldx (%rax,%rcx,1), %bnd0");
asm volatile("bndldx 0x12(%rax), %bnd0");
asm volatile("bndldx 0x12(%rbp), %bnd0");
asm volatile("bndldx 0x12(%rcx,%rax,1), %bnd0");
asm volatile("bndldx 0x12(%rbp,%rax,1), %bnd0");
asm volatile("bndldx 0x12(%rax,%rcx,1), %bnd0");
asm volatile("bndldx 0x12345678(%rax), %bnd0");
asm volatile("bndldx 0x12345678(%rbp), %bnd0");
asm volatile("bndldx 0x12345678(%rcx,%rax,1), %bnd0");
asm volatile("bndldx 0x12345678(%rbp,%rax,1), %bnd0");
asm volatile("bndldx 0x12345678(%rax,%rcx,1), %bnd0");
/* bndstx bnd, mib */
asm volatile("bndstx %bnd0, (%rax)");
asm volatile("bndstx %bnd0, (%r8)");
asm volatile("bndstx %bnd0, (0x12345678)");
asm volatile("bndstx %bnd3, (%rax)");
asm volatile("bndstx %bnd0, (%rcx,%rax,1)");
asm volatile("bndstx %bnd0, 0x12345678(,%rax,1)");
asm volatile("bndstx %bnd0, (%rax,%rcx,1)");
asm volatile("bndstx %bnd0, 0x12(%rax)");
asm volatile("bndstx %bnd0, 0x12(%rbp)");
asm volatile("bndstx %bnd0, 0x12(%rcx,%rax,1)");
asm volatile("bndstx %bnd0, 0x12(%rbp,%rax,1)");
asm volatile("bndstx %bnd0, 0x12(%rax,%rcx,1)");
asm volatile("bndstx %bnd0, 0x12345678(%rax)");
asm volatile("bndstx %bnd0, 0x12345678(%rbp)");
asm volatile("bndstx %bnd0, 0x12345678(%rcx,%rax,1)");
asm volatile("bndstx %bnd0, 0x12345678(%rbp,%rax,1)");
asm volatile("bndstx %bnd0, 0x12345678(%rax,%rcx,1)");
/* bnd prefix on call, ret, jmp and all jcc */
asm volatile("bnd call label1"); /* Expecting: call unconditional 0 */
asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
asm volatile("bnd ret"); /* Expecting: ret indirect 0 */
asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */
asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */
asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0 */
/* sha1rnds4 imm8, xmm2/m128, xmm1 */
asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0");
asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2");
asm volatile("sha1rnds4 $0x91, %xmm8, %xmm0");
asm volatile("sha1rnds4 $0x91, %xmm7, %xmm8");
asm volatile("sha1rnds4 $0x91, %xmm15, %xmm8");
asm volatile("sha1rnds4 $0x91, (%rax), %xmm0");
asm volatile("sha1rnds4 $0x91, (%r8), %xmm0");
asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0");
asm volatile("sha1rnds4 $0x91, (%rax), %xmm3");
asm volatile("sha1rnds4 $0x91, (%rcx,%rax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(,%rax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, (%rax,%rcx,1), %xmm0");
asm volatile("sha1rnds4 $0x91, (%rax,%rcx,8), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%rax), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%rbp), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%rcx,%rax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%rbp,%rax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,8), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rax), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rcx,%rax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp,%rax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm15");
/* sha1nexte xmm2/m128, xmm1 */
asm volatile("sha1nexte %xmm1, %xmm0");
asm volatile("sha1nexte %xmm7, %xmm2");
asm volatile("sha1nexte %xmm8, %xmm0");
asm volatile("sha1nexte %xmm7, %xmm8");
asm volatile("sha1nexte %xmm15, %xmm8");
asm volatile("sha1nexte (%rax), %xmm0");
asm volatile("sha1nexte (%r8), %xmm0");
asm volatile("sha1nexte (0x12345678), %xmm0");
asm volatile("sha1nexte (%rax), %xmm3");
asm volatile("sha1nexte (%rcx,%rax,1), %xmm0");
asm volatile("sha1nexte 0x12345678(,%rax,1), %xmm0");
asm volatile("sha1nexte (%rax,%rcx,1), %xmm0");
asm volatile("sha1nexte (%rax,%rcx,8), %xmm0");
asm volatile("sha1nexte 0x12(%rax), %xmm0");
asm volatile("sha1nexte 0x12(%rbp), %xmm0");
asm volatile("sha1nexte 0x12(%rcx,%rax,1), %xmm0");
asm volatile("sha1nexte 0x12(%rbp,%rax,1), %xmm0");
asm volatile("sha1nexte 0x12(%rax,%rcx,1), %xmm0");
asm volatile("sha1nexte 0x12(%rax,%rcx,8), %xmm0");
asm volatile("sha1nexte 0x12345678(%rax), %xmm0");
asm volatile("sha1nexte 0x12345678(%rbp), %xmm0");
asm volatile("sha1nexte 0x12345678(%rcx,%rax,1), %xmm0");
asm volatile("sha1nexte 0x12345678(%rbp,%rax,1), %xmm0");
asm volatile("sha1nexte 0x12345678(%rax,%rcx,1), %xmm0");
asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm0");
asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm15");
/* sha1msg1 xmm2/m128, xmm1 */
asm volatile("sha1msg1 %xmm1, %xmm0");
asm volatile("sha1msg1 %xmm7, %xmm2");
asm volatile("sha1msg1 %xmm8, %xmm0");
asm volatile("sha1msg1 %xmm7, %xmm8");
asm volatile("sha1msg1 %xmm15, %xmm8");
asm volatile("sha1msg1 (%rax), %xmm0");
asm volatile("sha1msg1 (%r8), %xmm0");
asm volatile("sha1msg1 (0x12345678), %xmm0");
asm volatile("sha1msg1 (%rax), %xmm3");
asm volatile("sha1msg1 (%rcx,%rax,1), %xmm0");
asm volatile("sha1msg1 0x12345678(,%rax,1), %xmm0");
asm volatile("sha1msg1 (%rax,%rcx,1), %xmm0");
asm volatile("sha1msg1 (%rax,%rcx,8), %xmm0");
asm volatile("sha1msg1 0x12(%rax), %xmm0");
asm volatile("sha1msg1 0x12(%rbp), %xmm0");
asm volatile("sha1msg1 0x12(%rcx,%rax,1), %xmm0");
asm volatile("sha1msg1 0x12(%rbp,%rax,1), %xmm0");
asm volatile("sha1msg1 0x12(%rax,%rcx,1), %xmm0");
asm volatile("sha1msg1 0x12(%rax,%rcx,8), %xmm0");
asm volatile("sha1msg1 0x12345678(%rax), %xmm0");
asm volatile("sha1msg1 0x12345678(%rbp), %xmm0");
asm volatile("sha1msg1 0x12345678(%rcx,%rax,1), %xmm0");
asm volatile("sha1msg1 0x12345678(%rbp,%rax,1), %xmm0");
asm volatile("sha1msg1 0x12345678(%rax,%rcx,1), %xmm0");
asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm0");
asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm15");
/* sha1msg2 xmm2/m128, xmm1 */
asm volatile("sha1msg2 %xmm1, %xmm0");
asm volatile("sha1msg2 %xmm7, %xmm2");
asm volatile("sha1msg2 %xmm8, %xmm0");
asm volatile("sha1msg2 %xmm7, %xmm8");
asm volatile("sha1msg2 %xmm15, %xmm8");
asm volatile("sha1msg2 (%rax), %xmm0");
asm volatile("sha1msg2 (%r8), %xmm0");
asm volatile("sha1msg2 (0x12345678), %xmm0");
asm volatile("sha1msg2 (%rax), %xmm3");
asm volatile("sha1msg2 (%rcx,%rax,1), %xmm0");
asm volatile("sha1msg2 0x12345678(,%rax,1), %xmm0");
asm volatile("sha1msg2 (%rax,%rcx,1), %xmm0");
asm volatile("sha1msg2 (%rax,%rcx,8), %xmm0");
asm volatile("sha1msg2 0x12(%rax), %xmm0");
asm volatile("sha1msg2 0x12(%rbp), %xmm0");
asm volatile("sha1msg2 0x12(%rcx,%rax,1), %xmm0");
asm volatile("sha1msg2 0x12(%rbp,%rax,1), %xmm0");
asm volatile("sha1msg2 0x12(%rax,%rcx,1), %xmm0");
asm volatile("sha1msg2 0x12(%rax,%rcx,8), %xmm0");
asm volatile("sha1msg2 0x12345678(%rax), %xmm0");
asm volatile("sha1msg2 0x12345678(%rbp), %xmm0");
asm volatile("sha1msg2 0x12345678(%rcx,%rax,1), %xmm0");
asm volatile("sha1msg2 0x12345678(%rbp,%rax,1), %xmm0");
asm volatile("sha1msg2 0x12345678(%rax,%rcx,1), %xmm0");
asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm0");
asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm15");
/* sha256rnds2 <XMM0>, xmm2/m128, xmm1 */
/* Note sha256rnds2 has an implicit operand 'xmm0' */
asm volatile("sha256rnds2 %xmm4, %xmm1");
asm volatile("sha256rnds2 %xmm7, %xmm2");
asm volatile("sha256rnds2 %xmm8, %xmm1");
asm volatile("sha256rnds2 %xmm7, %xmm8");
asm volatile("sha256rnds2 %xmm15, %xmm8");
asm volatile("sha256rnds2 (%rax), %xmm1");
asm volatile("sha256rnds2 (%r8), %xmm1");
asm volatile("sha256rnds2 (0x12345678), %xmm1");
asm volatile("sha256rnds2 (%rax), %xmm3");
asm volatile("sha256rnds2 (%rcx,%rax,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(,%rax,1), %xmm1");
asm volatile("sha256rnds2 (%rax,%rcx,1), %xmm1");
asm volatile("sha256rnds2 (%rax,%rcx,8), %xmm1");
asm volatile("sha256rnds2 0x12(%rax), %xmm1");
asm volatile("sha256rnds2 0x12(%rbp), %xmm1");
asm volatile("sha256rnds2 0x12(%rcx,%rax,1), %xmm1");
asm volatile("sha256rnds2 0x12(%rbp,%rax,1), %xmm1");
asm volatile("sha256rnds2 0x12(%rax,%rcx,1), %xmm1");
asm volatile("sha256rnds2 0x12(%rax,%rcx,8), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rax), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rbp), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rcx,%rax,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rbp,%rax,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rax,%rcx,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm15");
/* sha256msg1 xmm2/m128, xmm1 */
asm volatile("sha256msg1 %xmm1, %xmm0");
asm volatile("sha256msg1 %xmm7, %xmm2");
asm volatile("sha256msg1 %xmm8, %xmm0");
asm volatile("sha256msg1 %xmm7, %xmm8");
asm volatile("sha256msg1 %xmm15, %xmm8");
asm volatile("sha256msg1 (%rax), %xmm0");
asm volatile("sha256msg1 (%r8), %xmm0");
asm volatile("sha256msg1 (0x12345678), %xmm0");
asm volatile("sha256msg1 (%rax), %xmm3");
asm volatile("sha256msg1 (%rcx,%rax,1), %xmm0");
asm volatile("sha256msg1 0x12345678(,%rax,1), %xmm0");
asm volatile("sha256msg1 (%rax,%rcx,1), %xmm0");
asm volatile("sha256msg1 (%rax,%rcx,8), %xmm0");
asm volatile("sha256msg1 0x12(%rax), %xmm0");
asm volatile("sha256msg1 0x12(%rbp), %xmm0");
asm volatile("sha256msg1 0x12(%rcx,%rax,1), %xmm0");
asm volatile("sha256msg1 0x12(%rbp,%rax,1), %xmm0");
asm volatile("sha256msg1 0x12(%rax,%rcx,1), %xmm0");
asm volatile("sha256msg1 0x12(%rax,%rcx,8), %xmm0");
asm volatile("sha256msg1 0x12345678(%rax), %xmm0");
asm volatile("sha256msg1 0x12345678(%rbp), %xmm0");
asm volatile("sha256msg1 0x12345678(%rcx,%rax,1), %xmm0");
asm volatile("sha256msg1 0x12345678(%rbp,%rax,1), %xmm0");
asm volatile("sha256msg1 0x12345678(%rax,%rcx,1), %xmm0");
asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm0");
asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm15");
/* sha256msg2 xmm2/m128, xmm1 */
asm volatile("sha256msg2 %xmm1, %xmm0");
asm volatile("sha256msg2 %xmm7, %xmm2");
asm volatile("sha256msg2 %xmm8, %xmm0");
asm volatile("sha256msg2 %xmm7, %xmm8");
asm volatile("sha256msg2 %xmm15, %xmm8");
asm volatile("sha256msg2 (%rax), %xmm0");
asm volatile("sha256msg2 (%r8), %xmm0");
asm volatile("sha256msg2 (0x12345678), %xmm0");
asm volatile("sha256msg2 (%rax), %xmm3");
asm volatile("sha256msg2 (%rcx,%rax,1), %xmm0");
asm volatile("sha256msg2 0x12345678(,%rax,1), %xmm0");
asm volatile("sha256msg2 (%rax,%rcx,1), %xmm0");
asm volatile("sha256msg2 (%rax,%rcx,8), %xmm0");
asm volatile("sha256msg2 0x12(%rax), %xmm0");
asm volatile("sha256msg2 0x12(%rbp), %xmm0");
asm volatile("sha256msg2 0x12(%rcx,%rax,1), %xmm0");
asm volatile("sha256msg2 0x12(%rbp,%rax,1), %xmm0");
asm volatile("sha256msg2 0x12(%rax,%rcx,1), %xmm0");
asm volatile("sha256msg2 0x12(%rax,%rcx,8), %xmm0");
asm volatile("sha256msg2 0x12345678(%rax), %xmm0");
asm volatile("sha256msg2 0x12345678(%rbp), %xmm0");
asm volatile("sha256msg2 0x12345678(%rcx,%rax,1), %xmm0");
asm volatile("sha256msg2 0x12345678(%rbp,%rax,1), %xmm0");
asm volatile("sha256msg2 0x12345678(%rax,%rcx,1), %xmm0");
asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm0");
asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm15");
/* clflushopt m8 */
asm volatile("clflushopt (%rax)");
asm volatile("clflushopt (%r8)");
asm volatile("clflushopt (0x12345678)");
asm volatile("clflushopt 0x12345678(%rax,%rcx,8)");
asm volatile("clflushopt 0x12345678(%r8,%rcx,8)");
/* Also check instructions in the same group encoding as clflushopt */
asm volatile("clflush (%rax)");
asm volatile("clflush (%r8)");
asm volatile("sfence");
/* clwb m8 */
asm volatile("clwb (%rax)");
asm volatile("clwb (%r8)");
asm volatile("clwb (0x12345678)");
asm volatile("clwb 0x12345678(%rax,%rcx,8)");
asm volatile("clwb 0x12345678(%r8,%rcx,8)");
/* Also check instructions in the same group encoding as clwb */
asm volatile("xsaveopt (%rax)");
asm volatile("xsaveopt (%r8)");
asm volatile("mfence");
/* cldemote m8 */
asm volatile("cldemote (%rax)");
asm volatile("cldemote (%r8)");
asm volatile("cldemote (0x12345678)");
asm volatile("cldemote 0x12345678(%rax,%rcx,8)");
asm volatile("cldemote 0x12345678(%r8,%rcx,8)");
/* xsavec mem */
asm volatile("xsavec (%rax)");
asm volatile("xsavec (%r8)");
asm volatile("xsavec (0x12345678)");
asm volatile("xsavec 0x12345678(%rax,%rcx,8)");
asm volatile("xsavec 0x12345678(%r8,%rcx,8)");
/* xsaves mem */
asm volatile("xsaves (%rax)");
asm volatile("xsaves (%r8)");
asm volatile("xsaves (0x12345678)");
asm volatile("xsaves 0x12345678(%rax,%rcx,8)");
asm volatile("xsaves 0x12345678(%r8,%rcx,8)");
/* xrstors mem */
asm volatile("xrstors (%rax)");
asm volatile("xrstors (%r8)");
asm volatile("xrstors (0x12345678)");
asm volatile("xrstors 0x12345678(%rax,%rcx,8)");
asm volatile("xrstors 0x12345678(%r8,%rcx,8)");
/* ptwrite */
asm volatile("ptwrite (%rax)");
asm volatile("ptwrite (%r8)");
asm volatile("ptwrite (0x12345678)");
asm volatile("ptwrite 0x12345678(%rax,%rcx,8)");
asm volatile("ptwrite 0x12345678(%r8,%rcx,8)");
asm volatile("ptwritel (%rax)");
asm volatile("ptwritel (%r8)");
asm volatile("ptwritel (0x12345678)");
asm volatile("ptwritel 0x12345678(%rax,%rcx,8)");
asm volatile("ptwritel 0x12345678(%r8,%rcx,8)");
asm volatile("ptwriteq (%rax)");
asm volatile("ptwriteq (%r8)");
asm volatile("ptwriteq (0x12345678)");
asm volatile("ptwriteq 0x12345678(%rax,%rcx,8)");
asm volatile("ptwriteq 0x12345678(%r8,%rcx,8)");
/* tpause */
asm volatile("tpause %ebx");
asm volatile("tpause %r8d");
/* umonitor */
asm volatile("umonitor %eax");
asm volatile("umonitor %rax");
asm volatile("umonitor %r8d");
/* umwait */
asm volatile("umwait %eax");
asm volatile("umwait %r8d");
/* movdiri */
asm volatile("movdiri %rax,(%rbx)");
asm volatile("movdiri %rcx,0x12345678(%rax)");
/* movdir64b */
asm volatile("movdir64b (%rax),%rbx");
asm volatile("movdir64b 0x12345678(%rax),%rcx");
asm volatile("movdir64b (%eax),%ebx");
asm volatile("movdir64b 0x12345678(%eax),%ecx");
/* enqcmd */
asm volatile("enqcmd (%rax),%rbx");
asm volatile("enqcmd 0x12345678(%rax),%rcx");
asm volatile("enqcmd (%eax),%ebx");
asm volatile("enqcmd 0x12345678(%eax),%ecx");
/* enqcmds */
asm volatile("enqcmds (%rax),%rbx");
asm volatile("enqcmds 0x12345678(%rax),%rcx");
asm volatile("enqcmds (%eax),%ebx");
asm volatile("enqcmds 0x12345678(%eax),%ecx");
/* incsspd/q */
asm volatile("incsspd %eax");
asm volatile("incsspd %r8d");
asm volatile("incsspq %rax");
asm volatile("incsspq %r8");
/* Also check instructions in the same group encoding as incsspd/q */
asm volatile("xrstor (%rax)");
asm volatile("xrstor (%r8)");
asm volatile("xrstor (0x12345678)");
asm volatile("xrstor 0x12345678(%rax,%rcx,8)");
asm volatile("xrstor 0x12345678(%r8,%rcx,8)");
asm volatile("lfence");
/* rdsspd/q */
asm volatile("rdsspd %eax");
asm volatile("rdsspd %r8d");
asm volatile("rdsspq %rax");
asm volatile("rdsspq %r8");
/* saveprevssp */
asm volatile("saveprevssp");
/* rstorssp */
asm volatile("rstorssp (%rax)");
asm volatile("rstorssp (%r8)");
asm volatile("rstorssp (0x12345678)");
asm volatile("rstorssp 0x12345678(%rax,%rcx,8)");
asm volatile("rstorssp 0x12345678(%r8,%rcx,8)");
/* wrssd/q */
asm volatile("wrssd %ecx,(%rax)");
asm volatile("wrssd %edx,(%r8)");
asm volatile("wrssd %edx,(0x12345678)");
asm volatile("wrssd %edx,0x12345678(%rax,%rcx,8)");
asm volatile("wrssd %edx,0x12345678(%r8,%rcx,8)");
asm volatile("wrssq %rcx,(%rax)");
asm volatile("wrssq %rdx,(%r8)");
asm volatile("wrssq %rdx,(0x12345678)");
asm volatile("wrssq %rdx,0x12345678(%rax,%rcx,8)");
asm volatile("wrssq %rdx,0x12345678(%r8,%rcx,8)");
/* wrussd/q */
asm volatile("wrussd %ecx,(%rax)");
asm volatile("wrussd %edx,(%r8)");
asm volatile("wrussd %edx,(0x12345678)");
asm volatile("wrussd %edx,0x12345678(%rax,%rcx,8)");
asm volatile("wrussd %edx,0x12345678(%r8,%rcx,8)");
asm volatile("wrussq %rcx,(%rax)");
asm volatile("wrussq %rdx,(%r8)");
asm volatile("wrussq %rdx,(0x12345678)");
asm volatile("wrussq %rdx,0x12345678(%rax,%rcx,8)");
asm volatile("wrussq %rdx,0x12345678(%r8,%rcx,8)");
/* setssbsy */
asm volatile("setssbsy");
/* Also check instructions in the same group encoding as setssbsy */
asm volatile("rdpkru");
asm volatile("wrpkru");
/* clrssbsy */
asm volatile("clrssbsy (%rax)");
asm volatile("clrssbsy (%r8)");
asm volatile("clrssbsy (0x12345678)");
asm volatile("clrssbsy 0x12345678(%rax,%rcx,8)");
asm volatile("clrssbsy 0x12345678(%r8,%rcx,8)");
/* endbr32/64 */
asm volatile("endbr32");
asm volatile("endbr64");
/* call with/without notrack prefix */
asm volatile("callq *%rax"); /* Expecting: call indirect 0 */
asm volatile("callq *(%rax)"); /* Expecting: call indirect 0 */
asm volatile("callq *(%r8)"); /* Expecting: call indirect 0 */
asm volatile("callq *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("callq *0x12345678(%rax,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("callq *0x12345678(%r8,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("bnd callq *%rax"); /* Expecting: call indirect 0 */
asm volatile("bnd callq *(%rax)"); /* Expecting: call indirect 0 */
asm volatile("bnd callq *(%r8)"); /* Expecting: call indirect 0 */
asm volatile("bnd callq *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("bnd callq *0x12345678(%rax,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("bnd callq *0x12345678(%r8,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("notrack callq *%rax"); /* Expecting: call indirect 0 */
asm volatile("notrack callq *(%rax)"); /* Expecting: call indirect 0 */
asm volatile("notrack callq *(%r8)"); /* Expecting: call indirect 0 */
asm volatile("notrack callq *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("notrack callq *0x12345678(%rax,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("notrack callq *0x12345678(%r8,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd callq *%rax"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd callq *(%rax)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd callq *(%r8)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd callq *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd callq *0x12345678(%rax,%rcx,8)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd callq *0x12345678(%r8,%rcx,8)"); /* Expecting: call indirect 0 */
/* jmp with/without notrack prefix */
asm volatile("jmpq *%rax"); /* Expecting: jmp indirect 0 */
asm volatile("jmpq *(%rax)"); /* Expecting: jmp indirect 0 */
asm volatile("jmpq *(%r8)"); /* Expecting: jmp indirect 0 */
asm volatile("jmpq *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("jmpq *0x12345678(%rax,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("jmpq *0x12345678(%r8,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmpq *%rax"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmpq *(%rax)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmpq *(%r8)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmpq *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmpq *0x12345678(%rax,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmpq *0x12345678(%r8,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmpq *%rax"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmpq *(%rax)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmpq *(%r8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmpq *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmpq *0x12345678(%rax,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmpq *0x12345678(%r8,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmpq *%rax"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmpq *(%rax)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmpq *(%r8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmpq *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmpq *0x12345678(%rax,%rcx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmpq *0x12345678(%r8,%rcx,8)"); /* Expecting: jmp indirect 0 */
/* AMX */
asm volatile("ldtilecfg (%rax,%rcx,8)");
asm volatile("ldtilecfg (%r8,%rcx,8)");
asm volatile("sttilecfg (%rax,%rcx,8)");
asm volatile("sttilecfg (%r8,%rcx,8)");
asm volatile("tdpbf16ps %tmm0, %tmm1, %tmm2");
asm volatile("tdpbssd %tmm0, %tmm1, %tmm2");
asm volatile("tdpbsud %tmm0, %tmm1, %tmm2");
asm volatile("tdpbusd %tmm0, %tmm1, %tmm2");
asm volatile("tdpbuud %tmm0, %tmm1, %tmm2");
asm volatile("tileloadd (%rax,%rcx,8), %tmm1");
asm volatile("tileloadd (%r8,%rcx,8), %tmm2");
asm volatile("tileloaddt1 (%rax,%rcx,8), %tmm1");
asm volatile("tileloaddt1 (%r8,%rcx,8), %tmm2");
asm volatile("tilerelease");
asm volatile("tilestored %tmm1, (%rax,%rcx,8)");
asm volatile("tilestored %tmm2, (%r8,%rcx,8)");
asm volatile("tilezero %tmm0");
asm volatile("tilezero %tmm7");
/* User Interrupt */
asm volatile("clui");
asm volatile("senduipi %rax");
asm volatile("senduipi %r8");
asm volatile("stui");
asm volatile("testui");
asm volatile("uiret");
/* AVX512-FP16 */
asm volatile("vaddph %zmm3, %zmm2, %zmm1");
asm volatile("vaddph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vaddph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vaddph %xmm3, %xmm2, %xmm1");
asm volatile("vaddph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vaddph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vaddph %ymm3, %ymm2, %ymm1");
asm volatile("vaddph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vaddph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vaddsh %xmm3, %xmm2, %xmm1");
asm volatile("vaddsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vaddsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcmpph $0x12, %zmm3, %zmm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%rax,%rcx,8), %zmm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%eax,%ecx,8), %zmm2, %k5");
asm volatile("vcmpph $0x12, %xmm3, %xmm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%rax,%rcx,8), %xmm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %k5");
asm volatile("vcmpph $0x12, %ymm3, %ymm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%rax,%rcx,8), %ymm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%eax,%ecx,8), %ymm2, %k5");
asm volatile("vcmpsh $0x12, %xmm3, %xmm2, %k5");
asm volatile("vcmpsh $0x12, 0x12345678(%rax,%rcx,8), %xmm2, %k5");
asm volatile("vcmpsh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %k5");
asm volatile("vcomish %xmm2, %xmm1");
asm volatile("vcomish 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcomish 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtdq2ph %zmm2, %ymm1");
asm volatile("vcvtdq2ph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtdq2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtdq2ph %xmm2, %xmm1");
asm volatile("vcvtdq2ph %ymm2, %xmm1");
asm volatile("vcvtpd2ph %zmm2, %xmm1");
asm volatile("vcvtpd2ph %xmm2, %xmm1");
asm volatile("vcvtpd2ph %ymm2, %xmm1");
asm volatile("vcvtph2dq %ymm2, %zmm1");
asm volatile("vcvtph2dq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2dq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2dq %xmm2, %xmm1");
asm volatile("vcvtph2dq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2dq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2dq %xmm2, %ymm1");
asm volatile("vcvtph2dq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2dq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2pd %xmm2, %zmm1");
asm volatile("vcvtph2pd 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2pd 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2pd %xmm2, %xmm1");
asm volatile("vcvtph2pd 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2pd 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2pd %xmm2, %ymm1");
asm volatile("vcvtph2pd 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2pd 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2ps %ymm2, %zmm1");
asm volatile("vcvtph2ps 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2ps %xmm2, %xmm1");
asm volatile("vcvtph2ps 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2ps %xmm2, %ymm1");
asm volatile("vcvtph2ps 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2ps %xmm2, %xmm1");
asm volatile("vcvtph2ps 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2ps %xmm2, %ymm1");
asm volatile("vcvtph2ps 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2psx %ymm2, %zmm1");
asm volatile("vcvtph2psx 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2psx 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2psx %xmm2, %xmm1");
asm volatile("vcvtph2psx 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2psx 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2psx %xmm2, %ymm1");
asm volatile("vcvtph2psx 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2psx 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2qq %xmm2, %zmm1");
asm volatile("vcvtph2qq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2qq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2qq %xmm2, %xmm1");
asm volatile("vcvtph2qq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2qq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2qq %xmm2, %ymm1");
asm volatile("vcvtph2qq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2qq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2udq %ymm2, %zmm1");
asm volatile("vcvtph2udq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2udq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2udq %xmm2, %xmm1");
asm volatile("vcvtph2udq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2udq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2udq %xmm2, %ymm1");
asm volatile("vcvtph2udq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2udq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2uqq %xmm2, %zmm1");
asm volatile("vcvtph2uqq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2uqq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2uqq %xmm2, %xmm1");
asm volatile("vcvtph2uqq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2uqq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2uqq %xmm2, %ymm1");
asm volatile("vcvtph2uqq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2uqq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2uw %zmm2, %zmm1");
asm volatile("vcvtph2uw 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2uw 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2uw %xmm2, %xmm1");
asm volatile("vcvtph2uw 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2uw 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2uw %ymm2, %ymm1");
asm volatile("vcvtph2uw 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2uw 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2w %zmm2, %zmm1");
asm volatile("vcvtph2w 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtph2w 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2w %xmm2, %xmm1");
asm volatile("vcvtph2w 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtph2w 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2w %ymm2, %ymm1");
asm volatile("vcvtph2w 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtph2w 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtps2ph $0x12, %zmm1, 0x12345678(%rax,%rcx,8)");
asm volatile("vcvtps2ph $0x12, %zmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %zmm2, %ymm1");
asm volatile("vcvtps2ph $0x12, %ymm1, 0x12345678(%rax,%rcx,8)");
asm volatile("vcvtps2ph $0x12, %ymm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %xmm1, 0x12345678(%rax,%rcx,8)");
asm volatile("vcvtps2ph $0x12, %xmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %xmm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %ymm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %ymm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %ymm2, 0x12345678(%rax,%rcx,8)");
asm volatile("vcvtps2ph $0x12, %ymm2, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %xmm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %xmm2, 0x12345678(%rax,%rcx,8)");
asm volatile("vcvtps2ph $0x12, %xmm2, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2phx %zmm2, %ymm1");
asm volatile("vcvtps2phx 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtps2phx 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtps2phx %xmm2, %xmm1");
asm volatile("vcvtps2phx %ymm2, %xmm1");
asm volatile("vcvtqq2ph %zmm2, %xmm1");
asm volatile("vcvtqq2ph %xmm2, %xmm1");
asm volatile("vcvtqq2ph %ymm2, %xmm1");
asm volatile("vcvtsd2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsh2sd 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsh2si 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvtsh2si 0x12345678(%eax,%ecx,8), %rax");
asm volatile("vcvtsh2ss 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsh2usi %xmm1, %eax");
asm volatile("vcvtsh2usi 0x12345678(%rax,%rcx,8), %eax");
asm volatile("vcvtsh2usi 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvtsh2usi %xmm1, %rax");
asm volatile("vcvtsh2usi 0x12345678(%rax,%rcx,8), %rax");
asm volatile("vcvtsh2usi 0x12345678(%eax,%ecx,8), %rax");
asm volatile("vcvtsi2sh %eax, %xmm2, %xmm1");
asm volatile("vcvtsi2sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vcvtsi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsi2sh %rax, %xmm2, %xmm1");
asm volatile("vcvtsi2sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vcvtsi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtss2sh %xmm3, %xmm2, %xmm1");
asm volatile("vcvtss2sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vcvtss2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvttph2dq %ymm2, %zmm1");
asm volatile("vcvttph2dq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvttph2dq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2dq %xmm2, %xmm1");
asm volatile("vcvttph2dq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvttph2dq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2dq %xmm2, %ymm1");
asm volatile("vcvttph2dq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvttph2dq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2qq %xmm2, %zmm1");
asm volatile("vcvttph2qq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvttph2qq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2qq %xmm2, %xmm1");
asm volatile("vcvttph2qq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvttph2qq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2qq %xmm2, %ymm1");
asm volatile("vcvttph2qq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvttph2qq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2udq %ymm2, %zmm1");
asm volatile("vcvttph2udq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvttph2udq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2udq %xmm2, %xmm1");
asm volatile("vcvttph2udq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvttph2udq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2udq %xmm2, %ymm1");
asm volatile("vcvttph2udq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvttph2udq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2uqq %xmm2, %zmm1");
asm volatile("vcvttph2uqq 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvttph2uqq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2uqq %xmm2, %xmm1");
asm volatile("vcvttph2uqq 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvttph2uqq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2uqq %xmm2, %ymm1");
asm volatile("vcvttph2uqq 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvttph2uqq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2uw %zmm2, %zmm1");
asm volatile("vcvttph2uw 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvttph2uw 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2uw %xmm2, %xmm1");
asm volatile("vcvttph2uw 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvttph2uw 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2uw %ymm2, %ymm1");
asm volatile("vcvttph2uw 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvttph2uw 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2w %zmm2, %zmm1");
asm volatile("vcvttph2w 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvttph2w 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2w %xmm2, %xmm1");
asm volatile("vcvttph2w 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvttph2w 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2w %ymm2, %ymm1");
asm volatile("vcvttph2w 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvttph2w 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttsh2si %xmm1, %eax");
asm volatile("vcvttsh2si 0x12345678(%rax,%rcx,8), %eax");
asm volatile("vcvttsh2si 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvttsh2si %xmm1, %rax");
asm volatile("vcvttsh2si 0x12345678(%rax,%rcx,8), %rax");
asm volatile("vcvttsh2si 0x12345678(%eax,%ecx,8), %rax");
asm volatile("vcvttsh2usi %xmm1, %eax");
asm volatile("vcvttsh2usi 0x12345678(%rax,%rcx,8), %eax");
asm volatile("vcvttsh2usi 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvttsh2usi %xmm1, %rax");
asm volatile("vcvttsh2usi 0x12345678(%rax,%rcx,8), %rax");
asm volatile("vcvttsh2usi 0x12345678(%eax,%ecx,8), %rax");
asm volatile("vcvtudq2ph %zmm2, %ymm1");
asm volatile("vcvtudq2ph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtudq2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtudq2ph %xmm2, %xmm1");
asm volatile("vcvtudq2ph %ymm2, %xmm1");
asm volatile("vcvtuqq2ph %zmm2, %xmm1");
asm volatile("vcvtuqq2ph %xmm2, %xmm1");
asm volatile("vcvtuqq2ph %ymm2, %xmm1");
asm volatile("vcvtusi2sh %eax, %xmm2, %xmm1");
asm volatile("vcvtusi2sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vcvtusi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtusi2sh %rax, %xmm2, %xmm1");
asm volatile("vcvtusi2sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vcvtusi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtuw2ph %zmm2, %zmm1");
asm volatile("vcvtuw2ph 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtuw2ph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtuw2ph %xmm2, %xmm1");
asm volatile("vcvtuw2ph 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtuw2ph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtuw2ph %ymm2, %ymm1");
asm volatile("vcvtuw2ph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtuw2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtw2ph %zmm2, %zmm1");
asm volatile("vcvtw2ph 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vcvtw2ph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtw2ph %xmm2, %xmm1");
asm volatile("vcvtw2ph 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vcvtw2ph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtw2ph %ymm2, %ymm1");
asm volatile("vcvtw2ph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vcvtw2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vdivph %zmm3, %zmm2, %zmm1");
asm volatile("vdivph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vdivph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vdivph %xmm3, %xmm2, %xmm1");
asm volatile("vdivph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vdivph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vdivph %ymm3, %ymm2, %ymm1");
asm volatile("vdivph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vdivph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vdivsh %xmm3, %xmm2, %xmm1");
asm volatile("vdivsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vdivsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmaddcph %zmm3, %zmm2, %zmm1");
asm volatile("vfcmaddcph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfcmaddcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfcmaddcph %xmm3, %xmm2, %xmm1");
asm volatile("vfcmaddcph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfcmaddcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmaddcph %ymm3, %ymm2, %ymm1");
asm volatile("vfcmaddcph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfcmaddcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfcmaddcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfcmaddcsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfcmaddcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmulcph %zmm3, %zmm2, %zmm1");
asm volatile("vfcmulcph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfcmulcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfcmulcph %xmm3, %xmm2, %xmm1");
asm volatile("vfcmulcph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfcmulcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmulcph %ymm3, %ymm2, %ymm1");
asm volatile("vfcmulcph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfcmulcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfcmulcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfcmulcsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfcmulcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmadd132ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmadd132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmadd132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd132ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmadd132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmadd132ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmadd132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmadd132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd132sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmadd132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmadd213ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmadd213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmadd213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd213ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmadd213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmadd213ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmadd213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmadd213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd213sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmadd213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmadd231ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmadd231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmadd231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd231ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmadd231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmadd231ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmadd231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmadd231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd231sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmadd231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddcph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddcph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmaddcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddcph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddcph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmaddcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddcph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddcph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmaddcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmaddcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddcsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmaddcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddsub132ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddsub132ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddsub132ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddsub213ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddsub213ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddsub213ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddsub231ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddsub231ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddsub231ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsub132ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmsub132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsub132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub132ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsub132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsub132ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmsub132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub132sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsub132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsub213ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmsub213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsub213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub213ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsub213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsub213ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmsub213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub213sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsub213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsub231ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmsub231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsub231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub231ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsub231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsub231ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmsub231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub231sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsub231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsubadd132ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsubadd132ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsubadd132ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsubadd213ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsubadd213ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsubadd213ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsubadd231ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsubadd231ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsubadd231ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmulcph %zmm3, %zmm2, %zmm1");
asm volatile("vfmulcph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfmulcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmulcph %xmm3, %xmm2, %xmm1");
asm volatile("vfmulcph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmulcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmulcph %ymm3, %ymm2, %ymm1");
asm volatile("vfmulcph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfmulcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmulcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfmulcsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfmulcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmadd132ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfnmadd132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmadd132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd132ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmadd132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmadd132ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfnmadd132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmadd132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd132sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmadd132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmadd213ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfnmadd213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmadd213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd213ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmadd213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmadd213ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfnmadd213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmadd213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd213sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmadd213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmadd231ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfnmadd231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmadd231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd231ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmadd231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmadd231ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfnmadd231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmadd231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd231sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmadd231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmsub132ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfnmsub132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmsub132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub132ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmsub132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmsub132ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfnmsub132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmsub132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub132sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmsub132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmsub213ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfnmsub213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmsub213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub213ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmsub213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmsub213ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfnmsub213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmsub213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub213sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmsub213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmsub231ph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vfnmsub231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmsub231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub231ph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmsub231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmsub231ph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vfnmsub231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmsub231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub231sh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vfnmsub231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfpclassph $0x12, %zmm1, %k5");
asm volatile("vfpclassph $0x12, %xmm1, %k5");
asm volatile("vfpclassph $0x12, %ymm1, %k5");
asm volatile("vfpclasssh $0x12, %xmm1, %k5");
asm volatile("vfpclasssh $0x12, 0x12345678(%rax,%rcx,8), %k5");
asm volatile("vfpclasssh $0x12, 0x12345678(%eax,%ecx,8), %k5");
asm volatile("vgetexpph %zmm2, %zmm1");
asm volatile("vgetexpph 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vgetexpph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vgetexpph %xmm2, %xmm1");
asm volatile("vgetexpph 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vgetexpph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vgetexpph %ymm2, %ymm1");
asm volatile("vgetexpph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vgetexpph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vgetexpsh %xmm3, %xmm2, %xmm1");
asm volatile("vgetexpsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vgetexpsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vgetmantph $0x12, %zmm2, %zmm1");
asm volatile("vgetmantph $0x12, 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vgetmantph $0x12, 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vgetmantph $0x12, %xmm2, %xmm1");
asm volatile("vgetmantph $0x12, 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vgetmantph $0x12, 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vgetmantph $0x12, %ymm2, %ymm1");
asm volatile("vgetmantph $0x12, 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vgetmantph $0x12, 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vgetmantsh $0x12, %xmm3, %xmm2, %xmm1");
asm volatile("vgetmantsh $0x12, 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vgetmantsh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmaxph %zmm3, %zmm2, %zmm1");
asm volatile("vmaxph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vmaxph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vmaxph %xmm3, %xmm2, %xmm1");
asm volatile("vmaxph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vmaxph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmaxph %ymm3, %ymm2, %ymm1");
asm volatile("vmaxph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vmaxph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vmaxsh %xmm3, %xmm2, %xmm1");
asm volatile("vmaxsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vmaxsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vminph %zmm3, %zmm2, %zmm1");
asm volatile("vminph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vminph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vminph %xmm3, %xmm2, %xmm1");
asm volatile("vminph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vminph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vminph %ymm3, %ymm2, %ymm1");
asm volatile("vminph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vminph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vminsh %xmm3, %xmm2, %xmm1");
asm volatile("vminsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vminsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmovsh %xmm1, 0x12345678(%rax,%rcx,8)");
asm volatile("vmovsh %xmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vmovsh 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vmovsh 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vmovsh %xmm3, %xmm2, %xmm1");
asm volatile("vmovw %xmm1, %eax");
asm volatile("vmovw %xmm1, 0x12345678(%rax,%rcx,8)");
asm volatile("vmovw %xmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vmovw %eax, %xmm1");
asm volatile("vmovw 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vmovw 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vmulph %zmm3, %zmm2, %zmm1");
asm volatile("vmulph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vmulph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vmulph %xmm3, %xmm2, %xmm1");
asm volatile("vmulph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vmulph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmulph %ymm3, %ymm2, %ymm1");
asm volatile("vmulph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vmulph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vmulsh %xmm3, %xmm2, %xmm1");
asm volatile("vmulsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vmulsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vrcpph %zmm2, %zmm1");
asm volatile("vrcpph 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vrcpph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vrcpph %xmm2, %xmm1");
asm volatile("vrcpph 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vrcpph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vrcpph %ymm2, %ymm1");
asm volatile("vrcpph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vrcpph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vrcpsh %xmm3, %xmm2, %xmm1");
asm volatile("vrcpsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vrcpsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vreduceph $0x12, %zmm2, %zmm1");
asm volatile("vreduceph $0x12, 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vreduceph $0x12, 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vreduceph $0x12, %xmm2, %xmm1");
asm volatile("vreduceph $0x12, 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vreduceph $0x12, 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vreduceph $0x12, %ymm2, %ymm1");
asm volatile("vreduceph $0x12, 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vreduceph $0x12, 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vreducesh $0x12, %xmm3, %xmm2, %xmm1");
asm volatile("vreducesh $0x12, 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vreducesh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vrndscaleph $0x12, %zmm2, %zmm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vrndscaleph $0x12, %xmm2, %xmm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vrndscaleph $0x12, %ymm2, %ymm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vrndscalesh $0x12, %xmm3, %xmm2, %xmm1");
asm volatile("vrndscalesh $0x12, 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vrndscalesh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vrsqrtph %zmm2, %zmm1");
asm volatile("vrsqrtph 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vrsqrtph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vrsqrtph %xmm2, %xmm1");
asm volatile("vrsqrtph 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vrsqrtph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vrsqrtph %ymm2, %ymm1");
asm volatile("vrsqrtph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vrsqrtph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vrsqrtsh %xmm3, %xmm2, %xmm1");
asm volatile("vrsqrtsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vrsqrtsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vscalefph %zmm3, %zmm2, %zmm1");
asm volatile("vscalefph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vscalefph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vscalefph %xmm3, %xmm2, %xmm1");
asm volatile("vscalefph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vscalefph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vscalefph %ymm3, %ymm2, %ymm1");
asm volatile("vscalefph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vscalefph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vscalefsh %xmm3, %xmm2, %xmm1");
asm volatile("vscalefsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vscalefsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vsqrtph %zmm2, %zmm1");
asm volatile("vsqrtph 0x12345678(%rax,%rcx,8), %zmm1");
asm volatile("vsqrtph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vsqrtph %xmm2, %xmm1");
asm volatile("vsqrtph 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vsqrtph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vsqrtph %ymm2, %ymm1");
asm volatile("vsqrtph 0x12345678(%rax,%rcx,8), %ymm1");
asm volatile("vsqrtph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vsqrtsh %xmm3, %xmm2, %xmm1");
asm volatile("vsqrtsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vsqrtsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vsubph %zmm3, %zmm2, %zmm1");
asm volatile("vsubph 0x12345678(%rax,%rcx,8), %zmm2, %zmm1");
asm volatile("vsubph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vsubph %xmm3, %xmm2, %xmm1");
asm volatile("vsubph 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vsubph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vsubph %ymm3, %ymm2, %ymm1");
asm volatile("vsubph 0x12345678(%rax,%rcx,8), %ymm2, %ymm1");
asm volatile("vsubph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vsubsh %xmm3, %xmm2, %xmm1");
asm volatile("vsubsh 0x12345678(%rax,%rcx,8), %xmm2, %xmm1");
asm volatile("vsubsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vucomish %xmm2, %xmm1");
asm volatile("vucomish 0x12345678(%rax,%rcx,8), %xmm1");
asm volatile("vucomish 0x12345678(%eax,%ecx,8), %xmm1");
#else /* #ifdef __x86_64__ */
/* bound r32, mem (same op code as EVEX prefix) */
asm volatile("bound %eax, 0x12345678(%ecx)");
asm volatile("bound %ecx, 0x12345678(%eax)");
asm volatile("bound %edx, 0x12345678(%eax)");
asm volatile("bound %ebx, 0x12345678(%eax)");
asm volatile("bound %esp, 0x12345678(%eax)");
asm volatile("bound %ebp, 0x12345678(%eax)");
asm volatile("bound %esi, 0x12345678(%eax)");
asm volatile("bound %edi, 0x12345678(%eax)");
asm volatile("bound %ecx, (%eax)");
asm volatile("bound %eax, (0x12345678)");
asm volatile("bound %edx, (%ecx,%eax,1)");
asm volatile("bound %edx, 0x12345678(,%eax,1)");
asm volatile("bound %edx, (%eax,%ecx,1)");
asm volatile("bound %edx, (%eax,%ecx,8)");
asm volatile("bound %edx, 0x12(%eax)");
asm volatile("bound %edx, 0x12(%ebp)");
asm volatile("bound %edx, 0x12(%ecx,%eax,1)");
asm volatile("bound %edx, 0x12(%ebp,%eax,1)");
asm volatile("bound %edx, 0x12(%eax,%ecx,1)");
asm volatile("bound %edx, 0x12(%eax,%ecx,8)");
asm volatile("bound %edx, 0x12345678(%eax)");
asm volatile("bound %edx, 0x12345678(%ebp)");
asm volatile("bound %edx, 0x12345678(%ecx,%eax,1)");
asm volatile("bound %edx, 0x12345678(%ebp,%eax,1)");
asm volatile("bound %edx, 0x12345678(%eax,%ecx,1)");
asm volatile("bound %edx, 0x12345678(%eax,%ecx,8)");
/* bound r16, mem (same op code as EVEX prefix) */
asm volatile("bound %ax, 0x12345678(%ecx)");
asm volatile("bound %cx, 0x12345678(%eax)");
asm volatile("bound %dx, 0x12345678(%eax)");
asm volatile("bound %bx, 0x12345678(%eax)");
asm volatile("bound %sp, 0x12345678(%eax)");
asm volatile("bound %bp, 0x12345678(%eax)");
asm volatile("bound %si, 0x12345678(%eax)");
asm volatile("bound %di, 0x12345678(%eax)");
asm volatile("bound %cx, (%eax)");
asm volatile("bound %ax, (0x12345678)");
asm volatile("bound %dx, (%ecx,%eax,1)");
asm volatile("bound %dx, 0x12345678(,%eax,1)");
asm volatile("bound %dx, (%eax,%ecx,1)");
asm volatile("bound %dx, (%eax,%ecx,8)");
asm volatile("bound %dx, 0x12(%eax)");
asm volatile("bound %dx, 0x12(%ebp)");
asm volatile("bound %dx, 0x12(%ecx,%eax,1)");
asm volatile("bound %dx, 0x12(%ebp,%eax,1)");
asm volatile("bound %dx, 0x12(%eax,%ecx,1)");
asm volatile("bound %dx, 0x12(%eax,%ecx,8)");
asm volatile("bound %dx, 0x12345678(%eax)");
asm volatile("bound %dx, 0x12345678(%ebp)");
asm volatile("bound %dx, 0x12345678(%ecx,%eax,1)");
asm volatile("bound %dx, 0x12345678(%ebp,%eax,1)");
asm volatile("bound %dx, 0x12345678(%eax,%ecx,1)");
asm volatile("bound %dx, 0x12345678(%eax,%ecx,8)");
/* AVX-512: Instructions with the same op codes as Mask Instructions */
asm volatile("cmovno %eax,%ebx");
asm volatile("cmovno 0x12345678(%eax),%ecx");
asm volatile("cmovno 0x12345678(%eax),%cx");
asm volatile("cmove %eax,%ebx");
asm volatile("cmove 0x12345678(%eax),%ecx");
asm volatile("cmove 0x12345678(%eax),%cx");
asm volatile("seto 0x12345678(%eax)");
asm volatile("setno 0x12345678(%eax)");
asm volatile("setb 0x12345678(%eax)");
asm volatile("setc 0x12345678(%eax)");
asm volatile("setnae 0x12345678(%eax)");
asm volatile("setae 0x12345678(%eax)");
asm volatile("setnb 0x12345678(%eax)");
asm volatile("setnc 0x12345678(%eax)");
asm volatile("sets 0x12345678(%eax)");
asm volatile("setns 0x12345678(%eax)");
/* AVX-512: Mask Instructions */
asm volatile("kandw %k7,%k6,%k5");
asm volatile("kandq %k7,%k6,%k5");
asm volatile("kandb %k7,%k6,%k5");
asm volatile("kandd %k7,%k6,%k5");
asm volatile("kandnw %k7,%k6,%k5");
asm volatile("kandnq %k7,%k6,%k5");
asm volatile("kandnb %k7,%k6,%k5");
asm volatile("kandnd %k7,%k6,%k5");
asm volatile("knotw %k7,%k6");
asm volatile("knotq %k7,%k6");
asm volatile("knotb %k7,%k6");
asm volatile("knotd %k7,%k6");
asm volatile("korw %k7,%k6,%k5");
asm volatile("korq %k7,%k6,%k5");
asm volatile("korb %k7,%k6,%k5");
asm volatile("kord %k7,%k6,%k5");
asm volatile("kxnorw %k7,%k6,%k5");
asm volatile("kxnorq %k7,%k6,%k5");
asm volatile("kxnorb %k7,%k6,%k5");
asm volatile("kxnord %k7,%k6,%k5");
asm volatile("kxorw %k7,%k6,%k5");
asm volatile("kxorq %k7,%k6,%k5");
asm volatile("kxorb %k7,%k6,%k5");
asm volatile("kxord %k7,%k6,%k5");
asm volatile("kaddw %k7,%k6,%k5");
asm volatile("kaddq %k7,%k6,%k5");
asm volatile("kaddb %k7,%k6,%k5");
asm volatile("kaddd %k7,%k6,%k5");
asm volatile("kunpckbw %k7,%k6,%k5");
asm volatile("kunpckwd %k7,%k6,%k5");
asm volatile("kunpckdq %k7,%k6,%k5");
asm volatile("kmovw %k6,%k5");
asm volatile("kmovw (%ecx),%k5");
asm volatile("kmovw 0x123(%eax,%ecx,8),%k5");
asm volatile("kmovw %k5,(%ecx)");
asm volatile("kmovw %k5,0x123(%eax,%ecx,8)");
asm volatile("kmovw %eax,%k5");
asm volatile("kmovw %ebp,%k5");
asm volatile("kmovw %k5,%eax");
asm volatile("kmovw %k5,%ebp");
asm volatile("kmovq %k6,%k5");
asm volatile("kmovq (%ecx),%k5");
asm volatile("kmovq 0x123(%eax,%ecx,8),%k5");
asm volatile("kmovq %k5,(%ecx)");
asm volatile("kmovq %k5,0x123(%eax,%ecx,8)");
asm volatile("kmovb %k6,%k5");
asm volatile("kmovb (%ecx),%k5");
asm volatile("kmovb 0x123(%eax,%ecx,8),%k5");
asm volatile("kmovb %k5,(%ecx)");
asm volatile("kmovb %k5,0x123(%eax,%ecx,8)");
asm volatile("kmovb %eax,%k5");
asm volatile("kmovb %ebp,%k5");
asm volatile("kmovb %k5,%eax");
asm volatile("kmovb %k5,%ebp");
asm volatile("kmovd %k6,%k5");
asm volatile("kmovd (%ecx),%k5");
asm volatile("kmovd 0x123(%eax,%ecx,8),%k5");
asm volatile("kmovd %k5,(%ecx)");
asm volatile("kmovd %k5,0x123(%eax,%ecx,8)");
asm volatile("kmovd %eax,%k5");
asm volatile("kmovd %ebp,%k5");
asm volatile("kmovd %k5,%eax");
asm volatile("kmovd %k5,%ebp");
asm volatile("kortestw %k6,%k5");
asm volatile("kortestq %k6,%k5");
asm volatile("kortestb %k6,%k5");
asm volatile("kortestd %k6,%k5");
asm volatile("ktestw %k6,%k5");
asm volatile("ktestq %k6,%k5");
asm volatile("ktestb %k6,%k5");
asm volatile("ktestd %k6,%k5");
asm volatile("kshiftrw $0x12,%k6,%k5");
asm volatile("kshiftrq $0x5b,%k6,%k5");
asm volatile("kshiftlw $0x12,%k6,%k5");
asm volatile("kshiftlq $0x5b,%k6,%k5");
/* AVX-512: Op code 0f 5b */
asm volatile("vcvtdq2ps %xmm5,%xmm6");
asm volatile("vcvtqq2ps %zmm5,%ymm6{%k7}");
asm volatile("vcvtps2dq %xmm5,%xmm6");
asm volatile("vcvttps2dq %xmm5,%xmm6");
/* AVX-512: Op code 0f 6f */
asm volatile("movq %mm0,%mm4");
asm volatile("vmovdqa %ymm4,%ymm6");
asm volatile("vmovdqa32 %zmm5,%zmm6");
asm volatile("vmovdqa64 %zmm5,%zmm6");
asm volatile("vmovdqu %ymm4,%ymm6");
asm volatile("vmovdqu32 %zmm5,%zmm6");
asm volatile("vmovdqu64 %zmm5,%zmm6");
asm volatile("vmovdqu8 %zmm5,%zmm6");
asm volatile("vmovdqu16 %zmm5,%zmm6");
/* AVX-512: Op code 0f 78 */
asm volatile("vmread %eax,%ebx");
asm volatile("vcvttps2udq %zmm5,%zmm6");
asm volatile("vcvttpd2udq %zmm5,%ymm6{%k7}");
asm volatile("vcvttsd2usi %xmm6,%eax");
asm volatile("vcvttss2usi %xmm6,%eax");
asm volatile("vcvttps2uqq %ymm5,%zmm6{%k7}");
asm volatile("vcvttpd2uqq %zmm5,%zmm6");
/* AVX-512: Op code 0f 79 */
asm volatile("vmwrite %eax,%ebx");
asm volatile("vcvtps2udq %zmm5,%zmm6");
asm volatile("vcvtpd2udq %zmm5,%ymm6{%k7}");
asm volatile("vcvtsd2usi %xmm6,%eax");
asm volatile("vcvtss2usi %xmm6,%eax");
asm volatile("vcvtps2uqq %ymm5,%zmm6{%k7}");
asm volatile("vcvtpd2uqq %zmm5,%zmm6");
/* AVX-512: Op code 0f 7a */
asm volatile("vcvtudq2pd %ymm5,%zmm6{%k7}");
asm volatile("vcvtuqq2pd %zmm5,%zmm6");
asm volatile("vcvtudq2ps %zmm5,%zmm6");
asm volatile("vcvtuqq2ps %zmm5,%ymm6{%k7}");
asm volatile("vcvttps2qq %ymm5,%zmm6{%k7}");
asm volatile("vcvttpd2qq %zmm5,%zmm6");
/* AVX-512: Op code 0f 7b */
asm volatile("vcvtusi2sd %eax,%xmm5,%xmm6");
asm volatile("vcvtusi2ss %eax,%xmm5,%xmm6");
asm volatile("vcvtps2qq %ymm5,%zmm6{%k7}");
asm volatile("vcvtpd2qq %zmm5,%zmm6");
/* AVX-512: Op code 0f 7f */
asm volatile("movq.s %mm0,%mm4");
asm volatile("vmovdqa.s %ymm5,%ymm6");
asm volatile("vmovdqa32.s %zmm5,%zmm6");
asm volatile("vmovdqa64.s %zmm5,%zmm6");
asm volatile("vmovdqu.s %ymm5,%ymm6");
asm volatile("vmovdqu32.s %zmm5,%zmm6");
asm volatile("vmovdqu64.s %zmm5,%zmm6");
asm volatile("vmovdqu8.s %zmm5,%zmm6");
asm volatile("vmovdqu16.s %zmm5,%zmm6");
/* AVX-512: Op code 0f db */
asm volatile("pand %mm1,%mm2");
asm volatile("pand %xmm1,%xmm2");
asm volatile("vpand %ymm4,%ymm6,%ymm2");
asm volatile("vpandd %zmm4,%zmm5,%zmm6");
asm volatile("vpandq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f df */
asm volatile("pandn %mm1,%mm2");
asm volatile("pandn %xmm1,%xmm2");
asm volatile("vpandn %ymm4,%ymm6,%ymm2");
asm volatile("vpandnd %zmm4,%zmm5,%zmm6");
asm volatile("vpandnq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f e6 */
asm volatile("vcvttpd2dq %xmm1,%xmm2");
asm volatile("vcvtdq2pd %xmm5,%xmm6");
asm volatile("vcvtdq2pd %ymm5,%zmm6{%k7}");
asm volatile("vcvtqq2pd %zmm5,%zmm6");
asm volatile("vcvtpd2dq %xmm1,%xmm2");
/* AVX-512: Op code 0f eb */
asm volatile("por %mm4,%mm6");
asm volatile("vpor %ymm4,%ymm6,%ymm2");
asm volatile("vpord %zmm4,%zmm5,%zmm6");
asm volatile("vporq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f ef */
asm volatile("pxor %mm4,%mm6");
asm volatile("vpxor %ymm4,%ymm6,%ymm2");
asm volatile("vpxord %zmm4,%zmm5,%zmm6");
asm volatile("vpxorq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 10 */
asm volatile("pblendvb %xmm1,%xmm0");
asm volatile("vpsrlvw %zmm4,%zmm5,%zmm6");
asm volatile("vpmovuswb %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 11 */
asm volatile("vpmovusdb %zmm5,%xmm6{%k7}");
asm volatile("vpsravw %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 12 */
asm volatile("vpmovusqb %zmm5,%xmm6{%k7}");
asm volatile("vpsllvw %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 13 */
asm volatile("vcvtph2ps %xmm3,%ymm5");
asm volatile("vcvtph2ps %ymm5,%zmm6{%k7}");
asm volatile("vpmovusdw %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 14 */
asm volatile("blendvps %xmm1,%xmm0");
asm volatile("vpmovusqw %zmm5,%xmm6{%k7}");
asm volatile("vprorvd %zmm4,%zmm5,%zmm6");
asm volatile("vprorvq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 15 */
asm volatile("blendvpd %xmm1,%xmm0");
asm volatile("vpmovusqd %zmm5,%ymm6{%k7}");
asm volatile("vprolvd %zmm4,%zmm5,%zmm6");
asm volatile("vprolvq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 16 */
asm volatile("vpermps %ymm4,%ymm6,%ymm2");
asm volatile("vpermps %ymm4,%ymm6,%ymm2{%k7}");
asm volatile("vpermpd %ymm4,%ymm6,%ymm2{%k7}");
/* AVX-512: Op code 0f 38 19 */
asm volatile("vbroadcastsd %xmm4,%ymm6");
asm volatile("vbroadcastf32x2 %xmm7,%zmm6");
/* AVX-512: Op code 0f 38 1a */
asm volatile("vbroadcastf128 (%ecx),%ymm4");
asm volatile("vbroadcastf32x4 (%ecx),%zmm6");
asm volatile("vbroadcastf64x2 (%ecx),%zmm6");
/* AVX-512: Op code 0f 38 1b */
asm volatile("vbroadcastf32x8 (%ecx),%zmm6");
asm volatile("vbroadcastf64x4 (%ecx),%zmm6");
/* AVX-512: Op code 0f 38 1f */
asm volatile("vpabsq %zmm4,%zmm6");
/* AVX-512: Op code 0f 38 20 */
asm volatile("vpmovsxbw %xmm4,%xmm5");
asm volatile("vpmovswb %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 21 */
asm volatile("vpmovsxbd %xmm4,%ymm6");
asm volatile("vpmovsdb %zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 22 */
asm volatile("vpmovsxbq %xmm4,%ymm4");
asm volatile("vpmovsqb %zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 23 */
asm volatile("vpmovsxwd %xmm4,%ymm4");
asm volatile("vpmovsdw %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 24 */
asm volatile("vpmovsxwq %xmm4,%ymm6");
asm volatile("vpmovsqw %zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 25 */
asm volatile("vpmovsxdq %xmm4,%ymm4");
asm volatile("vpmovsqd %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 26 */
asm volatile("vptestmb %zmm5,%zmm6,%k5");
asm volatile("vptestmw %zmm5,%zmm6,%k5");
asm volatile("vptestnmb %zmm4,%zmm5,%k5");
asm volatile("vptestnmw %zmm4,%zmm5,%k5");
/* AVX-512: Op code 0f 38 27 */
asm volatile("vptestmd %zmm5,%zmm6,%k5");
asm volatile("vptestmq %zmm5,%zmm6,%k5");
asm volatile("vptestnmd %zmm4,%zmm5,%k5");
asm volatile("vptestnmq %zmm4,%zmm5,%k5");
/* AVX-512: Op code 0f 38 28 */
asm volatile("vpmuldq %ymm4,%ymm6,%ymm2");
asm volatile("vpmovm2b %k5,%zmm6");
asm volatile("vpmovm2w %k5,%zmm6");
/* AVX-512: Op code 0f 38 29 */
asm volatile("vpcmpeqq %ymm4,%ymm6,%ymm2");
asm volatile("vpmovb2m %zmm6,%k5");
asm volatile("vpmovw2m %zmm6,%k5");
/* AVX-512: Op code 0f 38 2a */
asm volatile("vmovntdqa (%ecx),%ymm4");
asm volatile("vpbroadcastmb2q %k6,%zmm1");
/* AVX-512: Op code 0f 38 2c */
asm volatile("vmaskmovps (%ecx),%ymm4,%ymm6");
asm volatile("vscalefps %zmm4,%zmm5,%zmm6");
asm volatile("vscalefpd %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 2d */
asm volatile("vmaskmovpd (%ecx),%ymm4,%ymm6");
asm volatile("vscalefss %xmm4,%xmm5,%xmm6{%k7}");
asm volatile("vscalefsd %xmm4,%xmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 30 */
asm volatile("vpmovzxbw %xmm4,%ymm4");
asm volatile("vpmovwb %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 31 */
asm volatile("vpmovzxbd %xmm4,%ymm6");
asm volatile("vpmovdb %zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 32 */
asm volatile("vpmovzxbq %xmm4,%ymm4");
asm volatile("vpmovqb %zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 33 */
asm volatile("vpmovzxwd %xmm4,%ymm4");
asm volatile("vpmovdw %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 34 */
asm volatile("vpmovzxwq %xmm4,%ymm6");
asm volatile("vpmovqw %zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 35 */
asm volatile("vpmovzxdq %xmm4,%ymm4");
asm volatile("vpmovqd %zmm5,%ymm6{%k7}");
/* AVX-512: Op code 0f 38 36 */
asm volatile("vpermd %ymm4,%ymm6,%ymm2");
asm volatile("vpermd %ymm4,%ymm6,%ymm2{%k7}");
asm volatile("vpermq %ymm4,%ymm6,%ymm2{%k7}");
/* AVX-512: Op code 0f 38 38 */
asm volatile("vpminsb %ymm4,%ymm6,%ymm2");
asm volatile("vpmovm2d %k5,%zmm6");
asm volatile("vpmovm2q %k5,%zmm6");
/* AVX-512: Op code 0f 38 39 */
asm volatile("vpminsd %xmm1,%xmm2,%xmm3");
asm volatile("vpminsd %zmm4,%zmm5,%zmm6");
asm volatile("vpminsq %zmm4,%zmm5,%zmm6");
asm volatile("vpmovd2m %zmm6,%k5");
asm volatile("vpmovq2m %zmm6,%k5");
/* AVX-512: Op code 0f 38 3a */
asm volatile("vpminuw %ymm4,%ymm6,%ymm2");
asm volatile("vpbroadcastmw2d %k6,%zmm6");
/* AVX-512: Op code 0f 38 3b */
asm volatile("vpminud %ymm4,%ymm6,%ymm2");
asm volatile("vpminud %zmm4,%zmm5,%zmm6");
asm volatile("vpminuq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 3d */
asm volatile("vpmaxsd %ymm4,%ymm6,%ymm2");
asm volatile("vpmaxsd %zmm4,%zmm5,%zmm6");
asm volatile("vpmaxsq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 3f */
asm volatile("vpmaxud %ymm4,%ymm6,%ymm2");
asm volatile("vpmaxud %zmm4,%zmm5,%zmm6");
asm volatile("vpmaxuq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 40 */
asm volatile("vpmulld %ymm4,%ymm6,%ymm2");
asm volatile("vpmulld %zmm4,%zmm5,%zmm6");
asm volatile("vpmullq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 42 */
asm volatile("vgetexpps %zmm5,%zmm6");
asm volatile("vgetexppd %zmm5,%zmm6");
/* AVX-512: Op code 0f 38 43 */
asm volatile("vgetexpss %xmm4,%xmm5,%xmm6{%k7}");
asm volatile("vgetexpsd %xmm2,%xmm3,%xmm4{%k7}");
/* AVX-512: Op code 0f 38 44 */
asm volatile("vplzcntd %zmm5,%zmm6");
asm volatile("vplzcntq %zmm5,%zmm6");
/* AVX-512: Op code 0f 38 46 */
asm volatile("vpsravd %ymm4,%ymm6,%ymm2");
asm volatile("vpsravd %zmm4,%zmm5,%zmm6");
asm volatile("vpsravq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 4c */
asm volatile("vrcp14ps %zmm5,%zmm6");
asm volatile("vrcp14pd %zmm5,%zmm6");
/* AVX-512: Op code 0f 38 4d */
asm volatile("vrcp14ss %xmm4,%xmm5,%xmm6{%k7}");
asm volatile("vrcp14sd %xmm4,%xmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 4e */
asm volatile("vrsqrt14ps %zmm5,%zmm6");
asm volatile("vrsqrt14pd %zmm5,%zmm6");
/* AVX-512: Op code 0f 38 4f */
asm volatile("vrsqrt14ss %xmm4,%xmm5,%xmm6{%k7}");
asm volatile("vrsqrt14sd %xmm4,%xmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 38 50 */
asm volatile("vpdpbusd %xmm1, %xmm2, %xmm3");
asm volatile("vpdpbusd %ymm1, %ymm2, %ymm3");
asm volatile("vpdpbusd %zmm1, %zmm2, %zmm3");
asm volatile("vpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 51 */
asm volatile("vpdpbusds %xmm1, %xmm2, %xmm3");
asm volatile("vpdpbusds %ymm1, %ymm2, %ymm3");
asm volatile("vpdpbusds %zmm1, %zmm2, %zmm3");
asm volatile("vpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 52 */
asm volatile("vdpbf16ps %xmm1, %xmm2, %xmm3");
asm volatile("vdpbf16ps %ymm1, %ymm2, %ymm3");
asm volatile("vdpbf16ps %zmm1, %zmm2, %zmm3");
asm volatile("vdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vpdpwssd %xmm1, %xmm2, %xmm3");
asm volatile("vpdpwssd %ymm1, %ymm2, %ymm3");
asm volatile("vpdpwssd %zmm1, %zmm2, %zmm3");
asm volatile("vpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vp4dpwssd (%eax), %zmm0, %zmm4");
asm volatile("vp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 53 */
asm volatile("vpdpwssds %xmm1, %xmm2, %xmm3");
asm volatile("vpdpwssds %ymm1, %ymm2, %ymm3");
asm volatile("vpdpwssds %zmm1, %zmm2, %zmm3");
asm volatile("vpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vp4dpwssds (%eax), %zmm0, %zmm4");
asm volatile("vp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 54 */
asm volatile("vpopcntb %xmm1, %xmm2");
asm volatile("vpopcntb %ymm1, %ymm2");
asm volatile("vpopcntb %zmm1, %zmm2");
asm volatile("vpopcntb 0x12345678(%eax,%ecx,8),%zmm2");
asm volatile("vpopcntw %xmm1, %xmm2");
asm volatile("vpopcntw %ymm1, %ymm2");
asm volatile("vpopcntw %zmm1, %zmm2");
asm volatile("vpopcntw 0x12345678(%eax,%ecx,8),%zmm2");
/* AVX-512: Op code 0f 38 55 */
asm volatile("vpopcntd %xmm1, %xmm2");
asm volatile("vpopcntd %ymm1, %ymm2");
asm volatile("vpopcntd %zmm1, %zmm2");
asm volatile("vpopcntd 0x12345678(%eax,%ecx,8),%zmm2");
asm volatile("vpopcntq %xmm1, %xmm2");
asm volatile("vpopcntq %ymm1, %ymm2");
asm volatile("vpopcntq %zmm1, %zmm2");
asm volatile("vpopcntq 0x12345678(%eax,%ecx,8),%zmm2");
/* AVX-512: Op code 0f 38 59 */
asm volatile("vpbroadcastq %xmm4,%xmm6");
asm volatile("vbroadcasti32x2 %xmm7,%zmm6");
/* AVX-512: Op code 0f 38 5a */
asm volatile("vbroadcasti128 (%ecx),%ymm4");
asm volatile("vbroadcasti32x4 (%ecx),%zmm6");
asm volatile("vbroadcasti64x2 (%ecx),%zmm6");
/* AVX-512: Op code 0f 38 5b */
asm volatile("vbroadcasti32x8 (%ecx),%zmm6");
asm volatile("vbroadcasti64x4 (%ecx),%zmm6");
/* AVX-512: Op code 0f 38 62 */
asm volatile("vpexpandb %xmm1, %xmm2");
asm volatile("vpexpandb %ymm1, %ymm2");
asm volatile("vpexpandb %zmm1, %zmm2");
asm volatile("vpexpandb 0x12345678(%eax,%ecx,8),%zmm2");
asm volatile("vpexpandw %xmm1, %xmm2");
asm volatile("vpexpandw %ymm1, %ymm2");
asm volatile("vpexpandw %zmm1, %zmm2");
asm volatile("vpexpandw 0x12345678(%eax,%ecx,8),%zmm2");
/* AVX-512: Op code 0f 38 63 */
asm volatile("vpcompressb %xmm1, %xmm2");
asm volatile("vpcompressb %ymm1, %ymm2");
asm volatile("vpcompressb %zmm1, %zmm2");
asm volatile("vpcompressb %zmm2,0x12345678(%eax,%ecx,8)");
asm volatile("vpcompressw %xmm1, %xmm2");
asm volatile("vpcompressw %ymm1, %ymm2");
asm volatile("vpcompressw %zmm1, %zmm2");
asm volatile("vpcompressw %zmm2,0x12345678(%eax,%ecx,8)");
/* AVX-512: Op code 0f 38 64 */
asm volatile("vpblendmd %zmm4,%zmm5,%zmm6");
asm volatile("vpblendmq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 65 */
asm volatile("vblendmps %zmm4,%zmm5,%zmm6");
asm volatile("vblendmpd %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 66 */
asm volatile("vpblendmb %zmm4,%zmm5,%zmm6");
asm volatile("vpblendmw %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 68 */
asm volatile("vp2intersectd %xmm1, %xmm2, %k3");
asm volatile("vp2intersectd %ymm1, %ymm2, %k3");
asm volatile("vp2intersectd %zmm1, %zmm2, %k3");
asm volatile("vp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3");
asm volatile("vp2intersectq %xmm1, %xmm2, %k3");
asm volatile("vp2intersectq %ymm1, %ymm2, %k3");
asm volatile("vp2intersectq %zmm1, %zmm2, %k3");
asm volatile("vp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3");
/* AVX-512: Op code 0f 38 70 */
asm volatile("vpshldvw %xmm1, %xmm2, %xmm3");
asm volatile("vpshldvw %ymm1, %ymm2, %ymm3");
asm volatile("vpshldvw %zmm1, %zmm2, %zmm3");
asm volatile("vpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 71 */
asm volatile("vpshldvd %xmm1, %xmm2, %xmm3");
asm volatile("vpshldvd %ymm1, %ymm2, %ymm3");
asm volatile("vpshldvd %zmm1, %zmm2, %zmm3");
asm volatile("vpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vpshldvq %xmm1, %xmm2, %xmm3");
asm volatile("vpshldvq %ymm1, %ymm2, %ymm3");
asm volatile("vpshldvq %zmm1, %zmm2, %zmm3");
asm volatile("vpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 72 */
asm volatile("vcvtne2ps2bf16 %xmm1, %xmm2, %xmm3");
asm volatile("vcvtne2ps2bf16 %ymm1, %ymm2, %ymm3");
asm volatile("vcvtne2ps2bf16 %zmm1, %zmm2, %zmm3");
asm volatile("vcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vcvtneps2bf16 %xmm1, %xmm2");
asm volatile("vcvtneps2bf16 %ymm1, %xmm2");
asm volatile("vcvtneps2bf16 %zmm1, %ymm2");
asm volatile("vcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2");
asm volatile("vpshrdvw %xmm1, %xmm2, %xmm3");
asm volatile("vpshrdvw %ymm1, %ymm2, %ymm3");
asm volatile("vpshrdvw %zmm1, %zmm2, %zmm3");
asm volatile("vpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 73 */
asm volatile("vpshrdvd %xmm1, %xmm2, %xmm3");
asm volatile("vpshrdvd %ymm1, %ymm2, %ymm3");
asm volatile("vpshrdvd %zmm1, %zmm2, %zmm3");
asm volatile("vpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vpshrdvq %xmm1, %xmm2, %xmm3");
asm volatile("vpshrdvq %ymm1, %ymm2, %ymm3");
asm volatile("vpshrdvq %zmm1, %zmm2, %zmm3");
asm volatile("vpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 75 */
asm volatile("vpermi2b %zmm4,%zmm5,%zmm6");
asm volatile("vpermi2w %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 76 */
asm volatile("vpermi2d %zmm4,%zmm5,%zmm6");
asm volatile("vpermi2q %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 77 */
asm volatile("vpermi2ps %zmm4,%zmm5,%zmm6");
asm volatile("vpermi2pd %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 7a */
asm volatile("vpbroadcastb %eax,%xmm3");
/* AVX-512: Op code 0f 38 7b */
asm volatile("vpbroadcastw %eax,%xmm3");
/* AVX-512: Op code 0f 38 7c */
asm volatile("vpbroadcastd %eax,%xmm3");
/* AVX-512: Op code 0f 38 7d */
asm volatile("vpermt2b %zmm4,%zmm5,%zmm6");
asm volatile("vpermt2w %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 7e */
asm volatile("vpermt2d %zmm4,%zmm5,%zmm6");
asm volatile("vpermt2q %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 7f */
asm volatile("vpermt2ps %zmm4,%zmm5,%zmm6");
asm volatile("vpermt2pd %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 83 */
asm volatile("vpmultishiftqb %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 88 */
asm volatile("vexpandps (%ecx),%zmm6");
asm volatile("vexpandpd (%ecx),%zmm6");
/* AVX-512: Op code 0f 38 89 */
asm volatile("vpexpandd (%ecx),%zmm6");
asm volatile("vpexpandq (%ecx),%zmm6");
/* AVX-512: Op code 0f 38 8a */
asm volatile("vcompressps %zmm6,(%ecx)");
asm volatile("vcompresspd %zmm6,(%ecx)");
/* AVX-512: Op code 0f 38 8b */
asm volatile("vpcompressd %zmm6,(%ecx)");
asm volatile("vpcompressq %zmm6,(%ecx)");
/* AVX-512: Op code 0f 38 8d */
asm volatile("vpermb %zmm4,%zmm5,%zmm6");
asm volatile("vpermw %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 8f */
asm volatile("vpshufbitqmb %xmm1, %xmm2, %k3");
asm volatile("vpshufbitqmb %ymm1, %ymm2, %k3");
asm volatile("vpshufbitqmb %zmm1, %zmm2, %k3");
asm volatile("vpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3");
/* AVX-512: Op code 0f 38 90 */
asm volatile("vpgatherdd %xmm2,0x02(%ebp,%xmm7,2),%xmm1");
asm volatile("vpgatherdq %xmm2,0x04(%ebp,%xmm7,2),%xmm1");
asm volatile("vpgatherdd 0x7b(%ebp,%zmm7,8),%zmm6{%k1}");
asm volatile("vpgatherdq 0x7b(%ebp,%ymm7,8),%zmm6{%k1}");
/* AVX-512: Op code 0f 38 91 */
asm volatile("vpgatherqd %xmm2,0x02(%ebp,%xmm7,2),%xmm1");
asm volatile("vpgatherqq %xmm2,0x02(%ebp,%xmm7,2),%xmm1");
asm volatile("vpgatherqd 0x7b(%ebp,%zmm7,8),%ymm6{%k1}");
asm volatile("vpgatherqq 0x7b(%ebp,%zmm7,8),%zmm6{%k1}");
/* AVX-512: Op code 0f 38 9a */
asm volatile("vfmsub132ps %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132ps %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub132ps %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub132ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vfmsub132pd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132pd %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub132pd %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub132pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("v4fmaddps (%eax), %zmm0, %zmm4");
asm volatile("v4fmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 9b */
asm volatile("vfmsub132ss %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("vfmsub132sd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub132sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("v4fmaddss (%eax), %xmm0, %xmm4");
asm volatile("v4fmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4");
/* AVX-512: Op code 0f 38 a0 */
asm volatile("vpscatterdd %zmm6,0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vpscatterdq %zmm6,0x7b(%ebp,%ymm7,8){%k1}");
/* AVX-512: Op code 0f 38 a1 */
asm volatile("vpscatterqd %ymm6,0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vpscatterqq %ymm6,0x7b(%ebp,%ymm7,8){%k1}");
/* AVX-512: Op code 0f 38 a2 */
asm volatile("vscatterdps %zmm6,0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterdpd %zmm6,0x7b(%ebp,%ymm7,8){%k1}");
/* AVX-512: Op code 0f 38 a3 */
asm volatile("vscatterqps %ymm6,0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterqpd %zmm6,0x7b(%ebp,%zmm7,8){%k1}");
/* AVX-512: Op code 0f 38 aa */
asm volatile("vfmsub213ps %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213ps %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub213ps %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub213ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("vfmsub213pd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213pd %ymm1, %ymm2, %ymm3");
asm volatile("vfmsub213pd %zmm1, %zmm2, %zmm3");
asm volatile("vfmsub213pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
asm volatile("v4fnmaddps (%eax), %zmm0, %zmm4");
asm volatile("v4fnmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4");
/* AVX-512: Op code 0f 38 ab */
asm volatile("vfmsub213ss %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("vfmsub213sd %xmm1, %xmm2, %xmm3");
asm volatile("vfmsub213sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3");
asm volatile("v4fnmaddss (%eax), %xmm0, %xmm4");
asm volatile("v4fnmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4");
/* AVX-512: Op code 0f 38 b4 */
asm volatile("vpmadd52luq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 b5 */
asm volatile("vpmadd52huq %zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 38 c4 */
asm volatile("vpconflictd %zmm5,%zmm6");
asm volatile("vpconflictq %zmm5,%zmm6");
/* AVX-512: Op code 0f 38 c8 */
asm volatile("vexp2ps %zmm6,%zmm7");
asm volatile("vexp2pd %zmm6,%zmm7");
/* AVX-512: Op code 0f 38 ca */
asm volatile("vrcp28ps %zmm6,%zmm7");
asm volatile("vrcp28pd %zmm6,%zmm7");
/* AVX-512: Op code 0f 38 cb */
asm volatile("vrcp28ss %xmm5,%xmm6,%xmm7{%k7}");
asm volatile("vrcp28sd %xmm5,%xmm6,%xmm7{%k7}");
/* AVX-512: Op code 0f 38 cc */
asm volatile("vrsqrt28ps %zmm6,%zmm7");
asm volatile("vrsqrt28pd %zmm6,%zmm7");
/* AVX-512: Op code 0f 38 cd */
asm volatile("vrsqrt28ss %xmm5,%xmm6,%xmm7{%k7}");
asm volatile("vrsqrt28sd %xmm5,%xmm6,%xmm7{%k7}");
/* AVX-512: Op code 0f 38 cf */
asm volatile("gf2p8mulb %xmm1, %xmm3");
asm volatile("gf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3");
asm volatile("vgf2p8mulb %xmm1, %xmm2, %xmm3");
asm volatile("vgf2p8mulb %ymm1, %ymm2, %ymm3");
asm volatile("vgf2p8mulb %zmm1, %zmm2, %zmm3");
asm volatile("vgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 dc */
asm volatile("vaesenc %xmm1, %xmm2, %xmm3");
asm volatile("vaesenc %ymm1, %ymm2, %ymm3");
asm volatile("vaesenc %zmm1, %zmm2, %zmm3");
asm volatile("vaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 dd */
asm volatile("vaesenclast %xmm1, %xmm2, %xmm3");
asm volatile("vaesenclast %ymm1, %ymm2, %ymm3");
asm volatile("vaesenclast %zmm1, %zmm2, %zmm3");
asm volatile("vaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 de */
asm volatile("vaesdec %xmm1, %xmm2, %xmm3");
asm volatile("vaesdec %ymm1, %ymm2, %ymm3");
asm volatile("vaesdec %zmm1, %zmm2, %zmm3");
asm volatile("vaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 38 df */
asm volatile("vaesdeclast %xmm1, %xmm2, %xmm3");
asm volatile("vaesdeclast %ymm1, %ymm2, %ymm3");
asm volatile("vaesdeclast %zmm1, %zmm2, %zmm3");
asm volatile("vaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a 03 */
asm volatile("valignd $0x12,%zmm5,%zmm6,%zmm7");
asm volatile("valignq $0x12,%zmm5,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 08 */
asm volatile("vroundps $0x5,%ymm6,%ymm2");
asm volatile("vrndscaleps $0x12,%zmm5,%zmm6");
/* AVX-512: Op code 0f 3a 09 */
asm volatile("vroundpd $0x5,%ymm6,%ymm2");
asm volatile("vrndscalepd $0x12,%zmm5,%zmm6");
/* AVX-512: Op code 0f 3a 0a */
asm volatile("vroundss $0x5,%xmm4,%xmm6,%xmm2");
asm volatile("vrndscaless $0x12,%xmm4,%xmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 3a 0b */
asm volatile("vroundsd $0x5,%xmm4,%xmm6,%xmm2");
asm volatile("vrndscalesd $0x12,%xmm4,%xmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 3a 18 */
asm volatile("vinsertf128 $0x5,%xmm4,%ymm4,%ymm6");
asm volatile("vinsertf32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}");
asm volatile("vinsertf64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}");
/* AVX-512: Op code 0f 3a 19 */
asm volatile("vextractf128 $0x5,%ymm4,%xmm4");
asm volatile("vextractf32x4 $0x12,%zmm5,%xmm6{%k7}");
asm volatile("vextractf64x2 $0x12,%zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 3a 1a */
asm volatile("vinsertf32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}");
asm volatile("vinsertf64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}");
/* AVX-512: Op code 0f 3a 1b */
asm volatile("vextractf32x8 $0x12,%zmm6,%ymm7{%k7}");
asm volatile("vextractf64x4 $0x12,%zmm6,%ymm7{%k7}");
/* AVX-512: Op code 0f 3a 1e */
asm volatile("vpcmpud $0x12,%zmm6,%zmm7,%k5");
asm volatile("vpcmpuq $0x12,%zmm6,%zmm7,%k5");
/* AVX-512: Op code 0f 3a 1f */
asm volatile("vpcmpd $0x12,%zmm6,%zmm7,%k5");
asm volatile("vpcmpq $0x12,%zmm6,%zmm7,%k5");
/* AVX-512: Op code 0f 3a 23 */
asm volatile("vshuff32x4 $0x12,%zmm5,%zmm6,%zmm7");
asm volatile("vshuff64x2 $0x12,%zmm5,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 25 */
asm volatile("vpternlogd $0x12,%zmm5,%zmm6,%zmm7");
asm volatile("vpternlogq $0x12,%zmm5,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 26 */
asm volatile("vgetmantps $0x12,%zmm6,%zmm7");
asm volatile("vgetmantpd $0x12,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 27 */
asm volatile("vgetmantss $0x12,%xmm5,%xmm6,%xmm7{%k7}");
asm volatile("vgetmantsd $0x12,%xmm5,%xmm6,%xmm7{%k7}");
/* AVX-512: Op code 0f 3a 38 */
asm volatile("vinserti128 $0x5,%xmm4,%ymm4,%ymm6");
asm volatile("vinserti32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}");
asm volatile("vinserti64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}");
/* AVX-512: Op code 0f 3a 39 */
asm volatile("vextracti128 $0x5,%ymm4,%xmm6");
asm volatile("vextracti32x4 $0x12,%zmm5,%xmm6{%k7}");
asm volatile("vextracti64x2 $0x12,%zmm5,%xmm6{%k7}");
/* AVX-512: Op code 0f 3a 3a */
asm volatile("vinserti32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}");
asm volatile("vinserti64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}");
/* AVX-512: Op code 0f 3a 3b */
asm volatile("vextracti32x8 $0x12,%zmm6,%ymm7{%k7}");
asm volatile("vextracti64x4 $0x12,%zmm6,%ymm7{%k7}");
/* AVX-512: Op code 0f 3a 3e */
asm volatile("vpcmpub $0x12,%zmm6,%zmm7,%k5");
asm volatile("vpcmpuw $0x12,%zmm6,%zmm7,%k5");
/* AVX-512: Op code 0f 3a 3f */
asm volatile("vpcmpb $0x12,%zmm6,%zmm7,%k5");
asm volatile("vpcmpw $0x12,%zmm6,%zmm7,%k5");
/* AVX-512: Op code 0f 3a 42 */
asm volatile("vmpsadbw $0x5,%ymm4,%ymm6,%ymm2");
asm volatile("vdbpsadbw $0x12,%zmm4,%zmm5,%zmm6");
/* AVX-512: Op code 0f 3a 43 */
asm volatile("vshufi32x4 $0x12,%zmm5,%zmm6,%zmm7");
asm volatile("vshufi64x2 $0x12,%zmm5,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 44 */
asm volatile("vpclmulqdq $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpclmulqdq $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpclmulqdq $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a 50 */
asm volatile("vrangeps $0x12,%zmm5,%zmm6,%zmm7");
asm volatile("vrangepd $0x12,%zmm5,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 51 */
asm volatile("vrangess $0x12,%xmm5,%xmm6,%xmm7");
asm volatile("vrangesd $0x12,%xmm5,%xmm6,%xmm7");
/* AVX-512: Op code 0f 3a 54 */
asm volatile("vfixupimmps $0x12,%zmm5,%zmm6,%zmm7");
asm volatile("vfixupimmpd $0x12,%zmm5,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 55 */
asm volatile("vfixupimmss $0x12,%xmm5,%xmm6,%xmm7{%k7}");
asm volatile("vfixupimmsd $0x12,%xmm5,%xmm6,%xmm7{%k7}");
/* AVX-512: Op code 0f 3a 56 */
asm volatile("vreduceps $0x12,%zmm6,%zmm7");
asm volatile("vreducepd $0x12,%zmm6,%zmm7");
/* AVX-512: Op code 0f 3a 57 */
asm volatile("vreducess $0x12,%xmm5,%xmm6,%xmm7");
asm volatile("vreducesd $0x12,%xmm5,%xmm6,%xmm7");
/* AVX-512: Op code 0f 3a 66 */
asm volatile("vfpclassps $0x12,%zmm7,%k5");
asm volatile("vfpclasspd $0x12,%zmm7,%k5");
/* AVX-512: Op code 0f 3a 67 */
asm volatile("vfpclassss $0x12,%xmm7,%k5");
asm volatile("vfpclasssd $0x12,%xmm7,%k5");
/* AVX-512: Op code 0f 3a 70 */
asm volatile("vpshldw $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshldw $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshldw $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a 71 */
asm volatile("vpshldd $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshldd $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshldd $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshldq $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshldq $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshldq $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a 72 */
asm volatile("vpshrdw $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshrdw $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshrdw $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a 73 */
asm volatile("vpshrdd $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshrdd $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshrdd $0x12,%zmm1,%zmm2,%zmm3");
asm volatile("vpshrdq $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vpshrdq $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vpshrdq $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a ce */
asm volatile("gf2p8affineqb $0x12,%xmm1,%xmm3");
asm volatile("vgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 3a cf */
asm volatile("gf2p8affineinvqb $0x12,%xmm1,%xmm3");
asm volatile("vgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3");
asm volatile("vgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3");
asm volatile("vgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3");
/* AVX-512: Op code 0f 72 (Grp13) */
asm volatile("vprord $0x12,%zmm5,%zmm6");
asm volatile("vprorq $0x12,%zmm5,%zmm6");
asm volatile("vprold $0x12,%zmm5,%zmm6");
asm volatile("vprolq $0x12,%zmm5,%zmm6");
asm volatile("psrad $0x2,%mm6");
asm volatile("vpsrad $0x5,%ymm6,%ymm2");
asm volatile("vpsrad $0x5,%zmm6,%zmm2");
asm volatile("vpsraq $0x5,%zmm6,%zmm2");
/* AVX-512: Op code 0f 38 c6 (Grp18) */
asm volatile("vgatherpf0dps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vgatherpf0dpd 0x7b(%ebp,%ymm7,8){%k1}");
asm volatile("vgatherpf1dps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vgatherpf1dpd 0x7b(%ebp,%ymm7,8){%k1}");
asm volatile("vscatterpf0dps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterpf0dpd 0x7b(%ebp,%ymm7,8){%k1}");
asm volatile("vscatterpf1dps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterpf1dpd 0x7b(%ebp,%ymm7,8){%k1}");
/* AVX-512: Op code 0f 38 c7 (Grp19) */
asm volatile("vgatherpf0qps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vgatherpf0qpd 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vgatherpf1qps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vgatherpf1qpd 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterpf0qps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterpf0qpd 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterpf1qps 0x7b(%ebp,%zmm7,8){%k1}");
asm volatile("vscatterpf1qpd 0x7b(%ebp,%zmm7,8){%k1}");
/* AVX-512: Examples */
asm volatile("vaddpd %zmm4,%zmm5,%zmm6");
asm volatile("vaddpd %zmm4,%zmm5,%zmm6{%k7}");
asm volatile("vaddpd %zmm4,%zmm5,%zmm6{%k7}{z}");
asm volatile("vaddpd {rn-sae},%zmm4,%zmm5,%zmm6");
asm volatile("vaddpd {ru-sae},%zmm4,%zmm5,%zmm6");
asm volatile("vaddpd {rd-sae},%zmm4,%zmm5,%zmm6");
asm volatile("vaddpd {rz-sae},%zmm4,%zmm5,%zmm6");
asm volatile("vaddpd (%ecx),%zmm5,%zmm6");
asm volatile("vaddpd 0x123(%eax,%ecx,8),%zmm5,%zmm6");
asm volatile("vaddpd (%ecx){1to8},%zmm5,%zmm6");
asm volatile("vaddpd 0x1fc0(%edx),%zmm5,%zmm6");
asm volatile("vaddpd 0x3f8(%edx){1to8},%zmm5,%zmm6");
asm volatile("vcmpeq_uqps 0x1fc(%edx){1to16},%zmm6,%k5");
asm volatile("vcmpltsd 0x123(%eax,%ecx,8),%xmm3,%k5{%k7}");
asm volatile("vcmplesd {sae},%xmm4,%xmm5,%k5{%k7}");
asm volatile("vgetmantss $0x5b,0x123(%eax,%ecx,8),%xmm4,%xmm5{%k7}");
/* bndmk m32, bnd */
asm volatile("bndmk (%eax), %bnd0");
asm volatile("bndmk (0x12345678), %bnd0");
asm volatile("bndmk (%eax), %bnd3");
asm volatile("bndmk (%ecx,%eax,1), %bnd0");
asm volatile("bndmk 0x12345678(,%eax,1), %bnd0");
asm volatile("bndmk (%eax,%ecx,1), %bnd0");
asm volatile("bndmk (%eax,%ecx,8), %bnd0");
asm volatile("bndmk 0x12(%eax), %bnd0");
asm volatile("bndmk 0x12(%ebp), %bnd0");
asm volatile("bndmk 0x12(%ecx,%eax,1), %bnd0");
asm volatile("bndmk 0x12(%ebp,%eax,1), %bnd0");
asm volatile("bndmk 0x12(%eax,%ecx,1), %bnd0");
asm volatile("bndmk 0x12(%eax,%ecx,8), %bnd0");
asm volatile("bndmk 0x12345678(%eax), %bnd0");
asm volatile("bndmk 0x12345678(%ebp), %bnd0");
asm volatile("bndmk 0x12345678(%ecx,%eax,1), %bnd0");
asm volatile("bndmk 0x12345678(%ebp,%eax,1), %bnd0");
asm volatile("bndmk 0x12345678(%eax,%ecx,1), %bnd0");
asm volatile("bndmk 0x12345678(%eax,%ecx,8), %bnd0");
/* bndcl r/m32, bnd */
asm volatile("bndcl (%eax), %bnd0");
asm volatile("bndcl (0x12345678), %bnd0");
asm volatile("bndcl (%eax), %bnd3");
asm volatile("bndcl (%ecx,%eax,1), %bnd0");
asm volatile("bndcl 0x12345678(,%eax,1), %bnd0");
asm volatile("bndcl (%eax,%ecx,1), %bnd0");
asm volatile("bndcl (%eax,%ecx,8), %bnd0");
asm volatile("bndcl 0x12(%eax), %bnd0");
asm volatile("bndcl 0x12(%ebp), %bnd0");
asm volatile("bndcl 0x12(%ecx,%eax,1), %bnd0");
asm volatile("bndcl 0x12(%ebp,%eax,1), %bnd0");
asm volatile("bndcl 0x12(%eax,%ecx,1), %bnd0");
asm volatile("bndcl 0x12(%eax,%ecx,8), %bnd0");
asm volatile("bndcl 0x12345678(%eax), %bnd0");
asm volatile("bndcl 0x12345678(%ebp), %bnd0");
asm volatile("bndcl 0x12345678(%ecx,%eax,1), %bnd0");
asm volatile("bndcl 0x12345678(%ebp,%eax,1), %bnd0");
asm volatile("bndcl 0x12345678(%eax,%ecx,1), %bnd0");
asm volatile("bndcl 0x12345678(%eax,%ecx,8), %bnd0");
asm volatile("bndcl %eax, %bnd0");
/* bndcu r/m32, bnd */
asm volatile("bndcu (%eax), %bnd0");
asm volatile("bndcu (0x12345678), %bnd0");
asm volatile("bndcu (%eax), %bnd3");
asm volatile("bndcu (%ecx,%eax,1), %bnd0");
asm volatile("bndcu 0x12345678(,%eax,1), %bnd0");
asm volatile("bndcu (%eax,%ecx,1), %bnd0");
asm volatile("bndcu (%eax,%ecx,8), %bnd0");
asm volatile("bndcu 0x12(%eax), %bnd0");
asm volatile("bndcu 0x12(%ebp), %bnd0");
asm volatile("bndcu 0x12(%ecx,%eax,1), %bnd0");
asm volatile("bndcu 0x12(%ebp,%eax,1), %bnd0");
asm volatile("bndcu 0x12(%eax,%ecx,1), %bnd0");
asm volatile("bndcu 0x12(%eax,%ecx,8), %bnd0");
asm volatile("bndcu 0x12345678(%eax), %bnd0");
asm volatile("bndcu 0x12345678(%ebp), %bnd0");
asm volatile("bndcu 0x12345678(%ecx,%eax,1), %bnd0");
asm volatile("bndcu 0x12345678(%ebp,%eax,1), %bnd0");
asm volatile("bndcu 0x12345678(%eax,%ecx,1), %bnd0");
asm volatile("bndcu 0x12345678(%eax,%ecx,8), %bnd0");
asm volatile("bndcu %eax, %bnd0");
/* bndcn r/m32, bnd */
asm volatile("bndcn (%eax), %bnd0");
asm volatile("bndcn (0x12345678), %bnd0");
asm volatile("bndcn (%eax), %bnd3");
asm volatile("bndcn (%ecx,%eax,1), %bnd0");
asm volatile("bndcn 0x12345678(,%eax,1), %bnd0");
asm volatile("bndcn (%eax,%ecx,1), %bnd0");
asm volatile("bndcn (%eax,%ecx,8), %bnd0");
asm volatile("bndcn 0x12(%eax), %bnd0");
asm volatile("bndcn 0x12(%ebp), %bnd0");
asm volatile("bndcn 0x12(%ecx,%eax,1), %bnd0");
asm volatile("bndcn 0x12(%ebp,%eax,1), %bnd0");
asm volatile("bndcn 0x12(%eax,%ecx,1), %bnd0");
asm volatile("bndcn 0x12(%eax,%ecx,8), %bnd0");
asm volatile("bndcn 0x12345678(%eax), %bnd0");
asm volatile("bndcn 0x12345678(%ebp), %bnd0");
asm volatile("bndcn 0x12345678(%ecx,%eax,1), %bnd0");
asm volatile("bndcn 0x12345678(%ebp,%eax,1), %bnd0");
asm volatile("bndcn 0x12345678(%eax,%ecx,1), %bnd0");
asm volatile("bndcn 0x12345678(%eax,%ecx,8), %bnd0");
asm volatile("bndcn %eax, %bnd0");
/* bndmov m64, bnd */
asm volatile("bndmov (%eax), %bnd0");
asm volatile("bndmov (0x12345678), %bnd0");
asm volatile("bndmov (%eax), %bnd3");
asm volatile("bndmov (%ecx,%eax,1), %bnd0");
asm volatile("bndmov 0x12345678(,%eax,1), %bnd0");
asm volatile("bndmov (%eax,%ecx,1), %bnd0");
asm volatile("bndmov (%eax,%ecx,8), %bnd0");
asm volatile("bndmov 0x12(%eax), %bnd0");
asm volatile("bndmov 0x12(%ebp), %bnd0");
asm volatile("bndmov 0x12(%ecx,%eax,1), %bnd0");
asm volatile("bndmov 0x12(%ebp,%eax,1), %bnd0");
asm volatile("bndmov 0x12(%eax,%ecx,1), %bnd0");
asm volatile("bndmov 0x12(%eax,%ecx,8), %bnd0");
asm volatile("bndmov 0x12345678(%eax), %bnd0");
asm volatile("bndmov 0x12345678(%ebp), %bnd0");
asm volatile("bndmov 0x12345678(%ecx,%eax,1), %bnd0");
asm volatile("bndmov 0x12345678(%ebp,%eax,1), %bnd0");
asm volatile("bndmov 0x12345678(%eax,%ecx,1), %bnd0");
asm volatile("bndmov 0x12345678(%eax,%ecx,8), %bnd0");
/* bndmov bnd, m64 */
asm volatile("bndmov %bnd0, (%eax)");
asm volatile("bndmov %bnd0, (0x12345678)");
asm volatile("bndmov %bnd3, (%eax)");
asm volatile("bndmov %bnd0, (%ecx,%eax,1)");
asm volatile("bndmov %bnd0, 0x12345678(,%eax,1)");
asm volatile("bndmov %bnd0, (%eax,%ecx,1)");
asm volatile("bndmov %bnd0, (%eax,%ecx,8)");
asm volatile("bndmov %bnd0, 0x12(%eax)");
asm volatile("bndmov %bnd0, 0x12(%ebp)");
asm volatile("bndmov %bnd0, 0x12(%ecx,%eax,1)");
asm volatile("bndmov %bnd0, 0x12(%ebp,%eax,1)");
asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,1)");
asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,8)");
asm volatile("bndmov %bnd0, 0x12345678(%eax)");
asm volatile("bndmov %bnd0, 0x12345678(%ebp)");
asm volatile("bndmov %bnd0, 0x12345678(%ecx,%eax,1)");
asm volatile("bndmov %bnd0, 0x12345678(%ebp,%eax,1)");
asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,1)");
asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,8)");
/* bndmov bnd2, bnd1 */
asm volatile("bndmov %bnd0, %bnd1");
asm volatile("bndmov %bnd1, %bnd0");
/* bndldx mib, bnd */
asm volatile("bndldx (%eax), %bnd0");
asm volatile("bndldx (0x12345678), %bnd0");
asm volatile("bndldx (%eax), %bnd3");
asm volatile("bndldx (%ecx,%eax,1), %bnd0");
asm volatile("bndldx 0x12345678(,%eax,1), %bnd0");
asm volatile("bndldx (%eax,%ecx,1), %bnd0");
asm volatile("bndldx 0x12(%eax), %bnd0");
asm volatile("bndldx 0x12(%ebp), %bnd0");
asm volatile("bndldx 0x12(%ecx,%eax,1), %bnd0");
asm volatile("bndldx 0x12(%ebp,%eax,1), %bnd0");
asm volatile("bndldx 0x12(%eax,%ecx,1), %bnd0");
asm volatile("bndldx 0x12345678(%eax), %bnd0");
asm volatile("bndldx 0x12345678(%ebp), %bnd0");
asm volatile("bndldx 0x12345678(%ecx,%eax,1), %bnd0");
asm volatile("bndldx 0x12345678(%ebp,%eax,1), %bnd0");
asm volatile("bndldx 0x12345678(%eax,%ecx,1), %bnd0");
/* bndstx bnd, mib */
asm volatile("bndstx %bnd0, (%eax)");
asm volatile("bndstx %bnd0, (0x12345678)");
asm volatile("bndstx %bnd3, (%eax)");
asm volatile("bndstx %bnd0, (%ecx,%eax,1)");
asm volatile("bndstx %bnd0, 0x12345678(,%eax,1)");
asm volatile("bndstx %bnd0, (%eax,%ecx,1)");
asm volatile("bndstx %bnd0, 0x12(%eax)");
asm volatile("bndstx %bnd0, 0x12(%ebp)");
asm volatile("bndstx %bnd0, 0x12(%ecx,%eax,1)");
asm volatile("bndstx %bnd0, 0x12(%ebp,%eax,1)");
asm volatile("bndstx %bnd0, 0x12(%eax,%ecx,1)");
asm volatile("bndstx %bnd0, 0x12345678(%eax)");
asm volatile("bndstx %bnd0, 0x12345678(%ebp)");
asm volatile("bndstx %bnd0, 0x12345678(%ecx,%eax,1)");
asm volatile("bndstx %bnd0, 0x12345678(%ebp,%eax,1)");
asm volatile("bndstx %bnd0, 0x12345678(%eax,%ecx,1)");
/* bnd prefix on call, ret, jmp and all jcc */
asm volatile("bnd call label1"); /* Expecting: call unconditional 0xfffffffc */
asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
asm volatile("bnd ret"); /* Expecting: ret indirect 0 */
asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */
asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */
asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0xfffffffc */
/* sha1rnds4 imm8, xmm2/m128, xmm1 */
asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0");
asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2");
asm volatile("sha1rnds4 $0x91, (%eax), %xmm0");
asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0");
asm volatile("sha1rnds4 $0x91, (%eax), %xmm3");
asm volatile("sha1rnds4 $0x91, (%ecx,%eax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(,%eax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, (%eax,%ecx,1), %xmm0");
asm volatile("sha1rnds4 $0x91, (%eax,%ecx,8), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%eax), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%ebp), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%ecx,%eax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%ebp,%eax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,8), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%eax), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%ecx,%eax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp,%eax,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,1), %xmm0");
asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,8), %xmm0");
/* sha1nexte xmm2/m128, xmm1 */
asm volatile("sha1nexte %xmm1, %xmm0");
asm volatile("sha1nexte %xmm7, %xmm2");
asm volatile("sha1nexte (%eax), %xmm0");
asm volatile("sha1nexte (0x12345678), %xmm0");
asm volatile("sha1nexte (%eax), %xmm3");
asm volatile("sha1nexte (%ecx,%eax,1), %xmm0");
asm volatile("sha1nexte 0x12345678(,%eax,1), %xmm0");
asm volatile("sha1nexte (%eax,%ecx,1), %xmm0");
asm volatile("sha1nexte (%eax,%ecx,8), %xmm0");
asm volatile("sha1nexte 0x12(%eax), %xmm0");
asm volatile("sha1nexte 0x12(%ebp), %xmm0");
asm volatile("sha1nexte 0x12(%ecx,%eax,1), %xmm0");
asm volatile("sha1nexte 0x12(%ebp,%eax,1), %xmm0");
asm volatile("sha1nexte 0x12(%eax,%ecx,1), %xmm0");
asm volatile("sha1nexte 0x12(%eax,%ecx,8), %xmm0");
asm volatile("sha1nexte 0x12345678(%eax), %xmm0");
asm volatile("sha1nexte 0x12345678(%ebp), %xmm0");
asm volatile("sha1nexte 0x12345678(%ecx,%eax,1), %xmm0");
asm volatile("sha1nexte 0x12345678(%ebp,%eax,1), %xmm0");
asm volatile("sha1nexte 0x12345678(%eax,%ecx,1), %xmm0");
asm volatile("sha1nexte 0x12345678(%eax,%ecx,8), %xmm0");
/* sha1msg1 xmm2/m128, xmm1 */
asm volatile("sha1msg1 %xmm1, %xmm0");
asm volatile("sha1msg1 %xmm7, %xmm2");
asm volatile("sha1msg1 (%eax), %xmm0");
asm volatile("sha1msg1 (0x12345678), %xmm0");
asm volatile("sha1msg1 (%eax), %xmm3");
asm volatile("sha1msg1 (%ecx,%eax,1), %xmm0");
asm volatile("sha1msg1 0x12345678(,%eax,1), %xmm0");
asm volatile("sha1msg1 (%eax,%ecx,1), %xmm0");
asm volatile("sha1msg1 (%eax,%ecx,8), %xmm0");
asm volatile("sha1msg1 0x12(%eax), %xmm0");
asm volatile("sha1msg1 0x12(%ebp), %xmm0");
asm volatile("sha1msg1 0x12(%ecx,%eax,1), %xmm0");
asm volatile("sha1msg1 0x12(%ebp,%eax,1), %xmm0");
asm volatile("sha1msg1 0x12(%eax,%ecx,1), %xmm0");
asm volatile("sha1msg1 0x12(%eax,%ecx,8), %xmm0");
asm volatile("sha1msg1 0x12345678(%eax), %xmm0");
asm volatile("sha1msg1 0x12345678(%ebp), %xmm0");
asm volatile("sha1msg1 0x12345678(%ecx,%eax,1), %xmm0");
asm volatile("sha1msg1 0x12345678(%ebp,%eax,1), %xmm0");
asm volatile("sha1msg1 0x12345678(%eax,%ecx,1), %xmm0");
asm volatile("sha1msg1 0x12345678(%eax,%ecx,8), %xmm0");
/* sha1msg2 xmm2/m128, xmm1 */
asm volatile("sha1msg2 %xmm1, %xmm0");
asm volatile("sha1msg2 %xmm7, %xmm2");
asm volatile("sha1msg2 (%eax), %xmm0");
asm volatile("sha1msg2 (0x12345678), %xmm0");
asm volatile("sha1msg2 (%eax), %xmm3");
asm volatile("sha1msg2 (%ecx,%eax,1), %xmm0");
asm volatile("sha1msg2 0x12345678(,%eax,1), %xmm0");
asm volatile("sha1msg2 (%eax,%ecx,1), %xmm0");
asm volatile("sha1msg2 (%eax,%ecx,8), %xmm0");
asm volatile("sha1msg2 0x12(%eax), %xmm0");
asm volatile("sha1msg2 0x12(%ebp), %xmm0");
asm volatile("sha1msg2 0x12(%ecx,%eax,1), %xmm0");
asm volatile("sha1msg2 0x12(%ebp,%eax,1), %xmm0");
asm volatile("sha1msg2 0x12(%eax,%ecx,1), %xmm0");
asm volatile("sha1msg2 0x12(%eax,%ecx,8), %xmm0");
asm volatile("sha1msg2 0x12345678(%eax), %xmm0");
asm volatile("sha1msg2 0x12345678(%ebp), %xmm0");
asm volatile("sha1msg2 0x12345678(%ecx,%eax,1), %xmm0");
asm volatile("sha1msg2 0x12345678(%ebp,%eax,1), %xmm0");
asm volatile("sha1msg2 0x12345678(%eax,%ecx,1), %xmm0");
asm volatile("sha1msg2 0x12345678(%eax,%ecx,8), %xmm0");
/* sha256rnds2 <XMM0>, xmm2/m128, xmm1 */
/* Note sha256rnds2 has an implicit operand 'xmm0' */
asm volatile("sha256rnds2 %xmm4, %xmm1");
asm volatile("sha256rnds2 %xmm7, %xmm2");
asm volatile("sha256rnds2 (%eax), %xmm1");
asm volatile("sha256rnds2 (0x12345678), %xmm1");
asm volatile("sha256rnds2 (%eax), %xmm3");
asm volatile("sha256rnds2 (%ecx,%eax,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(,%eax,1), %xmm1");
asm volatile("sha256rnds2 (%eax,%ecx,1), %xmm1");
asm volatile("sha256rnds2 (%eax,%ecx,8), %xmm1");
asm volatile("sha256rnds2 0x12(%eax), %xmm1");
asm volatile("sha256rnds2 0x12(%ebp), %xmm1");
asm volatile("sha256rnds2 0x12(%ecx,%eax,1), %xmm1");
asm volatile("sha256rnds2 0x12(%ebp,%eax,1), %xmm1");
asm volatile("sha256rnds2 0x12(%eax,%ecx,1), %xmm1");
asm volatile("sha256rnds2 0x12(%eax,%ecx,8), %xmm1");
asm volatile("sha256rnds2 0x12345678(%eax), %xmm1");
asm volatile("sha256rnds2 0x12345678(%ebp), %xmm1");
asm volatile("sha256rnds2 0x12345678(%ecx,%eax,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(%ebp,%eax,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(%eax,%ecx,1), %xmm1");
asm volatile("sha256rnds2 0x12345678(%eax,%ecx,8), %xmm1");
/* sha256msg1 xmm2/m128, xmm1 */
asm volatile("sha256msg1 %xmm1, %xmm0");
asm volatile("sha256msg1 %xmm7, %xmm2");
asm volatile("sha256msg1 (%eax), %xmm0");
asm volatile("sha256msg1 (0x12345678), %xmm0");
asm volatile("sha256msg1 (%eax), %xmm3");
asm volatile("sha256msg1 (%ecx,%eax,1), %xmm0");
asm volatile("sha256msg1 0x12345678(,%eax,1), %xmm0");
asm volatile("sha256msg1 (%eax,%ecx,1), %xmm0");
asm volatile("sha256msg1 (%eax,%ecx,8), %xmm0");
asm volatile("sha256msg1 0x12(%eax), %xmm0");
asm volatile("sha256msg1 0x12(%ebp), %xmm0");
asm volatile("sha256msg1 0x12(%ecx,%eax,1), %xmm0");
asm volatile("sha256msg1 0x12(%ebp,%eax,1), %xmm0");
asm volatile("sha256msg1 0x12(%eax,%ecx,1), %xmm0");
asm volatile("sha256msg1 0x12(%eax,%ecx,8), %xmm0");
asm volatile("sha256msg1 0x12345678(%eax), %xmm0");
asm volatile("sha256msg1 0x12345678(%ebp), %xmm0");
asm volatile("sha256msg1 0x12345678(%ecx,%eax,1), %xmm0");
asm volatile("sha256msg1 0x12345678(%ebp,%eax,1), %xmm0");
asm volatile("sha256msg1 0x12345678(%eax,%ecx,1), %xmm0");
asm volatile("sha256msg1 0x12345678(%eax,%ecx,8), %xmm0");
/* sha256msg2 xmm2/m128, xmm1 */
asm volatile("sha256msg2 %xmm1, %xmm0");
asm volatile("sha256msg2 %xmm7, %xmm2");
asm volatile("sha256msg2 (%eax), %xmm0");
asm volatile("sha256msg2 (0x12345678), %xmm0");
asm volatile("sha256msg2 (%eax), %xmm3");
asm volatile("sha256msg2 (%ecx,%eax,1), %xmm0");
asm volatile("sha256msg2 0x12345678(,%eax,1), %xmm0");
asm volatile("sha256msg2 (%eax,%ecx,1), %xmm0");
asm volatile("sha256msg2 (%eax,%ecx,8), %xmm0");
asm volatile("sha256msg2 0x12(%eax), %xmm0");
asm volatile("sha256msg2 0x12(%ebp), %xmm0");
asm volatile("sha256msg2 0x12(%ecx,%eax,1), %xmm0");
asm volatile("sha256msg2 0x12(%ebp,%eax,1), %xmm0");
asm volatile("sha256msg2 0x12(%eax,%ecx,1), %xmm0");
asm volatile("sha256msg2 0x12(%eax,%ecx,8), %xmm0");
asm volatile("sha256msg2 0x12345678(%eax), %xmm0");
asm volatile("sha256msg2 0x12345678(%ebp), %xmm0");
asm volatile("sha256msg2 0x12345678(%ecx,%eax,1), %xmm0");
asm volatile("sha256msg2 0x12345678(%ebp,%eax,1), %xmm0");
asm volatile("sha256msg2 0x12345678(%eax,%ecx,1), %xmm0");
asm volatile("sha256msg2 0x12345678(%eax,%ecx,8), %xmm0");
/* clflushopt m8 */
asm volatile("clflushopt (%eax)");
asm volatile("clflushopt (0x12345678)");
asm volatile("clflushopt 0x12345678(%eax,%ecx,8)");
/* Also check instructions in the same group encoding as clflushopt */
asm volatile("clflush (%eax)");
asm volatile("sfence");
/* clwb m8 */
asm volatile("clwb (%eax)");
asm volatile("clwb (0x12345678)");
asm volatile("clwb 0x12345678(%eax,%ecx,8)");
/* Also check instructions in the same group encoding as clwb */
asm volatile("xsaveopt (%eax)");
asm volatile("mfence");
/* cldemote m8 */
asm volatile("cldemote (%eax)");
asm volatile("cldemote (0x12345678)");
asm volatile("cldemote 0x12345678(%eax,%ecx,8)");
/* xsavec mem */
asm volatile("xsavec (%eax)");
asm volatile("xsavec (0x12345678)");
asm volatile("xsavec 0x12345678(%eax,%ecx,8)");
/* xsaves mem */
asm volatile("xsaves (%eax)");
asm volatile("xsaves (0x12345678)");
asm volatile("xsaves 0x12345678(%eax,%ecx,8)");
/* xrstors mem */
asm volatile("xrstors (%eax)");
asm volatile("xrstors (0x12345678)");
asm volatile("xrstors 0x12345678(%eax,%ecx,8)");
/* ptwrite */
asm volatile("ptwrite (%eax)");
asm volatile("ptwrite (0x12345678)");
asm volatile("ptwrite 0x12345678(%eax,%ecx,8)");
asm volatile("ptwritel (%eax)");
asm volatile("ptwritel (0x12345678)");
asm volatile("ptwritel 0x12345678(%eax,%ecx,8)");
/* tpause */
asm volatile("tpause %ebx");
/* umonitor */
asm volatile("umonitor %ax");
asm volatile("umonitor %eax");
/* umwait */
asm volatile("umwait %eax");
/* movdiri */
asm volatile("movdiri %eax,(%ebx)");
asm volatile("movdiri %ecx,0x12345678(%eax)");
/* movdir64b */
asm volatile("movdir64b (%eax),%ebx");
asm volatile("movdir64b 0x12345678(%eax),%ecx");
asm volatile("movdir64b (%si),%bx");
asm volatile("movdir64b 0x1234(%si),%cx");
/* enqcmd */
asm volatile("enqcmd (%eax),%ebx");
asm volatile("enqcmd 0x12345678(%eax),%ecx");
asm volatile("enqcmd (%si),%bx");
asm volatile("enqcmd 0x1234(%si),%cx");
/* enqcmds */
asm volatile("enqcmds (%eax),%ebx");
asm volatile("enqcmds 0x12345678(%eax),%ecx");
asm volatile("enqcmds (%si),%bx");
asm volatile("enqcmds 0x1234(%si),%cx");
/* incsspd */
asm volatile("incsspd %eax");
/* Also check instructions in the same group encoding as incsspd */
asm volatile("xrstor (%eax)");
asm volatile("xrstor (0x12345678)");
asm volatile("xrstor 0x12345678(%eax,%ecx,8)");
asm volatile("lfence");
/* rdsspd */
asm volatile("rdsspd %eax");
/* saveprevssp */
asm volatile("saveprevssp");
/* rstorssp */
asm volatile("rstorssp (%eax)");
asm volatile("rstorssp (0x12345678)");
asm volatile("rstorssp 0x12345678(%eax,%ecx,8)");
/* wrssd */
asm volatile("wrssd %ecx,(%eax)");
asm volatile("wrssd %edx,(0x12345678)");
asm volatile("wrssd %edx,0x12345678(%eax,%ecx,8)");
/* wrussd */
asm volatile("wrussd %ecx,(%eax)");
asm volatile("wrussd %edx,(0x12345678)");
asm volatile("wrussd %edx,0x12345678(%eax,%ecx,8)");
/* setssbsy */
asm volatile("setssbsy");
/* Also check instructions in the same group encoding as setssbsy */
asm volatile("rdpkru");
asm volatile("wrpkru");
/* clrssbsy */
asm volatile("clrssbsy (%eax)");
asm volatile("clrssbsy (0x12345678)");
asm volatile("clrssbsy 0x12345678(%eax,%ecx,8)");
/* endbr32/64 */
asm volatile("endbr32");
asm volatile("endbr64");
/* call with/without notrack prefix */
asm volatile("call *%eax"); /* Expecting: call indirect 0 */
asm volatile("call *(%eax)"); /* Expecting: call indirect 0 */
asm volatile("call *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("call *0x12345678(%eax,%ecx,8)"); /* Expecting: call indirect 0 */
asm volatile("bnd call *%eax"); /* Expecting: call indirect 0 */
asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
asm volatile("bnd call *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("bnd call *0x12345678(%eax,%ecx,8)"); /* Expecting: call indirect 0 */
asm volatile("notrack call *%eax"); /* Expecting: call indirect 0 */
asm volatile("notrack call *(%eax)"); /* Expecting: call indirect 0 */
asm volatile("notrack call *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("notrack call *0x12345678(%eax,%ecx,8)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd call *%eax"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd call *(%eax)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd call *(0x12345678)"); /* Expecting: call indirect 0 */
asm volatile("notrack bnd call *0x12345678(%eax,%ecx,8)"); /* Expecting: call indirect 0 */
/* jmp with/without notrack prefix */
asm volatile("jmp *%eax"); /* Expecting: jmp indirect 0 */
asm volatile("jmp *(%eax)"); /* Expecting: jmp indirect 0 */
asm volatile("jmp *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("jmp *0x12345678(%eax,%ecx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmp *%eax"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmp *(%eax)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmp *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("bnd jmp *0x12345678(%eax,%ecx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmp *%eax"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmp *(%eax)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmp *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack jmp *0x12345678(%eax,%ecx,8)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmp *%eax"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmp *(%eax)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmp *(0x12345678)"); /* Expecting: jmp indirect 0 */
asm volatile("notrack bnd jmp *0x12345678(%eax,%ecx,8)"); /* Expecting: jmp indirect 0 */
/* AVX512-FP16 */
asm volatile("vaddph %zmm3, %zmm2, %zmm1");
asm volatile("vaddph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vaddph %xmm3, %xmm2, %xmm1");
asm volatile("vaddph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vaddph %ymm3, %ymm2, %ymm1");
asm volatile("vaddph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vaddsh %xmm3, %xmm2, %xmm1");
asm volatile("vaddsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcmpph $0x12, %zmm3, %zmm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%eax,%ecx,8), %zmm2, %k5");
asm volatile("vcmpph $0x12, %xmm3, %xmm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %k5");
asm volatile("vcmpph $0x12, %ymm3, %ymm2, %k5");
asm volatile("vcmpph $0x12, 0x12345678(%eax,%ecx,8), %ymm2, %k5");
asm volatile("vcmpsh $0x12, %xmm3, %xmm2, %k5");
asm volatile("vcmpsh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %k5");
asm volatile("vcomish %xmm2, %xmm1");
asm volatile("vcomish 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtdq2ph %zmm2, %ymm1");
asm volatile("vcvtdq2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtdq2ph %xmm2, %xmm1");
asm volatile("vcvtdq2ph %ymm2, %xmm1");
asm volatile("vcvtpd2ph %zmm2, %xmm1");
asm volatile("vcvtpd2ph %xmm2, %xmm1");
asm volatile("vcvtpd2ph %ymm2, %xmm1");
asm volatile("vcvtph2dq %ymm2, %zmm1");
asm volatile("vcvtph2dq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2dq %xmm2, %xmm1");
asm volatile("vcvtph2dq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2dq %xmm2, %ymm1");
asm volatile("vcvtph2dq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2pd %xmm2, %zmm1");
asm volatile("vcvtph2pd 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2pd %xmm2, %xmm1");
asm volatile("vcvtph2pd 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2pd %xmm2, %ymm1");
asm volatile("vcvtph2pd 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2ps %ymm2, %zmm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2ps %xmm2, %xmm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2ps %xmm2, %ymm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2ps %xmm2, %xmm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2ps %xmm2, %ymm1");
asm volatile("vcvtph2ps 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2psx %ymm2, %zmm1");
asm volatile("vcvtph2psx 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2psx %xmm2, %xmm1");
asm volatile("vcvtph2psx 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2psx %xmm2, %ymm1");
asm volatile("vcvtph2psx 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2qq %xmm2, %zmm1");
asm volatile("vcvtph2qq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2qq %xmm2, %xmm1");
asm volatile("vcvtph2qq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2qq %xmm2, %ymm1");
asm volatile("vcvtph2qq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2udq %ymm2, %zmm1");
asm volatile("vcvtph2udq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2udq %xmm2, %xmm1");
asm volatile("vcvtph2udq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2udq %xmm2, %ymm1");
asm volatile("vcvtph2udq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2uqq %xmm2, %zmm1");
asm volatile("vcvtph2uqq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2uqq %xmm2, %xmm1");
asm volatile("vcvtph2uqq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2uqq %xmm2, %ymm1");
asm volatile("vcvtph2uqq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2uw %zmm2, %zmm1");
asm volatile("vcvtph2uw 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2uw %xmm2, %xmm1");
asm volatile("vcvtph2uw 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2uw %ymm2, %ymm1");
asm volatile("vcvtph2uw 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtph2w %zmm2, %zmm1");
asm volatile("vcvtph2w 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtph2w %xmm2, %xmm1");
asm volatile("vcvtph2w 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtph2w %ymm2, %ymm1");
asm volatile("vcvtph2w 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtps2ph $0x12, %zmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %zmm2, %ymm1");
asm volatile("vcvtps2ph $0x12, %ymm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %xmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %xmm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %ymm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %ymm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %ymm2, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2ph $0x12, %xmm2, %xmm1");
asm volatile("vcvtps2ph $0x12, %xmm2, 0x12345678(%eax,%ecx,8)");
asm volatile("vcvtps2phx %zmm2, %ymm1");
asm volatile("vcvtps2phx 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtps2phx %xmm2, %xmm1");
asm volatile("vcvtps2phx %ymm2, %xmm1");
asm volatile("vcvtqq2ph %zmm2, %xmm1");
asm volatile("vcvtqq2ph %xmm2, %xmm1");
asm volatile("vcvtqq2ph %ymm2, %xmm1");
asm volatile("vcvtsd2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsh2sd 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsh2si 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvtsh2ss 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsh2usi %xmm1, %eax");
asm volatile("vcvtsh2usi 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvtsi2sh %eax, %xmm2, %xmm1");
asm volatile("vcvtsi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtsi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtss2sh %xmm3, %xmm2, %xmm1");
asm volatile("vcvtss2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvttph2dq %ymm2, %zmm1");
asm volatile("vcvttph2dq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2dq %xmm2, %xmm1");
asm volatile("vcvttph2dq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2dq %xmm2, %ymm1");
asm volatile("vcvttph2dq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2qq %xmm2, %zmm1");
asm volatile("vcvttph2qq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2qq %xmm2, %xmm1");
asm volatile("vcvttph2qq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2qq %xmm2, %ymm1");
asm volatile("vcvttph2qq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2udq %ymm2, %zmm1");
asm volatile("vcvttph2udq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2udq %xmm2, %xmm1");
asm volatile("vcvttph2udq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2udq %xmm2, %ymm1");
asm volatile("vcvttph2udq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2uqq %xmm2, %zmm1");
asm volatile("vcvttph2uqq 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2uqq %xmm2, %xmm1");
asm volatile("vcvttph2uqq 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2uqq %xmm2, %ymm1");
asm volatile("vcvttph2uqq 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2uw %zmm2, %zmm1");
asm volatile("vcvttph2uw 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2uw %xmm2, %xmm1");
asm volatile("vcvttph2uw 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2uw %ymm2, %ymm1");
asm volatile("vcvttph2uw 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttph2w %zmm2, %zmm1");
asm volatile("vcvttph2w 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvttph2w %xmm2, %xmm1");
asm volatile("vcvttph2w 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvttph2w %ymm2, %ymm1");
asm volatile("vcvttph2w 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvttsh2si %xmm1, %eax");
asm volatile("vcvttsh2si 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvttsh2usi %xmm1, %eax");
asm volatile("vcvttsh2usi 0x12345678(%eax,%ecx,8), %eax");
asm volatile("vcvtudq2ph %zmm2, %ymm1");
asm volatile("vcvtudq2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtudq2ph %xmm2, %xmm1");
asm volatile("vcvtudq2ph %ymm2, %xmm1");
asm volatile("vcvtuqq2ph %zmm2, %xmm1");
asm volatile("vcvtuqq2ph %xmm2, %xmm1");
asm volatile("vcvtuqq2ph %ymm2, %xmm1");
asm volatile("vcvtusi2sh %eax, %xmm2, %xmm1");
asm volatile("vcvtusi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtusi2sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vcvtuw2ph %zmm2, %zmm1");
asm volatile("vcvtuw2ph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtuw2ph %xmm2, %xmm1");
asm volatile("vcvtuw2ph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtuw2ph %ymm2, %ymm1");
asm volatile("vcvtuw2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vcvtw2ph %zmm2, %zmm1");
asm volatile("vcvtw2ph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vcvtw2ph %xmm2, %xmm1");
asm volatile("vcvtw2ph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vcvtw2ph %ymm2, %ymm1");
asm volatile("vcvtw2ph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vdivph %zmm3, %zmm2, %zmm1");
asm volatile("vdivph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vdivph %xmm3, %xmm2, %xmm1");
asm volatile("vdivph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vdivph %ymm3, %ymm2, %ymm1");
asm volatile("vdivph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vdivsh %xmm3, %xmm2, %xmm1");
asm volatile("vdivsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmaddcph %zmm3, %zmm2, %zmm1");
asm volatile("vfcmaddcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfcmaddcph %xmm3, %xmm2, %xmm1");
asm volatile("vfcmaddcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmaddcph %ymm3, %ymm2, %ymm1");
asm volatile("vfcmaddcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfcmaddcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfcmaddcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmulcph %zmm3, %zmm2, %zmm1");
asm volatile("vfcmulcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfcmulcph %xmm3, %xmm2, %xmm1");
asm volatile("vfcmulcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfcmulcph %ymm3, %ymm2, %ymm1");
asm volatile("vfcmulcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfcmulcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfcmulcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmadd132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmadd132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmadd132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmadd132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmadd213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmadd213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmadd213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmadd213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmadd231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmadd231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmadd231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmadd231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmadd231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmadd231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddcph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddcph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddcph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmaddcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddsub132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddsub132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddsub132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddsub213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddsub213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddsub213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmaddsub231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmaddsub231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmaddsub231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmaddsub231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmaddsub231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmaddsub231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsub132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsub132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsub132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsub213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsub213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsub213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsub231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsub231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsub231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsub231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsub231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfmsub231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsubadd132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsubadd132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsubadd132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsubadd213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsubadd213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsubadd213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmsubadd231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfmsubadd231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmsubadd231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfmsubadd231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmsubadd231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfmsubadd231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmulcph %zmm3, %zmm2, %zmm1");
asm volatile("vfmulcph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfmulcph %xmm3, %xmm2, %xmm1");
asm volatile("vfmulcph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfmulcph %ymm3, %ymm2, %ymm1");
asm volatile("vfmulcph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfmulcsh %xmm3, %xmm2, %xmm1");
asm volatile("vfmulcsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmadd132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmadd132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmadd132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmadd132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmadd213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmadd213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmadd213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmadd213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmadd231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmadd231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmadd231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmadd231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmadd231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmadd231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub132ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmsub132ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmsub132ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub132ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub132ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmsub132ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmsub132sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub132sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub213ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmsub213ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmsub213ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub213ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub213ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmsub213ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmsub213sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub213sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub231ph %zmm3, %zmm2, %zmm1");
asm volatile("vfnmsub231ph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vfnmsub231ph %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub231ph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfnmsub231ph %ymm3, %ymm2, %ymm1");
asm volatile("vfnmsub231ph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vfnmsub231sh %xmm3, %xmm2, %xmm1");
asm volatile("vfnmsub231sh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vfpclassph $0x12, %zmm1, %k5");
asm volatile("vfpclassph $0x12, %xmm1, %k5");
asm volatile("vfpclassph $0x12, %ymm1, %k5");
asm volatile("vfpclasssh $0x12, %xmm1, %k5");
asm volatile("vfpclasssh $0x12, 0x12345678(%eax,%ecx,8), %k5");
asm volatile("vgetexpph %zmm2, %zmm1");
asm volatile("vgetexpph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vgetexpph %xmm2, %xmm1");
asm volatile("vgetexpph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vgetexpph %ymm2, %ymm1");
asm volatile("vgetexpph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vgetexpsh %xmm3, %xmm2, %xmm1");
asm volatile("vgetexpsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vgetmantph $0x12, %zmm2, %zmm1");
asm volatile("vgetmantph $0x12, 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vgetmantph $0x12, %xmm2, %xmm1");
asm volatile("vgetmantph $0x12, 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vgetmantph $0x12, %ymm2, %ymm1");
asm volatile("vgetmantph $0x12, 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vgetmantsh $0x12, %xmm3, %xmm2, %xmm1");
asm volatile("vgetmantsh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmaxph %zmm3, %zmm2, %zmm1");
asm volatile("vmaxph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vmaxph %xmm3, %xmm2, %xmm1");
asm volatile("vmaxph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmaxph %ymm3, %ymm2, %ymm1");
asm volatile("vmaxph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vmaxsh %xmm3, %xmm2, %xmm1");
asm volatile("vmaxsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vminph %zmm3, %zmm2, %zmm1");
asm volatile("vminph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vminph %xmm3, %xmm2, %xmm1");
asm volatile("vminph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vminph %ymm3, %ymm2, %ymm1");
asm volatile("vminph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vminsh %xmm3, %xmm2, %xmm1");
asm volatile("vminsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmovsh %xmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vmovsh 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vmovsh %xmm3, %xmm2, %xmm1");
asm volatile("vmovw %xmm1, %eax");
asm volatile("vmovw %xmm1, 0x12345678(%eax,%ecx,8)");
asm volatile("vmovw %eax, %xmm1");
asm volatile("vmovw 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vmulph %zmm3, %zmm2, %zmm1");
asm volatile("vmulph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vmulph %xmm3, %xmm2, %xmm1");
asm volatile("vmulph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vmulph %ymm3, %ymm2, %ymm1");
asm volatile("vmulph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vmulsh %xmm3, %xmm2, %xmm1");
asm volatile("vmulsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vrcpph %zmm2, %zmm1");
asm volatile("vrcpph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vrcpph %xmm2, %xmm1");
asm volatile("vrcpph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vrcpph %ymm2, %ymm1");
asm volatile("vrcpph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vrcpsh %xmm3, %xmm2, %xmm1");
asm volatile("vrcpsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vreduceph $0x12, %zmm2, %zmm1");
asm volatile("vreduceph $0x12, 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vreduceph $0x12, %xmm2, %xmm1");
asm volatile("vreduceph $0x12, 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vreduceph $0x12, %ymm2, %ymm1");
asm volatile("vreduceph $0x12, 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vreducesh $0x12, %xmm3, %xmm2, %xmm1");
asm volatile("vreducesh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vrndscaleph $0x12, %zmm2, %zmm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vrndscaleph $0x12, %xmm2, %xmm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vrndscaleph $0x12, %ymm2, %ymm1");
asm volatile("vrndscaleph $0x12, 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vrndscalesh $0x12, %xmm3, %xmm2, %xmm1");
asm volatile("vrndscalesh $0x12, 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vrsqrtph %zmm2, %zmm1");
asm volatile("vrsqrtph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vrsqrtph %xmm2, %xmm1");
asm volatile("vrsqrtph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vrsqrtph %ymm2, %ymm1");
asm volatile("vrsqrtph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vrsqrtsh %xmm3, %xmm2, %xmm1");
asm volatile("vrsqrtsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vscalefph %zmm3, %zmm2, %zmm1");
asm volatile("vscalefph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vscalefph %xmm3, %xmm2, %xmm1");
asm volatile("vscalefph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vscalefph %ymm3, %ymm2, %ymm1");
asm volatile("vscalefph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vscalefsh %xmm3, %xmm2, %xmm1");
asm volatile("vscalefsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vsqrtph %zmm2, %zmm1");
asm volatile("vsqrtph 0x12345678(%eax,%ecx,8), %zmm1");
asm volatile("vsqrtph %xmm2, %xmm1");
asm volatile("vsqrtph 0x12345678(%eax,%ecx,8), %xmm1");
asm volatile("vsqrtph %ymm2, %ymm1");
asm volatile("vsqrtph 0x12345678(%eax,%ecx,8), %ymm1");
asm volatile("vsqrtsh %xmm3, %xmm2, %xmm1");
asm volatile("vsqrtsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vsubph %zmm3, %zmm2, %zmm1");
asm volatile("vsubph 0x12345678(%eax,%ecx,8), %zmm2, %zmm1");
asm volatile("vsubph %xmm3, %xmm2, %xmm1");
asm volatile("vsubph 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vsubph %ymm3, %ymm2, %ymm1");
asm volatile("vsubph 0x12345678(%eax,%ecx,8), %ymm2, %ymm1");
asm volatile("vsubsh %xmm3, %xmm2, %xmm1");
asm volatile("vsubsh 0x12345678(%eax,%ecx,8), %xmm2, %xmm1");
asm volatile("vucomish %xmm2, %xmm1");
asm volatile("vucomish 0x12345678(%eax,%ecx,8), %xmm1");
#endif /* #ifndef __x86_64__ */
/* Prediction history reset */
asm volatile("hreset $0");
/* Serialize instruction execution */
asm volatile("serialize");
/* TSX suspend load address tracking */
asm volatile("xresldtrk");
asm volatile("xsusldtrk");
/* SGX */
asm volatile("encls");
asm volatile("enclu");
asm volatile("enclv");
/* pconfig */
asm volatile("pconfig");
/* wbnoinvd */
asm volatile("wbnoinvd");
/* Following line is a marker for the awk script - do not change */
asm volatile("rdtsc"); /* Stop here */
return 0;
}
| linux-master | tools/perf/arch/x86/tests/insn-x86-dat-src.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/types.h>
#include <string.h>
#include "debug.h"
#include "tests/tests.h"
#include "arch-tests.h"
#include "../../../../arch/x86/include/asm/insn.h"
#include "intel-pt-decoder/intel-pt-insn-decoder.h"
struct test_data {
u8 data[MAX_INSN_SIZE];
int expected_length;
int expected_rel;
const char *expected_op_str;
const char *expected_branch_str;
const char *asm_rep;
};
const struct test_data test_data_32[] = {
#include "insn-x86-dat-32.c"
{{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"},
{{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"},
{{0}, 0, 0, NULL, NULL, NULL},
};
const struct test_data test_data_64[] = {
#include "insn-x86-dat-64.c"
{{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"},
{{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"},
{{0xf2, 0x0f, 0x01, 0xca}, 4, 0, "erets", "indirect", "f2 0f 01 ca \terets"},
{{0xf3, 0x0f, 0x01, 0xca}, 4, 0, "eretu", "indirect", "f3 0f 01 ca \teretu"},
{{0}, 0, 0, NULL, NULL, NULL},
};
static int get_op(const char *op_str)
{
struct val_data {
const char *name;
int val;
} vals[] = {
{"other", INTEL_PT_OP_OTHER},
{"call", INTEL_PT_OP_CALL},
{"ret", INTEL_PT_OP_RET},
{"jcc", INTEL_PT_OP_JCC},
{"jmp", INTEL_PT_OP_JMP},
{"loop", INTEL_PT_OP_LOOP},
{"iret", INTEL_PT_OP_IRET},
{"int", INTEL_PT_OP_INT},
{"syscall", INTEL_PT_OP_SYSCALL},
{"sysret", INTEL_PT_OP_SYSRET},
{"vmentry", INTEL_PT_OP_VMENTRY},
{"erets", INTEL_PT_OP_ERETS},
{"eretu", INTEL_PT_OP_ERETU},
{NULL, 0},
};
struct val_data *val;
if (!op_str || !strlen(op_str))
return 0;
for (val = vals; val->name; val++) {
if (!strcmp(val->name, op_str))
return val->val;
}
pr_debug("Failed to get op\n");
return -1;
}
static int get_branch(const char *branch_str)
{
struct val_data {
const char *name;
int val;
} vals[] = {
{"no_branch", INTEL_PT_BR_NO_BRANCH},
{"indirect", INTEL_PT_BR_INDIRECT},
{"conditional", INTEL_PT_BR_CONDITIONAL},
{"unconditional", INTEL_PT_BR_UNCONDITIONAL},
{NULL, 0},
};
struct val_data *val;
if (!branch_str || !strlen(branch_str))
return 0;
for (val = vals; val->name; val++) {
if (!strcmp(val->name, branch_str))
return val->val;
}
pr_debug("Failed to get branch\n");
return -1;
}
static int test_data_item(const struct test_data *dat, int x86_64)
{
struct intel_pt_insn intel_pt_insn;
int op, branch, ret;
struct insn insn;
ret = insn_decode(&insn, dat->data, MAX_INSN_SIZE,
x86_64 ? INSN_MODE_64 : INSN_MODE_32);
if (ret < 0) {
pr_debug("Failed to decode: %s\n", dat->asm_rep);
return -1;
}
if (insn.length != dat->expected_length) {
pr_debug("Failed to decode length (%d vs expected %d): %s\n",
insn.length, dat->expected_length, dat->asm_rep);
return -1;
}
op = get_op(dat->expected_op_str);
branch = get_branch(dat->expected_branch_str);
if (intel_pt_get_insn(dat->data, MAX_INSN_SIZE, x86_64, &intel_pt_insn)) {
pr_debug("Intel PT failed to decode: %s\n", dat->asm_rep);
return -1;
}
if ((int)intel_pt_insn.op != op) {
pr_debug("Failed to decode 'op' value (%d vs expected %d): %s\n",
intel_pt_insn.op, op, dat->asm_rep);
return -1;
}
if ((int)intel_pt_insn.branch != branch) {
pr_debug("Failed to decode 'branch' value (%d vs expected %d): %s\n",
intel_pt_insn.branch, branch, dat->asm_rep);
return -1;
}
if (intel_pt_insn.rel != dat->expected_rel) {
pr_debug("Failed to decode 'rel' value (%#x vs expected %#x): %s\n",
intel_pt_insn.rel, dat->expected_rel, dat->asm_rep);
return -1;
}
pr_debug("Decoded ok: %s\n", dat->asm_rep);
return 0;
}
static int test_data_set(const struct test_data *dat_set, int x86_64)
{
const struct test_data *dat;
int ret = 0;
for (dat = dat_set; dat->expected_length; dat++) {
if (test_data_item(dat, x86_64))
ret = -1;
}
return ret;
}
/**
* test__insn_x86 - test x86 instruction decoder - new instructions.
*
* This function implements a test that decodes a selection of instructions and
* checks the results. The Intel PT function that further categorizes
* instructions (i.e. intel_pt_get_insn()) is also checked.
*
* The instructions are originally in insn-x86-dat-src.c which has been
* processed by scripts gen-insn-x86-dat.sh and gen-insn-x86-dat.awk to produce
* insn-x86-dat-32.c and insn-x86-dat-64.c which are included into this program.
* i.e. to add new instructions to the test, edit insn-x86-dat-src.c, run the
* gen-insn-x86-dat.sh script, make perf, and then run the test.
*
* If the test passes %0 is returned, otherwise %-1 is returned. Use the
* verbose (-v) option to see all the instructions and whether or not they
* decoded successfully.
*/
int test__insn_x86(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
int ret = 0;
if (test_data_set(test_data_32, 0))
ret = -1;
if (test_data_set(test_data_64, 1))
ret = -1;
return ret;
}
| linux-master | tools/perf/arch/x86/tests/insn-x86.c |
// SPDX-License-Identifier: GPL-2.0
#include "arch-tests.h"
#include "linux/perf_event.h"
#include "tests/tests.h"
#include "pmu.h"
#include "pmus.h"
#include "../perf-sys.h"
#include "debug.h"
#define NR_SUB_TESTS 5
static struct sub_tests {
int type;
unsigned long config;
bool valid;
} sub_tests[NR_SUB_TESTS] = {
{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, true },
{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, false },
{ PERF_TYPE_RAW, 0x076, true },
{ PERF_TYPE_RAW, 0x0C1, true },
{ PERF_TYPE_RAW, 0x012, false },
};
static int event_open(int type, unsigned long config)
{
struct perf_event_attr attr;
memset(&attr, 0, sizeof(struct perf_event_attr));
attr.type = type;
attr.size = sizeof(struct perf_event_attr);
attr.config = config;
attr.disabled = 1;
attr.precise_ip = 1;
attr.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_TID;
attr.sample_period = 100000;
return sys_perf_event_open(&attr, -1, 0, -1, 0);
}
int test__amd_ibs_via_core_pmu(struct test_suite *test __maybe_unused,
int subtest __maybe_unused)
{
struct perf_pmu *ibs_pmu;
int ret = TEST_OK;
int fd, i;
ibs_pmu = perf_pmus__find("ibs_op");
if (!ibs_pmu)
return TEST_SKIP;
for (i = 0; i < NR_SUB_TESTS; i++) {
fd = event_open(sub_tests[i].type, sub_tests[i].config);
pr_debug("type: 0x%x, config: 0x%lx, fd: %d - ", sub_tests[i].type,
sub_tests[i].config, fd);
if ((sub_tests[i].valid && fd == -1) ||
(!sub_tests[i].valid && fd > 0)) {
pr_debug("Fail\n");
ret = TEST_FAIL;
} else {
pr_debug("Pass\n");
}
if (fd > 0)
close(fd);
}
return ret;
}
| linux-master | tools/perf/arch/x86/tests/amd-ibs-via-core-pmu.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include "tests/tests.h"
#include "arch-tests.h"
#ifdef HAVE_AUXTRACE_SUPPORT
#ifdef HAVE_EXTRA_TESTS
DEFINE_SUITE("x86 instruction decoder - new instructions", insn_x86);
#endif
static struct test_case intel_pt_tests[] = {
TEST_CASE("Intel PT packet decoder", intel_pt_pkt_decoder),
TEST_CASE("Intel PT hybrid CPU compatibility", intel_pt_hybrid_compat),
{ .name = NULL, }
};
struct test_suite suite__intel_pt = {
.desc = "Intel PT",
.test_cases = intel_pt_tests,
};
#endif
#if defined(__x86_64__)
DEFINE_SUITE("x86 bp modify", bp_modify);
#endif
DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing);
DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu);
static struct test_case hybrid_tests[] = {
TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"),
{ .name = NULL, }
};
struct test_suite suite__hybrid = {
.desc = "x86 hybrid",
.test_cases = hybrid_tests,
};
struct test_suite *arch_tests[] = {
#ifdef HAVE_DWARF_UNWIND_SUPPORT
&suite__dwarf_unwind,
#endif
#ifdef HAVE_AUXTRACE_SUPPORT
#ifdef HAVE_EXTRA_TESTS
&suite__insn_x86,
#endif
&suite__intel_pt,
#endif
#if defined(__x86_64__)
&suite__bp_modify,
#endif
&suite__x86_sample_parsing,
&suite__amd_ibs_via_core_pmu,
&suite__hybrid,
NULL,
};
| linux-master | tools/perf/arch/x86/tests/arch-tests.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
#include <sys/types.h>
#include <sys/wait.h>
#include <sys/user.h>
#include <syscall.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/ptrace.h>
#include <asm/ptrace.h>
#include <errno.h>
#include "debug.h"
#include "tests/tests.h"
#include "arch-tests.h"
static noinline int bp_1(void)
{
pr_debug("in %s\n", __func__);
return 0;
}
static noinline int bp_2(void)
{
pr_debug("in %s\n", __func__);
return 0;
}
static int spawn_child(void)
{
int child = fork();
if (child == 0) {
/*
* The child sets itself for as tracee and
* waits in signal for parent to trace it,
* then it calls bp_1 and quits.
*/
int err = ptrace(PTRACE_TRACEME, 0, NULL, NULL);
if (err) {
pr_debug("failed to PTRACE_TRACEME\n");
exit(1);
}
raise(SIGCONT);
bp_1();
exit(0);
}
return child;
}
/*
* This tests creates HW breakpoint, tries to
* change it and checks it was properly changed.
*/
static int bp_modify1(void)
{
pid_t child;
int status;
unsigned long rip = 0, dr7 = 1;
child = spawn_child();
waitpid(child, &status, 0);
if (WIFEXITED(status)) {
pr_debug("tracee exited prematurely 1\n");
return TEST_FAIL;
}
/*
* The parent does following steps:
* - creates a new breakpoint (id 0) for bp_2 function
* - changes that breakpoint to bp_1 function
* - waits for the breakpoint to hit and checks
* it has proper rip of bp_1 function
* - detaches the child
*/
if (ptrace(PTRACE_POKEUSER, child,
offsetof(struct user, u_debugreg[0]), bp_2)) {
pr_debug("failed to set breakpoint, 1st time: %s\n",
strerror(errno));
goto out;
}
if (ptrace(PTRACE_POKEUSER, child,
offsetof(struct user, u_debugreg[0]), bp_1)) {
pr_debug("failed to set breakpoint, 2nd time: %s\n",
strerror(errno));
goto out;
}
if (ptrace(PTRACE_POKEUSER, child,
offsetof(struct user, u_debugreg[7]), dr7)) {
pr_debug("failed to set dr7: %s\n", strerror(errno));
goto out;
}
if (ptrace(PTRACE_CONT, child, NULL, NULL)) {
pr_debug("failed to PTRACE_CONT: %s\n", strerror(errno));
goto out;
}
waitpid(child, &status, 0);
if (WIFEXITED(status)) {
pr_debug("tracee exited prematurely 2\n");
return TEST_FAIL;
}
rip = ptrace(PTRACE_PEEKUSER, child,
offsetof(struct user_regs_struct, rip), NULL);
if (rip == (unsigned long) -1) {
pr_debug("failed to PTRACE_PEEKUSER: %s\n",
strerror(errno));
goto out;
}
pr_debug("rip %lx, bp_1 %p\n", rip, bp_1);
out:
if (ptrace(PTRACE_DETACH, child, NULL, NULL)) {
pr_debug("failed to PTRACE_DETACH: %s", strerror(errno));
return TEST_FAIL;
}
return rip == (unsigned long) bp_1 ? TEST_OK : TEST_FAIL;
}
/*
* This tests creates HW breakpoint, tries to
* change it to bogus value and checks the original
* breakpoint is hit.
*/
static int bp_modify2(void)
{
pid_t child;
int status;
unsigned long rip = 0, dr7 = 1;
child = spawn_child();
waitpid(child, &status, 0);
if (WIFEXITED(status)) {
pr_debug("tracee exited prematurely 1\n");
return TEST_FAIL;
}
/*
* The parent does following steps:
* - creates a new breakpoint (id 0) for bp_1 function
* - tries to change that breakpoint to (-1) address
* - waits for the breakpoint to hit and checks
* it has proper rip of bp_1 function
* - detaches the child
*/
if (ptrace(PTRACE_POKEUSER, child,
offsetof(struct user, u_debugreg[0]), bp_1)) {
pr_debug("failed to set breakpoint: %s\n",
strerror(errno));
goto out;
}
if (ptrace(PTRACE_POKEUSER, child,
offsetof(struct user, u_debugreg[7]), dr7)) {
pr_debug("failed to set dr7: %s\n", strerror(errno));
goto out;
}
if (!ptrace(PTRACE_POKEUSER, child,
offsetof(struct user, u_debugreg[0]), (unsigned long) (-1))) {
pr_debug("failed, breakpoint set to bogus address\n");
goto out;
}
if (ptrace(PTRACE_CONT, child, NULL, NULL)) {
pr_debug("failed to PTRACE_CONT: %s\n", strerror(errno));
goto out;
}
waitpid(child, &status, 0);
if (WIFEXITED(status)) {
pr_debug("tracee exited prematurely 2\n");
return TEST_FAIL;
}
rip = ptrace(PTRACE_PEEKUSER, child,
offsetof(struct user_regs_struct, rip), NULL);
if (rip == (unsigned long) -1) {
pr_debug("failed to PTRACE_PEEKUSER: %s\n",
strerror(errno));
goto out;
}
pr_debug("rip %lx, bp_1 %p\n", rip, bp_1);
out:
if (ptrace(PTRACE_DETACH, child, NULL, NULL)) {
pr_debug("failed to PTRACE_DETACH: %s", strerror(errno));
return TEST_FAIL;
}
return rip == (unsigned long) bp_1 ? TEST_OK : TEST_FAIL;
}
int test__bp_modify(struct test_suite *test __maybe_unused,
int subtest __maybe_unused)
{
TEST_ASSERT_VAL("modify test 1 failed\n", !bp_modify1());
TEST_ASSERT_VAL("modify test 2 failed\n", !bp_modify2());
return 0;
}
| linux-master | tools/perf/arch/x86/tests/bp-modify.c |
// SPDX-License-Identifier: GPL-2.0
#include <string.h>
#include "perf_regs.h"
#include "thread.h"
#include "map.h"
#include "maps.h"
#include "event.h"
#include "debug.h"
#include "tests/tests.h"
#define STACK_SIZE 8192
static int sample_ustack(struct perf_sample *sample,
struct thread *thread, u64 *regs)
{
struct stack_dump *stack = &sample->user_stack;
struct map *map;
unsigned long sp;
u64 stack_size, *buf;
buf = malloc(STACK_SIZE);
if (!buf) {
pr_debug("failed to allocate sample uregs data\n");
return -1;
}
sp = (unsigned long) regs[PERF_REG_X86_SP];
map = maps__find(thread__maps(thread), (u64)sp);
if (!map) {
pr_debug("failed to get stack map\n");
free(buf);
return -1;
}
stack_size = map__end(map) - sp;
stack_size = stack_size > STACK_SIZE ? STACK_SIZE : stack_size;
memcpy(buf, (void *) sp, stack_size);
#ifdef MEMORY_SANITIZER
/*
* Copying the stack may copy msan poison, avoid false positives in the
* unwinder by removing the poison here.
*/
__msan_unpoison(buf, stack_size);
#endif
stack->data = (char *) buf;
stack->size = stack_size;
return 0;
}
int test__arch_unwind_sample(struct perf_sample *sample,
struct thread *thread)
{
struct regs_dump *regs = &sample->user_regs;
u64 *buf;
buf = malloc(sizeof(u64) * PERF_REGS_MAX);
if (!buf) {
pr_debug("failed to allocate sample uregs data\n");
return -1;
}
#ifdef MEMORY_SANITIZER
/*
* Assignments to buf in the assembly function perf_regs_load aren't
* seen by memory sanitizer. Zero the memory to convince memory
* sanitizer the memory is initialized.
*/
memset(buf, 0, sizeof(u64) * PERF_REGS_MAX);
#endif
perf_regs_load(buf);
regs->abi = PERF_SAMPLE_REGS_ABI;
regs->regs = buf;
regs->mask = PERF_REGS_MASK;
return sample_ustack(sample, thread, buf);
}
| linux-master | tools/perf/arch/x86/tests/dwarf-unwind.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
* from insn-x86-dat-src.c for inclusion by insn-x86.c
* Do not change this code.
*/
{{0x0f, 0x31, }, 2, 0, "", "",
"0f 31 \trdtsc ",},
{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
{{0x48, 0x0f, 0x41, 0xd8, }, 4, 0, "", "",
"48 0f 41 d8 \tcmovno %rax,%rbx",},
{{0x48, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"48 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%rcx",},
{{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%rax),%cx",},
{{0x48, 0x0f, 0x44, 0xd8, }, 4, 0, "", "",
"48 0f 44 d8 \tcmove %rax,%rbx",},
{{0x48, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"48 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%rcx",},
{{0x66, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 44 88 78 56 34 12 \tcmove 0x12345678(%rax),%cx",},
{{0x0f, 0x90, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 90 80 78 56 34 12 \tseto 0x12345678(%rax)",},
{{0x0f, 0x91, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 91 80 78 56 34 12 \tsetno 0x12345678(%rax)",},
{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",},
{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",},
{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 92 80 78 56 34 12 \tsetb 0x12345678(%rax)",},
{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",},
{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",},
{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 93 80 78 56 34 12 \tsetae 0x12345678(%rax)",},
{{0x0f, 0x98, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 98 80 78 56 34 12 \tsets 0x12345678(%rax)",},
{{0x0f, 0x99, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 99 80 78 56 34 12 \tsetns 0x12345678(%rax)",},
{{0xc5, 0xcc, 0x41, 0xef, }, 4, 0, "", "",
"c5 cc 41 ef \tkandw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x41, 0xef, }, 5, 0, "", "",
"c4 e1 cc 41 ef \tkandq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x41, 0xef, }, 4, 0, "", "",
"c5 cd 41 ef \tkandb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x41, 0xef, }, 5, 0, "", "",
"c4 e1 cd 41 ef \tkandd %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x42, 0xef, }, 4, 0, "", "",
"c5 cc 42 ef \tkandnw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x42, 0xef, }, 5, 0, "", "",
"c4 e1 cc 42 ef \tkandnq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x42, 0xef, }, 4, 0, "", "",
"c5 cd 42 ef \tkandnb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x42, 0xef, }, 5, 0, "", "",
"c4 e1 cd 42 ef \tkandnd %k7,%k6,%k5",},
{{0xc5, 0xf8, 0x44, 0xf7, }, 4, 0, "", "",
"c5 f8 44 f7 \tknotw %k7,%k6",},
{{0xc4, 0xe1, 0xf8, 0x44, 0xf7, }, 5, 0, "", "",
"c4 e1 f8 44 f7 \tknotq %k7,%k6",},
{{0xc5, 0xf9, 0x44, 0xf7, }, 4, 0, "", "",
"c5 f9 44 f7 \tknotb %k7,%k6",},
{{0xc4, 0xe1, 0xf9, 0x44, 0xf7, }, 5, 0, "", "",
"c4 e1 f9 44 f7 \tknotd %k7,%k6",},
{{0xc5, 0xcc, 0x45, 0xef, }, 4, 0, "", "",
"c5 cc 45 ef \tkorw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x45, 0xef, }, 5, 0, "", "",
"c4 e1 cc 45 ef \tkorq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x45, 0xef, }, 4, 0, "", "",
"c5 cd 45 ef \tkorb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x45, 0xef, }, 5, 0, "", "",
"c4 e1 cd 45 ef \tkord %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x46, 0xef, }, 4, 0, "", "",
"c5 cc 46 ef \tkxnorw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x46, 0xef, }, 5, 0, "", "",
"c4 e1 cc 46 ef \tkxnorq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x46, 0xef, }, 4, 0, "", "",
"c5 cd 46 ef \tkxnorb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x46, 0xef, }, 5, 0, "", "",
"c4 e1 cd 46 ef \tkxnord %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x47, 0xef, }, 4, 0, "", "",
"c5 cc 47 ef \tkxorw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x47, 0xef, }, 5, 0, "", "",
"c4 e1 cc 47 ef \tkxorq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x47, 0xef, }, 4, 0, "", "",
"c5 cd 47 ef \tkxorb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x47, 0xef, }, 5, 0, "", "",
"c4 e1 cd 47 ef \tkxord %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x4a, 0xef, }, 4, 0, "", "",
"c5 cc 4a ef \tkaddw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x4a, 0xef, }, 5, 0, "", "",
"c4 e1 cc 4a ef \tkaddq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x4a, 0xef, }, 4, 0, "", "",
"c5 cd 4a ef \tkaddb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x4a, 0xef, }, 5, 0, "", "",
"c4 e1 cd 4a ef \tkaddd %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x4b, 0xef, }, 4, 0, "", "",
"c5 cd 4b ef \tkunpckbw %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x4b, 0xef, }, 4, 0, "", "",
"c5 cc 4b ef \tkunpckwd %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x4b, 0xef, }, 5, 0, "", "",
"c4 e1 cc 4b ef \tkunpckdq %k7,%k6,%k5",},
{{0xc5, 0xf8, 0x90, 0xee, }, 4, 0, "", "",
"c5 f8 90 ee \tkmovw %k6,%k5",},
{{0xc5, 0xf8, 0x90, 0x29, }, 4, 0, "", "",
"c5 f8 90 29 \tkmovw (%rcx),%k5",},
{{0xc4, 0xa1, 0x78, 0x90, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 78 90 ac f0 23 01 00 00 \tkmovw 0x123(%rax,%r14,8),%k5",},
{{0xc5, 0xf8, 0x91, 0x29, }, 4, 0, "", "",
"c5 f8 91 29 \tkmovw %k5,(%rcx)",},
{{0xc4, 0xa1, 0x78, 0x91, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 78 91 ac f0 23 01 00 00 \tkmovw %k5,0x123(%rax,%r14,8)",},
{{0xc5, 0xf8, 0x92, 0xe8, }, 4, 0, "", "",
"c5 f8 92 e8 \tkmovw %eax,%k5",},
{{0xc5, 0xf8, 0x92, 0xed, }, 4, 0, "", "",
"c5 f8 92 ed \tkmovw %ebp,%k5",},
{{0xc4, 0xc1, 0x78, 0x92, 0xed, }, 5, 0, "", "",
"c4 c1 78 92 ed \tkmovw %r13d,%k5",},
{{0xc5, 0xf8, 0x93, 0xc5, }, 4, 0, "", "",
"c5 f8 93 c5 \tkmovw %k5,%eax",},
{{0xc5, 0xf8, 0x93, 0xed, }, 4, 0, "", "",
"c5 f8 93 ed \tkmovw %k5,%ebp",},
{{0xc5, 0x78, 0x93, 0xed, }, 4, 0, "", "",
"c5 78 93 ed \tkmovw %k5,%r13d",},
{{0xc4, 0xe1, 0xf8, 0x90, 0xee, }, 5, 0, "", "",
"c4 e1 f8 90 ee \tkmovq %k6,%k5",},
{{0xc4, 0xe1, 0xf8, 0x90, 0x29, }, 5, 0, "", "",
"c4 e1 f8 90 29 \tkmovq (%rcx),%k5",},
{{0xc4, 0xa1, 0xf8, 0x90, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 f8 90 ac f0 23 01 00 00 \tkmovq 0x123(%rax,%r14,8),%k5",},
{{0xc4, 0xe1, 0xf8, 0x91, 0x29, }, 5, 0, "", "",
"c4 e1 f8 91 29 \tkmovq %k5,(%rcx)",},
{{0xc4, 0xa1, 0xf8, 0x91, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 f8 91 ac f0 23 01 00 00 \tkmovq %k5,0x123(%rax,%r14,8)",},
{{0xc4, 0xe1, 0xfb, 0x92, 0xe8, }, 5, 0, "", "",
"c4 e1 fb 92 e8 \tkmovq %rax,%k5",},
{{0xc4, 0xe1, 0xfb, 0x92, 0xed, }, 5, 0, "", "",
"c4 e1 fb 92 ed \tkmovq %rbp,%k5",},
{{0xc4, 0xc1, 0xfb, 0x92, 0xed, }, 5, 0, "", "",
"c4 c1 fb 92 ed \tkmovq %r13,%k5",},
{{0xc4, 0xe1, 0xfb, 0x93, 0xc5, }, 5, 0, "", "",
"c4 e1 fb 93 c5 \tkmovq %k5,%rax",},
{{0xc4, 0xe1, 0xfb, 0x93, 0xed, }, 5, 0, "", "",
"c4 e1 fb 93 ed \tkmovq %k5,%rbp",},
{{0xc4, 0x61, 0xfb, 0x93, 0xed, }, 5, 0, "", "",
"c4 61 fb 93 ed \tkmovq %k5,%r13",},
{{0xc5, 0xf9, 0x90, 0xee, }, 4, 0, "", "",
"c5 f9 90 ee \tkmovb %k6,%k5",},
{{0xc5, 0xf9, 0x90, 0x29, }, 4, 0, "", "",
"c5 f9 90 29 \tkmovb (%rcx),%k5",},
{{0xc4, 0xa1, 0x79, 0x90, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 79 90 ac f0 23 01 00 00 \tkmovb 0x123(%rax,%r14,8),%k5",},
{{0xc5, 0xf9, 0x91, 0x29, }, 4, 0, "", "",
"c5 f9 91 29 \tkmovb %k5,(%rcx)",},
{{0xc4, 0xa1, 0x79, 0x91, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 79 91 ac f0 23 01 00 00 \tkmovb %k5,0x123(%rax,%r14,8)",},
{{0xc5, 0xf9, 0x92, 0xe8, }, 4, 0, "", "",
"c5 f9 92 e8 \tkmovb %eax,%k5",},
{{0xc5, 0xf9, 0x92, 0xed, }, 4, 0, "", "",
"c5 f9 92 ed \tkmovb %ebp,%k5",},
{{0xc4, 0xc1, 0x79, 0x92, 0xed, }, 5, 0, "", "",
"c4 c1 79 92 ed \tkmovb %r13d,%k5",},
{{0xc5, 0xf9, 0x93, 0xc5, }, 4, 0, "", "",
"c5 f9 93 c5 \tkmovb %k5,%eax",},
{{0xc5, 0xf9, 0x93, 0xed, }, 4, 0, "", "",
"c5 f9 93 ed \tkmovb %k5,%ebp",},
{{0xc5, 0x79, 0x93, 0xed, }, 4, 0, "", "",
"c5 79 93 ed \tkmovb %k5,%r13d",},
{{0xc4, 0xe1, 0xf9, 0x90, 0xee, }, 5, 0, "", "",
"c4 e1 f9 90 ee \tkmovd %k6,%k5",},
{{0xc4, 0xe1, 0xf9, 0x90, 0x29, }, 5, 0, "", "",
"c4 e1 f9 90 29 \tkmovd (%rcx),%k5",},
{{0xc4, 0xa1, 0xf9, 0x90, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 f9 90 ac f0 23 01 00 00 \tkmovd 0x123(%rax,%r14,8),%k5",},
{{0xc4, 0xe1, 0xf9, 0x91, 0x29, }, 5, 0, "", "",
"c4 e1 f9 91 29 \tkmovd %k5,(%rcx)",},
{{0xc4, 0xa1, 0xf9, 0x91, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 a1 f9 91 ac f0 23 01 00 00 \tkmovd %k5,0x123(%rax,%r14,8)",},
{{0xc5, 0xfb, 0x92, 0xe8, }, 4, 0, "", "",
"c5 fb 92 e8 \tkmovd %eax,%k5",},
{{0xc5, 0xfb, 0x92, 0xed, }, 4, 0, "", "",
"c5 fb 92 ed \tkmovd %ebp,%k5",},
{{0xc4, 0xc1, 0x7b, 0x92, 0xed, }, 5, 0, "", "",
"c4 c1 7b 92 ed \tkmovd %r13d,%k5",},
{{0xc5, 0xfb, 0x93, 0xc5, }, 4, 0, "", "",
"c5 fb 93 c5 \tkmovd %k5,%eax",},
{{0xc5, 0xfb, 0x93, 0xed, }, 4, 0, "", "",
"c5 fb 93 ed \tkmovd %k5,%ebp",},
{{0xc5, 0x7b, 0x93, 0xed, }, 4, 0, "", "",
"c5 7b 93 ed \tkmovd %k5,%r13d",},
{{0xc5, 0xf8, 0x98, 0xee, }, 4, 0, "", "",
"c5 f8 98 ee \tkortestw %k6,%k5",},
{{0xc4, 0xe1, 0xf8, 0x98, 0xee, }, 5, 0, "", "",
"c4 e1 f8 98 ee \tkortestq %k6,%k5",},
{{0xc5, 0xf9, 0x98, 0xee, }, 4, 0, "", "",
"c5 f9 98 ee \tkortestb %k6,%k5",},
{{0xc4, 0xe1, 0xf9, 0x98, 0xee, }, 5, 0, "", "",
"c4 e1 f9 98 ee \tkortestd %k6,%k5",},
{{0xc5, 0xf8, 0x99, 0xee, }, 4, 0, "", "",
"c5 f8 99 ee \tktestw %k6,%k5",},
{{0xc4, 0xe1, 0xf8, 0x99, 0xee, }, 5, 0, "", "",
"c4 e1 f8 99 ee \tktestq %k6,%k5",},
{{0xc5, 0xf9, 0x99, 0xee, }, 4, 0, "", "",
"c5 f9 99 ee \tktestb %k6,%k5",},
{{0xc4, 0xe1, 0xf9, 0x99, 0xee, }, 5, 0, "", "",
"c4 e1 f9 99 ee \tktestd %k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x30, 0xee, 0x12, }, 6, 0, "", "",
"c4 e3 f9 30 ee 12 \tkshiftrw $0x12,%k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x31, 0xee, 0x5b, }, 6, 0, "", "",
"c4 e3 f9 31 ee 5b \tkshiftrq $0x5b,%k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x32, 0xee, 0x12, }, 6, 0, "", "",
"c4 e3 f9 32 ee 12 \tkshiftlw $0x12,%k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x33, 0xee, 0x5b, }, 6, 0, "", "",
"c4 e3 f9 33 ee 5b \tkshiftlq $0x5b,%k6,%k5",},
{{0xc5, 0xf8, 0x5b, 0xf5, }, 4, 0, "", "",
"c5 f8 5b f5 \tvcvtdq2ps %xmm5,%xmm6",},
{{0x62, 0x91, 0xfc, 0x4f, 0x5b, 0xf5, }, 6, 0, "", "",
"62 91 fc 4f 5b f5 \tvcvtqq2ps %zmm29,%ymm6{%k7}",},
{{0xc5, 0xf9, 0x5b, 0xf5, }, 4, 0, "", "",
"c5 f9 5b f5 \tvcvtps2dq %xmm5,%xmm6",},
{{0xc5, 0xfa, 0x5b, 0xf5, }, 4, 0, "", "",
"c5 fa 5b f5 \tvcvttps2dq %xmm5,%xmm6",},
{{0x0f, 0x6f, 0xe0, }, 3, 0, "", "",
"0f 6f e0 \tmovq %mm0,%mm4",},
{{0xc5, 0xfd, 0x6f, 0xf4, }, 4, 0, "", "",
"c5 fd 6f f4 \tvmovdqa %ymm4,%ymm6",},
{{0x62, 0x01, 0x7d, 0x48, 0x6f, 0xd1, }, 6, 0, "", "",
"62 01 7d 48 6f d1 \tvmovdqa32 %zmm25,%zmm26",},
{{0x62, 0x01, 0xfd, 0x48, 0x6f, 0xd1, }, 6, 0, "", "",
"62 01 fd 48 6f d1 \tvmovdqa64 %zmm25,%zmm26",},
{{0xc5, 0xfe, 0x6f, 0xf4, }, 4, 0, "", "",
"c5 fe 6f f4 \tvmovdqu %ymm4,%ymm6",},
{{0x62, 0x01, 0x7e, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 01 7e 48 6f f5 \tvmovdqu32 %zmm29,%zmm30",},
{{0x62, 0x01, 0xfe, 0x48, 0x6f, 0xd1, }, 6, 0, "", "",
"62 01 fe 48 6f d1 \tvmovdqu64 %zmm25,%zmm26",},
{{0x62, 0x01, 0x7f, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 01 7f 48 6f f5 \tvmovdqu8 %zmm29,%zmm30",},
{{0x62, 0x01, 0xff, 0x48, 0x6f, 0xd1, }, 6, 0, "", "",
"62 01 ff 48 6f d1 \tvmovdqu16 %zmm25,%zmm26",},
{{0x0f, 0x78, 0xc3, }, 3, 0, "", "",
"0f 78 c3 \tvmread %rax,%rbx",},
{{0x62, 0x01, 0x7c, 0x48, 0x78, 0xd1, }, 6, 0, "", "",
"62 01 7c 48 78 d1 \tvcvttps2udq %zmm25,%zmm26",},
{{0x62, 0x91, 0xfc, 0x4f, 0x78, 0xf5, }, 6, 0, "", "",
"62 91 fc 4f 78 f5 \tvcvttpd2udq %zmm29,%ymm6{%k7}",},
{{0x62, 0xf1, 0xff, 0x08, 0x78, 0xc6, }, 6, 0, "", "",
"62 f1 ff 08 78 c6 \tvcvttsd2usi %xmm6,%rax",},
{{0x62, 0xf1, 0xfe, 0x08, 0x78, 0xc6, }, 6, 0, "", "",
"62 f1 fe 08 78 c6 \tvcvttss2usi %xmm6,%rax",},
{{0x62, 0x61, 0x7d, 0x4f, 0x78, 0xd5, }, 6, 0, "", "",
"62 61 7d 4f 78 d5 \tvcvttps2uqq %ymm5,%zmm26{%k7}",},
{{0x62, 0x01, 0xfd, 0x48, 0x78, 0xf5, }, 6, 0, "", "",
"62 01 fd 48 78 f5 \tvcvttpd2uqq %zmm29,%zmm30",},
{{0x0f, 0x79, 0xd8, }, 3, 0, "", "",
"0f 79 d8 \tvmwrite %rax,%rbx",},
{{0x62, 0x01, 0x7c, 0x48, 0x79, 0xd1, }, 6, 0, "", "",
"62 01 7c 48 79 d1 \tvcvtps2udq %zmm25,%zmm26",},
{{0x62, 0x91, 0xfc, 0x4f, 0x79, 0xf5, }, 6, 0, "", "",
"62 91 fc 4f 79 f5 \tvcvtpd2udq %zmm29,%ymm6{%k7}",},
{{0x62, 0xf1, 0xff, 0x08, 0x79, 0xc6, }, 6, 0, "", "",
"62 f1 ff 08 79 c6 \tvcvtsd2usi %xmm6,%rax",},
{{0x62, 0xf1, 0xfe, 0x08, 0x79, 0xc6, }, 6, 0, "", "",
"62 f1 fe 08 79 c6 \tvcvtss2usi %xmm6,%rax",},
{{0x62, 0x61, 0x7d, 0x4f, 0x79, 0xd5, }, 6, 0, "", "",
"62 61 7d 4f 79 d5 \tvcvtps2uqq %ymm5,%zmm26{%k7}",},
{{0x62, 0x01, 0xfd, 0x48, 0x79, 0xf5, }, 6, 0, "", "",
"62 01 fd 48 79 f5 \tvcvtpd2uqq %zmm29,%zmm30",},
{{0x62, 0x61, 0x7e, 0x4f, 0x7a, 0xed, }, 6, 0, "", "",
"62 61 7e 4f 7a ed \tvcvtudq2pd %ymm5,%zmm29{%k7}",},
{{0x62, 0x01, 0xfe, 0x48, 0x7a, 0xd1, }, 6, 0, "", "",
"62 01 fe 48 7a d1 \tvcvtuqq2pd %zmm25,%zmm26",},
{{0x62, 0x01, 0x7f, 0x48, 0x7a, 0xf5, }, 6, 0, "", "",
"62 01 7f 48 7a f5 \tvcvtudq2ps %zmm29,%zmm30",},
{{0x62, 0x01, 0xff, 0x4f, 0x7a, 0xd1, }, 6, 0, "", "",
"62 01 ff 4f 7a d1 \tvcvtuqq2ps %zmm25,%ymm26{%k7}",},
{{0x62, 0x01, 0x7d, 0x4f, 0x7a, 0xd1, }, 6, 0, "", "",
"62 01 7d 4f 7a d1 \tvcvttps2qq %ymm25,%zmm26{%k7}",},
{{0x62, 0x01, 0xfd, 0x48, 0x7a, 0xf5, }, 6, 0, "", "",
"62 01 fd 48 7a f5 \tvcvttpd2qq %zmm29,%zmm30",},
{{0x62, 0xf1, 0x57, 0x08, 0x7b, 0xf0, }, 6, 0, "", "",
"62 f1 57 08 7b f0 \tvcvtusi2sd %eax,%xmm5,%xmm6",},
{{0x62, 0xf1, 0x56, 0x08, 0x7b, 0xf0, }, 6, 0, "", "",
"62 f1 56 08 7b f0 \tvcvtusi2ss %eax,%xmm5,%xmm6",},
{{0x62, 0x61, 0x7d, 0x4f, 0x7b, 0xd5, }, 6, 0, "", "",
"62 61 7d 4f 7b d5 \tvcvtps2qq %ymm5,%zmm26{%k7}",},
{{0x62, 0x01, 0xfd, 0x48, 0x7b, 0xf5, }, 6, 0, "", "",
"62 01 fd 48 7b f5 \tvcvtpd2qq %zmm29,%zmm30",},
{{0x0f, 0x7f, 0xc4, }, 3, 0, "", "",
"0f 7f c4 \tmovq %mm0,%mm4",},
{{0xc5, 0x7d, 0x7f, 0xc6, }, 4, 0, "", "",
"c5 7d 7f c6 \tvmovdqa %ymm8,%ymm6",},
{{0x62, 0x01, 0x7d, 0x48, 0x7f, 0xca, }, 6, 0, "", "",
"62 01 7d 48 7f ca \tvmovdqa32 %zmm25,%zmm26",},
{{0x62, 0x01, 0xfd, 0x48, 0x7f, 0xca, }, 6, 0, "", "",
"62 01 fd 48 7f ca \tvmovdqa64 %zmm25,%zmm26",},
{{0xc5, 0x7e, 0x7f, 0xc6, }, 4, 0, "", "",
"c5 7e 7f c6 \tvmovdqu %ymm8,%ymm6",},
{{0x62, 0x01, 0x7e, 0x48, 0x7f, 0xca, }, 6, 0, "", "",
"62 01 7e 48 7f ca \tvmovdqu32 %zmm25,%zmm26",},
{{0x62, 0x01, 0xfe, 0x48, 0x7f, 0xca, }, 6, 0, "", "",
"62 01 fe 48 7f ca \tvmovdqu64 %zmm25,%zmm26",},
{{0x62, 0x61, 0x7f, 0x48, 0x7f, 0x31, }, 6, 0, "", "",
"62 61 7f 48 7f 31 \tvmovdqu8 %zmm30,(%rcx)",},
{{0x62, 0x01, 0xff, 0x48, 0x7f, 0xca, }, 6, 0, "", "",
"62 01 ff 48 7f ca \tvmovdqu16 %zmm25,%zmm26",},
{{0x0f, 0xdb, 0xd1, }, 3, 0, "", "",
"0f db d1 \tpand %mm1,%mm2",},
{{0x66, 0x0f, 0xdb, 0xd1, }, 4, 0, "", "",
"66 0f db d1 \tpand %xmm1,%xmm2",},
{{0xc5, 0xcd, 0xdb, 0xd4, }, 4, 0, "", "",
"c5 cd db d4 \tvpand %ymm4,%ymm6,%ymm2",},
{{0x62, 0x01, 0x35, 0x40, 0xdb, 0xd0, }, 6, 0, "", "",
"62 01 35 40 db d0 \tvpandd %zmm24,%zmm25,%zmm26",},
{{0x62, 0x01, 0xb5, 0x40, 0xdb, 0xd0, }, 6, 0, "", "",
"62 01 b5 40 db d0 \tvpandq %zmm24,%zmm25,%zmm26",},
{{0x0f, 0xdf, 0xd1, }, 3, 0, "", "",
"0f df d1 \tpandn %mm1,%mm2",},
{{0x66, 0x0f, 0xdf, 0xd1, }, 4, 0, "", "",
"66 0f df d1 \tpandn %xmm1,%xmm2",},
{{0xc5, 0xcd, 0xdf, 0xd4, }, 4, 0, "", "",
"c5 cd df d4 \tvpandn %ymm4,%ymm6,%ymm2",},
{{0x62, 0x01, 0x35, 0x40, 0xdf, 0xd0, }, 6, 0, "", "",
"62 01 35 40 df d0 \tvpandnd %zmm24,%zmm25,%zmm26",},
{{0x62, 0x01, 0xb5, 0x40, 0xdf, 0xd0, }, 6, 0, "", "",
"62 01 b5 40 df d0 \tvpandnq %zmm24,%zmm25,%zmm26",},
{{0xc5, 0xf9, 0xe6, 0xd1, }, 4, 0, "", "",
"c5 f9 e6 d1 \tvcvttpd2dq %xmm1,%xmm2",},
{{0xc5, 0xfa, 0xe6, 0xf5, }, 4, 0, "", "",
"c5 fa e6 f5 \tvcvtdq2pd %xmm5,%xmm6",},
{{0x62, 0x61, 0x7e, 0x4f, 0xe6, 0xd5, }, 6, 0, "", "",
"62 61 7e 4f e6 d5 \tvcvtdq2pd %ymm5,%zmm26{%k7}",},
{{0x62, 0x01, 0xfe, 0x48, 0xe6, 0xd1, }, 6, 0, "", "",
"62 01 fe 48 e6 d1 \tvcvtqq2pd %zmm25,%zmm26",},
{{0xc5, 0xfb, 0xe6, 0xd1, }, 4, 0, "", "",
"c5 fb e6 d1 \tvcvtpd2dq %xmm1,%xmm2",},
{{0x0f, 0xeb, 0xf4, }, 3, 0, "", "",
"0f eb f4 \tpor %mm4,%mm6",},
{{0xc5, 0xcd, 0xeb, 0xd4, }, 4, 0, "", "",
"c5 cd eb d4 \tvpor %ymm4,%ymm6,%ymm2",},
{{0x62, 0x01, 0x35, 0x40, 0xeb, 0xd0, }, 6, 0, "", "",
"62 01 35 40 eb d0 \tvpord %zmm24,%zmm25,%zmm26",},
{{0x62, 0x01, 0xb5, 0x40, 0xeb, 0xd0, }, 6, 0, "", "",
"62 01 b5 40 eb d0 \tvporq %zmm24,%zmm25,%zmm26",},
{{0x0f, 0xef, 0xf4, }, 3, 0, "", "",
"0f ef f4 \tpxor %mm4,%mm6",},
{{0xc5, 0xcd, 0xef, 0xd4, }, 4, 0, "", "",
"c5 cd ef d4 \tvpxor %ymm4,%ymm6,%ymm2",},
{{0x62, 0x01, 0x35, 0x40, 0xef, 0xd0, }, 6, 0, "", "",
"62 01 35 40 ef d0 \tvpxord %zmm24,%zmm25,%zmm26",},
{{0x62, 0x01, 0xb5, 0x40, 0xef, 0xd0, }, 6, 0, "", "",
"62 01 b5 40 ef d0 \tvpxorq %zmm24,%zmm25,%zmm26",},
{{0x66, 0x0f, 0x38, 0x10, 0xc1, }, 5, 0, "", "",
"66 0f 38 10 c1 \tpblendvb %xmm0,%xmm1,%xmm0",},
{{0x62, 0x02, 0x9d, 0x40, 0x10, 0xeb, }, 6, 0, "", "",
"62 02 9d 40 10 eb \tvpsrlvw %zmm27,%zmm28,%zmm29",},
{{0x62, 0x62, 0x7e, 0x4f, 0x10, 0xe6, }, 6, 0, "", "",
"62 62 7e 4f 10 e6 \tvpmovuswb %zmm28,%ymm6{%k7}",},
{{0x62, 0x62, 0x7e, 0x4f, 0x11, 0xe6, }, 6, 0, "", "",
"62 62 7e 4f 11 e6 \tvpmovusdb %zmm28,%xmm6{%k7}",},
{{0x62, 0x02, 0x9d, 0x40, 0x11, 0xeb, }, 6, 0, "", "",
"62 02 9d 40 11 eb \tvpsravw %zmm27,%zmm28,%zmm29",},
{{0x62, 0x62, 0x7e, 0x4f, 0x12, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 12 de \tvpmovusqb %zmm27,%xmm6{%k7}",},
{{0x62, 0x02, 0x9d, 0x40, 0x12, 0xeb, }, 6, 0, "", "",
"62 02 9d 40 12 eb \tvpsllvw %zmm27,%zmm28,%zmm29",},
{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
{{0x62, 0x62, 0x7d, 0x4f, 0x13, 0xdd, }, 6, 0, "", "",
"62 62 7d 4f 13 dd \tvcvtph2ps %ymm5,%zmm27{%k7}",},
{{0x62, 0x62, 0x7e, 0x4f, 0x13, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 13 de \tvpmovusdw %zmm27,%ymm6{%k7}",},
{{0x66, 0x0f, 0x38, 0x14, 0xc1, }, 5, 0, "", "",
"66 0f 38 14 c1 \tblendvps %xmm0,%xmm1,%xmm0",},
{{0x62, 0x62, 0x7e, 0x4f, 0x14, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 14 de \tvpmovusqw %zmm27,%xmm6{%k7}",},
{{0x62, 0x02, 0x1d, 0x40, 0x14, 0xeb, }, 6, 0, "", "",
"62 02 1d 40 14 eb \tvprorvd %zmm27,%zmm28,%zmm29",},
{{0x62, 0x02, 0x9d, 0x40, 0x14, 0xeb, }, 6, 0, "", "",
"62 02 9d 40 14 eb \tvprorvq %zmm27,%zmm28,%zmm29",},
{{0x66, 0x0f, 0x38, 0x15, 0xc1, }, 5, 0, "", "",
"66 0f 38 15 c1 \tblendvpd %xmm0,%xmm1,%xmm0",},
{{0x62, 0x62, 0x7e, 0x4f, 0x15, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 15 de \tvpmovusqd %zmm27,%ymm6{%k7}",},
{{0x62, 0x02, 0x1d, 0x40, 0x15, 0xeb, }, 6, 0, "", "",
"62 02 1d 40 15 eb \tvprolvd %zmm27,%zmm28,%zmm29",},
{{0x62, 0x02, 0x9d, 0x40, 0x15, 0xeb, }, 6, 0, "", "",
"62 02 9d 40 15 eb \tvprolvq %zmm27,%zmm28,%zmm29",},
{{0xc4, 0xe2, 0x4d, 0x16, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 16 d4 \tvpermps %ymm4,%ymm6,%ymm2",},
{{0x62, 0x82, 0x2d, 0x27, 0x16, 0xf0, }, 6, 0, "", "",
"62 82 2d 27 16 f0 \tvpermps %ymm24,%ymm26,%ymm22{%k7}",},
{{0x62, 0x82, 0xad, 0x27, 0x16, 0xf0, }, 6, 0, "", "",
"62 82 ad 27 16 f0 \tvpermpd %ymm24,%ymm26,%ymm22{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x19, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 19 f4 \tvbroadcastsd %xmm4,%ymm6",},
{{0x62, 0x02, 0x7d, 0x48, 0x19, 0xd3, }, 6, 0, "", "",
"62 02 7d 48 19 d3 \tvbroadcastf32x2 %xmm27,%zmm26",},
{{0xc4, 0xe2, 0x7d, 0x1a, 0x21, }, 5, 0, "", "",
"c4 e2 7d 1a 21 \tvbroadcastf128 (%rcx),%ymm4",},
{{0x62, 0x62, 0x7d, 0x48, 0x1a, 0x11, }, 6, 0, "", "",
"62 62 7d 48 1a 11 \tvbroadcastf32x4 (%rcx),%zmm26",},
{{0x62, 0x62, 0xfd, 0x48, 0x1a, 0x11, }, 6, 0, "", "",
"62 62 fd 48 1a 11 \tvbroadcastf64x2 (%rcx),%zmm26",},
{{0x62, 0x62, 0x7d, 0x48, 0x1b, 0x19, }, 6, 0, "", "",
"62 62 7d 48 1b 19 \tvbroadcastf32x8 (%rcx),%zmm27",},
{{0x62, 0x62, 0xfd, 0x48, 0x1b, 0x11, }, 6, 0, "", "",
"62 62 fd 48 1b 11 \tvbroadcastf64x4 (%rcx),%zmm26",},
{{0x62, 0x02, 0xfd, 0x48, 0x1f, 0xe3, }, 6, 0, "", "",
"62 02 fd 48 1f e3 \tvpabsq %zmm27,%zmm28",},
{{0xc4, 0xe2, 0x79, 0x20, 0xec, }, 5, 0, "", "",
"c4 e2 79 20 ec \tvpmovsxbw %xmm4,%xmm5",},
{{0x62, 0x62, 0x7e, 0x4f, 0x20, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 20 de \tvpmovswb %zmm27,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x21, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 21 f4 \tvpmovsxbd %xmm4,%ymm6",},
{{0x62, 0x62, 0x7e, 0x4f, 0x21, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 21 de \tvpmovsdb %zmm27,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x22, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 22 e4 \tvpmovsxbq %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x22, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 22 de \tvpmovsqb %zmm27,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x23, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 23 e4 \tvpmovsxwd %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x23, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 23 de \tvpmovsdw %zmm27,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x24, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 24 f4 \tvpmovsxwq %xmm4,%ymm6",},
{{0x62, 0x62, 0x7e, 0x4f, 0x24, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 24 de \tvpmovsqw %zmm27,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x25, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 25 e4 \tvpmovsxdq %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x25, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 25 de \tvpmovsqd %zmm27,%ymm6{%k7}",},
{{0x62, 0x92, 0x1d, 0x40, 0x26, 0xeb, }, 6, 0, "", "",
"62 92 1d 40 26 eb \tvptestmb %zmm27,%zmm28,%k5",},
{{0x62, 0x92, 0x9d, 0x40, 0x26, 0xeb, }, 6, 0, "", "",
"62 92 9d 40 26 eb \tvptestmw %zmm27,%zmm28,%k5",},
{{0x62, 0x92, 0x26, 0x40, 0x26, 0xea, }, 6, 0, "", "",
"62 92 26 40 26 ea \tvptestnmb %zmm26,%zmm27,%k5",},
{{0x62, 0x92, 0xa6, 0x40, 0x26, 0xea, }, 6, 0, "", "",
"62 92 a6 40 26 ea \tvptestnmw %zmm26,%zmm27,%k5",},
{{0x62, 0x92, 0x1d, 0x40, 0x27, 0xeb, }, 6, 0, "", "",
"62 92 1d 40 27 eb \tvptestmd %zmm27,%zmm28,%k5",},
{{0x62, 0x92, 0x9d, 0x40, 0x27, 0xeb, }, 6, 0, "", "",
"62 92 9d 40 27 eb \tvptestmq %zmm27,%zmm28,%k5",},
{{0x62, 0x92, 0x26, 0x40, 0x27, 0xea, }, 6, 0, "", "",
"62 92 26 40 27 ea \tvptestnmd %zmm26,%zmm27,%k5",},
{{0x62, 0x92, 0xa6, 0x40, 0x27, 0xea, }, 6, 0, "", "",
"62 92 a6 40 27 ea \tvptestnmq %zmm26,%zmm27,%k5",},
{{0xc4, 0xe2, 0x4d, 0x28, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 28 d4 \tvpmuldq %ymm4,%ymm6,%ymm2",},
{{0x62, 0x62, 0x7e, 0x48, 0x28, 0xe5, }, 6, 0, "", "",
"62 62 7e 48 28 e5 \tvpmovm2b %k5,%zmm28",},
{{0x62, 0x62, 0xfe, 0x48, 0x28, 0xe5, }, 6, 0, "", "",
"62 62 fe 48 28 e5 \tvpmovm2w %k5,%zmm28",},
{{0xc4, 0xe2, 0x4d, 0x29, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 29 d4 \tvpcmpeqq %ymm4,%ymm6,%ymm2",},
{{0x62, 0x92, 0x7e, 0x48, 0x29, 0xec, }, 6, 0, "", "",
"62 92 7e 48 29 ec \tvpmovb2m %zmm28,%k5",},
{{0x62, 0x92, 0xfe, 0x48, 0x29, 0xec, }, 6, 0, "", "",
"62 92 fe 48 29 ec \tvpmovw2m %zmm28,%k5",},
{{0xc4, 0xe2, 0x7d, 0x2a, 0x21, }, 5, 0, "", "",
"c4 e2 7d 2a 21 \tvmovntdqa (%rcx),%ymm4",},
{{0x62, 0x62, 0xfe, 0x48, 0x2a, 0xf6, }, 6, 0, "", "",
"62 62 fe 48 2a f6 \tvpbroadcastmb2q %k6,%zmm30",},
{{0xc4, 0xe2, 0x5d, 0x2c, 0x31, }, 5, 0, "", "",
"c4 e2 5d 2c 31 \tvmaskmovps (%rcx),%ymm4,%ymm6",},
{{0x62, 0x02, 0x35, 0x40, 0x2c, 0xd0, }, 6, 0, "", "",
"62 02 35 40 2c d0 \tvscalefps %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x2c, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 2c d0 \tvscalefpd %zmm24,%zmm25,%zmm26",},
{{0xc4, 0xe2, 0x5d, 0x2d, 0x31, }, 5, 0, "", "",
"c4 e2 5d 2d 31 \tvmaskmovpd (%rcx),%ymm4,%ymm6",},
{{0x62, 0x02, 0x35, 0x07, 0x2d, 0xd0, }, 6, 0, "", "",
"62 02 35 07 2d d0 \tvscalefss %xmm24,%xmm25,%xmm26{%k7}",},
{{0x62, 0x02, 0xb5, 0x07, 0x2d, 0xd0, }, 6, 0, "", "",
"62 02 b5 07 2d d0 \tvscalefsd %xmm24,%xmm25,%xmm26{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x30, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 30 e4 \tvpmovzxbw %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x30, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 30 de \tvpmovwb %zmm27,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x31, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 31 f4 \tvpmovzxbd %xmm4,%ymm6",},
{{0x62, 0x62, 0x7e, 0x4f, 0x31, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 31 de \tvpmovdb %zmm27,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x32, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 32 e4 \tvpmovzxbq %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x32, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 32 de \tvpmovqb %zmm27,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x33, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 33 e4 \tvpmovzxwd %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x33, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 33 de \tvpmovdw %zmm27,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x34, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 34 f4 \tvpmovzxwq %xmm4,%ymm6",},
{{0x62, 0x62, 0x7e, 0x4f, 0x34, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 34 de \tvpmovqw %zmm27,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x35, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 35 e4 \tvpmovzxdq %xmm4,%ymm4",},
{{0x62, 0x62, 0x7e, 0x4f, 0x35, 0xde, }, 6, 0, "", "",
"62 62 7e 4f 35 de \tvpmovqd %zmm27,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x4d, 0x36, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 36 d4 \tvpermd %ymm4,%ymm6,%ymm2",},
{{0x62, 0x82, 0x2d, 0x27, 0x36, 0xf0, }, 6, 0, "", "",
"62 82 2d 27 36 f0 \tvpermd %ymm24,%ymm26,%ymm22{%k7}",},
{{0x62, 0x82, 0xad, 0x27, 0x36, 0xf0, }, 6, 0, "", "",
"62 82 ad 27 36 f0 \tvpermq %ymm24,%ymm26,%ymm22{%k7}",},
{{0xc4, 0xe2, 0x4d, 0x38, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 38 d4 \tvpminsb %ymm4,%ymm6,%ymm2",},
{{0x62, 0x62, 0x7e, 0x48, 0x38, 0xe5, }, 6, 0, "", "",
"62 62 7e 48 38 e5 \tvpmovm2d %k5,%zmm28",},
{{0x62, 0x62, 0xfe, 0x48, 0x38, 0xe5, }, 6, 0, "", "",
"62 62 fe 48 38 e5 \tvpmovm2q %k5,%zmm28",},
{{0xc4, 0xe2, 0x69, 0x39, 0xd9, }, 5, 0, "", "",
"c4 e2 69 39 d9 \tvpminsd %xmm1,%xmm2,%xmm3",},
{{0x62, 0x02, 0x35, 0x40, 0x39, 0xd0, }, 6, 0, "", "",
"62 02 35 40 39 d0 \tvpminsd %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x39, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 39 d0 \tvpminsq %zmm24,%zmm25,%zmm26",},
{{0x62, 0x92, 0x7e, 0x48, 0x39, 0xec, }, 6, 0, "", "",
"62 92 7e 48 39 ec \tvpmovd2m %zmm28,%k5",},
{{0x62, 0x92, 0xfe, 0x48, 0x39, 0xec, }, 6, 0, "", "",
"62 92 fe 48 39 ec \tvpmovq2m %zmm28,%k5",},
{{0xc4, 0xe2, 0x4d, 0x3a, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3a d4 \tvpminuw %ymm4,%ymm6,%ymm2",},
{{0x62, 0x62, 0x7e, 0x48, 0x3a, 0xe6, }, 6, 0, "", "",
"62 62 7e 48 3a e6 \tvpbroadcastmw2d %k6,%zmm28",},
{{0xc4, 0xe2, 0x4d, 0x3b, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3b d4 \tvpminud %ymm4,%ymm6,%ymm2",},
{{0x62, 0x02, 0x35, 0x40, 0x3b, 0xd0, }, 6, 0, "", "",
"62 02 35 40 3b d0 \tvpminud %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x3b, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 3b d0 \tvpminuq %zmm24,%zmm25,%zmm26",},
{{0xc4, 0xe2, 0x4d, 0x3d, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3d d4 \tvpmaxsd %ymm4,%ymm6,%ymm2",},
{{0x62, 0x02, 0x35, 0x40, 0x3d, 0xd0, }, 6, 0, "", "",
"62 02 35 40 3d d0 \tvpmaxsd %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x3d, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 3d d0 \tvpmaxsq %zmm24,%zmm25,%zmm26",},
{{0xc4, 0xe2, 0x4d, 0x3f, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3f d4 \tvpmaxud %ymm4,%ymm6,%ymm2",},
{{0x62, 0x02, 0x35, 0x40, 0x3f, 0xd0, }, 6, 0, "", "",
"62 02 35 40 3f d0 \tvpmaxud %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x3f, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 3f d0 \tvpmaxuq %zmm24,%zmm25,%zmm26",},
{{0xc4, 0xe2, 0x4d, 0x40, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 40 d4 \tvpmulld %ymm4,%ymm6,%ymm2",},
{{0x62, 0x02, 0x35, 0x40, 0x40, 0xd0, }, 6, 0, "", "",
"62 02 35 40 40 d0 \tvpmulld %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x40, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 40 d0 \tvpmullq %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0x7d, 0x48, 0x42, 0xd1, }, 6, 0, "", "",
"62 02 7d 48 42 d1 \tvgetexpps %zmm25,%zmm26",},
{{0x62, 0x02, 0xfd, 0x48, 0x42, 0xe3, }, 6, 0, "", "",
"62 02 fd 48 42 e3 \tvgetexppd %zmm27,%zmm28",},
{{0x62, 0x02, 0x35, 0x07, 0x43, 0xd0, }, 6, 0, "", "",
"62 02 35 07 43 d0 \tvgetexpss %xmm24,%xmm25,%xmm26{%k7}",},
{{0x62, 0x02, 0x95, 0x07, 0x43, 0xf4, }, 6, 0, "", "",
"62 02 95 07 43 f4 \tvgetexpsd %xmm28,%xmm29,%xmm30{%k7}",},
{{0x62, 0x02, 0x7d, 0x48, 0x44, 0xe3, }, 6, 0, "", "",
"62 02 7d 48 44 e3 \tvplzcntd %zmm27,%zmm28",},
{{0x62, 0x02, 0xfd, 0x48, 0x44, 0xe3, }, 6, 0, "", "",
"62 02 fd 48 44 e3 \tvplzcntq %zmm27,%zmm28",},
{{0xc4, 0xe2, 0x4d, 0x46, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 46 d4 \tvpsravd %ymm4,%ymm6,%ymm2",},
{{0x62, 0x02, 0x35, 0x40, 0x46, 0xd0, }, 6, 0, "", "",
"62 02 35 40 46 d0 \tvpsravd %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xb5, 0x40, 0x46, 0xd0, }, 6, 0, "", "",
"62 02 b5 40 46 d0 \tvpsravq %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0x7d, 0x48, 0x4c, 0xd1, }, 6, 0, "", "",
"62 02 7d 48 4c d1 \tvrcp14ps %zmm25,%zmm26",},
{{0x62, 0x02, 0xfd, 0x48, 0x4c, 0xe3, }, 6, 0, "", "",
"62 02 fd 48 4c e3 \tvrcp14pd %zmm27,%zmm28",},
{{0x62, 0x02, 0x35, 0x07, 0x4d, 0xd0, }, 6, 0, "", "",
"62 02 35 07 4d d0 \tvrcp14ss %xmm24,%xmm25,%xmm26{%k7}",},
{{0x62, 0x02, 0xb5, 0x07, 0x4d, 0xd0, }, 6, 0, "", "",
"62 02 b5 07 4d d0 \tvrcp14sd %xmm24,%xmm25,%xmm26{%k7}",},
{{0x62, 0x02, 0x7d, 0x48, 0x4e, 0xd1, }, 6, 0, "", "",
"62 02 7d 48 4e d1 \tvrsqrt14ps %zmm25,%zmm26",},
{{0x62, 0x02, 0xfd, 0x48, 0x4e, 0xe3, }, 6, 0, "", "",
"62 02 fd 48 4e e3 \tvrsqrt14pd %zmm27,%zmm28",},
{{0x62, 0x02, 0x35, 0x07, 0x4f, 0xd0, }, 6, 0, "", "",
"62 02 35 07 4f d0 \tvrsqrt14ss %xmm24,%xmm25,%xmm26{%k7}",},
{{0x62, 0x02, 0xb5, 0x07, 0x4f, 0xd0, }, 6, 0, "", "",
"62 02 b5 07 4f d0 \tvrsqrt14sd %xmm24,%xmm25,%xmm26{%k7}",},
{{0x62, 0xf2, 0x6d, 0x08, 0x50, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 50 d9 \tvpdpbusd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x50, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 50 d9 \tvpdpbusd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 50 d9 \tvpdpbusd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 50 9c c8 78 56 34 12 \tvpdpbusd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x50, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 50 9c c8 78 56 34 12 \tvpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x51, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 51 d9 \tvpdpbusds %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x51, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 51 d9 \tvpdpbusds %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 51 d9 \tvpdpbusds %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 51 9c c8 78 56 34 12 \tvpdpbusds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x51, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 51 9c c8 78 56 34 12 \tvpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6e, 0x08, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6e 08 52 d9 \tvdpbf16ps %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6e, 0x28, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6e 28 52 d9 \tvdpbf16ps %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6e 48 52 d9 \tvdpbf16ps %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6e 48 52 9c c8 78 56 34 12 \tvdpbf16ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6e, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6e 48 52 9c c8 78 56 34 12 \tvdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 52 d9 \tvpdpwssd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 52 d9 \tvpdpwssd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 52 d9 \tvpdpwssd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 52 9c c8 78 56 34 12 \tvpdpwssd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 52 9c c8 78 56 34 12 \tvpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0x20, }, 6, 0, "", "",
"62 f2 7f 48 52 20 \tvp4dpwssd (%rax),%zmm0,%zmm4",},
{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x52, 0x20, }, 7, 0, "", "",
"67 62 f2 7f 48 52 20 \tvp4dpwssd (%eax),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 48 52 a4 c8 78 56 34 12 \tvp4dpwssd 0x12345678(%rax,%rcx,8),%zmm0,%zmm4",},
{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x52, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7f 48 52 a4 c8 78 56 34 12 \tvp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x6d, 0x08, 0x53, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 53 d9 \tvpdpwssds %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x53, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 53 d9 \tvpdpwssds %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 53 d9 \tvpdpwssds %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 53 9c c8 78 56 34 12 \tvpdpwssds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x53, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 53 9c c8 78 56 34 12 \tvpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0x20, }, 6, 0, "", "",
"62 f2 7f 48 53 20 \tvp4dpwssds (%rax),%zmm0,%zmm4",},
{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x53, 0x20, }, 7, 0, "", "",
"67 62 f2 7f 48 53 20 \tvp4dpwssds (%eax),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 48 53 a4 c8 78 56 34 12 \tvp4dpwssds 0x12345678(%rax,%rcx,8),%zmm0,%zmm4",},
{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x53, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7f 48 53 a4 c8 78 56 34 12 \tvp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7d, 0x08, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 7d 08 54 d1 \tvpopcntb %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 7d 28 54 d1 \tvpopcntb %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 7d 48 54 d1 \tvpopcntb %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 54 94 c8 78 56 34 12 \tvpopcntb 0x12345678(%rax,%rcx,8),%zmm2",},
{{0x67, 0x62, 0xf2, 0x7d, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7d 48 54 94 c8 78 56 34 12 \tvpopcntb 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0xfd, 0x08, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 fd 08 54 d1 \tvpopcntw %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 fd 28 54 d1 \tvpopcntw %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 fd 48 54 d1 \tvpopcntw %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 54 94 c8 78 56 34 12 \tvpopcntw 0x12345678(%rax,%rcx,8),%zmm2",},
{{0x67, 0x62, 0xf2, 0xfd, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 fd 48 54 94 c8 78 56 34 12 \tvpopcntw 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0x7d, 0x08, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 7d 08 55 d1 \tvpopcntd %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 7d 28 55 d1 \tvpopcntd %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 7d 48 55 d1 \tvpopcntd %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 55 94 c8 78 56 34 12 \tvpopcntd 0x12345678(%rax,%rcx,8),%zmm2",},
{{0x67, 0x62, 0xf2, 0x7d, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7d 48 55 94 c8 78 56 34 12 \tvpopcntd 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0xfd, 0x08, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 fd 08 55 d1 \tvpopcntq %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 fd 28 55 d1 \tvpopcntq %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 fd 48 55 d1 \tvpopcntq %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 55 94 c8 78 56 34 12 \tvpopcntq 0x12345678(%rax,%rcx,8),%zmm2",},
{{0x67, 0x62, 0xf2, 0xfd, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 fd 48 55 94 c8 78 56 34 12 \tvpopcntq 0x12345678(%eax,%ecx,8),%zmm2",},
{{0xc4, 0xe2, 0x79, 0x59, 0xf4, }, 5, 0, "", "",
"c4 e2 79 59 f4 \tvpbroadcastq %xmm4,%xmm6",},
{{0x62, 0x02, 0x7d, 0x48, 0x59, 0xd3, }, 6, 0, "", "",
"62 02 7d 48 59 d3 \tvbroadcasti32x2 %xmm27,%zmm26",},
{{0xc4, 0xe2, 0x7d, 0x5a, 0x21, }, 5, 0, "", "",
"c4 e2 7d 5a 21 \tvbroadcasti128 (%rcx),%ymm4",},
{{0x62, 0x62, 0x7d, 0x48, 0x5a, 0x11, }, 6, 0, "", "",
"62 62 7d 48 5a 11 \tvbroadcasti32x4 (%rcx),%zmm26",},
{{0x62, 0x62, 0xfd, 0x48, 0x5a, 0x11, }, 6, 0, "", "",
"62 62 fd 48 5a 11 \tvbroadcasti64x2 (%rcx),%zmm26",},
{{0x62, 0x62, 0x7d, 0x48, 0x5b, 0x21, }, 6, 0, "", "",
"62 62 7d 48 5b 21 \tvbroadcasti32x8 (%rcx),%zmm28",},
{{0x62, 0x62, 0xfd, 0x48, 0x5b, 0x11, }, 6, 0, "", "",
"62 62 fd 48 5b 11 \tvbroadcasti64x4 (%rcx),%zmm26",},
{{0x62, 0xf2, 0x7d, 0x08, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 7d 08 62 d1 \tvpexpandb %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 7d 28 62 d1 \tvpexpandb %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 7d 48 62 d1 \tvpexpandb %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 62 94 c8 78 56 34 12 \tvpexpandb 0x12345678(%rax,%rcx,8),%zmm2",},
{{0x67, 0x62, 0xf2, 0x7d, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7d 48 62 94 c8 78 56 34 12 \tvpexpandb 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0xfd, 0x08, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 fd 08 62 d1 \tvpexpandw %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 fd 28 62 d1 \tvpexpandw %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 fd 48 62 d1 \tvpexpandw %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 62 94 c8 78 56 34 12 \tvpexpandw 0x12345678(%rax,%rcx,8),%zmm2",},
{{0x67, 0x62, 0xf2, 0xfd, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 fd 48 62 94 c8 78 56 34 12 \tvpexpandw 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0x7d, 0x08, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 7d 08 63 ca \tvpcompressb %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 7d 28 63 ca \tvpcompressb %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 7d 48 63 ca \tvpcompressb %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 63 94 c8 78 56 34 12 \tvpcompressb %zmm2,0x12345678(%rax,%rcx,8)",},
{{0x67, 0x62, 0xf2, 0x7d, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7d 48 63 94 c8 78 56 34 12 \tvpcompressb %zmm2,0x12345678(%eax,%ecx,8)",},
{{0x62, 0xf2, 0xfd, 0x08, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 fd 08 63 ca \tvpcompressw %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 fd 28 63 ca \tvpcompressw %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 fd 48 63 ca \tvpcompressw %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 63 94 c8 78 56 34 12 \tvpcompressw %zmm2,0x12345678(%rax,%rcx,8)",},
{{0x67, 0x62, 0xf2, 0xfd, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 fd 48 63 94 c8 78 56 34 12 \tvpcompressw %zmm2,0x12345678(%eax,%ecx,8)",},
{{0x62, 0x02, 0x25, 0x40, 0x64, 0xe2, }, 6, 0, "", "",
"62 02 25 40 64 e2 \tvpblendmd %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x64, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 64 e2 \tvpblendmq %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0x35, 0x40, 0x65, 0xd0, }, 6, 0, "", "",
"62 02 35 40 65 d0 \tvblendmps %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xa5, 0x40, 0x65, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 65 e2 \tvblendmpd %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0x25, 0x40, 0x66, 0xe2, }, 6, 0, "", "",
"62 02 25 40 66 e2 \tvpblendmb %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x66, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 66 e2 \tvpblendmw %zmm26,%zmm27,%zmm28",},
{{0x62, 0xf2, 0x6f, 0x08, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 6f 08 68 d9 \tvp2intersectd %xmm1,%xmm2,%k3",},
{{0x62, 0xf2, 0x6f, 0x28, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 6f 28 68 d9 \tvp2intersectd %ymm1,%ymm2,%k3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 6f 48 68 d9 \tvp2intersectd %zmm1,%zmm2,%k3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6f 48 68 9c c8 78 56 34 12 \tvp2intersectd 0x12345678(%rax,%rcx,8),%zmm2,%k3",},
{{0x67, 0x62, 0xf2, 0x6f, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6f 48 68 9c c8 78 56 34 12 \tvp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3",},
{{0x62, 0xf2, 0xef, 0x08, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 ef 08 68 d9 \tvp2intersectq %xmm1,%xmm2,%k3",},
{{0x62, 0xf2, 0xef, 0x28, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 ef 28 68 d9 \tvp2intersectq %ymm1,%ymm2,%k3",},
{{0x62, 0xf2, 0xef, 0x48, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 ef 48 68 d9 \tvp2intersectq %zmm1,%zmm2,%k3",},
{{0x62, 0xf2, 0xef, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ef 48 68 9c c8 78 56 34 12 \tvp2intersectq 0x12345678(%rax,%rcx,8),%zmm2,%k3",},
{{0x67, 0x62, 0xf2, 0xef, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 ef 48 68 9c c8 78 56 34 12 \tvp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3",},
{{0x62, 0xf2, 0xed, 0x08, 0x70, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 70 d9 \tvpshldvw %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x70, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 70 d9 \tvpshldvw %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x70, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 70 d9 \tvpshldvw %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x70, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 70 9c c8 78 56 34 12 \tvpshldvw 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0xed, 0x48, 0x70, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 ed 48 70 9c c8 78 56 34 12 \tvpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 71 d9 \tvpshldvd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 71 d9 \tvpshldvd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 71 d9 \tvpshldvd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 71 9c c8 78 56 34 12 \tvpshldvd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 71 9c c8 78 56 34 12 \tvpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x08, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 71 d9 \tvpshldvq %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 71 d9 \tvpshldvq %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 71 d9 \tvpshldvq %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 71 9c c8 78 56 34 12 \tvpshldvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0xed, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 ed 48 71 9c c8 78 56 34 12 \tvpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6f, 0x08, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 6f 08 72 d9 \tvcvtne2ps2bf16 %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6f, 0x28, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 6f 28 72 d9 \tvcvtne2ps2bf16 %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 6f 48 72 d9 \tvcvtne2ps2bf16 %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6f 48 72 9c c8 78 56 34 12 \tvcvtne2ps2bf16 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6f, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6f 48 72 9c c8 78 56 34 12 \tvcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7e, 0x08, 0x72, 0xd1, }, 6, 0, "", "",
"62 f2 7e 08 72 d1 \tvcvtneps2bf16 %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7e, 0x28, 0x72, 0xd1, }, 6, 0, "", "",
"62 f2 7e 28 72 d1 \tvcvtneps2bf16 %ymm1,%xmm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x72, 0xd1, }, 6, 0, "", "",
"62 f2 7e 48 72 d1 \tvcvtneps2bf16 %zmm1,%ymm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x72, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7e 48 72 94 c8 78 56 34 12 \tvcvtneps2bf16 0x12345678(%rax,%rcx,8),%ymm2",},
{{0x67, 0x62, 0xf2, 0x7e, 0x48, 0x72, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 7e 48 72 94 c8 78 56 34 12 \tvcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2",},
{{0x62, 0xf2, 0xed, 0x08, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 72 d9 \tvpshrdvw %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 72 d9 \tvpshrdvw %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 72 d9 \tvpshrdvw %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 72 9c c8 78 56 34 12 \tvpshrdvw 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0xed, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 ed 48 72 9c c8 78 56 34 12 \tvpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 73 d9 \tvpshrdvd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 73 d9 \tvpshrdvd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 73 d9 \tvpshrdvd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 73 9c c8 78 56 34 12 \tvpshrdvd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 73 9c c8 78 56 34 12 \tvpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x08, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 73 d9 \tvpshrdvq %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 73 d9 \tvpshrdvq %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 73 d9 \tvpshrdvq %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 73 9c c8 78 56 34 12 \tvpshrdvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0xed, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 ed 48 73 9c c8 78 56 34 12 \tvpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0x02, 0x35, 0x40, 0x75, 0xd0, }, 6, 0, "", "",
"62 02 35 40 75 d0 \tvpermi2b %zmm24,%zmm25,%zmm26",},
{{0x62, 0x02, 0xa5, 0x40, 0x75, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 75 e2 \tvpermi2w %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0x25, 0x40, 0x76, 0xe2, }, 6, 0, "", "",
"62 02 25 40 76 e2 \tvpermi2d %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x76, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 76 e2 \tvpermi2q %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0x25, 0x40, 0x77, 0xe2, }, 6, 0, "", "",
"62 02 25 40 77 e2 \tvpermi2ps %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x77, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 77 e2 \tvpermi2pd %zmm26,%zmm27,%zmm28",},
{{0x62, 0x62, 0x7d, 0x08, 0x7a, 0xf0, }, 6, 0, "", "",
"62 62 7d 08 7a f0 \tvpbroadcastb %eax,%xmm30",},
{{0x62, 0x62, 0x7d, 0x08, 0x7b, 0xf0, }, 6, 0, "", "",
"62 62 7d 08 7b f0 \tvpbroadcastw %eax,%xmm30",},
{{0x62, 0x62, 0x7d, 0x08, 0x7c, 0xf0, }, 6, 0, "", "",
"62 62 7d 08 7c f0 \tvpbroadcastd %eax,%xmm30",},
{{0x62, 0x62, 0xfd, 0x48, 0x7c, 0xf0, }, 6, 0, "", "",
"62 62 fd 48 7c f0 \tvpbroadcastq %rax,%zmm30",},
{{0x62, 0x02, 0x25, 0x40, 0x7d, 0xe2, }, 6, 0, "", "",
"62 02 25 40 7d e2 \tvpermt2b %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x7d, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 7d e2 \tvpermt2w %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0x25, 0x40, 0x7e, 0xe2, }, 6, 0, "", "",
"62 02 25 40 7e e2 \tvpermt2d %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x7e, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 7e e2 \tvpermt2q %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0x25, 0x40, 0x7f, 0xe2, }, 6, 0, "", "",
"62 02 25 40 7f e2 \tvpermt2ps %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x7f, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 7f e2 \tvpermt2pd %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x83, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 83 e2 \tvpmultishiftqb %zmm26,%zmm27,%zmm28",},
{{0x62, 0x62, 0x7d, 0x48, 0x88, 0x11, }, 6, 0, "", "",
"62 62 7d 48 88 11 \tvexpandps (%rcx),%zmm26",},
{{0x62, 0x62, 0xfd, 0x48, 0x88, 0x21, }, 6, 0, "", "",
"62 62 fd 48 88 21 \tvexpandpd (%rcx),%zmm28",},
{{0x62, 0x62, 0x7d, 0x48, 0x89, 0x21, }, 6, 0, "", "",
"62 62 7d 48 89 21 \tvpexpandd (%rcx),%zmm28",},
{{0x62, 0x62, 0xfd, 0x48, 0x89, 0x11, }, 6, 0, "", "",
"62 62 fd 48 89 11 \tvpexpandq (%rcx),%zmm26",},
{{0x62, 0x62, 0x7d, 0x48, 0x8a, 0x21, }, 6, 0, "", "",
"62 62 7d 48 8a 21 \tvcompressps %zmm28,(%rcx)",},
{{0x62, 0x62, 0xfd, 0x48, 0x8a, 0x21, }, 6, 0, "", "",
"62 62 fd 48 8a 21 \tvcompresspd %zmm28,(%rcx)",},
{{0x62, 0x62, 0x7d, 0x48, 0x8b, 0x21, }, 6, 0, "", "",
"62 62 7d 48 8b 21 \tvpcompressd %zmm28,(%rcx)",},
{{0x62, 0x62, 0xfd, 0x48, 0x8b, 0x11, }, 6, 0, "", "",
"62 62 fd 48 8b 11 \tvpcompressq %zmm26,(%rcx)",},
{{0x62, 0x02, 0x25, 0x40, 0x8d, 0xe2, }, 6, 0, "", "",
"62 02 25 40 8d e2 \tvpermb %zmm26,%zmm27,%zmm28",},
{{0x62, 0x02, 0xa5, 0x40, 0x8d, 0xe2, }, 6, 0, "", "",
"62 02 a5 40 8d e2 \tvpermw %zmm26,%zmm27,%zmm28",},
{{0x62, 0xf2, 0x6d, 0x08, 0x8f, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 8f d9 \tvpshufbitqmb %xmm1,%xmm2,%k3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x8f, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 8f d9 \tvpshufbitqmb %ymm1,%ymm2,%k3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0xd9, }, 6, 0, "", "",
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"62 f2 6d 48 dd 9c c8 78 56 34 12 \tvaesenclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xdd, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 dd 9c c8 78 56 34 12 \tvaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0x69, 0xde, 0xd9, }, 5, 0, "", "",
"c4 e2 69 de d9 \tvaesdec %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xde, 0xd9, }, 5, 0, "", "",
"c4 e2 6d de d9 \tvaesdec %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 de d9 \tvaesdec %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 de 9c c8 78 56 34 12 \tvaesdec 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xde, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 de 9c c8 78 56 34 12 \tvaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0x69, 0xdf, 0xd9, }, 5, 0, "", "",
"c4 e2 69 df d9 \tvaesdeclast %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xdf, 0xd9, }, 5, 0, "", "",
"c4 e2 6d df d9 \tvaesdeclast %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 df d9 \tvaesdeclast %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 df 9c c8 78 56 34 12 \tvaesdeclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",},
{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xdf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f2 6d 48 df 9c c8 78 56 34 12 \tvaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0x03, 0x15, 0x40, 0x03, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 15 40 03 f4 12 \tvalignd $0x12,%zmm28,%zmm29,%zmm30",},
{{0x62, 0x03, 0xad, 0x40, 0x03, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 03 d9 12 \tvalignq $0x12,%zmm25,%zmm26,%zmm27",},
{{0xc4, 0xe3, 0x7d, 0x08, 0xd6, 0x05, }, 6, 0, "", "",
"c4 e3 7d 08 d6 05 \tvroundps $0x5,%ymm6,%ymm2",},
{{0x62, 0x03, 0x7d, 0x48, 0x08, 0xd1, 0x12, }, 7, 0, "", "",
"62 03 7d 48 08 d1 12 \tvrndscaleps $0x12,%zmm25,%zmm26",},
{{0xc4, 0xe3, 0x7d, 0x09, 0xd6, 0x05, }, 6, 0, "", "",
"c4 e3 7d 09 d6 05 \tvroundpd $0x5,%ymm6,%ymm2",},
{{0x62, 0x03, 0xfd, 0x48, 0x09, 0xd1, 0x12, }, 7, 0, "", "",
"62 03 fd 48 09 d1 12 \tvrndscalepd $0x12,%zmm25,%zmm26",},
{{0xc4, 0xe3, 0x49, 0x0a, 0xd4, 0x05, }, 6, 0, "", "",
"c4 e3 49 0a d4 05 \tvroundss $0x5,%xmm4,%xmm6,%xmm2",},
{{0x62, 0x03, 0x35, 0x07, 0x0a, 0xd0, 0x12, }, 7, 0, "", "",
"62 03 35 07 0a d0 12 \tvrndscaless $0x12,%xmm24,%xmm25,%xmm26{%k7}",},
{{0xc4, 0xe3, 0x49, 0x0b, 0xd4, 0x05, }, 6, 0, "", "",
"c4 e3 49 0b d4 05 \tvroundsd $0x5,%xmm4,%xmm6,%xmm2",},
{{0x62, 0x03, 0xb5, 0x07, 0x0b, 0xd0, 0x12, }, 7, 0, "", "",
"62 03 b5 07 0b d0 12 \tvrndscalesd $0x12,%xmm24,%xmm25,%xmm26{%k7}",},
{{0xc4, 0xe3, 0x5d, 0x18, 0xf4, 0x05, }, 6, 0, "", "",
"c4 e3 5d 18 f4 05 \tvinsertf128 $0x5,%xmm4,%ymm4,%ymm6",},
{{0x62, 0x03, 0x35, 0x47, 0x18, 0xd0, 0x12, }, 7, 0, "", "",
"62 03 35 47 18 d0 12 \tvinsertf32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}",},
{{0x62, 0x03, 0xb5, 0x47, 0x18, 0xd0, 0x12, }, 7, 0, "", "",
"62 03 b5 47 18 d0 12 \tvinsertf64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}",},
{{0xc4, 0xe3, 0x7d, 0x19, 0xe4, 0x05, }, 6, 0, "", "",
"c4 e3 7d 19 e4 05 \tvextractf128 $0x5,%ymm4,%xmm4",},
{{0x62, 0x03, 0x7d, 0x4f, 0x19, 0xca, 0x12, }, 7, 0, "", "",
"62 03 7d 4f 19 ca 12 \tvextractf32x4 $0x12,%zmm25,%xmm26{%k7}",},
{{0x62, 0x03, 0xfd, 0x4f, 0x19, 0xca, 0x12, }, 7, 0, "", "",
"62 03 fd 4f 19 ca 12 \tvextractf64x2 $0x12,%zmm25,%xmm26{%k7}",},
{{0x62, 0x03, 0x2d, 0x47, 0x1a, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 47 1a d9 12 \tvinsertf32x8 $0x12,%ymm25,%zmm26,%zmm27{%k7}",},
{{0x62, 0x03, 0x95, 0x47, 0x1a, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 47 1a f4 12 \tvinsertf64x4 $0x12,%ymm28,%zmm29,%zmm30{%k7}",},
{{0x62, 0x03, 0x7d, 0x4f, 0x1b, 0xee, 0x12, }, 7, 0, "", "",
"62 03 7d 4f 1b ee 12 \tvextractf32x8 $0x12,%zmm29,%ymm30{%k7}",},
{{0x62, 0x03, 0xfd, 0x4f, 0x1b, 0xd3, 0x12, }, 7, 0, "", "",
"62 03 fd 4f 1b d3 12 \tvextractf64x4 $0x12,%zmm26,%ymm27{%k7}",},
{{0x62, 0x93, 0x0d, 0x40, 0x1e, 0xed, 0x12, }, 7, 0, "", "",
"62 93 0d 40 1e ed 12 \tvpcmpud $0x12,%zmm29,%zmm30,%k5",},
{{0x62, 0x93, 0xa5, 0x40, 0x1e, 0xea, 0x12, }, 7, 0, "", "",
"62 93 a5 40 1e ea 12 \tvpcmpuq $0x12,%zmm26,%zmm27,%k5",},
{{0x62, 0x93, 0x0d, 0x40, 0x1f, 0xed, 0x12, }, 7, 0, "", "",
"62 93 0d 40 1f ed 12 \tvpcmpd $0x12,%zmm29,%zmm30,%k5",},
{{0x62, 0x93, 0xa5, 0x40, 0x1f, 0xea, 0x12, }, 7, 0, "", "",
"62 93 a5 40 1f ea 12 \tvpcmpq $0x12,%zmm26,%zmm27,%k5",},
{{0x62, 0x03, 0x15, 0x40, 0x23, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 15 40 23 f4 12 \tvshuff32x4 $0x12,%zmm28,%zmm29,%zmm30",},
{{0x62, 0x03, 0xad, 0x40, 0x23, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 23 d9 12 \tvshuff64x2 $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0x03, 0x15, 0x40, 0x25, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 15 40 25 f4 12 \tvpternlogd $0x12,%zmm28,%zmm29,%zmm30",},
{{0x62, 0x03, 0x95, 0x40, 0x25, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 40 25 f4 12 \tvpternlogq $0x12,%zmm28,%zmm29,%zmm30",},
{{0x62, 0x03, 0x7d, 0x48, 0x26, 0xda, 0x12, }, 7, 0, "", "",
"62 03 7d 48 26 da 12 \tvgetmantps $0x12,%zmm26,%zmm27",},
{{0x62, 0x03, 0xfd, 0x48, 0x26, 0xf5, 0x12, }, 7, 0, "", "",
"62 03 fd 48 26 f5 12 \tvgetmantpd $0x12,%zmm29,%zmm30",},
{{0x62, 0x03, 0x2d, 0x07, 0x27, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 07 27 d9 12 \tvgetmantss $0x12,%xmm25,%xmm26,%xmm27{%k7}",},
{{0x62, 0x03, 0x95, 0x07, 0x27, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 07 27 f4 12 \tvgetmantsd $0x12,%xmm28,%xmm29,%xmm30{%k7}",},
{{0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x05, }, 6, 0, "", "",
"c4 e3 5d 38 f4 05 \tvinserti128 $0x5,%xmm4,%ymm4,%ymm6",},
{{0x62, 0x03, 0x35, 0x47, 0x38, 0xd0, 0x12, }, 7, 0, "", "",
"62 03 35 47 38 d0 12 \tvinserti32x4 $0x12,%xmm24,%zmm25,%zmm26{%k7}",},
{{0x62, 0x03, 0xb5, 0x47, 0x38, 0xd0, 0x12, }, 7, 0, "", "",
"62 03 b5 47 38 d0 12 \tvinserti64x2 $0x12,%xmm24,%zmm25,%zmm26{%k7}",},
{{0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x05, }, 6, 0, "", "",
"c4 e3 7d 39 e6 05 \tvextracti128 $0x5,%ymm4,%xmm6",},
{{0x62, 0x03, 0x7d, 0x4f, 0x39, 0xca, 0x12, }, 7, 0, "", "",
"62 03 7d 4f 39 ca 12 \tvextracti32x4 $0x12,%zmm25,%xmm26{%k7}",},
{{0x62, 0x03, 0xfd, 0x4f, 0x39, 0xca, 0x12, }, 7, 0, "", "",
"62 03 fd 4f 39 ca 12 \tvextracti64x2 $0x12,%zmm25,%xmm26{%k7}",},
{{0x62, 0x03, 0x15, 0x47, 0x3a, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 15 47 3a f4 12 \tvinserti32x8 $0x12,%ymm28,%zmm29,%zmm30{%k7}",},
{{0x62, 0x03, 0xad, 0x47, 0x3a, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 47 3a d9 12 \tvinserti64x4 $0x12,%ymm25,%zmm26,%zmm27{%k7}",},
{{0x62, 0x03, 0x7d, 0x4f, 0x3b, 0xee, 0x12, }, 7, 0, "", "",
"62 03 7d 4f 3b ee 12 \tvextracti32x8 $0x12,%zmm29,%ymm30{%k7}",},
{{0x62, 0x03, 0xfd, 0x4f, 0x3b, 0xd3, 0x12, }, 7, 0, "", "",
"62 03 fd 4f 3b d3 12 \tvextracti64x4 $0x12,%zmm26,%ymm27{%k7}",},
{{0x62, 0x93, 0x0d, 0x40, 0x3e, 0xed, 0x12, }, 7, 0, "", "",
"62 93 0d 40 3e ed 12 \tvpcmpub $0x12,%zmm29,%zmm30,%k5",},
{{0x62, 0x93, 0xa5, 0x40, 0x3e, 0xea, 0x12, }, 7, 0, "", "",
"62 93 a5 40 3e ea 12 \tvpcmpuw $0x12,%zmm26,%zmm27,%k5",},
{{0x62, 0x93, 0x0d, 0x40, 0x3f, 0xed, 0x12, }, 7, 0, "", "",
"62 93 0d 40 3f ed 12 \tvpcmpb $0x12,%zmm29,%zmm30,%k5",},
{{0x62, 0x93, 0xa5, 0x40, 0x3f, 0xea, 0x12, }, 7, 0, "", "",
"62 93 a5 40 3f ea 12 \tvpcmpw $0x12,%zmm26,%zmm27,%k5",},
{{0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x05, }, 6, 0, "", "",
"c4 e3 4d 42 d4 05 \tvmpsadbw $0x5,%ymm4,%ymm6,%ymm2",},
{{0x62, 0xf3, 0x55, 0x48, 0x42, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 55 48 42 f4 12 \tvdbpsadbw $0x12,%zmm4,%zmm5,%zmm6",},
{{0x62, 0x03, 0x2d, 0x40, 0x43, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 40 43 d9 12 \tvshufi32x4 $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0x03, 0x95, 0x40, 0x43, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 40 43 f4 12 \tvshufi64x2 $0x12,%zmm28,%zmm29,%zmm30",},
{{0xc4, 0xe3, 0x69, 0x44, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 69 44 d9 12 \tvpclmulqdq $0x12,%xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe3, 0x6d, 0x44, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 6d 44 d9 12 \tvpclmulqdq $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0x6d, 0x48, 0x44, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 48 44 d9 12 \tvpclmulqdq $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0x2d, 0x40, 0x44, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 40 44 d9 12 \tvpclmulqdq $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0x03, 0x2d, 0x40, 0x50, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 40 50 d9 12 \tvrangeps $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0x03, 0x95, 0x40, 0x50, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 40 50 f4 12 \tvrangepd $0x12,%zmm28,%zmm29,%zmm30",},
{{0x62, 0x03, 0x2d, 0x00, 0x51, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 00 51 d9 12 \tvrangess $0x12,%xmm25,%xmm26,%xmm27",},
{{0x62, 0x03, 0x95, 0x00, 0x51, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 00 51 f4 12 \tvrangesd $0x12,%xmm28,%xmm29,%xmm30",},
{{0x62, 0x03, 0x15, 0x40, 0x54, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 15 40 54 f4 12 \tvfixupimmps $0x12,%zmm28,%zmm29,%zmm30",},
{{0x62, 0x03, 0xad, 0x40, 0x54, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 54 d9 12 \tvfixupimmpd $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0x03, 0x15, 0x07, 0x55, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 15 07 55 f4 12 \tvfixupimmss $0x12,%xmm28,%xmm29,%xmm30{%k7}",},
{{0x62, 0x03, 0xad, 0x07, 0x55, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 07 55 d9 12 \tvfixupimmsd $0x12,%xmm25,%xmm26,%xmm27{%k7}",},
{{0x62, 0x03, 0x7d, 0x48, 0x56, 0xda, 0x12, }, 7, 0, "", "",
"62 03 7d 48 56 da 12 \tvreduceps $0x12,%zmm26,%zmm27",},
{{0x62, 0x03, 0xfd, 0x48, 0x56, 0xf5, 0x12, }, 7, 0, "", "",
"62 03 fd 48 56 f5 12 \tvreducepd $0x12,%zmm29,%zmm30",},
{{0x62, 0x03, 0x2d, 0x00, 0x57, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 00 57 d9 12 \tvreducess $0x12,%xmm25,%xmm26,%xmm27",},
{{0x62, 0x03, 0x95, 0x00, 0x57, 0xf4, 0x12, }, 7, 0, "", "",
"62 03 95 00 57 f4 12 \tvreducesd $0x12,%xmm28,%xmm29,%xmm30",},
{{0x62, 0x93, 0x7d, 0x48, 0x66, 0xeb, 0x12, }, 7, 0, "", "",
"62 93 7d 48 66 eb 12 \tvfpclassps $0x12,%zmm27,%k5",},
{{0x62, 0x93, 0xfd, 0x48, 0x66, 0xee, 0x12, }, 7, 0, "", "",
"62 93 fd 48 66 ee 12 \tvfpclasspd $0x12,%zmm30,%k5",},
{{0x62, 0x93, 0x7d, 0x08, 0x67, 0xeb, 0x12, }, 7, 0, "", "",
"62 93 7d 08 67 eb 12 \tvfpclassss $0x12,%xmm27,%k5",},
{{0x62, 0x93, 0xfd, 0x08, 0x67, 0xee, 0x12, }, 7, 0, "", "",
"62 93 fd 08 67 ee 12 \tvfpclasssd $0x12,%xmm30,%k5",},
{{0x62, 0xf3, 0xed, 0x08, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 70 d9 12 \tvpshldw $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 70 d9 12 \tvpshldw $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 70 d9 12 \tvpshldw $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0xad, 0x40, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 70 d9 12 \tvpshldw $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0xf3, 0x6d, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 08 71 d9 12 \tvpshldd $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0x6d, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 28 71 d9 12 \tvpshldd $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0x6d, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 48 71 d9 12 \tvpshldd $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0x2d, 0x40, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 40 71 d9 12 \tvpshldd $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0xf3, 0xed, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 71 d9 12 \tvpshldq $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 71 d9 12 \tvpshldq $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 71 d9 12 \tvpshldq $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0xad, 0x40, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 71 d9 12 \tvpshldq $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0xf3, 0xed, 0x08, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 72 d9 12 \tvpshrdw $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 72 d9 12 \tvpshrdw $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 72 d9 12 \tvpshrdw $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0xad, 0x40, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 72 d9 12 \tvpshrdw $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0xf3, 0x6d, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 08 73 d9 12 \tvpshrdd $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0x6d, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 28 73 d9 12 \tvpshrdd $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0x6d, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 48 73 d9 12 \tvpshrdd $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0x2d, 0x40, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 2d 40 73 d9 12 \tvpshrdd $0x12,%zmm25,%zmm26,%zmm27",},
{{0x62, 0xf3, 0xed, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 73 d9 12 \tvpshrdq $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 73 d9 12 \tvpshrdq $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 73 d9 12 \tvpshrdq $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0xad, 0x40, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 73 d9 12 \tvpshrdq $0x12,%zmm25,%zmm26,%zmm27",},
{{0x66, 0x0f, 0x3a, 0xce, 0xd9, 0x12, }, 6, 0, "", "",
"66 0f 3a ce d9 12 \tgf2p8affineqb $0x12,%xmm1,%xmm3",},
{{0xc4, 0xe3, 0xe9, 0xce, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 e9 ce d9 12 \tvgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe3, 0xed, 0xce, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 ed ce d9 12 \tvgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0xce, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 ce d9 12 \tvgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0x03, 0xad, 0x40, 0xce, 0xd9, 0x12, }, 7, 0, "", "",
"62 03 ad 40 ce d9 12 \tvgf2p8affineqb $0x12,%zmm25,%zmm26,%zmm27",},
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{{0xf2, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
"f2 41 0f 1b 00 \tbndcn (%r8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 04 25 78 56 34 12 \tbndcn 0x12345678,%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
"f2 0f 1b 18 \tbndcn (%rax),%bnd3",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
"f2 0f 1b 04 01 \tbndcn (%rcx,%rax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%rax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
"f2 0f 1b 04 08 \tbndcn (%rax,%rcx,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
"f2 0f 1b 04 c8 \tbndcn (%rax,%rcx,8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
"f2 0f 1b 40 12 \tbndcn 0x12(%rax),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
"f2 0f 1b 45 12 \tbndcn 0x12(%rbp),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 01 12 \tbndcn 0x12(%rcx,%rax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 05 12 \tbndcn 0x12(%rbp,%rax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 08 12 \tbndcn 0x12(%rax,%rcx,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 c8 12 \tbndcn 0x12(%rax,%rcx,8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%rax),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%rbp),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%rcx,%rax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%rbp,%rax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "",
"f2 0f 1b c0 \tbndcn %rax,%bnd0",},
{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
"66 0f 1a 00 \tbndmov (%rax),%bnd0",},
{{0x66, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
"66 41 0f 1a 00 \tbndmov (%r8),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 04 25 78 56 34 12 \tbndmov 0x12345678,%bnd0",},
{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
"66 0f 1a 18 \tbndmov (%rax),%bnd3",},
{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
"66 0f 1a 04 01 \tbndmov (%rcx,%rax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%rax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
"66 0f 1a 04 08 \tbndmov (%rax,%rcx,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
"66 0f 1a 04 c8 \tbndmov (%rax,%rcx,8),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
"66 0f 1a 40 12 \tbndmov 0x12(%rax),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
"66 0f 1a 45 12 \tbndmov 0x12(%rbp),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 01 12 \tbndmov 0x12(%rcx,%rax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 05 12 \tbndmov 0x12(%rbp,%rax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 08 12 \tbndmov 0x12(%rax,%rcx,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 c8 12 \tbndmov 0x12(%rax,%rcx,8),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%rax),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%rbp),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%rcx,%rax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%rbp,%rax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,8),%bnd0",},
{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"66 0f 1b 00 \tbndmov %bnd0,(%rax)",},
{{0x66, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
"66 41 0f 1b 00 \tbndmov %bnd0,(%r8)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 04 25 78 56 34 12 \tbndmov %bnd0,0x12345678",},
{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
"66 0f 1b 18 \tbndmov %bnd3,(%rax)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
"66 0f 1b 04 01 \tbndmov %bnd0,(%rcx,%rax,1)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%rax,1)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
"66 0f 1b 04 08 \tbndmov %bnd0,(%rax,%rcx,1)",},
{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
"66 0f 1b 04 c8 \tbndmov %bnd0,(%rax,%rcx,8)",},
{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%rax)",},
{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%rbp)",},
{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%rcx,%rax,1)",},
{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%rbp,%rax,1)",},
{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%rax,%rcx,1)",},
{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%rax,%rcx,8)",},
{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax)",},
{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp)",},
{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%rcx,%rax,1)",},
{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 05 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp,%rax,1)",},
{{0x66, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 08 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,1)",},
{{0x66, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 c8 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,8)",},
{{0x66, 0x0f, 0x1a, 0xc8, }, 4, 0, "", "",
"66 0f 1a c8 \tbndmov %bnd0,%bnd1",},
{{0x66, 0x0f, 0x1a, 0xc1, }, 4, 0, "", "",
"66 0f 1a c1 \tbndmov %bnd1,%bnd0",},
{{0x0f, 0x1a, 0x00, }, 3, 0, "", "",
"0f 1a 00 \tbndldx (%rax),%bnd0",},
{{0x41, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
"41 0f 1a 00 \tbndldx (%r8),%bnd0",},
{{0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 04 25 78 56 34 12 \tbndldx 0x12345678,%bnd0",},
{{0x0f, 0x1a, 0x18, }, 3, 0, "", "",
"0f 1a 18 \tbndldx (%rax),%bnd3",},
{{0x0f, 0x1a, 0x04, 0x01, }, 4, 0, "", "",
"0f 1a 04 01 \tbndldx (%rcx,%rax,1),%bnd0",},
{{0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 04 05 78 56 34 12 \tbndldx 0x12345678(,%rax,1),%bnd0",},
{{0x0f, 0x1a, 0x04, 0x08, }, 4, 0, "", "",
"0f 1a 04 08 \tbndldx (%rax,%rcx,1),%bnd0",},
{{0x0f, 0x1a, 0x40, 0x12, }, 4, 0, "", "",
"0f 1a 40 12 \tbndldx 0x12(%rax),%bnd0",},
{{0x0f, 0x1a, 0x45, 0x12, }, 4, 0, "", "",
"0f 1a 45 12 \tbndldx 0x12(%rbp),%bnd0",},
{{0x0f, 0x1a, 0x44, 0x01, 0x12, }, 5, 0, "", "",
"0f 1a 44 01 12 \tbndldx 0x12(%rcx,%rax,1),%bnd0",},
{{0x0f, 0x1a, 0x44, 0x05, 0x12, }, 5, 0, "", "",
"0f 1a 44 05 12 \tbndldx 0x12(%rbp,%rax,1),%bnd0",},
{{0x0f, 0x1a, 0x44, 0x08, 0x12, }, 5, 0, "", "",
"0f 1a 44 08 12 \tbndldx 0x12(%rax,%rcx,1),%bnd0",},
{{0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1a 80 78 56 34 12 \tbndldx 0x12345678(%rax),%bnd0",},
{{0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1a 85 78 56 34 12 \tbndldx 0x12345678(%rbp),%bnd0",},
{{0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 84 01 78 56 34 12 \tbndldx 0x12345678(%rcx,%rax,1),%bnd0",},
{{0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 84 05 78 56 34 12 \tbndldx 0x12345678(%rbp,%rax,1),%bnd0",},
{{0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 84 08 78 56 34 12 \tbndldx 0x12345678(%rax,%rcx,1),%bnd0",},
{{0x0f, 0x1b, 0x00, }, 3, 0, "", "",
"0f 1b 00 \tbndstx %bnd0,(%rax)",},
{{0x41, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"41 0f 1b 00 \tbndstx %bnd0,(%r8)",},
{{0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 04 25 78 56 34 12 \tbndstx %bnd0,0x12345678",},
{{0x0f, 0x1b, 0x18, }, 3, 0, "", "",
"0f 1b 18 \tbndstx %bnd3,(%rax)",},
{{0x0f, 0x1b, 0x04, 0x01, }, 4, 0, "", "",
"0f 1b 04 01 \tbndstx %bnd0,(%rcx,%rax,1)",},
{{0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 04 05 78 56 34 12 \tbndstx %bnd0,0x12345678(,%rax,1)",},
{{0x0f, 0x1b, 0x04, 0x08, }, 4, 0, "", "",
"0f 1b 04 08 \tbndstx %bnd0,(%rax,%rcx,1)",},
{{0x0f, 0x1b, 0x40, 0x12, }, 4, 0, "", "",
"0f 1b 40 12 \tbndstx %bnd0,0x12(%rax)",},
{{0x0f, 0x1b, 0x45, 0x12, }, 4, 0, "", "",
"0f 1b 45 12 \tbndstx %bnd0,0x12(%rbp)",},
{{0x0f, 0x1b, 0x44, 0x01, 0x12, }, 5, 0, "", "",
"0f 1b 44 01 12 \tbndstx %bnd0,0x12(%rcx,%rax,1)",},
{{0x0f, 0x1b, 0x44, 0x05, 0x12, }, 5, 0, "", "",
"0f 1b 44 05 12 \tbndstx %bnd0,0x12(%rbp,%rax,1)",},
{{0x0f, 0x1b, 0x44, 0x08, 0x12, }, 5, 0, "", "",
"0f 1b 44 08 12 \tbndstx %bnd0,0x12(%rax,%rcx,1)",},
{{0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1b 80 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax)",},
{{0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1b 85 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp)",},
{{0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 84 01 78 56 34 12 \tbndstx %bnd0,0x12345678(%rcx,%rax,1)",},
{{0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 84 05 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp,%rax,1)",},
{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",},
{{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional",
"f2 e8 00 00 00 00 \tbnd callq f22 <main+0xf22>",},
{{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",
"67 f2 ff 10 \tbnd callq *(%eax)",},
{{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
"f2 c3 \tbnd retq ",},
{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
"f2 e9 00 00 00 00 \tbnd jmpq f2e <main+0xf2e>",},
{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
"f2 e9 00 00 00 00 \tbnd jmpq f34 <main+0xf34>",},
{{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect",
"67 f2 ff 21 \tbnd jmpq *(%ecx)",},
{{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional",
"f2 0f 85 00 00 00 00 \tbnd jne f3f <main+0xf3f>",},
{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
"0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
"0f 3a cc d7 91 \tsha1rnds4 $0x91,%xmm7,%xmm2",},
{{0x41, 0x0f, 0x3a, 0xcc, 0xc0, 0x91, }, 6, 0, "", "",
"41 0f 3a cc c0 91 \tsha1rnds4 $0x91,%xmm8,%xmm0",},
{{0x44, 0x0f, 0x3a, 0xcc, 0xc7, 0x91, }, 6, 0, "", "",
"44 0f 3a cc c7 91 \tsha1rnds4 $0x91,%xmm7,%xmm8",},
{{0x45, 0x0f, 0x3a, 0xcc, 0xc7, 0x91, }, 6, 0, "", "",
"45 0f 3a cc c7 91 \tsha1rnds4 $0x91,%xmm15,%xmm8",},
{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
"0f 3a cc 00 91 \tsha1rnds4 $0x91,(%rax),%xmm0",},
{{0x41, 0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 6, 0, "", "",
"41 0f 3a cc 00 91 \tsha1rnds4 $0x91,(%r8),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
"0f 3a cc 04 25 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
"0f 3a cc 18 91 \tsha1rnds4 $0x91,(%rax),%xmm3",},
{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
"0f 3a cc 04 01 91 \tsha1rnds4 $0x91,(%rcx,%rax,1),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%rax,1),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
"0f 3a cc 04 08 91 \tsha1rnds4 $0x91,(%rax,%rcx,1),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
"0f 3a cc 04 c8 91 \tsha1rnds4 $0x91,(%rax,%rcx,8),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
"0f 3a cc 40 12 91 \tsha1rnds4 $0x91,0x12(%rax),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
"0f 3a cc 45 12 91 \tsha1rnds4 $0x91,0x12(%rbp),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%rcx,%rax,1),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%rbp,%rax,1),%xmm0",},
{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0xc1, }, 4, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0xd7, }, 4, 0, "", "",
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{{0x41, 0x0f, 0x38, 0xcd, 0xc0, }, 5, 0, "", "",
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{{0x44, 0x0f, 0x38, 0xcd, 0xc7, }, 5, 0, "", "",
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{{0x45, 0x0f, 0x38, 0xcd, 0xc7, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x00, }, 4, 0, "", "",
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{{0x41, 0x0f, 0x38, 0xcd, 0x00, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x18, }, 4, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x04, 0x01, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "",
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{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
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{{0x66, 0x41, 0x0f, 0xae, 0x38, }, 5, 0, "", "",
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{{0x66, 0x0f, 0xae, 0x3c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f ae 3c 25 78 56 34 12 \tclflushopt 0x12345678",},
{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%rax,%rcx,8)",},
{{0x66, 0x41, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"66 41 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
"0f ae 38 \tclflush (%rax)",},
{{0x41, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
"41 0f ae 38 \tclflush (%r8)",},
{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
"0f ae f8 \tsfence ",},
{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
"66 0f ae 30 \tclwb (%rax)",},
{{0x66, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "",
"66 41 0f ae 30 \tclwb (%r8)",},
{{0x66, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f ae 34 25 78 56 34 12 \tclwb 0x12345678",},
{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%rax,%rcx,8)",},
{{0x66, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"66 41 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
"0f ae 30 \txsaveopt (%rax)",},
{{0x41, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
"41 0f ae 30 \txsaveopt (%r8)",},
{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
"0f ae f0 \tmfence ",},
{{0x0f, 0x1c, 0x00, }, 3, 0, "", "",
"0f 1c 00 \tcldemote (%rax)",},
{{0x41, 0x0f, 0x1c, 0x00, }, 4, 0, "", "",
"41 0f 1c 00 \tcldemote (%r8)",},
{{0x0f, 0x1c, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1c 04 25 78 56 34 12 \tcldemote 0x12345678",},
{{0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
"0f c7 20 \txsavec (%rax)",},
{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "",
"41 0f c7 20 \txsavec (%r8)",},
{{0x0f, 0xc7, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 24 25 78 56 34 12 \txsavec 0x12345678",},
{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
"0f c7 28 \txsaves (%rax)",},
{{0x41, 0x0f, 0xc7, 0x28, }, 4, 0, "", "",
"41 0f c7 28 \txsaves (%r8)",},
{{0x0f, 0xc7, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 2c 25 78 56 34 12 \txsaves 0x12345678",},
{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
"0f c7 18 \txrstors (%rax)",},
{{0x41, 0x0f, 0xc7, 0x18, }, 4, 0, "", "",
"41 0f c7 18 \txrstors (%r8)",},
{{0x0f, 0xc7, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 1c 25 78 56 34 12 \txrstors 0x12345678",},
{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",},
{{0xf3, 0x0f, 0xae, 0x20, }, 4, 0, "", "",
"f3 0f ae 20 \tptwritel (%rax)",},
{{0xf3, 0x41, 0x0f, 0xae, 0x20, }, 5, 0, "", "",
"f3 41 0f ae 20 \tptwritel (%r8)",},
{{0xf3, 0x0f, 0xae, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae 24 25 78 56 34 12 \tptwritel 0x12345678",},
{{0xf3, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae a4 c8 78 56 34 12 \tptwritel 0x12345678(%rax,%rcx,8)",},
{{0xf3, 0x41, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 41 0f ae a4 c8 78 56 34 12 \tptwritel 0x12345678(%r8,%rcx,8)",},
{{0xf3, 0x0f, 0xae, 0x20, }, 4, 0, "", "",
"f3 0f ae 20 \tptwritel (%rax)",},
{{0xf3, 0x41, 0x0f, 0xae, 0x20, }, 5, 0, "", "",
"f3 41 0f ae 20 \tptwritel (%r8)",},
{{0xf3, 0x0f, 0xae, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae 24 25 78 56 34 12 \tptwritel 0x12345678",},
{{0xf3, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae a4 c8 78 56 34 12 \tptwritel 0x12345678(%rax,%rcx,8)",},
{{0xf3, 0x41, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 41 0f ae a4 c8 78 56 34 12 \tptwritel 0x12345678(%r8,%rcx,8)",},
{{0xf3, 0x48, 0x0f, 0xae, 0x20, }, 5, 0, "", "",
"f3 48 0f ae 20 \tptwriteq (%rax)",},
{{0xf3, 0x49, 0x0f, 0xae, 0x20, }, 5, 0, "", "",
"f3 49 0f ae 20 \tptwriteq (%r8)",},
{{0xf3, 0x48, 0x0f, 0xae, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 48 0f ae 24 25 78 56 34 12 \tptwriteq 0x12345678",},
{{0xf3, 0x48, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 48 0f ae a4 c8 78 56 34 12 \tptwriteq 0x12345678(%rax,%rcx,8)",},
{{0xf3, 0x49, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 49 0f ae a4 c8 78 56 34 12 \tptwriteq 0x12345678(%r8,%rcx,8)",},
{{0x66, 0x0f, 0xae, 0xf3, }, 4, 0, "", "",
"66 0f ae f3 \ttpause %ebx",},
{{0x66, 0x41, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"66 41 0f ae f0 \ttpause %r8d",},
{{0x67, 0xf3, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"67 f3 0f ae f0 \tumonitor %eax",},
{{0xf3, 0x0f, 0xae, 0xf0, }, 4, 0, "", "",
"f3 0f ae f0 \tumonitor %rax",},
{{0x67, 0xf3, 0x41, 0x0f, 0xae, 0xf0, }, 6, 0, "", "",
"67 f3 41 0f ae f0 \tumonitor %r8d",},
{{0xf2, 0x0f, 0xae, 0xf0, }, 4, 0, "", "",
"f2 0f ae f0 \tumwait %eax",},
{{0xf2, 0x41, 0x0f, 0xae, 0xf0, }, 5, 0, "", "",
"f2 41 0f ae f0 \tumwait %r8d",},
{{0x48, 0x0f, 0x38, 0xf9, 0x03, }, 5, 0, "", "",
"48 0f 38 f9 03 \tmovdiri %rax,(%rbx)",},
{{0x48, 0x0f, 0x38, 0xf9, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"48 0f 38 f9 88 78 56 34 12 \tmovdiri %rcx,0x12345678(%rax)",},
{{0x66, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"66 0f 38 f8 18 \tmovdir64b (%rax),%rbx",},
{{0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%rax),%rcx",},
{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "",
"67 66 0f 38 f8 18 \tmovdir64b (%eax),%ebx",},
{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"67 66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%eax),%ecx",},
{{0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"f2 0f 38 f8 18 \tenqcmd (%rax),%rbx",},
{{0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%rax),%rcx",},
{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "",
"67 f2 0f 38 f8 18 \tenqcmd (%eax),%ebx",},
{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"67 f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%eax),%ecx",},
{{0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "",
"f3 0f 38 f8 18 \tenqcmds (%rax),%rbx",},
{{0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%rax),%rcx",},
{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "",
"67 f3 0f 38 f8 18 \tenqcmds (%eax),%ebx",},
{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"67 f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%eax),%ecx",},
{{0xf3, 0x0f, 0xae, 0xe8, }, 4, 0, "", "",
"f3 0f ae e8 \tincsspd %eax",},
{{0xf3, 0x41, 0x0f, 0xae, 0xe8, }, 5, 0, "", "",
"f3 41 0f ae e8 \tincsspd %r8d",},
{{0xf3, 0x48, 0x0f, 0xae, 0xe8, }, 5, 0, "", "",
"f3 48 0f ae e8 \tincsspq %rax",},
{{0xf3, 0x49, 0x0f, 0xae, 0xe8, }, 5, 0, "", "",
"f3 49 0f ae e8 \tincsspq %r8",},
{{0x0f, 0xae, 0x28, }, 3, 0, "", "",
"0f ae 28 \txrstor (%rax)",},
{{0x41, 0x0f, 0xae, 0x28, }, 4, 0, "", "",
"41 0f ae 28 \txrstor (%r8)",},
{{0x0f, 0xae, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f ae 2c 25 78 56 34 12 \txrstor 0x12345678",},
{{0x0f, 0xae, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f ae ac c8 78 56 34 12 \txrstor 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0xae, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f ae ac c8 78 56 34 12 \txrstor 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0xae, 0xe8, }, 3, 0, "", "",
"0f ae e8 \tlfence ",},
{{0xf3, 0x0f, 0x1e, 0xc8, }, 4, 0, "", "",
"f3 0f 1e c8 \trdsspd %eax",},
{{0xf3, 0x41, 0x0f, 0x1e, 0xc8, }, 5, 0, "", "",
"f3 41 0f 1e c8 \trdsspd %r8d",},
{{0xf3, 0x48, 0x0f, 0x1e, 0xc8, }, 5, 0, "", "",
"f3 48 0f 1e c8 \trdsspq %rax",},
{{0xf3, 0x49, 0x0f, 0x1e, 0xc8, }, 5, 0, "", "",
"f3 49 0f 1e c8 \trdsspq %r8",},
{{0xf3, 0x0f, 0x01, 0xea, }, 4, 0, "", "",
"f3 0f 01 ea \tsaveprevssp ",},
{{0xf3, 0x0f, 0x01, 0x28, }, 4, 0, "", "",
"f3 0f 01 28 \trstorssp (%rax)",},
{{0xf3, 0x41, 0x0f, 0x01, 0x28, }, 5, 0, "", "",
"f3 41 0f 01 28 \trstorssp (%r8)",},
{{0xf3, 0x0f, 0x01, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 01 2c 25 78 56 34 12 \trstorssp 0x12345678",},
{{0xf3, 0x0f, 0x01, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 01 ac c8 78 56 34 12 \trstorssp 0x12345678(%rax,%rcx,8)",},
{{0xf3, 0x41, 0x0f, 0x01, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 41 0f 01 ac c8 78 56 34 12 \trstorssp 0x12345678(%r8,%rcx,8)",},
{{0x0f, 0x38, 0xf6, 0x08, }, 4, 0, "", "",
"0f 38 f6 08 \twrssd %ecx,(%rax)",},
{{0x41, 0x0f, 0x38, 0xf6, 0x10, }, 5, 0, "", "",
"41 0f 38 f6 10 \twrssd %edx,(%r8)",},
{{0x0f, 0x38, 0xf6, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"0f 38 f6 14 25 78 56 34 12 \twrssd %edx,0x12345678",},
{{0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"0f 38 f6 94 c8 78 56 34 12 \twrssd %edx,0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"41 0f 38 f6 94 c8 78 56 34 12 \twrssd %edx,0x12345678(%r8,%rcx,8)",},
{{0x48, 0x0f, 0x38, 0xf6, 0x08, }, 5, 0, "", "",
"48 0f 38 f6 08 \twrssq %rcx,(%rax)",},
{{0x49, 0x0f, 0x38, 0xf6, 0x10, }, 5, 0, "", "",
"49 0f 38 f6 10 \twrssq %rdx,(%r8)",},
{{0x48, 0x0f, 0x38, 0xf6, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"48 0f 38 f6 14 25 78 56 34 12 \twrssq %rdx,0x12345678",},
{{0x48, 0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"48 0f 38 f6 94 c8 78 56 34 12 \twrssq %rdx,0x12345678(%rax,%rcx,8)",},
{{0x49, 0x0f, 0x38, 0xf6, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"49 0f 38 f6 94 c8 78 56 34 12 \twrssq %rdx,0x12345678(%r8,%rcx,8)",},
{{0x66, 0x0f, 0x38, 0xf5, 0x08, }, 5, 0, "", "",
"66 0f 38 f5 08 \twrussd %ecx,(%rax)",},
{{0x66, 0x41, 0x0f, 0x38, 0xf5, 0x10, }, 6, 0, "", "",
"66 41 0f 38 f5 10 \twrussd %edx,(%r8)",},
{{0x66, 0x0f, 0x38, 0xf5, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"66 0f 38 f5 14 25 78 56 34 12 \twrussd %edx,0x12345678",},
{{0x66, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"66 0f 38 f5 94 c8 78 56 34 12 \twrussd %edx,0x12345678(%rax,%rcx,8)",},
{{0x66, 0x41, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"66 41 0f 38 f5 94 c8 78 56 34 12 \twrussd %edx,0x12345678(%r8,%rcx,8)",},
{{0x66, 0x48, 0x0f, 0x38, 0xf5, 0x08, }, 6, 0, "", "",
"66 48 0f 38 f5 08 \twrussq %rcx,(%rax)",},
{{0x66, 0x49, 0x0f, 0x38, 0xf5, 0x10, }, 6, 0, "", "",
"66 49 0f 38 f5 10 \twrussq %rdx,(%r8)",},
{{0x66, 0x48, 0x0f, 0x38, 0xf5, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"66 48 0f 38 f5 14 25 78 56 34 12 \twrussq %rdx,0x12345678",},
{{0x66, 0x48, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"66 48 0f 38 f5 94 c8 78 56 34 12 \twrussq %rdx,0x12345678(%rax,%rcx,8)",},
{{0x66, 0x49, 0x0f, 0x38, 0xf5, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"66 49 0f 38 f5 94 c8 78 56 34 12 \twrussq %rdx,0x12345678(%r8,%rcx,8)",},
{{0xf3, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",
"f3 0f 01 e8 \tsetssbsy ",},
{{0x0f, 0x01, 0xee, }, 3, 0, "", "",
"0f 01 ee \trdpkru ",},
{{0x0f, 0x01, 0xef, }, 3, 0, "", "",
"0f 01 ef \twrpkru ",},
{{0xf3, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
"f3 0f ae 30 \tclrssbsy (%rax)",},
{{0xf3, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "",
"f3 41 0f ae 30 \tclrssbsy (%r8)",},
{{0xf3, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae 34 25 78 56 34 12 \tclrssbsy 0x12345678",},
{{0xf3, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f ae b4 c8 78 56 34 12 \tclrssbsy 0x12345678(%rax,%rcx,8)",},
{{0xf3, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"f3 41 0f ae b4 c8 78 56 34 12 \tclrssbsy 0x12345678(%r8,%rcx,8)",},
{{0xf3, 0x0f, 0x1e, 0xfb, }, 4, 0, "", "",
"f3 0f 1e fb \tendbr32 ",},
{{0xf3, 0x0f, 0x1e, 0xfa, }, 4, 0, "", "",
"f3 0f 1e fa \tendbr64 ",},
{{0xff, 0xd0, }, 2, 0, "call", "indirect",
"ff d0 \tcallq *%rax",},
{{0xff, 0x10, }, 2, 0, "call", "indirect",
"ff 10 \tcallq *(%rax)",},
{{0x41, 0xff, 0x10, }, 3, 0, "call", "indirect",
"41 ff 10 \tcallq *(%r8)",},
{{0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",
"ff 14 25 78 56 34 12 \tcallq *0x12345678",},
{{0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "call", "indirect",
"ff 94 c8 78 56 34 12 \tcallq *0x12345678(%rax,%rcx,8)",},
{{0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",
"41 ff 94 c8 78 56 34 12 \tcallq *0x12345678(%r8,%rcx,8)",},
{{0xf2, 0xff, 0xd0, }, 3, 0, "call", "indirect",
"f2 ff d0 \tbnd callq *%rax",},
{{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect",
"f2 ff 10 \tbnd callq *(%rax)",},
{{0xf2, 0x41, 0xff, 0x10, }, 4, 0, "call", "indirect",
"f2 41 ff 10 \tbnd callq *(%r8)",},
{{0xf2, 0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",
"f2 ff 14 25 78 56 34 12 \tbnd callq *0x12345678",},
{{0xf2, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",
"f2 ff 94 c8 78 56 34 12 \tbnd callq *0x12345678(%rax,%rcx,8)",},
{{0xf2, 0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",
"f2 41 ff 94 c8 78 56 34 12 \tbnd callq *0x12345678(%r8,%rcx,8)",},
{{0x3e, 0xff, 0xd0, }, 3, 0, "call", "indirect",
"3e ff d0 \tnotrack callq *%rax",},
{{0x3e, 0xff, 0x10, }, 3, 0, "call", "indirect",
"3e ff 10 \tnotrack callq *(%rax)",},
{{0x3e, 0x41, 0xff, 0x10, }, 4, 0, "call", "indirect",
"3e 41 ff 10 \tnotrack callq *(%r8)",},
{{0x3e, 0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",
"3e ff 14 25 78 56 34 12 \tnotrack callq *0x12345678",},
{{0x3e, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "call", "indirect",
"3e ff 94 c8 78 56 34 12 \tnotrack callq *0x12345678(%rax,%rcx,8)",},
{{0x3e, 0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",
"3e 41 ff 94 c8 78 56 34 12 \tnotrack callq *0x12345678(%r8,%rcx,8)",},
{{0x3e, 0xf2, 0xff, 0xd0, }, 4, 0, "call", "indirect",
"3e f2 ff d0 \tnotrack bnd callq *%rax",},
{{0x3e, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",
"3e f2 ff 10 \tnotrack bnd callq *(%rax)",},
{{0x3e, 0xf2, 0x41, 0xff, 0x10, }, 5, 0, "call", "indirect",
"3e f2 41 ff 10 \tnotrack bnd callq *(%r8)",},
{{0x3e, 0xf2, 0xff, 0x14, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",
"3e f2 ff 14 25 78 56 34 12 \tnotrack bnd callq *0x12345678",},
{{0x3e, 0xf2, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "call", "indirect",
"3e f2 ff 94 c8 78 56 34 12 \tnotrack bnd callq *0x12345678(%rax,%rcx,8)",},
{{0x3e, 0xf2, 0x41, 0xff, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "call", "indirect",
"3e f2 41 ff 94 c8 78 56 34 12 \tnotrack bnd callq *0x12345678(%r8,%rcx,8)",},
{{0xff, 0xe0, }, 2, 0, "jmp", "indirect",
"ff e0 \tjmpq *%rax",},
{{0xff, 0x20, }, 2, 0, "jmp", "indirect",
"ff 20 \tjmpq *(%rax)",},
{{0x41, 0xff, 0x20, }, 3, 0, "jmp", "indirect",
"41 ff 20 \tjmpq *(%r8)",},
{{0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",
"ff 24 25 78 56 34 12 \tjmpq *0x12345678",},
{{0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "jmp", "indirect",
"ff a4 c8 78 56 34 12 \tjmpq *0x12345678(%rax,%rcx,8)",},
{{0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",
"41 ff a4 c8 78 56 34 12 \tjmpq *0x12345678(%r8,%rcx,8)",},
{{0xf2, 0xff, 0xe0, }, 3, 0, "jmp", "indirect",
"f2 ff e0 \tbnd jmpq *%rax",},
{{0xf2, 0xff, 0x20, }, 3, 0, "jmp", "indirect",
"f2 ff 20 \tbnd jmpq *(%rax)",},
{{0xf2, 0x41, 0xff, 0x20, }, 4, 0, "jmp", "indirect",
"f2 41 ff 20 \tbnd jmpq *(%r8)",},
{{0xf2, 0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",
"f2 ff 24 25 78 56 34 12 \tbnd jmpq *0x12345678",},
{{0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",
"f2 ff a4 c8 78 56 34 12 \tbnd jmpq *0x12345678(%rax,%rcx,8)",},
{{0xf2, 0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",
"f2 41 ff a4 c8 78 56 34 12 \tbnd jmpq *0x12345678(%r8,%rcx,8)",},
{{0x3e, 0xff, 0xe0, }, 3, 0, "jmp", "indirect",
"3e ff e0 \tnotrack jmpq *%rax",},
{{0x3e, 0xff, 0x20, }, 3, 0, "jmp", "indirect",
"3e ff 20 \tnotrack jmpq *(%rax)",},
{{0x3e, 0x41, 0xff, 0x20, }, 4, 0, "jmp", "indirect",
"3e 41 ff 20 \tnotrack jmpq *(%r8)",},
{{0x3e, 0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",
"3e ff 24 25 78 56 34 12 \tnotrack jmpq *0x12345678",},
{{0x3e, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "jmp", "indirect",
"3e ff a4 c8 78 56 34 12 \tnotrack jmpq *0x12345678(%rax,%rcx,8)",},
{{0x3e, 0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",
"3e 41 ff a4 c8 78 56 34 12 \tnotrack jmpq *0x12345678(%r8,%rcx,8)",},
{{0x3e, 0xf2, 0xff, 0xe0, }, 4, 0, "jmp", "indirect",
"3e f2 ff e0 \tnotrack bnd jmpq *%rax",},
{{0x3e, 0xf2, 0xff, 0x20, }, 4, 0, "jmp", "indirect",
"3e f2 ff 20 \tnotrack bnd jmpq *(%rax)",},
{{0x3e, 0xf2, 0x41, 0xff, 0x20, }, 5, 0, "jmp", "indirect",
"3e f2 41 ff 20 \tnotrack bnd jmpq *(%r8)",},
{{0x3e, 0xf2, 0xff, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",
"3e f2 ff 24 25 78 56 34 12 \tnotrack bnd jmpq *0x12345678",},
{{0x3e, 0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",
"3e f2 ff a4 c8 78 56 34 12 \tnotrack bnd jmpq *0x12345678(%rax,%rcx,8)",},
{{0x3e, 0xf2, 0x41, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "jmp", "indirect",
"3e f2 41 ff a4 c8 78 56 34 12 \tnotrack bnd jmpq *0x12345678(%r8,%rcx,8)",},
{{0xc4, 0xe2, 0x78, 0x49, 0x04, 0xc8, }, 6, 0, "", "",
"c4 e2 78 49 04 c8 \tldtilecfg (%rax,%rcx,8)",},
{{0xc4, 0xc2, 0x78, 0x49, 0x04, 0xc8, }, 6, 0, "", "",
"c4 c2 78 49 04 c8 \tldtilecfg (%r8,%rcx,8)",},
{{0xc4, 0xe2, 0x79, 0x49, 0x04, 0xc8, }, 6, 0, "", "",
"c4 e2 79 49 04 c8 \tsttilecfg (%rax,%rcx,8)",},
{{0xc4, 0xc2, 0x79, 0x49, 0x04, 0xc8, }, 6, 0, "", "",
"c4 c2 79 49 04 c8 \tsttilecfg (%r8,%rcx,8)",},
{{0xc4, 0xe2, 0x7a, 0x5c, 0xd1, }, 5, 0, "", "",
"c4 e2 7a 5c d1 \ttdpbf16ps %tmm0,%tmm1,%tmm2",},
{{0xc4, 0xe2, 0x7b, 0x5e, 0xd1, }, 5, 0, "", "",
"c4 e2 7b 5e d1 \ttdpbssd %tmm0,%tmm1,%tmm2",},
{{0xc4, 0xe2, 0x7a, 0x5e, 0xd1, }, 5, 0, "", "",
"c4 e2 7a 5e d1 \ttdpbsud %tmm0,%tmm1,%tmm2",},
{{0xc4, 0xe2, 0x79, 0x5e, 0xd1, }, 5, 0, "", "",
"c4 e2 79 5e d1 \ttdpbusd %tmm0,%tmm1,%tmm2",},
{{0xc4, 0xe2, 0x78, 0x5e, 0xd1, }, 5, 0, "", "",
"c4 e2 78 5e d1 \ttdpbuud %tmm0,%tmm1,%tmm2",},
{{0xc4, 0xe2, 0x7b, 0x4b, 0x0c, 0xc8, }, 6, 0, "", "",
"c4 e2 7b 4b 0c c8 \ttileloadd (%rax,%rcx,8),%tmm1",},
{{0xc4, 0xc2, 0x7b, 0x4b, 0x14, 0xc8, }, 6, 0, "", "",
"c4 c2 7b 4b 14 c8 \ttileloadd (%r8,%rcx,8),%tmm2",},
{{0xc4, 0xe2, 0x79, 0x4b, 0x0c, 0xc8, }, 6, 0, "", "",
"c4 e2 79 4b 0c c8 \ttileloaddt1 (%rax,%rcx,8),%tmm1",},
{{0xc4, 0xc2, 0x79, 0x4b, 0x14, 0xc8, }, 6, 0, "", "",
"c4 c2 79 4b 14 c8 \ttileloaddt1 (%r8,%rcx,8),%tmm2",},
{{0xc4, 0xe2, 0x78, 0x49, 0xc0, }, 5, 0, "", "",
"c4 e2 78 49 c0 \ttilerelease ",},
{{0xc4, 0xe2, 0x7a, 0x4b, 0x0c, 0xc8, }, 6, 0, "", "",
"c4 e2 7a 4b 0c c8 \ttilestored %tmm1,(%rax,%rcx,8)",},
{{0xc4, 0xc2, 0x7a, 0x4b, 0x14, 0xc8, }, 6, 0, "", "",
"c4 c2 7a 4b 14 c8 \ttilestored %tmm2,(%r8,%rcx,8)",},
{{0xc4, 0xe2, 0x7b, 0x49, 0xc0, }, 5, 0, "", "",
"c4 e2 7b 49 c0 \ttilezero %tmm0",},
{{0xc4, 0xe2, 0x7b, 0x49, 0xf8, }, 5, 0, "", "",
"c4 e2 7b 49 f8 \ttilezero %tmm7",},
{{0xf3, 0x0f, 0x01, 0xee, }, 4, 0, "", "",
"f3 0f 01 ee \tclui ",},
{{0xf3, 0x0f, 0xc7, 0xf0, }, 4, 0, "", "",
"f3 0f c7 f0 \tsenduipi %rax",},
{{0xf3, 0x41, 0x0f, 0xc7, 0xf0, }, 5, 0, "", "",
"f3 41 0f c7 f0 \tsenduipi %r8",},
{{0xf3, 0x0f, 0x01, 0xef, }, 4, 0, "", "",
"f3 0f 01 ef \tstui ",},
{{0xf3, 0x0f, 0x01, 0xed, }, 4, 0, "", "",
"f3 0f 01 ed \ttestui ",},
{{0xf3, 0x0f, 0x01, 0xec, }, 4, 0, "", "",
"f3 0f 01 ec \tuiret ",},
{{0x62, 0xf5, 0x6c, 0x48, 0x58, 0xcb, }, 6, 0, "", "",
"62 f5 6c 48 58 cb \tvaddph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 48 58 8c c8 78 56 34 12 \tvaddph 0x12345678(%rax,%rcx,8),%zmm2,%zmm1",},
{{0x67, 0x62, 0xf5, 0x6c, 0x48, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6c 48 58 8c c8 78 56 34 12 \tvaddph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x58, 0xcb, }, 6, 0, "", "",
"62 f5 6c 08 58 cb \tvaddph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 08 58 8c c8 78 56 34 12 \tvaddph 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf5, 0x6c, 0x08, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6c 08 58 8c c8 78 56 34 12 \tvaddph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x58, 0xcb, }, 6, 0, "", "",
"62 f5 6c 28 58 cb \tvaddph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 28 58 8c c8 78 56 34 12 \tvaddph 0x12345678(%rax,%rcx,8),%ymm2,%ymm1",},
{{0x67, 0x62, 0xf5, 0x6c, 0x28, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6c 28 58 8c c8 78 56 34 12 \tvaddph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x58, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 58 cb \tvaddsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 58 8c c8 78 56 34 12 \tvaddsh 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf5, 0x6e, 0x08, 0x58, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6e 08 58 8c c8 78 56 34 12 \tvaddsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
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{{0x62, 0xf6, 0x6d, 0x48, 0x97, 0xcb, }, 6, 0, "", "",
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{{0x62, 0xf6, 0x7d, 0x48, 0x4e, 0xca, }, 6, 0, "", "",
"62 f6 7d 48 4e ca \tvrsqrtph %zmm2,%zmm1",},
{{0x62, 0xf6, 0x7d, 0x48, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 48 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%rax,%rcx,8),%zmm1",},
{{0x67, 0x62, 0xf6, 0x7d, 0x48, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 7d 48 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf6, 0x7d, 0x08, 0x4e, 0xca, }, 6, 0, "", "",
"62 f6 7d 08 4e ca \tvrsqrtph %xmm2,%xmm1",},
{{0x62, 0xf6, 0x7d, 0x08, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 08 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%rax,%rcx,8),%xmm1",},
{{0x67, 0x62, 0xf6, 0x7d, 0x08, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 7d 08 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf6, 0x7d, 0x28, 0x4e, 0xca, }, 6, 0, "", "",
"62 f6 7d 28 4e ca \tvrsqrtph %ymm2,%ymm1",},
{{0x62, 0xf6, 0x7d, 0x28, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 28 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%rax,%rcx,8),%ymm1",},
{{0x67, 0x62, 0xf6, 0x7d, 0x28, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 7d 28 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x4f, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 4f cb \tvrsqrtsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x4f, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 4f 8c c8 78 56 34 12 \tvrsqrtsh 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf6, 0x6d, 0x08, 0x4f, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 6d 08 4f 8c c8 78 56 34 12 \tvrsqrtsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x48, 0x2c, 0xcb, }, 6, 0, "", "",
"62 f6 6d 48 2c cb \tvscalefph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf6, 0x6d, 0x48, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 48 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%rax,%rcx,8),%zmm2,%zmm1",},
{{0x67, 0x62, 0xf6, 0x6d, 0x48, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 6d 48 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2c, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 2c cb \tvscalefph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf6, 0x6d, 0x08, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 6d 08 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x28, 0x2c, 0xcb, }, 6, 0, "", "",
"62 f6 6d 28 2c cb \tvscalefph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf6, 0x6d, 0x28, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 28 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%rax,%rcx,8),%ymm2,%ymm1",},
{{0x67, 0x62, 0xf6, 0x6d, 0x28, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 6d 28 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2d, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 2d cb \tvscalefsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 2d 8c c8 78 56 34 12 \tvscalefsh 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf6, 0x6d, 0x08, 0x2d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f6 6d 08 2d 8c c8 78 56 34 12 \tvscalefsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x48, 0x51, 0xca, }, 6, 0, "", "",
"62 f5 7c 48 51 ca \tvsqrtph %zmm2,%zmm1",},
{{0x62, 0xf5, 0x7c, 0x48, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 48 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%rax,%rcx,8),%zmm1",},
{{0x67, 0x62, 0xf5, 0x7c, 0x48, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 7c 48 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x51, 0xca, }, 6, 0, "", "",
"62 f5 7c 08 51 ca \tvsqrtph %xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 08 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%rax,%rcx,8),%xmm1",},
{{0x67, 0x62, 0xf5, 0x7c, 0x08, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 7c 08 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf5, 0x7c, 0x28, 0x51, 0xca, }, 6, 0, "", "",
"62 f5 7c 28 51 ca \tvsqrtph %ymm2,%ymm1",},
{{0x62, 0xf5, 0x7c, 0x28, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 28 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%rax,%rcx,8),%ymm1",},
{{0x67, 0x62, 0xf5, 0x7c, 0x28, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 7c 28 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x51, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 51 cb \tvsqrtsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 51 8c c8 78 56 34 12 \tvsqrtsh 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf5, 0x6e, 0x08, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6e 08 51 8c c8 78 56 34 12 \tvsqrtsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6c 48 5c cb \tvsubph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 48 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%rax,%rcx,8),%zmm2,%zmm1",},
{{0x67, 0x62, 0xf5, 0x6c, 0x48, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6c 48 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6c 08 5c cb \tvsubph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 08 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf5, 0x6c, 0x08, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6c 08 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6c 28 5c cb \tvsubph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 28 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%rax,%rcx,8),%ymm2,%ymm1",},
{{0x67, 0x62, 0xf5, 0x6c, 0x28, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6c 28 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 5c cb \tvsubsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 5c 8c c8 78 56 34 12 \tvsubsh 0x12345678(%rax,%rcx,8),%xmm2,%xmm1",},
{{0x67, 0x62, 0xf5, 0x6e, 0x08, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 6e 08 5c 8c c8 78 56 34 12 \tvsubsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x2e, 0xca, }, 6, 0, "", "",
"62 f5 7c 08 2e ca \tvucomish %xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x2e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 08 2e 8c c8 78 56 34 12 \tvucomish 0x12345678(%rax,%rcx,8),%xmm1",},
{{0x67, 0x62, 0xf5, 0x7c, 0x08, 0x2e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "",
"67 62 f5 7c 08 2e 8c c8 78 56 34 12 \tvucomish 0x12345678(%eax,%ecx,8),%xmm1",},
{{0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x00, }, 6, 0, "", "",
"f3 0f 3a f0 c0 00 \threset $0x0",},
{{0x0f, 0x01, 0xe8, }, 3, 0, "", "",
"0f 01 e8 \tserialize ",},
{{0xf2, 0x0f, 0x01, 0xe9, }, 4, 0, "", "",
"f2 0f 01 e9 \txresldtrk ",},
{{0xf2, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",
"f2 0f 01 e8 \txsusldtrk ",},
{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",
"0f 01 cf \tencls ",},
{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",
"0f 01 d7 \tenclu ",},
{{0x0f, 0x01, 0xc0, }, 3, 0, "", "",
"0f 01 c0 \tenclv ",},
{{0x0f, 0x01, 0xc5, }, 3, 0, "", "",
"0f 01 c5 \tpconfig ",},
{{0xf3, 0x0f, 0x09, }, 3, 0, "", "",
"f3 0f 09 \twbnoinvd ",},
| linux-master | tools/perf/arch/x86/tests/insn-x86-dat-64.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compiler.h>
#include <linux/bits.h>
#include <string.h>
#include <cpuid.h>
#include <sched.h>
#include "intel-pt-decoder/intel-pt-pkt-decoder.h"
#include "debug.h"
#include "tests/tests.h"
#include "arch-tests.h"
#include "cpumap.h"
/**
* struct test_data - Test data.
* @len: number of bytes to decode
* @bytes: bytes to decode
* @ctx: packet context to decode
* @packet: expected packet
* @new_ctx: expected new packet context
* @ctx_unchanged: the packet context must not change
*/
static const struct test_data {
int len;
u8 bytes[INTEL_PT_PKT_MAX_SZ];
enum intel_pt_pkt_ctx ctx;
struct intel_pt_pkt packet;
enum intel_pt_pkt_ctx new_ctx;
int ctx_unchanged;
} data[] = {
/* Padding Packet */
{1, {0}, 0, {INTEL_PT_PAD, 0, 0}, 0, 1 },
/* Short Taken/Not Taken Packet */
{1, {4}, 0, {INTEL_PT_TNT, 1, 0}, 0, 0 },
{1, {6}, 0, {INTEL_PT_TNT, 1, 0x20ULL << 58}, 0, 0 },
{1, {0x80}, 0, {INTEL_PT_TNT, 6, 0}, 0, 0 },
{1, {0xfe}, 0, {INTEL_PT_TNT, 6, 0x3fULL << 58}, 0, 0 },
/* Long Taken/Not Taken Packet */
{8, {0x02, 0xa3, 2}, 0, {INTEL_PT_TNT, 1, 0xa302ULL << 47}, 0, 0 },
{8, {0x02, 0xa3, 3}, 0, {INTEL_PT_TNT, 1, 0x1a302ULL << 47}, 0, 0 },
{8, {0x02, 0xa3, 0, 0, 0, 0, 0, 0x80}, 0, {INTEL_PT_TNT, 47, 0xa302ULL << 1}, 0, 0 },
{8, {0x02, 0xa3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, 0, {INTEL_PT_TNT, 47, 0xffffffffffffa302ULL << 1}, 0, 0 },
/* Target IP Packet */
{1, {0x0d}, 0, {INTEL_PT_TIP, 0, 0}, 0, 0 },
{3, {0x2d, 1, 2}, 0, {INTEL_PT_TIP, 1, 0x201}, 0, 0 },
{5, {0x4d, 1, 2, 3, 4}, 0, {INTEL_PT_TIP, 2, 0x4030201}, 0, 0 },
{7, {0x6d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP, 3, 0x60504030201}, 0, 0 },
{7, {0x8d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP, 4, 0x60504030201}, 0, 0 },
{9, {0xcd, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP, 6, 0x807060504030201}, 0, 0 },
/* Packet Generation Enable */
{1, {0x11}, 0, {INTEL_PT_TIP_PGE, 0, 0}, 0, 0 },
{3, {0x31, 1, 2}, 0, {INTEL_PT_TIP_PGE, 1, 0x201}, 0, 0 },
{5, {0x51, 1, 2, 3, 4}, 0, {INTEL_PT_TIP_PGE, 2, 0x4030201}, 0, 0 },
{7, {0x71, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGE, 3, 0x60504030201}, 0, 0 },
{7, {0x91, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGE, 4, 0x60504030201}, 0, 0 },
{9, {0xd1, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP_PGE, 6, 0x807060504030201}, 0, 0 },
/* Packet Generation Disable */
{1, {0x01}, 0, {INTEL_PT_TIP_PGD, 0, 0}, 0, 0 },
{3, {0x21, 1, 2}, 0, {INTEL_PT_TIP_PGD, 1, 0x201}, 0, 0 },
{5, {0x41, 1, 2, 3, 4}, 0, {INTEL_PT_TIP_PGD, 2, 0x4030201}, 0, 0 },
{7, {0x61, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGD, 3, 0x60504030201}, 0, 0 },
{7, {0x81, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGD, 4, 0x60504030201}, 0, 0 },
{9, {0xc1, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP_PGD, 6, 0x807060504030201}, 0, 0 },
/* Flow Update Packet */
{1, {0x1d}, 0, {INTEL_PT_FUP, 0, 0}, 0, 0 },
{3, {0x3d, 1, 2}, 0, {INTEL_PT_FUP, 1, 0x201}, 0, 0 },
{5, {0x5d, 1, 2, 3, 4}, 0, {INTEL_PT_FUP, 2, 0x4030201}, 0, 0 },
{7, {0x7d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_FUP, 3, 0x60504030201}, 0, 0 },
{7, {0x9d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_FUP, 4, 0x60504030201}, 0, 0 },
{9, {0xdd, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_FUP, 6, 0x807060504030201}, 0, 0 },
/* Paging Information Packet */
{8, {0x02, 0x43, 2, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0xC0A08060402}, 0, 0 },
{8, {0x02, 0x43, 3, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0xC0A08060403}, 0, 0 },
/* Mode Exec Packet */
{2, {0x99, 0x00}, 0, {INTEL_PT_MODE_EXEC, 0, 16}, 0, 0 },
{2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 1, 64}, 0, 0 },
{2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 2, 32}, 0, 0 },
{2, {0x99, 0x04}, 0, {INTEL_PT_MODE_EXEC, 4, 16}, 0, 0 },
{2, {0x99, 0x05}, 0, {INTEL_PT_MODE_EXEC, 5, 64}, 0, 0 },
{2, {0x99, 0x06}, 0, {INTEL_PT_MODE_EXEC, 6, 32}, 0, 0 },
/* Mode TSX Packet */
{2, {0x99, 0x20}, 0, {INTEL_PT_MODE_TSX, 0, 0}, 0, 0 },
{2, {0x99, 0x21}, 0, {INTEL_PT_MODE_TSX, 0, 1}, 0, 0 },
{2, {0x99, 0x22}, 0, {INTEL_PT_MODE_TSX, 0, 2}, 0, 0 },
/* Trace Stop Packet */
{2, {0x02, 0x83}, 0, {INTEL_PT_TRACESTOP, 0, 0}, 0, 0 },
/* Core:Bus Ratio Packet */
{4, {0x02, 0x03, 0x12, 0}, 0, {INTEL_PT_CBR, 0, 0x12}, 0, 1 },
/* Timestamp Counter Packet */
{8, {0x19, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_TSC, 0, 0x7060504030201}, 0, 1 },
/* Mini Time Counter Packet */
{2, {0x59, 0x12}, 0, {INTEL_PT_MTC, 0, 0x12}, 0, 1 },
/* TSC / MTC Alignment Packet */
{7, {0x02, 0x73}, 0, {INTEL_PT_TMA, 0, 0}, 0, 1 },
{7, {0x02, 0x73, 1, 2}, 0, {INTEL_PT_TMA, 0, 0x201}, 0, 1 },
{7, {0x02, 0x73, 0, 0, 0, 0xff, 1}, 0, {INTEL_PT_TMA, 0x1ff, 0}, 0, 1 },
{7, {0x02, 0x73, 0x80, 0xc0, 0, 0xff, 1}, 0, {INTEL_PT_TMA, 0x1ff, 0xc080}, 0, 1 },
/* Cycle Count Packet */
{1, {0x03}, 0, {INTEL_PT_CYC, 0, 0}, 0, 1 },
{1, {0x0b}, 0, {INTEL_PT_CYC, 0, 1}, 0, 1 },
{1, {0xfb}, 0, {INTEL_PT_CYC, 0, 0x1f}, 0, 1 },
{2, {0x07, 2}, 0, {INTEL_PT_CYC, 0, 0x20}, 0, 1 },
{2, {0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0xfff}, 0, 1 },
{3, {0x07, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x1000}, 0, 1 },
{3, {0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x7ffff}, 0, 1 },
{4, {0x07, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x80000}, 0, 1 },
{4, {0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x3ffffff}, 0, 1 },
{5, {0x07, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x4000000}, 0, 1 },
{5, {0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x1ffffffff}, 0, 1 },
{6, {0x07, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x200000000}, 0, 1 },
{6, {0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0xffffffffff}, 0, 1 },
{7, {0x07, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x10000000000}, 0, 1 },
{7, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x7fffffffffff}, 0, 1 },
{8, {0x07, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x800000000000}, 0, 1 },
{8, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x3fffffffffffff}, 0, 1 },
{9, {0x07, 1, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x40000000000000}, 0, 1 },
{9, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x1fffffffffffffff}, 0, 1 },
{10, {0x07, 1, 1, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x2000000000000000}, 0, 1 },
{10, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe}, 0, {INTEL_PT_CYC, 0, 0xffffffffffffffff}, 0, 1 },
/* Virtual-Machine Control Structure Packet */
{7, {0x02, 0xc8, 1, 2, 3, 4, 5}, 0, {INTEL_PT_VMCS, 5, 0x504030201}, 0, 0 },
/* Overflow Packet */
{2, {0x02, 0xf3}, 0, {INTEL_PT_OVF, 0, 0}, 0, 0 },
{2, {0x02, 0xf3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_OVF, 0, 0}, 0, 0 },
{2, {0x02, 0xf3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_OVF, 0, 0}, 0, 0 },
/* Packet Stream Boundary*/
{16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, 0, {INTEL_PT_PSB, 0, 0}, 0, 0 },
{16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, INTEL_PT_BLK_4_CTX, {INTEL_PT_PSB, 0, 0}, 0, 0 },
{16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, INTEL_PT_BLK_8_CTX, {INTEL_PT_PSB, 0, 0}, 0, 0 },
/* PSB End Packet */
{2, {0x02, 0x23}, 0, {INTEL_PT_PSBEND, 0, 0}, 0, 0 },
/* Maintenance Packet */
{11, {0x02, 0xc3, 0x88, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_MNT, 0, 0x7060504030201}, 0, 1 },
/* Write Data to PT Packet */
{6, {0x02, 0x12, 1, 2, 3, 4}, 0, {INTEL_PT_PTWRITE, 0, 0x4030201}, 0, 0 },
{10, {0x02, 0x32, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_PTWRITE, 1, 0x807060504030201}, 0, 0 },
{6, {0x02, 0x92, 1, 2, 3, 4}, 0, {INTEL_PT_PTWRITE_IP, 0, 0x4030201}, 0, 0 },
{10, {0x02, 0xb2, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_PTWRITE_IP, 1, 0x807060504030201}, 0, 0 },
/* Execution Stop Packet */
{2, {0x02, 0x62}, 0, {INTEL_PT_EXSTOP, 0, 0}, 0, 1 },
{2, {0x02, 0xe2}, 0, {INTEL_PT_EXSTOP_IP, 0, 0}, 0, 1 },
/* Monitor Wait Packet */
{10, {0x02, 0xc2}, 0, {INTEL_PT_MWAIT, 0, 0}, 0, 0 },
{10, {0x02, 0xc2, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_MWAIT, 0, 0x807060504030201}, 0, 0 },
{10, {0x02, 0xc2, 0xff, 2, 3, 4, 7, 6, 7, 8}, 0, {INTEL_PT_MWAIT, 0, 0x8070607040302ff}, 0, 0 },
/* Power Entry Packet */
{4, {0x02, 0x22}, 0, {INTEL_PT_PWRE, 0, 0}, 0, 1 },
{4, {0x02, 0x22, 1, 2}, 0, {INTEL_PT_PWRE, 0, 0x0201}, 0, 1 },
{4, {0x02, 0x22, 0x80, 0x34}, 0, {INTEL_PT_PWRE, 0, 0x3480}, 0, 1 },
{4, {0x02, 0x22, 0x00, 0x56}, 0, {INTEL_PT_PWRE, 0, 0x5600}, 0, 1 },
/* Power Exit Packet */
{7, {0x02, 0xa2}, 0, {INTEL_PT_PWRX, 0, 0}, 0, 1 },
{7, {0x02, 0xa2, 1, 2, 3, 4, 5}, 0, {INTEL_PT_PWRX, 0, 0x504030201}, 0, 1 },
{7, {0x02, 0xa2, 0xff, 0xff, 0xff, 0xff, 0xff}, 0, {INTEL_PT_PWRX, 0, 0xffffffffff}, 0, 1 },
/* Block Begin Packet */
{3, {0x02, 0x63, 0x00}, 0, {INTEL_PT_BBP, 0, 0}, INTEL_PT_BLK_8_CTX, 0 },
{3, {0x02, 0x63, 0x80}, 0, {INTEL_PT_BBP, 1, 0}, INTEL_PT_BLK_4_CTX, 0 },
{3, {0x02, 0x63, 0x1f}, 0, {INTEL_PT_BBP, 0, 0x1f}, INTEL_PT_BLK_8_CTX, 0 },
{3, {0x02, 0x63, 0x9f}, 0, {INTEL_PT_BBP, 1, 0x1f}, INTEL_PT_BLK_4_CTX, 0 },
/* 4-byte Block Item Packet */
{5, {0x04}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0, 0}, INTEL_PT_BLK_4_CTX, 0 },
{5, {0xfc}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0x1f, 0}, INTEL_PT_BLK_4_CTX, 0 },
{5, {0x04, 1, 2, 3, 4}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0, 0x04030201}, INTEL_PT_BLK_4_CTX, 0 },
{5, {0xfc, 1, 2, 3, 4}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0x1f, 0x04030201}, INTEL_PT_BLK_4_CTX, 0 },
/* 8-byte Block Item Packet */
{9, {0x04}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0, 0}, INTEL_PT_BLK_8_CTX, 0 },
{9, {0xfc}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0x1f, 0}, INTEL_PT_BLK_8_CTX, 0 },
{9, {0x04, 1, 2, 3, 4, 5, 6, 7, 8}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0, 0x0807060504030201}, INTEL_PT_BLK_8_CTX, 0 },
{9, {0xfc, 1, 2, 3, 4, 5, 6, 7, 8}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0x1f, 0x0807060504030201}, INTEL_PT_BLK_8_CTX, 0 },
/* Block End Packet */
{2, {0x02, 0x33}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 },
{2, {0x02, 0xb3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 },
{2, {0x02, 0x33}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 },
{2, {0x02, 0xb3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 },
/* Control Flow Event Packet */
{4, {0x02, 0x13, 0x01, 0x03}, 0, {INTEL_PT_CFE, 1, 3}, 0, 0 },
{4, {0x02, 0x13, 0x81, 0x03}, 0, {INTEL_PT_CFE_IP, 1, 3}, 0, 0 },
{4, {0x02, 0x13, 0x1f, 0x00}, 0, {INTEL_PT_CFE, 0x1f, 0}, 0, 0 },
{4, {0x02, 0x13, 0x9f, 0xff}, 0, {INTEL_PT_CFE_IP, 0x1f, 0xff}, 0, 0 },
/* */
{11, {0x02, 0x53, 0x09, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_EVD, 0x09, 0x7060504030201}, 0, 0 },
{11, {0x02, 0x53, 0x3f, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_EVD, 0x3f, 0x8070605040302}, 0, 0 },
/* Terminator */
{0, {0}, 0, {0, 0, 0}, 0, 0 },
};
static int dump_packet(const struct intel_pt_pkt *packet, const u8 *bytes, int len)
{
char desc[INTEL_PT_PKT_DESC_MAX];
int ret, i;
for (i = 0; i < len; i++)
pr_debug(" %02x", bytes[i]);
for (; i < INTEL_PT_PKT_MAX_SZ; i++)
pr_debug(" ");
pr_debug(" ");
ret = intel_pt_pkt_desc(packet, desc, INTEL_PT_PKT_DESC_MAX);
if (ret < 0) {
pr_debug("intel_pt_pkt_desc failed!\n");
return TEST_FAIL;
}
pr_debug("%s\n", desc);
return TEST_OK;
}
static void decoding_failed(const struct test_data *d)
{
pr_debug("Decoding failed!\n");
pr_debug("Decoding: ");
dump_packet(&d->packet, d->bytes, d->len);
}
static int fail(const struct test_data *d, struct intel_pt_pkt *packet, int len,
enum intel_pt_pkt_ctx new_ctx)
{
decoding_failed(d);
if (len != d->len)
pr_debug("Expected length: %d Decoded length %d\n",
d->len, len);
if (packet->type != d->packet.type)
pr_debug("Expected type: %d Decoded type %d\n",
d->packet.type, packet->type);
if (packet->count != d->packet.count)
pr_debug("Expected count: %d Decoded count %d\n",
d->packet.count, packet->count);
if (packet->payload != d->packet.payload)
pr_debug("Expected payload: 0x%llx Decoded payload 0x%llx\n",
(unsigned long long)d->packet.payload,
(unsigned long long)packet->payload);
if (new_ctx != d->new_ctx)
pr_debug("Expected packet context: %d Decoded packet context %d\n",
d->new_ctx, new_ctx);
return TEST_FAIL;
}
static int test_ctx_unchanged(const struct test_data *d, struct intel_pt_pkt *packet,
enum intel_pt_pkt_ctx ctx)
{
enum intel_pt_pkt_ctx old_ctx = ctx;
intel_pt_upd_pkt_ctx(packet, &ctx);
if (ctx != old_ctx) {
decoding_failed(d);
pr_debug("Packet context changed!\n");
return TEST_FAIL;
}
return TEST_OK;
}
static int test_one(const struct test_data *d)
{
struct intel_pt_pkt packet;
enum intel_pt_pkt_ctx ctx = d->ctx;
int ret;
memset(&packet, 0xff, sizeof(packet));
/* Decode a packet */
ret = intel_pt_get_packet(d->bytes, d->len, &packet, &ctx);
if (ret < 0 || ret > INTEL_PT_PKT_MAX_SZ) {
decoding_failed(d);
pr_debug("intel_pt_get_packet returned %d\n", ret);
return TEST_FAIL;
}
/* Some packets must always leave the packet context unchanged */
if (d->ctx_unchanged) {
int err;
err = test_ctx_unchanged(d, &packet, INTEL_PT_NO_CTX);
if (err)
return err;
err = test_ctx_unchanged(d, &packet, INTEL_PT_BLK_4_CTX);
if (err)
return err;
err = test_ctx_unchanged(d, &packet, INTEL_PT_BLK_8_CTX);
if (err)
return err;
}
/* Compare to the expected values */
if (ret != d->len || packet.type != d->packet.type ||
packet.count != d->packet.count ||
packet.payload != d->packet.payload || ctx != d->new_ctx)
return fail(d, &packet, ret, ctx);
pr_debug("Decoded ok:");
ret = dump_packet(&d->packet, d->bytes, d->len);
return ret;
}
/*
* This test feeds byte sequences to the Intel PT packet decoder and checks the
* results. Changes to the packet context are also checked.
*/
int test__intel_pt_pkt_decoder(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
const struct test_data *d = data;
int ret;
for (d = data; d->len; d++) {
ret = test_one(d);
if (ret)
return ret;
}
return TEST_OK;
}
static int setaffinity(int cpu)
{
cpu_set_t cpu_set;
CPU_ZERO(&cpu_set);
CPU_SET(cpu, &cpu_set);
if (sched_setaffinity(0, sizeof(cpu_set), &cpu_set)) {
pr_debug("sched_setaffinity() failed for CPU %d\n", cpu);
return -1;
}
return 0;
}
#define INTEL_PT_ADDR_FILT_CNT_MASK GENMASK(2, 0)
#define INTEL_PT_SUBLEAF_CNT 2
#define CPUID_REG_CNT 4
struct cpuid_result {
union {
struct {
unsigned int eax;
unsigned int ebx;
unsigned int ecx;
unsigned int edx;
};
unsigned int reg[CPUID_REG_CNT];
};
};
struct pt_caps {
struct cpuid_result subleaf[INTEL_PT_SUBLEAF_CNT];
};
static int get_pt_caps(int cpu, struct pt_caps *caps)
{
struct cpuid_result r;
int i;
if (setaffinity(cpu))
return -1;
memset(caps, 0, sizeof(*caps));
for (i = 0; i < INTEL_PT_SUBLEAF_CNT; i++) {
__get_cpuid_count(20, i, &r.eax, &r.ebx, &r.ecx, &r.edx);
pr_debug("CPU %d CPUID leaf 20 subleaf %d\n", cpu, i);
pr_debug("eax = 0x%08x\n", r.eax);
pr_debug("ebx = 0x%08x\n", r.ebx);
pr_debug("ecx = 0x%08x\n", r.ecx);
pr_debug("edx = 0x%08x\n", r.edx);
caps->subleaf[i] = r;
}
return 0;
}
static bool is_hydrid(void)
{
unsigned int eax, ebx, ecx, edx = 0;
bool result;
__get_cpuid_count(7, 0, &eax, &ebx, &ecx, &edx);
result = edx & BIT(15);
pr_debug("Is %shybrid : CPUID leaf 7 subleaf 0 edx %#x (bit-15 indicates hybrid)\n",
result ? "" : "not ", edx);
return result;
}
static int compare_caps(int cpu, struct pt_caps *caps, struct pt_caps *caps0)
{
struct pt_caps mask = { /* Mask of bits to check*/
.subleaf = {
[0] = {
.ebx = GENMASK(8, 0),
.ecx = GENMASK(3, 0),
},
[1] = {
.eax = GENMASK(31, 16),
.ebx = GENMASK(31, 0),
}
}
};
unsigned int m, reg, reg0;
int ret = 0;
int i, j;
for (i = 0; i < INTEL_PT_SUBLEAF_CNT; i++) {
for (j = 0; j < CPUID_REG_CNT; j++) {
m = mask.subleaf[i].reg[j];
reg = m & caps->subleaf[i].reg[j];
reg0 = m & caps0->subleaf[i].reg[j];
if ((reg & reg0) != reg0) {
pr_debug("CPU %d subleaf %d reg %d FAIL %#x vs %#x\n",
cpu, i, j, reg, reg0);
ret = -1;
}
}
}
m = INTEL_PT_ADDR_FILT_CNT_MASK;
reg = m & caps->subleaf[1].eax;
reg0 = m & caps0->subleaf[1].eax;
if (reg < reg0) {
pr_debug("CPU %d subleaf 1 reg 0 FAIL address filter count %#x vs %#x\n",
cpu, reg, reg0);
ret = -1;
}
if (!ret)
pr_debug("CPU %d OK\n", cpu);
return ret;
}
int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest)
{
int max_cpu = cpu__max_cpu().cpu;
struct pt_caps last_caps;
struct pt_caps caps0;
int ret = TEST_OK;
int cpu;
if (!is_hydrid()) {
test->test_cases[subtest].skip_reason = "not hybrid";
return TEST_SKIP;
}
if (get_pt_caps(0, &caps0))
return TEST_FAIL;
for (cpu = 1, last_caps = caps0; cpu < max_cpu; cpu++) {
struct pt_caps caps;
if (get_pt_caps(cpu, &caps)) {
pr_debug("CPU %d not found\n", cpu);
continue;
}
if (!memcmp(&caps, &last_caps, sizeof(caps))) {
pr_debug("CPU %d same caps as previous CPU\n", cpu);
continue;
}
if (compare_caps(cpu, &caps, &caps0))
ret = TEST_FAIL;
last_caps = caps;
}
return ret;
}
| linux-master | tools/perf/arch/x86/tests/intel-pt-test.c |
// SPDX-License-Identifier: GPL-2.0
#include "arch-tests.h"
#include "debug.h"
#include "evlist.h"
#include "evsel.h"
#include "pmu.h"
#include "pmus.h"
#include "tests/tests.h"
static bool test_config(const struct evsel *evsel, __u64 expected_config)
{
return (evsel->core.attr.config & PERF_HW_EVENT_MASK) == expected_config;
}
static bool test_perf_config(const struct perf_evsel *evsel, __u64 expected_config)
{
return (evsel->attr.config & PERF_HW_EVENT_MASK) == expected_config;
}
static bool test_hybrid_type(const struct evsel *evsel, __u64 expected_config)
{
return (evsel->core.attr.config >> PERF_PMU_TYPE_SHIFT) == expected_config;
}
static int test__hybrid_hw_event_with_pmu(struct evlist *evlist)
{
struct evsel *evsel = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCLES));
return TEST_OK;
}
static int test__hybrid_hw_group_event(struct evlist *evlist)
{
struct evsel *evsel, *leader;
evsel = leader = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCLES));
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
evsel = evsel__next(evsel);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCTIONS));
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
return TEST_OK;
}
static int test__hybrid_sw_hw_group_event(struct evlist *evlist)
{
struct evsel *evsel, *leader;
evsel = leader = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
evsel = evsel__next(evsel);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCLES));
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
return TEST_OK;
}
static int test__hybrid_hw_sw_group_event(struct evlist *evlist)
{
struct evsel *evsel, *leader;
evsel = leader = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCLES));
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
evsel = evsel__next(evsel);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
return TEST_OK;
}
static int test__hybrid_group_modifier1(struct evlist *evlist)
{
struct evsel *evsel, *leader;
evsel = leader = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCLES));
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user);
TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel);
evsel = evsel__next(evsel);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RAW));
TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCTIONS));
TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader));
TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user);
TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel);
return TEST_OK;
}
static int test__hybrid_raw1(struct evlist *evlist)
{
struct perf_evsel *evsel;
perf_evlist__for_each_evsel(&evlist->core, evsel) {
struct perf_pmu *pmu = perf_pmus__find_by_type(evsel->attr.type);
TEST_ASSERT_VAL("missing pmu", pmu);
TEST_ASSERT_VAL("unexpected pmu", !strncmp(pmu->name, "cpu_", 4));
TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 0x1a));
}
return TEST_OK;
}
static int test__hybrid_raw2(struct evlist *evlist)
{
struct evsel *evsel = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a));
return TEST_OK;
}
static int test__hybrid_cache_event(struct evlist *evlist)
{
struct evsel *evsel = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong config", 0x2 == (evsel->core.attr.config & 0xffffffff));
return TEST_OK;
}
static int test__checkevent_pmu(struct evlist *evlist)
{
struct evsel *evsel = evlist__first(evlist);
TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries);
TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW == evsel->core.attr.type);
TEST_ASSERT_VAL("wrong config", 10 == evsel->core.attr.config);
TEST_ASSERT_VAL("wrong config1", 1 == evsel->core.attr.config1);
TEST_ASSERT_VAL("wrong config2", 3 == evsel->core.attr.config2);
TEST_ASSERT_VAL("wrong config3", 0 == evsel->core.attr.config3);
/*
* The period value gets configured within evlist__config,
* while this test executes only parse events method.
*/
TEST_ASSERT_VAL("wrong period", 0 == evsel->core.attr.sample_period);
return TEST_OK;
}
struct evlist_test {
const char *name;
bool (*valid)(void);
int (*check)(struct evlist *evlist);
};
static const struct evlist_test test__hybrid_events[] = {
{
.name = "cpu_core/cpu-cycles/",
.check = test__hybrid_hw_event_with_pmu,
/* 0 */
},
{
.name = "{cpu_core/cpu-cycles/,cpu_core/instructions/}",
.check = test__hybrid_hw_group_event,
/* 1 */
},
{
.name = "{cpu-clock,cpu_core/cpu-cycles/}",
.check = test__hybrid_sw_hw_group_event,
/* 2 */
},
{
.name = "{cpu_core/cpu-cycles/,cpu-clock}",
.check = test__hybrid_hw_sw_group_event,
/* 3 */
},
{
.name = "{cpu_core/cpu-cycles/k,cpu_core/instructions/u}",
.check = test__hybrid_group_modifier1,
/* 4 */
},
{
.name = "r1a",
.check = test__hybrid_raw1,
/* 5 */
},
{
.name = "cpu_core/r1a/",
.check = test__hybrid_raw2,
/* 6 */
},
{
.name = "cpu_core/config=10,config1,config2=3,period=1000/u",
.check = test__checkevent_pmu,
/* 7 */
},
{
.name = "cpu_core/LLC-loads/",
.check = test__hybrid_cache_event,
/* 8 */
},
};
static int test_event(const struct evlist_test *e)
{
struct parse_events_error err;
struct evlist *evlist;
int ret;
if (e->valid && !e->valid()) {
pr_debug("... SKIP\n");
return TEST_OK;
}
evlist = evlist__new();
if (evlist == NULL) {
pr_err("Failed allocation");
return TEST_FAIL;
}
parse_events_error__init(&err);
ret = parse_events(evlist, e->name, &err);
if (ret) {
pr_debug("failed to parse event '%s', err %d, str '%s'\n",
e->name, ret, err.str);
parse_events_error__print(&err, e->name);
ret = TEST_FAIL;
if (strstr(err.str, "can't access trace events"))
ret = TEST_SKIP;
} else {
ret = e->check(evlist);
}
parse_events_error__exit(&err);
evlist__delete(evlist);
return ret;
}
static int combine_test_results(int existing, int latest)
{
if (existing == TEST_FAIL)
return TEST_FAIL;
if (existing == TEST_SKIP)
return latest == TEST_OK ? TEST_SKIP : latest;
return latest;
}
static int test_events(const struct evlist_test *events, int cnt)
{
int ret = TEST_OK;
for (int i = 0; i < cnt; i++) {
const struct evlist_test *e = &events[i];
int test_ret;
pr_debug("running test %d '%s'\n", i, e->name);
test_ret = test_event(e);
if (test_ret != TEST_OK) {
pr_debug("Event test failure: test %d '%s'", i, e->name);
ret = combine_test_results(ret, test_ret);
}
}
return ret;
}
int test__hybrid(struct test_suite *test __maybe_unused, int subtest __maybe_unused)
{
if (perf_pmus__num_core_pmus() == 1)
return TEST_SKIP;
return test_events(test__hybrid_events, ARRAY_SIZE(test__hybrid_events));
}
| linux-master | tools/perf/arch/x86/tests/hybrid.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
* from insn-x86-dat-src.c for inclusion by insn-x86.c
* Do not change this code.
*/
{{0x0f, 0x31, }, 2, 0, "", "",
"0f 31 \trdtsc ",},
{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
{{0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 81 78 56 34 12 \tbound %eax,0x12345678(%ecx)",},
{{0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 88 78 56 34 12 \tbound %ecx,0x12345678(%eax)",},
{{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",},
{{0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 98 78 56 34 12 \tbound %ebx,0x12345678(%eax)",},
{{0x62, 0xa0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 a0 78 56 34 12 \tbound %esp,0x12345678(%eax)",},
{{0x62, 0xa8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 a8 78 56 34 12 \tbound %ebp,0x12345678(%eax)",},
{{0x62, 0xb0, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 b0 78 56 34 12 \tbound %esi,0x12345678(%eax)",},
{{0x62, 0xb8, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 b8 78 56 34 12 \tbound %edi,0x12345678(%eax)",},
{{0x62, 0x08, }, 2, 0, "", "",
"62 08 \tbound %ecx,(%eax)",},
{{0x62, 0x05, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 05 78 56 34 12 \tbound %eax,0x12345678",},
{{0x62, 0x14, 0x01, }, 3, 0, "", "",
"62 14 01 \tbound %edx,(%ecx,%eax,1)",},
{{0x62, 0x14, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"62 14 05 78 56 34 12 \tbound %edx,0x12345678(,%eax,1)",},
{{0x62, 0x14, 0x08, }, 3, 0, "", "",
"62 14 08 \tbound %edx,(%eax,%ecx,1)",},
{{0x62, 0x14, 0xc8, }, 3, 0, "", "",
"62 14 c8 \tbound %edx,(%eax,%ecx,8)",},
{{0x62, 0x50, 0x12, }, 3, 0, "", "",
"62 50 12 \tbound %edx,0x12(%eax)",},
{{0x62, 0x55, 0x12, }, 3, 0, "", "",
"62 55 12 \tbound %edx,0x12(%ebp)",},
{{0x62, 0x54, 0x01, 0x12, }, 4, 0, "", "",
"62 54 01 12 \tbound %edx,0x12(%ecx,%eax,1)",},
{{0x62, 0x54, 0x05, 0x12, }, 4, 0, "", "",
"62 54 05 12 \tbound %edx,0x12(%ebp,%eax,1)",},
{{0x62, 0x54, 0x08, 0x12, }, 4, 0, "", "",
"62 54 08 12 \tbound %edx,0x12(%eax,%ecx,1)",},
{{0x62, 0x54, 0xc8, 0x12, }, 4, 0, "", "",
"62 54 c8 12 \tbound %edx,0x12(%eax,%ecx,8)",},
{{0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 90 78 56 34 12 \tbound %edx,0x12345678(%eax)",},
{{0x62, 0x95, 0x78, 0x56, 0x34, 0x12, }, 6, 0, "", "",
"62 95 78 56 34 12 \tbound %edx,0x12345678(%ebp)",},
{{0x62, 0x94, 0x01, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"62 94 01 78 56 34 12 \tbound %edx,0x12345678(%ecx,%eax,1)",},
{{0x62, 0x94, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"62 94 05 78 56 34 12 \tbound %edx,0x12345678(%ebp,%eax,1)",},
{{0x62, 0x94, 0x08, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"62 94 08 78 56 34 12 \tbound %edx,0x12345678(%eax,%ecx,1)",},
{{0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"62 94 c8 78 56 34 12 \tbound %edx,0x12345678(%eax,%ecx,8)",},
{{0x66, 0x62, 0x81, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 81 78 56 34 12 \tbound %ax,0x12345678(%ecx)",},
{{0x66, 0x62, 0x88, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 88 78 56 34 12 \tbound %cx,0x12345678(%eax)",},
{{0x66, 0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 90 78 56 34 12 \tbound %dx,0x12345678(%eax)",},
{{0x66, 0x62, 0x98, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 98 78 56 34 12 \tbound %bx,0x12345678(%eax)",},
{{0x66, 0x62, 0xa0, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 a0 78 56 34 12 \tbound %sp,0x12345678(%eax)",},
{{0x66, 0x62, 0xa8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 a8 78 56 34 12 \tbound %bp,0x12345678(%eax)",},
{{0x66, 0x62, 0xb0, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 b0 78 56 34 12 \tbound %si,0x12345678(%eax)",},
{{0x66, 0x62, 0xb8, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 b8 78 56 34 12 \tbound %di,0x12345678(%eax)",},
{{0x66, 0x62, 0x08, }, 3, 0, "", "",
"66 62 08 \tbound %cx,(%eax)",},
{{0x66, 0x62, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 05 78 56 34 12 \tbound %ax,0x12345678",},
{{0x66, 0x62, 0x14, 0x01, }, 4, 0, "", "",
"66 62 14 01 \tbound %dx,(%ecx,%eax,1)",},
{{0x66, 0x62, 0x14, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 62 14 05 78 56 34 12 \tbound %dx,0x12345678(,%eax,1)",},
{{0x66, 0x62, 0x14, 0x08, }, 4, 0, "", "",
"66 62 14 08 \tbound %dx,(%eax,%ecx,1)",},
{{0x66, 0x62, 0x14, 0xc8, }, 4, 0, "", "",
"66 62 14 c8 \tbound %dx,(%eax,%ecx,8)",},
{{0x66, 0x62, 0x50, 0x12, }, 4, 0, "", "",
"66 62 50 12 \tbound %dx,0x12(%eax)",},
{{0x66, 0x62, 0x55, 0x12, }, 4, 0, "", "",
"66 62 55 12 \tbound %dx,0x12(%ebp)",},
{{0x66, 0x62, 0x54, 0x01, 0x12, }, 5, 0, "", "",
"66 62 54 01 12 \tbound %dx,0x12(%ecx,%eax,1)",},
{{0x66, 0x62, 0x54, 0x05, 0x12, }, 5, 0, "", "",
"66 62 54 05 12 \tbound %dx,0x12(%ebp,%eax,1)",},
{{0x66, 0x62, 0x54, 0x08, 0x12, }, 5, 0, "", "",
"66 62 54 08 12 \tbound %dx,0x12(%eax,%ecx,1)",},
{{0x66, 0x62, 0x54, 0xc8, 0x12, }, 5, 0, "", "",
"66 62 54 c8 12 \tbound %dx,0x12(%eax,%ecx,8)",},
{{0x66, 0x62, 0x90, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 90 78 56 34 12 \tbound %dx,0x12345678(%eax)",},
{{0x66, 0x62, 0x95, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"66 62 95 78 56 34 12 \tbound %dx,0x12345678(%ebp)",},
{{0x66, 0x62, 0x94, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 62 94 01 78 56 34 12 \tbound %dx,0x12345678(%ecx,%eax,1)",},
{{0x66, 0x62, 0x94, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 62 94 05 78 56 34 12 \tbound %dx,0x12345678(%ebp,%eax,1)",},
{{0x66, 0x62, 0x94, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 62 94 08 78 56 34 12 \tbound %dx,0x12345678(%eax,%ecx,1)",},
{{0x66, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 62 94 c8 78 56 34 12 \tbound %dx,0x12345678(%eax,%ecx,8)",},
{{0x0f, 0x41, 0xd8, }, 3, 0, "", "",
"0f 41 d8 \tcmovno %eax,%ebx",},
{{0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 41 88 78 56 34 12 \tcmovno 0x12345678(%eax),%ecx",},
{{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 41 88 78 56 34 12 \tcmovno 0x12345678(%eax),%cx",},
{{0x0f, 0x44, 0xd8, }, 3, 0, "", "",
"0f 44 d8 \tcmove %eax,%ebx",},
{{0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 44 88 78 56 34 12 \tcmove 0x12345678(%eax),%ecx",},
{{0x66, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 44 88 78 56 34 12 \tcmove 0x12345678(%eax),%cx",},
{{0x0f, 0x90, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 90 80 78 56 34 12 \tseto 0x12345678(%eax)",},
{{0x0f, 0x91, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 91 80 78 56 34 12 \tsetno 0x12345678(%eax)",},
{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 92 80 78 56 34 12 \tsetb 0x12345678(%eax)",},
{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 92 80 78 56 34 12 \tsetb 0x12345678(%eax)",},
{{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 92 80 78 56 34 12 \tsetb 0x12345678(%eax)",},
{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 93 80 78 56 34 12 \tsetae 0x12345678(%eax)",},
{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 93 80 78 56 34 12 \tsetae 0x12345678(%eax)",},
{{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 93 80 78 56 34 12 \tsetae 0x12345678(%eax)",},
{{0x0f, 0x98, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 98 80 78 56 34 12 \tsets 0x12345678(%eax)",},
{{0x0f, 0x99, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 99 80 78 56 34 12 \tsetns 0x12345678(%eax)",},
{{0xc5, 0xcc, 0x41, 0xef, }, 4, 0, "", "",
"c5 cc 41 ef \tkandw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x41, 0xef, }, 5, 0, "", "",
"c4 e1 cc 41 ef \tkandq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x41, 0xef, }, 4, 0, "", "",
"c5 cd 41 ef \tkandb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x41, 0xef, }, 5, 0, "", "",
"c4 e1 cd 41 ef \tkandd %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x42, 0xef, }, 4, 0, "", "",
"c5 cc 42 ef \tkandnw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x42, 0xef, }, 5, 0, "", "",
"c4 e1 cc 42 ef \tkandnq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x42, 0xef, }, 4, 0, "", "",
"c5 cd 42 ef \tkandnb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x42, 0xef, }, 5, 0, "", "",
"c4 e1 cd 42 ef \tkandnd %k7,%k6,%k5",},
{{0xc5, 0xf8, 0x44, 0xf7, }, 4, 0, "", "",
"c5 f8 44 f7 \tknotw %k7,%k6",},
{{0xc4, 0xe1, 0xf8, 0x44, 0xf7, }, 5, 0, "", "",
"c4 e1 f8 44 f7 \tknotq %k7,%k6",},
{{0xc5, 0xf9, 0x44, 0xf7, }, 4, 0, "", "",
"c5 f9 44 f7 \tknotb %k7,%k6",},
{{0xc4, 0xe1, 0xf9, 0x44, 0xf7, }, 5, 0, "", "",
"c4 e1 f9 44 f7 \tknotd %k7,%k6",},
{{0xc5, 0xcc, 0x45, 0xef, }, 4, 0, "", "",
"c5 cc 45 ef \tkorw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x45, 0xef, }, 5, 0, "", "",
"c4 e1 cc 45 ef \tkorq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x45, 0xef, }, 4, 0, "", "",
"c5 cd 45 ef \tkorb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x45, 0xef, }, 5, 0, "", "",
"c4 e1 cd 45 ef \tkord %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x46, 0xef, }, 4, 0, "", "",
"c5 cc 46 ef \tkxnorw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x46, 0xef, }, 5, 0, "", "",
"c4 e1 cc 46 ef \tkxnorq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x46, 0xef, }, 4, 0, "", "",
"c5 cd 46 ef \tkxnorb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x46, 0xef, }, 5, 0, "", "",
"c4 e1 cd 46 ef \tkxnord %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x47, 0xef, }, 4, 0, "", "",
"c5 cc 47 ef \tkxorw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x47, 0xef, }, 5, 0, "", "",
"c4 e1 cc 47 ef \tkxorq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x47, 0xef, }, 4, 0, "", "",
"c5 cd 47 ef \tkxorb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x47, 0xef, }, 5, 0, "", "",
"c4 e1 cd 47 ef \tkxord %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x4a, 0xef, }, 4, 0, "", "",
"c5 cc 4a ef \tkaddw %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x4a, 0xef, }, 5, 0, "", "",
"c4 e1 cc 4a ef \tkaddq %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x4a, 0xef, }, 4, 0, "", "",
"c5 cd 4a ef \tkaddb %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcd, 0x4a, 0xef, }, 5, 0, "", "",
"c4 e1 cd 4a ef \tkaddd %k7,%k6,%k5",},
{{0xc5, 0xcd, 0x4b, 0xef, }, 4, 0, "", "",
"c5 cd 4b ef \tkunpckbw %k7,%k6,%k5",},
{{0xc5, 0xcc, 0x4b, 0xef, }, 4, 0, "", "",
"c5 cc 4b ef \tkunpckwd %k7,%k6,%k5",},
{{0xc4, 0xe1, 0xcc, 0x4b, 0xef, }, 5, 0, "", "",
"c4 e1 cc 4b ef \tkunpckdq %k7,%k6,%k5",},
{{0xc5, 0xf8, 0x90, 0xee, }, 4, 0, "", "",
"c5 f8 90 ee \tkmovw %k6,%k5",},
{{0xc5, 0xf8, 0x90, 0x29, }, 4, 0, "", "",
"c5 f8 90 29 \tkmovw (%ecx),%k5",},
{{0xc5, 0xf8, 0x90, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 9, 0, "", "",
"c5 f8 90 ac c8 23 01 00 00 \tkmovw 0x123(%eax,%ecx,8),%k5",},
{{0xc5, 0xf8, 0x91, 0x29, }, 4, 0, "", "",
"c5 f8 91 29 \tkmovw %k5,(%ecx)",},
{{0xc5, 0xf8, 0x91, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 9, 0, "", "",
"c5 f8 91 ac c8 23 01 00 00 \tkmovw %k5,0x123(%eax,%ecx,8)",},
{{0xc5, 0xf8, 0x92, 0xe8, }, 4, 0, "", "",
"c5 f8 92 e8 \tkmovw %eax,%k5",},
{{0xc5, 0xf8, 0x92, 0xed, }, 4, 0, "", "",
"c5 f8 92 ed \tkmovw %ebp,%k5",},
{{0xc5, 0xf8, 0x93, 0xc5, }, 4, 0, "", "",
"c5 f8 93 c5 \tkmovw %k5,%eax",},
{{0xc5, 0xf8, 0x93, 0xed, }, 4, 0, "", "",
"c5 f8 93 ed \tkmovw %k5,%ebp",},
{{0xc4, 0xe1, 0xf8, 0x90, 0xee, }, 5, 0, "", "",
"c4 e1 f8 90 ee \tkmovq %k6,%k5",},
{{0xc4, 0xe1, 0xf8, 0x90, 0x29, }, 5, 0, "", "",
"c4 e1 f8 90 29 \tkmovq (%ecx),%k5",},
{{0xc4, 0xe1, 0xf8, 0x90, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 e1 f8 90 ac c8 23 01 00 00 \tkmovq 0x123(%eax,%ecx,8),%k5",},
{{0xc4, 0xe1, 0xf8, 0x91, 0x29, }, 5, 0, "", "",
"c4 e1 f8 91 29 \tkmovq %k5,(%ecx)",},
{{0xc4, 0xe1, 0xf8, 0x91, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 e1 f8 91 ac c8 23 01 00 00 \tkmovq %k5,0x123(%eax,%ecx,8)",},
{{0xc5, 0xf9, 0x90, 0xee, }, 4, 0, "", "",
"c5 f9 90 ee \tkmovb %k6,%k5",},
{{0xc5, 0xf9, 0x90, 0x29, }, 4, 0, "", "",
"c5 f9 90 29 \tkmovb (%ecx),%k5",},
{{0xc5, 0xf9, 0x90, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 9, 0, "", "",
"c5 f9 90 ac c8 23 01 00 00 \tkmovb 0x123(%eax,%ecx,8),%k5",},
{{0xc5, 0xf9, 0x91, 0x29, }, 4, 0, "", "",
"c5 f9 91 29 \tkmovb %k5,(%ecx)",},
{{0xc5, 0xf9, 0x91, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 9, 0, "", "",
"c5 f9 91 ac c8 23 01 00 00 \tkmovb %k5,0x123(%eax,%ecx,8)",},
{{0xc5, 0xf9, 0x92, 0xe8, }, 4, 0, "", "",
"c5 f9 92 e8 \tkmovb %eax,%k5",},
{{0xc5, 0xf9, 0x92, 0xed, }, 4, 0, "", "",
"c5 f9 92 ed \tkmovb %ebp,%k5",},
{{0xc5, 0xf9, 0x93, 0xc5, }, 4, 0, "", "",
"c5 f9 93 c5 \tkmovb %k5,%eax",},
{{0xc5, 0xf9, 0x93, 0xed, }, 4, 0, "", "",
"c5 f9 93 ed \tkmovb %k5,%ebp",},
{{0xc4, 0xe1, 0xf9, 0x90, 0xee, }, 5, 0, "", "",
"c4 e1 f9 90 ee \tkmovd %k6,%k5",},
{{0xc4, 0xe1, 0xf9, 0x90, 0x29, }, 5, 0, "", "",
"c4 e1 f9 90 29 \tkmovd (%ecx),%k5",},
{{0xc4, 0xe1, 0xf9, 0x90, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 e1 f9 90 ac c8 23 01 00 00 \tkmovd 0x123(%eax,%ecx,8),%k5",},
{{0xc4, 0xe1, 0xf9, 0x91, 0x29, }, 5, 0, "", "",
"c4 e1 f9 91 29 \tkmovd %k5,(%ecx)",},
{{0xc4, 0xe1, 0xf9, 0x91, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 10, 0, "", "",
"c4 e1 f9 91 ac c8 23 01 00 00 \tkmovd %k5,0x123(%eax,%ecx,8)",},
{{0xc5, 0xfb, 0x92, 0xe8, }, 4, 0, "", "",
"c5 fb 92 e8 \tkmovd %eax,%k5",},
{{0xc5, 0xfb, 0x92, 0xed, }, 4, 0, "", "",
"c5 fb 92 ed \tkmovd %ebp,%k5",},
{{0xc5, 0xfb, 0x93, 0xc5, }, 4, 0, "", "",
"c5 fb 93 c5 \tkmovd %k5,%eax",},
{{0xc5, 0xfb, 0x93, 0xed, }, 4, 0, "", "",
"c5 fb 93 ed \tkmovd %k5,%ebp",},
{{0xc5, 0xf8, 0x98, 0xee, }, 4, 0, "", "",
"c5 f8 98 ee \tkortestw %k6,%k5",},
{{0xc4, 0xe1, 0xf8, 0x98, 0xee, }, 5, 0, "", "",
"c4 e1 f8 98 ee \tkortestq %k6,%k5",},
{{0xc5, 0xf9, 0x98, 0xee, }, 4, 0, "", "",
"c5 f9 98 ee \tkortestb %k6,%k5",},
{{0xc4, 0xe1, 0xf9, 0x98, 0xee, }, 5, 0, "", "",
"c4 e1 f9 98 ee \tkortestd %k6,%k5",},
{{0xc5, 0xf8, 0x99, 0xee, }, 4, 0, "", "",
"c5 f8 99 ee \tktestw %k6,%k5",},
{{0xc4, 0xe1, 0xf8, 0x99, 0xee, }, 5, 0, "", "",
"c4 e1 f8 99 ee \tktestq %k6,%k5",},
{{0xc5, 0xf9, 0x99, 0xee, }, 4, 0, "", "",
"c5 f9 99 ee \tktestb %k6,%k5",},
{{0xc4, 0xe1, 0xf9, 0x99, 0xee, }, 5, 0, "", "",
"c4 e1 f9 99 ee \tktestd %k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x30, 0xee, 0x12, }, 6, 0, "", "",
"c4 e3 f9 30 ee 12 \tkshiftrw $0x12,%k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x31, 0xee, 0x5b, }, 6, 0, "", "",
"c4 e3 f9 31 ee 5b \tkshiftrq $0x5b,%k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x32, 0xee, 0x12, }, 6, 0, "", "",
"c4 e3 f9 32 ee 12 \tkshiftlw $0x12,%k6,%k5",},
{{0xc4, 0xe3, 0xf9, 0x33, 0xee, 0x5b, }, 6, 0, "", "",
"c4 e3 f9 33 ee 5b \tkshiftlq $0x5b,%k6,%k5",},
{{0xc5, 0xf8, 0x5b, 0xf5, }, 4, 0, "", "",
"c5 f8 5b f5 \tvcvtdq2ps %xmm5,%xmm6",},
{{0x62, 0xf1, 0xfc, 0x4f, 0x5b, 0xf5, }, 6, 0, "", "",
"62 f1 fc 4f 5b f5 \tvcvtqq2ps %zmm5,%ymm6{%k7}",},
{{0xc5, 0xf9, 0x5b, 0xf5, }, 4, 0, "", "",
"c5 f9 5b f5 \tvcvtps2dq %xmm5,%xmm6",},
{{0xc5, 0xfa, 0x5b, 0xf5, }, 4, 0, "", "",
"c5 fa 5b f5 \tvcvttps2dq %xmm5,%xmm6",},
{{0x0f, 0x6f, 0xe0, }, 3, 0, "", "",
"0f 6f e0 \tmovq %mm0,%mm4",},
{{0xc5, 0xfd, 0x6f, 0xf4, }, 4, 0, "", "",
"c5 fd 6f f4 \tvmovdqa %ymm4,%ymm6",},
{{0x62, 0xf1, 0x7d, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 f1 7d 48 6f f5 \tvmovdqa32 %zmm5,%zmm6",},
{{0x62, 0xf1, 0xfd, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 f1 fd 48 6f f5 \tvmovdqa64 %zmm5,%zmm6",},
{{0xc5, 0xfe, 0x6f, 0xf4, }, 4, 0, "", "",
"c5 fe 6f f4 \tvmovdqu %ymm4,%ymm6",},
{{0x62, 0xf1, 0x7e, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 f1 7e 48 6f f5 \tvmovdqu32 %zmm5,%zmm6",},
{{0x62, 0xf1, 0xfe, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 f1 fe 48 6f f5 \tvmovdqu64 %zmm5,%zmm6",},
{{0x62, 0xf1, 0x7f, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 f1 7f 48 6f f5 \tvmovdqu8 %zmm5,%zmm6",},
{{0x62, 0xf1, 0xff, 0x48, 0x6f, 0xf5, }, 6, 0, "", "",
"62 f1 ff 48 6f f5 \tvmovdqu16 %zmm5,%zmm6",},
{{0x0f, 0x78, 0xc3, }, 3, 0, "", "",
"0f 78 c3 \tvmread %eax,%ebx",},
{{0x62, 0xf1, 0x7c, 0x48, 0x78, 0xf5, }, 6, 0, "", "",
"62 f1 7c 48 78 f5 \tvcvttps2udq %zmm5,%zmm6",},
{{0x62, 0xf1, 0xfc, 0x4f, 0x78, 0xf5, }, 6, 0, "", "",
"62 f1 fc 4f 78 f5 \tvcvttpd2udq %zmm5,%ymm6{%k7}",},
{{0x62, 0xf1, 0x7f, 0x08, 0x78, 0xc6, }, 6, 0, "", "",
"62 f1 7f 08 78 c6 \tvcvttsd2usi %xmm6,%eax",},
{{0x62, 0xf1, 0x7e, 0x08, 0x78, 0xc6, }, 6, 0, "", "",
"62 f1 7e 08 78 c6 \tvcvttss2usi %xmm6,%eax",},
{{0x62, 0xf1, 0x7d, 0x4f, 0x78, 0xf5, }, 6, 0, "", "",
"62 f1 7d 4f 78 f5 \tvcvttps2uqq %ymm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xfd, 0x48, 0x78, 0xf5, }, 6, 0, "", "",
"62 f1 fd 48 78 f5 \tvcvttpd2uqq %zmm5,%zmm6",},
{{0x0f, 0x79, 0xd8, }, 3, 0, "", "",
"0f 79 d8 \tvmwrite %eax,%ebx",},
{{0x62, 0xf1, 0x7c, 0x48, 0x79, 0xf5, }, 6, 0, "", "",
"62 f1 7c 48 79 f5 \tvcvtps2udq %zmm5,%zmm6",},
{{0x62, 0xf1, 0xfc, 0x4f, 0x79, 0xf5, }, 6, 0, "", "",
"62 f1 fc 4f 79 f5 \tvcvtpd2udq %zmm5,%ymm6{%k7}",},
{{0x62, 0xf1, 0x7f, 0x08, 0x79, 0xc6, }, 6, 0, "", "",
"62 f1 7f 08 79 c6 \tvcvtsd2usi %xmm6,%eax",},
{{0x62, 0xf1, 0x7e, 0x08, 0x79, 0xc6, }, 6, 0, "", "",
"62 f1 7e 08 79 c6 \tvcvtss2usi %xmm6,%eax",},
{{0x62, 0xf1, 0x7d, 0x4f, 0x79, 0xf5, }, 6, 0, "", "",
"62 f1 7d 4f 79 f5 \tvcvtps2uqq %ymm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xfd, 0x48, 0x79, 0xf5, }, 6, 0, "", "",
"62 f1 fd 48 79 f5 \tvcvtpd2uqq %zmm5,%zmm6",},
{{0x62, 0xf1, 0x7e, 0x4f, 0x7a, 0xf5, }, 6, 0, "", "",
"62 f1 7e 4f 7a f5 \tvcvtudq2pd %ymm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xfe, 0x48, 0x7a, 0xf5, }, 6, 0, "", "",
"62 f1 fe 48 7a f5 \tvcvtuqq2pd %zmm5,%zmm6",},
{{0x62, 0xf1, 0x7f, 0x48, 0x7a, 0xf5, }, 6, 0, "", "",
"62 f1 7f 48 7a f5 \tvcvtudq2ps %zmm5,%zmm6",},
{{0x62, 0xf1, 0xff, 0x4f, 0x7a, 0xf5, }, 6, 0, "", "",
"62 f1 ff 4f 7a f5 \tvcvtuqq2ps %zmm5,%ymm6{%k7}",},
{{0x62, 0xf1, 0x7d, 0x4f, 0x7a, 0xf5, }, 6, 0, "", "",
"62 f1 7d 4f 7a f5 \tvcvttps2qq %ymm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xfd, 0x48, 0x7a, 0xf5, }, 6, 0, "", "",
"62 f1 fd 48 7a f5 \tvcvttpd2qq %zmm5,%zmm6",},
{{0x62, 0xf1, 0x57, 0x08, 0x7b, 0xf0, }, 6, 0, "", "",
"62 f1 57 08 7b f0 \tvcvtusi2sd %eax,%xmm5,%xmm6",},
{{0x62, 0xf1, 0x56, 0x08, 0x7b, 0xf0, }, 6, 0, "", "",
"62 f1 56 08 7b f0 \tvcvtusi2ss %eax,%xmm5,%xmm6",},
{{0x62, 0xf1, 0x7d, 0x4f, 0x7b, 0xf5, }, 6, 0, "", "",
"62 f1 7d 4f 7b f5 \tvcvtps2qq %ymm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xfd, 0x48, 0x7b, 0xf5, }, 6, 0, "", "",
"62 f1 fd 48 7b f5 \tvcvtpd2qq %zmm5,%zmm6",},
{{0x0f, 0x7f, 0xc4, }, 3, 0, "", "",
"0f 7f c4 \tmovq %mm0,%mm4",},
{{0xc5, 0xfd, 0x7f, 0xee, }, 4, 0, "", "",
"c5 fd 7f ee \tvmovdqa %ymm5,%ymm6",},
{{0x62, 0xf1, 0x7d, 0x48, 0x7f, 0xee, }, 6, 0, "", "",
"62 f1 7d 48 7f ee \tvmovdqa32 %zmm5,%zmm6",},
{{0x62, 0xf1, 0xfd, 0x48, 0x7f, 0xee, }, 6, 0, "", "",
"62 f1 fd 48 7f ee \tvmovdqa64 %zmm5,%zmm6",},
{{0xc5, 0xfe, 0x7f, 0xee, }, 4, 0, "", "",
"c5 fe 7f ee \tvmovdqu %ymm5,%ymm6",},
{{0x62, 0xf1, 0x7e, 0x48, 0x7f, 0xee, }, 6, 0, "", "",
"62 f1 7e 48 7f ee \tvmovdqu32 %zmm5,%zmm6",},
{{0x62, 0xf1, 0xfe, 0x48, 0x7f, 0xee, }, 6, 0, "", "",
"62 f1 fe 48 7f ee \tvmovdqu64 %zmm5,%zmm6",},
{{0x62, 0xf1, 0x7f, 0x48, 0x7f, 0xee, }, 6, 0, "", "",
"62 f1 7f 48 7f ee \tvmovdqu8 %zmm5,%zmm6",},
{{0x62, 0xf1, 0xff, 0x48, 0x7f, 0xee, }, 6, 0, "", "",
"62 f1 ff 48 7f ee \tvmovdqu16 %zmm5,%zmm6",},
{{0x0f, 0xdb, 0xd1, }, 3, 0, "", "",
"0f db d1 \tpand %mm1,%mm2",},
{{0x66, 0x0f, 0xdb, 0xd1, }, 4, 0, "", "",
"66 0f db d1 \tpand %xmm1,%xmm2",},
{{0xc5, 0xcd, 0xdb, 0xd4, }, 4, 0, "", "",
"c5 cd db d4 \tvpand %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf1, 0x55, 0x48, 0xdb, 0xf4, }, 6, 0, "", "",
"62 f1 55 48 db f4 \tvpandd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0xdb, 0xf4, }, 6, 0, "", "",
"62 f1 d5 48 db f4 \tvpandq %zmm4,%zmm5,%zmm6",},
{{0x0f, 0xdf, 0xd1, }, 3, 0, "", "",
"0f df d1 \tpandn %mm1,%mm2",},
{{0x66, 0x0f, 0xdf, 0xd1, }, 4, 0, "", "",
"66 0f df d1 \tpandn %xmm1,%xmm2",},
{{0xc5, 0xcd, 0xdf, 0xd4, }, 4, 0, "", "",
"c5 cd df d4 \tvpandn %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf1, 0x55, 0x48, 0xdf, 0xf4, }, 6, 0, "", "",
"62 f1 55 48 df f4 \tvpandnd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0xdf, 0xf4, }, 6, 0, "", "",
"62 f1 d5 48 df f4 \tvpandnq %zmm4,%zmm5,%zmm6",},
{{0xc5, 0xf9, 0xe6, 0xd1, }, 4, 0, "", "",
"c5 f9 e6 d1 \tvcvttpd2dq %xmm1,%xmm2",},
{{0xc5, 0xfa, 0xe6, 0xf5, }, 4, 0, "", "",
"c5 fa e6 f5 \tvcvtdq2pd %xmm5,%xmm6",},
{{0x62, 0xf1, 0x7e, 0x4f, 0xe6, 0xf5, }, 6, 0, "", "",
"62 f1 7e 4f e6 f5 \tvcvtdq2pd %ymm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xfe, 0x48, 0xe6, 0xf5, }, 6, 0, "", "",
"62 f1 fe 48 e6 f5 \tvcvtqq2pd %zmm5,%zmm6",},
{{0xc5, 0xfb, 0xe6, 0xd1, }, 4, 0, "", "",
"c5 fb e6 d1 \tvcvtpd2dq %xmm1,%xmm2",},
{{0x0f, 0xeb, 0xf4, }, 3, 0, "", "",
"0f eb f4 \tpor %mm4,%mm6",},
{{0xc5, 0xcd, 0xeb, 0xd4, }, 4, 0, "", "",
"c5 cd eb d4 \tvpor %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf1, 0x55, 0x48, 0xeb, 0xf4, }, 6, 0, "", "",
"62 f1 55 48 eb f4 \tvpord %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0xeb, 0xf4, }, 6, 0, "", "",
"62 f1 d5 48 eb f4 \tvporq %zmm4,%zmm5,%zmm6",},
{{0x0f, 0xef, 0xf4, }, 3, 0, "", "",
"0f ef f4 \tpxor %mm4,%mm6",},
{{0xc5, 0xcd, 0xef, 0xd4, }, 4, 0, "", "",
"c5 cd ef d4 \tvpxor %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf1, 0x55, 0x48, 0xef, 0xf4, }, 6, 0, "", "",
"62 f1 55 48 ef f4 \tvpxord %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0xef, 0xf4, }, 6, 0, "", "",
"62 f1 d5 48 ef f4 \tvpxorq %zmm4,%zmm5,%zmm6",},
{{0x66, 0x0f, 0x38, 0x10, 0xc1, }, 5, 0, "", "",
"66 0f 38 10 c1 \tpblendvb %xmm0,%xmm1,%xmm0",},
{{0x62, 0xf2, 0xd5, 0x48, 0x10, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 10 f4 \tvpsrlvw %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x10, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 10 ee \tvpmovuswb %zmm5,%ymm6{%k7}",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x11, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 11 ee \tvpmovusdb %zmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0xd5, 0x48, 0x11, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 11 f4 \tvpsravw %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x12, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 12 ee \tvpmovusqb %zmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0xd5, 0x48, 0x12, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 12 f4 \tvpsllvw %zmm4,%zmm5,%zmm6",},
{{0xc4, 0xe2, 0x7d, 0x13, 0xeb, }, 5, 0, "", "",
"c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
{{0x62, 0xf2, 0x7d, 0x4f, 0x13, 0xf5, }, 6, 0, "", "",
"62 f2 7d 4f 13 f5 \tvcvtph2ps %ymm5,%zmm6{%k7}",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x13, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 13 ee \tvpmovusdw %zmm5,%ymm6{%k7}",},
{{0x66, 0x0f, 0x38, 0x14, 0xc1, }, 5, 0, "", "",
"66 0f 38 14 c1 \tblendvps %xmm0,%xmm1,%xmm0",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x14, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 14 ee \tvpmovusqw %zmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0x55, 0x48, 0x14, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 14 f4 \tvprorvd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x14, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 14 f4 \tvprorvq %zmm4,%zmm5,%zmm6",},
{{0x66, 0x0f, 0x38, 0x15, 0xc1, }, 5, 0, "", "",
"66 0f 38 15 c1 \tblendvpd %xmm0,%xmm1,%xmm0",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x15, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 15 ee \tvpmovusqd %zmm5,%ymm6{%k7}",},
{{0x62, 0xf2, 0x55, 0x48, 0x15, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 15 f4 \tvprolvd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x15, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 15 f4 \tvprolvq %zmm4,%zmm5,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x16, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 16 d4 \tvpermps %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x4d, 0x2f, 0x16, 0xd4, }, 6, 0, "", "",
"62 f2 4d 2f 16 d4 \tvpermps %ymm4,%ymm6,%ymm2{%k7}",},
{{0x62, 0xf2, 0xcd, 0x2f, 0x16, 0xd4, }, 6, 0, "", "",
"62 f2 cd 2f 16 d4 \tvpermpd %ymm4,%ymm6,%ymm2{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x19, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 19 f4 \tvbroadcastsd %xmm4,%ymm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x19, 0xf7, }, 6, 0, "", "",
"62 f2 7d 48 19 f7 \tvbroadcastf32x2 %xmm7,%zmm6",},
{{0xc4, 0xe2, 0x7d, 0x1a, 0x21, }, 5, 0, "", "",
"c4 e2 7d 1a 21 \tvbroadcastf128 (%ecx),%ymm4",},
{{0x62, 0xf2, 0x7d, 0x48, 0x1a, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 1a 31 \tvbroadcastf32x4 (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x1a, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 1a 31 \tvbroadcastf64x2 (%ecx),%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x1b, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 1b 31 \tvbroadcastf32x8 (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x1b, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 1b 31 \tvbroadcastf64x4 (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x1f, 0xf4, }, 6, 0, "", "",
"62 f2 fd 48 1f f4 \tvpabsq %zmm4,%zmm6",},
{{0xc4, 0xe2, 0x79, 0x20, 0xec, }, 5, 0, "", "",
"c4 e2 79 20 ec \tvpmovsxbw %xmm4,%xmm5",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x20, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 20 ee \tvpmovswb %zmm5,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x21, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 21 f4 \tvpmovsxbd %xmm4,%ymm6",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x21, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 21 ee \tvpmovsdb %zmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x22, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 22 e4 \tvpmovsxbq %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x22, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 22 ee \tvpmovsqb %zmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x23, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 23 e4 \tvpmovsxwd %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x23, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 23 ee \tvpmovsdw %zmm5,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x24, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 24 f4 \tvpmovsxwq %xmm4,%ymm6",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x24, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 24 ee \tvpmovsqw %zmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x25, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 25 e4 \tvpmovsxdq %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x25, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 25 ee \tvpmovsqd %zmm5,%ymm6{%k7}",},
{{0x62, 0xf2, 0x4d, 0x48, 0x26, 0xed, }, 6, 0, "", "",
"62 f2 4d 48 26 ed \tvptestmb %zmm5,%zmm6,%k5",},
{{0x62, 0xf2, 0xcd, 0x48, 0x26, 0xed, }, 6, 0, "", "",
"62 f2 cd 48 26 ed \tvptestmw %zmm5,%zmm6,%k5",},
{{0x62, 0xf2, 0x56, 0x48, 0x26, 0xec, }, 6, 0, "", "",
"62 f2 56 48 26 ec \tvptestnmb %zmm4,%zmm5,%k5",},
{{0x62, 0xf2, 0xd6, 0x48, 0x26, 0xec, }, 6, 0, "", "",
"62 f2 d6 48 26 ec \tvptestnmw %zmm4,%zmm5,%k5",},
{{0x62, 0xf2, 0x4d, 0x48, 0x27, 0xed, }, 6, 0, "", "",
"62 f2 4d 48 27 ed \tvptestmd %zmm5,%zmm6,%k5",},
{{0x62, 0xf2, 0xcd, 0x48, 0x27, 0xed, }, 6, 0, "", "",
"62 f2 cd 48 27 ed \tvptestmq %zmm5,%zmm6,%k5",},
{{0x62, 0xf2, 0x56, 0x48, 0x27, 0xec, }, 6, 0, "", "",
"62 f2 56 48 27 ec \tvptestnmd %zmm4,%zmm5,%k5",},
{{0x62, 0xf2, 0xd6, 0x48, 0x27, 0xec, }, 6, 0, "", "",
"62 f2 d6 48 27 ec \tvptestnmq %zmm4,%zmm5,%k5",},
{{0xc4, 0xe2, 0x4d, 0x28, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 28 d4 \tvpmuldq %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x28, 0xf5, }, 6, 0, "", "",
"62 f2 7e 48 28 f5 \tvpmovm2b %k5,%zmm6",},
{{0x62, 0xf2, 0xfe, 0x48, 0x28, 0xf5, }, 6, 0, "", "",
"62 f2 fe 48 28 f5 \tvpmovm2w %k5,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x29, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 29 d4 \tvpcmpeqq %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x29, 0xee, }, 6, 0, "", "",
"62 f2 7e 48 29 ee \tvpmovb2m %zmm6,%k5",},
{{0x62, 0xf2, 0xfe, 0x48, 0x29, 0xee, }, 6, 0, "", "",
"62 f2 fe 48 29 ee \tvpmovw2m %zmm6,%k5",},
{{0xc4, 0xe2, 0x7d, 0x2a, 0x21, }, 5, 0, "", "",
"c4 e2 7d 2a 21 \tvmovntdqa (%ecx),%ymm4",},
{{0x62, 0xf2, 0xfe, 0x48, 0x2a, 0xce, }, 6, 0, "", "",
"62 f2 fe 48 2a ce \tvpbroadcastmb2q %k6,%zmm1",},
{{0xc4, 0xe2, 0x5d, 0x2c, 0x31, }, 5, 0, "", "",
"c4 e2 5d 2c 31 \tvmaskmovps (%ecx),%ymm4,%ymm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x2c, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 2c f4 \tvscalefps %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x2c, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 2c f4 \tvscalefpd %zmm4,%zmm5,%zmm6",},
{{0xc4, 0xe2, 0x5d, 0x2d, 0x31, }, 5, 0, "", "",
"c4 e2 5d 2d 31 \tvmaskmovpd (%ecx),%ymm4,%ymm6",},
{{0x62, 0xf2, 0x55, 0x0f, 0x2d, 0xf4, }, 6, 0, "", "",
"62 f2 55 0f 2d f4 \tvscalefss %xmm4,%xmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0xd5, 0x0f, 0x2d, 0xf4, }, 6, 0, "", "",
"62 f2 d5 0f 2d f4 \tvscalefsd %xmm4,%xmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x30, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 30 e4 \tvpmovzxbw %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x30, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 30 ee \tvpmovwb %zmm5,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x31, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 31 f4 \tvpmovzxbd %xmm4,%ymm6",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x31, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 31 ee \tvpmovdb %zmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x32, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 32 e4 \tvpmovzxbq %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x32, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 32 ee \tvpmovqb %zmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x33, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 33 e4 \tvpmovzxwd %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x33, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 33 ee \tvpmovdw %zmm5,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x34, 0xf4, }, 5, 0, "", "",
"c4 e2 7d 34 f4 \tvpmovzxwq %xmm4,%ymm6",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x34, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 34 ee \tvpmovqw %zmm5,%xmm6{%k7}",},
{{0xc4, 0xe2, 0x7d, 0x35, 0xe4, }, 5, 0, "", "",
"c4 e2 7d 35 e4 \tvpmovzxdq %xmm4,%ymm4",},
{{0x62, 0xf2, 0x7e, 0x4f, 0x35, 0xee, }, 6, 0, "", "",
"62 f2 7e 4f 35 ee \tvpmovqd %zmm5,%ymm6{%k7}",},
{{0xc4, 0xe2, 0x4d, 0x36, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 36 d4 \tvpermd %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x4d, 0x2f, 0x36, 0xd4, }, 6, 0, "", "",
"62 f2 4d 2f 36 d4 \tvpermd %ymm4,%ymm6,%ymm2{%k7}",},
{{0x62, 0xf2, 0xcd, 0x2f, 0x36, 0xd4, }, 6, 0, "", "",
"62 f2 cd 2f 36 d4 \tvpermq %ymm4,%ymm6,%ymm2{%k7}",},
{{0xc4, 0xe2, 0x4d, 0x38, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 38 d4 \tvpminsb %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x38, 0xf5, }, 6, 0, "", "",
"62 f2 7e 48 38 f5 \tvpmovm2d %k5,%zmm6",},
{{0x62, 0xf2, 0xfe, 0x48, 0x38, 0xf5, }, 6, 0, "", "",
"62 f2 fe 48 38 f5 \tvpmovm2q %k5,%zmm6",},
{{0xc4, 0xe2, 0x69, 0x39, 0xd9, }, 5, 0, "", "",
"c4 e2 69 39 d9 \tvpminsd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x55, 0x48, 0x39, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 39 f4 \tvpminsd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x39, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 39 f4 \tvpminsq %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7e, 0x48, 0x39, 0xee, }, 6, 0, "", "",
"62 f2 7e 48 39 ee \tvpmovd2m %zmm6,%k5",},
{{0x62, 0xf2, 0xfe, 0x48, 0x39, 0xee, }, 6, 0, "", "",
"62 f2 fe 48 39 ee \tvpmovq2m %zmm6,%k5",},
{{0xc4, 0xe2, 0x4d, 0x3a, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3a d4 \tvpminuw %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x3a, 0xf6, }, 6, 0, "", "",
"62 f2 7e 48 3a f6 \tvpbroadcastmw2d %k6,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x3b, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3b d4 \tvpminud %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x55, 0x48, 0x3b, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 3b f4 \tvpminud %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x3b, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 3b f4 \tvpminuq %zmm4,%zmm5,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x3d, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3d d4 \tvpmaxsd %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x55, 0x48, 0x3d, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 3d f4 \tvpmaxsd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x3d, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 3d f4 \tvpmaxsq %zmm4,%zmm5,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x3f, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 3f d4 \tvpmaxud %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x55, 0x48, 0x3f, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 3f f4 \tvpmaxud %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x3f, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 3f f4 \tvpmaxuq %zmm4,%zmm5,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x40, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 40 d4 \tvpmulld %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x55, 0x48, 0x40, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 40 f4 \tvpmulld %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x40, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 40 f4 \tvpmullq %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x42, 0xf5, }, 6, 0, "", "",
"62 f2 7d 48 42 f5 \tvgetexpps %zmm5,%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x42, 0xf5, }, 6, 0, "", "",
"62 f2 fd 48 42 f5 \tvgetexppd %zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x0f, 0x43, 0xf4, }, 6, 0, "", "",
"62 f2 55 0f 43 f4 \tvgetexpss %xmm4,%xmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0xe5, 0x0f, 0x43, 0xe2, }, 6, 0, "", "",
"62 f2 e5 0f 43 e2 \tvgetexpsd %xmm2,%xmm3,%xmm4{%k7}",},
{{0x62, 0xf2, 0x7d, 0x48, 0x44, 0xf5, }, 6, 0, "", "",
"62 f2 7d 48 44 f5 \tvplzcntd %zmm5,%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x44, 0xf5, }, 6, 0, "", "",
"62 f2 fd 48 44 f5 \tvplzcntq %zmm5,%zmm6",},
{{0xc4, 0xe2, 0x4d, 0x46, 0xd4, }, 5, 0, "", "",
"c4 e2 4d 46 d4 \tvpsravd %ymm4,%ymm6,%ymm2",},
{{0x62, 0xf2, 0x55, 0x48, 0x46, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 46 f4 \tvpsravd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x46, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 46 f4 \tvpsravq %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x4c, 0xf5, }, 6, 0, "", "",
"62 f2 7d 48 4c f5 \tvrcp14ps %zmm5,%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x4c, 0xf5, }, 6, 0, "", "",
"62 f2 fd 48 4c f5 \tvrcp14pd %zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x0f, 0x4d, 0xf4, }, 6, 0, "", "",
"62 f2 55 0f 4d f4 \tvrcp14ss %xmm4,%xmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0xd5, 0x0f, 0x4d, 0xf4, }, 6, 0, "", "",
"62 f2 d5 0f 4d f4 \tvrcp14sd %xmm4,%xmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0x7d, 0x48, 0x4e, 0xf5, }, 6, 0, "", "",
"62 f2 7d 48 4e f5 \tvrsqrt14ps %zmm5,%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x4e, 0xf5, }, 6, 0, "", "",
"62 f2 fd 48 4e f5 \tvrsqrt14pd %zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x0f, 0x4f, 0xf4, }, 6, 0, "", "",
"62 f2 55 0f 4f f4 \tvrsqrt14ss %xmm4,%xmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0xd5, 0x0f, 0x4f, 0xf4, }, 6, 0, "", "",
"62 f2 d5 0f 4f f4 \tvrsqrt14sd %xmm4,%xmm5,%xmm6{%k7}",},
{{0x62, 0xf2, 0x6d, 0x08, 0x50, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 50 d9 \tvpdpbusd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x50, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 50 d9 \tvpdpbusd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 50 d9 \tvpdpbusd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 50 9c c8 78 56 34 12 \tvpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x51, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 51 d9 \tvpdpbusds %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x51, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 51 d9 \tvpdpbusds %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 51 d9 \tvpdpbusds %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 51 9c c8 78 56 34 12 \tvpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6e, 0x08, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6e 08 52 d9 \tvdpbf16ps %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6e, 0x28, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6e 28 52 d9 \tvdpbf16ps %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6e 48 52 d9 \tvdpbf16ps %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6e 48 52 9c c8 78 56 34 12 \tvdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 52 d9 \tvpdpwssd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 52 d9 \tvpdpwssd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 52 d9 \tvpdpwssd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 52 9c c8 78 56 34 12 \tvpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0x20, }, 6, 0, "", "",
"62 f2 7f 48 52 20 \tvp4dpwssd (%eax),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 48 52 a4 c8 78 56 34 12 \tvp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x6d, 0x08, 0x53, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 53 d9 \tvpdpwssds %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x53, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 53 d9 \tvpdpwssds %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 53 d9 \tvpdpwssds %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 53 9c c8 78 56 34 12 \tvpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0x20, }, 6, 0, "", "",
"62 f2 7f 48 53 20 \tvp4dpwssds (%eax),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 48 53 a4 c8 78 56 34 12 \tvp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7d, 0x08, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 7d 08 54 d1 \tvpopcntb %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 7d 28 54 d1 \tvpopcntb %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 7d 48 54 d1 \tvpopcntb %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 54 94 c8 78 56 34 12 \tvpopcntb 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0xfd, 0x08, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 fd 08 54 d1 \tvpopcntw %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 fd 28 54 d1 \tvpopcntw %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x54, 0xd1, }, 6, 0, "", "",
"62 f2 fd 48 54 d1 \tvpopcntw %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 54 94 c8 78 56 34 12 \tvpopcntw 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0x7d, 0x08, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 7d 08 55 d1 \tvpopcntd %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 7d 28 55 d1 \tvpopcntd %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 7d 48 55 d1 \tvpopcntd %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 55 94 c8 78 56 34 12 \tvpopcntd 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0xfd, 0x08, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 fd 08 55 d1 \tvpopcntq %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 fd 28 55 d1 \tvpopcntq %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0xd1, }, 6, 0, "", "",
"62 f2 fd 48 55 d1 \tvpopcntq %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 55 94 c8 78 56 34 12 \tvpopcntq 0x12345678(%eax,%ecx,8),%zmm2",},
{{0xc4, 0xe2, 0x79, 0x59, 0xf4, }, 5, 0, "", "",
"c4 e2 79 59 f4 \tvpbroadcastq %xmm4,%xmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x59, 0xf7, }, 6, 0, "", "",
"62 f2 7d 48 59 f7 \tvbroadcasti32x2 %xmm7,%zmm6",},
{{0xc4, 0xe2, 0x7d, 0x5a, 0x21, }, 5, 0, "", "",
"c4 e2 7d 5a 21 \tvbroadcasti128 (%ecx),%ymm4",},
{{0x62, 0xf2, 0x7d, 0x48, 0x5a, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 5a 31 \tvbroadcasti32x4 (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x5a, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 5a 31 \tvbroadcasti64x2 (%ecx),%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x5b, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 5b 31 \tvbroadcasti32x8 (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 5b 31 \tvbroadcasti64x4 (%ecx),%zmm6",},
{{0x62, 0xf2, 0x7d, 0x08, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 7d 08 62 d1 \tvpexpandb %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 7d 28 62 d1 \tvpexpandb %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 7d 48 62 d1 \tvpexpandb %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 62 94 c8 78 56 34 12 \tvpexpandb 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0xfd, 0x08, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 fd 08 62 d1 \tvpexpandw %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 fd 28 62 d1 \tvpexpandw %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x62, 0xd1, }, 6, 0, "", "",
"62 f2 fd 48 62 d1 \tvpexpandw %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 62 94 c8 78 56 34 12 \tvpexpandw 0x12345678(%eax,%ecx,8),%zmm2",},
{{0x62, 0xf2, 0x7d, 0x08, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 7d 08 63 ca \tvpcompressb %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7d, 0x28, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 7d 28 63 ca \tvpcompressb %ymm1,%ymm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 7d 48 63 ca \tvpcompressb %zmm1,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7d 48 63 94 c8 78 56 34 12 \tvpcompressb %zmm2,0x12345678(%eax,%ecx,8)",},
{{0x62, 0xf2, 0xfd, 0x08, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 fd 08 63 ca \tvpcompressw %xmm1,%xmm2",},
{{0x62, 0xf2, 0xfd, 0x28, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 fd 28 63 ca \tvpcompressw %ymm1,%ymm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca, }, 6, 0, "", "",
"62 f2 fd 48 63 ca \tvpcompressw %zmm1,%zmm2",},
{{0x62, 0xf2, 0xfd, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 fd 48 63 94 c8 78 56 34 12 \tvpcompressw %zmm2,0x12345678(%eax,%ecx,8)",},
{{0x62, 0xf2, 0x55, 0x48, 0x64, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 64 f4 \tvpblendmd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x64, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 64 f4 \tvpblendmq %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x65, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 65 f4 \tvblendmps %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x65, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 65 f4 \tvblendmpd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x66, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 66 f4 \tvpblendmb %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x66, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 66 f4 \tvpblendmw %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x6f, 0x08, 0x68, 0xd9, }, 6, 0, "", "",
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{{0x62, 0xf2, 0x6f, 0x28, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 6f 28 68 d9 \tvp2intersectd %ymm1,%ymm2,%k3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 6f 48 68 d9 \tvp2intersectd %zmm1,%zmm2,%k3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6f 48 68 9c c8 78 56 34 12 \tvp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3",},
{{0x62, 0xf2, 0xef, 0x08, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 ef 08 68 d9 \tvp2intersectq %xmm1,%xmm2,%k3",},
{{0x62, 0xf2, 0xef, 0x28, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 ef 28 68 d9 \tvp2intersectq %ymm1,%ymm2,%k3",},
{{0x62, 0xf2, 0xef, 0x48, 0x68, 0xd9, }, 6, 0, "", "",
"62 f2 ef 48 68 d9 \tvp2intersectq %zmm1,%zmm2,%k3",},
{{0x62, 0xf2, 0xef, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ef 48 68 9c c8 78 56 34 12 \tvp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3",},
{{0x62, 0xf2, 0xed, 0x08, 0x70, 0xd9, }, 6, 0, "", "",
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{{0x62, 0xf2, 0xed, 0x28, 0x70, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 70 d9 \tvpshldvw %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x70, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 70 d9 \tvpshldvw %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x70, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 70 9c c8 78 56 34 12 \tvpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 71 d9 \tvpshldvd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 71 d9 \tvpshldvd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 71 d9 \tvpshldvd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 71 9c c8 78 56 34 12 \tvpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x08, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 71 d9 \tvpshldvq %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 71 d9 \tvpshldvq %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x71, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 71 d9 \tvpshldvq %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 71 9c c8 78 56 34 12 \tvpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6f, 0x08, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 6f 08 72 d9 \tvcvtne2ps2bf16 %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6f, 0x28, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 6f 28 72 d9 \tvcvtne2ps2bf16 %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 6f 48 72 d9 \tvcvtne2ps2bf16 %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6f, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6f 48 72 9c c8 78 56 34 12 \tvcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7e, 0x08, 0x72, 0xd1, }, 6, 0, "", "",
"62 f2 7e 08 72 d1 \tvcvtneps2bf16 %xmm1,%xmm2",},
{{0x62, 0xf2, 0x7e, 0x28, 0x72, 0xd1, }, 6, 0, "", "",
"62 f2 7e 28 72 d1 \tvcvtneps2bf16 %ymm1,%xmm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x72, 0xd1, }, 6, 0, "", "",
"62 f2 7e 48 72 d1 \tvcvtneps2bf16 %zmm1,%ymm2",},
{{0x62, 0xf2, 0x7e, 0x48, 0x72, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7e 48 72 94 c8 78 56 34 12 \tvcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2",},
{{0x62, 0xf2, 0xed, 0x08, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 72 d9 \tvpshrdvw %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 72 d9 \tvpshrdvw %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x72, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 72 d9 \tvpshrdvw %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 72 9c c8 78 56 34 12 \tvpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x08, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 73 d9 \tvpshrdvd %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 73 d9 \tvpshrdvd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 73 d9 \tvpshrdvd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 73 9c c8 78 56 34 12 \tvpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x08, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 ed 08 73 d9 \tvpshrdvq %xmm1,%xmm2,%xmm3",},
{{0x62, 0xf2, 0xed, 0x28, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 ed 28 73 d9 \tvpshrdvq %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x73, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 73 d9 \tvpshrdvq %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 73 9c c8 78 56 34 12 \tvpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x55, 0x48, 0x75, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 75 f4 \tvpermi2b %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x75, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 75 f4 \tvpermi2w %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x76, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 76 f4 \tvpermi2d %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x76, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 76 f4 \tvpermi2q %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x77, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 77 f4 \tvpermi2ps %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x77, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 77 f4 \tvpermi2pd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7d, 0x08, 0x7a, 0xd8, }, 6, 0, "", "",
"62 f2 7d 08 7a d8 \tvpbroadcastb %eax,%xmm3",},
{{0x62, 0xf2, 0x7d, 0x08, 0x7b, 0xd8, }, 6, 0, "", "",
"62 f2 7d 08 7b d8 \tvpbroadcastw %eax,%xmm3",},
{{0x62, 0xf2, 0x7d, 0x08, 0x7c, 0xd8, }, 6, 0, "", "",
"62 f2 7d 08 7c d8 \tvpbroadcastd %eax,%xmm3",},
{{0x62, 0xf2, 0x55, 0x48, 0x7d, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 7d f4 \tvpermt2b %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x7d, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 7d f4 \tvpermt2w %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x7e, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 7e f4 \tvpermt2d %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x7e, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 7e f4 \tvpermt2q %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x55, 0x48, 0x7f, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 7f f4 \tvpermt2ps %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x7f, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 7f f4 \tvpermt2pd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x83, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 83 f4 \tvpmultishiftqb %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x88, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 88 31 \tvexpandps (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x88, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 88 31 \tvexpandpd (%ecx),%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x89, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 89 31 \tvpexpandd (%ecx),%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0x89, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 89 31 \tvpexpandq (%ecx),%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0x8a, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 8a 31 \tvcompressps %zmm6,(%ecx)",},
{{0x62, 0xf2, 0xfd, 0x48, 0x8a, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 8a 31 \tvcompresspd %zmm6,(%ecx)",},
{{0x62, 0xf2, 0x7d, 0x48, 0x8b, 0x31, }, 6, 0, "", "",
"62 f2 7d 48 8b 31 \tvpcompressd %zmm6,(%ecx)",},
{{0x62, 0xf2, 0xfd, 0x48, 0x8b, 0x31, }, 6, 0, "", "",
"62 f2 fd 48 8b 31 \tvpcompressq %zmm6,(%ecx)",},
{{0x62, 0xf2, 0x55, 0x48, 0x8d, 0xf4, }, 6, 0, "", "",
"62 f2 55 48 8d f4 \tvpermb %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0x8d, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 8d f4 \tvpermw %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x6d, 0x08, 0x8f, 0xd9, }, 6, 0, "", "",
"62 f2 6d 08 8f d9 \tvpshufbitqmb %xmm1,%xmm2,%k3",},
{{0x62, 0xf2, 0x6d, 0x28, 0x8f, 0xd9, }, 6, 0, "", "",
"62 f2 6d 28 8f d9 \tvpshufbitqmb %ymm1,%ymm2,%k3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 8f d9 \tvpshufbitqmb %zmm1,%zmm2,%k3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 8f 9c c8 78 56 34 12 \tvpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3",},
{{0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x02, }, 7, 0, "", "",
"c4 e2 69 90 4c 7d 02 \tvpgatherdd %xmm2,0x2(%ebp,%xmm7,2),%xmm1",},
{{0xc4, 0xe2, 0xe9, 0x90, 0x4c, 0x7d, 0x04, }, 7, 0, "", "",
"c4 e2 e9 90 4c 7d 04 \tvpgatherdq %xmm2,0x4(%ebp,%xmm7,2),%xmm1",},
{{0x62, 0xf2, 0x7d, 0x49, 0x90, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 90 b4 fd 7b 00 00 00 \tvpgatherdd 0x7b(%ebp,%zmm7,8),%zmm6{%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0x90, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 90 b4 fd 7b 00 00 00 \tvpgatherdq 0x7b(%ebp,%ymm7,8),%zmm6{%k1}",},
{{0xc4, 0xe2, 0x69, 0x91, 0x4c, 0x7d, 0x02, }, 7, 0, "", "",
"c4 e2 69 91 4c 7d 02 \tvpgatherqd %xmm2,0x2(%ebp,%xmm7,2),%xmm1",},
{{0xc4, 0xe2, 0xe9, 0x91, 0x4c, 0x7d, 0x02, }, 7, 0, "", "",
"c4 e2 e9 91 4c 7d 02 \tvpgatherqq %xmm2,0x2(%ebp,%xmm7,2),%xmm1",},
{{0x62, 0xf2, 0x7d, 0x49, 0x91, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 91 b4 fd 7b 00 00 00 \tvpgatherqd 0x7b(%ebp,%zmm7,8),%ymm6{%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0x91, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 91 b4 fd 7b 00 00 00 \tvpgatherqq 0x7b(%ebp,%zmm7,8),%zmm6{%k1}",},
{{0xc4, 0xe2, 0x69, 0x9a, 0xd9, }, 5, 0, "", "",
"c4 e2 69 9a d9 \tvfmsub132ps %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0x9a, 0xd9, }, 5, 0, "", "",
"c4 e2 6d 9a d9 \tvfmsub132ps %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x9a, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 9a d9 \tvfmsub132ps %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0x9a, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 9a 9c c8 78 56 34 12 \tvfmsub132ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0xe9, 0x9a, 0xd9, }, 5, 0, "", "",
"c4 e2 e9 9a d9 \tvfmsub132pd %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0xed, 0x9a, 0xd9, }, 5, 0, "", "",
"c4 e2 ed 9a d9 \tvfmsub132pd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x9a, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 9a d9 \tvfmsub132pd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0x9a, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 9a 9c c8 78 56 34 12 \tvfmsub132pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x20, }, 6, 0, "", "",
"62 f2 7f 48 9a 20 \tv4fmaddps (%eax),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7f, 0x48, 0x9a, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 48 9a a4 c8 78 56 34 12 \tv4fmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",},
{{0xc4, 0xe2, 0x69, 0x9b, 0xd9, }, 5, 0, "", "",
"c4 e2 69 9b d9 \tvfmsub132ss %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x69, 0x9b, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"c4 e2 69 9b 9c c8 78 56 34 12 \tvfmsub132ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",},
{{0xc4, 0xe2, 0xe9, 0x9b, 0xd9, }, 5, 0, "", "",
"c4 e2 e9 9b d9 \tvfmsub132sd %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0xe9, 0x9b, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"c4 e2 e9 9b 9c c8 78 56 34 12 \tvfmsub132sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",},
{{0x62, 0xf2, 0x7f, 0x08, 0x9b, 0x20, }, 6, 0, "", "",
"62 f2 7f 08 9b 20 \tv4fmaddss (%eax),%xmm0,%xmm4",},
{{0x62, 0xf2, 0x7f, 0x08, 0x9b, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 08 9b a4 c8 78 56 34 12 \tv4fmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4",},
{{0x62, 0xf2, 0x7d, 0x49, 0xa0, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 a0 b4 fd 7b 00 00 00 \tvpscatterdd %zmm6,0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xa0, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 a0 b4 fd 7b 00 00 00 \tvpscatterdq %zmm6,0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xa1, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 a1 b4 fd 7b 00 00 00 \tvpscatterqd %ymm6,0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x29, 0xa1, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 29 a1 b4 fd 7b 00 00 00 \tvpscatterqq %ymm6,0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xa2, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 a2 b4 fd 7b 00 00 00 \tvscatterdps %zmm6,0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xa2, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 a2 b4 fd 7b 00 00 00 \tvscatterdpd %zmm6,0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xa3, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 a3 b4 fd 7b 00 00 00 \tvscatterqps %ymm6,0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xa3, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 a3 b4 fd 7b 00 00 00 \tvscatterqpd %zmm6,0x7b(%ebp,%zmm7,8){%k1}",},
{{0xc4, 0xe2, 0x69, 0xaa, 0xd9, }, 5, 0, "", "",
"c4 e2 69 aa d9 \tvfmsub213ps %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xaa, 0xd9, }, 5, 0, "", "",
"c4 e2 6d aa d9 \tvfmsub213ps %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xaa, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 aa d9 \tvfmsub213ps %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xaa, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 aa 9c c8 78 56 34 12 \tvfmsub213ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0xe9, 0xaa, 0xd9, }, 5, 0, "", "",
"c4 e2 e9 aa d9 \tvfmsub213pd %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0xed, 0xaa, 0xd9, }, 5, 0, "", "",
"c4 e2 ed aa d9 \tvfmsub213pd %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0xed, 0x48, 0xaa, 0xd9, }, 6, 0, "", "",
"62 f2 ed 48 aa d9 \tvfmsub213pd %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0xed, 0x48, 0xaa, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 ed 48 aa 9c c8 78 56 34 12 \tvfmsub213pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x20, }, 6, 0, "", "",
"62 f2 7f 48 aa 20 \tv4fnmaddps (%eax),%zmm0,%zmm4",},
{{0x62, 0xf2, 0x7f, 0x48, 0xaa, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 48 aa a4 c8 78 56 34 12 \tv4fnmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",},
{{0xc4, 0xe2, 0x69, 0xab, 0xd9, }, 5, 0, "", "",
"c4 e2 69 ab d9 \tvfmsub213ss %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x69, 0xab, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"c4 e2 69 ab 9c c8 78 56 34 12 \tvfmsub213ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",},
{{0xc4, 0xe2, 0xe9, 0xab, 0xd9, }, 5, 0, "", "",
"c4 e2 e9 ab d9 \tvfmsub213sd %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0xe9, 0xab, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"c4 e2 e9 ab 9c c8 78 56 34 12 \tvfmsub213sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",},
{{0x62, 0xf2, 0x7f, 0x08, 0xab, 0x20, }, 6, 0, "", "",
"62 f2 7f 08 ab 20 \tv4fnmaddss (%eax),%xmm0,%xmm4",},
{{0x62, 0xf2, 0x7f, 0x08, 0xab, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 7f 08 ab a4 c8 78 56 34 12 \tv4fnmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4",},
{{0x62, 0xf2, 0xd5, 0x48, 0xb4, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 b4 f4 \tvpmadd52luq %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0xd5, 0x48, 0xb5, 0xf4, }, 6, 0, "", "",
"62 f2 d5 48 b5 f4 \tvpmadd52huq %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0xc4, 0xf5, }, 6, 0, "", "",
"62 f2 7d 48 c4 f5 \tvpconflictd %zmm5,%zmm6",},
{{0x62, 0xf2, 0xfd, 0x48, 0xc4, 0xf5, }, 6, 0, "", "",
"62 f2 fd 48 c4 f5 \tvpconflictq %zmm5,%zmm6",},
{{0x62, 0xf2, 0x7d, 0x48, 0xc8, 0xfe, }, 6, 0, "", "",
"62 f2 7d 48 c8 fe \tvexp2ps %zmm6,%zmm7",},
{{0x62, 0xf2, 0xfd, 0x48, 0xc8, 0xfe, }, 6, 0, "", "",
"62 f2 fd 48 c8 fe \tvexp2pd %zmm6,%zmm7",},
{{0x62, 0xf2, 0x7d, 0x48, 0xca, 0xfe, }, 6, 0, "", "",
"62 f2 7d 48 ca fe \tvrcp28ps %zmm6,%zmm7",},
{{0x62, 0xf2, 0xfd, 0x48, 0xca, 0xfe, }, 6, 0, "", "",
"62 f2 fd 48 ca fe \tvrcp28pd %zmm6,%zmm7",},
{{0x62, 0xf2, 0x4d, 0x0f, 0xcb, 0xfd, }, 6, 0, "", "",
"62 f2 4d 0f cb fd \tvrcp28ss %xmm5,%xmm6,%xmm7{%k7}",},
{{0x62, 0xf2, 0xcd, 0x0f, 0xcb, 0xfd, }, 6, 0, "", "",
"62 f2 cd 0f cb fd \tvrcp28sd %xmm5,%xmm6,%xmm7{%k7}",},
{{0x62, 0xf2, 0x7d, 0x48, 0xcc, 0xfe, }, 6, 0, "", "",
"62 f2 7d 48 cc fe \tvrsqrt28ps %zmm6,%zmm7",},
{{0x62, 0xf2, 0xfd, 0x48, 0xcc, 0xfe, }, 6, 0, "", "",
"62 f2 fd 48 cc fe \tvrsqrt28pd %zmm6,%zmm7",},
{{0x62, 0xf2, 0x4d, 0x0f, 0xcd, 0xfd, }, 6, 0, "", "",
"62 f2 4d 0f cd fd \tvrsqrt28ss %xmm5,%xmm6,%xmm7{%k7}",},
{{0x62, 0xf2, 0xcd, 0x0f, 0xcd, 0xfd, }, 6, 0, "", "",
"62 f2 cd 0f cd fd \tvrsqrt28sd %xmm5,%xmm6,%xmm7{%k7}",},
{{0x66, 0x0f, 0x38, 0xcf, 0xd9, }, 5, 0, "", "",
"66 0f 38 cf d9 \tgf2p8mulb %xmm1,%xmm3",},
{{0x66, 0x0f, 0x38, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
"66 0f 38 cf 9c c8 78 56 34 12 \tgf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3",},
{{0xc4, 0xe2, 0x69, 0xcf, 0xd9, }, 5, 0, "", "",
"c4 e2 69 cf d9 \tvgf2p8mulb %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xcf, 0xd9, }, 5, 0, "", "",
"c4 e2 6d cf d9 \tvgf2p8mulb %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xcf, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 cf d9 \tvgf2p8mulb %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 cf 9c c8 78 56 34 12 \tvgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0x69, 0xdc, 0xd9, }, 5, 0, "", "",
"c4 e2 69 dc d9 \tvaesenc %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xdc, 0xd9, }, 5, 0, "", "",
"c4 e2 6d dc d9 \tvaesenc %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdc, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 dc d9 \tvaesenc %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdc, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 dc 9c c8 78 56 34 12 \tvaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0x69, 0xdd, 0xd9, }, 5, 0, "", "",
"c4 e2 69 dd d9 \tvaesenclast %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xdd, 0xd9, }, 5, 0, "", "",
"c4 e2 6d dd d9 \tvaesenclast %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdd, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 dd d9 \tvaesenclast %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdd, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 dd 9c c8 78 56 34 12 \tvaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0x69, 0xde, 0xd9, }, 5, 0, "", "",
"c4 e2 69 de d9 \tvaesdec %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xde, 0xd9, }, 5, 0, "", "",
"c4 e2 6d de d9 \tvaesdec %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 de d9 \tvaesdec %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 de 9c c8 78 56 34 12 \tvaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0xc4, 0xe2, 0x69, 0xdf, 0xd9, }, 5, 0, "", "",
"c4 e2 69 df d9 \tvaesdeclast %xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe2, 0x6d, 0xdf, 0xd9, }, 5, 0, "", "",
"c4 e2 6d df d9 \tvaesdeclast %ymm1,%ymm2,%ymm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0xd9, }, 6, 0, "", "",
"62 f2 6d 48 df d9 \tvaesdeclast %zmm1,%zmm2,%zmm3",},
{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f2 6d 48 df 9c c8 78 56 34 12 \tvaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",},
{{0x62, 0xf3, 0x4d, 0x48, 0x03, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 48 03 fd 12 \tvalignd $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xcd, 0x48, 0x03, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 48 03 fd 12 \tvalignq $0x12,%zmm5,%zmm6,%zmm7",},
{{0xc4, 0xe3, 0x7d, 0x08, 0xd6, 0x05, }, 6, 0, "", "",
"c4 e3 7d 08 d6 05 \tvroundps $0x5,%ymm6,%ymm2",},
{{0x62, 0xf3, 0x7d, 0x48, 0x08, 0xf5, 0x12, }, 7, 0, "", "",
"62 f3 7d 48 08 f5 12 \tvrndscaleps $0x12,%zmm5,%zmm6",},
{{0xc4, 0xe3, 0x7d, 0x09, 0xd6, 0x05, }, 6, 0, "", "",
"c4 e3 7d 09 d6 05 \tvroundpd $0x5,%ymm6,%ymm2",},
{{0x62, 0xf3, 0xfd, 0x48, 0x09, 0xf5, 0x12, }, 7, 0, "", "",
"62 f3 fd 48 09 f5 12 \tvrndscalepd $0x12,%zmm5,%zmm6",},
{{0xc4, 0xe3, 0x49, 0x0a, 0xd4, 0x05, }, 6, 0, "", "",
"c4 e3 49 0a d4 05 \tvroundss $0x5,%xmm4,%xmm6,%xmm2",},
{{0x62, 0xf3, 0x55, 0x0f, 0x0a, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 55 0f 0a f4 12 \tvrndscaless $0x12,%xmm4,%xmm5,%xmm6{%k7}",},
{{0xc4, 0xe3, 0x49, 0x0b, 0xd4, 0x05, }, 6, 0, "", "",
"c4 e3 49 0b d4 05 \tvroundsd $0x5,%xmm4,%xmm6,%xmm2",},
{{0x62, 0xf3, 0xd5, 0x0f, 0x0b, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 d5 0f 0b f4 12 \tvrndscalesd $0x12,%xmm4,%xmm5,%xmm6{%k7}",},
{{0xc4, 0xe3, 0x5d, 0x18, 0xf4, 0x05, }, 6, 0, "", "",
"c4 e3 5d 18 f4 05 \tvinsertf128 $0x5,%xmm4,%ymm4,%ymm6",},
{{0x62, 0xf3, 0x55, 0x4f, 0x18, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 55 4f 18 f4 12 \tvinsertf32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}",},
{{0x62, 0xf3, 0xd5, 0x4f, 0x18, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 d5 4f 18 f4 12 \tvinsertf64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}",},
{{0xc4, 0xe3, 0x7d, 0x19, 0xe4, 0x05, }, 6, 0, "", "",
"c4 e3 7d 19 e4 05 \tvextractf128 $0x5,%ymm4,%xmm4",},
{{0x62, 0xf3, 0x7d, 0x4f, 0x19, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 7d 4f 19 ee 12 \tvextractf32x4 $0x12,%zmm5,%xmm6{%k7}",},
{{0x62, 0xf3, 0xfd, 0x4f, 0x19, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 fd 4f 19 ee 12 \tvextractf64x2 $0x12,%zmm5,%xmm6{%k7}",},
{{0x62, 0xf3, 0x4d, 0x4f, 0x1a, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 4f 1a fd 12 \tvinsertf32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}",},
{{0x62, 0xf3, 0xcd, 0x4f, 0x1a, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 4f 1a fd 12 \tvinsertf64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}",},
{{0x62, 0xf3, 0x7d, 0x4f, 0x1b, 0xf7, 0x12, }, 7, 0, "", "",
"62 f3 7d 4f 1b f7 12 \tvextractf32x8 $0x12,%zmm6,%ymm7{%k7}",},
{{0x62, 0xf3, 0xfd, 0x4f, 0x1b, 0xf7, 0x12, }, 7, 0, "", "",
"62 f3 fd 4f 1b f7 12 \tvextractf64x4 $0x12,%zmm6,%ymm7{%k7}",},
{{0x62, 0xf3, 0x45, 0x48, 0x1e, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 45 48 1e ee 12 \tvpcmpud $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0xc5, 0x48, 0x1e, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 c5 48 1e ee 12 \tvpcmpuq $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0x45, 0x48, 0x1f, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 45 48 1f ee 12 \tvpcmpd $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0xc5, 0x48, 0x1f, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 c5 48 1f ee 12 \tvpcmpq $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0x4d, 0x48, 0x23, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 48 23 fd 12 \tvshuff32x4 $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xcd, 0x48, 0x23, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 48 23 fd 12 \tvshuff64x2 $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0x4d, 0x48, 0x25, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 48 25 fd 12 \tvpternlogd $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xcd, 0x48, 0x25, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 48 25 fd 12 \tvpternlogq $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0x7d, 0x48, 0x26, 0xfe, 0x12, }, 7, 0, "", "",
"62 f3 7d 48 26 fe 12 \tvgetmantps $0x12,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xfd, 0x48, 0x26, 0xfe, 0x12, }, 7, 0, "", "",
"62 f3 fd 48 26 fe 12 \tvgetmantpd $0x12,%zmm6,%zmm7",},
{{0x62, 0xf3, 0x4d, 0x0f, 0x27, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 0f 27 fd 12 \tvgetmantss $0x12,%xmm5,%xmm6,%xmm7{%k7}",},
{{0x62, 0xf3, 0xcd, 0x0f, 0x27, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 0f 27 fd 12 \tvgetmantsd $0x12,%xmm5,%xmm6,%xmm7{%k7}",},
{{0xc4, 0xe3, 0x5d, 0x38, 0xf4, 0x05, }, 6, 0, "", "",
"c4 e3 5d 38 f4 05 \tvinserti128 $0x5,%xmm4,%ymm4,%ymm6",},
{{0x62, 0xf3, 0x55, 0x4f, 0x38, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 55 4f 38 f4 12 \tvinserti32x4 $0x12,%xmm4,%zmm5,%zmm6{%k7}",},
{{0x62, 0xf3, 0xd5, 0x4f, 0x38, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 d5 4f 38 f4 12 \tvinserti64x2 $0x12,%xmm4,%zmm5,%zmm6{%k7}",},
{{0xc4, 0xe3, 0x7d, 0x39, 0xe6, 0x05, }, 6, 0, "", "",
"c4 e3 7d 39 e6 05 \tvextracti128 $0x5,%ymm4,%xmm6",},
{{0x62, 0xf3, 0x7d, 0x4f, 0x39, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 7d 4f 39 ee 12 \tvextracti32x4 $0x12,%zmm5,%xmm6{%k7}",},
{{0x62, 0xf3, 0xfd, 0x4f, 0x39, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 fd 4f 39 ee 12 \tvextracti64x2 $0x12,%zmm5,%xmm6{%k7}",},
{{0x62, 0xf3, 0x4d, 0x4f, 0x3a, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 4f 3a fd 12 \tvinserti32x8 $0x12,%ymm5,%zmm6,%zmm7{%k7}",},
{{0x62, 0xf3, 0xcd, 0x4f, 0x3a, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 4f 3a fd 12 \tvinserti64x4 $0x12,%ymm5,%zmm6,%zmm7{%k7}",},
{{0x62, 0xf3, 0x7d, 0x4f, 0x3b, 0xf7, 0x12, }, 7, 0, "", "",
"62 f3 7d 4f 3b f7 12 \tvextracti32x8 $0x12,%zmm6,%ymm7{%k7}",},
{{0x62, 0xf3, 0xfd, 0x4f, 0x3b, 0xf7, 0x12, }, 7, 0, "", "",
"62 f3 fd 4f 3b f7 12 \tvextracti64x4 $0x12,%zmm6,%ymm7{%k7}",},
{{0x62, 0xf3, 0x45, 0x48, 0x3e, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 45 48 3e ee 12 \tvpcmpub $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0xc5, 0x48, 0x3e, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 c5 48 3e ee 12 \tvpcmpuw $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0x45, 0x48, 0x3f, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 45 48 3f ee 12 \tvpcmpb $0x12,%zmm6,%zmm7,%k5",},
{{0x62, 0xf3, 0xc5, 0x48, 0x3f, 0xee, 0x12, }, 7, 0, "", "",
"62 f3 c5 48 3f ee 12 \tvpcmpw $0x12,%zmm6,%zmm7,%k5",},
{{0xc4, 0xe3, 0x4d, 0x42, 0xd4, 0x05, }, 6, 0, "", "",
"c4 e3 4d 42 d4 05 \tvmpsadbw $0x5,%ymm4,%ymm6,%ymm2",},
{{0x62, 0xf3, 0x55, 0x48, 0x42, 0xf4, 0x12, }, 7, 0, "", "",
"62 f3 55 48 42 f4 12 \tvdbpsadbw $0x12,%zmm4,%zmm5,%zmm6",},
{{0x62, 0xf3, 0x4d, 0x48, 0x43, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 48 43 fd 12 \tvshufi32x4 $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xcd, 0x48, 0x43, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 48 43 fd 12 \tvshufi64x2 $0x12,%zmm5,%zmm6,%zmm7",},
{{0xc4, 0xe3, 0x69, 0x44, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 69 44 d9 12 \tvpclmulqdq $0x12,%xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe3, 0x6d, 0x44, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 6d 44 d9 12 \tvpclmulqdq $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0x6d, 0x48, 0x44, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 48 44 d9 12 \tvpclmulqdq $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf3, 0x4d, 0x48, 0x50, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 48 50 fd 12 \tvrangeps $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xcd, 0x48, 0x50, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 48 50 fd 12 \tvrangepd $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0x4d, 0x08, 0x51, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 08 51 fd 12 \tvrangess $0x12,%xmm5,%xmm6,%xmm7",},
{{0x62, 0xf3, 0xcd, 0x08, 0x51, 0xfd, 0x12, }, 7, 0, "", "",
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{{0x62, 0xf3, 0x4d, 0x48, 0x54, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 48 54 fd 12 \tvfixupimmps $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xcd, 0x48, 0x54, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 48 54 fd 12 \tvfixupimmpd $0x12,%zmm5,%zmm6,%zmm7",},
{{0x62, 0xf3, 0x4d, 0x0f, 0x55, 0xfd, 0x12, }, 7, 0, "", "",
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{{0x62, 0xf3, 0xcd, 0x0f, 0x55, 0xfd, 0x12, }, 7, 0, "", "",
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{{0x62, 0xf3, 0x7d, 0x48, 0x56, 0xfe, 0x12, }, 7, 0, "", "",
"62 f3 7d 48 56 fe 12 \tvreduceps $0x12,%zmm6,%zmm7",},
{{0x62, 0xf3, 0xfd, 0x48, 0x56, 0xfe, 0x12, }, 7, 0, "", "",
"62 f3 fd 48 56 fe 12 \tvreducepd $0x12,%zmm6,%zmm7",},
{{0x62, 0xf3, 0x4d, 0x08, 0x57, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 4d 08 57 fd 12 \tvreducess $0x12,%xmm5,%xmm6,%xmm7",},
{{0x62, 0xf3, 0xcd, 0x08, 0x57, 0xfd, 0x12, }, 7, 0, "", "",
"62 f3 cd 08 57 fd 12 \tvreducesd $0x12,%xmm5,%xmm6,%xmm7",},
{{0x62, 0xf3, 0x7d, 0x48, 0x66, 0xef, 0x12, }, 7, 0, "", "",
"62 f3 7d 48 66 ef 12 \tvfpclassps $0x12,%zmm7,%k5",},
{{0x62, 0xf3, 0xfd, 0x48, 0x66, 0xef, 0x12, }, 7, 0, "", "",
"62 f3 fd 48 66 ef 12 \tvfpclasspd $0x12,%zmm7,%k5",},
{{0x62, 0xf3, 0x7d, 0x08, 0x67, 0xef, 0x12, }, 7, 0, "", "",
"62 f3 7d 08 67 ef 12 \tvfpclassss $0x12,%xmm7,%k5",},
{{0x62, 0xf3, 0xfd, 0x08, 0x67, 0xef, 0x12, }, 7, 0, "", "",
"62 f3 fd 08 67 ef 12 \tvfpclasssd $0x12,%xmm7,%k5",},
{{0x62, 0xf3, 0xed, 0x08, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
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{{0x62, 0xf3, 0xed, 0x28, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 70 d9 12 \tvpshldw $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x70, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 70 d9 12 \tvpshldw $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf3, 0x6d, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 08 71 d9 12 \tvpshldd $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0x6d, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 28 71 d9 12 \tvpshldd $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0x6d, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 48 71 d9 12 \tvpshldd $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf3, 0xed, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 71 d9 12 \tvpshldq $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 71 d9 12 \tvpshldq $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 71 d9 12 \tvpshldq $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf3, 0xed, 0x08, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 72 d9 12 \tvpshrdw $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 72 d9 12 \tvpshrdw $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x72, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 72 d9 12 \tvpshrdw $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf3, 0x6d, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 08 73 d9 12 \tvpshrdd $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0x6d, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 28 73 d9 12 \tvpshrdd $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0x6d, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 6d 48 73 d9 12 \tvpshrdd $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf3, 0xed, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 08 73 d9 12 \tvpshrdq $0x12,%xmm1,%xmm2,%xmm3",},
{{0x62, 0xf3, 0xed, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 28 73 d9 12 \tvpshrdq $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 73 d9 12 \tvpshrdq $0x12,%zmm1,%zmm2,%zmm3",},
{{0x66, 0x0f, 0x3a, 0xce, 0xd9, 0x12, }, 6, 0, "", "",
"66 0f 3a ce d9 12 \tgf2p8affineqb $0x12,%xmm1,%xmm3",},
{{0xc4, 0xe3, 0xe9, 0xce, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 e9 ce d9 12 \tvgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe3, 0xed, 0xce, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 ed ce d9 12 \tvgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0xce, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 ce d9 12 \tvgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3",},
{{0x66, 0x0f, 0x3a, 0xcf, 0xd9, 0x12, }, 6, 0, "", "",
"66 0f 3a cf d9 12 \tgf2p8affineinvqb $0x12,%xmm1,%xmm3",},
{{0xc4, 0xe3, 0xe9, 0xcf, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 e9 cf d9 12 \tvgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3",},
{{0xc4, 0xe3, 0xed, 0xcf, 0xd9, 0x12, }, 6, 0, "", "",
"c4 e3 ed cf d9 12 \tvgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3",},
{{0x62, 0xf3, 0xed, 0x48, 0xcf, 0xd9, 0x12, }, 7, 0, "", "",
"62 f3 ed 48 cf d9 12 \tvgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3",},
{{0x62, 0xf1, 0x4d, 0x48, 0x72, 0xc5, 0x12, }, 7, 0, "", "",
"62 f1 4d 48 72 c5 12 \tvprord $0x12,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xcd, 0x48, 0x72, 0xc5, 0x12, }, 7, 0, "", "",
"62 f1 cd 48 72 c5 12 \tvprorq $0x12,%zmm5,%zmm6",},
{{0x62, 0xf1, 0x4d, 0x48, 0x72, 0xcd, 0x12, }, 7, 0, "", "",
"62 f1 4d 48 72 cd 12 \tvprold $0x12,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xcd, 0x48, 0x72, 0xcd, 0x12, }, 7, 0, "", "",
"62 f1 cd 48 72 cd 12 \tvprolq $0x12,%zmm5,%zmm6",},
{{0x0f, 0x72, 0xe6, 0x02, }, 4, 0, "", "",
"0f 72 e6 02 \tpsrad $0x2,%mm6",},
{{0xc5, 0xed, 0x72, 0xe6, 0x05, }, 5, 0, "", "",
"c5 ed 72 e6 05 \tvpsrad $0x5,%ymm6,%ymm2",},
{{0x62, 0xf1, 0x6d, 0x48, 0x72, 0xe6, 0x05, }, 7, 0, "", "",
"62 f1 6d 48 72 e6 05 \tvpsrad $0x5,%zmm6,%zmm2",},
{{0x62, 0xf1, 0xed, 0x48, 0x72, 0xe6, 0x05, }, 7, 0, "", "",
"62 f1 ed 48 72 e6 05 \tvpsraq $0x5,%zmm6,%zmm2",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c6 8c fd 7b 00 00 00 \tvgatherpf0dps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c6 8c fd 7b 00 00 00 \tvgatherpf0dpd 0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c6 94 fd 7b 00 00 00 \tvgatherpf1dps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c6 94 fd 7b 00 00 00 \tvgatherpf1dpd 0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c6 ac fd 7b 00 00 00 \tvscatterpf0dps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c6 ac fd 7b 00 00 00 \tvscatterpf0dpd 0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc6, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c6 b4 fd 7b 00 00 00 \tvscatterpf1dps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc6, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c6 b4 fd 7b 00 00 00 \tvscatterpf1dpd 0x7b(%ebp,%ymm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c7 8c fd 7b 00 00 00 \tvgatherpf0qps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0x8c, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c7 8c fd 7b 00 00 00 \tvgatherpf0qpd 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c7 94 fd 7b 00 00 00 \tvgatherpf1qps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0x94, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c7 94 fd 7b 00 00 00 \tvgatherpf1qpd 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c7 ac fd 7b 00 00 00 \tvscatterpf0qps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0xac, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c7 ac fd 7b 00 00 00 \tvscatterpf0qpd 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0x7d, 0x49, 0xc7, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 7d 49 c7 b4 fd 7b 00 00 00 \tvscatterpf1qps 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf2, 0xfd, 0x49, 0xc7, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "",
"62 f2 fd 49 c7 b4 fd 7b 00 00 00 \tvscatterpf1qpd 0x7b(%ebp,%zmm7,8){%k1}",},
{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 48 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x4f, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 4f 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6{%k7}",},
{{0x62, 0xf1, 0xd5, 0xcf, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 cf 58 f4 \tvaddpd %zmm4,%zmm5,%zmm6{%k7}{z}",},
{{0x62, 0xf1, 0xd5, 0x18, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 18 58 f4 \tvaddpd {rn-sae},%zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 58 58 f4 \tvaddpd {ru-sae},%zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x38, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 38 58 f4 \tvaddpd {rd-sae},%zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x78, 0x58, 0xf4, }, 6, 0, "", "",
"62 f1 d5 78 58 f4 \tvaddpd {rz-sae},%zmm4,%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0x31, }, 6, 0, "", "",
"62 f1 d5 48 58 31 \tvaddpd (%ecx),%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0xb4, 0xc8, 0x23, 0x01, 0x00, 0x00, }, 11, 0, "", "",
"62 f1 d5 48 58 b4 c8 23 01 00 00 \tvaddpd 0x123(%eax,%ecx,8),%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0x31, }, 6, 0, "", "",
"62 f1 d5 58 58 31 \tvaddpd (%ecx){1to8},%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x48, 0x58, 0x72, 0x7f, }, 7, 0, "", "",
"62 f1 d5 48 58 72 7f \tvaddpd 0x1fc0(%edx),%zmm5,%zmm6",},
{{0x62, 0xf1, 0xd5, 0x58, 0x58, 0x72, 0x7f, }, 7, 0, "", "",
"62 f1 d5 58 58 72 7f \tvaddpd 0x3f8(%edx){1to8},%zmm5,%zmm6",},
{{0x62, 0xf1, 0x4c, 0x58, 0xc2, 0x6a, 0x7f, 0x08, }, 8, 0, "", "",
"62 f1 4c 58 c2 6a 7f 08 \tvcmpeq_uqps 0x1fc(%edx){1to16},%zmm6,%k5",},
{{0x62, 0xf1, 0xe7, 0x0f, 0xc2, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, 0x01, }, 12, 0, "", "",
"62 f1 e7 0f c2 ac c8 23 01 00 00 01 \tvcmpltsd 0x123(%eax,%ecx,8),%xmm3,%k5{%k7}",},
{{0x62, 0xf1, 0xd7, 0x1f, 0xc2, 0xec, 0x02, }, 7, 0, "", "",
"62 f1 d7 1f c2 ec 02 \tvcmplesd {sae},%xmm4,%xmm5,%k5{%k7}",},
{{0x62, 0xf3, 0x5d, 0x0f, 0x27, 0xac, 0xc8, 0x23, 0x01, 0x00, 0x00, 0x5b, }, 12, 0, "", "",
"62 f3 5d 0f 27 ac c8 23 01 00 00 5b \tvgetmantss $0x5b,0x123(%eax,%ecx,8),%xmm4,%xmm5{%k7}",},
{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"f3 0f 1b 00 \tbndmk (%eax),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f3 0f 1b 05 78 56 34 12 \tbndmk 0x12345678,%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
"f3 0f 1b 18 \tbndmk (%eax),%bnd3",},
{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
"f3 0f 1b 04 01 \tbndmk (%ecx,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
"f3 0f 1b 04 08 \tbndmk (%eax,%ecx,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
"f3 0f 1b 04 c8 \tbndmk (%eax,%ecx,8),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
"f3 0f 1b 40 12 \tbndmk 0x12(%eax),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
"f3 0f 1b 45 12 \tbndmk 0x12(%ebp),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
"f3 0f 1b 44 01 12 \tbndmk 0x12(%ecx,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"f3 0f 1b 44 05 12 \tbndmk 0x12(%ebp,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"f3 0f 1b 44 08 12 \tbndmk 0x12(%eax,%ecx,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"f3 0f 1b 44 c8 12 \tbndmk 0x12(%eax,%ecx,8),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%eax),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%ebp),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%ecx,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f3 0f 1a 05 78 56 34 12 \tbndcl 0x12345678,%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
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{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%eax),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%ebp),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%ecx,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%ebp,%eax,1),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%eax,%ecx,1),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%eax,%ecx,8),%bnd0",},
{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
"f3 0f 1a c0 \tbndcl %eax,%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
"f2 0f 1a 00 \tbndcu (%eax),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1a 05 78 56 34 12 \tbndcu 0x12345678,%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
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{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
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{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
"f2 0f 1a 04 08 \tbndcu (%eax,%ecx,1),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
"f2 0f 1a 04 c8 \tbndcu (%eax,%ecx,8),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
"f2 0f 1a 40 12 \tbndcu 0x12(%eax),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
"f2 0f 1a 45 12 \tbndcu 0x12(%ebp),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
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{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
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{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
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{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
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{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%eax),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%ebp),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%ecx,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%ebp,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1a 84 08 78 56 34 12 \tbndcu 0x12345678(%eax,%ecx,1),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%eax,%ecx,8),%bnd0",},
{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
"f2 0f 1a c0 \tbndcu %eax,%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"f2 0f 1b 00 \tbndcn (%eax),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1b 05 78 56 34 12 \tbndcn 0x12345678,%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
"f2 0f 1b 18 \tbndcn (%eax),%bnd3",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
"f2 0f 1b 04 01 \tbndcn (%ecx,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
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{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
"f2 0f 1b 04 c8 \tbndcn (%eax,%ecx,8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
"f2 0f 1b 40 12 \tbndcn 0x12(%eax),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
"f2 0f 1b 45 12 \tbndcn 0x12(%ebp),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 01 12 \tbndcn 0x12(%ecx,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 05 12 \tbndcn 0x12(%ebp,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 08 12 \tbndcn 0x12(%eax,%ecx,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"f2 0f 1b 44 c8 12 \tbndcn 0x12(%eax,%ecx,8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%eax),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%ebp),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%ecx,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%ebp,%eax,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%eax,%ecx,1),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%eax,%ecx,8),%bnd0",},
{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "",
"f2 0f 1b c0 \tbndcn %eax,%bnd0",},
{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
"66 0f 1a 00 \tbndmov (%eax),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1a 05 78 56 34 12 \tbndmov 0x12345678,%bnd0",},
{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
"66 0f 1a 18 \tbndmov (%eax),%bnd3",},
{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
"66 0f 1a 04 01 \tbndmov (%ecx,%eax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%eax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
"66 0f 1a 04 08 \tbndmov (%eax,%ecx,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
"66 0f 1a 04 c8 \tbndmov (%eax,%ecx,8),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
"66 0f 1a 40 12 \tbndmov 0x12(%eax),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
"66 0f 1a 45 12 \tbndmov 0x12(%ebp),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 01 12 \tbndmov 0x12(%ecx,%eax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 05 12 \tbndmov 0x12(%ebp,%eax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 08 12 \tbndmov 0x12(%eax,%ecx,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"66 0f 1a 44 c8 12 \tbndmov 0x12(%eax,%ecx,8),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%eax),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%ebp),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%ecx,%eax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%ebp,%eax,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%eax,%ecx,1),%bnd0",},
{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%eax,%ecx,8),%bnd0",},
{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
"66 0f 1b 00 \tbndmov %bnd0,(%eax)",},
{{0x66, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1b 05 78 56 34 12 \tbndmov %bnd0,0x12345678",},
{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
"66 0f 1b 18 \tbndmov %bnd3,(%eax)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
"66 0f 1b 04 01 \tbndmov %bnd0,(%ecx,%eax,1)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%eax,1)",},
{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
"66 0f 1b 04 08 \tbndmov %bnd0,(%eax,%ecx,1)",},
{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
"66 0f 1b 04 c8 \tbndmov %bnd0,(%eax,%ecx,8)",},
{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%eax)",},
{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%ebp)",},
{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
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{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%ebp,%eax,1)",},
{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%eax,%ecx,1)",},
{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%eax,%ecx,8)",},
{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%eax)",},
{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%ebp)",},
{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%ecx,%eax,1)",},
{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 05 78 56 34 12 \tbndmov %bnd0,0x12345678(%ebp,%eax,1)",},
{{0x66, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 08 78 56 34 12 \tbndmov %bnd0,0x12345678(%eax,%ecx,1)",},
{{0x66, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"66 0f 1b 84 c8 78 56 34 12 \tbndmov %bnd0,0x12345678(%eax,%ecx,8)",},
{{0x66, 0x0f, 0x1a, 0xc8, }, 4, 0, "", "",
"66 0f 1a c8 \tbndmov %bnd0,%bnd1",},
{{0x66, 0x0f, 0x1a, 0xc1, }, 4, 0, "", "",
"66 0f 1a c1 \tbndmov %bnd1,%bnd0",},
{{0x0f, 0x1a, 0x00, }, 3, 0, "", "",
"0f 1a 00 \tbndldx (%eax),%bnd0",},
{{0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1a 05 78 56 34 12 \tbndldx 0x12345678,%bnd0",},
{{0x0f, 0x1a, 0x18, }, 3, 0, "", "",
"0f 1a 18 \tbndldx (%eax),%bnd3",},
{{0x0f, 0x1a, 0x04, 0x01, }, 4, 0, "", "",
"0f 1a 04 01 \tbndldx (%ecx,%eax,1),%bnd0",},
{{0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 04 05 78 56 34 12 \tbndldx 0x12345678(,%eax,1),%bnd0",},
{{0x0f, 0x1a, 0x04, 0x08, }, 4, 0, "", "",
"0f 1a 04 08 \tbndldx (%eax,%ecx,1),%bnd0",},
{{0x0f, 0x1a, 0x40, 0x12, }, 4, 0, "", "",
"0f 1a 40 12 \tbndldx 0x12(%eax),%bnd0",},
{{0x0f, 0x1a, 0x45, 0x12, }, 4, 0, "", "",
"0f 1a 45 12 \tbndldx 0x12(%ebp),%bnd0",},
{{0x0f, 0x1a, 0x44, 0x01, 0x12, }, 5, 0, "", "",
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{{0x0f, 0x1a, 0x44, 0x05, 0x12, }, 5, 0, "", "",
"0f 1a 44 05 12 \tbndldx 0x12(%ebp,%eax,1),%bnd0",},
{{0x0f, 0x1a, 0x44, 0x08, 0x12, }, 5, 0, "", "",
"0f 1a 44 08 12 \tbndldx 0x12(%eax,%ecx,1),%bnd0",},
{{0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1a 80 78 56 34 12 \tbndldx 0x12345678(%eax),%bnd0",},
{{0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
"0f 1a 85 78 56 34 12 \tbndldx 0x12345678(%ebp),%bnd0",},
{{0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f 1a 84 01 78 56 34 12 \tbndldx 0x12345678(%ecx,%eax,1),%bnd0",},
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{{0x62, 0xf5, 0x6c, 0x28, 0x5f, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 28 5f 8c c8 78 56 34 12 \tvmaxph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5f, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 5f cb \tvmaxsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5f, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 5f 8c c8 78 56 34 12 \tvmaxsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x5d, 0xcb, }, 6, 0, "", "",
"62 f5 6c 48 5d cb \tvminph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x5d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 48 5d 8c c8 78 56 34 12 \tvminph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x5d, 0xcb, }, 6, 0, "", "",
"62 f5 6c 08 5d cb \tvminph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x5d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 08 5d 8c c8 78 56 34 12 \tvminph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x5d, 0xcb, }, 6, 0, "", "",
"62 f5 6c 28 5d cb \tvminph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x5d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 28 5d 8c c8 78 56 34 12 \tvminph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5d, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 5d cb \tvminsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 5d 8c c8 78 56 34 12 \tvminsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x7e, 0x08, 0x11, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7e 08 11 8c c8 78 56 34 12 \tvmovsh %xmm1,0x12345678(%eax,%ecx,8)",},
{{0x62, 0xf5, 0x7e, 0x08, 0x10, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7e 08 10 8c c8 78 56 34 12 \tvmovsh 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x10, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 10 cb \tvmovsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x7d, 0x08, 0x7e, 0xc8, }, 6, 0, "", "",
"62 f5 7d 08 7e c8 \tvmovw %xmm1,%eax",},
{{0x62, 0xf5, 0x7d, 0x08, 0x7e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7d 08 7e 8c c8 78 56 34 12 \tvmovw %xmm1,0x12345678(%eax,%ecx,8)",},
{{0x62, 0xf5, 0x7d, 0x08, 0x6e, 0xc8, }, 6, 0, "", "",
"62 f5 7d 08 6e c8 \tvmovw %eax,%xmm1",},
{{0x62, 0xf5, 0x7d, 0x08, 0x6e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7d 08 6e 8c c8 78 56 34 12 \tvmovw 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x59, 0xcb, }, 6, 0, "", "",
"62 f5 6c 48 59 cb \tvmulph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x59, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 48 59 8c c8 78 56 34 12 \tvmulph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x59, 0xcb, }, 6, 0, "", "",
"62 f5 6c 08 59 cb \tvmulph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x59, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 08 59 8c c8 78 56 34 12 \tvmulph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x59, 0xcb, }, 6, 0, "", "",
"62 f5 6c 28 59 cb \tvmulph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x59, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 28 59 8c c8 78 56 34 12 \tvmulph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x59, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 59 cb \tvmulsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x59, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 59 8c c8 78 56 34 12 \tvmulsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf6, 0x7d, 0x48, 0x4c, 0xca, }, 6, 0, "", "",
"62 f6 7d 48 4c ca \tvrcpph %zmm2,%zmm1",},
{{0x62, 0xf6, 0x7d, 0x48, 0x4c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 48 4c 8c c8 78 56 34 12 \tvrcpph 0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf6, 0x7d, 0x08, 0x4c, 0xca, }, 6, 0, "", "",
"62 f6 7d 08 4c ca \tvrcpph %xmm2,%xmm1",},
{{0x62, 0xf6, 0x7d, 0x08, 0x4c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 08 4c 8c c8 78 56 34 12 \tvrcpph 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf6, 0x7d, 0x28, 0x4c, 0xca, }, 6, 0, "", "",
"62 f6 7d 28 4c ca \tvrcpph %ymm2,%ymm1",},
{{0x62, 0xf6, 0x7d, 0x28, 0x4c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 28 4c 8c c8 78 56 34 12 \tvrcpph 0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x4d, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 4d cb \tvrcpsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x4d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 4d 8c c8 78 56 34 12 \tvrcpsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf3, 0x7c, 0x48, 0x56, 0xca, 0x12, }, 7, 0, "", "",
"62 f3 7c 48 56 ca 12 \tvreduceph $0x12,%zmm2,%zmm1",},
{{0x62, 0xf3, 0x7c, 0x48, 0x56, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 7c 48 56 8c c8 78 56 34 12 12 \tvreduceph $0x12,0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf3, 0x7c, 0x08, 0x56, 0xca, 0x12, }, 7, 0, "", "",
"62 f3 7c 08 56 ca 12 \tvreduceph $0x12,%xmm2,%xmm1",},
{{0x62, 0xf3, 0x7c, 0x08, 0x56, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 7c 08 56 8c c8 78 56 34 12 12 \tvreduceph $0x12,0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf3, 0x7c, 0x28, 0x56, 0xca, 0x12, }, 7, 0, "", "",
"62 f3 7c 28 56 ca 12 \tvreduceph $0x12,%ymm2,%ymm1",},
{{0x62, 0xf3, 0x7c, 0x28, 0x56, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 7c 28 56 8c c8 78 56 34 12 12 \tvreduceph $0x12,0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf3, 0x6c, 0x08, 0x57, 0xcb, 0x12, }, 7, 0, "", "",
"62 f3 6c 08 57 cb 12 \tvreducesh $0x12,%xmm3,%xmm2,%xmm1",},
{{0x62, 0xf3, 0x6c, 0x08, 0x57, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 6c 08 57 8c c8 78 56 34 12 12 \tvreducesh $0x12,0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf3, 0x7c, 0x48, 0x08, 0xca, 0x12, }, 7, 0, "", "",
"62 f3 7c 48 08 ca 12 \tvrndscaleph $0x12,%zmm2,%zmm1",},
{{0x62, 0xf3, 0x7c, 0x48, 0x08, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 7c 48 08 8c c8 78 56 34 12 12 \tvrndscaleph $0x12,0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf3, 0x7c, 0x08, 0x08, 0xca, 0x12, }, 7, 0, "", "",
"62 f3 7c 08 08 ca 12 \tvrndscaleph $0x12,%xmm2,%xmm1",},
{{0x62, 0xf3, 0x7c, 0x08, 0x08, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 7c 08 08 8c c8 78 56 34 12 12 \tvrndscaleph $0x12,0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf3, 0x7c, 0x28, 0x08, 0xca, 0x12, }, 7, 0, "", "",
"62 f3 7c 28 08 ca 12 \tvrndscaleph $0x12,%ymm2,%ymm1",},
{{0x62, 0xf3, 0x7c, 0x28, 0x08, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 7c 28 08 8c c8 78 56 34 12 12 \tvrndscaleph $0x12,0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf3, 0x6c, 0x08, 0x0a, 0xcb, 0x12, }, 7, 0, "", "",
"62 f3 6c 08 0a cb 12 \tvrndscalesh $0x12,%xmm3,%xmm2,%xmm1",},
{{0x62, 0xf3, 0x6c, 0x08, 0x0a, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x12, }, 12, 0, "", "",
"62 f3 6c 08 0a 8c c8 78 56 34 12 12 \tvrndscalesh $0x12,0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf6, 0x7d, 0x48, 0x4e, 0xca, }, 6, 0, "", "",
"62 f6 7d 48 4e ca \tvrsqrtph %zmm2,%zmm1",},
{{0x62, 0xf6, 0x7d, 0x48, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 48 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf6, 0x7d, 0x08, 0x4e, 0xca, }, 6, 0, "", "",
"62 f6 7d 08 4e ca \tvrsqrtph %xmm2,%xmm1",},
{{0x62, 0xf6, 0x7d, 0x08, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 08 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf6, 0x7d, 0x28, 0x4e, 0xca, }, 6, 0, "", "",
"62 f6 7d 28 4e ca \tvrsqrtph %ymm2,%ymm1",},
{{0x62, 0xf6, 0x7d, 0x28, 0x4e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 7d 28 4e 8c c8 78 56 34 12 \tvrsqrtph 0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x4f, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 4f cb \tvrsqrtsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x4f, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 4f 8c c8 78 56 34 12 \tvrsqrtsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x48, 0x2c, 0xcb, }, 6, 0, "", "",
"62 f6 6d 48 2c cb \tvscalefph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf6, 0x6d, 0x48, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 48 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2c, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 2c cb \tvscalefph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x28, 0x2c, 0xcb, }, 6, 0, "", "",
"62 f6 6d 28 2c cb \tvscalefph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf6, 0x6d, 0x28, 0x2c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 28 2c 8c c8 78 56 34 12 \tvscalefph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2d, 0xcb, }, 6, 0, "", "",
"62 f6 6d 08 2d cb \tvscalefsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf6, 0x6d, 0x08, 0x2d, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f6 6d 08 2d 8c c8 78 56 34 12 \tvscalefsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x48, 0x51, 0xca, }, 6, 0, "", "",
"62 f5 7c 48 51 ca \tvsqrtph %zmm2,%zmm1",},
{{0x62, 0xf5, 0x7c, 0x48, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 48 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%eax,%ecx,8),%zmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x51, 0xca, }, 6, 0, "", "",
"62 f5 7c 08 51 ca \tvsqrtph %xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 08 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%eax,%ecx,8),%xmm1",},
{{0x62, 0xf5, 0x7c, 0x28, 0x51, 0xca, }, 6, 0, "", "",
"62 f5 7c 28 51 ca \tvsqrtph %ymm2,%ymm1",},
{{0x62, 0xf5, 0x7c, 0x28, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 28 51 8c c8 78 56 34 12 \tvsqrtph 0x12345678(%eax,%ecx,8),%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x51, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 51 cb \tvsqrtsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x51, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 51 8c c8 78 56 34 12 \tvsqrtsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6c 48 5c cb \tvsubph %zmm3,%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x48, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 48 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%eax,%ecx,8),%zmm2,%zmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6c 08 5c cb \tvsubph %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x08, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 08 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6c 28 5c cb \tvsubph %ymm3,%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6c, 0x28, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6c 28 5c 8c c8 78 56 34 12 \tvsubph 0x12345678(%eax,%ecx,8),%ymm2,%ymm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5c, 0xcb, }, 6, 0, "", "",
"62 f5 6e 08 5c cb \tvsubsh %xmm3,%xmm2,%xmm1",},
{{0x62, 0xf5, 0x6e, 0x08, 0x5c, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 6e 08 5c 8c c8 78 56 34 12 \tvsubsh 0x12345678(%eax,%ecx,8),%xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x2e, 0xca, }, 6, 0, "", "",
"62 f5 7c 08 2e ca \tvucomish %xmm2,%xmm1",},
{{0x62, 0xf5, 0x7c, 0x08, 0x2e, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "",
"62 f5 7c 08 2e 8c c8 78 56 34 12 \tvucomish 0x12345678(%eax,%ecx,8),%xmm1",},
{{0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x00, }, 6, 0, "", "",
"f3 0f 3a f0 c0 00 \threset $0x0",},
{{0x0f, 0x01, 0xe8, }, 3, 0, "", "",
"0f 01 e8 \tserialize ",},
{{0xf2, 0x0f, 0x01, 0xe9, }, 4, 0, "", "",
"f2 0f 01 e9 \txresldtrk ",},
{{0xf2, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",
"f2 0f 01 e8 \txsusldtrk ",},
{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",
"0f 01 cf \tencls ",},
{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",
"0f 01 d7 \tenclu ",},
{{0x0f, 0x01, 0xc0, }, 3, 0, "", "",
"0f 01 c0 \tenclv ",},
{{0x0f, 0x01, 0xc5, }, 3, 0, "", "",
"0f 01 c5 \tpconfig ",},
{{0xf3, 0x0f, 0x09, }, 3, 0, "", "",
"f3 0f 09 \twbnoinvd ",},
| linux-master | tools/perf/arch/x86/tests/insn-x86-dat-32.c |
// SPDX-License-Identifier: GPL-2.0
/*
* x86 instruction nmemonic table to parse disasm lines for annotate.
* This table is searched twice - one for exact match and another for
* match without a size suffix (b, w, l, q) in case of AT&T syntax.
*
* So this table should not have entries with the suffix unless it's
* a complete different instruction than ones without the suffix.
*/
static struct ins x86__instructions[] = {
{ .name = "adc", .ops = &mov_ops, },
{ .name = "add", .ops = &mov_ops, },
{ .name = "addsd", .ops = &mov_ops, },
{ .name = "and", .ops = &mov_ops, },
{ .name = "andpd", .ops = &mov_ops, },
{ .name = "andps", .ops = &mov_ops, },
{ .name = "bsr", .ops = &mov_ops, },
{ .name = "bt", .ops = &mov_ops, },
{ .name = "btr", .ops = &mov_ops, },
{ .name = "bts", .ops = &mov_ops, },
{ .name = "call", .ops = &call_ops, },
{ .name = "cmovbe", .ops = &mov_ops, },
{ .name = "cmove", .ops = &mov_ops, },
{ .name = "cmovae", .ops = &mov_ops, },
{ .name = "cmp", .ops = &mov_ops, },
{ .name = "cmpxch", .ops = &mov_ops, },
{ .name = "cmpxchg", .ops = &mov_ops, },
{ .name = "cs", .ops = &mov_ops, },
{ .name = "dec", .ops = &dec_ops, },
{ .name = "divsd", .ops = &mov_ops, },
{ .name = "divss", .ops = &mov_ops, },
{ .name = "gs", .ops = &mov_ops, },
{ .name = "imul", .ops = &mov_ops, },
{ .name = "inc", .ops = &dec_ops, },
{ .name = "ja", .ops = &jump_ops, },
{ .name = "jae", .ops = &jump_ops, },
{ .name = "jb", .ops = &jump_ops, },
{ .name = "jbe", .ops = &jump_ops, },
{ .name = "jc", .ops = &jump_ops, },
{ .name = "jcxz", .ops = &jump_ops, },
{ .name = "je", .ops = &jump_ops, },
{ .name = "jecxz", .ops = &jump_ops, },
{ .name = "jg", .ops = &jump_ops, },
{ .name = "jge", .ops = &jump_ops, },
{ .name = "jl", .ops = &jump_ops, },
{ .name = "jle", .ops = &jump_ops, },
{ .name = "jmp", .ops = &jump_ops, },
{ .name = "jna", .ops = &jump_ops, },
{ .name = "jnae", .ops = &jump_ops, },
{ .name = "jnb", .ops = &jump_ops, },
{ .name = "jnbe", .ops = &jump_ops, },
{ .name = "jnc", .ops = &jump_ops, },
{ .name = "jne", .ops = &jump_ops, },
{ .name = "jng", .ops = &jump_ops, },
{ .name = "jnge", .ops = &jump_ops, },
{ .name = "jnl", .ops = &jump_ops, },
{ .name = "jnle", .ops = &jump_ops, },
{ .name = "jno", .ops = &jump_ops, },
{ .name = "jnp", .ops = &jump_ops, },
{ .name = "jns", .ops = &jump_ops, },
{ .name = "jnz", .ops = &jump_ops, },
{ .name = "jo", .ops = &jump_ops, },
{ .name = "jp", .ops = &jump_ops, },
{ .name = "jpe", .ops = &jump_ops, },
{ .name = "jpo", .ops = &jump_ops, },
{ .name = "jrcxz", .ops = &jump_ops, },
{ .name = "js", .ops = &jump_ops, },
{ .name = "jz", .ops = &jump_ops, },
{ .name = "lea", .ops = &mov_ops, },
{ .name = "lock", .ops = &lock_ops, },
{ .name = "mov", .ops = &mov_ops, },
{ .name = "movapd", .ops = &mov_ops, },
{ .name = "movaps", .ops = &mov_ops, },
{ .name = "movdqa", .ops = &mov_ops, },
{ .name = "movdqu", .ops = &mov_ops, },
{ .name = "movsd", .ops = &mov_ops, },
{ .name = "movslq", .ops = &mov_ops, },
{ .name = "movss", .ops = &mov_ops, },
{ .name = "movupd", .ops = &mov_ops, },
{ .name = "movups", .ops = &mov_ops, },
{ .name = "movzbl", .ops = &mov_ops, },
{ .name = "movzwl", .ops = &mov_ops, },
{ .name = "mulsd", .ops = &mov_ops, },
{ .name = "mulss", .ops = &mov_ops, },
{ .name = "nop", .ops = &nop_ops, },
{ .name = "or", .ops = &mov_ops, },
{ .name = "orps", .ops = &mov_ops, },
{ .name = "pand", .ops = &mov_ops, },
{ .name = "paddq", .ops = &mov_ops, },
{ .name = "pcmpeqb", .ops = &mov_ops, },
{ .name = "por", .ops = &mov_ops, },
{ .name = "rcl", .ops = &mov_ops, },
{ .name = "ret", .ops = &ret_ops, },
{ .name = "sbb", .ops = &mov_ops, },
{ .name = "sete", .ops = &mov_ops, },
{ .name = "sub", .ops = &mov_ops, },
{ .name = "subsd", .ops = &mov_ops, },
{ .name = "test", .ops = &mov_ops, },
{ .name = "tzcnt", .ops = &mov_ops, },
{ .name = "ucomisd", .ops = &mov_ops, },
{ .name = "ucomiss", .ops = &mov_ops, },
{ .name = "vaddsd", .ops = &mov_ops, },
{ .name = "vandpd", .ops = &mov_ops, },
{ .name = "vmovdqa", .ops = &mov_ops, },
{ .name = "vmovq", .ops = &mov_ops, },
{ .name = "vmovsd", .ops = &mov_ops, },
{ .name = "vmulsd", .ops = &mov_ops, },
{ .name = "vorpd", .ops = &mov_ops, },
{ .name = "vsubsd", .ops = &mov_ops, },
{ .name = "vucomisd", .ops = &mov_ops, },
{ .name = "xadd", .ops = &mov_ops, },
{ .name = "xbegin", .ops = &jump_ops, },
{ .name = "xchg", .ops = &mov_ops, },
{ .name = "xor", .ops = &mov_ops, },
{ .name = "xorpd", .ops = &mov_ops, },
{ .name = "xorps", .ops = &mov_ops, },
};
static bool amd__ins_is_fused(struct arch *arch, const char *ins1,
const char *ins2)
{
if (strstr(ins2, "jmp"))
return false;
/* Family >= 15h supports cmp/test + branch fusion */
if (arch->family >= 0x15 && (strstarts(ins1, "test") ||
(strstarts(ins1, "cmp") && !strstr(ins1, "xchg")))) {
return true;
}
/* Family >= 19h supports some ALU + branch fusion */
if (arch->family >= 0x19 && (strstarts(ins1, "add") ||
strstarts(ins1, "sub") || strstarts(ins1, "and") ||
strstarts(ins1, "inc") || strstarts(ins1, "dec") ||
strstarts(ins1, "or") || strstarts(ins1, "xor"))) {
return true;
}
return false;
}
static bool intel__ins_is_fused(struct arch *arch, const char *ins1,
const char *ins2)
{
if (arch->family != 6 || arch->model < 0x1e || strstr(ins2, "jmp"))
return false;
if (arch->model == 0x1e) {
/* Nehalem */
if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) ||
strstr(ins1, "test")) {
return true;
}
} else {
/* Newer platform */
if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) ||
strstr(ins1, "test") ||
strstr(ins1, "add") ||
strstr(ins1, "sub") ||
strstr(ins1, "and") ||
strstr(ins1, "inc") ||
strstr(ins1, "dec")) {
return true;
}
}
return false;
}
static int x86__cpuid_parse(struct arch *arch, char *cpuid)
{
unsigned int family, model, stepping;
int ret;
/*
* cpuid = "GenuineIntel,family,model,stepping"
*/
ret = sscanf(cpuid, "%*[^,],%u,%u,%u", &family, &model, &stepping);
if (ret == 3) {
arch->family = family;
arch->model = model;
arch->ins_is_fused = strstarts(cpuid, "AuthenticAMD") ?
amd__ins_is_fused :
intel__ins_is_fused;
return 0;
}
return -1;
}
static int x86__annotate_init(struct arch *arch, char *cpuid)
{
int err = 0;
if (arch->initialized)
return 0;
if (cpuid) {
if (x86__cpuid_parse(arch, cpuid))
err = SYMBOL_ANNOTATE_ERRNO__ARCH_INIT_CPUID_PARSING;
}
arch->initialized = true;
return err;
}
| linux-master | tools/perf/arch/x86/annotate/instructions.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright(C) 2015 Linaro Limited. All rights reserved.
* Author: Mathieu Poirier <[email protected]>
*/
#include <dirent.h>
#include <stdbool.h>
#include <linux/coresight-pmu.h>
#include <linux/zalloc.h>
#include <api/fs/fs.h>
#include "../../../util/auxtrace.h"
#include "../../../util/debug.h"
#include "../../../util/evlist.h"
#include "../../../util/pmu.h"
#include "../../../util/pmus.h"
#include "cs-etm.h"
#include "arm-spe.h"
#include "hisi-ptt.h"
static struct perf_pmu **find_all_arm_spe_pmus(int *nr_spes, int *err)
{
struct perf_pmu **arm_spe_pmus = NULL;
int ret, i, nr_cpus = sysconf(_SC_NPROCESSORS_CONF);
/* arm_spe_xxxxxxxxx\0 */
char arm_spe_pmu_name[sizeof(ARM_SPE_PMU_NAME) + 10];
arm_spe_pmus = zalloc(sizeof(struct perf_pmu *) * nr_cpus);
if (!arm_spe_pmus) {
pr_err("spes alloc failed\n");
*err = -ENOMEM;
return NULL;
}
for (i = 0; i < nr_cpus; i++) {
ret = sprintf(arm_spe_pmu_name, "%s%d", ARM_SPE_PMU_NAME, i);
if (ret < 0) {
pr_err("sprintf failed\n");
*err = -ENOMEM;
return NULL;
}
arm_spe_pmus[*nr_spes] = perf_pmus__find(arm_spe_pmu_name);
if (arm_spe_pmus[*nr_spes]) {
pr_debug2("%s %d: arm_spe_pmu %d type %d name %s\n",
__func__, __LINE__, *nr_spes,
arm_spe_pmus[*nr_spes]->type,
arm_spe_pmus[*nr_spes]->name);
(*nr_spes)++;
}
}
return arm_spe_pmus;
}
static struct perf_pmu **find_all_hisi_ptt_pmus(int *nr_ptts, int *err)
{
struct perf_pmu **hisi_ptt_pmus = NULL;
struct dirent *dent;
char path[PATH_MAX];
DIR *dir = NULL;
int idx = 0;
perf_pmu__event_source_devices_scnprintf(path, sizeof(path));
dir = opendir(path);
if (!dir) {
pr_err("can't read directory '%s'\n", path);
*err = -EINVAL;
return NULL;
}
while ((dent = readdir(dir))) {
if (strstr(dent->d_name, HISI_PTT_PMU_NAME))
(*nr_ptts)++;
}
if (!(*nr_ptts))
goto out;
hisi_ptt_pmus = zalloc(sizeof(struct perf_pmu *) * (*nr_ptts));
if (!hisi_ptt_pmus) {
pr_err("hisi_ptt alloc failed\n");
*err = -ENOMEM;
goto out;
}
rewinddir(dir);
while ((dent = readdir(dir))) {
if (strstr(dent->d_name, HISI_PTT_PMU_NAME) && idx < *nr_ptts) {
hisi_ptt_pmus[idx] = perf_pmus__find(dent->d_name);
if (hisi_ptt_pmus[idx])
idx++;
}
}
out:
closedir(dir);
return hisi_ptt_pmus;
}
static struct perf_pmu *find_pmu_for_event(struct perf_pmu **pmus,
int pmu_nr, struct evsel *evsel)
{
int i;
if (!pmus)
return NULL;
for (i = 0; i < pmu_nr; i++) {
if (evsel->core.attr.type == pmus[i]->type)
return pmus[i];
}
return NULL;
}
struct auxtrace_record
*auxtrace_record__init(struct evlist *evlist, int *err)
{
struct perf_pmu *cs_etm_pmu = NULL;
struct perf_pmu **arm_spe_pmus = NULL;
struct perf_pmu **hisi_ptt_pmus = NULL;
struct evsel *evsel;
struct perf_pmu *found_etm = NULL;
struct perf_pmu *found_spe = NULL;
struct perf_pmu *found_ptt = NULL;
int auxtrace_event_cnt = 0;
int nr_spes = 0;
int nr_ptts = 0;
if (!evlist)
return NULL;
cs_etm_pmu = perf_pmus__find(CORESIGHT_ETM_PMU_NAME);
arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err);
hisi_ptt_pmus = find_all_hisi_ptt_pmus(&nr_ptts, err);
evlist__for_each_entry(evlist, evsel) {
if (cs_etm_pmu && !found_etm)
found_etm = find_pmu_for_event(&cs_etm_pmu, 1, evsel);
if (arm_spe_pmus && !found_spe)
found_spe = find_pmu_for_event(arm_spe_pmus, nr_spes, evsel);
if (hisi_ptt_pmus && !found_ptt)
found_ptt = find_pmu_for_event(hisi_ptt_pmus, nr_ptts, evsel);
}
free(arm_spe_pmus);
free(hisi_ptt_pmus);
if (found_etm)
auxtrace_event_cnt++;
if (found_spe)
auxtrace_event_cnt++;
if (found_ptt)
auxtrace_event_cnt++;
if (auxtrace_event_cnt > 1) {
pr_err("Concurrent AUX trace operation not currently supported\n");
*err = -EOPNOTSUPP;
return NULL;
}
if (found_etm)
return cs_etm_record_init(err);
#if defined(__aarch64__)
if (found_spe)
return arm_spe_recording_init(err, found_spe);
if (found_ptt)
return hisi_ptt_recording_init(err, found_ptt);
#endif
/*
* Clear 'err' even if we haven't found an event - that way perf
* record can still be used even if tracers aren't present. The NULL
* return value will take care of telling the infrastructure HW tracing
* isn't available.
*/
*err = 0;
return NULL;
}
#if defined(__arm__)
u64 compat_auxtrace_mmap__read_head(struct auxtrace_mmap *mm)
{
struct perf_event_mmap_page *pc = mm->userpg;
u64 result;
__asm__ __volatile__(
" ldrd %0, %H0, [%1]"
: "=&r" (result)
: "r" (&pc->aux_head), "Qo" (pc->aux_head)
);
return result;
}
int compat_auxtrace_mmap__write_tail(struct auxtrace_mmap *mm, u64 tail)
{
struct perf_event_mmap_page *pc = mm->userpg;
/* Ensure all reads are done before we write the tail out */
smp_mb();
__asm__ __volatile__(
" strd %2, %H2, [%1]"
: "=Qo" (pc->aux_tail)
: "r" (&pc->aux_tail), "r" (tail)
);
return 0;
}
#endif
| linux-master | tools/perf/arch/arm/util/auxtrace.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright(C) 2015 Linaro Limited. All rights reserved.
* Author: Mathieu Poirier <[email protected]>
*/
#include <string.h>
#include <linux/coresight-pmu.h>
#include <linux/perf_event.h>
#include <linux/string.h>
#include "arm-spe.h"
#include "hisi-ptt.h"
#include "../../../util/pmu.h"
#include "../../../util/cs-etm.h"
struct perf_event_attr
*perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused)
{
#ifdef HAVE_AUXTRACE_SUPPORT
if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) {
/* add ETM default config here */
pmu->selectable = true;
return cs_etm_get_default_config(pmu);
#if defined(__aarch64__)
} else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) {
return arm_spe_pmu_default_config(pmu);
} else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) {
pmu->selectable = true;
#endif
}
#endif
return NULL;
}
| linux-master | tools/perf/arch/arm/util/pmu.c |
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