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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* arch/arm/mach-at91/pm.c
* AT91 Power Management
*
* Copyright (C) 2005 David Brownell
*/
#include <linux/genalloc.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/parser.h>
#include <linux/suspend.h>
#include <linux/clk.h>
#include <linux/clk/at91_pmc.h>
#include <linux/platform_data/atmel.h>
#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/system_misc.h>
#include <asm/suspend.h>
#include "generic.h"
#include "pm.h"
#include "sam_secure.h"
#define BACKUP_DDR_PHY_CALIBRATION (9)
/**
* struct at91_pm_bu - AT91 power management backup unit data structure
* @suspended: true if suspended to backup mode
* @reserved: reserved
* @canary: canary data for memory checking after exit from backup mode
* @resume: resume API
* @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
* of the memory
*/
struct at91_pm_bu {
int suspended;
unsigned long reserved;
phys_addr_t canary;
phys_addr_t resume;
unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
};
/**
* struct at91_pm_sfrbu_regs - registers mapping for SFRBU
* @pswbu: power switch BU control registers
*/
struct at91_pm_sfrbu_regs {
struct {
u32 key;
u32 ctrl;
u32 state;
u32 softsw;
} pswbu;
};
/**
* enum at91_pm_eth_clk - Ethernet clock indexes
* @AT91_PM_ETH_PCLK: pclk index
* @AT91_PM_ETH_HCLK: hclk index
* @AT91_PM_ETH_MAX_CLK: max index
*/
enum at91_pm_eth_clk {
AT91_PM_ETH_PCLK,
AT91_PM_ETH_HCLK,
AT91_PM_ETH_MAX_CLK,
};
/**
* enum at91_pm_eth - Ethernet controller indexes
* @AT91_PM_G_ETH: gigabit Ethernet controller index
* @AT91_PM_E_ETH: megabit Ethernet controller index
* @AT91_PM_MAX_ETH: max index
*/
enum at91_pm_eth {
AT91_PM_G_ETH,
AT91_PM_E_ETH,
AT91_PM_MAX_ETH,
};
/**
* struct at91_pm_quirk_eth - AT91 PM Ethernet quirks
* @dev: Ethernet device
* @np: Ethernet device node
* @clks: Ethernet clocks
* @modes: power management mode that this quirk applies to
* @dns_modes: do not suspend modes: stop suspending if Ethernet is configured
* as wakeup source but buggy and no other wakeup source is
* available
*/
struct at91_pm_quirk_eth {
struct device *dev;
struct device_node *np;
struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK];
u32 modes;
u32 dns_modes;
};
/**
* struct at91_pm_quirks - AT91 PM quirks
* @eth: Ethernet quirks
*/
struct at91_pm_quirks {
struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH];
};
/**
* struct at91_soc_pm - AT91 SoC power management data structure
* @config_shdwc_ws: wakeup sources configuration function for SHDWC
* @config_pmc_ws: wakeup srouces configuration function for PMC
* @ws_ids: wakup sources of_device_id array
* @bu: backup unit mapped data (for backup mode)
* @quirks: PM quirks
* @data: PM data to be used on last phase of suspend
* @sfrbu_regs: SFRBU registers mapping
* @memcs: memory chip select
*/
struct at91_soc_pm {
int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
const struct of_device_id *ws_ids;
struct at91_pm_bu *bu;
struct at91_pm_quirks quirks;
struct at91_pm_data data;
struct at91_pm_sfrbu_regs sfrbu_regs;
void *memcs;
};
/**
* enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes
* @AT91_PM_IOMAP_SHDWC: SHDWC controller
* @AT91_PM_IOMAP_SFRBU: SFRBU controller
* @AT91_PM_IOMAP_ETHC: Ethernet controller
*/
enum at91_pm_iomaps {
AT91_PM_IOMAP_SHDWC,
AT91_PM_IOMAP_SFRBU,
AT91_PM_IOMAP_ETHC,
};
#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
static struct at91_soc_pm soc_pm = {
.data = {
.standby_mode = AT91_PM_STANDBY,
.suspend_mode = AT91_PM_ULP0,
},
};
static const match_table_t pm_modes __initconst = {
{ AT91_PM_STANDBY, "standby" },
{ AT91_PM_ULP0, "ulp0" },
{ AT91_PM_ULP0_FAST, "ulp0-fast" },
{ AT91_PM_ULP1, "ulp1" },
{ AT91_PM_BACKUP, "backup" },
{ -1, NULL },
};
#define at91_ramc_read(id, field) \
__raw_readl(soc_pm.data.ramc[id] + field)
#define at91_ramc_write(id, field, value) \
__raw_writel(value, soc_pm.data.ramc[id] + field)
static int at91_pm_valid_state(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_ON:
case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM:
return 1;
default:
return 0;
}
}
static int canary = 0xA5A5A5A5;
struct wakeup_source_info {
unsigned int pmc_fsmr_bit;
unsigned int shdwc_mr_bit;
bool set_polarity;
};
static const struct wakeup_source_info ws_info[] = {
{ .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
{ .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
{ .pmc_fsmr_bit = AT91_PMC_USBAL },
{ .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
{ .pmc_fsmr_bit = AT91_PMC_RTTAL },
{ .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
};
static const struct of_device_id sama5d2_ws_ids[] = {
{ .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
{ .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
{ /* sentinel */ }
};
static const struct of_device_id sam9x60_ws_ids[] = {
{ .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
{ .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
{ /* sentinel */ }
};
static const struct of_device_id sama7g5_ws_ids[] = {
{ .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
{ .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
{ /* sentinel */ }
};
static int at91_pm_config_ws(unsigned int pm_mode, bool set)
{
const struct wakeup_source_info *wsi;
const struct of_device_id *match;
struct platform_device *pdev;
struct device_node *np;
unsigned int mode = 0, polarity = 0, val = 0;
if (pm_mode != AT91_PM_ULP1)
return 0;
if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
return -EPERM;
if (!set) {
writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
return 0;
}
if (soc_pm.config_shdwc_ws)
soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
/* SHDWC.MR */
val = readl(soc_pm.data.shdwc + 0x04);
/* Loop through defined wakeup sources. */
for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
pdev = of_find_device_by_node(np);
if (!pdev)
continue;
if (device_may_wakeup(&pdev->dev)) {
wsi = match->data;
/* Check if enabled on SHDWC. */
if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
goto put_device;
mode |= wsi->pmc_fsmr_bit;
if (wsi->set_polarity)
polarity |= wsi->pmc_fsmr_bit;
}
put_device:
put_device(&pdev->dev);
}
if (mode) {
if (soc_pm.config_pmc_ws)
soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
} else {
pr_err("AT91: PM: no ULP1 wakeup sources found!");
}
return mode ? 0 : -EPERM;
}
static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
u32 *polarity)
{
u32 val;
/* SHDWC.WUIR */
val = readl(shdwc + 0x0c);
*mode |= (val & 0x3ff);
*polarity |= ((val >> 16) & 0x3ff);
return 0;
}
static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
{
writel(mode, pmc + AT91_PMC_FSMR);
writel(polarity, pmc + AT91_PMC_FSPR);
return 0;
}
static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
{
writel(mode, pmc + AT91_PMC_FSMR);
return 0;
}
static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth)
{
struct platform_device *pdev;
/* Interface NA in DT. */
if (!eth->np)
return false;
/* No quirks for this interface and current suspend mode. */
if (!(eth->modes & BIT(soc_pm.data.mode)))
return false;
if (!eth->dev) {
/* Driver not probed. */
pdev = of_find_device_by_node(eth->np);
if (!pdev)
return false;
/* put_device(eth->dev) is called at the end of suspend. */
eth->dev = &pdev->dev;
}
/* No quirks if device isn't a wakeup source. */
if (!device_may_wakeup(eth->dev))
return false;
return true;
}
static int at91_pm_config_quirks(bool suspend)
{
struct at91_pm_quirk_eth *eth;
int i, j, ret, tmp;
/*
* Ethernet IPs who's device_node pointers are stored into
* soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
* or both due to a hardware bug. If they receive WoL packets while in
* ULP0 or ULP1 IPs could stop working or the whole system could stop
* working. We cannot handle this scenario in the ethernet driver itself
* as the driver is common to multiple vendors and also we only know
* here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle
* these scenarios here, as quirks.
*/
for (i = 0; i < AT91_PM_MAX_ETH; i++) {
eth = &soc_pm.quirks.eth[i];
if (!at91_pm_eth_quirk_is_valid(eth))
continue;
/*
* For modes in dns_modes mask the system blocks if quirk is not
* applied but if applied the interface doesn't act at WoL
* events. Thus take care to avoid suspending if this interface
* is the only configured wakeup source.
*/
if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
int ws_count = 0;
#ifdef CONFIG_PM_SLEEP
struct wakeup_source *ws;
for_each_wakeup_source(ws) {
if (ws->dev == eth->dev)
continue;
ws_count++;
break;
}
#endif
/*
* Checking !ws is good for all platforms with issues
* even when both G_ETH and E_ETH are available as dns_modes
* is populated only on G_ETH interface.
*/
if (!ws_count) {
pr_err("AT91: PM: Ethernet cannot resume from WoL!");
ret = -EPERM;
put_device(eth->dev);
eth->dev = NULL;
/* No need to revert clock settings for this eth. */
i--;
goto clk_unconfigure;
}
}
if (suspend) {
clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks);
} else {
ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK,
eth->clks);
if (ret)
goto clk_unconfigure;
/*
* Release the reference to eth->dev taken in
* at91_pm_eth_quirk_is_valid().
*/
put_device(eth->dev);
eth->dev = NULL;
}
}
return 0;
clk_unconfigure:
/*
* In case of resume we reach this point if clk_prepare_enable() failed.
* we don't want to revert the previous clk_prepare_enable() for the
* other IP.
*/
for (j = i; j >= 0; j--) {
eth = &soc_pm.quirks.eth[j];
if (suspend) {
if (!at91_pm_eth_quirk_is_valid(eth))
continue;
tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks);
if (tmp) {
pr_err("AT91: PM: failed to enable %s clocks\n",
j == AT91_PM_G_ETH ? "geth" : "eth");
}
}
/*
* Release the reference to eth->dev taken in
* at91_pm_eth_quirk_is_valid().
*/
put_device(eth->dev);
eth->dev = NULL;
}
return ret;
}
/*
* Called after processes are frozen, but before we shutdown devices.
*/
static int at91_pm_begin(suspend_state_t state)
{
int ret;
switch (state) {
case PM_SUSPEND_MEM:
soc_pm.data.mode = soc_pm.data.suspend_mode;
break;
case PM_SUSPEND_STANDBY:
soc_pm.data.mode = soc_pm.data.standby_mode;
break;
default:
soc_pm.data.mode = -1;
}
ret = at91_pm_config_ws(soc_pm.data.mode, true);
if (ret)
return ret;
if (soc_pm.data.mode == AT91_PM_BACKUP)
soc_pm.bu->suspended = 1;
else if (soc_pm.bu)
soc_pm.bu->suspended = 0;
return 0;
}
/*
* Verify that all the clocks are correct before entering
* slow-clock mode.
*/
static int at91_pm_verify_clocks(void)
{
unsigned long scsr;
int i;
scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
/* USB must not be using PLLB */
if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
return 0;
}
/* PCK0..PCK3 must be disabled, or configured to use clk32k */
for (i = 0; i < 4; i++) {
u32 css;
if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
continue;
css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
if (css != AT91_PMC_CSS_SLOW) {
pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
return 0;
}
}
return 1;
}
/*
* Call this from platform driver suspend() to see how deeply to suspend.
* For example, some controllers (like OHCI) need one of the PLL clocks
* in order to act as a wakeup source, and those are not available when
* going into slow clock mode.
*
* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
* the very same problem (but not using at91 main_clk), and it'd be better
* to add one generic API rather than lots of platform-specific ones.
*/
int at91_suspend_entering_slow_clock(void)
{
return (soc_pm.data.mode >= AT91_PM_ULP0);
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
extern u32 at91_pm_suspend_in_sram_sz;
static int at91_suspend_finish(unsigned long val)
{
unsigned char modified_gray_code[] = {
0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
0x10, 0x11,
};
unsigned int tmp, index;
int i;
if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
/*
* Bootloader will perform DDR recalibration and will try to
* restore the ZQ0SR0 with the value saved here. But the
* calibration is buggy and restoring some values from ZQ0SR0
* is forbidden and risky thus we need to provide processed
* values for these (modified gray code values).
*/
tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
/* Store pull-down output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
/* Store pull-up output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
/* Store pull-down on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
/* Store pull-up on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
/*
* The 1st 8 words of memory might get corrupted in the process
* of DDR PHY recalibration; it is saved here in securam and it
* will be restored later, after recalibration, by bootloader
*/
for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
soc_pm.bu->ddr_phy_calibration[i] =
*((unsigned int *)soc_pm.memcs + (i - 1));
}
flush_cache_all();
outer_disable();
at91_suspend_sram_fn(&soc_pm.data);
return 0;
}
static void at91_pm_switch_ba_to_vbat(void)
{
unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
unsigned int val;
/* Just for safety. */
if (!soc_pm.data.sfrbu)
return;
val = readl(soc_pm.data.sfrbu + offset);
/* Already on VBAT. */
if (!(val & soc_pm.sfrbu_regs.pswbu.state))
return;
val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
writel(val, soc_pm.data.sfrbu + offset);
/* Wait for update. */
val = readl(soc_pm.data.sfrbu + offset);
while (val & soc_pm.sfrbu_regs.pswbu.state)
val = readl(soc_pm.data.sfrbu + offset);
}
static void at91_pm_suspend(suspend_state_t state)
{
if (soc_pm.data.mode == AT91_PM_BACKUP) {
at91_pm_switch_ba_to_vbat();
cpu_suspend(0, at91_suspend_finish);
/* The SRAM is lost between suspend cycles */
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
&at91_pm_suspend_in_sram,
at91_pm_suspend_in_sram_sz);
} else {
at91_suspend_finish(0);
}
outer_resume();
}
/*
* STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
* event sources; and reduces DRAM power. But otherwise it's identical to
* PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
*
* AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
* suspend more deeply, the master clock switches to the clk32k and turns off
* the main oscillator
*
* AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
*/
static int at91_pm_enter(suspend_state_t state)
{
int ret;
ret = at91_pm_config_quirks(true);
if (ret)
return ret;
switch (state) {
case PM_SUSPEND_MEM:
case PM_SUSPEND_STANDBY:
/*
* Ensure that clocks are in a valid state.
*/
if (soc_pm.data.mode >= AT91_PM_ULP0 &&
!at91_pm_verify_clocks())
goto error;
at91_pm_suspend(state);
break;
case PM_SUSPEND_ON:
cpu_do_idle();
break;
default:
pr_debug("AT91: PM - bogus suspend state %d\n", state);
goto error;
}
error:
at91_pm_config_quirks(false);
return 0;
}
/*
* Called right prior to thawing processes.
*/
static void at91_pm_end(void)
{
at91_pm_config_ws(soc_pm.data.mode, false);
}
static const struct platform_suspend_ops at91_pm_ops = {
.valid = at91_pm_valid_state,
.begin = at91_pm_begin,
.enter = at91_pm_enter,
.end = at91_pm_end,
};
static struct platform_device at91_cpuidle_device = {
.name = "cpuidle-at91",
};
/*
* The AT91RM9200 goes into self-refresh mode with this command, and will
* terminate self-refresh automatically on the next SDRAM access.
*
* Self-refresh mode is exited as soon as a memory access is made, but we don't
* know for sure when that happens. However, we need to restore the low-power
* mode if it was enabled before going idle. Restoring low-power mode while
* still in self-refresh is "not recommended", but seems to work.
*/
static void at91rm9200_standby(void)
{
asm volatile(
"b 1f\n\t"
".align 5\n\t"
"1: mcr p15, 0, %0, c7, c10, 4\n\t"
" str %2, [%1, %3]\n\t"
" mcr p15, 0, %0, c7, c0, 4\n\t"
:
: "r" (0), "r" (soc_pm.data.ramc[0]),
"r" (1), "r" (AT91_MC_SDRAMC_SRR));
}
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
static void at91_ddr_standby(void)
{
/* Those two values allow us to delay self-refresh activation
* to the maximum. */
u32 lpr0, lpr1 = 0;
u32 mdr, saved_mdr0, saved_mdr1 = 0;
u32 saved_lpr0, saved_lpr1 = 0;
/* LPDDR1 --> force DDR2 mode during self-refresh */
saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
mdr |= AT91_DDRSDRC_MD_DDR2;
at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
}
if (soc_pm.data.ramc[1]) {
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
mdr |= AT91_DDRSDRC_MD_DDR2;
at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
}
}
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
/* self-refresh mode now */
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
if (soc_pm.data.ramc[1])
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
cpu_do_idle();
at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
if (soc_pm.data.ramc[1]) {
at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}
}
static void sama5d3_ddr_standby(void)
{
u32 lpr0;
u32 saved_lpr0;
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
cpu_do_idle();
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
}
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
static void at91sam9_sdram_standby(void)
{
u32 lpr0, lpr1 = 0;
u32 saved_lpr0, saved_lpr1 = 0;
if (soc_pm.data.ramc[1]) {
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
}
saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
/* self-refresh mode now */
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
if (soc_pm.data.ramc[1])
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
cpu_do_idle();
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
if (soc_pm.data.ramc[1])
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}
static void sama7g5_standby(void)
{
int pwrtmg, ratio;
pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
/*
* Place RAM into self-refresh after a maximum idle clocks. The maximum
* idle clocks is configured by bootloader in
* UDDRC_PWRMGT.SELFREF_TO_X32.
*/
writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
soc_pm.data.ramc[0] + UDDRC_PWRCTL);
/* Divide CPU clock by 16. */
writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
cpu_do_idle();
/* Restore previous configuration. */
writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
}
struct ramc_info {
void (*idle)(void);
unsigned int memctrl;
};
static const struct ramc_info ramc_infos[] __initconst = {
{ .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
{ .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
{ .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
{ .idle = sama7g5_standby, },
};
static const struct of_device_id ramc_ids[] __initconst = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
{ .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
{ /*sentinel*/ }
};
static const struct of_device_id ramc_phy_ids[] __initconst = {
{ .compatible = "microchip,sama7g5-ddr3phy", },
{ /* Sentinel. */ },
};
static __init int at91_dt_ramc(bool phy_mandatory)
{
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
void *standby = NULL;
const struct ramc_info *ramc;
int ret;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
soc_pm.data.ramc[idx] = of_iomap(np, 0);
if (!soc_pm.data.ramc[idx]) {
pr_err("unable to map ramc[%d] cpu registers\n", idx);
ret = -ENOMEM;
of_node_put(np);
goto unmap_ramc;
}
ramc = of_id->data;
if (ramc) {
if (!standby)
standby = ramc->idle;
soc_pm.data.memctrl = ramc->memctrl;
}
idx++;
}
if (!idx) {
pr_err("unable to find compatible ram controller node in dtb\n");
ret = -ENODEV;
goto unmap_ramc;
}
/* Lookup for DDR PHY node, if any. */
for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
soc_pm.data.ramc_phy = of_iomap(np, 0);
if (!soc_pm.data.ramc_phy) {
pr_err("unable to map ramc phy cpu registers\n");
ret = -ENOMEM;
of_node_put(np);
goto unmap_ramc;
}
}
if (phy_mandatory && !soc_pm.data.ramc_phy) {
pr_err("DDR PHY is mandatory!\n");
ret = -ENODEV;
goto unmap_ramc;
}
if (!standby) {
pr_warn("ramc no standby function available\n");
return 0;
}
at91_cpuidle_device.dev.platform_data = standby;
return 0;
unmap_ramc:
while (idx)
iounmap(soc_pm.data.ramc[--idx]);
return ret;
}
static void at91rm9200_idle(void)
{
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
}
static void at91sam9_idle(void)
{
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
cpu_do_idle();
}
static void __init at91_pm_sram_init(void)
{
struct gen_pool *sram_pool;
phys_addr_t sram_pbase;
unsigned long sram_base;
struct device_node *node;
struct platform_device *pdev = NULL;
for_each_compatible_node(node, NULL, "mmio-sram") {
pdev = of_find_device_by_node(node);
if (pdev) {
of_node_put(node);
break;
}
}
if (!pdev) {
pr_warn("%s: failed to find sram device!\n", __func__);
return;
}
sram_pool = gen_pool_get(&pdev->dev, NULL);
if (!sram_pool) {
pr_warn("%s: sram pool unavailable!\n", __func__);
goto out_put_device;
}
sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
if (!sram_base) {
pr_warn("%s: unable to alloc sram!\n", __func__);
goto out_put_device;
}
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
at91_pm_suspend_in_sram_sz, false);
if (!at91_suspend_sram_fn) {
pr_warn("SRAM: Could not map\n");
goto out_put_device;
}
/* Copy the pm suspend handler to SRAM */
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
return;
out_put_device:
put_device(&pdev->dev);
return;
}
static bool __init at91_is_pm_mode_active(int pm_mode)
{
return (soc_pm.data.standby_mode == pm_mode ||
soc_pm.data.suspend_mode == pm_mode);
}
static int __init at91_pm_backup_scan_memcs(unsigned long node,
const char *uname, int depth,
void *data)
{
const char *type;
const __be32 *reg;
int *located = data;
int size;
/* Memory node already located. */
if (*located)
return 0;
type = of_get_flat_dt_prop(node, "device_type", NULL);
/* We are scanning "memory" nodes only. */
if (!type || strcmp(type, "memory"))
return 0;
reg = of_get_flat_dt_prop(node, "reg", &size);
if (reg) {
soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
*located = 1;
}
return 0;
}
static int __init at91_pm_backup_init(void)
{
struct gen_pool *sram_pool;
struct device_node *np;
struct platform_device *pdev;
int ret = -ENODEV, located = 0;
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
!IS_ENABLED(CONFIG_SOC_SAMA7G5))
return -EPERM;
if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
return 0;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
if (!np)
return ret;
pdev = of_find_device_by_node(np);
of_node_put(np);
if (!pdev) {
pr_warn("%s: failed to find securam device!\n", __func__);
return ret;
}
sram_pool = gen_pool_get(&pdev->dev, NULL);
if (!sram_pool) {
pr_warn("%s: securam pool unavailable!\n", __func__);
goto securam_fail;
}
soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
if (!soc_pm.bu) {
pr_warn("%s: unable to alloc securam!\n", __func__);
ret = -ENOMEM;
goto securam_fail;
}
soc_pm.bu->suspended = 0;
soc_pm.bu->canary = __pa_symbol(&canary);
soc_pm.bu->resume = __pa_symbol(cpu_resume);
if (soc_pm.data.ramc_phy) {
of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
if (!located)
goto securam_fail;
}
return 0;
securam_fail:
put_device(&pdev->dev);
return ret;
}
static void __init at91_pm_secure_init(void)
{
int suspend_mode;
struct arm_smccc_res res;
suspend_mode = soc_pm.data.suspend_mode;
res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE,
suspend_mode, 0);
if (res.a0 == 0) {
pr_info("AT91: Secure PM: suspend mode set to %s\n",
pm_modes[suspend_mode].pattern);
return;
}
pr_warn("AT91: Secure PM: %s mode not supported !\n",
pm_modes[suspend_mode].pattern);
res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
if (res.a0 == 0) {
pr_warn("AT91: Secure PM: failed to get default mode\n");
return;
}
pr_info("AT91: Secure PM: using default suspend mode %s\n",
pm_modes[suspend_mode].pattern);
soc_pm.data.suspend_mode = res.a1;
}
static const struct of_device_id atmel_shdwc_ids[] = {
{ .compatible = "atmel,sama5d2-shdwc" },
{ .compatible = "microchip,sam9x60-shdwc" },
{ .compatible = "microchip,sama7g5-shdwc" },
{ /* sentinel. */ }
};
static const struct of_device_id gmac_ids[] __initconst = {
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d29-gem" },
{ .compatible = "microchip,sama7g5-gem" },
{ },
};
static const struct of_device_id emac_ids[] __initconst = {
{ .compatible = "atmel,sama5d3-macb" },
{ .compatible = "microchip,sama7g5-emac" },
{ },
};
/*
* Replaces _mode_to_replace with a supported mode that doesn't depend
* on controller pointed by _map_bitmask
* @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91
* PM mode
* @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on
* controller represented by _map_bitmask, _mode_to_replace needs to be
* updated
* @_mode_to_replace: standby_mode or suspend_mode that need to be
* updated
* @_mode_to_check: standby_mode or suspend_mode; this is needed here
* to avoid having standby_mode and suspend_mode set with the same AT91
* PM mode
*/
#define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \
_mode_to_check) \
do { \
if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \
int _mode_to_use, _mode_complementary; \
/* Use ULP0 if it doesn't need _map_bitmask. */ \
if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\
_mode_to_use = AT91_PM_ULP0; \
_mode_complementary = AT91_PM_STANDBY; \
} else { \
_mode_to_use = AT91_PM_STANDBY; \
_mode_complementary = AT91_PM_STANDBY; \
} \
\
if ((_mode_to_check) != _mode_to_use) \
(_mode_to_replace) = _mode_to_use; \
else \
(_mode_to_replace) = _mode_complementary;\
} \
} while (0)
/*
* Replaces standby and suspend modes with default supported modes:
* ULP0 and STANDBY.
* @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP()
* flags
* @_map: controller specific name; standby and suspend mode need to be
* replaced in order to not depend on this controller
*/
#define AT91_PM_REPLACE_MODES(_maps, _map) \
do { \
AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
(soc_pm.data.standby_mode), \
(soc_pm.data.suspend_mode)); \
AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\
(soc_pm.data.suspend_mode), \
(soc_pm.data.standby_mode)); \
} while (0)
static int __init at91_pm_get_eth_clks(struct device_node *np,
struct clk_bulk_data *clks)
{
clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk");
if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk))
return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk);
clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk");
if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk))
return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk);
return 0;
}
static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks)
{
return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) ||
IS_ERR(clks[AT91_PM_ETH_HCLK].clk);
}
static void __init at91_pm_modes_init(const u32 *maps, int len)
{
struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
struct device_node *np;
int ret;
ret = at91_pm_backup_init();
if (ret) {
if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
soc_pm.data.standby_mode = AT91_PM_ULP0;
if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
soc_pm.data.suspend_mode = AT91_PM_ULP0;
}
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
np = of_find_matching_node(NULL, atmel_shdwc_ids);
if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__);
AT91_PM_REPLACE_MODES(maps, SHDWC);
} else {
soc_pm.data.shdwc = of_iomap(np, 0);
of_node_put(np);
}
}
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
if (!np) {
pr_warn("%s: failed to find sfrbu!\n", __func__);
AT91_PM_REPLACE_MODES(maps, SFRBU);
} else {
soc_pm.data.sfrbu = of_iomap(np, 0);
of_node_put(np);
}
}
if ((at91_is_pm_mode_active(AT91_PM_ULP1) ||
at91_is_pm_mode_active(AT91_PM_ULP0) ||
at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) &&
(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
np = of_find_matching_node(NULL, gmac_ids);
if (!np) {
np = of_find_matching_node(NULL, emac_ids);
if (np)
goto get_emac_clks;
AT91_PM_REPLACE_MODES(maps, ETHC);
goto unmap_unused_nodes;
} else {
gmac->np = np;
at91_pm_get_eth_clks(np, gmac->clks);
}
np = of_find_matching_node(NULL, emac_ids);
if (!np) {
if (at91_pm_eth_clks_empty(gmac->clks))
AT91_PM_REPLACE_MODES(maps, ETHC);
} else {
get_emac_clks:
emac->np = np;
ret = at91_pm_get_eth_clks(np, emac->clks);
if (ret && at91_pm_eth_clks_empty(gmac->clks)) {
of_node_put(gmac->np);
of_node_put(emac->np);
gmac->np = NULL;
emac->np = NULL;
}
}
}
unmap_unused_nodes:
/* Unmap all unnecessary. */
if (soc_pm.data.shdwc &&
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
iounmap(soc_pm.data.shdwc);
soc_pm.data.shdwc = NULL;
}
if (soc_pm.data.sfrbu &&
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
iounmap(soc_pm.data.sfrbu);
soc_pm.data.sfrbu = NULL;
}
return;
}
struct pmc_info {
unsigned long uhp_udp_mask;
unsigned long mckr;
unsigned long version;
};
static const struct pmc_info pmc_infos[] __initconst = {
{
.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
.mckr = 0x30,
.version = AT91_PMC_V1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
.mckr = 0x30,
.version = AT91_PMC_V1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP,
.mckr = 0x30,
.version = AT91_PMC_V1,
},
{ .uhp_udp_mask = 0,
.mckr = 0x30,
.version = AT91_PMC_V1,
},
{
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
.mckr = 0x28,
.version = AT91_PMC_V2,
},
{
.mckr = 0x28,
.version = AT91_PMC_V2,
},
};
static const struct of_device_id atmel_pmc_ids[] __initconst = {
{ .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
{ .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
{ .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
{ .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
{ /* sentinel */ },
};
static void __init at91_pm_modes_validate(const int *modes, int len)
{
u8 i, standby = 0, suspend = 0;
int mode;
for (i = 0; i < len; i++) {
if (standby && suspend)
break;
if (modes[i] == soc_pm.data.standby_mode && !standby) {
standby = 1;
continue;
}
if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
suspend = 1;
continue;
}
}
if (!standby) {
if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
mode = AT91_PM_ULP0;
else
mode = AT91_PM_STANDBY;
pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
pm_modes[soc_pm.data.standby_mode].pattern,
pm_modes[mode].pattern);
soc_pm.data.standby_mode = mode;
}
if (!suspend) {
if (soc_pm.data.standby_mode == AT91_PM_ULP0)
mode = AT91_PM_STANDBY;
else
mode = AT91_PM_ULP0;
pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
pm_modes[soc_pm.data.suspend_mode].pattern,
pm_modes[mode].pattern);
soc_pm.data.suspend_mode = mode;
}
}
static void __init at91_pm_init(void (*pm_idle)(void))
{
struct device_node *pmc_np;
const struct of_device_id *of_id;
const struct pmc_info *pmc;
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
soc_pm.data.pmc = of_iomap(pmc_np, 0);
of_node_put(pmc_np);
if (!soc_pm.data.pmc) {
pr_err("AT91: PM not supported, PMC not found\n");
return;
}
pmc = of_id->data;
soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
soc_pm.data.pmc_mckr_offset = pmc->mckr;
soc_pm.data.pmc_version = pmc->version;
if (pm_idle)
arm_pm_idle = pm_idle;
at91_pm_sram_init();
if (at91_suspend_sram_fn) {
suspend_set_ops(&at91_pm_ops);
pr_info("AT91: PM: standby: %s, suspend: %s\n",
pm_modes[soc_pm.data.standby_mode].pattern,
pm_modes[soc_pm.data.suspend_mode].pattern);
} else {
pr_info("AT91: PM not supported, due to no SRAM allocated\n");
}
}
void __init at91rm9200_pm_init(void)
{
int ret;
if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
return;
/*
* Force STANDBY and ULP0 mode to avoid calling
* at91_pm_modes_validate() which may increase booting time.
* Platform supports anyway only STANDBY and ULP0 modes.
*/
soc_pm.data.standby_mode = AT91_PM_STANDBY;
soc_pm.data.suspend_mode = AT91_PM_ULP0;
ret = at91_dt_ramc(false);
if (ret)
return;
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
*/
at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
at91_pm_init(at91rm9200_idle);
}
void __init sam9x60_pm_init(void)
{
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
};
static const int iomaps[] __initconst = {
[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
ret = at91_dt_ramc(false);
if (ret)
return;
at91_pm_init(NULL);
soc_pm.ws_ids = sam9x60_ws_ids;
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
}
void __init at91sam9_pm_init(void)
{
int ret;
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
return;
/*
* Force STANDBY and ULP0 mode to avoid calling
* at91_pm_modes_validate() which may increase booting time.
* Platform supports anyway only STANDBY and ULP0 modes.
*/
soc_pm.data.standby_mode = AT91_PM_STANDBY;
soc_pm.data.suspend_mode = AT91_PM_ULP0;
ret = at91_dt_ramc(false);
if (ret)
return;
at91_pm_init(at91sam9_idle);
}
void __init sama5_pm_init(void)
{
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
};
static const u32 iomaps[] __initconst = {
[AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
[AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAMA5))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
ret = at91_dt_ramc(false);
if (ret)
return;
at91_pm_init(NULL);
/* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */
soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
BIT(AT91_PM_ULP0_FAST) |
BIT(AT91_PM_ULP1);
/* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */
soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
BIT(AT91_PM_ULP0_FAST);
}
void __init sama5d2_pm_init(void)
{
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
AT91_PM_BACKUP,
};
static const u32 iomaps[] __initconst = {
[AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC),
[AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC),
[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(ETHC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(SFRBU),
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
return;
if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) {
pr_warn("AT91: Secure PM: ignoring standby mode\n");
at91_pm_secure_init();
return;
}
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
ret = at91_dt_ramc(false);
if (ret)
return;
at91_pm_init(NULL);
soc_pm.ws_ids = sama5d2_ws_ids;
soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
soc_pm.sfrbu_regs.pswbu.state = BIT(3);
/* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */
soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
BIT(AT91_PM_ULP0_FAST) |
BIT(AT91_PM_ULP1);
/*
* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup
* source.
*/
soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
BIT(AT91_PM_ULP0_FAST);
}
void __init sama7_pm_init(void)
{
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
};
static const u32 iomaps[] __initconst = {
[AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
[AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC) |
AT91_PM_IOMAP(ETHC),
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
AT91_PM_IOMAP(SHDWC),
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAMA7))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
ret = at91_dt_ramc(true);
if (ret)
return;
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
at91_pm_init(NULL);
soc_pm.ws_ids = sama7g5_ws_ids;
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
soc_pm.sfrbu_regs.pswbu.state = BIT(2);
/* Quirks applies to ULP1 for both Ethernet interfaces. */
soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
}
static int __init at91_pm_modes_select(char *str)
{
char *s;
substring_t args[MAX_OPT_ARGS];
int standby, suspend;
if (!str)
return 0;
s = strsep(&str, ",");
standby = match_token(s, pm_modes, args);
if (standby < 0)
return 0;
suspend = match_token(str, pm_modes, args);
if (suspend < 0)
return 0;
soc_pm.data.standby_mode = standby;
soc_pm.data.suspend_mode = suspend;
return 0;
}
early_param("atmel.pm_modes", at91_pm_modes_select);
| linux-master | arch/arm/mach-at91/pm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Setup code for SAMA7
*
* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
*
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/system_misc.h>
#include "generic.h"
static void __init sama7_dt_device_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sama7_pm_init();
}
static const char *const sama7_dt_board_compat[] __initconst = {
"microchip,sama7",
NULL
};
DT_MACHINE_START(sama7_dt, "Microchip SAMA7")
/* Maintainer: Microchip */
.init_machine = sama7_dt_device_init,
.dt_compat = sama7_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-at91/sama7.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/stddef.h>
#include <linux/kbuild.h>
#include "pm.h"
int main(void)
{
DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc));
DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0]));
DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1]));
DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data,
ramc_phy));
DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl));
DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc));
DEFINE(PM_DATA_SFRBU, offsetof(struct at91_pm_data, sfrbu));
DEFINE(PM_DATA_PMC_MCKR_OFFSET, offsetof(struct at91_pm_data,
pmc_mckr_offset));
DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
pmc_version));
return 0;
}
| linux-master | arch/arm/mach-at91/pm_data-offsets.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Setup code for SAM9X60.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Claudiu Beznea <[email protected]>
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/system_misc.h>
#include "generic.h"
static void __init sam9x60_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam9x60_pm_init();
}
static const char *const sam9x60_dt_board_compat[] __initconst = {
"microchip,sam9x60",
NULL
};
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
/* Maintainer: Microchip */
.init_machine = sam9x60_init,
.dt_compat = sam9x60_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-at91/sam9x60.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Setup code for SAMv7x
*
* Copyright (C) 2013 Atmel,
* 2016 Andras Szemzo <[email protected]>
*/
#include <asm/mach/arch.h>
static const char *const samv7_dt_board_compat[] __initconst = {
"atmel,samv7",
NULL
};
DT_MACHINE_START(samv7_dt, "Atmel SAMV7")
.dt_compat = samv7_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-at91/samv7.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2022, Microchip
*/
#include <linux/arm-smccc.h>
#include <linux/of.h>
#include "sam_secure.h"
static bool optee_available;
#define SAM_SIP_SMC_STD_CALL_VAL(func_num) \
ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
ARM_SMCCC_OWNER_SIP, (func_num))
struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1)
{
struct arm_smccc_res res = {.a0 = -1};
if (WARN_ON(!optee_available))
return res;
arm_smccc_smc(SAM_SIP_SMC_STD_CALL_VAL(fn), arg0, arg1, 0, 0, 0, 0, 0,
&res);
return res;
}
bool sam_linux_is_optee_available(void)
{
/* If optee has been detected, then we are running in normal world */
return optee_available;
}
void __init sam_secure_init(void)
{
struct device_node *np;
/*
* We only check that the OP-TEE node is present and available. The
* OP-TEE kernel driver is not needed for the type of interaction made
* with OP-TEE here so the driver's status is not checked.
*/
np = of_find_node_by_path("/firmware/optee");
if (np && of_device_is_available(np))
optee_available = true;
of_node_put(np);
if (optee_available)
pr_info("Running under OP-TEE firmware\n");
}
| linux-master | arch/arm/mach-at91/sam_secure.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Setup code for AT91RM9200
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <[email protected]>
* 2012 Joachim Eastwood <[email protected]>
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
static void __init at91rm9200_dt_device_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
at91rm9200_pm_init();
}
static const char *const at91rm9200_dt_board_compat[] __initconst = {
"atmel,at91rm9200",
NULL
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
.init_machine = at91rm9200_dt_device_init,
.dt_compat = at91rm9200_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-at91/at91rm9200.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a73a4 processor support
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
*/
#include <linux/init.h>
#include <asm/mach/arch.h>
#include "common.h"
static const char *const r8a73a4_boards_compat_dt[] __initconst = {
"renesas,r8a73a4",
NULL
};
DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
.init_late = shmobile_init_late,
.dt_compat = r8a73a4_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-r8a73a4.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for R-Mobile / SH-Mobile - r8a7779 portion
*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Magnus Damm
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/soc/renesas/rcar-sysc.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "common.h"
#include "r8a7779.h"
#define HPBREG_BASE 0xfe700000
#define AVECR 0x0040 /* ARM Reset Vector Address Register */
#define R8A7779_SCU_BASE 0xf0000000
static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int ret = -EIO;
cpu = cpu_logical_map(cpu);
if (cpu)
ret = rcar_sysc_power_up_cpu(cpu);
return ret;
}
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
{
void __iomem *base = ioremap(HPBREG_BASE, 0x1000);
/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
writel(__pa(shmobile_boot_vector), base + AVECR);
/* setup r8a7779 specific SCU bits */
shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus);
iounmap(base);
}
#ifdef CONFIG_HOTPLUG_CPU
static int r8a7779_platform_cpu_kill(unsigned int cpu)
{
int ret = -EIO;
cpu = cpu_logical_map(cpu);
if (cpu)
ret = rcar_sysc_power_down_cpu(cpu);
return ret ? ret : 1;
}
static int r8a7779_cpu_kill(unsigned int cpu)
{
if (shmobile_smp_scu_cpu_kill(cpu))
return r8a7779_platform_cpu_kill(cpu);
return 0;
}
#endif /* CONFIG_HOTPLUG_CPU */
const struct smp_operations r8a7779_smp_ops __initconst = {
.smp_prepare_cpus = r8a7779_smp_prepare_cpus,
.smp_boot_secondary = r8a7779_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = shmobile_smp_scu_cpu_die,
.cpu_kill = r8a7779_cpu_kill,
#endif
};
| linux-master | arch/arm/mach-shmobile/smp-r8a7779.c |
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car Generation 2 da9063(L)/da9210 regulator quirk
*
* Certain Gen2 development boards have an da9063 and one or more da9210
* regulators. All of these regulators have their interrupt request lines
* tied to the same interrupt pin (IRQ2) on the SoC.
*
* After cold boot or da9063-induced restart, both the da9063 and da9210 seem
* to assert their interrupt request lines. Hence as soon as one driver
* requests this irq, it gets stuck in an interrupt storm, as it only manages
* to deassert its own interrupt request line, and the other driver hasn't
* installed an interrupt handler yet.
*
* To handle this, install a quirk that masks the interrupts in both the
* da9063 and da9210. This quirk has to run after the i2c master driver has
* been initialized, but before the i2c slave drivers are initialized.
*
* Copyright (C) 2015 Glider bvba
*/
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/mfd/da9063/registers.h>
#define IRQC_BASE 0xe61c0000
#define IRQC_MONITOR 0x104 /* IRQn Signal Level Monitor Register */
#define REGULATOR_IRQ_MASK BIT(2) /* IRQ2, active low */
/* start of DA9210 System Control and Event Registers */
#define DA9210_REG_MASK_A 0x54
struct regulator_quirk {
struct list_head list;
const struct of_device_id *id;
struct device_node *np;
struct of_phandle_args irq_args;
struct i2c_msg i2c_msg;
bool shared; /* IRQ line is shared */
};
static LIST_HEAD(quirk_list);
static void __iomem *irqc;
/* first byte sets the memory pointer, following are consecutive reg values */
static u8 da9063_irq_clr[] = { DA9063_REG_IRQ_MASK_A, 0xff, 0xff, 0xff, 0xff };
static u8 da9210_irq_clr[] = { DA9210_REG_MASK_A, 0xff, 0xff };
static struct i2c_msg da9063_msg = {
.len = ARRAY_SIZE(da9063_irq_clr),
.buf = da9063_irq_clr,
};
static struct i2c_msg da9210_msg = {
.len = ARRAY_SIZE(da9210_irq_clr),
.buf = da9210_irq_clr,
};
static const struct of_device_id rcar_gen2_quirk_match[] = {
{ .compatible = "dlg,da9063", .data = &da9063_msg },
{ .compatible = "dlg,da9063l", .data = &da9063_msg },
{ .compatible = "dlg,da9210", .data = &da9210_msg },
{ /* sentinel */ }
};
static int regulator_quirk_notify(struct notifier_block *nb,
unsigned long action, void *data)
{
struct regulator_quirk *pos, *tmp;
struct device *dev = data;
struct i2c_client *client;
static bool done;
int ret;
u32 mon;
if (done)
return 0;
mon = ioread32(irqc + IRQC_MONITOR);
dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
if (mon & REGULATOR_IRQ_MASK)
goto remove;
if (action != BUS_NOTIFY_ADD_DEVICE || dev->type == &i2c_adapter_type)
return 0;
client = to_i2c_client(dev);
dev_dbg(dev, "Detected %s\n", client->name);
/*
* Send message to all PMICs that share an IRQ line to deassert it.
*
* WARNING: This works only if all the PMICs are on the same I2C bus.
*/
list_for_each_entry(pos, &quirk_list, list) {
if (!pos->shared)
continue;
if (pos->np->parent != client->dev.parent->of_node)
continue;
dev_info(&client->dev, "clearing %s@0x%02x interrupts\n",
pos->id->compatible, pos->i2c_msg.addr);
ret = i2c_transfer(client->adapter, &pos->i2c_msg, 1);
if (ret != 1)
dev_err(&client->dev, "i2c error %d\n", ret);
}
mon = ioread32(irqc + IRQC_MONITOR);
if (mon & REGULATOR_IRQ_MASK)
goto remove;
return 0;
remove:
dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
list_del(&pos->list);
of_node_put(pos->np);
kfree(pos);
}
done = true;
iounmap(irqc);
return 0;
}
static struct notifier_block regulator_quirk_nb = {
.notifier_call = regulator_quirk_notify
};
static int __init rcar_gen2_regulator_quirk(void)
{
struct regulator_quirk *quirk, *pos, *tmp;
struct of_phandle_args *argsa, *argsb;
const struct of_device_id *id;
struct device_node *np;
u32 mon, addr;
int ret;
if (!of_machine_is_compatible("renesas,koelsch") &&
!of_machine_is_compatible("renesas,lager") &&
!of_machine_is_compatible("renesas,porter") &&
!of_machine_is_compatible("renesas,stout") &&
!of_machine_is_compatible("renesas,gose"))
return -ENODEV;
for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) {
if (!of_device_is_available(np)) {
of_node_put(np);
break;
}
ret = of_property_read_u32(np, "reg", &addr);
if (ret) /* Skip invalid entry and continue */
continue;
quirk = kzalloc(sizeof(*quirk), GFP_KERNEL);
if (!quirk) {
ret = -ENOMEM;
of_node_put(np);
goto err_mem;
}
argsa = &quirk->irq_args;
memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
quirk->id = id;
quirk->np = of_node_get(np);
quirk->i2c_msg.addr = addr;
ret = of_irq_parse_one(np, 0, argsa);
if (ret) { /* Skip invalid entry and continue */
of_node_put(np);
kfree(quirk);
continue;
}
list_for_each_entry(pos, &quirk_list, list) {
argsb = &pos->irq_args;
if (argsa->args_count != argsb->args_count)
continue;
ret = memcmp(argsa->args, argsb->args,
argsa->args_count *
sizeof(argsa->args[0]));
if (!ret) {
pos->shared = true;
quirk->shared = true;
}
}
list_add_tail(&quirk->list, &quirk_list);
}
irqc = ioremap(IRQC_BASE, PAGE_SIZE);
if (!irqc) {
ret = -ENOMEM;
goto err_mem;
}
mon = ioread32(irqc + IRQC_MONITOR);
if (mon & REGULATOR_IRQ_MASK) {
pr_debug("%s: IRQ2 is not asserted, not installing quirk\n",
__func__);
ret = 0;
goto err_free;
}
pr_info("IRQ2 is asserted, installing regulator quirk\n");
bus_register_notifier(&i2c_bus_type, ®ulator_quirk_nb);
return 0;
err_free:
iounmap(irqc);
err_mem:
list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
list_del(&pos->list);
of_node_put(pos->np);
kfree(pos);
}
return ret;
}
arch_initcall(rcar_gen2_regulator_quirk);
| linux-master | arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for SoCs with SCU covered by mach-shmobile
*
* Copyright (C) 2013 Magnus Damm
*/
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "common.h"
static phys_addr_t shmobile_scu_base_phys;
static void __iomem *shmobile_scu_base;
static int shmobile_scu_cpu_prepare(unsigned int cpu)
{
/* For this particular CPU register SCU SMP boot vector */
shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu),
shmobile_scu_base_phys);
return 0;
}
void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
unsigned int max_cpus)
{
/* install boot code shared by all CPUs */
shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
/* enable SCU and cache coherency on booting CPU */
shmobile_scu_base_phys = scu_base_phys;
shmobile_scu_base = ioremap(scu_base_phys, PAGE_SIZE);
scu_enable(shmobile_scu_base);
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
/* Use CPU notifier for reset vector control */
cpuhp_setup_state_nocalls(CPUHP_ARM_SHMOBILE_SCU_PREPARE,
"arm/shmobile-scu:prepare",
shmobile_scu_cpu_prepare, NULL);
}
#ifdef CONFIG_HOTPLUG_CPU
void shmobile_smp_scu_cpu_die(unsigned int cpu)
{
/* For this particular CPU deregister boot vector */
shmobile_smp_hook(cpu, 0, 0);
dsb();
flush_cache_all();
/* disable cache coherency */
scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
/* jump to shared mach-shmobile sleep / reset code */
shmobile_smp_sleep();
}
static int shmobile_smp_scu_psr_core_disabled(int cpu)
{
unsigned long mask = SCU_PM_POWEROFF << (cpu * 8);
if ((readl(shmobile_scu_base + 8) & mask) == mask)
return 1;
return 0;
}
int shmobile_smp_scu_cpu_kill(unsigned int cpu)
{
int k;
/* this function is running on another CPU than the offline target,
* here we need wait for shutdown code in platform_cpu_die() to
* finish before asking SoC-specific code to power off the CPU core.
*/
for (k = 0; k < 1000; k++) {
if (shmobile_smp_scu_psr_core_disabled(cpu))
return 1;
mdelay(1);
}
return 0;
}
#endif
| linux-master | arch/arm/mach-shmobile/platsmp-scu.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r7s9210 processor support
*
* Copyright (C) 2018 Renesas Electronics Corporation
* Copyright (C) 2018 Chris Brandt
*
*/
#include <linux/kernel.h>
#include <asm/mach/arch.h>
#include "common.h"
static const char *const r7s9210_boards_compat_dt[] __initconst = {
"renesas,r7s9210",
NULL
};
DT_MACHINE_START(R7S72100_DT, "Generic R7S9210 (Flattened Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_early = shmobile_init_delay,
.init_late = shmobile_init_late,
.dt_compat = r7s9210_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-r7s9210.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SH-Mobile Timer
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2002 - 2009 Paul Mundt
*/
#include <linux/platform_device.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include "common.h"
void __init shmobile_init_delay(void)
{
struct device_node *np;
u32 max_freq = 0;
for_each_of_cpu_node(np) {
u32 freq;
if (!of_property_read_u32(np, "clock-frequency", &freq))
max_freq = max(max_freq, freq);
}
if (!max_freq)
return;
/*
* Calculate a worst-case loops-per-jiffy value
* based on maximum cpu core hz setting and the
* __delay() implementation in arch/arm/lib/delay.S.
*
* This will result in a longer delay than expected
* when the cpu core runs on lower frequencies.
*/
if (!preset_lpj)
preset_lpj = max_freq / HZ;
}
| linux-master | arch/arm/mach-shmobile/timer.c |
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car Generation 2 Power management support
*
* Copyright (C) 2013 - 2015 Renesas Electronics Corporation
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Magnus Damm
*/
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <asm/io.h>
#include <asm/cputype.h>
#include "common.h"
#include "rcar-gen2.h"
/* RST */
#define RST 0xe6160000
#define CA15BAR 0x0020 /* CA15 Boot Address Register */
#define CA7BAR 0x0030 /* CA7 Boot Address Register */
#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
/* SYS Boot Address Register */
#define SBAR_BAREN BIT(4) /* SBAR is valid */
/* Reset Control Registers */
#define CA15RESCNT_CODE 0xa5a50000
#define CA15RESCNT_CPUS 0xf /* CPU0-3 */
#define CA7RESCNT_CODE 0x5a5a0000
#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
/* On-chip RAM */
#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
static inline u32 phys_to_sbar(phys_addr_t addr)
{
return (addr >> 8) & 0xfffffc00;
}
void __init rcar_gen2_pm_init(void)
{
void __iomem *p;
u32 bar;
static int once;
struct device_node *np;
bool has_a7 = false;
bool has_a15 = false;
struct resource res;
int error;
if (once++)
return;
for_each_of_cpu_node(np) {
if (of_device_is_compatible(np, "arm,cortex-a15"))
has_a15 = true;
else if (of_device_is_compatible(np, "arm,cortex-a7"))
has_a7 = true;
}
np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
if (!np) {
/* No smp-sram in DT, fall back to hardcoded address */
res = (struct resource)DEFINE_RES_MEM(ICRAM1,
shmobile_boot_size);
goto map;
}
error = of_address_to_resource(np, 0, &res);
of_node_put(np);
if (error) {
pr_err("Failed to get smp-sram address: %d\n", error);
return;
}
map:
/* RAM for jump stub, because BAR requires 256KB aligned address */
if (res.start & (256 * 1024 - 1) ||
resource_size(&res) < shmobile_boot_size) {
pr_err("Invalid smp-sram region\n");
return;
}
p = ioremap(res.start, resource_size(&res));
if (!p)
return;
/*
* install the reset vector, use the largest version if we have enough
* memory available
*/
if (resource_size(&res) >= shmobile_boot_size_gen2) {
shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
memcpy_toio(p, shmobile_boot_vector_gen2,
shmobile_boot_size_gen2);
} else {
memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
}
iounmap(p);
/* setup reset vectors */
p = ioremap(RST, 0x63);
bar = phys_to_sbar(res.start);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
/* de-assert reset for CA15 CPUs */
writel_relaxed((readl_relaxed(p + CA15RESCNT) &
~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
/* de-assert reset for CA7 CPUs */
writel_relaxed((readl_relaxed(p + CA7RESCNT) &
~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
p + CA7RESCNT);
}
iounmap(p);
shmobile_smp_apmu_suspend_init();
}
| linux-master | arch/arm/mach-shmobile/pm-rcar-gen2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for SoCs with APMU
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2013 Magnus Damm
*/
#include <linux/cpu_pm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/suspend.h>
#include <linux/threads.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/proc-fns.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include "common.h"
#include "rcar-gen2.h"
static struct {
void __iomem *iomem;
int bit;
} apmu_cpus[NR_CPUS];
#define WUPCR_OFFS 0x10 /* Wake Up Control Register */
#define PSTR_OFFS 0x40 /* Power Status Register */
#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
/* CPUn Power Status Control Register */
#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */
/* Power Status Register */
#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */
#define CPUST_RUN 0 /* Run Mode */
#define CPUST_STANDBY 3 /* CoreStandby Mode */
/* Debug Resource Reset Control Register */
#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */
#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */
#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */
static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
{
/* request power on */
writel_relaxed(BIT(bit), p + WUPCR_OFFS);
/* wait for APMU to finish */
while (readl_relaxed(p + WUPCR_OFFS) != 0)
;
return 0;
}
static int __maybe_unused apmu_power_off(void __iomem *p, int bit)
{
/* request Core Standby for next WFI */
writel_relaxed(3, p + CPUNCR_OFFS(bit));
return 0;
}
static int __maybe_unused apmu_power_off_poll(void __iomem *p, int bit)
{
int k;
for (k = 0; k < 1000; k++) {
if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
return 1;
mdelay(1);
}
return 0;
}
static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
{
void __iomem *p = apmu_cpus[cpu].iomem;
return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
}
#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_SUSPEND)
/* nicked from arch/arm/mach-exynos/hotplug.c */
static inline void cpu_enter_lowpower_a15(void)
{
unsigned int v;
asm volatile(
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "Ir" (CR_C)
: "cc");
flush_cache_louis();
asm volatile(
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (0x40)
: "cc");
isb();
dsb();
}
static void shmobile_smp_apmu_cpu_shutdown(unsigned int cpu)
{
/* Select next sleep mode using the APMU */
apmu_wrap(cpu, apmu_power_off);
/* Do ARM specific CPU shutdown */
cpu_enter_lowpower_a15();
}
#endif
#if defined(CONFIG_HOTPLUG_CPU)
static void shmobile_smp_apmu_cpu_die(unsigned int cpu)
{
/* For this particular CPU deregister boot vector */
shmobile_smp_hook(cpu, 0, 0);
/* Shutdown CPU core */
shmobile_smp_apmu_cpu_shutdown(cpu);
/* jump to shared mach-shmobile sleep / reset code */
shmobile_smp_sleep();
}
static int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
{
return apmu_wrap(cpu, apmu_power_off_poll);
}
#endif
#if defined(CONFIG_SUSPEND)
static int shmobile_smp_apmu_do_suspend(unsigned long cpu)
{
shmobile_smp_hook(cpu, __pa_symbol(cpu_resume), 0);
shmobile_smp_apmu_cpu_shutdown(cpu);
cpu_do_idle(); /* WFI selects Core Standby */
return 1;
}
static inline void cpu_leave_lowpower(void)
{
unsigned int v;
asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
" orr %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
" mrc p15, 0, %0, c1, c0, 1\n"
" orr %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
static int shmobile_smp_apmu_enter_suspend(suspend_state_t state)
{
cpu_suspend(smp_processor_id(), shmobile_smp_apmu_do_suspend);
cpu_leave_lowpower();
return 0;
}
void __init shmobile_smp_apmu_suspend_init(void)
{
shmobile_suspend_ops.enter = shmobile_smp_apmu_enter_suspend;
}
#endif
#ifdef CONFIG_SMP
static void apmu_init_cpu(struct resource *res, int cpu, int bit)
{
u32 x;
if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
return;
apmu_cpus[cpu].iomem = ioremap(res->start, resource_size(res));
apmu_cpus[cpu].bit = bit;
pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
/* Setup for debug mode */
x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
}
static const struct of_device_id apmu_ids[] = {
{ .compatible = "renesas,apmu" },
{ /*sentinel*/ }
};
static void apmu_parse_dt(void (*fn)(struct resource *res, int cpu, int bit))
{
struct device_node *np_apmu, *np_cpu;
struct resource res;
int bit, index;
for_each_matching_node(np_apmu, apmu_ids) {
/* only enable the cluster that includes the boot CPU */
bool is_allowed = false;
for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
if (!np_cpu)
break;
if (of_cpu_node_to_id(np_cpu) == 0) {
is_allowed = true;
of_node_put(np_cpu);
break;
}
of_node_put(np_cpu);
}
if (!is_allowed)
continue;
for (bit = 0; bit < CONFIG_NR_CPUS; bit++) {
np_cpu = of_parse_phandle(np_apmu, "cpus", bit);
if (!np_cpu)
break;
index = of_cpu_node_to_id(np_cpu);
if ((index >= 0) &&
!of_address_to_resource(np_apmu, 0, &res))
fn(&res, index, bit);
of_node_put(np_cpu);
}
}
}
static void __init shmobile_smp_apmu_setup_boot(void)
{
/* install boot code shared by all CPUs */
shmobile_boot_fn = __pa_symbol(shmobile_smp_boot);
shmobile_boot_fn_gen2 = shmobile_boot_fn;
}
static int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
/* For this particular CPU register boot vector */
shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_apmu), 0);
return apmu_wrap(cpu, apmu_power_on);
}
static void __init shmobile_smp_apmu_prepare_cpus_dt(unsigned int max_cpus)
{
shmobile_smp_apmu_setup_boot();
apmu_parse_dt(apmu_init_cpu);
rcar_gen2_pm_init();
}
static struct smp_operations apmu_smp_ops __initdata = {
.smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
.smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_can_disable = shmobile_smp_cpu_can_disable,
.cpu_die = shmobile_smp_apmu_cpu_die,
.cpu_kill = shmobile_smp_apmu_cpu_kill,
#endif
};
CPU_METHOD_OF_DECLARE(shmobile_smp_apmu, "renesas,apmu", &apmu_smp_ops);
#endif /* CONFIG_SMP */
| linux-master | arch/arm/mach-shmobile/platsmp-apmu.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Suspend-to-RAM support code for SH-Mobile ARM
*
* Copyright (C) 2011 Magnus Damm
*/
#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/cpu.h>
#include <asm/io.h>
#include <asm/system_misc.h>
#include "common.h"
static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
{
cpu_do_idle();
return 0;
}
static int shmobile_suspend_begin(suspend_state_t state)
{
cpu_idle_poll_ctrl(true);
return 0;
}
static void shmobile_suspend_end(void)
{
cpu_idle_poll_ctrl(false);
}
struct platform_suspend_ops shmobile_suspend_ops = {
.begin = shmobile_suspend_begin,
.end = shmobile_suspend_end,
.enter = shmobile_suspend_default_enter,
.valid = suspend_valid_only_mem,
};
int __init shmobile_suspend_init(void)
{
suspend_set_ops(&shmobile_suspend_ops);
return 0;
}
| linux-master | arch/arm/mach-shmobile/suspend.c |
// SPDX-License-Identifier: GPL-2.0
/*
* sh73a0 processor support
*
* Copyright (C) 2010 Takashi Yoshii
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2008 Yoshihiro Shimoda
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
#include "sh73a0.h"
static void __init sh73a0_generic_init(void)
{
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(ioremap(0xf0100000, PAGE_SIZE), 0x00400000, 0xc20f0fff);
#endif
}
static const char *const sh73a0_boards_compat_dt[] __initconst = {
"renesas,sh73a0",
NULL
};
DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.smp = smp_ops(sh73a0_smp_ops),
.init_machine = sh73a0_generic_init,
.init_late = shmobile_init_late,
.dt_compat = sh73a0_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-sh73a0.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7779 processor support
*
* Copyright (C) 2011, 2013 Renesas Solutions Corp.
* Copyright (C) 2011 Magnus Damm
* Copyright (C) 2013 Cogent Embedded, Inc.
*/
#include <linux/init.h>
#include <linux/irqchip.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "r8a7779.h"
#define HPBREG_BASE 0xfe700000
/* IRQ */
#define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */
#define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */
#define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */
#define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */
#define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */
#define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */
#define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */
static void __init r8a7779_init_irq_dt(void)
{
void __iomem *base = ioremap(HPBREG_BASE, 0x00100000);
irqchip_init();
/* route all interrupts to ARM */
writel(0xffffffff, base + INT2NTSR0);
writel(0x3fffffff, base + INT2NTSR1);
/* unmask all known interrupts in INTCS2 */
writel(0xfffffff0, base + INT2SMSKCR0);
writel(0xfff7ffff, base + INT2SMSKCR1);
writel(0xfffbffdf, base + INT2SMSKCR2);
writel(0xbffffffc, base + INT2SMSKCR3);
writel(0x003fee3f, base + INT2SMSKCR4);
iounmap(base);
}
static const char *const r8a7779_compat_dt[] __initconst = {
"renesas,r8a7779",
NULL
};
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
.smp = smp_ops(r8a7779_smp_ops),
.init_irq = r8a7779_init_irq_dt,
.init_late = shmobile_init_late,
.dt_compat = r8a7779_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-r8a7779.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for R-Mobile / SH-Mobile - sh73a0 portion
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2010 Takashi Yoshii
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <asm/smp_plat.h>
#include "common.h"
#include "sh73a0.h"
#define CPG_BASE2 0xe6151000
#define WUPCR 0x10 /* System-CPU Wake Up Control Register */
#define SRESCR 0x18 /* System-CPU Software Reset Control Register */
#define PSTR 0x40 /* System-CPU Power Status Register */
#define SYSC_BASE 0xe6180000
#define SBAR 0x20 /* SYS Boot Address Register */
#define AP_BASE 0xe6f10000
#define APARMBAREA 0x20 /* Address Translation Area Register */
#define SH73A0_SCU_BASE 0xf0000000
static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned int lcpu = cpu_logical_map(cpu);
void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE);
if (((readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3)
writel(1 << lcpu, cpg2 + WUPCR); /* wake up */
else
writel(1 << lcpu, cpg2 + SRESCR); /* reset */
iounmap(cpg2);
return 0;
}
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
{
void __iomem *ap = ioremap(AP_BASE, PAGE_SIZE);
void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE);
/* Map the reset vector (in headsmp.S) */
writel(0, ap + APARMBAREA); /* 4k */
writel(__pa(shmobile_boot_vector), sysc + SBAR);
iounmap(sysc);
iounmap(ap);
/* setup sh73a0 specific SCU bits */
shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus);
}
const struct smp_operations sh73a0_smp_ops __initconst = {
.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
.smp_boot_secondary = sh73a0_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_can_disable = shmobile_smp_cpu_can_disable,
.cpu_die = shmobile_smp_scu_cpu_die,
.cpu_kill = shmobile_smp_scu_cpu_kill,
#endif
};
| linux-master | arch/arm/mach-shmobile/smp-sh73a0.c |
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car Generation 2 support
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
* Copyright (C) 2014 Ulrich Hecht
*/
#include <linux/clocksource.h>
#include <linux/device.h>
#include <linux/dma-map-ops.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/of_fdt.h>
#include <linux/psci.h>
#include <asm/mach/arch.h>
#include <asm/secure_cntvoff.h>
#include "common.h"
#include "rcar-gen2.h"
static const struct of_device_id cpg_matches[] __initconst = {
{ .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
{ /* sentinel */ }
};
static unsigned int __init get_extal_freq(void)
{
const struct of_device_id *match;
struct device_node *cpg, *extal;
u32 freq = 20000000;
int idx = 0;
cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match);
if (!cpg)
return freq;
if (match->data)
idx = of_property_match_string(cpg, "clock-names", match->data);
extal = of_parse_phandle(cpg, "clocks", idx);
of_node_put(cpg);
if (!extal)
return freq;
of_property_read_u32(extal, "clock-frequency", &freq);
of_node_put(extal);
return freq;
}
#define CNTCR 0
#define CNTFID0 0x20
static void __init rcar_gen2_timer_init(void)
{
bool need_update = true;
void __iomem *base;
u32 freq;
/*
* If PSCI is available then most likely we are running on PSCI-enabled
* U-Boot which, we assume, has already taken care of resetting CNTVOFF
* and updating counter module before switching to non-secure mode
* and we don't need to.
*/
#ifdef CONFIG_ARM_PSCI_FW
if (psci_ops.cpu_on)
need_update = false;
#endif
if (need_update == false)
goto skip_update;
secure_cntvoff_init();
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a77470") ||
of_machine_is_compatible("renesas,r8a7792") ||
of_machine_is_compatible("renesas,r8a7794")) {
freq = 260000000 / 8; /* ZS / 8 */
} else {
/* At Linux boot time the r8a7790 arch timer comes up
* with the counter disabled. Moreover, it may also report
* a potentially incorrect fixed 13 MHz frequency. To be
* correct these registers need to be updated to use the
* frequency EXTAL / 2.
*/
freq = get_extal_freq() / 2;
}
/* Remap "armgcnt address map" space */
base = ioremap(0xe6080000, PAGE_SIZE);
/*
* Update the timer if it is either not running, or is not at the
* right frequency. The timer is only configurable in secure mode
* so this avoids an abort if the loader started the timer and
* entered the kernel in non-secure mode.
*/
if ((ioread32(base + CNTCR) & 1) == 0 ||
ioread32(base + CNTFID0) != freq) {
/* Update registers with correct frequency */
iowrite32(freq, base + CNTFID0);
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
/* make sure arch timer is started by setting bit 0 of CNTCR */
iowrite32(1, base + CNTCR);
}
iounmap(base);
skip_update:
of_clk_init(NULL);
timer_probe();
}
struct memory_reserve_config {
u64 reserved;
u64 base, size;
};
static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
int depth, void *data)
{
const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
const __be32 *reg, *endp;
int l;
struct memory_reserve_config *mrc = data;
u64 lpae_start = 1ULL << 32;
/* We are scanning "memory" nodes only */
if (type == NULL || strcmp(type, "memory"))
return 0;
reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
if (reg == NULL)
reg = of_get_flat_dt_prop(node, "reg", &l);
if (reg == NULL)
return 0;
endp = reg + (l / sizeof(__be32));
while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
u64 base, size;
base = dt_mem_next_cell(dt_root_addr_cells, ®);
size = dt_mem_next_cell(dt_root_size_cells, ®);
if (base >= lpae_start)
continue;
if ((base + size) >= lpae_start)
size = lpae_start - base;
if (size < mrc->reserved)
continue;
if (base < mrc->base)
continue;
/* keep the area at top near the 32-bit legacy limit */
mrc->base = base + size - mrc->reserved;
mrc->size = mrc->reserved;
}
return 0;
}
static void __init rcar_gen2_reserve(void)
{
struct memory_reserve_config mrc;
/* reserve 256 MiB at the top of the physical legacy 32-bit space */
memset(&mrc, 0, sizeof(mrc));
mrc.reserved = SZ_256M;
of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
#ifdef CONFIG_DMA_CMA
if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
static struct cma *rcar_gen2_dma_contiguous;
dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
&rcar_gen2_dma_contiguous, true);
}
#endif
}
static const char * const rcar_gen2_boards_compat_dt[] __initconst = {
"renesas,r8a7790",
"renesas,r8a7791",
"renesas,r8a7792",
"renesas,r8a7793",
"renesas,r8a7794",
NULL
};
DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
.init_late = shmobile_init_late,
.init_time = rcar_gen2_timer_init,
.reserve = rcar_gen2_reserve,
.dt_compat = rcar_gen2_boards_compat_dt,
MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
"renesas,r8a7742",
"renesas,r8a7743",
"renesas,r8a7744",
"renesas,r8a7745",
"renesas,r8a77470",
NULL
};
DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)")
.init_late = shmobile_init_late,
.init_time = rcar_gen2_timer_init,
.reserve = rcar_gen2_reserve,
.dt_compat = rz_g1_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-rcar-gen2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r7s72100 processor support
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
*/
#include <linux/kernel.h>
#include <asm/mach/arch.h>
#include "common.h"
static const char *const r7s72100_boards_compat_dt[] __initconst = {
"renesas,r7s72100",
NULL
};
DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_early = shmobile_init_delay,
.init_late = shmobile_init_late,
.dt_compat = r7s72100_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-r7s72100.c |
// SPDX-License-Identifier: GPL-2.0
/*
* r8a7778 processor support
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Kuninori Morimoto <[email protected]>
* Copyright (C) 2013 Cogent Embedded, Inc.
*/
#include <linux/io.h>
#include <linux/irqchip.h>
#include <asm/mach/arch.h>
#include "common.h"
#define HPBREG_BASE 0xfe700000
#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
#define INT2NTSR0 0x00018 /* 0xfe700018 */
#define INT2NTSR1 0x0002c /* 0xfe70002c */
static void __init r8a7778_init_irq_dt(void)
{
void __iomem *base = ioremap(HPBREG_BASE, 0x00100000);
BUG_ON(!base);
irqchip_init();
/* route all interrupts to ARM */
writel(0x73ffffff, base + INT2NTSR0);
writel(0xffffffff, base + INT2NTSR1);
/* unmask all known interrupts in INTCS2 */
writel(0x08330773, base + INT2SMSKCR0);
writel(0x00311110, base + INT2SMSKCR1);
iounmap(base);
}
static const char *const r8a7778_compat_dt[] __initconst = {
"renesas,r8a7778",
NULL
};
DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
.init_irq = r8a7778_init_irq_dt,
.init_late = shmobile_init_late,
.dt_compat = r8a7778_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-r8a7778.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Emma Mobile EV2 processor support
*
* Copyright (C) 2012 Magnus Damm
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "emev2.h"
static const char *const emev2_boards_compat_dt[] __initconst = {
"renesas,emev2",
NULL
};
DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
.smp = smp_ops(emev2_smp_ops),
.init_early = shmobile_init_delay,
.init_late = shmobile_init_late,
.dt_compat = emev2_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-emev2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for Emma Mobile EV2
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Magnus Damm
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "common.h"
#include "emev2.h"
#define EMEV2_SCU_BASE 0x1e000000
#define EMEV2_SMU_BASE 0xe0110000
#define SMU_GENERAL_REG0 0x7c0
static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
return 0;
}
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
{
void __iomem *smu;
/* Tell ROM loader about our vector (in headsmp.S) */
smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
if (smu) {
iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
iounmap(smu);
}
/* setup EMEV2 specific SCU bits */
shmobile_smp_scu_prepare_cpus(EMEV2_SCU_BASE, max_cpus);
}
const struct smp_operations emev2_smp_ops __initconst = {
.smp_prepare_cpus = emev2_smp_prepare_cpus,
.smp_boot_secondary = emev2_boot_secondary,
};
| linux-master | arch/arm/mach-shmobile/smp-emev2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SMP support for R-Mobile / SH-Mobile
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2011 Paul Mundt
*
* Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
*/
#include <linux/init.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "common.h"
extern unsigned long shmobile_smp_fn[];
extern unsigned long shmobile_smp_arg[];
extern unsigned long shmobile_smp_mpidr[];
void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg)
{
shmobile_smp_fn[cpu] = 0;
flush_cache_all();
shmobile_smp_mpidr[cpu] = cpu_logical_map(cpu);
shmobile_smp_fn[cpu] = fn;
shmobile_smp_arg[cpu] = arg;
flush_cache_all();
}
#ifdef CONFIG_HOTPLUG_CPU
bool shmobile_smp_cpu_can_disable(unsigned int cpu)
{
return true; /* Hotplug of any CPU is supported */
}
#endif
| linux-master | arch/arm/mach-shmobile/platsmp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* R8A7740 processor support
*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
/*
* r8a7740 chip has lasting errata on MERAM buffer.
* this is work-around for it.
* see
* "Media RAM (MERAM)" on r8a7740 documentation
*/
#define MEBUFCNTR 0xFE950098
static void __init r8a7740_meram_workaround(void)
{
void __iomem *reg;
reg = ioremap(MEBUFCNTR, 4);
if (reg) {
iowrite32(0x01600164, reg);
iounmap(reg);
}
}
static void __init r8a7740_init_irq_of(void)
{
void __iomem *intc_prio_base = ioremap(0xe6900010, 0x10);
void __iomem *intc_msk_base = ioremap(0xe6900040, 0x10);
void __iomem *pfc_inta_ctrl = ioremap(0xe605807c, 0x4);
irqchip_init();
/* route signals to GIC */
iowrite32(0x0, pfc_inta_ctrl);
/*
* To mask the shared interrupt to SPI 149 we must ensure to set
* PRIO *and* MASK. Else we run into IRQ floods when registering
* the intc_irqpin devices
*/
iowrite32(0x0, intc_prio_base + 0x0);
iowrite32(0x0, intc_prio_base + 0x4);
iowrite32(0x0, intc_prio_base + 0x8);
iowrite32(0x0, intc_prio_base + 0xc);
iowrite8(0xff, intc_msk_base + 0x0);
iowrite8(0xff, intc_msk_base + 0x4);
iowrite8(0xff, intc_msk_base + 0x8);
iowrite8(0xff, intc_msk_base + 0xc);
iounmap(intc_prio_base);
iounmap(intc_msk_base);
iounmap(pfc_inta_ctrl);
}
static void __init r8a7740_generic_init(void)
{
r8a7740_meram_workaround();
}
static const char *const r8a7740_boards_compat_dt[] __initconst = {
"renesas,r8a7740",
NULL
};
DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_early = shmobile_init_delay,
.init_irq = r8a7740_init_irq_of,
.init_machine = r8a7740_generic_init,
.init_late = shmobile_init_late,
.dt_compat = r8a7740_boards_compat_dt,
MACHINE_END
| linux-master | arch/arm/mach-shmobile/setup-r8a7740.c |
/*
* arch/arm/plat-orion/mpp.c
*
* MPP functions for Marvell orion SoCs
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/orion-gpio.h>
#include <plat/mpp.h>
/* Address of the ith MPP control register */
static __init void __iomem *mpp_ctrl_addr(unsigned int i,
void __iomem *dev_bus)
{
return dev_bus + (i) * 4;
}
void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
unsigned int mpp_max, void __iomem *dev_bus)
{
unsigned int mpp_nr_regs = (1 + mpp_max/8);
u32 mpp_ctrl[8];
int i;
printk(KERN_DEBUG "initial MPP regs:");
if (mpp_nr_regs > ARRAY_SIZE(mpp_ctrl)) {
printk(KERN_ERR "orion_mpp_conf: invalid mpp_max\n");
return;
}
for (i = 0; i < mpp_nr_regs; i++) {
mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
if (num > mpp_max) {
printk(KERN_ERR "orion_mpp_conf: invalid MPP "
"number (%u)\n", num);
continue;
}
if (variant_mask && !(*mpp_list & variant_mask)) {
printk(KERN_WARNING
"orion_mpp_conf: requested MPP%u config "
"unavailable on this hardware\n", num);
continue;
}
shift = (num & 7) << 2;
mpp_ctrl[num / 8] &= ~(0xf << shift);
mpp_ctrl[num / 8] |= sel << shift;
gpio_mode = 0;
if (*mpp_list & MPP_INPUT_MASK)
gpio_mode |= GPIO_INPUT_OK;
if (*mpp_list & MPP_OUTPUT_MASK)
gpio_mode |= GPIO_OUTPUT_OK;
orion_gpio_set_valid(num, gpio_mode);
}
printk(KERN_DEBUG " final MPP regs:");
for (i = 0; i < mpp_nr_regs; i++) {
writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
printk(" %08x", mpp_ctrl[i]);
}
printk("\n");
}
| linux-master | arch/arm/plat-orion/mpp.c |
/*
* arch/arm/plat-orion/common.c
*
* Marvell Orion SoC common setup code used by multiple mach-/common.c
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/ata_platform.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <plat/common.h>
#include <linux/phy.h>
/* Create a clkdev entry for a given device/clk */
void __init orion_clkdev_add(const char *con_id, const char *dev_id,
struct clk *clk)
{
clkdev_create(clk, con_id, "%s", dev_id);
}
/* Create clkdev entries for all orion platforms except kirkwood.
Kirkwood has gated clocks for some of its peripherals, so creates
its own clkdev entries. For all the other orion devices, create
clkdev entries to the tclk. */
void __init orion_clkdev_init(struct clk *tclk)
{
orion_clkdev_add(NULL, "orion_spi.0", tclk);
orion_clkdev_add(NULL, "orion_spi.1", tclk);
orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk);
orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk);
orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
orion_clkdev_add(NULL, "orion_wdt", tclk);
orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
}
/* Fill in the resources structure and link it into the platform
device structure. There is always a memory region, and nearly
always an interrupt.*/
static void fill_resources(struct platform_device *device,
struct resource *resources,
resource_size_t mapbase,
resource_size_t size)
{
device->resource = resources;
device->num_resources = 1;
resources[0].flags = IORESOURCE_MEM;
resources[0].start = mapbase;
resources[0].end = mapbase + size;
}
static void fill_resources_irq(struct platform_device *device,
struct resource *resources,
resource_size_t mapbase,
resource_size_t size,
unsigned int irq)
{
fill_resources(device, resources, mapbase, size);
device->num_resources++;
resources[1].flags = IORESOURCE_IRQ;
resources[1].start = irq;
resources[1].end = irq;
}
/*****************************************************************************
* UART
****************************************************************************/
static unsigned long __init uart_get_clk_rate(struct clk *clk)
{
clk_prepare_enable(clk);
return clk_get_rate(clk);
}
static void __init uart_complete(
struct platform_device *orion_uart,
struct plat_serial8250_port *data,
struct resource *resources,
void __iomem *membase,
resource_size_t mapbase,
unsigned int irq,
struct clk *clk)
{
data->mapbase = mapbase;
data->membase = membase;
data->irq = irq;
data->uartclk = uart_get_clk_rate(clk);
orion_uart->dev.platform_data = data;
fill_resources_irq(orion_uart, resources, mapbase, 0xff, irq);
platform_device_register(orion_uart);
}
/*****************************************************************************
* UART0
****************************************************************************/
static struct plat_serial8250_port orion_uart0_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart0_resources[2];
static struct platform_device orion_uart0 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
};
void __init orion_uart0_init(void __iomem *membase,
resource_size_t mapbase,
unsigned int irq,
struct clk *clk)
{
uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
membase, mapbase, irq, clk);
}
/*****************************************************************************
* UART1
****************************************************************************/
static struct plat_serial8250_port orion_uart1_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart1_resources[2];
static struct platform_device orion_uart1 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
};
void __init orion_uart1_init(void __iomem *membase,
resource_size_t mapbase,
unsigned int irq,
struct clk *clk)
{
uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
membase, mapbase, irq, clk);
}
/*****************************************************************************
* UART2
****************************************************************************/
static struct plat_serial8250_port orion_uart2_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart2_resources[2];
static struct platform_device orion_uart2 = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
};
void __init orion_uart2_init(void __iomem *membase,
resource_size_t mapbase,
unsigned int irq,
struct clk *clk)
{
uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
membase, mapbase, irq, clk);
}
/*****************************************************************************
* UART3
****************************************************************************/
static struct plat_serial8250_port orion_uart3_data[] = {
{
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
}, {
},
};
static struct resource orion_uart3_resources[2];
static struct platform_device orion_uart3 = {
.name = "serial8250",
.id = 3,
};
void __init orion_uart3_init(void __iomem *membase,
resource_size_t mapbase,
unsigned int irq,
struct clk *clk)
{
uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
membase, mapbase, irq, clk);
}
/*****************************************************************************
* SoC RTC
****************************************************************************/
static struct resource orion_rtc_resource[2];
void __init orion_rtc_init(unsigned long mapbase,
unsigned long irq)
{
orion_rtc_resource[0].start = mapbase;
orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
orion_rtc_resource[0].flags = IORESOURCE_MEM;
orion_rtc_resource[1].start = irq;
orion_rtc_resource[1].end = irq;
orion_rtc_resource[1].flags = IORESOURCE_IRQ;
platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
}
/*****************************************************************************
* GE
****************************************************************************/
static __init void ge_complete(
struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
struct resource *orion_ge_resource, unsigned long irq,
struct platform_device *orion_ge_shared,
struct platform_device *orion_ge_mvmdio,
struct mv643xx_eth_platform_data *eth_data,
struct platform_device *orion_ge)
{
orion_ge_resource->start = irq;
orion_ge_resource->end = irq;
eth_data->shared = orion_ge_shared;
orion_ge->dev.platform_data = eth_data;
platform_device_register(orion_ge_shared);
if (orion_ge_mvmdio)
platform_device_register(orion_ge_mvmdio);
platform_device_register(orion_ge);
}
/*****************************************************************************
* GE00
****************************************************************************/
static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
static struct resource orion_ge00_shared_resources[] = {
{
.name = "ge00 base",
},
};
static struct platform_device orion_ge00_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.dev = {
.platform_data = &orion_ge00_shared_data,
},
};
static struct resource orion_ge_mvmdio_resources[] = {
{
.name = "ge00 mvmdio base",
}, {
.name = "ge00 mvmdio err irq",
},
};
static struct platform_device orion_ge_mvmdio = {
.name = "orion-mdio",
.id = -1,
};
static struct resource orion_ge00_resources[] = {
{
.name = "ge00 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge00 = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = 1,
.resource = orion_ge00_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
unsigned long mapbase,
unsigned long irq,
unsigned long irq_err,
unsigned int tx_csum_limit)
{
fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
mapbase + 0x2000, SZ_16K - 1);
fill_resources_irq(&orion_ge_mvmdio, orion_ge_mvmdio_resources,
mapbase + 0x2004, 0x84 - 1, irq_err);
orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
ge_complete(&orion_ge00_shared_data,
orion_ge00_resources, irq, &orion_ge00_shared,
&orion_ge_mvmdio,
eth_data, &orion_ge00);
}
/*****************************************************************************
* GE01
****************************************************************************/
static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
static struct resource orion_ge01_shared_resources[] = {
{
.name = "ge01 base",
}
};
static struct platform_device orion_ge01_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 1,
.dev = {
.platform_data = &orion_ge01_shared_data,
},
};
static struct resource orion_ge01_resources[] = {
{
.name = "ge01 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge01 = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = 1,
.resource = orion_ge01_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
unsigned long mapbase,
unsigned long irq,
unsigned int tx_csum_limit)
{
fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
mapbase + 0x2000, SZ_16K - 1);
orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
ge_complete(&orion_ge01_shared_data,
orion_ge01_resources, irq, &orion_ge01_shared,
NULL,
eth_data, &orion_ge01);
}
/*****************************************************************************
* GE10
****************************************************************************/
static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
static struct resource orion_ge10_shared_resources[] = {
{
.name = "ge10 base",
}
};
static struct platform_device orion_ge10_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 2,
.dev = {
.platform_data = &orion_ge10_shared_data,
},
};
static struct resource orion_ge10_resources[] = {
{
.name = "ge10 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge10 = {
.name = MV643XX_ETH_NAME,
.id = 2,
.num_resources = 1,
.resource = orion_ge10_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
unsigned long mapbase,
unsigned long irq)
{
fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
mapbase + 0x2000, SZ_16K - 1);
ge_complete(&orion_ge10_shared_data,
orion_ge10_resources, irq, &orion_ge10_shared,
NULL,
eth_data, &orion_ge10);
}
/*****************************************************************************
* GE11
****************************************************************************/
static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
static struct resource orion_ge11_shared_resources[] = {
{
.name = "ge11 base",
},
};
static struct platform_device orion_ge11_shared = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 3,
.dev = {
.platform_data = &orion_ge11_shared_data,
},
};
static struct resource orion_ge11_resources[] = {
{
.name = "ge11 irq",
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_ge11 = {
.name = MV643XX_ETH_NAME,
.id = 3,
.num_resources = 1,
.resource = orion_ge11_resources,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
unsigned long mapbase,
unsigned long irq)
{
fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
mapbase + 0x2000, SZ_16K - 1);
ge_complete(&orion_ge11_shared_data,
orion_ge11_resources, irq, &orion_ge11_shared,
NULL,
eth_data, &orion_ge11);
}
/*****************************************************************************
* I2C
****************************************************************************/
static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion_i2c_resources[2];
static struct platform_device orion_i2c = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 0,
.dev = {
.platform_data = &orion_i2c_pdata,
},
};
static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
.freq_n = 3,
.timeout = 1000, /* Default timeout of 1 second */
};
static struct resource orion_i2c_1_resources[2];
static struct platform_device orion_i2c_1 = {
.name = MV64XXX_I2C_CTLR_NAME,
.id = 1,
.dev = {
.platform_data = &orion_i2c_1_pdata,
},
};
void __init orion_i2c_init(unsigned long mapbase,
unsigned long irq,
unsigned long freq_m)
{
orion_i2c_pdata.freq_m = freq_m;
fill_resources_irq(&orion_i2c, orion_i2c_resources, mapbase,
SZ_32 - 1, irq);
platform_device_register(&orion_i2c);
}
void __init orion_i2c_1_init(unsigned long mapbase,
unsigned long irq,
unsigned long freq_m)
{
orion_i2c_1_pdata.freq_m = freq_m;
fill_resources_irq(&orion_i2c_1, orion_i2c_1_resources, mapbase,
SZ_32 - 1, irq);
platform_device_register(&orion_i2c_1);
}
/*****************************************************************************
* SPI
****************************************************************************/
static struct resource orion_spi_resources;
static struct platform_device orion_spi = {
.name = "orion_spi",
.id = 0,
};
static struct resource orion_spi_1_resources;
static struct platform_device orion_spi_1 = {
.name = "orion_spi",
.id = 1,
};
/* Note: The SPI silicon core does have interrupts. However the
* current Linux software driver does not use interrupts. */
void __init orion_spi_init(unsigned long mapbase)
{
fill_resources(&orion_spi, &orion_spi_resources,
mapbase, SZ_512 - 1);
platform_device_register(&orion_spi);
}
void __init orion_spi_1_init(unsigned long mapbase)
{
fill_resources(&orion_spi_1, &orion_spi_1_resources,
mapbase, SZ_512 - 1);
platform_device_register(&orion_spi_1);
}
/*****************************************************************************
* XOR
****************************************************************************/
static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* XOR0
****************************************************************************/
static struct resource orion_xor0_shared_resources[] = {
{
.name = "xor 0 low",
.flags = IORESOURCE_MEM,
}, {
.name = "xor 0 high",
.flags = IORESOURCE_MEM,
}, {
.name = "irq channel 0",
.flags = IORESOURCE_IRQ,
}, {
.name = "irq channel 1",
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_channel_data orion_xor0_channels_data[2];
static struct mv_xor_platform_data orion_xor0_pdata = {
.channels = orion_xor0_channels_data,
};
static struct platform_device orion_xor0_shared = {
.name = MV_XOR_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
.resource = orion_xor0_shared_resources,
.dev = {
.dma_mask = &orion_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_xor0_pdata,
},
};
void __init orion_xor0_init(unsigned long mapbase_low,
unsigned long mapbase_high,
unsigned long irq_0,
unsigned long irq_1)
{
orion_xor0_shared_resources[0].start = mapbase_low;
orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
orion_xor0_shared_resources[1].start = mapbase_high;
orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
orion_xor0_shared_resources[2].start = irq_0;
orion_xor0_shared_resources[2].end = irq_0;
orion_xor0_shared_resources[3].start = irq_1;
orion_xor0_shared_resources[3].end = irq_1;
dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
platform_device_register(&orion_xor0_shared);
}
/*****************************************************************************
* XOR1
****************************************************************************/
static struct resource orion_xor1_shared_resources[] = {
{
.name = "xor 1 low",
.flags = IORESOURCE_MEM,
}, {
.name = "xor 1 high",
.flags = IORESOURCE_MEM,
}, {
.name = "irq channel 0",
.flags = IORESOURCE_IRQ,
}, {
.name = "irq channel 1",
.flags = IORESOURCE_IRQ,
},
};
static struct mv_xor_channel_data orion_xor1_channels_data[2];
static struct mv_xor_platform_data orion_xor1_pdata = {
.channels = orion_xor1_channels_data,
};
static struct platform_device orion_xor1_shared = {
.name = MV_XOR_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
.resource = orion_xor1_shared_resources,
.dev = {
.dma_mask = &orion_xor_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_xor1_pdata,
},
};
void __init orion_xor1_init(unsigned long mapbase_low,
unsigned long mapbase_high,
unsigned long irq_0,
unsigned long irq_1)
{
orion_xor1_shared_resources[0].start = mapbase_low;
orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
orion_xor1_shared_resources[1].start = mapbase_high;
orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
orion_xor1_shared_resources[2].start = irq_0;
orion_xor1_shared_resources[2].end = irq_0;
orion_xor1_shared_resources[3].start = irq_1;
orion_xor1_shared_resources[3].end = irq_1;
dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
platform_device_register(&orion_xor1_shared);
}
/*****************************************************************************
* EHCI
****************************************************************************/
static struct orion_ehci_data orion_ehci_data;
static u64 ehci_dmamask = DMA_BIT_MASK(32);
/*****************************************************************************
* EHCI0
****************************************************************************/
static struct resource orion_ehci_resources[2];
static struct platform_device orion_ehci = {
.name = "orion-ehci",
.id = 0,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_ehci_data,
},
};
void __init orion_ehci_init(unsigned long mapbase,
unsigned long irq,
enum orion_ehci_phy_ver phy_version)
{
orion_ehci_data.phy_version = phy_version;
fill_resources_irq(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
irq);
platform_device_register(&orion_ehci);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
static struct resource orion_ehci_1_resources[2];
static struct platform_device orion_ehci_1 = {
.name = "orion-ehci",
.id = 1,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_ehci_data,
},
};
void __init orion_ehci_1_init(unsigned long mapbase,
unsigned long irq)
{
fill_resources_irq(&orion_ehci_1, orion_ehci_1_resources,
mapbase, SZ_4K - 1, irq);
platform_device_register(&orion_ehci_1);
}
/*****************************************************************************
* EHCI2
****************************************************************************/
static struct resource orion_ehci_2_resources[2];
static struct platform_device orion_ehci_2 = {
.name = "orion-ehci",
.id = 2,
.dev = {
.dma_mask = &ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &orion_ehci_data,
},
};
void __init orion_ehci_2_init(unsigned long mapbase,
unsigned long irq)
{
fill_resources_irq(&orion_ehci_2, orion_ehci_2_resources,
mapbase, SZ_4K - 1, irq);
platform_device_register(&orion_ehci_2);
}
/*****************************************************************************
* SATA
****************************************************************************/
static struct resource orion_sata_resources[2] = {
{
.name = "sata base",
}, {
.name = "sata irq",
},
};
static struct platform_device orion_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
unsigned long mapbase,
unsigned long irq)
{
orion_sata.dev.platform_data = sata_data;
fill_resources_irq(&orion_sata, orion_sata_resources,
mapbase, 0x5000 - 1, irq);
platform_device_register(&orion_sata);
}
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
static struct resource orion_crypto_resources[] = {
{
.name = "regs",
}, {
.name = "crypto interrupt",
}, {
.name = "sram",
.flags = IORESOURCE_MEM,
},
};
static struct platform_device orion_crypto = {
.name = "mv_crypto",
.id = -1,
};
void __init orion_crypto_init(unsigned long mapbase,
unsigned long srambase,
unsigned long sram_size,
unsigned long irq)
{
fill_resources_irq(&orion_crypto, orion_crypto_resources,
mapbase, 0xffff, irq);
orion_crypto.num_resources = 3;
orion_crypto_resources[2].start = srambase;
orion_crypto_resources[2].end = srambase + sram_size - 1;
platform_device_register(&orion_crypto);
}
| linux-master | arch/arm/plat-orion/common.c |
/*
* arch/arm/plat-orion/irq.c
*
* Marvell Orion SoC IRQ handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/exception.h>
#include <plat/irq.h>
#include <plat/orion-gpio.h>
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
/*
* Mask all interrupts initially.
*/
writel(0, maskaddr);
gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
handle_level_irq);
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
}
| linux-master | arch/arm/plat-orion/irq.c |
/*
* arch/arm/plat-orion/gpio.c
*
* Marvell Orion SoC GPIO handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define DEBUG
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/leds.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <plat/orion-gpio.h>
/*
* GPIO unit register offsets.
*/
#define GPIO_OUT_OFF 0x0000
#define GPIO_IO_CONF_OFF 0x0004
#define GPIO_BLINK_EN_OFF 0x0008
#define GPIO_IN_POL_OFF 0x000c
#define GPIO_DATA_IN_OFF 0x0010
#define GPIO_EDGE_CAUSE_OFF 0x0014
#define GPIO_EDGE_MASK_OFF 0x0018
#define GPIO_LEVEL_MASK_OFF 0x001c
struct orion_gpio_chip {
struct gpio_chip chip;
spinlock_t lock;
void __iomem *base;
unsigned long valid_input;
unsigned long valid_output;
int mask_offset;
int secondary_irq_base;
struct irq_domain *domain;
};
static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
{
return ochip->base + GPIO_OUT_OFF;
}
static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
{
return ochip->base + GPIO_IO_CONF_OFF;
}
static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
{
return ochip->base + GPIO_BLINK_EN_OFF;
}
static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
{
return ochip->base + GPIO_IN_POL_OFF;
}
static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
{
return ochip->base + GPIO_DATA_IN_OFF;
}
static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
{
return ochip->base + GPIO_EDGE_CAUSE_OFF;
}
static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
{
return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
}
static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
{
return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
}
static struct orion_gpio_chip orion_gpio_chips[2];
static int orion_gpio_chip_count;
static inline void
__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
{
u32 u;
u = readl(GPIO_IO_CONF(ochip));
if (input)
u |= 1 << pin;
else
u &= ~(1 << pin);
writel(u, GPIO_IO_CONF(ochip));
}
static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
{
u32 u;
u = readl(GPIO_OUT(ochip));
if (high)
u |= 1 << pin;
else
u &= ~(1 << pin);
writel(u, GPIO_OUT(ochip));
}
static inline void
__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
{
u32 u;
u = readl(GPIO_BLINK_EN(ochip));
if (blink)
u |= 1 << pin;
else
u &= ~(1 << pin);
writel(u, GPIO_BLINK_EN(ochip));
}
static inline int
orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
{
if (pin >= ochip->chip.ngpio)
goto err_out;
if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
goto err_out;
if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
goto err_out;
return 1;
err_out:
pr_debug("%s: invalid GPIO %d\n", __func__, pin);
return false;
}
/*
* GPIO primitives.
*/
static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
return 0;
return -EINVAL;
}
static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
unsigned long flags;
if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
return -EINVAL;
spin_lock_irqsave(&ochip->lock, flags);
__set_direction(ochip, pin, 1);
spin_unlock_irqrestore(&ochip->lock, flags);
return 0;
}
static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
int val;
if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
} else {
val = readl(GPIO_OUT(ochip));
}
return (val >> pin) & 1;
}
static int
orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
unsigned long flags;
if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
return -EINVAL;
spin_lock_irqsave(&ochip->lock, flags);
__set_blinking(ochip, pin, 0);
__set_level(ochip, pin, value);
__set_direction(ochip, pin, 0);
spin_unlock_irqrestore(&ochip->lock, flags);
return 0;
}
static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
unsigned long flags;
spin_lock_irqsave(&ochip->lock, flags);
__set_level(ochip, pin, value);
spin_unlock_irqrestore(&ochip->lock, flags);
}
static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
return irq_create_mapping(ochip->domain,
ochip->secondary_irq_base + pin);
}
/*
* Orion-specific GPIO API extensions.
*/
static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
{
int i;
for (i = 0; i < orion_gpio_chip_count; i++) {
struct orion_gpio_chip *ochip = orion_gpio_chips + i;
struct gpio_chip *chip = &ochip->chip;
if (pin >= chip->base && pin < chip->base + chip->ngpio)
return ochip;
}
return NULL;
}
void __init orion_gpio_set_unused(unsigned pin)
{
struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
if (ochip == NULL)
return;
pin -= ochip->chip.base;
/* Configure as output, drive low. */
__set_level(ochip, pin, 0);
__set_direction(ochip, pin, 0);
}
void __init orion_gpio_set_valid(unsigned pin, int mode)
{
struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
if (ochip == NULL)
return;
pin -= ochip->chip.base;
if (mode == 1)
mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
if (mode & GPIO_INPUT_OK)
__set_bit(pin, &ochip->valid_input);
else
__clear_bit(pin, &ochip->valid_input);
if (mode & GPIO_OUTPUT_OK)
__set_bit(pin, &ochip->valid_output);
else
__clear_bit(pin, &ochip->valid_output);
}
void orion_gpio_set_blink(unsigned pin, int blink)
{
struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
unsigned long flags;
if (ochip == NULL)
return;
spin_lock_irqsave(&ochip->lock, flags);
__set_level(ochip, pin & 31, 0);
__set_blinking(ochip, pin & 31, blink);
spin_unlock_irqrestore(&ochip->lock, flags);
}
EXPORT_SYMBOL(orion_gpio_set_blink);
#define ORION_BLINK_HALF_PERIOD 100 /* ms */
int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
unsigned long *delay_on, unsigned long *delay_off)
{
unsigned gpio = desc_to_gpio(desc);
if (delay_on && delay_off && !*delay_on && !*delay_off)
*delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
switch (state) {
case GPIO_LED_NO_BLINK_LOW:
case GPIO_LED_NO_BLINK_HIGH:
orion_gpio_set_blink(gpio, 0);
gpiod_set_raw_value(desc, state);
break;
case GPIO_LED_BLINK:
orion_gpio_set_blink(gpio, 1);
}
return 0;
}
EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
/*****************************************************************************
* Orion GPIO IRQ
*
* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
* value of the line or the opposite value.
*
* Level IRQ handlers: DATA_IN is used directly as cause register.
* Interrupt are masked by LEVEL_MASK registers.
* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
* Interrupt are masked by EDGE_MASK registers.
* Both-edge handlers: Similar to regular Edge handlers, but also swaps
* the polarity to catch the next line transaction.
* This is a race condition that might not perfectly
* work on some use cases.
*
* Every eight GPIO lines are grouped (OR'ed) before going up to main
* cause register.
*
* EDGE cause mask
* data-in /--------| |-----| |----\
* -----| |----- ---- to main cause reg
* X \----------------| |----/
* polarity LEVEL mask
*
****************************************************************************/
static int gpio_irq_set_type(struct irq_data *d, u32 type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
struct orion_gpio_chip *ochip = gc->private;
int pin;
u32 u;
pin = d->hwirq - ochip->secondary_irq_base;
u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
if (!u) {
return -EINVAL;
}
type &= IRQ_TYPE_SENSE_MASK;
if (type == IRQ_TYPE_NONE)
return -EINVAL;
/* Check if we need to change chip and handler */
if (!(ct->type & type))
if (irq_setup_alt_chip(d, type))
return -EINVAL;
/*
* Configure interrupt polarity.
*/
if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
u = readl(GPIO_IN_POL(ochip));
u &= ~(1 << pin);
writel(u, GPIO_IN_POL(ochip));
} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
u = readl(GPIO_IN_POL(ochip));
u |= 1 << pin;
writel(u, GPIO_IN_POL(ochip));
} else if (type == IRQ_TYPE_EDGE_BOTH) {
u32 v;
v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
/*
* set initial polarity based on current input level
*/
u = readl(GPIO_IN_POL(ochip));
if (v & (1 << pin))
u |= 1 << pin; /* falling */
else
u &= ~(1 << pin); /* rising */
writel(u, GPIO_IN_POL(ochip));
}
return 0;
}
static void gpio_irq_handler(struct irq_desc *desc)
{
struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
u32 cause, type;
int i;
if (ochip == NULL)
return;
cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
for (i = 0; i < ochip->chip.ngpio; i++) {
int irq;
irq = ochip->secondary_irq_base + i;
if (!(cause & (1 << i)))
continue;
type = irq_get_trigger_type(irq);
if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
/* Swap polarity (race with GPIO line) */
u32 polarity;
polarity = readl(GPIO_IN_POL(ochip));
polarity ^= 1 << i;
writel(polarity, GPIO_IN_POL(ochip));
}
generic_handle_irq(irq);
}
}
#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>
static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
const char *label;
int i;
out = readl_relaxed(GPIO_OUT(ochip));
io_conf = readl_relaxed(GPIO_IO_CONF(ochip));
blink = readl_relaxed(GPIO_BLINK_EN(ochip));
in_pol = readl_relaxed(GPIO_IN_POL(ochip));
data_in = readl_relaxed(GPIO_DATA_IN(ochip));
cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip));
edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
for_each_requested_gpio(chip, i, label) {
u32 msk;
bool is_out;
msk = 1 << i;
is_out = !(io_conf & msk);
seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
if (is_out) {
seq_printf(s, " out %s %s\n",
out & msk ? "hi" : "lo",
blink & msk ? "(blink )" : "");
continue;
}
seq_printf(s, " in %s (act %s) - IRQ",
(data_in ^ in_pol) & msk ? "hi" : "lo",
in_pol & msk ? "lo" : "hi");
if (!((edg_msk | lvl_msk) & msk)) {
seq_puts(s, " disabled\n");
continue;
}
if (edg_msk & msk)
seq_puts(s, " edge ");
if (lvl_msk & msk)
seq_puts(s, " level");
seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
}
}
#else
#define orion_gpio_dbg_show NULL
#endif
static void orion_gpio_unmask_irq(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
u32 reg_val;
u32 mask = d->mask;
irq_gc_lock(gc);
reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val |= mask;
irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_gc_unlock(gc);
}
static void orion_gpio_mask_irq(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
u32 mask = d->mask;
u32 reg_val;
irq_gc_lock(gc);
reg_val = irq_reg_readl(gc, ct->regs.mask);
reg_val &= ~mask;
irq_reg_writel(gc, reg_val, ct->regs.mask);
irq_gc_unlock(gc);
}
void __init orion_gpio_init(int gpio_base, int ngpio,
void __iomem *base, int mask_offset,
int secondary_irq_base,
int irqs[4])
{
struct orion_gpio_chip *ochip;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
char gc_label[16];
int i;
if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
return;
snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
orion_gpio_chip_count);
ochip = orion_gpio_chips + orion_gpio_chip_count;
ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
ochip->chip.request = orion_gpio_request;
ochip->chip.direction_input = orion_gpio_direction_input;
ochip->chip.get = orion_gpio_get;
ochip->chip.direction_output = orion_gpio_direction_output;
ochip->chip.set = orion_gpio_set;
ochip->chip.to_irq = orion_gpio_to_irq;
ochip->chip.base = gpio_base;
ochip->chip.ngpio = ngpio;
ochip->chip.can_sleep = 0;
ochip->chip.dbg_show = orion_gpio_dbg_show;
spin_lock_init(&ochip->lock);
ochip->base = (void __iomem *)base;
ochip->valid_input = 0;
ochip->valid_output = 0;
ochip->mask_offset = mask_offset;
ochip->secondary_irq_base = secondary_irq_base;
gpiochip_add_data(&ochip->chip, ochip);
/*
* Mask and clear GPIO interrupts.
*/
writel(0, GPIO_EDGE_CAUSE(ochip));
writel(0, GPIO_EDGE_MASK(ochip));
writel(0, GPIO_LEVEL_MASK(ochip));
/* Setup the interrupt handlers. Each chip can have up to 4
* interrupt handlers, with each handler dealing with 8 GPIO
* pins. */
for (i = 0; i < 4; i++) {
if (irqs[i]) {
irq_set_chained_handler_and_data(irqs[i],
gpio_irq_handler,
ochip);
}
}
gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
secondary_irq_base,
ochip->base, handle_level_irq);
gc->private = ochip;
ct = gc->chip_types;
ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
ct->chip.irq_mask = orion_gpio_mask_irq;
ct->chip.irq_unmask = orion_gpio_unmask_irq;
ct->chip.irq_set_type = gpio_irq_set_type;
ct->chip.name = ochip->chip.label;
ct++;
ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
ct->chip.irq_ack = irq_gc_ack_clr_bit;
ct->chip.irq_mask = orion_gpio_mask_irq;
ct->chip.irq_unmask = orion_gpio_unmask_irq;
ct->chip.irq_set_type = gpio_irq_set_type;
ct->handler = handle_edge_irq;
ct->chip.name = ochip->chip.label;
irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
/* Setup irq domain on top of the generic chip. */
ochip->domain = irq_domain_add_legacy(NULL,
ochip->chip.ngpio,
ochip->secondary_irq_base,
ochip->secondary_irq_base,
&irq_domain_simple_ops,
ochip);
if (!ochip->domain)
panic("%s: couldn't allocate irq domain (DT).\n",
ochip->chip.label);
orion_gpio_chip_count++;
}
| linux-master | arch/arm/plat-orion/gpio.c |
/*
* arch/arm/plat-orion/time.c
*
* Marvell Orion SoC timer handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Timer 0 is used as free-running clocksource, while timer 1 is
* used as clock_event_device.
*/
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
#include <plat/time.h>
#include <asm/delay.h>
/*
* MBus bridge block registers.
*/
#define BRIDGE_CAUSE_OFF 0x0110
#define BRIDGE_MASK_OFF 0x0114
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
/*
* Timer block registers.
*/
#define TIMER_CTRL_OFF 0x0000
#define TIMER0_EN 0x0001
#define TIMER0_RELOAD_EN 0x0002
#define TIMER1_EN 0x0004
#define TIMER1_RELOAD_EN 0x0008
#define TIMER0_RELOAD_OFF 0x0010
#define TIMER0_VAL_OFF 0x0014
#define TIMER1_RELOAD_OFF 0x0018
#define TIMER1_VAL_OFF 0x001c
/*
* SoC-specific data.
*/
static void __iomem *bridge_base;
static u32 bridge_timer1_clr_mask;
static void __iomem *timer_base;
/*
* Number of timer ticks per jiffy.
*/
static u32 ticks_per_jiffy;
/*
* Orion's sched_clock implementation. It has a resolution of
* at least 7.5ns (133MHz TCLK).
*/
static u64 notrace orion_read_sched_clock(void)
{
return ~readl(timer_base + TIMER0_VAL_OFF);
}
/*
* Clockevent handling.
*/
static int
orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
{
unsigned long flags;
u32 u;
if (delta == 0)
return -ETIME;
local_irq_save(flags);
/*
* Clear and enable clockevent timer interrupt.
*/
writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
u = readl(bridge_base + BRIDGE_MASK_OFF);
u |= BRIDGE_INT_TIMER1;
writel(u, bridge_base + BRIDGE_MASK_OFF);
/*
* Setup new clockevent timer value.
*/
writel(delta, timer_base + TIMER1_VAL_OFF);
/*
* Enable the timer.
*/
u = readl(timer_base + TIMER_CTRL_OFF);
u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
writel(u, timer_base + TIMER_CTRL_OFF);
local_irq_restore(flags);
return 0;
}
static int orion_clkevt_shutdown(struct clock_event_device *evt)
{
unsigned long flags;
u32 u;
local_irq_save(flags);
/* Disable timer */
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
/* Disable timer interrupt */
u = readl(bridge_base + BRIDGE_MASK_OFF);
writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
/* ACK pending timer interrupt */
writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
local_irq_restore(flags);
return 0;
}
static int orion_clkevt_set_periodic(struct clock_event_device *evt)
{
unsigned long flags;
u32 u;
local_irq_save(flags);
/* Setup timer to fire at 1/HZ intervals */
writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
/* Enable timer interrupt */
u = readl(bridge_base + BRIDGE_MASK_OFF);
writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
/* Enable timer */
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
local_irq_restore(flags);
return 0;
}
static struct clock_event_device orion_clkevt = {
.name = "orion_tick",
.features = CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_PERIODIC,
.rating = 300,
.set_next_event = orion_clkevt_next_event,
.set_state_shutdown = orion_clkevt_shutdown,
.set_state_periodic = orion_clkevt_set_periodic,
.set_state_oneshot = orion_clkevt_shutdown,
.tick_resume = orion_clkevt_shutdown,
};
static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
{
/*
* ACK timer interrupt and call event handler.
*/
writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
orion_clkevt.event_handler(&orion_clkevt);
return IRQ_HANDLED;
}
void __init
orion_time_set_base(void __iomem *_timer_base)
{
timer_base = _timer_base;
}
static unsigned long orion_delay_timer_read(void)
{
return ~readl(timer_base + TIMER0_VAL_OFF);
}
static struct delay_timer orion_delay_timer = {
.read_current_timer = orion_delay_timer_read,
};
void __init
orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
unsigned int irq, unsigned int tclk)
{
u32 u;
/*
* Set SoC-specific data.
*/
bridge_base = _bridge_base;
bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
ticks_per_jiffy = (tclk + HZ/2) / HZ;
orion_delay_timer.freq = tclk;
register_current_timer_delay(&orion_delay_timer);
/*
* Set scale and timer for sched_clock.
*/
sched_clock_register(orion_read_sched_clock, 32, tclk);
/*
* Setup free-running clocksource timer (interrupts
* disabled).
*/
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
u = readl(bridge_base + BRIDGE_MASK_OFF);
writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
tclk, 300, 32, clocksource_mmio_readl_down);
/*
* Setup clockevent timer (interrupt-driven).
*/
if (request_irq(irq, orion_timer_interrupt, IRQF_TIMER, "orion_tick",
NULL))
pr_err("Failed to request irq %u (orion_tick)\n", irq);
orion_clkevt.cpumask = cpumask_of(0);
clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
}
| linux-master | arch/arm/plat-orion/time.c |
/*
* arch/arm/plat-orion/pcie.c
*
* Marvell Orion SoC PCIe handling.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <plat/addr-map.h>
#include <linux/delay.h>
/*
* PCIe unit register offsets.
*/
#define PCIE_DEV_ID_OFF 0x0000
#define PCIE_CMD_OFF 0x0004
#define PCIE_DEV_REV_OFF 0x0008
#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
#define PCIE_HEADER_LOG_4_OFF 0x0128
#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
#define PCIE_WIN5_CTRL_OFF 0x1880
#define PCIE_WIN5_BASE_OFF 0x1884
#define PCIE_WIN5_REMAP_OFF 0x188c
#define PCIE_CONF_ADDR_OFF 0x18f8
#define PCIE_CONF_ADDR_EN 0x80000000
#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_STAT_OFF 0x1a04
#define PCIE_STAT_DEV_OFFS 20
#define PCIE_STAT_DEV_MASK 0x1f
#define PCIE_STAT_BUS_OFFS 8
#define PCIE_STAT_BUS_MASK 0xff
#define PCIE_STAT_LINK_DOWN 1
#define PCIE_DEBUG_CTRL 0x1a60
#define PCIE_DEBUG_SOFT_RESET (1<<20)
u32 orion_pcie_dev_id(void __iomem *base)
{
return readl(base + PCIE_DEV_ID_OFF) >> 16;
}
u32 orion_pcie_rev(void __iomem *base)
{
return readl(base + PCIE_DEV_REV_OFF) & 0xff;
}
int orion_pcie_link_up(void __iomem *base)
{
return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
}
int __init orion_pcie_x4_mode(void __iomem *base)
{
return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
}
int orion_pcie_get_local_bus_nr(void __iomem *base)
{
u32 stat = readl(base + PCIE_STAT_OFF);
return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
}
void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
{
u32 stat;
stat = readl(base + PCIE_STAT_OFF);
stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
stat |= nr << PCIE_STAT_BUS_OFFS;
writel(stat, base + PCIE_STAT_OFF);
}
void __init orion_pcie_reset(void __iomem *base)
{
u32 reg;
int i;
/*
* MV-S104860-U0, Rev. C:
* PCI Express Unit Soft Reset
* When set, generates an internal reset in the PCI Express unit.
* This bit should be cleared after the link is re-established.
*/
reg = readl(base + PCIE_DEBUG_CTRL);
reg |= PCIE_DEBUG_SOFT_RESET;
writel(reg, base + PCIE_DEBUG_CTRL);
for (i = 0; i < 20; i++) {
mdelay(10);
if (orion_pcie_link_up(base))
break;
}
reg &= ~(PCIE_DEBUG_SOFT_RESET);
writel(reg, base + PCIE_DEBUG_CTRL);
}
/*
* Setup PCIE BARs and Address Decode Wins:
* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
* WIN[0-3] -> DRAM bank[0-3]
*/
static void __init orion_pcie_setup_wins(void __iomem *base)
{
const struct mbus_dram_target_info *dram;
u32 size;
int i;
dram = mv_mbus_dram_info();
/*
* First, disable and clear BARs and windows.
*/
for (i = 1; i <= 2; i++) {
writel(0, base + PCIE_BAR_CTRL_OFF(i));
writel(0, base + PCIE_BAR_LO_OFF(i));
writel(0, base + PCIE_BAR_HI_OFF(i));
}
for (i = 0; i < 5; i++) {
writel(0, base + PCIE_WIN04_CTRL_OFF(i));
writel(0, base + PCIE_WIN04_BASE_OFF(i));
writel(0, base + PCIE_WIN04_REMAP_OFF(i));
}
writel(0, base + PCIE_WIN5_CTRL_OFF);
writel(0, base + PCIE_WIN5_BASE_OFF);
writel(0, base + PCIE_WIN5_REMAP_OFF);
/*
* Setup windows for DDR banks. Count total DDR size on the fly.
*/
size = 0;
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
writel(0, base + PCIE_WIN04_REMAP_OFF(i));
writel(((cs->size - 1) & 0xffff0000) |
(cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
base + PCIE_WIN04_CTRL_OFF(i));
size += cs->size;
}
/*
* Round up 'size' to the nearest power of two.
*/
if ((size & (size - 1)) != 0)
size = 1 << fls(size);
/*
* Setup BAR[1] to all DRAM banks.
*/
writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
writel(0, base + PCIE_BAR_HI_OFF(1));
writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
}
void __init orion_pcie_setup(void __iomem *base)
{
u16 cmd;
u32 mask;
/*
* Point PCIe unit MBUS decode windows to DRAM space.
*/
orion_pcie_setup_wins(base);
/*
* Master + slave enable.
*/
cmd = readw(base + PCIE_CMD_OFF);
cmd |= PCI_COMMAND_IO;
cmd |= PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER;
writew(cmd, base + PCIE_CMD_OFF);
/*
* Enable interrupt lines A-D.
*/
mask = readl(base + PCIE_MASK_OFF);
mask |= 0x0f000000;
writel(mask, base + PCIE_MASK_OFF);
}
int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
writel(PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
base + PCIE_CONF_ADDR_OFF);
*val = readl(base + PCIE_CONF_DATA_OFF);
if (size == 1)
*val = (*val >> (8 * (where & 3))) & 0xff;
else if (size == 2)
*val = (*val >> (8 * (where & 3))) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
writel(PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
base + PCIE_CONF_ADDR_OFF);
*val = readl(base + PCIE_CONF_DATA_OFF);
if (bus->number != orion_pcie_get_local_bus_nr(base) ||
PCI_FUNC(devfn) != 0)
*val = readl(base + PCIE_HEADER_LOG_4_OFF);
if (size == 1)
*val = (*val >> (8 * (where & 3))) & 0xff;
else if (size == 2)
*val = (*val >> (8 * (where & 3))) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
*val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where)));
if (size == 1)
*val = (*val >> (8 * (where & 3))) & 0xff;
else if (size == 2)
*val = (*val >> (8 * (where & 3))) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
u32 devfn, int where, int size, u32 val)
{
int ret = PCIBIOS_SUCCESSFUL;
writel(PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
base + PCIE_CONF_ADDR_OFF);
if (size == 4) {
writel(val, base + PCIE_CONF_DATA_OFF);
} else if (size == 2) {
writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
} else if (size == 1) {
writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
} else {
ret = PCIBIOS_BAD_REGISTER_NUMBER;
}
return ret;
}
| linux-master | arch/arm/plat-orion/pcie.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/common.c
*
* Code common to PXA168 processor lines
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include "addr-map.h"
#include <linux/soc/mmp/cputype.h>
#include "common.h"
#define MMP_CHIPID CIU_REG(0x00)
unsigned int mmp_chip_id;
EXPORT_SYMBOL(mmp_chip_id);
static struct map_desc standard_io_desc[] __initdata = {
{
.pfn = __phys_to_pfn(APB_PHYS_BASE),
.virtual = (unsigned long)APB_VIRT_BASE,
.length = APB_PHYS_SIZE,
.type = MT_DEVICE,
}, {
.pfn = __phys_to_pfn(AXI_PHYS_BASE),
.virtual = (unsigned long)AXI_VIRT_BASE,
.length = AXI_PHYS_SIZE,
.type = MT_DEVICE,
},
};
static struct map_desc mmp2_io_desc[] __initdata = {
{
.pfn = __phys_to_pfn(PGU_PHYS_BASE),
.virtual = (unsigned long)PGU_VIRT_BASE,
.length = PGU_PHYS_SIZE,
.type = MT_DEVICE,
},
};
void __init mmp_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
/* this is early, initialize mmp_chip_id here */
mmp_chip_id = __raw_readl(MMP_CHIPID);
}
void __init mmp2_map_io(void)
{
mmp_map_io();
iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
}
| linux-master | arch/arm/mach-mmp/common.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell MMP3 aka PXA2128 aka 88AP2128 support
*
* Copyright (C) 2019 Lubomir Rintel <[email protected]>
*/
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
#include "common.h"
static const char *const mmp3_dt_board_compat[] __initconst = {
"marvell,mmp3",
NULL,
};
DT_MACHINE_START(MMP2_DT, "Marvell MMP3")
.map_io = mmp2_map_io,
.dt_compat = mmp3_dt_board_compat,
.l2c_aux_val = 1 << L310_AUX_CTRL_FWA_SHIFT |
L310_AUX_CTRL_DATA_PREFETCH |
L310_AUX_CTRL_INSTR_PREFETCH,
.l2c_aux_mask = 0xc20fffff,
MACHINE_END
| linux-master | arch/arm/mach-mmp/mmp3.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/mmp2-dt.c
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <[email protected]>
*/
#include <linux/of_clk.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-tauros2.h>
#include "common.h"
static void __init mmp_init_time(void)
{
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
of_clk_init(NULL);
timer_probe();
}
static const char *const mmp2_dt_board_compat[] __initconst = {
"mrvl,mmp2",
NULL,
};
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
.map_io = mmp2_map_io,
.init_time = mmp_init_time,
.dt_compat = mmp2_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-mmp/mmp2-dt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/mmp-dt.c
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <[email protected]>
*/
#include <linux/of_clk.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-tauros2.h>
#include "common.h"
static const char *const pxa168_dt_board_compat[] __initconst = {
"mrvl,pxa168-aspenite",
NULL,
};
static const char *const pxa910_dt_board_compat[] __initconst = {
"mrvl,pxa910-dkb",
NULL,
};
static void __init mmp_init_time(void)
{
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
of_clk_init(NULL);
timer_probe();
}
DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
.map_io = mmp_map_io,
.init_time = mmp_init_time,
.dt_compat = pxa168_dt_board_compat,
MACHINE_END
DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
.map_io = mmp_map_io,
.init_time = mmp_init_time,
.dt_compat = pxa910_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-mmp/mmp-dt.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/time.c
*
* Support for clocksource and clockevents
*
* Copyright (C) 2008 Marvell International Ltd.
* All rights reserved.
*
* 2008-04-11: Jason Chagas <[email protected]>
* 2008-10-08: Bin Yang <[email protected]>
*
* The timers module actually includes three timers, each timer with up to
* three match comparators. Timer #0 is used here in free-running mode as
* the clock source, and match comparator #1 used as clock event device.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>
#include "regs-timers.h"
#include <linux/soc/mmp/cputype.h>
#define MAX_DELTA (0xfffffffe)
#define MIN_DELTA (16)
static void __iomem *mmp_timer_base;
/*
* Read the timer through the CVWR register. Delay is required after requesting
* a read. The CR register cannot be directly read due to metastability issues
* documented in the PXA168 software manual.
*/
static inline uint32_t timer_read(void)
{
uint32_t val;
int delay = 3;
__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
while (delay--)
val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
return val;
}
static u64 notrace mmp_read_sched_clock(void)
{
return timer_read();
}
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
/*
* Clear pending interrupt status.
*/
__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
/*
* Disable timer 0.
*/
__raw_writel(0x02, mmp_timer_base + TMR_CER);
c->event_handler(c);
return IRQ_HANDLED;
}
static int timer_set_next_event(unsigned long delta,
struct clock_event_device *dev)
{
unsigned long flags;
local_irq_save(flags);
/*
* Disable timer 0.
*/
__raw_writel(0x02, mmp_timer_base + TMR_CER);
/*
* Clear and enable timer match 0 interrupt.
*/
__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
/*
* Setup new clockevent timer value.
*/
__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
/*
* Enable timer 0.
*/
__raw_writel(0x03, mmp_timer_base + TMR_CER);
local_irq_restore(flags);
return 0;
}
static int timer_set_shutdown(struct clock_event_device *evt)
{
unsigned long flags;
local_irq_save(flags);
/* disable the matching interrupt */
__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
local_irq_restore(flags);
return 0;
}
static struct clock_event_device ckevt = {
.name = "clockevent",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_next_event = timer_set_next_event,
.set_state_shutdown = timer_set_shutdown,
.set_state_oneshot = timer_set_shutdown,
};
static u64 clksrc_read(struct clocksource *cs)
{
return timer_read();
}
static struct clocksource cksrc = {
.name = "clocksource",
.rating = 200,
.read = clksrc_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void __init timer_config(void)
{
uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
__raw_writel(ccr, mmp_timer_base + TMR_CCR);
/* set timer 0 to periodic mode, and timer 1 to free-running mode */
__raw_writel(0x2, mmp_timer_base + TMR_CMR);
__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
__raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
__raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
/* enable timer 1 counter */
__raw_writel(0x2, mmp_timer_base + TMR_CER);
}
static void __init mmp_timer_init(int irq, unsigned long rate)
{
timer_config();
sched_clock_register(mmp_read_sched_clock, 32, rate);
ckevt.cpumask = cpumask_of(0);
if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
"timer", &ckevt))
pr_err("Failed to request irq %d (timer)\n", irq);
clocksource_register_hz(&cksrc, rate);
clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
}
static int __init mmp_dt_init_timer(struct device_node *np)
{
struct clk *clk;
int irq, ret;
unsigned long rate;
clk = of_clk_get(np, 0);
if (!IS_ERR(clk)) {
ret = clk_prepare_enable(clk);
if (ret)
return ret;
rate = clk_get_rate(clk);
} else if (cpu_is_pj4()) {
rate = 6500000;
} else {
rate = 3250000;
}
irq = irq_of_parse_and_map(np, 0);
if (!irq)
return -EINVAL;
mmp_timer_base = of_iomap(np, 0);
if (!mmp_timer_base)
return -ENOMEM;
mmp_timer_init(irq, rate);
return 0;
}
TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
| linux-master | arch/arm/mach-mmp/time.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2019 Lubomir Rintel <[email protected]>
*/
#include <linux/io.h>
#include <asm/smp_scu.h>
#include <asm/smp.h>
#include "addr-map.h"
#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/*
* Apparently, the boot ROM on the second core spins on this
* register becoming non-zero and then jumps to the address written
* there. No IPIs involved.
*/
__raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
return 0;
}
static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
{
scu_enable(SCU_VIRT_BASE);
}
static const struct smp_operations mmp3_smp_ops __initconst = {
.smp_prepare_cpus = mmp3_smp_prepare_cpus,
.smp_boot_secondary = mmp3_boot_secondary,
};
CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
| linux-master | arch/arm/mach-mmp/platsmp.c |
// SPDX-License-Identifier: GPL-2.0
//
// Samsung's S3C64XX generic DMA support using amba-pl08x driver.
//
// Copyright (c) 2013 Tomasz Figa <[email protected]>
#include <linux/kernel.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl080.h>
#include <linux/amba/pl08x.h>
#include <linux/of.h>
#include "cpu.h"
#include "irqs.h"
#include "map.h"
#include "regs-sys-s3c64xx.h"
static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd)
{
return cd->min_signal;
}
static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch)
{
}
/*
* DMA0
*/
static struct pl08x_channel_data s3c64xx_dma0_info[] = {
{
.bus_id = "uart0_tx",
.min_signal = 0,
.max_signal = 0,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart0_rx",
.min_signal = 1,
.max_signal = 1,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart1_tx",
.min_signal = 2,
.max_signal = 2,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart1_rx",
.min_signal = 3,
.max_signal = 3,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart2_tx",
.min_signal = 4,
.max_signal = 4,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart2_rx",
.min_signal = 5,
.max_signal = 5,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart3_tx",
.min_signal = 6,
.max_signal = 6,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "uart3_rx",
.min_signal = 7,
.max_signal = 7,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "pcm0_tx",
.min_signal = 8,
.max_signal = 8,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "pcm0_rx",
.min_signal = 9,
.max_signal = 9,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "i2s0_tx",
.min_signal = 10,
.max_signal = 10,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "i2s0_rx",
.min_signal = 11,
.max_signal = 11,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "spi0_tx",
.min_signal = 12,
.max_signal = 12,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "spi0_rx",
.min_signal = 13,
.max_signal = 13,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "i2s2_tx",
.min_signal = 14,
.max_signal = 14,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "i2s2_rx",
.min_signal = 15,
.max_signal = 15,
.periph_buses = PL08X_AHB2,
}
};
static const struct dma_slave_map s3c64xx_dma0_slave_map[] = {
{ "s3c6400-uart.0", "tx", &s3c64xx_dma0_info[0] },
{ "s3c6400-uart.0", "rx", &s3c64xx_dma0_info[1] },
{ "s3c6400-uart.1", "tx", &s3c64xx_dma0_info[2] },
{ "s3c6400-uart.1", "rx", &s3c64xx_dma0_info[3] },
{ "s3c6400-uart.2", "tx", &s3c64xx_dma0_info[4] },
{ "s3c6400-uart.2", "rx", &s3c64xx_dma0_info[5] },
{ "s3c6400-uart.3", "tx", &s3c64xx_dma0_info[6] },
{ "s3c6400-uart.3", "rx", &s3c64xx_dma0_info[7] },
{ "samsung-pcm.0", "tx", &s3c64xx_dma0_info[8] },
{ "samsung-pcm.0", "rx", &s3c64xx_dma0_info[9] },
{ "samsung-i2s.0", "tx", &s3c64xx_dma0_info[10] },
{ "samsung-i2s.0", "rx", &s3c64xx_dma0_info[11] },
{ "s3c6410-spi.0", "tx", &s3c64xx_dma0_info[12] },
{ "s3c6410-spi.0", "rx", &s3c64xx_dma0_info[13] },
{ "samsung-i2s.2", "tx", &s3c64xx_dma0_info[14] },
{ "samsung-i2s.2", "rx", &s3c64xx_dma0_info[15] },
};
struct pl08x_platform_data s3c64xx_dma0_plat_data = {
.memcpy_burst_size = PL08X_BURST_SZ_4,
.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
.memcpy_prot_buff = true,
.memcpy_prot_cache = true,
.lli_buses = PL08X_AHB1,
.mem_buses = PL08X_AHB1,
.get_xfer_signal = pl08x_get_xfer_signal,
.put_xfer_signal = pl08x_put_xfer_signal,
.slave_channels = s3c64xx_dma0_info,
.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
.slave_map = s3c64xx_dma0_slave_map,
.slave_map_len = ARRAY_SIZE(s3c64xx_dma0_slave_map),
};
static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0,
0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
/*
* DMA1
*/
static struct pl08x_channel_data s3c64xx_dma1_info[] = {
{
.bus_id = "pcm1_tx",
.min_signal = 0,
.max_signal = 0,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "pcm1_rx",
.min_signal = 1,
.max_signal = 1,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "i2s1_tx",
.min_signal = 2,
.max_signal = 2,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "i2s1_rx",
.min_signal = 3,
.max_signal = 3,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "spi1_tx",
.min_signal = 4,
.max_signal = 4,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "spi1_rx",
.min_signal = 5,
.max_signal = 5,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "ac97_out",
.min_signal = 6,
.max_signal = 6,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "ac97_in",
.min_signal = 7,
.max_signal = 7,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "ac97_mic",
.min_signal = 8,
.max_signal = 8,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "pwm",
.min_signal = 9,
.max_signal = 9,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "irda",
.min_signal = 10,
.max_signal = 10,
.periph_buses = PL08X_AHB2,
}, {
.bus_id = "external",
.min_signal = 11,
.max_signal = 11,
.periph_buses = PL08X_AHB2,
},
};
static const struct dma_slave_map s3c64xx_dma1_slave_map[] = {
{ "samsung-pcm.1", "tx", &s3c64xx_dma1_info[0] },
{ "samsung-pcm.1", "rx", &s3c64xx_dma1_info[1] },
{ "samsung-i2s.1", "tx", &s3c64xx_dma1_info[2] },
{ "samsung-i2s.1", "rx", &s3c64xx_dma1_info[3] },
{ "s3c6410-spi.1", "tx", &s3c64xx_dma1_info[4] },
{ "s3c6410-spi.1", "rx", &s3c64xx_dma1_info[5] },
};
struct pl08x_platform_data s3c64xx_dma1_plat_data = {
.memcpy_burst_size = PL08X_BURST_SZ_4,
.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
.memcpy_prot_buff = true,
.memcpy_prot_cache = true,
.lli_buses = PL08X_AHB1,
.mem_buses = PL08X_AHB1,
.get_xfer_signal = pl08x_get_xfer_signal,
.put_xfer_signal = pl08x_put_xfer_signal,
.slave_channels = s3c64xx_dma1_info,
.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
.slave_map = s3c64xx_dma1_slave_map,
.slave_map_len = ARRAY_SIZE(s3c64xx_dma1_slave_map),
};
static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0,
0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
static int __init s3c64xx_pl080_init(void)
{
if (!soc_is_s3c64xx())
return 0;
/* Set all DMA configuration to be DMA, not SDMA */
writel(0xffffff, S3C64XX_SDMA_SEL);
if (of_have_populated_dt())
return 0;
amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
return 0;
}
arch_initcall(s3c64xx_pl080_init);
| linux-master | arch/arm/mach-s3c/pl080.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2010 Ben Dooks <ben-linux <at> fluff.org>
//
// Helper for platform data setting
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include "devs.h"
#include "sdhci.h"
void __init *s3c_set_platdata(void *pd, size_t pdsize,
struct platform_device *pdev)
{
void *npd;
if (!pd) {
/* too early to use dev_name(), may not be registered */
printk(KERN_ERR "%s: no platform data supplied\n", pdev->name);
return NULL;
}
npd = kmemdup(pd, pdsize, GFP_KERNEL);
if (!npd)
return NULL;
pdev->dev.platform_data = npd;
return npd;
}
void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
struct s3c_sdhci_platdata *set)
{
set->cd_type = pd->cd_type;
set->ext_cd_init = pd->ext_cd_init;
set->ext_cd_cleanup = pd->ext_cd_cleanup;
set->ext_cd_gpio = pd->ext_cd_gpio;
set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
if (pd->max_width)
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->host_caps)
set->host_caps |= pd->host_caps;
if (pd->host_caps2)
set->host_caps2 |= pd->host_caps2;
if (pd->pm_caps)
set->pm_caps |= pd->pm_caps;
}
| linux-master | arch/arm/mach-s3c/platformdata.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2011 Samsung Electronics Ltd.
// http://www.samsung.com/
#include <linux/gpio.h>
#include <linux/platform_data/spi-s3c64xx.h>
#include "gpio-cfg.h"
#include "gpio-samsung.h"
#ifdef CONFIG_S3C64XX_DEV_SPI0
int s3c64xx_spi0_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
#endif
| linux-master | arch/arm/mach-s3c/setup-spi-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Common Codes for S3C64XX machines
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/io.h>
#include <linux/clk/samsung.h>
#include <linux/dma-mapping.h>
#include <linux/irq.h>
#include <linux/irqchip/arm-vic.h>
#include <clocksource/samsung_pwm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include "map.h"
#include "irqs.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include "cpu.h"
#include "devs.h"
#include "pm.h"
#include "gpio-cfg.h"
#include "pwm-core.h"
#include "regs-irqtype.h"
#include "s3c64xx.h"
#include "irq-uart-s3c64xx.h"
/* External clock frequency */
static unsigned long xtal_f __ro_after_init = 12000000;
static unsigned long xusbxti_f __ro_after_init = 48000000;
void __init s3c64xx_set_xtal_freq(unsigned long freq)
{
xtal_f = freq;
}
void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
{
xusbxti_f = freq;
}
/* uart registration process */
static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
}
/* table of supported CPUs */
static const char name_s3c6410[] = "S3C6410";
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = S3C6410_CPU_ID,
.idmask = S3C64XX_CPU_MASK,
.map_io = s3c6410_map_io,
.init_uarts = s3c64xx_init_uarts,
.init = s3c6410_init,
.name = name_s3c6410,
},
};
/* minimal IO mapping */
/*
* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
#define UART_OFFS (S3C_PA_UART & 0xfffff)
static struct map_desc s3c_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_MEM,
.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC0,
.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)VA_VIC1,
.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_TIMER,
.pfn = __phys_to_pfn(S3C_PA_TIMER),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C64XX_VA_GPIO,
.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C64XX_VA_MODEM,
.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_WATCHDOG,
.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
.length = SZ_1K,
.type = MT_DEVICE,
},
};
static struct bus_type s3c64xx_subsys = {
.name = "s3c64xx-core",
.dev_name = "s3c64xx-core",
};
static struct device s3c64xx_dev = {
.bus = &s3c64xx_subsys,
};
static struct samsung_pwm_variant s3c64xx_pwm_variant = {
.bits = 32,
.div_base = 0,
.has_tint_cstat = true,
.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
};
void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
enum s3c64xx_timer_mode source)
{
s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
void __init s3c64xx_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
};
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &s3c64xx_pwm_variant);
}
/* read cpu identification code */
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
{
/* initialise the io descriptors we need for initialisation */
iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
iotable_init(mach_desc, size);
/* detect cpu id */
s3c64xx_init_cpu();
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
}
static __init int s3c64xx_dev_init(void)
{
/* Not applicable when using DT. */
if (of_have_populated_dt() || !soc_is_s3c64xx())
return 0;
subsys_system_register(&s3c64xx_subsys, NULL);
return device_register(&s3c64xx_dev);
}
core_initcall(s3c64xx_dev_init);
/*
* setup the sources the vic should advertise resume
* for, even though it is not doing the wake
* (set_irq_wake needs to be valid)
*/
#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
}
#define eint_offset(irq) ((irq) - IRQ_EINT(0))
#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
static inline void s3c_irq_eint_mask(struct irq_data *data)
{
u32 mask;
mask = __raw_readl(S3C64XX_EINT0MASK);
mask |= (u32)data->chip_data;
__raw_writel(mask, S3C64XX_EINT0MASK);
}
static void s3c_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
mask = __raw_readl(S3C64XX_EINT0MASK);
mask &= ~((u32)data->chip_data);
__raw_writel(mask, S3C64XX_EINT0MASK);
}
static inline void s3c_irq_eint_ack(struct irq_data *data)
{
__raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
}
static void s3c_irq_eint_maskack(struct irq_data *data)
{
/* compiler should in-line these */
s3c_irq_eint_mask(data);
s3c_irq_eint_ack(data);
}
static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = eint_offset(data->irq);
int pin, pin_val;
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
void __iomem *reg;
if (offs > 27)
return -EINVAL;
if (offs <= 15)
reg = S3C64XX_EINT0CON0;
else
reg = S3C64XX_EINT0CON1;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S3C2410_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S3C2410_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S3C2410_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S3C2410_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S3C2410_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
if (offs <= 15)
shift = (offs / 2) * 4;
else
shift = ((offs - 16) / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(reg);
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, reg);
/* set the GPIO pin appropriately */
if (offs < 16) {
pin = S3C64XX_GPN(offs);
pin_val = S3C_GPIO_SFN(2);
} else if (offs < 23) {
pin = S3C64XX_GPL(offs + 8 - 16);
pin_val = S3C_GPIO_SFN(3);
} else {
pin = S3C64XX_GPM(offs - 23);
pin_val = S3C_GPIO_SFN(3);
}
s3c_gpio_cfgpin(pin, pin_val);
return 0;
}
static struct irq_chip s3c_irq_eint = {
.name = "s3c-eint",
.irq_mask = s3c_irq_eint_mask,
.irq_unmask = s3c_irq_eint_unmask,
.irq_mask_ack = s3c_irq_eint_maskack,
.irq_ack = s3c_irq_eint_ack,
.irq_set_type = s3c_irq_eint_set_type,
.irq_set_wake = s3c_irqext_wake,
};
/* s3c_irq_demux_eint
*
* This function demuxes the IRQ from the group0 external interrupts,
* from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
* the specific handlers s3c_irq_demux_eintX_Y.
*/
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
{
u32 status = __raw_readl(S3C64XX_EINT0PEND);
u32 mask = __raw_readl(S3C64XX_EINT0MASK);
unsigned int irq;
status &= ~mask;
status >>= start;
status &= (1 << (end - start + 1)) - 1;
for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
if (status & 1)
generic_handle_irq(irq);
status >>= 1;
}
}
static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
{
s3c_irq_demux_eint(0, 3);
}
static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
{
s3c_irq_demux_eint(4, 11);
}
static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
{
s3c_irq_demux_eint(12, 19);
}
static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
{
s3c_irq_demux_eint(20, 27);
}
static int __init s3c64xx_init_irq_eint(void)
{
int irq;
/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
if (of_have_populated_dt() || !soc_is_s3c64xx())
return -ENODEV;
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
irq_clear_status_flags(irq, IRQ_NOREQUEST);
}
irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
return 0;
}
arch_initcall(s3c64xx_init_irq_eint);
#ifndef CONFIG_COMPILE_TEST
#pragma message "The platform is deprecated and scheduled for removal. " \
"Please reach to the maintainers of the platform " \
"and [email protected] if you still use it." \
"Without such feedback, the platform will be removed after 2024."
#endif
| linux-master | arch/arm/mach-s3c/s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
// Base Samsung platform device definitions
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/dma-mapping.h>
#include <linux/fb.h>
#include <linux/gfp.h>
#include <linux/mmc/host.h>
#include <linux/ioport.h>
#include <linux/sizes.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "irqs.h"
#include "map.h"
#include "gpio-samsung.h"
#include "gpio-cfg.h"
#include "cpu.h"
#include "devs.h"
#include "fb.h"
#include <linux/platform_data/i2c-s3c2410.h>
#include "keypad.h"
#include "pwm-core.h"
#include "sdhci.h"
#include "usb-phy.h"
#include <linux/platform_data/asoc-s3c.h>
#include <linux/platform_data/spi-s3c64xx.h>
#define samsung_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
/* FB */
#ifdef CONFIG_S3C_DEV_FB
static struct resource s3c_fb_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
[1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
[2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
[3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
};
struct platform_device s3c_device_fb = {
.name = "s3c-fb",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_fb_resource),
.resource = s3c_fb_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
{
s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
&s3c_device_fb);
}
#endif /* CONFIG_S3C_DEV_FB */
/* HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC
static struct resource s3c_hsmmc_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
};
struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc0 = {
.name = "s3c-sdhci",
.id = 0,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s3c_hsmmc0_def_platdata,
},
};
void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
{
s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
}
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1
static struct resource s3c_hsmmc1_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
};
struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc1 = {
.name = "s3c-sdhci",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
.resource = s3c_hsmmc1_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s3c_hsmmc1_def_platdata,
},
};
void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
{
s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
}
#endif /* CONFIG_S3C_DEV_HSMMC1 */
/* HSMMC2 */
#ifdef CONFIG_S3C_DEV_HSMMC2
static struct resource s3c_hsmmc2_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
};
struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc2 = {
.name = "s3c-sdhci",
.id = 2,
.num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
.resource = s3c_hsmmc2_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s3c_hsmmc2_def_platdata,
},
};
void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
{
s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
}
#endif /* CONFIG_S3C_DEV_HSMMC2 */
#ifdef CONFIG_S3C_DEV_HSMMC3
static struct resource s3c_hsmmc3_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
};
struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc3 = {
.name = "s3c-sdhci",
.id = 3,
.num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
.resource = s3c_hsmmc3_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s3c_hsmmc3_def_platdata,
},
};
void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
{
s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
}
#endif /* CONFIG_S3C_DEV_HSMMC3 */
/* I2C */
static struct resource s3c_i2c0_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_IIC),
};
struct platform_device s3c_device_i2c0 = {
.name = "s3c2410-i2c",
.id = 0,
.num_resources = ARRAY_SIZE(s3c_i2c0_resource),
.resource = s3c_i2c0_resource,
};
struct s3c2410_platform_i2c default_i2c_data __initdata = {
.flags = 0,
.slave_addr = 0x10,
.frequency = 100*1000,
.sda_delay = 100,
};
void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd) {
pd = &default_i2c_data;
pd->bus_num = 0;
}
npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c0);
if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c0_cfg_gpio;
}
#ifdef CONFIG_S3C_DEV_I2C1
static struct resource s3c_i2c1_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
[1] = DEFINE_RES_IRQ(IRQ_IIC1),
};
struct platform_device s3c_device_i2c1 = {
.name = "s3c2410-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_i2c1_resource),
.resource = s3c_i2c1_resource,
};
void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd) {
pd = &default_i2c_data;
pd->bus_num = 1;
}
npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_i2c1);
if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c1_cfg_gpio;
}
#endif /* CONFIG_S3C_DEV_I2C1 */
/* KEYPAD */
#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
static struct resource samsung_keypad_resources[] = {
[0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
[1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
};
struct platform_device samsung_device_keypad = {
.name = "samsung-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(samsung_keypad_resources),
.resource = samsung_keypad_resources,
};
void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
{
struct samsung_keypad_platdata *npd;
npd = s3c_set_platdata(pd, sizeof(*npd), &samsung_device_keypad);
if (!npd->cfg_gpio)
npd->cfg_gpio = samsung_keypad_cfg_gpio;
}
#endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
/* PWM Timer */
#ifdef CONFIG_SAMSUNG_DEV_PWM
static struct resource samsung_pwm_resource[] = {
DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K),
};
struct platform_device samsung_device_pwm = {
.name = "samsung-pwm",
.id = -1,
.num_resources = ARRAY_SIZE(samsung_pwm_resource),
.resource = samsung_pwm_resource,
};
void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd)
{
samsung_device_pwm.dev.platform_data = pd;
}
#endif /* CONFIG_SAMSUNG_DEV_PWM */
/* USB */
#ifdef CONFIG_S3C_DEV_USB_HOST
static struct resource s3c_usb_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
[1] = DEFINE_RES_IRQ(IRQ_USBH),
};
struct platform_device s3c_device_ohci = {
.name = "s3c2410-ohci",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_usb_resource),
.resource = s3c_usb_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
#endif /* CONFIG_S3C_DEV_USB_HOST */
/* USB HSOTG */
#ifdef CONFIG_S3C_DEV_USB_HSOTG
static struct resource s3c_usb_hsotg_resources[] = {
[0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
[1] = DEFINE_RES_IRQ(IRQ_OTG),
};
struct platform_device s3c_device_usb_hsotg = {
.name = "s3c-hsotg",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
.resource = s3c_usb_hsotg_resources,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init dwc2_hsotg_set_platdata(struct dwc2_hsotg_plat *pd)
{
struct dwc2_hsotg_plat *npd;
npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_usb_hsotg);
if (!npd->phy_init)
npd->phy_init = s3c_usb_phy_init;
if (!npd->phy_exit)
npd->phy_exit = s3c_usb_phy_exit;
}
#endif /* CONFIG_S3C_DEV_USB_HSOTG */
#ifdef CONFIG_S3C64XX_DEV_SPI0
static struct resource s3c64xx_spi0_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
[1] = DEFINE_RES_IRQ(IRQ_SPI0),
};
struct platform_device s3c64xx_device_spi0 = {
.name = "s3c6410-spi",
.id = 0,
.num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
.resource = s3c64xx_spi0_resource,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void __init s3c64xx_spi0_set_platdata(int src_clk_nr, int num_cs)
{
struct s3c64xx_spi_info pd;
/* Reject invalid configuration */
if (!num_cs || src_clk_nr < 0) {
pr_err("%s: Invalid SPI configuration\n", __func__);
return;
}
pd.num_cs = num_cs;
pd.src_clk_nr = src_clk_nr;
pd.cfg_gpio = s3c64xx_spi0_cfg_gpio;
s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
}
#endif /* CONFIG_S3C64XX_DEV_SPI0 */
| linux-master | arch/arm/mach-s3c/devs.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2010 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// GPIO configuration for S3C64XX KeyPad device
#include <linux/gpio.h>
#include "gpio-cfg.h"
#include "keypad.h"
#include "gpio-samsung.h"
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3));
/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
}
| linux-master | arch/arm/mach-s3c/setup-keypad-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
// Samsung CPU Support
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include "map-base.h"
#include "cpu.h"
unsigned long samsung_cpu_id;
void __init s3c64xx_init_cpu(void)
{
samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118);
if (!samsung_cpu_id) {
/*
* S3C6400 has the ID register in a different place,
* and needs a write before it can be read.
*/
writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
}
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
pr_err("The platform is deprecated and scheduled for removal. Please reach to the maintainers of the platform and [email protected] if you still use it. Without such feedback, the platform will be removed after 2022.\n");
}
| linux-master | arch/arm/mach-s3c/cpu.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// S3C series CPU initialisation
/*
* NOTE: Code in this file is not used on S3C64xx when booting with
* Device Tree support.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "cpu.h"
#include "devs.h"
static struct cpu_table *cpu;
static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
struct cpu_table *tab,
unsigned int count)
{
for (; count != 0; count--, tab++) {
if ((idcode & tab->idmask) == (tab->idcode & tab->idmask))
return tab;
}
return NULL;
}
void __init s3c_init_cpu(unsigned long idcode,
struct cpu_table *cputab, unsigned int cputab_size)
{
cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
if (cpu == NULL) {
printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
panic("Unknown S3C24XX CPU");
}
printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
if (cpu->init == NULL) {
printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
panic("Unsupported Samsung CPU");
}
if (cpu->map_io)
cpu->map_io();
pr_err("The platform is deprecated and scheduled for removal. Please reach to the maintainers of the platform and [email protected] if you still use it. Without such feedback, the platform will be removed after 2022.\n");
}
/* uart management */
#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
static int nr_uarts __initdata = 0;
#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
#endif
/* s3c24xx_init_uartdevs
*
* copy the specified platform data and configuration into our central
* set of devices, before the data is thrown away after the init process.
*
* This also fills in the array passed to the serial driver for the
* early initialisation of the console.
*/
void __init s3c24xx_init_uartdevs(char *name,
struct s3c24xx_uart_resources *res,
struct s3c2410_uartcfg *cfg, int no)
{
#ifdef CONFIG_SERIAL_SAMSUNG_UARTS
struct platform_device *platdev;
struct s3c2410_uartcfg *cfgptr = uart_cfgs;
struct s3c24xx_uart_resources *resp;
int uart;
memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
platdev = s3c24xx_uart_src[cfgptr->hwport];
resp = res + cfgptr->hwport;
s3c24xx_uart_devs[uart] = platdev;
platdev->name = name;
platdev->resource = resp->resources;
platdev->num_resources = resp->nr_resources;
platdev->dev.platform_data = cfgptr;
}
nr_uarts = no;
#endif
}
void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
if (cpu == NULL)
return;
if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) {
printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
} else
(cpu->init_uarts)(cfg, no);
}
#endif
static int __init s3c_arch_init(void)
{
int ret;
/* init is only needed for ATAGS based platforms */
if (!IS_ENABLED(CONFIG_ATAGS))
return 0;
// do the correct init for cpu
if (cpu == NULL) {
/* Not needed when booting with device tree. */
if (of_have_populated_dt())
return 0;
panic("s3c_arch_init: NULL cpu\n");
}
ret = (cpu->init)();
if (ret != 0)
return ret;
#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
#endif
return ret;
}
arch_initcall(s3c_arch_init);
| linux-master | arch/arm/mach-s3c/init.c |
// SPDX-License-Identifier: GPL-2.0
//
// Speyside modules for Cragganmore - board data probing
//
// Copyright 2011 Wolfson Microelectronics plc
// Mark Brown <[email protected]>
#include <linux/export.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/gpio/machine.h>
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/arizona/pdata.h>
#include <linux/regulator/machine.h>
#include <sound/wm0010.h>
#include <sound/wm2200.h>
#include <sound/wm5100.h>
#include <sound/wm8996.h>
#include <sound/wm8962.h>
#include <sound/wm9081.h>
#include <linux/platform_data/spi-s3c64xx.h>
#include "cpu.h"
#include "irqs.h"
#include "crag6410.h"
static struct wm0010_pdata wm0010_pdata = {
.gpio_reset = S3C64XX_GPN(6),
.reset_active_high = 1, /* Active high for Glenfarclas Rev 2 */
};
static struct spi_board_info wm1253_devs[] = {
[0] = {
.modalias = "wm0010",
.max_speed_hz = 26 * 1000 * 1000,
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
.irq = S3C_EINT(4),
.platform_data = &wm0010_pdata,
},
};
static struct spi_board_info balblair_devs[] = {
[0] = {
.modalias = "wm0010",
.max_speed_hz = 26 * 1000 * 1000,
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
.irq = S3C_EINT(4),
.platform_data = &wm0010_pdata,
},
};
static struct wm5100_pdata wm5100_pdata = {
.ldo_ena = S3C64XX_GPN(7),
.irq_flags = IRQF_TRIGGER_HIGH,
.gpio_base = CODEC_GPIO_BASE,
.in_mode = {
WM5100_IN_DIFF,
WM5100_IN_DIFF,
WM5100_IN_DIFF,
WM5100_IN_SE,
},
.hp_pol = CODEC_GPIO_BASE + 3,
.jack_modes = {
{ WM5100_MICDET_MICBIAS3, 0, 0 },
{ WM5100_MICDET_MICBIAS2, 1, 1 },
},
.gpio_defaults = {
0,
0,
0,
0,
0x2, /* IRQ: CMOS output */
0x3, /* CLKOUT: CMOS output */
},
};
static struct wm8996_retune_mobile_config wm8996_retune[] = {
{
.name = "Sub LPF",
.rate = 48000,
.regs = {
0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
},
},
{
.name = "Sub HPF",
.rate = 48000,
.regs = {
0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
},
},
};
static struct wm8996_pdata wm8996_pdata __initdata = {
.ldo_ena = S3C64XX_GPN(7),
.gpio_base = CODEC_GPIO_BASE,
.micdet_def = 1,
.inl_mode = WM8996_DIFFERRENTIAL_1,
.inr_mode = WM8996_DIFFERRENTIAL_1,
.irq_flags = IRQF_TRIGGER_RISING,
.gpio_default = {
0x8001, /* GPIO1 == ADCLRCLK1 */
0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
0x0141, /* GPIO3 == HP_SEL */
0x0002, /* GPIO4 == IRQ */
0x020e, /* GPIO5 == CLKOUT */
},
.retune_mobile_cfgs = wm8996_retune,
.num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
};
static struct wm8962_pdata wm8962_pdata __initdata = {
.gpio_init = {
0,
WM8962_GPIO_FN_OPCLK,
WM8962_GPIO_FN_DMICCLK,
0,
0x8000 | WM8962_GPIO_FN_DMICDAT,
WM8962_GPIO_FN_IRQ, /* Open drain mode */
},
.in4_dc_measure = true,
};
static struct wm9081_pdata wm9081_pdata __initdata = {
.irq_high = false,
.irq_cmos = false,
};
static const struct i2c_board_info wm1254_devs[] = {
{ I2C_BOARD_INFO("wm8996", 0x1a),
.platform_data = &wm8996_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
{ I2C_BOARD_INFO("wm9081", 0x6c),
.platform_data = &wm9081_pdata, },
};
static const struct i2c_board_info wm1255_devs[] = {
{ I2C_BOARD_INFO("wm5100", 0x1a),
.platform_data = &wm5100_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
{ I2C_BOARD_INFO("wm9081", 0x6c),
.platform_data = &wm9081_pdata, },
};
static const struct i2c_board_info wm1259_devs[] = {
{ I2C_BOARD_INFO("wm8962", 0x1a),
.platform_data = &wm8962_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
},
};
static struct regulator_init_data wm8994_ldo1 = {
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data wm8994_ldo2 = {
.supply_regulator = "WALLVDD",
};
static struct wm8994_pdata wm8994_pdata = {
.gpio_base = CODEC_GPIO_BASE,
.micb2_delay = 150,
.gpio_defaults = {
0x3, /* IRQ out, active high, CMOS */
},
.ldo = {
{ .init_data = &wm8994_ldo1, },
{ .init_data = &wm8994_ldo2, },
},
};
static const struct i2c_board_info wm1277_devs[] = {
{ I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */
.platform_data = &wm8994_pdata,
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
.dev_name = "wm8958",
},
};
static struct gpiod_lookup_table wm8994_gpiod_table = {
.dev_id = "i2c-wm8958", /* I2C device name */
.table = {
GPIO_LOOKUP("GPION", 6,
"wlf,ldo1ena", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("GPION", 4,
"wlf,ldo2ena", GPIO_ACTIVE_HIGH),
{ },
},
};
static struct arizona_pdata wm5102_reva_pdata = {
.gpio_base = CODEC_GPIO_BASE,
.irq_flags = IRQF_TRIGGER_HIGH,
.micd_pol_gpio = CODEC_GPIO_BASE + 4,
.micd_rate = 6,
.gpio_defaults = {
[2] = 0x10000, /* AIF3TXLRCLK */
[3] = 0x4, /* OPCLK */
},
};
static struct spi_board_info wm5102_reva_spi_devs[] = {
[0] = {
.modalias = "wm5102",
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
.irq = GLENFARCLAS_PMIC_IRQ_BASE +
WM831X_IRQ_GPIO_2,
.platform_data = &wm5102_reva_pdata,
},
};
static struct gpiod_lookup_table wm5102_reva_gpiod_table = {
.dev_id = "spi0.1", /* SPI device name */
.table = {
GPIO_LOOKUP("GPION", 7,
"wlf,ldoena", GPIO_ACTIVE_HIGH),
{ },
},
};
static struct arizona_pdata wm5102_pdata = {
.gpio_base = CODEC_GPIO_BASE,
.irq_flags = IRQF_TRIGGER_HIGH,
.micd_pol_gpio = CODEC_GPIO_BASE + 2,
.gpio_defaults = {
[2] = 0x10000, /* AIF3TXLRCLK */
[3] = 0x4, /* OPCLK */
},
};
static struct spi_board_info wm5102_spi_devs[] = {
[0] = {
.modalias = "wm5102",
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
.irq = GLENFARCLAS_PMIC_IRQ_BASE +
WM831X_IRQ_GPIO_2,
.platform_data = &wm5102_pdata,
},
};
static struct gpiod_lookup_table wm5102_gpiod_table = {
.dev_id = "spi0.1", /* SPI device name */
.table = {
GPIO_LOOKUP("GPION", 7,
"wlf,ldo1ena", GPIO_ACTIVE_HIGH),
{ },
},
};
static struct spi_board_info wm5110_spi_devs[] = {
[0] = {
.modalias = "wm5110",
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
.irq = GLENFARCLAS_PMIC_IRQ_BASE +
WM831X_IRQ_GPIO_2,
.platform_data = &wm5102_reva_pdata,
},
};
static const struct i2c_board_info wm6230_i2c_devs[] = {
{ I2C_BOARD_INFO("wm9081", 0x6c),
.platform_data = &wm9081_pdata, },
};
static struct wm2200_pdata wm2200_pdata = {
.ldo_ena = S3C64XX_GPN(7),
.gpio_defaults = {
[2] = 0x0005, /* GPIO3 24.576MHz output clock */
},
};
static const struct i2c_board_info wm2200_i2c[] = {
{ I2C_BOARD_INFO("wm2200", 0x3a),
.platform_data = &wm2200_pdata, },
};
static const struct {
u8 id;
u8 rev;
const char *name;
const struct i2c_board_info *i2c_devs;
int num_i2c_devs;
const struct spi_board_info *spi_devs;
int num_spi_devs;
struct gpiod_lookup_table *gpiod_table;
} gf_mods[] = {
{ .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
{ .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
{ .id = 0x03, .rev = 0xff, .name = "1252-EV1 Glenlivet" },
{ .id = 0x06, .rev = 0xff, .name = "WM8997-6721-CS96-EV1 Lapraoig" },
{ .id = 0x07, .rev = 0xff, .name = "WM5110-6271 Deanston",
.spi_devs = wm5110_spi_devs,
.num_spi_devs = ARRAY_SIZE(wm5110_spi_devs) },
{ .id = 0x08, .rev = 0xff, .name = "WM8903-6102 Tamdhu" },
{ .id = 0x09, .rev = 0xff, .name = "WM1811A-6305 Adelphi" },
{ .id = 0x0a, .rev = 0xff, .name = "WM8996-6272 Blackadder" },
{ .id = 0x0b, .rev = 0xff, .name = "WM8994-6235 Benromach" },
{ .id = 0x11, .rev = 0xff, .name = "6249-EV2 Glenfarclas", },
{ .id = 0x14, .rev = 0xff, .name = "6271-EV1 Lochnagar" },
{ .id = 0x15, .rev = 0xff, .name = "6320-EV1 Bells",
.i2c_devs = wm6230_i2c_devs,
.num_i2c_devs = ARRAY_SIZE(wm6230_i2c_devs) },
{ .id = 0x21, .rev = 0xff, .name = "1275-EV1 Mortlach" },
{ .id = 0x25, .rev = 0xff, .name = "1274-EV1 Glencadam" },
{ .id = 0x31, .rev = 0xff, .name = "1253-EV1 Tomatin",
.spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
{ .id = 0x32, .rev = 0xff, .name = "XXXX-EV1 Caol Illa" },
{ .id = 0x33, .rev = 0xff, .name = "XXXX-EV1 Oban" },
{ .id = 0x34, .rev = 0xff, .name = "WM0010-6320-CS42 Balblair",
.spi_devs = balblair_devs,
.num_spi_devs = ARRAY_SIZE(balblair_devs) },
{ .id = 0x39, .rev = 0xff, .name = "1254-EV1 Dallas Dhu",
.i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
{ .id = 0x3a, .rev = 0xff, .name = "1259-EV1 Tobermory",
.i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
{ .id = 0x3b, .rev = 0xff, .name = "1255-EV1 Kilchoman",
.i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
{ .id = 0x3c, .rev = 0xff, .name = "1273-EV1 Longmorn" },
{ .id = 0x3d, .rev = 0xff, .name = "1277-EV1 Littlemill",
.i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs),
.gpiod_table = &wm8994_gpiod_table },
{ .id = 0x3e, .rev = 0, .name = "WM5102-6271-EV1-CS127 Amrut",
.spi_devs = wm5102_reva_spi_devs,
.num_spi_devs = ARRAY_SIZE(wm5102_reva_spi_devs),
.gpiod_table = &wm5102_reva_gpiod_table },
{ .id = 0x3e, .rev = -1, .name = "WM5102-6271-EV1-CS127 Amrut",
.spi_devs = wm5102_spi_devs,
.num_spi_devs = ARRAY_SIZE(wm5102_spi_devs),
.gpiod_table = &wm5102_gpiod_table },
{ .id = 0x3f, .rev = -1, .name = "WM2200-6271-CS90-M-REV1",
.i2c_devs = wm2200_i2c, .num_i2c_devs = ARRAY_SIZE(wm2200_i2c) },
};
static int wlf_gf_module_probe(struct i2c_client *i2c)
{
int ret, i, j, id, rev;
ret = i2c_smbus_read_byte_data(i2c, 0);
if (ret < 0) {
dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
return ret;
}
id = (ret & 0xfe) >> 2;
rev = ret & 0x3;
for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
if (id == gf_mods[i].id && (gf_mods[i].rev == 0xff ||
rev == gf_mods[i].rev))
break;
gpiod_add_lookup_table(&wm5102_reva_gpiod_table);
gpiod_add_lookup_table(&wm5102_gpiod_table);
gpiod_add_lookup_table(&wm8994_gpiod_table);
if (i < ARRAY_SIZE(gf_mods)) {
dev_info(&i2c->dev, "%s revision %d\n",
gf_mods[i].name, rev + 1);
for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
if (IS_ERR(i2c_new_client_device(i2c->adapter,
&(gf_mods[i].i2c_devs[j]))))
dev_err(&i2c->dev, "Failed to register\n");
}
spi_register_board_info(gf_mods[i].spi_devs,
gf_mods[i].num_spi_devs);
if (gf_mods[i].gpiod_table)
gpiod_add_lookup_table(gf_mods[i].gpiod_table);
} else {
dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
id, rev + 1);
}
return 0;
}
static const struct i2c_device_id wlf_gf_module_id[] = {
{ "wlf-gf-module", 0 },
{ }
};
static struct i2c_driver wlf_gf_module_driver = {
.driver = {
.name = "wlf-gf-module"
},
.probe = wlf_gf_module_probe,
.id_table = wlf_gf_module_id,
};
static int __init wlf_gf_module_register(void)
{
if (!soc_is_s3c64xx())
return 0;
return i2c_add_driver(&wlf_gf_module_driver);
}
device_initcall(wlf_gf_module_register);
| linux-master | arch/arm/mach-s3c/mach-crag6410-module.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// S3C64XX CPU PM support.
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/serial_core.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/pm_domain.h>
#include "map.h"
#include "irqs.h"
#include "cpu.h"
#include "devs.h"
#include "pm.h"
#include "wakeup-mask.h"
#include "regs-gpio.h"
#include "regs-clock.h"
#include "gpio-samsung.h"
#include "regs-gpio-memport-s3c64xx.h"
#include "regs-modem-s3c64xx.h"
#include "regs-sys-s3c64xx.h"
#include "regs-syscon-power-s3c64xx.h"
struct s3c64xx_pm_domain {
char *const name;
u32 ena;
u32 pwr_stat;
struct generic_pm_domain pd;
};
static int s3c64xx_pd_off(struct generic_pm_domain *domain)
{
struct s3c64xx_pm_domain *pd;
u32 val;
pd = container_of(domain, struct s3c64xx_pm_domain, pd);
val = __raw_readl(S3C64XX_NORMAL_CFG);
val &= ~(pd->ena);
__raw_writel(val, S3C64XX_NORMAL_CFG);
return 0;
}
static int s3c64xx_pd_on(struct generic_pm_domain *domain)
{
struct s3c64xx_pm_domain *pd;
u32 val;
long retry = 1000000L;
pd = container_of(domain, struct s3c64xx_pm_domain, pd);
val = __raw_readl(S3C64XX_NORMAL_CFG);
val |= pd->ena;
__raw_writel(val, S3C64XX_NORMAL_CFG);
/* Not all domains provide power status readback */
if (pd->pwr_stat) {
do {
cpu_relax();
if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
break;
} while (retry--);
if (!retry) {
pr_err("Failed to start domain %s\n", pd->name);
return -EBUSY;
}
}
return 0;
}
static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
.name = "IROM",
.ena = S3C64XX_NORMALCFG_IROM_ON,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
.name = "ETM",
.ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_s = {
.name = "S",
.ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_S,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_f = {
.name = "F",
.ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_F,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_p = {
.name = "P",
.ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_P,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_i = {
.name = "I",
.ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_I,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_g = {
.name = "G",
.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain s3c64xx_pm_v = {
.name = "V",
.ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
.pwr_stat = S3C64XX_BLKPWRSTAT_V,
.pd = {
.power_off = s3c64xx_pd_off,
.power_on = s3c64xx_pd_on,
},
};
static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
&s3c64xx_pm_irom,
};
static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
&s3c64xx_pm_etm,
&s3c64xx_pm_g,
&s3c64xx_pm_v,
&s3c64xx_pm_i,
&s3c64xx_pm_p,
&s3c64xx_pm_s,
&s3c64xx_pm_f,
};
#ifdef CONFIG_PM_SLEEP
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C64XX_MEM0DRVCON),
SAVE_ITEM(S3C64XX_MEM1DRVCON),
};
static struct sleep_save misc_save[] = {
SAVE_ITEM(S3C64XX_AHB_CON0),
SAVE_ITEM(S3C64XX_AHB_CON1),
SAVE_ITEM(S3C64XX_AHB_CON2),
SAVE_ITEM(S3C64XX_SPCON),
SAVE_ITEM(S3C64XX_MEM0CONSTOP),
SAVE_ITEM(S3C64XX_MEM1CONSTOP),
SAVE_ITEM(S3C64XX_MEM0CONSLP0),
SAVE_ITEM(S3C64XX_MEM0CONSLP1),
SAVE_ITEM(S3C64XX_MEM1CONSLP),
SAVE_ITEM(S3C64XX_SDMA_SEL),
SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
SAVE_ITEM(S3C64XX_NORMAL_CFG),
};
void s3c_pm_configure_extint(void)
{
__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
}
void s3c_pm_restore_core(void)
{
__raw_writel(0, S3C64XX_EINT_MASK);
s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
}
void s3c_pm_save_core(void)
{
s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
}
#endif
/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
* put the per-cpu code in here until any new cpu comes along and changes
* this.
*/
static int s3c64xx_cpu_suspend(unsigned long arg)
{
unsigned long tmp;
/* set our standby method to sleep */
tmp = __raw_readl(S3C64XX_PWR_CFG);
tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
__raw_writel(tmp, S3C64XX_PWR_CFG);
/* clear any old wakeup */
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
S3C64XX_WAKEUP_STAT);
/* issue the standby signal into the pm unit. Note, we
* issue a write-buffer drain just in case */
tmp = 0;
asm("b 1f\n\t"
".align 5\n\t"
"1:\n\t"
"mcr p15, 0, %0, c7, c10, 5\n\t"
"mcr p15, 0, %0, c7, c10, 4\n\t"
"mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
/* we should never get past here */
pr_info("Failed to suspend the system\n");
return 1; /* Aborting suspend */
}
/* mapping of interrupts to parts of the wakeup mask */
static const struct samsung_wakeup_mask wake_irqs[] = {
{ .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
{ .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
{ .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
{ .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
{ .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
{ .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
{ .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
};
static void s3c64xx_pm_prepare(void)
{
samsung_sync_wakemask(S3C64XX_PWR_CFG,
wake_irqs, ARRAY_SIZE(wake_irqs));
/* store address of resume. */
__raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
/* ensure previous wakeup state is cleared before sleeping */
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
}
int __init s3c64xx_pm_init(void)
{
int i;
s3c_pm_init();
for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
&pm_domain_always_on_gov, false);
for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
#ifdef CONFIG_S3C_DEV_FB
if (dev_get_platdata(&s3c_device_fb.dev))
pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
#endif
return 0;
}
static __init int s3c64xx_pm_initcall(void)
{
if (!soc_is_s3c64xx())
return 0;
pm_cpu_prep = s3c64xx_pm_prepare;
pm_cpu_sleep = s3c64xx_cpu_suspend;
return 0;
}
arch_initcall(s3c64xx_pm_initcall);
| linux-master | arch/arm/mach-s3c/pm-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include "gpio-cfg.h"
#include "sdhci.h"
#include "gpio-samsung.h"
void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
/* Set all the necessary GPG pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
}
}
void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
/* Set all the necessary GPH pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
}
}
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
/* Set all the necessary GPH pins to special-function 3 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
/* Set all the necessary GPC pins to special-function 3 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
}
| linux-master | arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2013 Samsung Electronics Co., Ltd.
// Tomasz Figa <[email protected]>
// Copyright (C) 2008 Openmoko, Inc.
// Copyright (C) 2004-2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Samsung common power management helper functions.
#include <linux/io.h>
#include <linux/kernel.h>
#include "pm-common.h"
/* helper functions to save and restore register state */
/**
* s3c_pm_do_save() - save a set of registers for restoration on resume.
* @ptr: Pointer to an array of registers.
* @count: Size of the ptr array.
*
* Run through the list of registers given, saving their contents in the
* array for later restoration when we wakeup.
*/
void s3c_pm_do_save(struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
ptr->val = readl_relaxed(ptr->reg);
S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
}
}
/**
* s3c_pm_do_restore() - restore register values from the save list.
* @ptr: Pointer to an array of registers.
* @count: Size of the ptr array.
*
* Restore the register values saved from s3c_pm_do_save().
*
* Note, we do not use S3C_PMDBG() in here, as the system may not have
* restore the UARTs state yet
*/
void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
pr_debug("restore %p (restore %08lx, was %08x)\n",
ptr->reg, ptr->val, readl_relaxed(ptr->reg));
writel_relaxed(ptr->val, ptr->reg);
}
}
/**
* s3c_pm_do_restore_core() - early restore register values from save list.
* @ptr: Pointer to an array of registers.
* @count: Size of the ptr array.
*
* This is similar to s3c_pm_do_restore() except we try and minimise the
* side effects of the function in case registers that hardware might need
* to work has been restored.
*
* WARNING: Do not put any debug in here that may effect memory or use
* peripherals, as things may be changing!
*/
void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++)
writel_relaxed(ptr->val, ptr->reg);
}
| linux-master | arch/arm/mach-s3c/pm-common.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2011 Wolfson Microelectronics, plc
// Copyright (c) 2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cpuidle.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/time.h>
#include <asm/cpuidle.h>
#include "cpu.h"
#include "map.h"
#include "regs-sys-s3c64xx.h"
#include "regs-syscon-power-s3c64xx.h"
static __cpuidle int s3c64xx_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
unsigned long tmp;
/* Setup PWRCFG to enter idle mode */
tmp = __raw_readl(S3C64XX_PWR_CFG);
tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
__raw_writel(tmp, S3C64XX_PWR_CFG);
cpu_do_idle();
return index;
}
static struct cpuidle_driver s3c64xx_cpuidle_driver = {
.name = "s3c64xx_cpuidle",
.owner = THIS_MODULE,
.states = {
{
.enter = s3c64xx_enter_idle,
.exit_latency = 1,
.target_residency = 1,
.name = "IDLE",
.desc = "System active, ARM gated",
},
},
.state_count = 1,
};
static int __init s3c64xx_init_cpuidle(void)
{
if (soc_is_s3c64xx())
return cpuidle_register(&s3c64xx_cpuidle_driver, NULL);
return 0;
}
device_initcall(s3c64xx_init_cpuidle);
| linux-master | arch/arm/mach-s3c/cpuidle-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// S3C64XX - Interrupt handling Power Management
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include "map.h"
#include "regs-gpio.h"
#include "cpu.h"
#include "pm.h"
/* We handled all the IRQ types in this code, to save having to make several
* small files to handle each different type separately. Having the EINT_GRP
* code here shouldn't be as much bloat as the IRQ table space needed when
* they are enabled. The added benefit is we ensure that these registers are
* in the same state as we suspended.
*/
static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C64XX_PRIORITY),
SAVE_ITEM(S3C64XX_EINT0CON0),
SAVE_ITEM(S3C64XX_EINT0CON1),
SAVE_ITEM(S3C64XX_EINT0FLTCON0),
SAVE_ITEM(S3C64XX_EINT0FLTCON1),
SAVE_ITEM(S3C64XX_EINT0FLTCON2),
SAVE_ITEM(S3C64XX_EINT0FLTCON3),
SAVE_ITEM(S3C64XX_EINT0MASK),
};
static struct irq_grp_save {
u32 fltcon;
u32 con;
u32 mask;
} eint_grp_save[5];
#ifndef CONFIG_SERIAL_SAMSUNG_UARTS
#define SERIAL_SAMSUNG_UARTS 0
#else
#define SERIAL_SAMSUNG_UARTS CONFIG_SERIAL_SAMSUNG_UARTS
#endif
static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS];
static int s3c64xx_irq_pm_suspend(void)
{
struct irq_grp_save *grp = eint_grp_save;
int i;
S3C_PMDBG("%s: suspending IRQs\n", __func__);
s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
}
return 0;
}
static void s3c64xx_irq_pm_resume(void)
{
struct irq_grp_save *grp = eint_grp_save;
int i;
S3C_PMDBG("%s: resuming IRQs\n", __func__);
s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
for (i = 0; i < SERIAL_SAMSUNG_UARTS; i++)
__raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
__raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
__raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
__raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
}
S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
}
static struct syscore_ops s3c64xx_irq_syscore_ops = {
.suspend = s3c64xx_irq_pm_suspend,
.resume = s3c64xx_irq_pm_resume,
};
static __init int s3c64xx_syscore_init(void)
{
/* Appropriate drivers (pinctrl, uart) handle this when using DT. */
if (of_have_populated_dt() || !soc_is_s3c64xx())
return 0;
register_syscore_ops(&s3c64xx_irq_syscore_ops);
return 0;
}
core_initcall(s3c64xx_syscore_init);
| linux-master | arch/arm/mach-s3c/irq-pm-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com/
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Samsung - GPIOlib support
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/of_address.h>
#include <asm/irq.h>
#include "irqs.h"
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include "cpu.h"
#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"
#include "pm.h"
static int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
unsigned int off, samsung_gpio_pull_t pull)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup;
pup = __raw_readl(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
__raw_writel(pup, reg);
return 0;
}
static samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup = __raw_readl(reg);
pup >>= shift;
pup &= 0x3;
return (__force samsung_gpio_pull_t)pup;
}
static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off * 2;
u32 con;
if (samsung_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
if (cfg > 3)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x3 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
/*
* samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
*
* The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
* could be directly passed back to samsung_gpio_setcfg_2bit(), from the
* S3C_GPIO_SPECIAL() macro.
*/
static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
unsigned int off)
{
u32 con;
con = __raw_readl(chip->base);
con >>= off * 2;
con &= 3;
/* this conversion works for IN and OUT as well as special mode */
return S3C_GPIO_SPECIAL(con);
}
/*
* samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register has 4 bits
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
* others = Special functions (dependent on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a separate set of functions for
* each case.
*/
static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = (off & 7) * 4;
u32 con;
if (off < 8 && chip->chip.ngpio > 8)
reg -= 4;
if (samsung_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
/*
* samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
*
* The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
* register setting into a value the software can use, such as could be passed
* to samsung_gpio_setcfg_4bit().
*
* @sa samsung_gpio_getcfg_2bit
*/
static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base;
unsigned int shift = (off & 7) * 4;
u32 con;
if (off < 8 && chip->chip.ngpio > 8)
reg -= 4;
con = __raw_readl(reg);
con >>= shift;
con &= 0xf;
/* this conversion works for IN and OUT as well as special mode */
return S3C_GPIO_SPECIAL(con);
}
static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chipcfg++) {
if (!chipcfg->set_config)
chipcfg->set_config = samsung_gpio_setcfg_4bit;
if (!chipcfg->get_config)
chipcfg->get_config = samsung_gpio_getcfg_4bit;
if (!chipcfg->set_pull)
chipcfg->set_pull = samsung_gpio_setpull_updown;
if (!chipcfg->get_pull)
chipcfg->get_pull = samsung_gpio_getpull_updown;
}
}
static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
[0] = {
.cfg_eint = 0x0,
},
[1] = {
.cfg_eint = 0x3,
},
[2] = {
.cfg_eint = 0x7,
},
[3] = {
.cfg_eint = 0xF,
},
[4] = {
.cfg_eint = 0x0,
.set_config = samsung_gpio_setcfg_2bit,
.get_config = samsung_gpio_getcfg_2bit,
},
[5] = {
.cfg_eint = 0x2,
.set_config = samsung_gpio_setcfg_2bit,
.get_config = samsung_gpio_getcfg_2bit,
},
[6] = {
.cfg_eint = 0x3,
.set_config = samsung_gpio_setcfg_2bit,
.get_config = samsung_gpio_getcfg_2bit,
},
[7] = {
.set_config = samsung_gpio_setcfg_2bit,
.get_config = samsung_gpio_getcfg_2bit,
},
};
/*
* Default routines for controlling GPIO, based on the original S3C24XX
* GPIO functions which deal with the case where each gpio bank of the
* chip is as following:
*
* base + 0x00: Control register, 2 bits per gpio
* gpio n: 2 bits starting at (2*n)
* 00 = input, 01 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*/
static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
samsung_gpio_lock(ourchip, flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
__raw_writel(con, base + 0x00);
samsung_gpio_unlock(ourchip, flags);
return 0;
}
static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
samsung_gpio_lock(ourchip, flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
samsung_gpio_unlock(ourchip, flags);
return 0;
}
/*
* The samsung_gpiolib_4bit routines are to control the gpio banks where
* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
* following example:
*
* base + 0x00: Control register, 4 bits per gpio
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*
* Note, since the data register is one bit per gpio and is at base + 0x4
* we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
* state of the output.
*/
static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
unsigned int offset)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
con = __raw_readl(base + GPIOCON_OFF);
if (ourchip->bitmap_gpio_int & BIT(offset))
con |= 0xf << con_4bit_shift(offset);
else
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, base + GPIOCON_OFF);
pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
return 0;
}
static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
unsigned long dat;
con = __raw_readl(base + GPIOCON_OFF);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + GPIODAT_OFF);
__raw_writel(con, base + GPIOCON_OFF);
__raw_writel(dat, base + GPIODAT_OFF);
pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
/*
* The next set of routines are for the case where the GPIO configuration
* registers are 4 bits per GPIO but there is more than one register (the
* bank has more than 8 GPIOs.
*
* This case is the similar to the 4 bit case, but the registers are as
* follows:
*
* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x08: Data register, 1 bit per gpio
* bit n: data bit n
*
* To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
* routines we store the 'base + 0x4' address so that these routines see
* the data register at ourchip->base + 0x04.
*/
static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
unsigned int offset)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
if (offset > 7)
offset -= 8;
else
regcon -= 4;
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, regcon);
pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
return 0;
}
static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
unsigned int offset, int value)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
unsigned long dat;
unsigned con_offset = offset;
if (con_offset > 7)
con_offset -= 8;
else
regcon -= 4;
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(con_offset));
con |= 0x1 << con_4bit_shift(con_offset);
dat = __raw_readl(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + GPIODAT_OFF);
__raw_writel(con, regcon);
__raw_writel(dat, base + GPIODAT_OFF);
pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
static void samsung_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
samsung_gpio_lock(ourchip, flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
samsung_gpio_unlock(ourchip, flags);
}
static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
/*
* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
* for use with the configuration calls, and other parts of the s3c gpiolib
* support code.
*
* Not all s3c support code will need this, as some configurations of cpu
* may only support one or two different configuration options and have an
* easy gpio to samsung_gpio_chip mapping function. If this is the case, then
* the machine support file should provide its own samsung_gpiolib_getchip()
* and any other necessary functions.
*/
#ifdef CONFIG_S3C_GPIO_TRACK
struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
{
unsigned int gpn;
int i;
gpn = chip->chip.base;
for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
s3c_gpios[gpn] = chip;
}
}
#endif /* CONFIG_S3C_GPIO_TRACK */
/*
* samsung_gpiolib_add() - add the Samsung gpio_chip.
* @chip: The chip to register
*
* This is a wrapper to gpiochip_add() that takes our specific gpio chip
* information and makes the necessary alterations for the platform and
* notes the information for use with the configuration systems and any
* other parts of the system.
*/
static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
{
struct gpio_chip *gc = &chip->chip;
int ret;
BUG_ON(!chip->base);
BUG_ON(!gc->label);
BUG_ON(!gc->ngpio);
spin_lock_init(&chip->lock);
if (!gc->direction_input)
gc->direction_input = samsung_gpiolib_2bit_input;
if (!gc->direction_output)
gc->direction_output = samsung_gpiolib_2bit_output;
if (!gc->set)
gc->set = samsung_gpiolib_set;
if (!gc->get)
gc->get = samsung_gpiolib_get;
#ifdef CONFIG_PM
if (chip->pm != NULL) {
if (!chip->pm->save || !chip->pm->resume)
pr_err("gpio: %s has missing PM functions\n",
gc->label);
} else
pr_err("gpio: %s has no PM function\n", gc->label);
#endif
/* gpiochip_add() prints own failure message on error. */
ret = gpiochip_add_data(gc, chip);
if (ret >= 0)
s3c_gpiolib_track(chip);
}
static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
int nr_chips, void __iomem *base,
unsigned int offset)
{
int i;
for (i = 0 ; i < nr_chips; i++, chip++) {
chip->chip.direction_input = samsung_gpiolib_2bit_input;
chip->chip.direction_output = samsung_gpiolib_2bit_output;
if (!chip->config)
chip->config = &samsung_gpio_cfgs[7];
if (!chip->pm)
chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
if ((base != NULL) && (chip->base == NULL))
chip->base = base + ((i) * offset);
samsung_gpiolib_add(chip);
}
}
/*
* samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
* @chip: The gpio chip that is being configured.
* @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
*
* This helper deal with the GPIO cases where the control register has 4 bits
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
* others = Special functions (dependent on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a separate set of function
* (samsung_gpiolib_add_4bit2_chips)for each case.
*/
static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
int nr_chips, void __iomem *base)
{
int i;
for (i = 0 ; i < nr_chips; i++, chip++) {
chip->chip.direction_input = samsung_gpiolib_4bit_input;
chip->chip.direction_output = samsung_gpiolib_4bit_output;
if (!chip->config)
chip->config = &samsung_gpio_cfgs[2];
if (!chip->pm)
chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
if ((base != NULL) && (chip->base == NULL))
chip->base = base + ((i) * 0x20);
chip->bitmap_gpio_int = 0;
samsung_gpiolib_add(chip);
}
}
static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
int nr_chips)
{
for (; nr_chips > 0; nr_chips--, chip++) {
chip->chip.direction_input = samsung_gpiolib_4bit2_input;
chip->chip.direction_output = samsung_gpiolib_4bit2_output;
if (!chip->config)
chip->config = &samsung_gpio_cfgs[2];
if (!chip->pm)
chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
samsung_gpiolib_add(chip);
}
}
int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
{
struct samsung_gpio_chip *samsung_chip = gpiochip_get_data(chip);
return samsung_chip->irq_base + offset;
}
static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
{
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
}
static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
{
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}
/*
* GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 8 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* D 5 4Bit Yes 3
* E 5 4Bit Yes None
* F 16 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* K 16 4Bit[2] No None
* L 15 4Bit[2] No None
* M 6 4Bit No IRQ_EINT
* N 16 2Bit No IRQ_EINT
* O 16 2Bit Yes 7
* P 15 2Bit Yes 8
* Q 9 2Bit Yes 9
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
{
.chip = {
.base = S3C64XX_GPA(0),
.ngpio = S3C64XX_GPIO_A_NR,
.label = "GPA",
},
}, {
.chip = {
.base = S3C64XX_GPB(0),
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.config = &samsung_gpio_cfgs[0],
.chip = {
.base = S3C64XX_GPE(0),
.ngpio = S3C64XX_GPIO_E_NR,
.label = "GPE",
},
}, {
.base = S3C64XX_GPG_BASE,
.chip = {
.base = S3C64XX_GPG(0),
.ngpio = S3C64XX_GPIO_G_NR,
.label = "GPG",
},
}, {
.base = S3C64XX_GPM_BASE,
.config = &samsung_gpio_cfgs[1],
.chip = {
.base = S3C64XX_GPM(0),
.ngpio = S3C64XX_GPIO_M_NR,
.label = "GPM",
.to_irq = s3c64xx_gpiolib_mbank_to_irq,
},
},
};
static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
{
.base = S3C64XX_GPH_BASE + 0x4,
.chip = {
.base = S3C64XX_GPH(0),
.ngpio = S3C64XX_GPIO_H_NR,
.label = "GPH",
},
}, {
.base = S3C64XX_GPK_BASE + 0x4,
.config = &samsung_gpio_cfgs[0],
.chip = {
.base = S3C64XX_GPK(0),
.ngpio = S3C64XX_GPIO_K_NR,
.label = "GPK",
},
}, {
.base = S3C64XX_GPL_BASE + 0x4,
.config = &samsung_gpio_cfgs[1],
.chip = {
.base = S3C64XX_GPL(0),
.ngpio = S3C64XX_GPIO_L_NR,
.label = "GPL",
.to_irq = s3c64xx_gpiolib_lbank_to_irq,
},
},
};
static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
.config = &samsung_gpio_cfgs[6],
.chip = {
.base = S3C64XX_GPF(0),
.ngpio = S3C64XX_GPIO_F_NR,
.label = "GPF",
},
}, {
.config = &samsung_gpio_cfgs[7],
.chip = {
.base = S3C64XX_GPI(0),
.ngpio = S3C64XX_GPIO_I_NR,
.label = "GPI",
},
}, {
.config = &samsung_gpio_cfgs[7],
.chip = {
.base = S3C64XX_GPJ(0),
.ngpio = S3C64XX_GPIO_J_NR,
.label = "GPJ",
},
}, {
.config = &samsung_gpio_cfgs[6],
.chip = {
.base = S3C64XX_GPO(0),
.ngpio = S3C64XX_GPIO_O_NR,
.label = "GPO",
},
}, {
.config = &samsung_gpio_cfgs[6],
.chip = {
.base = S3C64XX_GPP(0),
.ngpio = S3C64XX_GPIO_P_NR,
.label = "GPP",
},
}, {
.config = &samsung_gpio_cfgs[6],
.chip = {
.base = S3C64XX_GPQ(0),
.ngpio = S3C64XX_GPIO_Q_NR,
.label = "GPQ",
},
}, {
.base = S3C64XX_GPN_BASE,
.irq_base = IRQ_EINT(0),
.config = &samsung_gpio_cfgs[5],
.chip = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
.to_irq = samsung_gpiolib_to_irq,
},
},
};
/* TODO: cleanup soc_is_* */
static __init int samsung_gpiolib_init(void)
{
/*
* Currently there are two drivers that can provide GPIO support for
* Samsung SoCs. For device tree enabled platforms, the new
* pinctrl-samsung driver is used, providing both GPIO and pin control
* interfaces. For legacy (non-DT) platforms this driver is used.
*/
if (of_have_populated_dt())
return 0;
if (soc_is_s3c64xx()) {
samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
ARRAY_SIZE(samsung_gpio_cfgs));
samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
ARRAY_SIZE(s3c64xx_gpios_2bit),
S3C64XX_VA_GPIO + 0xE0, 0x20);
samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
ARRAY_SIZE(s3c64xx_gpios_4bit),
S3C64XX_VA_GPIO);
samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
ARRAY_SIZE(s3c64xx_gpios_4bit2));
}
return 0;
}
core_initcall(samsung_gpiolib_init);
int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
{
struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
unsigned long flags;
int offset;
int ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
samsung_gpio_lock(chip, flags);
ret = samsung_gpio_do_setcfg(chip, offset, config);
samsung_gpio_unlock(chip, flags);
return ret;
}
EXPORT_SYMBOL(s3c_gpio_cfgpin);
int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
unsigned int cfg)
{
int ret;
for (; nr > 0; nr--, start++) {
ret = s3c_gpio_cfgpin(start, cfg);
if (ret != 0)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
unsigned int cfg, samsung_gpio_pull_t pull)
{
int ret;
for (; nr > 0; nr--, start++) {
s3c_gpio_setpull(start, pull);
ret = s3c_gpio_cfgpin(start, cfg);
if (ret != 0)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
{
struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
unsigned long flags;
int offset, ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
samsung_gpio_lock(chip, flags);
ret = samsung_gpio_do_setpull(chip, offset, pull);
samsung_gpio_unlock(chip, flags);
return ret;
}
EXPORT_SYMBOL(s3c_gpio_setpull);
| linux-master | arch/arm/mach-s3c/gpio-samsung.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2004-2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// S3C common power management (suspend to ram) support.
#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/serial_s3c.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/suspend.h>
#include "map.h"
#include "regs-clock.h"
#include "regs-irq.h"
#include "irqs.h"
#include <asm/irq.h>
#include "cpu.h"
#include "pm.h"
#include "pm-core.h"
/* for external use */
unsigned long s3c_pm_flags;
/* The IRQ ext-int code goes here, it is too small to currently bother
* with its own file. */
unsigned long s3c_irqwake_intmask = 0xffffffffL;
unsigned long s3c_irqwake_eintmask = 0xffffffffL;
int s3c_irqext_wake(struct irq_data *data, unsigned int state)
{
unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);
if (!(s3c_irqwake_eintallow & bit))
return -ENOENT;
printk(KERN_INFO "wake %s for irq %d\n",
state ? "enabled" : "disabled", data->irq);
if (!state)
s3c_irqwake_eintmask |= bit;
else
s3c_irqwake_eintmask &= ~bit;
return 0;
}
void (*pm_cpu_prep)(void);
int (*pm_cpu_sleep)(unsigned long);
#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
/* s3c_pm_enter
*
* central control for sleep/resume process
*/
static int s3c_pm_enter(suspend_state_t state)
{
int ret;
/* ensure the debug is initialised (if enabled) */
s3c_pm_debug_init_uart();
S3C_PMDBG("%s(%d)\n", __func__, state);
if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
return -EINVAL;
}
/* check if we have anything to wake-up with... bad things seem
* to happen if you suspend with no wakeup (system will often
* require a full power-cycle)
*/
if (!of_have_populated_dt() &&
!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
printk(KERN_ERR "%s: Aborting sleep\n", __func__);
return -EINVAL;
}
/* save all necessary core registers not covered by the drivers */
if (!of_have_populated_dt()) {
samsung_pm_save_gpios();
samsung_pm_saved_gpios();
}
s3c_pm_save_uarts(false);
s3c_pm_save_core();
/* set the irq configuration for wake */
s3c_pm_configure_extint();
S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
s3c_irqwake_intmask, s3c_irqwake_eintmask);
s3c_pm_arch_prepare_irqs();
/* call cpu specific preparation */
pm_cpu_prep();
/* flush cache back to ram */
flush_cache_all();
s3c_pm_check_store();
/* send the cpu to sleep... */
s3c_pm_arch_stop_clocks();
/* this will also act as our return point from when
* we resume as it saves its own register state and restores it
* during the resume. */
ret = cpu_suspend(0, pm_cpu_sleep);
if (ret)
return ret;
/* restore the system state */
s3c_pm_restore_core();
s3c_pm_restore_uarts(false);
if (!of_have_populated_dt()) {
samsung_pm_restore_gpios();
s3c_pm_restored_gpios();
}
s3c_pm_debug_init_uart();
/* check what irq (if any) restored the system */
s3c_pm_arch_show_resume_irqs();
S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
s3c_pm_check_restore();
/* ok, let's return from sleep */
S3C_PMDBG("S3C PM Resume (post-restore)\n");
return 0;
}
static int s3c_pm_prepare(void)
{
/* prepare check area if configured */
s3c_pm_check_prepare();
return 0;
}
static void s3c_pm_finish(void)
{
s3c_pm_check_cleanup();
}
static const struct platform_suspend_ops s3c_pm_ops = {
.enter = s3c_pm_enter,
.prepare = s3c_pm_prepare,
.finish = s3c_pm_finish,
.valid = suspend_valid_only_mem,
};
/* s3c_pm_init
*
* Attach the power management functions. This should be called
* from the board specific initialisation if the board supports
* it.
*/
int __init s3c_pm_init(void)
{
printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
suspend_set_ops(&s3c_pm_ops);
return 0;
}
| linux-master | arch/arm/mach-s3c/pm.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011 Samsung Electronics Co.Ltd
// Author: Joonyoung Shim <[email protected]>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include "map.h"
#include "cpu.h"
#include "usb-phy.h"
#include "regs-sys-s3c64xx.h"
#include "regs-usb-hsotg-phy-s3c64xx.h"
enum samsung_usb_phy_type {
USB_PHY_TYPE_DEVICE,
USB_PHY_TYPE_HOST,
};
static int s3c_usb_otgphy_init(struct platform_device *pdev)
{
struct clk *xusbxti;
u32 phyclk;
writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
/* set clock frequency for PLL */
phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
xusbxti = clk_get(&pdev->dev, "xusbxti");
if (!IS_ERR(xusbxti)) {
switch (clk_get_rate(xusbxti)) {
case 12 * MHZ:
phyclk |= S3C_PHYCLK_CLKSEL_12M;
break;
case 24 * MHZ:
phyclk |= S3C_PHYCLK_CLKSEL_24M;
break;
default:
case 48 * MHZ:
/* default reference clock */
break;
}
clk_put(xusbxti);
}
/* TODO: select external clock/oscillator */
writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
/* set to normal OTG PHY */
writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
mdelay(1);
/* reset OTG PHY and Link */
writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
S3C_RSTCON);
udelay(20); /* at-least 10uS */
writel(0, S3C_RSTCON);
return 0;
}
static int s3c_usb_otgphy_exit(struct platform_device *pdev)
{
writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
return 0;
}
int s3c_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == USB_PHY_TYPE_DEVICE)
return s3c_usb_otgphy_init(pdev);
return -EINVAL;
}
int s3c_usb_phy_exit(struct platform_device *pdev, int type)
{
if (type == USB_PHY_TYPE_DEVICE)
return s3c_usb_otgphy_exit(pdev);
return -EINVAL;
}
| linux-master | arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Base S3C64XX setup information for 24bpp LCD framebuffer
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include "fb.h"
#include "gpio-cfg.h"
#include "gpio-samsung.h"
void s3c64xx_fb_gpio_setup_24bpp(void)
{
s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
}
| linux-master | arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// originally from arch/arm/plat-s3c24xx/devs.c
//
// Copyright (c) 2004 Simtec Electronics
// Ben Dooks <[email protected]>
//
// Base S3C24XX platform device definitions
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include "devs.h"
/* uart devices */
static struct platform_device s3c24xx_uart_device0 = {
.id = 0,
};
static struct platform_device s3c24xx_uart_device1 = {
.id = 1,
};
static struct platform_device s3c24xx_uart_device2 = {
.id = 2,
};
static struct platform_device s3c24xx_uart_device3 = {
.id = 3,
};
struct platform_device *s3c24xx_uart_src[4] = {
&s3c24xx_uart_device0,
&s3c24xx_uart_device1,
&s3c24xx_uart_device2,
&s3c24xx_uart_device3,
};
struct platform_device *s3c24xx_uart_devs[4] = {
};
| linux-master | arch/arm/mach-s3c/dev-uart.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2009 Wolfson Microelectronics
// Mark Brown <[email protected]>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/export.h>
#include "irqs.h"
#include "map.h"
#include "devs.h"
#include <linux/platform_data/asoc-s3c.h>
#include "gpio-cfg.h"
#include "gpio-samsung.h"
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static struct resource s3c64xx_iis0_resource[] = {
[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256),
};
static struct s3c_audio_pdata i2s0_pdata = {
.cfg_gpio = s3c64xx_i2s_cfg_gpio,
};
struct platform_device s3c64xx_device_iis0 = {
.name = "samsung-i2s",
.id = 0,
.num_resources = ARRAY_SIZE(s3c64xx_iis0_resource),
.resource = s3c64xx_iis0_resource,
.dev = {
.platform_data = &i2s0_pdata,
},
};
EXPORT_SYMBOL(s3c64xx_device_iis0);
static struct resource s3c64xx_iis1_resource[] = {
[0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256),
};
static struct s3c_audio_pdata i2s1_pdata = {
.cfg_gpio = s3c64xx_i2s_cfg_gpio,
};
struct platform_device s3c64xx_device_iis1 = {
.name = "samsung-i2s",
.id = 1,
.num_resources = ARRAY_SIZE(s3c64xx_iis1_resource),
.resource = s3c64xx_iis1_resource,
.dev = {
.platform_data = &i2s1_pdata,
},
};
EXPORT_SYMBOL(s3c64xx_device_iis1);
| linux-master | arch/arm/mach-s3c/dev-audio-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// S3C series GPIO PM code
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include "gpio-samsung.h"
#include "gpio-core.h"
#include "pm.h"
/* PM GPIO helpers */
#define OFFS_CON (0x00)
#define OFFS_DAT (0x04)
#define OFFS_UP (0x08)
static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip)
{
chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
}
static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
u32 old_gpcon = __raw_readl(base + OFFS_CON);
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
u32 gps_gpcon = chip->pm_save[0];
u32 gps_gpdat = chip->pm_save[1];
u32 gpcon;
/* GPACON only has one bit per control / data and no PULLUPs.
* GPACON[x] = 0 => Output, 1 => SFN */
/* first set all SFN bits to SFN */
gpcon = old_gpcon | gps_gpcon;
__raw_writel(gpcon, base + OFFS_CON);
/* now set all the other bits */
__raw_writel(gps_gpdat, base + OFFS_DAT);
__raw_writel(gps_gpcon, base + OFFS_CON);
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
}
struct samsung_gpio_pm samsung_gpio_pm_1bit = {
.save = samsung_gpio_pm_1bit_save,
.resume = samsung_gpio_pm_1bit_resume,
};
static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip)
{
chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
}
/* Test whether the given masked+shifted bits of an GPIO configuration
* are one of the SFN (special function) modes. */
static inline int is_sfn(unsigned long con)
{
return con >= 2;
}
/* Test if the given masked+shifted GPIO configuration is an input */
static inline int is_in(unsigned long con)
{
return con == 0;
}
/* Test if the given masked+shifted GPIO configuration is an output */
static inline int is_out(unsigned long con)
{
return con == 1;
}
/**
* samsung_gpio_pm_2bit_resume() - restore the given GPIO bank
* @chip: The chip information to resume.
*
* Restore one of the GPIO banks that was saved during suspend. This is
* not as simple as once thought, due to the possibility of glitches
* from the order that the CON and DAT registers are set in.
*
* The three states the pin can be are {IN,OUT,SFN} which gives us 9
* combinations of changes to check. Three of these, if the pin stays
* in the same configuration can be discounted. This leaves us with
* the following:
*
* { IN => OUT } Change DAT first
* { IN => SFN } Change CON first
* { OUT => SFN } Change CON first, so new data will not glitch
* { OUT => IN } Change CON first, so new data will not glitch
* { SFN => IN } Change CON first
* { SFN => OUT } Change DAT first, so new data will not glitch [1]
*
* We do not currently deal with the UP registers as these control
* weak resistors, so a small delay in change should not need to bring
* these into the calculations.
*
* [1] this assumes that writing to a pin DAT whilst in SFN will set the
* state for when it is next output.
*/
static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
u32 old_gpcon = __raw_readl(base + OFFS_CON);
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
u32 gps_gpcon = chip->pm_save[0];
u32 gps_gpdat = chip->pm_save[1];
u32 gpcon, old, new, mask;
u32 change_mask = 0x0;
int nr;
/* restore GPIO pull-up settings */
__raw_writel(chip->pm_save[2], base + OFFS_UP);
/* Create a change_mask of all the items that need to have
* their CON value changed before their DAT value, so that
* we minimise the work between the two settings.
*/
for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
old = (old_gpcon & mask) >> nr;
new = (gps_gpcon & mask) >> nr;
/* If there is no change, then skip */
if (old == new)
continue;
/* If both are special function, then skip */
if (is_sfn(old) && is_sfn(new))
continue;
/* Change is IN => OUT, do not change now */
if (is_in(old) && is_out(new))
continue;
/* Change is SFN => OUT, do not change now */
if (is_sfn(old) && is_out(new))
continue;
/* We should now be at the case of IN=>SFN,
* OUT=>SFN, OUT=>IN, SFN=>IN. */
change_mask |= mask;
}
/* Write the new CON settings */
gpcon = old_gpcon & ~change_mask;
gpcon |= gps_gpcon & change_mask;
__raw_writel(gpcon, base + OFFS_CON);
/* Now change any items that require DAT,CON */
__raw_writel(gps_gpdat, base + OFFS_DAT);
__raw_writel(gps_gpcon, base + OFFS_CON);
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
}
struct samsung_gpio_pm samsung_gpio_pm_2bit = {
.save = samsung_gpio_pm_2bit_save,
.resume = samsung_gpio_pm_2bit_resume,
};
#if defined(CONFIG_ARCH_S3C64XX)
static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
{
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
if (chip->chip.ngpio > 8)
chip->pm_save[0] = __raw_readl(chip->base - 4);
}
static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
{
u32 old, new, mask;
u32 change_mask = 0x0;
int nr;
for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
old = (old_gpcon & mask) >> nr;
new = (gps_gpcon & mask) >> nr;
/* If there is no change, then skip */
if (old == new)
continue;
/* If both are special function, then skip */
if (is_sfn(old) && is_sfn(new))
continue;
/* Change is IN => OUT, do not change now */
if (is_in(old) && is_out(new))
continue;
/* Change is SFN => OUT, do not change now */
if (is_sfn(old) && is_out(new))
continue;
/* We should now be at the case of IN=>SFN,
* OUT=>SFN, OUT=>IN, SFN=>IN. */
change_mask |= mask;
}
return change_mask;
}
static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index)
{
void __iomem *con = chip->base + (index * 4);
u32 old_gpcon = __raw_readl(con);
u32 gps_gpcon = chip->pm_save[index + 1];
u32 gpcon, mask;
mask = samsung_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
gpcon = old_gpcon & ~mask;
gpcon |= gps_gpcon & mask;
__raw_writel(gpcon, con);
}
static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
u32 old_gpcon[2];
u32 old_gpdat = __raw_readl(base + OFFS_DAT);
u32 gps_gpdat = chip->pm_save[2];
/* First, modify the CON settings */
old_gpcon[0] = 0;
old_gpcon[1] = __raw_readl(base + OFFS_CON);
samsung_gpio_pm_4bit_con(chip, 0);
if (chip->chip.ngpio > 8) {
old_gpcon[0] = __raw_readl(base - 4);
samsung_gpio_pm_4bit_con(chip, -1);
}
/* Now change the configurations that require DAT,CON */
__raw_writel(chip->pm_save[2], base + OFFS_DAT);
__raw_writel(chip->pm_save[1], base + OFFS_CON);
if (chip->chip.ngpio > 8)
__raw_writel(chip->pm_save[0], base - 4);
__raw_writel(chip->pm_save[2], base + OFFS_DAT);
__raw_writel(chip->pm_save[3], base + OFFS_UP);
if (chip->chip.ngpio > 8) {
S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon[0], old_gpcon[1],
__raw_readl(base - 4),
__raw_readl(base + OFFS_CON),
old_gpdat, gps_gpdat);
} else
S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon[1],
__raw_readl(base + OFFS_CON),
old_gpdat, gps_gpdat);
}
struct samsung_gpio_pm samsung_gpio_pm_4bit = {
.save = samsung_gpio_pm_4bit_save,
.resume = samsung_gpio_pm_4bit_resume,
};
#endif /* CONFIG_ARCH_S3C64XX */
/**
* samsung_pm_save_gpio() - save gpio chip data for suspend
* @ourchip: The chip for suspend.
*/
static void samsung_pm_save_gpio(struct samsung_gpio_chip *ourchip)
{
struct samsung_gpio_pm *pm = ourchip->pm;
if (pm == NULL || pm->save == NULL)
S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
else
pm->save(ourchip);
}
/**
* samsung_pm_save_gpios() - Save the state of the GPIO banks.
*
* For all the GPIO banks, save the state of each one ready for going
* into a suspend mode.
*/
void samsung_pm_save_gpios(void)
{
struct samsung_gpio_chip *ourchip;
unsigned int gpio_nr;
for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
ourchip = samsung_gpiolib_getchip(gpio_nr);
if (!ourchip) {
gpio_nr++;
continue;
}
samsung_pm_save_gpio(ourchip);
S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
ourchip->chip.label,
ourchip->pm_save[0],
ourchip->pm_save[1],
ourchip->pm_save[2],
ourchip->pm_save[3]);
gpio_nr += ourchip->chip.ngpio;
gpio_nr += CONFIG_S3C_GPIO_SPACE;
}
}
/**
* samsung_pm_resume_gpio() - restore gpio chip data after suspend
* @ourchip: The suspended chip.
*/
static void samsung_pm_resume_gpio(struct samsung_gpio_chip *ourchip)
{
struct samsung_gpio_pm *pm = ourchip->pm;
if (pm == NULL || pm->resume == NULL)
S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
else
pm->resume(ourchip);
}
void samsung_pm_restore_gpios(void)
{
struct samsung_gpio_chip *ourchip;
unsigned int gpio_nr;
for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
ourchip = samsung_gpiolib_getchip(gpio_nr);
if (!ourchip) {
gpio_nr++;
continue;
}
samsung_pm_resume_gpio(ourchip);
gpio_nr += ourchip->chip.ngpio;
gpio_nr += CONFIG_S3C_GPIO_SPACE;
}
}
| linux-master | arch/arm/mach-s3c/pm-gpio.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2011 Wolfson Microelectronics plc
// Mark Brown <[email protected]>
//
// Copyright 2011 Simtec Electronics
// Ben Dooks <[email protected]>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/input-event-codes.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/leds.h>
#include <linux/delay.h>
#include <linux/mmc/host.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/dm9000.h>
#include <linux/gpio_keys.h>
#include <linux/gpio/driver.h>
#include <linux/spi/spi.h>
#include <linux/platform_data/pca953x.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <video/platform_lcd.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/irq.h>
#include <linux/mfd/wm831x/gpio.h>
#include <sound/wm1250-ev1.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <video/samsung_fimd.h>
#include "map.h"
#include "regs-gpio.h"
#include "gpio-samsung.h"
#include "irqs.h"
#include "fb.h"
#include "sdhci.h"
#include "gpio-cfg.h"
#include <linux/platform_data/spi-s3c64xx.h>
#include "keypad.h"
#include "devs.h"
#include "cpu.h"
#include <linux/platform_data/i2c-s3c2410.h>
#include "pm.h"
#include "s3c64xx.h"
#include "crag6410.h"
#include "regs-gpio-memport-s3c64xx.h"
#include "regs-modem-s3c64xx.h"
#include "regs-sys-s3c64xx.h"
/* serial port setup */
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
};
static struct pwm_lookup crag6410_pwm_lookup[] = {
PWM_LOOKUP("samsung-pwm", 0, "pwm-backlight", NULL, 100000,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data crag6410_backlight_data = {
.max_brightness = 1000,
.dft_brightness = 600,
};
static struct platform_device crag6410_backlight_device = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.parent = &samsung_device_pwm.dev,
.platform_data = &crag6410_backlight_data,
},
};
static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
{
pr_debug("%s: setting power %d\n", __func__, power);
if (power) {
gpio_set_value(S3C64XX_GPB(0), 1);
msleep(1);
s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
} else {
gpio_direction_output(S3C64XX_GPF(14), 0);
gpio_set_value(S3C64XX_GPB(0), 0);
}
}
static struct platform_device crag6410_lcd_powerdev = {
.name = "platform-lcd",
.id = -1,
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &(struct plat_lcd_data) {
.set_power = crag6410_lcd_power_set,
},
};
/* 640x480 URT */
static struct s3c_fb_pd_win crag6410_fb_win0 = {
.max_bpp = 32,
.default_bpp = 16,
.xres = 640,
.yres = 480,
.virtual_y = 480 * 2,
.virtual_x = 640,
};
static struct fb_videomode crag6410_lcd_timing = {
.left_margin = 150,
.right_margin = 80,
.upper_margin = 40,
.lower_margin = 5,
.hsync_len = 40,
.vsync_len = 5,
.xres = 640,
.yres = 480,
};
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata crag6410_lcd_pdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.vtiming = &crag6410_lcd_timing,
.win[0] = &crag6410_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
/* 2x6 keypad */
static uint32_t crag6410_keymap[] = {
/* KEY(row, col, keycode) */
KEY(0, 0, KEY_VOLUMEUP),
KEY(0, 1, KEY_HOME),
KEY(0, 2, KEY_VOLUMEDOWN),
KEY(0, 3, KEY_HELP),
KEY(0, 4, KEY_MENU),
KEY(0, 5, KEY_MEDIA),
KEY(1, 0, 232),
KEY(1, 1, KEY_DOWN),
KEY(1, 2, KEY_LEFT),
KEY(1, 3, KEY_UP),
KEY(1, 4, KEY_RIGHT),
KEY(1, 5, KEY_CAMERA),
};
static struct matrix_keymap_data crag6410_keymap_data = {
.keymap = crag6410_keymap,
.keymap_size = ARRAY_SIZE(crag6410_keymap),
};
static struct samsung_keypad_platdata crag6410_keypad_data = {
.keymap_data = &crag6410_keymap_data,
.rows = 2,
.cols = 6,
};
static struct gpio_keys_button crag6410_gpio_keys[] = {
[0] = {
.code = KEY_SUSPEND,
.gpio = S3C64XX_GPL(10), /* EINT 18 */
.type = EV_KEY,
.wakeup = 1,
.active_low = 1,
},
[1] = {
.code = SW_FRONT_PROXIMITY,
.gpio = S3C64XX_GPN(11), /* EINT 11 */
.type = EV_SW,
},
};
static struct gpio_keys_platform_data crag6410_gpio_keydata = {
.buttons = crag6410_gpio_keys,
.nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
};
static struct platform_device crag6410_gpio_keydev = {
.name = "gpio-keys",
.id = 0,
.dev.platform_data = &crag6410_gpio_keydata,
};
static struct resource crag6410_dm9k_resource[] = {
[0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2),
[1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2),
[2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \
| IORESOURCE_IRQ_HIGHLEVEL),
};
static struct dm9000_plat_data mini6410_dm9k_pdata = {
.flags = DM9000_PLATF_16BITONLY,
};
static struct platform_device crag6410_dm9k_device = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
.resource = crag6410_dm9k_resource,
.dev.platform_data = &mini6410_dm9k_pdata,
};
static struct resource crag6410_mmgpio_resource[] = {
[0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
};
static struct platform_device crag6410_mmgpio = {
.name = "basic-mmio-gpio",
.id = -1,
.resource = crag6410_mmgpio_resource,
.num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
.dev.platform_data = &(struct bgpio_pdata) {
.base = MMGPIO_GPIO_BASE,
},
};
static struct platform_device speyside_device = {
.name = "speyside",
.id = -1,
};
static struct platform_device lowland_device = {
.name = "lowland",
.id = -1,
};
static struct platform_device tobermory_device = {
.name = "tobermory",
.id = -1,
};
static struct platform_device littlemill_device = {
.name = "littlemill",
.id = -1,
};
static struct platform_device bells_wm2200_device = {
.name = "bells",
.id = 0,
};
static struct platform_device bells_wm5102_device = {
.name = "bells",
.id = 1,
};
static struct platform_device bells_wm5110_device = {
.name = "bells",
.id = 2,
};
static struct regulator_consumer_supply wallvdd_consumers[] = {
REGULATOR_SUPPLY("SPKVDD", "1-001a"),
REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
REGULATOR_SUPPLY("SPKVDDL", "spi0.1"),
REGULATOR_SUPPLY("SPKVDDR", "spi0.1"),
REGULATOR_SUPPLY("DC1VDD", "0-0034"),
REGULATOR_SUPPLY("DC2VDD", "0-0034"),
REGULATOR_SUPPLY("DC3VDD", "0-0034"),
REGULATOR_SUPPLY("LDO1VDD", "0-0034"),
REGULATOR_SUPPLY("LDO2VDD", "0-0034"),
REGULATOR_SUPPLY("LDO4VDD", "0-0034"),
REGULATOR_SUPPLY("LDO5VDD", "0-0034"),
REGULATOR_SUPPLY("LDO6VDD", "0-0034"),
REGULATOR_SUPPLY("LDO7VDD", "0-0034"),
REGULATOR_SUPPLY("LDO8VDD", "0-0034"),
REGULATOR_SUPPLY("LDO9VDD", "0-0034"),
REGULATOR_SUPPLY("LDO10VDD", "0-0034"),
REGULATOR_SUPPLY("LDO11VDD", "0-0034"),
REGULATOR_SUPPLY("DC1VDD", "1-0034"),
REGULATOR_SUPPLY("DC2VDD", "1-0034"),
REGULATOR_SUPPLY("DC3VDD", "1-0034"),
REGULATOR_SUPPLY("LDO1VDD", "1-0034"),
REGULATOR_SUPPLY("LDO2VDD", "1-0034"),
REGULATOR_SUPPLY("LDO4VDD", "1-0034"),
REGULATOR_SUPPLY("LDO5VDD", "1-0034"),
REGULATOR_SUPPLY("LDO6VDD", "1-0034"),
REGULATOR_SUPPLY("LDO7VDD", "1-0034"),
REGULATOR_SUPPLY("LDO8VDD", "1-0034"),
REGULATOR_SUPPLY("LDO9VDD", "1-0034"),
REGULATOR_SUPPLY("LDO10VDD", "1-0034"),
REGULATOR_SUPPLY("LDO11VDD", "1-0034"),
};
static struct regulator_init_data wallvdd_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
.consumer_supplies = wallvdd_consumers,
};
static struct fixed_voltage_config wallvdd_pdata = {
.supply_name = "WALLVDD",
.microvolts = 5000000,
.init_data = &wallvdd_data,
};
static struct platform_device wallvdd_device = {
.name = "reg-fixed-voltage",
.id = -1,
.dev = {
.platform_data = &wallvdd_pdata,
},
};
static struct platform_device *crag6410_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&s3c_device_ohci,
&s3c_device_usb_hsotg,
&samsung_device_pwm,
&s3c64xx_device_iis0,
&s3c64xx_device_iis1,
&samsung_device_keypad,
&crag6410_gpio_keydev,
&crag6410_dm9k_device,
&s3c64xx_device_spi0,
&crag6410_mmgpio,
&crag6410_lcd_powerdev,
&crag6410_backlight_device,
&speyside_device,
&tobermory_device,
&littlemill_device,
&lowland_device,
&bells_wm2200_device,
&bells_wm5102_device,
&bells_wm5110_device,
&wallvdd_device,
};
static struct pca953x_platform_data crag6410_pca_data = {
.gpio_base = PCA935X_GPIO_BASE,
.irq_base = -1,
};
/* VDDARM is controlled by DVS1 connected to GPK(0) */
static struct wm831x_buckv_pdata vddarm_pdata = {
.dvs_control_src = 1,
};
static struct regulator_consumer_supply vddarm_consumers[] = {
REGULATOR_SUPPLY("vddarm", NULL),
};
static struct regulator_init_data vddarm = {
.constraints = {
.name = "VDDARM",
.min_uV = 1000000,
.max_uV = 1300000,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
.consumer_supplies = vddarm_consumers,
.supply_regulator = "WALLVDD",
.driver_data = &vddarm_pdata,
};
static struct regulator_consumer_supply vddint_consumers[] = {
REGULATOR_SUPPLY("vddint", NULL),
};
static struct regulator_init_data vddint = {
.constraints = {
.name = "VDDINT",
.min_uV = 1000000,
.max_uV = 1200000,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
.consumer_supplies = vddint_consumers,
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddmem = {
.constraints = {
.name = "VDDMEM",
.always_on = 1,
},
};
static struct regulator_init_data vddsys = {
.constraints = {
.name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
.always_on = 1,
},
};
static struct regulator_consumer_supply vddmmc_consumers[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
};
static struct regulator_init_data vddmmc = {
.constraints = {
.name = "VDDMMC,UH",
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
.consumer_supplies = vddmmc_consumers,
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddotgi = {
.constraints = {
.name = "VDDOTGi",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddotg = {
.constraints = {
.name = "VDDOTG",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddhi = {
.constraints = {
.name = "VDDHI",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddadc = {
.constraints = {
.name = "VDDADC,VDDDAC",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddmem0 = {
.constraints = {
.name = "VDDMEM0",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddpll = {
.constraints = {
.name = "VDDPLL",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddlcd = {
.constraints = {
.name = "VDDLCD",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct regulator_init_data vddalive = {
.constraints = {
.name = "VDDALIVE",
.always_on = 1,
},
.supply_regulator = "WALLVDD",
};
static struct wm831x_backup_pdata banff_backup_pdata = {
.charger_enable = 1,
.vlim = 2500, /* mV */
.ilim = 200, /* uA */
};
static struct wm831x_status_pdata banff_red_led = {
.name = "banff:red:",
.default_src = WM831X_STATUS_MANUAL,
};
static struct wm831x_status_pdata banff_green_led = {
.name = "banff:green:",
.default_src = WM831X_STATUS_MANUAL,
};
static struct wm831x_touch_pdata touch_pdata = {
.data_irq = S3C_EINT(26),
.pd_irq = S3C_EINT(27),
};
static struct wm831x_pdata crag_pmic_pdata = {
.wm831x_num = 1,
.irq_base = BANFF_PMIC_IRQ_BASE,
.gpio_base = BANFF_PMIC_GPIO_BASE,
.soft_shutdown = true,
.backup = &banff_backup_pdata,
.gpio_defaults = {
/* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
[4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
/* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
[10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
/* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
[11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
},
.dcdc = {
&vddarm, /* DCDC1 */
&vddint, /* DCDC2 */
&vddmem, /* DCDC3 */
},
.ldo = {
&vddsys, /* LDO1 */
&vddmmc, /* LDO2 */
NULL, /* LDO3 */
&vddotgi, /* LDO4 */
&vddotg, /* LDO5 */
&vddhi, /* LDO6 */
&vddadc, /* LDO7 */
&vddmem0, /* LDO8 */
&vddpll, /* LDO9 */
&vddlcd, /* LDO10 */
&vddalive, /* LDO11 */
},
.status = {
&banff_green_led,
&banff_red_led,
},
.touch = &touch_pdata,
};
/*
* VDDARM is eventually ending up as a regulator hanging on the MFD cell device
* "wm831x-buckv.1" spawn from drivers/mfd/wm831x-core.c.
*
* From the note on the platform data we can see that this is clearly DVS1
* and assigned as dcdc1 resource to the MFD core which sets .id of the cell
* spawning the DVS1 platform device to 1, then the cell platform device
* name is calculated from 10*instance + id resulting in the device name
* "wm831x-buckv.11"
*/
static struct gpiod_lookup_table crag_pmic_gpiod_table = {
.dev_id = "wm831x-buckv.11",
.table = {
GPIO_LOOKUP("GPIOK", 0, "dvs", GPIO_ACTIVE_HIGH),
{ },
},
};
static struct i2c_board_info i2c_devs0[] = {
{ I2C_BOARD_INFO("24c08", 0x50), },
{ I2C_BOARD_INFO("tca6408", 0x20),
.platform_data = &crag6410_pca_data,
},
{ I2C_BOARD_INFO("wm8312", 0x34),
.platform_data = &crag_pmic_pdata,
.irq = S3C_EINT(23),
},
};
static struct s3c2410_platform_i2c i2c0_pdata = {
.frequency = 400000,
};
static struct regulator_consumer_supply pvdd_1v2_consumers[] = {
REGULATOR_SUPPLY("DCVDD", "spi0.0"),
REGULATOR_SUPPLY("AVDD", "spi0.0"),
REGULATOR_SUPPLY("AVDD", "spi0.1"),
};
static struct regulator_init_data pvdd_1v2 = {
.constraints = {
.name = "PVDD_1V2",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = pvdd_1v2_consumers,
.num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
};
static struct regulator_consumer_supply pvdd_1v8_consumers[] = {
REGULATOR_SUPPLY("LDOVDD", "1-001a"),
REGULATOR_SUPPLY("PLLVDD", "1-001a"),
REGULATOR_SUPPLY("DBVDD", "1-001a"),
REGULATOR_SUPPLY("DBVDD1", "1-001a"),
REGULATOR_SUPPLY("DBVDD2", "1-001a"),
REGULATOR_SUPPLY("DBVDD3", "1-001a"),
REGULATOR_SUPPLY("CPVDD", "1-001a"),
REGULATOR_SUPPLY("AVDD2", "1-001a"),
REGULATOR_SUPPLY("DCVDD", "1-001a"),
REGULATOR_SUPPLY("AVDD", "1-001a"),
REGULATOR_SUPPLY("DBVDD", "spi0.0"),
REGULATOR_SUPPLY("DBVDD", "1-003a"),
REGULATOR_SUPPLY("LDOVDD", "1-003a"),
REGULATOR_SUPPLY("CPVDD", "1-003a"),
REGULATOR_SUPPLY("AVDD", "1-003a"),
REGULATOR_SUPPLY("DBVDD1", "spi0.1"),
REGULATOR_SUPPLY("DBVDD2", "spi0.1"),
REGULATOR_SUPPLY("DBVDD3", "spi0.1"),
REGULATOR_SUPPLY("LDOVDD", "spi0.1"),
REGULATOR_SUPPLY("CPVDD", "spi0.1"),
};
static struct regulator_init_data pvdd_1v8 = {
.constraints = {
.name = "PVDD_1V8",
.always_on = 1,
},
.consumer_supplies = pvdd_1v8_consumers,
.num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
};
static struct regulator_consumer_supply pvdd_3v3_consumers[] = {
REGULATOR_SUPPLY("MICVDD", "1-001a"),
REGULATOR_SUPPLY("AVDD1", "1-001a"),
};
static struct regulator_init_data pvdd_3v3 = {
.constraints = {
.name = "PVDD_3V3",
.always_on = 1,
},
.consumer_supplies = pvdd_3v3_consumers,
.num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
};
static struct wm831x_pdata glenfarclas_pmic_pdata = {
.wm831x_num = 2,
.irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
.gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
.soft_shutdown = true,
.gpio_defaults = {
/* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
[0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
[1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
[2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
},
.dcdc = {
&pvdd_1v2, /* DCDC1 */
&pvdd_1v8, /* DCDC2 */
&pvdd_3v3, /* DCDC3 */
},
.disable_touch = true,
};
static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
.gpios = {
[WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
[WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
[WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
[WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
[WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
},
};
static struct i2c_board_info i2c_devs1[] = {
{ I2C_BOARD_INFO("wm8311", 0x34),
.irq = S3C_EINT(0),
.platform_data = &glenfarclas_pmic_pdata },
{ I2C_BOARD_INFO("wlf-gf-module", 0x20) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x22) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x24) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x25) },
{ I2C_BOARD_INFO("wlf-gf-module", 0x26) },
{ I2C_BOARD_INFO("wm1250-ev1", 0x27),
.platform_data = &wm1250_ev1_pdata },
};
static struct s3c2410_platform_i2c i2c1_pdata = {
.frequency = 400000,
.bus_num = 1,
};
static void __init crag6410_map_io(void)
{
s3c64xx_init_io(NULL, 0);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
/* LCD type and Bypass set by bootloader */
}
static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_PERMANENT,
.host_caps = MMC_CAP_POWER_OFF_CARD,
};
static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
{
/* Set all the necessary GPG pins to special-function 2 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
/* force card-detected for prototype 0 */
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
}
static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
.max_width = 4,
.cd_type = S3C_SDHCI_CD_INTERNAL,
.cfg_gpio = crag6410_cfg_sdhci0,
.host_caps = MMC_CAP_POWER_OFF_CARD,
};
static const struct gpio_led gpio_leds[] = {
{
.name = "d13:green:",
.gpio = MMGPIO_GPIO_BASE + 0,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d14:green:",
.gpio = MMGPIO_GPIO_BASE + 1,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d15:green:",
.gpio = MMGPIO_GPIO_BASE + 2,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d16:green:",
.gpio = MMGPIO_GPIO_BASE + 3,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d17:green:",
.gpio = MMGPIO_GPIO_BASE + 4,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d18:green:",
.gpio = MMGPIO_GPIO_BASE + 5,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d19:green:",
.gpio = MMGPIO_GPIO_BASE + 6,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d20:green:",
.gpio = MMGPIO_GPIO_BASE + 7,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
};
static const struct gpio_led_platform_data gpio_leds_pdata = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct dwc2_hsotg_plat crag6410_hsotg_pdata;
static struct gpiod_lookup_table crag_spi0_gpiod_table = {
.dev_id = "s3c6410-spi.0",
.table = {
GPIO_LOOKUP_IDX("GPIOC", 3, "cs", 0, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("GPION", 5, "cs", 1, GPIO_ACTIVE_LOW),
{ },
},
};
static void __init crag6410_machine_init(void)
{
/* Open drain IRQs need pullups */
s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
gpio_request(S3C64XX_GPB(0), "LCD power");
gpio_direction_output(S3C64XX_GPB(0), 0);
gpio_request(S3C64XX_GPF(14), "LCD PWM");
gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
gpio_request(S3C64XX_GPB(1), "SD power");
gpio_direction_output(S3C64XX_GPB(1), 0);
gpio_request(S3C64XX_GPF(10), "nRESETSEL");
gpio_direction_output(S3C64XX_GPF(10), 1);
s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
s3c_i2c0_set_platdata(&i2c0_pdata);
s3c_i2c1_set_platdata(&i2c1_pdata);
s3c_fb_set_platdata(&crag6410_lcd_pdata);
dwc2_hsotg_set_platdata(&crag6410_hsotg_pdata);
gpiod_add_lookup_table(&crag_pmic_gpiod_table);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
samsung_keypad_set_platdata(&crag6410_keypad_data);
gpiod_add_lookup_table(&crag_spi0_gpiod_table);
s3c64xx_spi0_set_platdata(0, 2);
pwm_add_table(crag6410_pwm_lookup, ARRAY_SIZE(crag6410_pwm_lookup));
platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
gpio_led_register_device(-1, &gpio_leds_pdata);
regulator_has_full_constraints();
s3c64xx_pm_init();
}
MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
/* Maintainer: Mark Brown <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = S3C64XX_NR_IRQS,
.init_irq = s3c6410_init_irq,
.map_io = crag6410_map_io,
.init_machine = crag6410_machine_init,
.init_time = s3c64xx_timer_init,
MACHINE_END
| linux-master | arch/arm/mach-s3c/mach-crag6410.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Base S3C64XX UART resource and device definitions
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include "map.h"
#include "irqs.h"
#include "devs.h"
/* Serial port registrations */
/* 64xx uarts are closer together */
static struct resource s3c64xx_uart0_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_UART0, SZ_256),
[1] = DEFINE_RES_IRQ(IRQ_UART0),
};
static struct resource s3c64xx_uart1_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_UART1, SZ_256),
[1] = DEFINE_RES_IRQ(IRQ_UART1),
};
static struct resource s3c6xx_uart2_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_UART2, SZ_256),
[1] = DEFINE_RES_IRQ(IRQ_UART2),
};
static struct resource s3c64xx_uart3_resource[] = {
[0] = DEFINE_RES_MEM(S3C_PA_UART3, SZ_256),
[1] = DEFINE_RES_IRQ(IRQ_UART3),
};
struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
[0] = {
.resources = s3c64xx_uart0_resource,
.nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource),
},
[1] = {
.resources = s3c64xx_uart1_resource,
.nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource),
},
[2] = {
.resources = s3c6xx_uart2_resource,
.nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource),
},
[3] = {
.resources = s3c64xx_uart3_resource,
.nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource),
},
};
| linux-master | arch/arm/mach-s3c/dev-uart-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Base S3C64XX I2C bus 1 gpio configuration
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
#include "gpio-cfg.h"
#include "gpio-samsung.h"
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPB(2), 2,
S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
}
| linux-master | arch/arm/mach-s3c/setup-i2c1-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0
//
// Samsung's S3C64XX flattened device tree enabled machine
//
// Copyright (c) 2013 Tomasz Figa <[email protected]>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include "cpu.h"
#include "map.h"
#include "s3c64xx.h"
/*
* IO mapping for shared system controller IP.
*
* FIXME: Make remaining drivers use dynamic mapping.
*/
static struct map_desc s3c64xx_dt_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void __init s3c64xx_dt_map_io(void)
{
debug_ll_io_init();
iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc));
s3c64xx_init_cpu();
if (!soc_is_s3c64xx())
panic("SoC is not S3C64xx!");
}
static const char *const s3c64xx_dt_compat[] __initconst = {
"samsung,s3c6400",
"samsung,s3c6410",
NULL
};
DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)")
/* Maintainer: Tomasz Figa <[email protected]> */
.dt_compat = s3c64xx_dt_compat,
.map_io = s3c64xx_dt_map_io,
MACHINE_END
| linux-master | arch/arm/mach-s3c/mach-s3c64xx-dt.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Simtec Electronics
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <linux/soc/samsung/s3c-pm.h>
#include "regs-clock.h"
#include "cpu.h"
#include "devs.h"
#include "sdhci.h"
#include "iic-core.h"
#include "s3c64xx.h"
void __init s3c6410_map_io(void)
{
/* initialise device information early */
s3c6410_default_sdhci0();
s3c6410_default_sdhci1();
s3c6410_default_sdhci2();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
}
void __init s3c6410_init_irq(void)
{
/* VIC0 is missing IRQ7, VIC1 is fully populated. */
s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
}
struct bus_type s3c6410_subsys = {
.name = "s3c6410-core",
.dev_name = "s3c6410-core",
};
static struct device s3c6410_dev = {
.bus = &s3c6410_subsys,
};
static int __init s3c6410_core_init(void)
{
/* Not applicable when using DT. */
if (of_have_populated_dt() || !soc_is_s3c64xx())
return 0;
return subsys_system_register(&s3c6410_subsys, NULL);
}
core_initcall(s3c6410_core_init);
int __init s3c6410_init(void)
{
printk("S3C6410: Initialising architecture\n");
return device_register(&s3c6410_dev);
}
| linux-master | arch/arm/mach-s3c/s3c6410.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2010 Ben Dooks <[email protected]>
//
// Support for wakeup mask interrupts on newer SoCs
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/io.h>
#include "wakeup-mask.h"
#include "pm.h"
void samsung_sync_wakemask(void __iomem *reg,
const struct samsung_wakeup_mask *mask, int nr_mask)
{
struct irq_data *data;
u32 val;
val = __raw_readl(reg);
for (; nr_mask > 0; nr_mask--, mask++) {
if (mask->irq == NO_WAKEUP_IRQ) {
val |= mask->bit;
continue;
}
data = irq_get_irq_data(mask->irq);
/* bit of a liberty to read this directly from irq_data. */
if (irqd_is_wakeup_set(data))
val &= ~mask->bit;
else
val |= mask->bit;
}
printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val);
__raw_writel(val, reg);
}
| linux-master | arch/arm/mach-s3c/wakeup-mask.c |
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
// Ben Dooks <[email protected]>
// http://armlinux.simtec.co.uk/
//
// Base S3C64XX I2C bus 0 gpio configuration
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
#include "gpio-cfg.h"
#include "gpio-samsung.h"
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPB(5), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
| linux-master | arch/arm/mach-s3c/setup-i2c0-s3c64xx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QNAP TS-109/TS-209 Board Setup
*
* Maintainer: Byron Bradley <[email protected]>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/rawnand.h>
#include <linux/mv643xx_eth.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/serial_reg.h>
#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
#include "tsx09-common.h"
#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
/****************************************************************************
* 8MiB NOR flash. The struct mtd_partition is not in the same order as the
* partitions on the device because we want to keep compatibility with
* existing QNAP firmware.
*
* Layout as used by QNAP:
* [2] 0x00000000-0x00200000 : "Kernel"
* [3] 0x00200000-0x00600000 : "RootFS1"
* [4] 0x00600000-0x00700000 : "RootFS2"
* [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
* [5] 0x00760000-0x00780000 : "U-Boot Config"
* [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
***************************************************************************/
static struct mtd_partition qnap_ts209_partitions[] = {
{
.name = "U-Boot",
.size = 0x00080000,
.offset = 0x00780000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.size = 0x00200000,
.offset = 0,
}, {
.name = "RootFS1",
.size = 0x00400000,
.offset = 0x00200000,
}, {
.name = "RootFS2",
.size = 0x00100000,
.offset = 0x00600000,
}, {
.name = "U-Boot Config",
.size = 0x00020000,
.offset = 0x00760000,
}, {
.name = "NAS Config",
.size = 0x00060000,
.offset = 0x00700000,
.mask_flags = MTD_WRITEABLE,
},
};
static struct physmap_flash_data qnap_ts209_nor_flash_data = {
.width = 1,
.parts = qnap_ts209_partitions,
.nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
};
static struct resource qnap_ts209_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = QNAP_TS209_NOR_BOOT_BASE,
.end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
};
static struct platform_device qnap_ts209_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &qnap_ts209_nor_flash_data,
},
.resource = &qnap_ts209_nor_flash_resource,
.num_resources = 1,
};
/*****************************************************************************
* PCI
****************************************************************************/
#define QNAP_TS209_PCI_SLOT0_OFFS 7
#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
static void __init qnap_ts209_pci_preinit(void)
{
int pin;
/*
* Configure PCI GPIO IRQ pins
*/
pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
"set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
"%d\n", pin);
}
pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) {
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed "
"to set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
"%d\n", pin);
}
}
static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
/*
* PCI IRQs are connected via GPIOs.
*/
switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) {
case 0:
return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN);
case 1:
return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN);
default:
return -1;
}
}
static struct hw_pci qnap_ts209_pci __initdata = {
.nr_controllers = 2,
.preinit = qnap_ts209_pci_preinit,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = qnap_ts209_pci_map_irq,
};
static int __init qnap_ts209_pci_init(void)
{
if (machine_is_ts209())
pci_common_init(&qnap_ts209_pci);
return 0;
}
subsys_initcall(qnap_ts209_pci_init);
/*****************************************************************************
* RTC S35390A on I2C bus
****************************************************************************/
#define TS209_RTC_GPIO 3
static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
I2C_BOARD_INFO("s35390a", 0x30),
.irq = 0,
};
/****************************************************************************
* GPIO Attached Keys
* Power button is attached to the PIC microcontroller
****************************************************************************/
#define QNAP_TS209_GPIO_KEY_MEDIA 1
#define QNAP_TS209_GPIO_KEY_RESET 2
static struct gpio_keys_button qnap_ts209_buttons[] = {
{
.code = KEY_COPY,
.gpio = QNAP_TS209_GPIO_KEY_MEDIA,
.desc = "USB Copy Button",
.active_low = 1,
}, {
.code = KEY_RESTART,
.gpio = QNAP_TS209_GPIO_KEY_RESET,
.desc = "Reset Button",
.active_low = 1,
},
};
static struct gpio_keys_platform_data qnap_ts209_button_data = {
.buttons = qnap_ts209_buttons,
.nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
};
static struct platform_device qnap_ts209_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &qnap_ts209_button_data,
},
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data qnap_ts209_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int ts209_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_GPIO, /* USB copy button */
MPP2_GPIO, /* Load defaults button */
MPP3_GPIO, /* GPIO RTC */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_GPIO, /* PCI Int A */
MPP7_GPIO, /* PCI Int B */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_GPIO, /* SW_RST */
MPP19_UNUSED,
0,
};
static void __init qnap_ts209_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(ts209_mpp_modes);
/*
* MPP[20] PCI clock 0
* MPP[21] PCI clock 1
* MPP[22] USB 0 over current
* MPP[23-25] Reserved
*/
/*
* Configure peripherals.
*/
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
QNAP_TS209_NOR_BOOT_BASE,
QNAP_TS209_NOR_BOOT_SIZE);
platform_device_register(&qnap_ts209_nor_flash);
orion5x_ehci0_init();
orion5x_ehci1_init();
qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
qnap_ts209_partitions[5].offset,
qnap_ts209_partitions[5].size);
orion5x_eth_init(&qnap_tsx09_eth_data);
orion5x_i2c_init();
orion5x_sata_init(&qnap_ts209_sata_data);
orion5x_uart0_init();
orion5x_uart1_init();
orion5x_xor_init();
platform_device_register(&qnap_ts209_button_device);
/* Get RTC IRQ and register the chip */
if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
if (gpio_direction_input(TS209_RTC_GPIO) == 0)
qnap_ts209_i2c_rtc.irq = gpio_to_irq(TS209_RTC_GPIO);
else
gpio_free(TS209_RTC_GPIO);
}
if (qnap_ts209_i2c_rtc.irq == 0)
pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
/* register tsx09 specific power-off method */
pm_power_off = qnap_tsx09_power_off;
}
MACHINE_START(TS209, "QNAP TS-109/TS-209")
/* Maintainer: Byron Bradley <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = qnap_ts209_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/ts209-setup.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/mpp.c
*
* MPP functions for Marvell Orion 5x SoCs
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <plat/mpp.h>
#include "orion5x.h"
#include "mpp.h"
#include "common.h"
static unsigned int __init orion5x_variant(void)
{
u32 dev;
u32 rev;
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID)
return MPP_F5181_MASK;
if (dev == MV88F5182_DEV_ID)
return MPP_F5182_MASK;
if (dev == MV88F5281_DEV_ID)
return MPP_F5281_MASK;
printk(KERN_ERR "MPP setup: unknown orion5x variant "
"(dev %#x rev %#x)\n", dev, rev);
return 0;
}
void __init orion5x_mpp_conf(unsigned int *mpp_list)
{
orion_mpp_conf(mpp_list, orion5x_variant(),
MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
}
| linux-master | arch/arm/mach-orion5x/mpp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/common.c
*
* Core functions for Marvell Orion 5x SoCs
*
* Maintainer: Tzachi Perelstein <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/system_misc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <linux/platform_data/mtd-orion_nand.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <plat/time.h>
#include <plat/common.h>
#include "bridge-regs.h"
#include "common.h"
#include "orion5x.h"
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc orion5x_io_desc[] __initdata = {
{
.virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
.length = ORION5X_REGS_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
.length = ORION5X_PCIE_WA_SIZE,
.type = MT_DEVICE,
},
};
void __init orion5x_map_io(void)
{
iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}
/*****************************************************************************
* CLK tree
****************************************************************************/
static struct clk *tclk;
void __init clk_init(void)
{
tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk);
orion_clkdev_init(tclk);
}
/*****************************************************************************
* EHCI0
****************************************************************************/
void __init orion5x_ehci0_init(void)
{
orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
EHCI_PHY_ORION);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
void __init orion5x_ehci1_init(void)
{
orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
}
/*****************************************************************************
* GE00
****************************************************************************/
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
orion_ge00_init(eth_data,
ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
IRQ_ORION5X_ETH_ERR,
MV643XX_TX_CSUM_DEFAULT_LIMIT);
}
/*****************************************************************************
* I2C
****************************************************************************/
void __init orion5x_i2c_init(void)
{
orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
}
/*****************************************************************************
* SATA
****************************************************************************/
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
}
/*****************************************************************************
* SPI
****************************************************************************/
void __init orion5x_spi_init(void)
{
orion_spi_init(SPI_PHYS_BASE);
}
/*****************************************************************************
* UART0
****************************************************************************/
void __init orion5x_uart0_init(void)
{
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
IRQ_ORION5X_UART0, tclk);
}
/*****************************************************************************
* UART1
****************************************************************************/
void __init orion5x_uart1_init(void)
{
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
IRQ_ORION5X_UART1, tclk);
}
/*****************************************************************************
* XOR engine
****************************************************************************/
void __init orion5x_xor_init(void)
{
orion_xor0_init(ORION5X_XOR_PHYS_BASE,
ORION5X_XOR_PHYS_BASE + 0x200,
IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
}
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
static void __init orion5x_crypto_init(void)
{
mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
ORION_MBUS_SRAM_ATTR,
ORION5X_SRAM_PHYS_BASE,
ORION5X_SRAM_SIZE);
orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
SZ_8K, IRQ_ORION5X_CESA);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct resource orion_wdt_resource[] = {
DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
};
static struct platform_device orion_wdt_device = {
.name = "orion_wdt",
.id = -1,
.num_resources = ARRAY_SIZE(orion_wdt_resource),
.resource = orion_wdt_resource,
};
static void __init orion5x_wdt_init(void)
{
platform_device_register(&orion_wdt_device);
}
/*****************************************************************************
* Time handling
****************************************************************************/
void __init orion5x_init_early(void)
{
u32 rev, dev;
const char *mbus_soc_name;
orion_time_set_base(TIMER_VIRT_BASE);
/* Initialize the MBUS driver */
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5281_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f5281-mbus";
else if (dev == MV88F5182_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f5182-mbus";
else if (dev == MV88F5181_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f5181-mbus";
else if (dev == MV88F6183_DEV_ID)
mbus_soc_name = "marvell,orion5x-88f6183-mbus";
else
mbus_soc_name = NULL;
mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
ORION5X_BRIDGE_WINS_SZ,
ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
}
void orion5x_setup_wins(void)
{
/*
* The PCIe windows will no longer be statically allocated
* here once Orion5x is migrated to the pci-mvebu driver.
*/
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
ORION_MBUS_PCIE_IO_ATTR,
ORION5X_PCIE_IO_PHYS_BASE,
ORION5X_PCIE_IO_SIZE,
ORION5X_PCIE_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
ORION_MBUS_PCIE_MEM_ATTR,
ORION5X_PCIE_MEM_PHYS_BASE,
ORION5X_PCIE_MEM_SIZE);
mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
ORION_MBUS_PCI_IO_ATTR,
ORION5X_PCI_IO_PHYS_BASE,
ORION5X_PCI_IO_SIZE,
ORION5X_PCI_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
ORION_MBUS_PCI_MEM_ATTR,
ORION5X_PCI_MEM_PHYS_BASE,
ORION5X_PCI_MEM_SIZE);
}
int orion5x_tclk;
static int __init orion5x_find_tclk(void)
{
u32 dev, rev;
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F6183_DEV_ID &&
(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
return 133333333;
return 166666667;
}
void __init orion5x_timer_init(void)
{
orion5x_tclk = orion5x_find_tclk();
orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
IRQ_ORION5X_BRIDGE, orion5x_tclk);
}
/*****************************************************************************
* General
****************************************************************************/
/*
* Identify device ID and rev from PCIe configuration header space '0'.
*/
void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
orion5x_pcie_id(dev, rev);
if (*dev == MV88F5281_DEV_ID) {
if (*rev == MV88F5281_REV_D2) {
*dev_name = "MV88F5281-D2";
} else if (*rev == MV88F5281_REV_D1) {
*dev_name = "MV88F5281-D1";
} else if (*rev == MV88F5281_REV_D0) {
*dev_name = "MV88F5281-D0";
} else {
*dev_name = "MV88F5281-Rev-Unsupported";
}
} else if (*dev == MV88F5182_DEV_ID) {
if (*rev == MV88F5182_REV_A2) {
*dev_name = "MV88F5182-A2";
} else {
*dev_name = "MV88F5182-Rev-Unsupported";
}
} else if (*dev == MV88F5181_DEV_ID) {
if (*rev == MV88F5181_REV_B1) {
*dev_name = "MV88F5181-Rev-B1";
} else if (*rev == MV88F5181L_REV_A1) {
*dev_name = "MV88F5181L-Rev-A1";
} else {
*dev_name = "MV88F5181(L)-Rev-Unsupported";
}
} else if (*dev == MV88F6183_DEV_ID) {
if (*rev == MV88F6183_REV_B0) {
*dev_name = "MV88F6183-Rev-B0";
} else {
*dev_name = "MV88F6183-Rev-Unsupported";
}
} else {
*dev_name = "Device-Unknown";
}
}
void __init orion5x_init(void)
{
char *dev_name;
u32 dev, rev;
orion5x_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
/*
* Setup Orion address map
*/
orion5x_setup_wins();
/* Setup root of clk tree */
clk_init();
/*
* Don't issue "Wait for Interrupt" instruction if we are
* running on D0 5281 silicon.
*/
if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
cpu_idle_poll_ctrl(true);
}
/*
* The 5082/5181l/5182/6082/6082l/6183 have crypto
* while 5180n/5181/5281 don't have crypto.
*/
if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
orion5x_crypto_init();
/*
* Register watchdog driver
*/
orion5x_wdt_init();
}
void orion5x_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Enable and issue soft reset
*/
orion5x_setbits(RSTOUTn_MASK, (1 << 2));
orion5x_setbits(CPU_SOFT_RESET, 1);
mdelay(200);
orion5x_clrbits(CPU_SOFT_RESET, 1);
}
/*
* Many orion-based systems have buggy bootloader implementations.
* This is a common fixup for bogus memory tags.
*/
void __init tag_fixup_mem32(struct tag *t, char **from)
{
for (; t->hdr.size; t = tag_next(t))
if (t->hdr.tag == ATAG_MEM &&
(!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
t->u.mem.start & ~PAGE_MASK)) {
printk(KERN_WARNING
"Clearing invalid memory bank %dKB@0x%08x\n",
t->u.mem.size / 1024, t->u.mem.start);
t->hdr.tag = 0;
}
}
| linux-master | arch/arm/mach-orion5x/common.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/kurobox_pro-setup.c
*
* Maintainer: Ronen Shitrit <[email protected]>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/rawnand.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <linux/serial_reg.h>
#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <linux/platform_data/mtd-orion_nand.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
/*****************************************************************************
* KUROBOX-PRO Info
****************************************************************************/
/*
* 256K NOR flash Device bus boot chip select
*/
#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000
#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K
/*
* 256M NAND flash on Device bus chip select 1
*/
#define KUROBOX_PRO_NAND_BASE 0xfc000000
#define KUROBOX_PRO_NAND_SIZE SZ_2M
/*****************************************************************************
* 256MB NAND Flash on Device bus CS0
****************************************************************************/
static struct mtd_partition kurobox_pro_nand_parts[] = {
{
.name = "uImage",
.offset = 0,
.size = SZ_4M,
}, {
.name = "rootfs",
.offset = SZ_4M,
.size = SZ_64M,
}, {
.name = "extra",
.offset = SZ_4M + SZ_64M,
.size = SZ_256M - (SZ_4M + SZ_64M),
},
};
static struct resource kurobox_pro_nand_resource = {
.flags = IORESOURCE_MEM,
.start = KUROBOX_PRO_NAND_BASE,
.end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1,
};
static struct orion_nand_data kurobox_pro_nand_data = {
.parts = kurobox_pro_nand_parts,
.nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts),
.cle = 0,
.ale = 1,
.width = 8,
};
static struct platform_device kurobox_pro_nand_flash = {
.name = "orion_nand",
.id = -1,
.dev = {
.platform_data = &kurobox_pro_nand_data,
},
.resource = &kurobox_pro_nand_resource,
.num_resources = 1,
};
/*****************************************************************************
* 256KB NOR Flash on BOOT Device
****************************************************************************/
static struct physmap_flash_data kurobox_pro_nor_flash_data = {
.width = 1,
};
static struct resource kurobox_pro_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = KUROBOX_PRO_NOR_BOOT_BASE,
.end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1,
};
static struct platform_device kurobox_pro_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &kurobox_pro_nor_flash_data,
},
.num_resources = 1,
.resource = &kurobox_pro_nor_flash_resource,
};
/*****************************************************************************
* PCI
****************************************************************************/
static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
/*
* PCI isn't used on the Kuro
*/
return -1;
}
static struct hw_pci kurobox_pro_pci __initdata = {
.nr_controllers = 2,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = kurobox_pro_pci_map_irq,
};
static int __init kurobox_pro_pci_init(void)
{
if (machine_is_kurobox_pro()) {
orion5x_pci_disable();
pci_common_init(&kurobox_pro_pci);
}
return 0;
}
subsys_initcall(kurobox_pro_pci_init);
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
/*****************************************************************************
* RTC 5C372a on I2C bus
****************************************************************************/
static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
I2C_BOARD_INFO("rs5c372a", 0x32),
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data kurobox_pro_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* Kurobox Pro specific power off method via UART1-attached microcontroller
****************************************************************************/
#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
static int kurobox_pro_miconread(unsigned char *buf, int count)
{
int i;
int timeout;
for (i = 0; i < count; i++) {
timeout = 10;
while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
if (--timeout == 0)
break;
udelay(1000);
}
if (timeout == 0)
break;
buf[i] = readl(UART1_REG(RX));
}
/* return read bytes */
return i;
}
static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
{
int i = 0;
while (count--) {
while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
barrier();
writel(buf[i++], UART1_REG(TX));
}
return 0;
}
static int kurobox_pro_miconsend(const unsigned char *data, int count)
{
int i;
unsigned char checksum = 0;
unsigned char recv_buf[40];
unsigned char send_buf[40];
unsigned char correct_ack[3];
int retry = 2;
/* Generate checksum */
for (i = 0; i < count; i++)
checksum -= data[i];
do {
/* Send data */
kurobox_pro_miconwrite(data, count);
/* send checksum */
kurobox_pro_miconwrite(&checksum, 1);
if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
printk(KERN_ERR ">%s: receive failed.\n", __func__);
/* send preamble to clear the receive buffer */
memset(&send_buf, 0xff, sizeof(send_buf));
kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
/* make dummy reads */
mdelay(100);
kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
} else {
/* Generate expected ack */
correct_ack[0] = 0x01;
correct_ack[1] = data[1];
correct_ack[2] = 0x00;
/* checksum Check */
if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
recv_buf[3]) & 0xFF) {
printk(KERN_ERR ">%s: Checksum Error : "
"Received data[%02x, %02x, %02x, %02x]"
"\n", __func__, recv_buf[0],
recv_buf[1], recv_buf[2], recv_buf[3]);
} else {
/* Check Received Data */
if (correct_ack[0] == recv_buf[0] &&
correct_ack[1] == recv_buf[1] &&
correct_ack[2] == recv_buf[2]) {
/* Interval for next command */
mdelay(10);
/* Receive ACK */
return 0;
}
}
/* Received NAK or illegal Data */
printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
"Received\n", __func__);
}
} while (retry--);
/* Interval for next command */
mdelay(10);
return -1;
}
static void kurobox_pro_power_off(void)
{
const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
const unsigned char shutdownwait[] = {0x00, 0x0c};
const unsigned char poweroff[] = {0x00, 0x06};
/* 38400 baud divisor */
const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
pr_info("%s: triggering power-off...\n", __func__);
/* hijack uart1 and reset into sane state (38400,8n1,even parity) */
writel(0x83, UART1_REG(LCR));
writel(divisor & 0xff, UART1_REG(DLL));
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
writel(0x1b, UART1_REG(LCR));
writel(0x00, UART1_REG(IER));
writel(0x07, UART1_REG(FCR));
writel(0x00, UART1_REG(MCR));
/* Send the commands to shutdown the Kurobox Pro */
kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
kurobox_pro_miconsend(poweroff, sizeof(poweroff));
}
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int kurobox_pro_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_UNUSED,
MPP2_GPIO, /* GPIO Micon */
MPP3_GPIO, /* GPIO Rtc */
MPP4_UNUSED,
MPP5_UNUSED,
MPP6_NAND, /* NAND Flash REn */
MPP7_NAND, /* NAND Flash WEn */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_UART, /* UART1 CTSn */
MPP19_UART, /* UART1 RTSn */
0,
};
static void __init kurobox_pro_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(kurobox_pro_mpp_modes);
/*
* Configure peripherals.
*/
orion5x_ehci0_init();
orion5x_ehci1_init();
orion5x_eth_init(&kurobox_pro_eth_data);
orion5x_i2c_init();
orion5x_sata_init(&kurobox_pro_sata_data);
orion5x_uart0_init();
orion5x_uart1_init();
orion5x_xor_init();
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
KUROBOX_PRO_NOR_BOOT_BASE,
KUROBOX_PRO_NOR_BOOT_SIZE);
platform_device_register(&kurobox_pro_nor_flash);
if (machine_is_kurobox_pro()) {
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
ORION_MBUS_DEVBUS_ATTR(0),
KUROBOX_PRO_NAND_BASE,
KUROBOX_PRO_NAND_SIZE);
platform_device_register(&kurobox_pro_nand_flash);
}
i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
/* register Kurobox Pro specific power-off method */
pm_power_off = kurobox_pro_power_off;
}
#ifdef CONFIG_MACH_KUROBOX_PRO
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
#endif
#ifdef CONFIG_MACH_LINKSTATION_PRO
MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
/* Maintainer: Byron Bradley <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = kurobox_pro_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
#endif
| linux-master | arch/arm/mach-orion5x/kurobox_pro-setup.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/board-d2net.c
*
* LaCie d2Network and Big Disk Network NAS setup
*
* Copyright (C) 2009 Simon Guinot <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <plat/orion-gpio.h>
#include "common.h"
#include "orion5x.h"
/*****************************************************************************
* LaCie d2 Network Info
****************************************************************************/
/*****************************************************************************
* GPIO LED's
****************************************************************************/
/*
* The blue front LED is wired to the CPLD and can blink in relation with the
* SATA activity.
*
* The following array detail the different LED registers and the combination
* of their possible values:
*
* led_off | blink_ctrl | SATA active | LED state
* | | |
* 1 | x | x | off
* 0 | 0 | 0 | off
* 0 | 1 | 0 | blink (rate 300ms)
* 0 | x | 1 | on
*
* Notes: The blue and the red front LED's can't be on at the same time.
* Red LED have priority.
*/
#define D2NET_GPIO_RED_LED 6
#define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16
#define D2NET_GPIO_BLUE_LED_OFF 23
static struct gpio_led d2net_leds[] = {
{
.name = "d2net:blue:sata",
.default_trigger = "default-on",
.gpio = D2NET_GPIO_BLUE_LED_OFF,
.active_low = 1,
},
{
.name = "d2net:red:fail",
.gpio = D2NET_GPIO_RED_LED,
},
};
static struct gpio_led_platform_data d2net_led_data = {
.num_leds = ARRAY_SIZE(d2net_leds),
.leds = d2net_leds,
};
static struct platform_device d2net_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &d2net_led_data,
},
};
static void __init d2net_gpio_leds_init(void)
{
int err;
/* Configure register blink_ctrl to allow SATA activity LED blinking. */
err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink");
if (err == 0) {
err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1);
if (err)
gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL);
}
if (err)
pr_err("d2net: failed to configure blue LED blink GPIO\n");
platform_device_register(&d2net_gpio_leds);
}
/*****************************************************************************
* General Setup
****************************************************************************/
void __init d2net_init(void)
{
d2net_gpio_leds_init();
pr_notice("d2net: Flash write are not yet supported.\n");
}
| linux-master | arch/arm/mach-orion5x/board-d2net.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/rd88f5182-setup.c
*
* Marvell Orion-NAS Reference Design Setup
*
* Maintainer: Ronen Shitrit <[email protected]>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include "common.h"
#include "orion5x.h"
/*****************************************************************************
* RD-88F5182 Info
****************************************************************************/
/*
* PCI
*/
#define RD88F5182_PCI_SLOT0_OFFS 7
#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
/*****************************************************************************
* PCI
****************************************************************************/
static void __init rd88f5182_pci_preinit(void)
{
int pin;
/*
* Configure PCI GPIO IRQ pins
*/
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
if (gpio_request(pin, "PCI IntA") == 0) {
if (gpio_direction_input(pin) == 0) {
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit failed to "
"set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
}
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
if (gpio_request(pin, "PCI IntB") == 0) {
if (gpio_direction_input(pin) == 0) {
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "rd88f5182_pci_preinit failed to "
"set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
}
}
static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
/*
* PCI IRQs are connected via GPIOs
*/
switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
case 0:
if (pin == 1)
return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
else
return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
default:
return -1;
}
}
static struct hw_pci rd88f5182_pci __initdata = {
.nr_controllers = 2,
.preinit = rd88f5182_pci_preinit,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = rd88f5182_pci_map_irq,
};
static int __init rd88f5182_pci_init(void)
{
if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
pci_common_init(&rd88f5182_pci);
return 0;
}
subsys_initcall(rd88f5182_pci_init);
| linux-master | arch/arm/mach-orion5x/board-rd88f5182.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2012 (C), Thomas Petazzoni <[email protected]>
*
* arch/arm/mach-orion5x/board-dt.c
*
* Flattened Device Tree board initialization
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/cpu.h>
#include <linux/mbus.h>
#include <linux/clocksource.h>
#include <asm/system_misc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat/irq.h>
#include <plat/time.h>
#include "orion5x.h"
#include "bridge-regs.h"
#include "common.h"
static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
NULL),
OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1090000, "mv_crypto", NULL),
{},
};
static void __init orion5x_dt_init(void)
{
char *dev_name;
u32 dev, rev;
orion5x_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
BUG_ON(mvebu_mbus_dt_init(false));
/*
* Setup Orion address map
*/
orion5x_setup_wins();
/*
* Don't issue "Wait for Interrupt" instruction if we are
* running on D0 5281 silicon.
*/
if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
cpu_idle_poll_ctrl(true);
}
if (of_machine_is_compatible("maxtor,shared-storage-2"))
mss2_init();
if (of_machine_is_compatible("lacie,d2-network"))
d2net_init();
of_platform_default_populate(NULL, orion5x_auxdata_lookup, NULL);
}
static const char *orion5x_dt_compat[] = {
"marvell,orion5x",
NULL,
};
DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
/* Maintainer: Thomas Petazzoni <[email protected]> */
.map_io = orion5x_map_io,
.init_machine = orion5x_dt_init,
.restart = orion5x_restart,
.dt_compat = orion5x_dt_compat,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/board-dt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QNAP TS-409 Board Setup
*
* Maintainer: Sylver Bruneau <[email protected]>
*
* Copyright (C) 2008 Sylver Bruneau <[email protected]>
* Copyright (C) 2008 Martin Michlmayr <[email protected]>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/serial_reg.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
#include "tsx09-common.h"
/*****************************************************************************
* QNAP TS-409 Info
****************************************************************************/
/*
* QNAP TS-409 hardware :
* - Marvell 88F5281-D0
* - Marvell 88SX7042 SATA controller (PCIe)
* - Marvell 88E1118 Gigabit Ethernet PHY
* - RTC S35390A (@0x30) on I2C bus
* - 8MB NOR flash
* - 256MB of DDR-2 RAM
*/
/*
* 8MB NOR flash Device bus boot chip select
*/
#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
/****************************************************************************
* 8MiB NOR flash. The struct mtd_partition is not in the same order as the
* partitions on the device because we want to keep compatibility with
* existing QNAP firmware.
*
* Layout as used by QNAP:
* [2] 0x00000000-0x00200000 : "Kernel"
* [3] 0x00200000-0x00600000 : "RootFS1"
* [4] 0x00600000-0x00700000 : "RootFS2"
* [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
* [5] 0x00760000-0x00780000 : "U-Boot Config"
* [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
***************************************************************************/
static struct mtd_partition qnap_ts409_partitions[] = {
{
.name = "U-Boot",
.size = 0x00080000,
.offset = 0x00780000,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "Kernel",
.size = 0x00200000,
.offset = 0,
}, {
.name = "RootFS1",
.size = 0x00400000,
.offset = 0x00200000,
}, {
.name = "RootFS2",
.size = 0x00100000,
.offset = 0x00600000,
}, {
.name = "U-Boot Config",
.size = 0x00020000,
.offset = 0x00760000,
}, {
.name = "NAS Config",
.size = 0x00060000,
.offset = 0x00700000,
.mask_flags = MTD_WRITEABLE,
},
};
static struct physmap_flash_data qnap_ts409_nor_flash_data = {
.width = 1,
.parts = qnap_ts409_partitions,
.nr_parts = ARRAY_SIZE(qnap_ts409_partitions)
};
static struct resource qnap_ts409_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = QNAP_TS409_NOR_BOOT_BASE,
.end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
};
static struct platform_device qnap_ts409_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = { .platform_data = &qnap_ts409_nor_flash_data, },
.num_resources = 1,
.resource = &qnap_ts409_nor_flash_resource,
};
/*****************************************************************************
* PCI
****************************************************************************/
static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
/*
* PCI isn't used on the TS-409
*/
return -1;
}
static struct hw_pci qnap_ts409_pci __initdata = {
.nr_controllers = 2,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = qnap_ts409_pci_map_irq,
};
static int __init qnap_ts409_pci_init(void)
{
if (machine_is_ts409())
pci_common_init(&qnap_ts409_pci);
return 0;
}
subsys_initcall(qnap_ts409_pci_init);
/*****************************************************************************
* RTC S35390A on I2C bus
****************************************************************************/
#define TS409_RTC_GPIO 10
static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
I2C_BOARD_INFO("s35390a", 0x30),
};
/*****************************************************************************
* LEDs attached to GPIO
****************************************************************************/
static struct gpio_led ts409_led_pins[] = {
{
.name = "ts409:red:sata1",
.gpio = 4,
.active_low = 1,
}, {
.name = "ts409:red:sata2",
.gpio = 5,
.active_low = 1,
}, {
.name = "ts409:red:sata3",
.gpio = 6,
.active_low = 1,
}, {
.name = "ts409:red:sata4",
.gpio = 7,
.active_low = 1,
},
};
static struct gpio_led_platform_data ts409_led_data = {
.leds = ts409_led_pins,
.num_leds = ARRAY_SIZE(ts409_led_pins),
};
static struct platform_device ts409_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &ts409_led_data,
},
};
/****************************************************************************
* GPIO Attached Keys
* Power button is attached to the PIC microcontroller
****************************************************************************/
#define QNAP_TS409_GPIO_KEY_RESET 14
#define QNAP_TS409_GPIO_KEY_MEDIA 15
static struct gpio_keys_button qnap_ts409_buttons[] = {
{
.code = KEY_RESTART,
.gpio = QNAP_TS409_GPIO_KEY_RESET,
.desc = "Reset Button",
.active_low = 1,
}, {
.code = KEY_COPY,
.gpio = QNAP_TS409_GPIO_KEY_MEDIA,
.desc = "USB Copy Button",
.active_low = 1,
},
};
static struct gpio_keys_platform_data qnap_ts409_button_data = {
.buttons = qnap_ts409_buttons,
.nbuttons = ARRAY_SIZE(qnap_ts409_buttons),
};
static struct platform_device qnap_ts409_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &qnap_ts409_button_data,
},
};
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int ts409_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_UNUSED,
MPP2_UNUSED,
MPP3_UNUSED,
MPP4_GPIO, /* HDD 1 status */
MPP5_GPIO, /* HDD 2 status */
MPP6_GPIO, /* HDD 3 status */
MPP7_GPIO, /* HDD 4 status */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_GPIO, /* RTC int */
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_GPIO, /* SW_RST */
MPP15_GPIO, /* USB copy button */
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static void __init qnap_ts409_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(ts409_mpp_modes);
/*
* Configure peripherals.
*/
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
QNAP_TS409_NOR_BOOT_BASE,
QNAP_TS409_NOR_BOOT_SIZE);
platform_device_register(&qnap_ts409_nor_flash);
orion5x_ehci0_init();
qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
qnap_ts409_partitions[5].offset,
qnap_ts409_partitions[5].size);
orion5x_eth_init(&qnap_tsx09_eth_data);
orion5x_i2c_init();
orion5x_uart0_init();
orion5x_uart1_init();
platform_device_register(&qnap_ts409_button_device);
/* Get RTC IRQ and register the chip */
if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
if (gpio_direction_input(TS409_RTC_GPIO) == 0)
qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
else
gpio_free(TS409_RTC_GPIO);
}
if (qnap_ts409_i2c_rtc.irq == 0)
pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
platform_device_register(&ts409_leds);
/* register tsx09 specific power-off method */
pm_power_off = qnap_tsx09_power_off;
}
MACHINE_START(TS409, "QNAP TS-409")
/* Maintainer: Sylver Bruneau <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = qnap_ts409_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/ts409-setup.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/irq.c
*
* Core IRQ functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <[email protected]>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <plat/orion-gpio.h>
#include <plat/irq.h>
#include <asm/exception.h>
#include "bridge-regs.h"
#include "common.h"
static int __initdata gpio0_irqs[4] = {
IRQ_ORION5X_GPIO_0_7,
IRQ_ORION5X_GPIO_8_15,
IRQ_ORION5X_GPIO_16_23,
IRQ_ORION5X_GPIO_24_31,
};
static asmlinkage void
__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
{
u32 stat;
stat = readl_relaxed(MAIN_IRQ_CAUSE);
stat &= readl_relaxed(MAIN_IRQ_MASK);
if (stat) {
unsigned int hwirq = 1 + __fls(stat);
handle_IRQ(hwirq, regs);
return;
}
}
void __init orion5x_init_irq(void)
{
orion_irq_init(1, MAIN_IRQ_MASK);
set_handle_irq(orion5x_legacy_handle_irq);
/*
* Initialize gpiolib for GPIOs 0-31.
*/
orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0,
IRQ_ORION5X_GPIO_START, gpio0_irqs);
}
| linux-master | arch/arm/mach-orion5x/irq.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/pci.c
*
* PCI and PCIe functions for Marvell Orion System On Chip
*
* Maintainer: Tzachi Perelstein <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <plat/addr-map.h>
#include "common.h"
#include "orion5x.h"
/*****************************************************************************
* Orion has one PCIe controller and one PCI controller.
*
* Note1: The local PCIe bus number is '0'. The local PCI bus number
* follows the scanned PCIe bridged busses, if any.
*
* Note2: It is possible for PCI/PCIe agents to access many subsystem's
* space, by configuring BARs and Address Decode Windows, e.g. flashes on
* device bus, Orion registers, etc. However this code only enable the
* access to DDR banks.
****************************************************************************/
/*****************************************************************************
* PCIe controller
****************************************************************************/
#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
void __init orion5x_pcie_id(u32 *dev, u32 *rev)
{
*dev = orion_pcie_dev_id(PCIE_BASE);
*rev = orion_pcie_rev(PCIE_BASE);
}
static int pcie_valid_config(int bus, int dev)
{
/*
* Don't go out when trying to access --
* 1. nonexisting device on local bus
* 2. where there's no device connected (no link)
*/
if (bus == 0 && dev == 0)
return 1;
if (!orion_pcie_link_up(PCIE_BASE))
return 0;
if (bus == 0 && dev != 1)
return 0;
return 1;
}
/*
* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
* and then reading the PCIE_CONF_DATA register. Need to make sure these
* transactions are atomic.
*/
static DEFINE_SPINLOCK(orion5x_pcie_lock);
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
unsigned long flags;
int ret;
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
spin_lock_irqsave(&orion5x_pcie_lock, flags);
ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
return ret;
}
static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
int ret;
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
/*
* We only support access to the non-extended configuration
* space when using the WA access method (or we would have to
* sacrifice 256M of CPU virtual address space.)
*/
if (where >= 0x100) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
bus, devfn, where, size, val);
return ret;
}
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
unsigned long flags;
int ret;
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
spin_lock_irqsave(&orion5x_pcie_lock, flags);
ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
return ret;
}
static struct pci_ops pcie_ops = {
.read = pcie_rd_conf,
.write = pcie_wr_conf,
};
static int __init pcie_setup(struct pci_sys_data *sys)
{
struct resource *res;
struct resource realio;
int dev;
/*
* Generic PCIe unit setup.
*/
orion_pcie_setup(PCIE_BASE);
/*
* Check whether to apply Orion-1/Orion-NAS PCIe config
* read transaction workaround.
*/
dev = orion_pcie_dev_id(PCIE_BASE);
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
"read transaction workaround\n");
mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
ORION_MBUS_PCIE_WA_ATTR,
ORION5X_PCIE_WA_PHYS_BASE,
ORION5X_PCIE_WA_SIZE);
pcie_ops.read = pcie_rd_conf_wa;
}
realio.start = sys->busnr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
/*
* Request resources.
*/
res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
panic("pcie_setup unable to alloc resources");
/*
* IORESOURCE_MEM
*/
res->name = "PCIe Memory Space";
res->flags = IORESOURCE_MEM;
res->start = ORION5X_PCIE_MEM_PHYS_BASE;
res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, res))
panic("Request PCIe Memory resource failed\n");
pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1;
}
/*****************************************************************************
* PCI controller
****************************************************************************/
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
#define PCI_MODE ORION5X_PCI_REG(0xd00)
#define PCI_CMD ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
/*
* PCI_MODE bits
*/
#define PCI_MODE_64BIT (1 << 2)
#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
/*
* PCI_CMD bits
*/
#define PCI_CMD_HOST_REORDER (1 << 29)
/*
* PCI_P2P_CONF bits
*/
#define PCI_P2P_BUS_OFFS 16
#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS 24
#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
/*
* PCI_CONF_ADDR bits
*/
#define PCI_CONF_REG(reg) ((reg) & 0xfc)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN (1 << 31)
/*
* Internal configuration space
*/
#define PCI_CONF_FUNC_STAT_CMD 0
#define PCI_CONF_REG_STAT_CMD 4
#define PCIX_STAT 0x64
#define PCIX_STAT_BUS_OFFS 8
#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
/*
* PCI Address Decode Windows registers
*/
#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
/*
* PCI configuration helpers for BAR settings
*/
#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
/*
* PCI config cycles are done by programming the PCI_CONF_ADDR register
* and then reading the PCI_CONF_DATA register. Need to make sure these
* transactions are atomic.
*/
static DEFINE_SPINLOCK(orion5x_pci_lock);
static int orion5x_pci_cardbus_mode;
static int orion5x_pci_local_bus_nr(void)
{
u32 conf = readl(PCI_P2P_CONF);
return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}
static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
u32 where, u32 size, u32 *val)
{
unsigned long flags;
spin_lock_irqsave(&orion5x_pci_lock, flags);
writel(PCI_CONF_BUS(bus) |
PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
*val = readl(PCI_CONF_DATA);
if (size == 1)
*val = (*val >> (8*(where & 0x3))) & 0xff;
else if (size == 2)
*val = (*val >> (8*(where & 0x3))) & 0xffff;
spin_unlock_irqrestore(&orion5x_pci_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
u32 where, u32 size, u32 val)
{
unsigned long flags;
int ret = PCIBIOS_SUCCESSFUL;
spin_lock_irqsave(&orion5x_pci_lock, flags);
writel(PCI_CONF_BUS(bus) |
PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
if (size == 4) {
__raw_writel(val, PCI_CONF_DATA);
} else if (size == 2) {
__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
} else if (size == 1) {
__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
} else {
ret = PCIBIOS_BAD_REGISTER_NUMBER;
}
spin_unlock_irqrestore(&orion5x_pci_lock, flags);
return ret;
}
static int orion5x_pci_valid_config(int bus, u32 devfn)
{
if (bus == orion5x_pci_local_bus_nr()) {
/*
* Don't go out for local device
*/
if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
return 0;
/*
* When the PCI signals are directly connected to a
* Cardbus slot, ignore all but device IDs 0 and 1.
*/
if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
return 0;
}
return 1;
}
static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 *val)
{
if (!orion5x_pci_valid_config(bus->number, devfn)) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where, size, val);
}
static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
if (!orion5x_pci_valid_config(bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
PCI_FUNC(devfn), where, size, val);
}
static struct pci_ops pci_ops = {
.read = orion5x_pci_rd_conf,
.write = orion5x_pci_wr_conf,
};
static void __init orion5x_pci_set_bus_nr(int nr)
{
u32 p2p = readl(PCI_P2P_CONF);
if (readl(PCI_MODE) & PCI_MODE_PCIX) {
/*
* PCI-X mode
*/
u32 pcix_status, bus, dev;
bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
pcix_status &= ~PCIX_STAT_BUS_MASK;
pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
} else {
/*
* PCI Conventional mode
*/
p2p &= ~PCI_P2P_BUS_MASK;
p2p |= (nr << PCI_P2P_BUS_OFFS);
writel(p2p, PCI_P2P_CONF);
}
}
static void __init orion5x_pci_master_slave_enable(void)
{
int bus_nr, func, reg;
u32 val;
bus_nr = orion5x_pci_local_bus_nr();
func = PCI_CONF_FUNC_STAT_CMD;
reg = PCI_CONF_REG_STAT_CMD;
orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
}
static void __init orion5x_setup_pci_wins(void)
{
const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
u32 win_enable;
int bus;
int i;
/*
* First, disable windows.
*/
win_enable = 0xffffffff;
writel(win_enable, PCI_BAR_ENABLE);
/*
* Setup windows for DDR banks.
*/
bus = orion5x_pci_local_bus_nr();
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
u32 reg;
u32 val;
/*
* Write DRAM bank base address register.
*/
reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
val = (cs->base & 0xfffff000) | (val & 0xfff);
orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
/*
* Write DRAM bank size register.
*/
reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
writel((cs->size - 1) & 0xfffff000,
PCI_BAR_SIZE_DDR_CS(cs->cs_index));
writel(cs->base & 0xfffff000,
PCI_BAR_REMAP_DDR_CS(cs->cs_index));
/*
* Enable decode window for this chip select.
*/
win_enable &= ~(1 << cs->cs_index);
}
/*
* Re-enable decode windows.
*/
writel(win_enable, PCI_BAR_ENABLE);
/*
* Disable automatic update of address remapping when writing to BARs.
*/
orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
}
static int __init pci_setup(struct pci_sys_data *sys)
{
struct resource *res;
struct resource realio;
/*
* Point PCI unit MBUS decode windows to DRAM space.
*/
orion5x_setup_pci_wins();
/*
* Master + Slave enable
*/
orion5x_pci_master_slave_enable();
/*
* Force ordering
*/
orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
realio.start = sys->busnr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
/*
* Request resources
*/
res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
panic("pci_setup unable to alloc resources");
/*
* IORESOURCE_MEM
*/
res->name = "PCI Memory Space";
res->flags = IORESOURCE_MEM;
res->start = ORION5X_PCI_MEM_PHYS_BASE;
res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, res))
panic("Request PCI Memory resource failed\n");
pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1;
}
/*****************************************************************************
* General PCIe + PCI
****************************************************************************/
/*
* The root complex has a hardwired class of PCI_CLASS_MEMORY_OTHER, when it
* is operating as a root complex this needs to be switched to
* PCI_CLASS_BRIDGE_HOST or Linux will errantly try to process the BAR's on
* the device. Decoding setup is handled by the orion code.
*/
static void rc_pci_fixup(struct pci_dev *dev)
{
if (dev->bus->parent == NULL && dev->devfn == 0) {
struct resource *r;
dev->class &= 0xff;
dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
pci_dev_for_each_resource(dev, r) {
r->start = 0;
r->end = 0;
r->flags = 0;
}
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
static int orion5x_pci_disabled __initdata;
void __init orion5x_pci_disable(void)
{
orion5x_pci_disabled = 1;
}
void __init orion5x_pci_set_cardbus_mode(void)
{
orion5x_pci_cardbus_mode = 1;
}
int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
if (nr == 0) {
orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
return pcie_setup(sys);
}
if (nr == 1 && !orion5x_pci_disabled) {
orion5x_pci_set_bus_nr(sys->busnr);
return pci_setup(sys);
}
return 0;
}
int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge)
{
struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
list_splice_init(&sys->resources, &bridge->windows);
bridge->dev.parent = NULL;
bridge->sysdata = sys;
bridge->busnr = sys->busnr;
if (nr == 0) {
bridge->ops = &pcie_ops;
return pci_scan_root_bus_bridge(bridge);
}
if (nr == 1 && !orion5x_pci_disabled) {
bridge->ops = &pci_ops;
return pci_scan_root_bus_bridge(bridge);
}
BUG();
return -ENODEV;
}
int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int bus = dev->bus->number;
/*
* PCIe endpoint?
*/
if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
return IRQ_ORION5X_PCIE0_INT;
return -1;
}
| linux-master | arch/arm/mach-orion5x/pci.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Buffalo Terastation Pro II/Live Board Setup
*
* Maintainer: Sylver Bruneau <[email protected]>
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <linux/serial_reg.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
/*****************************************************************************
* Terastation Pro 2/Live Info
****************************************************************************/
/*
* Terastation Pro 2 hardware :
* - Marvell 88F5281-D0
* - Marvell 88SX6042 SATA controller (PCI)
* - Marvell 88E1118 Gigabit Ethernet PHY
* - 256KB NOR flash
* - 128MB of DDR RAM
* - PCIe port (not equipped)
*/
/*
* 256K NOR flash Device bus boot chip select
*/
#define TSP2_NOR_BOOT_BASE 0xf4000000
#define TSP2_NOR_BOOT_SIZE SZ_256K
/*****************************************************************************
* 256KB NOR Flash on BOOT Device
****************************************************************************/
static struct physmap_flash_data tsp2_nor_flash_data = {
.width = 1,
};
static struct resource tsp2_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = TSP2_NOR_BOOT_BASE,
.end = TSP2_NOR_BOOT_BASE + TSP2_NOR_BOOT_SIZE - 1,
};
static struct platform_device tsp2_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &tsp2_nor_flash_data,
},
.num_resources = 1,
.resource = &tsp2_nor_flash_resource,
};
/*****************************************************************************
* PCI
****************************************************************************/
#define TSP2_PCI_SLOT0_OFFS 7
#define TSP2_PCI_SLOT0_IRQ_PIN 11
static void __init tsp2_pci_preinit(void)
{
int pin;
/*
* Configure PCI GPIO IRQ pins
*/
pin = TSP2_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) {
irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else {
printk(KERN_ERR "tsp2_pci_preinit failed "
"to set_irq_type pin %d\n", pin);
gpio_free(pin);
}
} else {
printk(KERN_ERR "tsp2_pci_preinit failed to "
"gpio_request %d\n", pin);
}
}
static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
/*
* PCI IRQs are connected via GPIOs.
*/
if (slot == TSP2_PCI_SLOT0_OFFS)
return gpio_to_irq(TSP2_PCI_SLOT0_IRQ_PIN);
return -1;
}
static struct hw_pci tsp2_pci __initdata = {
.nr_controllers = 2,
.preinit = tsp2_pci_preinit,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = tsp2_pci_map_irq,
};
static int __init tsp2_pci_init(void)
{
if (machine_is_terastation_pro2())
pci_common_init(&tsp2_pci);
return 0;
}
subsys_initcall(tsp2_pci_init);
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data tsp2_eth_data = {
.phy_addr = 0,
};
/*****************************************************************************
* RTC 5C372a on I2C bus
****************************************************************************/
#define TSP2_RTC_GPIO 9
static struct i2c_board_info __initdata tsp2_i2c_rtc = {
I2C_BOARD_INFO("rs5c372a", 0x32),
};
/*****************************************************************************
* Terastation Pro II specific power off method via UART1-attached
* microcontroller
****************************************************************************/
#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
static int tsp2_miconread(unsigned char *buf, int count)
{
int i;
int timeout;
for (i = 0; i < count; i++) {
timeout = 10;
while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
if (--timeout == 0)
break;
udelay(1000);
}
if (timeout == 0)
break;
buf[i] = readl(UART1_REG(RX));
}
/* return read bytes */
return i;
}
static int tsp2_miconwrite(const unsigned char *buf, int count)
{
int i = 0;
while (count--) {
while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
barrier();
writel(buf[i++], UART1_REG(TX));
}
return 0;
}
static int tsp2_miconsend(const unsigned char *data, int count)
{
int i;
unsigned char checksum = 0;
unsigned char recv_buf[40];
unsigned char send_buf[40];
unsigned char correct_ack[3];
int retry = 2;
/* Generate checksum */
for (i = 0; i < count; i++)
checksum -= data[i];
do {
/* Send data */
tsp2_miconwrite(data, count);
/* send checksum */
tsp2_miconwrite(&checksum, 1);
if (tsp2_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
printk(KERN_ERR ">%s: receive failed.\n", __func__);
/* send preamble to clear the receive buffer */
memset(&send_buf, 0xff, sizeof(send_buf));
tsp2_miconwrite(send_buf, sizeof(send_buf));
/* make dummy reads */
mdelay(100);
tsp2_miconread(recv_buf, sizeof(recv_buf));
} else {
/* Generate expected ack */
correct_ack[0] = 0x01;
correct_ack[1] = data[1];
correct_ack[2] = 0x00;
/* checksum Check */
if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
recv_buf[3]) & 0xFF) {
printk(KERN_ERR ">%s: Checksum Error : "
"Received data[%02x, %02x, %02x, %02x]"
"\n", __func__, recv_buf[0],
recv_buf[1], recv_buf[2], recv_buf[3]);
} else {
/* Check Received Data */
if (correct_ack[0] == recv_buf[0] &&
correct_ack[1] == recv_buf[1] &&
correct_ack[2] == recv_buf[2]) {
/* Interval for next command */
mdelay(10);
/* Receive ACK */
return 0;
}
}
/* Received NAK or illegal Data */
printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
"Received\n", __func__);
}
} while (retry--);
/* Interval for next command */
mdelay(10);
return -1;
}
static void tsp2_power_off(void)
{
const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
const unsigned char shutdownwait[] = {0x00, 0x0c};
const unsigned char poweroff[] = {0x00, 0x06};
/* 38400 baud divisor */
const unsigned divisor = ((orion5x_tclk + (8 * 38400)) / (16 * 38400));
pr_info("%s: triggering power-off...\n", __func__);
/* hijack uart1 and reset into sane state (38400,8n1,even parity) */
writel(0x83, UART1_REG(LCR));
writel(divisor & 0xff, UART1_REG(DLL));
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
writel(0x1b, UART1_REG(LCR));
writel(0x00, UART1_REG(IER));
writel(0x07, UART1_REG(FCR));
writel(0x00, UART1_REG(MCR));
/* Send the commands to shutdown the Terastation Pro II */
tsp2_miconsend(watchdogkill, sizeof(watchdogkill)) ;
tsp2_miconsend(shutdownwait, sizeof(shutdownwait)) ;
tsp2_miconsend(poweroff, sizeof(poweroff));
}
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int tsp2_mpp_modes[] __initdata = {
MPP0_PCIE_RST_OUTn,
MPP1_UNUSED,
MPP2_UNUSED,
MPP3_UNUSED,
MPP4_NAND, /* BOOT NAND Flash REn */
MPP5_NAND, /* BOOT NAND Flash WEn */
MPP6_NAND, /* BOOT NAND Flash HREn[0] */
MPP7_NAND, /* BOOT NAND Flash WEn[0] */
MPP8_GPIO, /* MICON int */
MPP9_GPIO, /* RTC int */
MPP10_UNUSED,
MPP11_GPIO, /* PCI Int A */
MPP12_UNUSED,
MPP13_GPIO, /* UPS on UART0 enable */
MPP14_GPIO, /* UPS low battery detection */
MPP15_UNUSED,
MPP16_UART, /* UART1 RXD */
MPP17_UART, /* UART1 TXD */
MPP18_UART, /* UART1 CTSn */
MPP19_UART, /* UART1 RTSn */
0,
};
static void __init tsp2_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(tsp2_mpp_modes);
/*
* Configure peripherals.
*/
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
TSP2_NOR_BOOT_BASE,
TSP2_NOR_BOOT_SIZE);
platform_device_register(&tsp2_nor_flash);
orion5x_ehci0_init();
orion5x_eth_init(&tsp2_eth_data);
orion5x_i2c_init();
orion5x_uart0_init();
orion5x_uart1_init();
/* Get RTC IRQ and register the chip */
if (gpio_request(TSP2_RTC_GPIO, "rtc") == 0) {
if (gpio_direction_input(TSP2_RTC_GPIO) == 0)
tsp2_i2c_rtc.irq = gpio_to_irq(TSP2_RTC_GPIO);
else
gpio_free(TSP2_RTC_GPIO);
}
if (tsp2_i2c_rtc.irq == 0)
pr_warn("tsp2_init: failed to get RTC IRQ\n");
i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
/* register Terastation Pro II specific power-off method */
pm_power_off = tsp2_power_off;
}
MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
/* Maintainer: Sylver Bruneau <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = tsp2_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/terastation_pro2-setup.c |
/*
* arch/arm/mach-orion5x/dns323-setup.c
*
* Copyright (C) 2007 Herbert Valerio Riedel <[email protected]>
*
* Support for HW Rev C1:
*
* Copyright (C) 2010 Benjamin Herrenschmidt <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/ata_platform.h>
#include <linux/phy.h>
#include <linux/marvell_phy.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <asm/system_info.h>
#include <plat/orion-gpio.h>
#include "orion5x.h"
#include "common.h"
#include "mpp.h"
/* Rev A1 and B1 */
#define DNS323_GPIO_LED_RIGHT_AMBER 1
#define DNS323_GPIO_LED_LEFT_AMBER 2
#define DNS323_GPIO_SYSTEM_UP 3
#define DNS323_GPIO_LED_POWER1 4
#define DNS323_GPIO_LED_POWER2 5
#define DNS323_GPIO_OVERTEMP 6
#define DNS323_GPIO_RTC 7
#define DNS323_GPIO_POWER_OFF 8
#define DNS323_GPIO_KEY_POWER 9
#define DNS323_GPIO_KEY_RESET 10
/* Rev C1 */
#define DNS323C_GPIO_KEY_POWER 1
#define DNS323C_GPIO_POWER_OFF 2
#define DNS323C_GPIO_LED_RIGHT_AMBER 8
#define DNS323C_GPIO_LED_LEFT_AMBER 9
#define DNS323C_GPIO_LED_POWER 17
#define DNS323C_GPIO_FAN_BIT1 18
#define DNS323C_GPIO_FAN_BIT0 19
/* Exposed to userspace, do not change */
enum {
DNS323_REV_A1, /* 0 */
DNS323_REV_B1, /* 1 */
DNS323_REV_C1, /* 2 */
};
/****************************************************************************
* PCI setup
*/
static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
return -1;
}
static struct hw_pci dns323_pci __initdata = {
.nr_controllers = 2,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = dns323_pci_map_irq,
};
static int __init dns323_pci_init(void)
{
/* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
* gets in the way of initialising the SATA controller.
*/
if (machine_is_dns323() && system_rev == DNS323_REV_A1)
pci_common_init(&dns323_pci);
return 0;
}
subsys_initcall(dns323_pci_init);
/****************************************************************************
* 8MiB NOR flash (Spansion S29GL064M90TFIR4)
*
* Layout as used by D-Link:
* 0x00000000-0x00010000 : "MTD1"
* 0x00010000-0x00020000 : "MTD2"
* 0x00020000-0x001a0000 : "Linux Kernel"
* 0x001a0000-0x007d0000 : "File System"
* 0x007d0000-0x00800000 : "u-boot"
*/
#define DNS323_NOR_BOOT_BASE 0xf4000000
#define DNS323_NOR_BOOT_SIZE SZ_8M
static struct mtd_partition dns323_partitions[] = {
{
.name = "MTD1",
.size = 0x00010000,
.offset = 0,
}, {
.name = "MTD2",
.size = 0x00010000,
.offset = 0x00010000,
}, {
.name = "Linux Kernel",
.size = 0x00180000,
.offset = 0x00020000,
}, {
.name = "File System",
.size = 0x00630000,
.offset = 0x001A0000,
}, {
.name = "u-boot",
.size = 0x00030000,
.offset = 0x007d0000,
},
};
static struct physmap_flash_data dns323_nor_flash_data = {
.width = 1,
.parts = dns323_partitions,
.nr_parts = ARRAY_SIZE(dns323_partitions)
};
static struct resource dns323_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = DNS323_NOR_BOOT_BASE,
.end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1,
};
static struct platform_device dns323_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &dns323_nor_flash_data,
},
.resource = &dns323_nor_flash_resource,
.num_resources = 1,
};
/****************************************************************************
* Ethernet
*/
static struct mv643xx_eth_platform_data dns323_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these
* functions be kept somewhere?
*/
static int __init dns323_parse_hex_nibble(char n)
{
if (n >= '0' && n <= '9')
return n - '0';
if (n >= 'A' && n <= 'F')
return n - 'A' + 10;
if (n >= 'a' && n <= 'f')
return n - 'a' + 10;
return -1;
}
static int __init dns323_parse_hex_byte(const char *b)
{
int hi;
int lo;
hi = dns323_parse_hex_nibble(b[0]);
lo = dns323_parse_hex_nibble(b[1]);
if (hi < 0 || lo < 0)
return -1;
return (hi << 4) | lo;
}
static int __init dns323_read_mac_addr(void)
{
u_int8_t addr[6];
int i;
char *mac_page;
/* MAC address is stored as a regular ol' string in /dev/mtdblock4
* (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80).
*/
mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024);
if (!mac_page)
return -ENOMEM;
/* Sanity check the string we're looking at */
for (i = 0; i < 5; i++) {
if (*(mac_page + (i * 3) + 2) != ':') {
goto error_fail;
}
}
for (i = 0; i < 6; i++) {
int byte;
byte = dns323_parse_hex_byte(mac_page + (i * 3));
if (byte < 0) {
goto error_fail;
}
addr[i] = byte;
}
iounmap(mac_page);
printk("DNS-323: Found ethernet MAC address: %pM\n", addr);
memcpy(dns323_eth_data.mac_addr, addr, 6);
return 0;
error_fail:
iounmap(mac_page);
return -EINVAL;
}
/****************************************************************************
* GPIO LEDs (simple - doesn't use hardware blinking support)
*/
static struct gpio_led dns323ab_leds[] = {
{
.name = "power:blue",
.gpio = DNS323_GPIO_LED_POWER2,
.default_trigger = "default-on",
}, {
.name = "right:amber",
.gpio = DNS323_GPIO_LED_RIGHT_AMBER,
.active_low = 1,
}, {
.name = "left:amber",
.gpio = DNS323_GPIO_LED_LEFT_AMBER,
.active_low = 1,
},
};
static struct gpio_led dns323c_leds[] = {
{
.name = "power:blue",
.gpio = DNS323C_GPIO_LED_POWER,
.default_trigger = "timer",
.active_low = 1,
}, {
.name = "right:amber",
.gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
.active_low = 1,
}, {
.name = "left:amber",
.gpio = DNS323C_GPIO_LED_LEFT_AMBER,
.active_low = 1,
},
};
static struct gpio_led_platform_data dns323ab_led_data = {
.num_leds = ARRAY_SIZE(dns323ab_leds),
.leds = dns323ab_leds,
.gpio_blink_set = orion_gpio_led_blink_set,
};
static struct gpio_led_platform_data dns323c_led_data = {
.num_leds = ARRAY_SIZE(dns323c_leds),
.leds = dns323c_leds,
.gpio_blink_set = orion_gpio_led_blink_set,
};
static struct platform_device dns323_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &dns323ab_led_data,
},
};
/****************************************************************************
* GPIO Attached Keys
*/
static struct gpio_keys_button dns323ab_buttons[] = {
{
.code = KEY_RESTART,
.gpio = DNS323_GPIO_KEY_RESET,
.desc = "Reset Button",
.active_low = 1,
}, {
.code = KEY_POWER,
.gpio = DNS323_GPIO_KEY_POWER,
.desc = "Power Button",
.active_low = 1,
},
};
static struct gpio_keys_platform_data dns323ab_button_data = {
.buttons = dns323ab_buttons,
.nbuttons = ARRAY_SIZE(dns323ab_buttons),
};
static struct gpio_keys_button dns323c_buttons[] = {
{
.code = KEY_POWER,
.gpio = DNS323C_GPIO_KEY_POWER,
.desc = "Power Button",
.active_low = 1,
},
};
static struct gpio_keys_platform_data dns323c_button_data = {
.buttons = dns323c_buttons,
.nbuttons = ARRAY_SIZE(dns323c_buttons),
};
static struct platform_device dns323_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &dns323ab_button_data,
},
};
/*****************************************************************************
* SATA
*/
static struct mv_sata_platform_data dns323_sata_data = {
.n_ports = 2,
};
/****************************************************************************
* General Setup
*/
static unsigned int dns323a_mpp_modes[] __initdata = {
MPP0_PCIE_RST_OUTn,
MPP1_GPIO, /* right amber LED (sata ch0) */
MPP2_GPIO, /* left amber LED (sata ch1) */
MPP3_UNUSED,
MPP4_GPIO, /* power button LED */
MPP5_GPIO, /* power button LED */
MPP6_GPIO, /* GMT G751-2f overtemp */
MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
MPP8_GPIO, /* triggers power off */
MPP9_GPIO, /* power button switch */
MPP10_GPIO, /* reset button switch */
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_UNUSED,
MPP15_UNUSED,
MPP16_UNUSED,
MPP17_UNUSED,
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static unsigned int dns323b_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_GPIO, /* right amber LED (sata ch0) */
MPP2_GPIO, /* left amber LED (sata ch1) */
MPP3_GPIO, /* system up flag */
MPP4_GPIO, /* power button LED */
MPP5_GPIO, /* power button LED */
MPP6_GPIO, /* GMT G751-2f overtemp */
MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
MPP8_GPIO, /* triggers power off */
MPP9_GPIO, /* power button switch */
MPP10_GPIO, /* reset button switch */
MPP11_UNUSED,
MPP12_SATA_LED,
MPP13_SATA_LED,
MPP14_SATA_LED,
MPP15_SATA_LED,
MPP16_UNUSED,
MPP17_UNUSED,
MPP18_UNUSED,
MPP19_UNUSED,
0,
};
static unsigned int dns323c_mpp_modes[] __initdata = {
MPP0_GPIO, /* ? input */
MPP1_GPIO, /* input power switch (0 = pressed) */
MPP2_GPIO, /* output power off */
MPP3_UNUSED, /* ? output */
MPP4_UNUSED, /* ? output */
MPP5_UNUSED, /* ? output */
MPP6_UNUSED, /* ? output */
MPP7_UNUSED, /* ? output */
MPP8_GPIO, /* i/o right amber LED */
MPP9_GPIO, /* i/o left amber LED */
MPP10_GPIO, /* input */
MPP11_UNUSED,
MPP12_SATA_LED,
MPP13_SATA_LED,
MPP14_SATA_LED,
MPP15_SATA_LED,
MPP16_UNUSED,
MPP17_GPIO, /* power button LED */
MPP18_GPIO, /* fan speed bit 0 */
MPP19_GPIO, /* fan speed bit 1 */
0,
};
/* Rev C1 Fan speed notes:
*
* The fan is controlled by 2 GPIOs on this board. The settings
* of the bits is as follow:
*
* GPIO 18 GPIO 19 Fan
*
* 0 0 stopped
* 0 1 low speed
* 1 0 high speed
* 1 1 don't do that (*)
*
* (*) I think the two bits control two feed-in resistors into a fixed
* PWN circuit, setting both bits will basically go a 'bit' faster
* than high speed, but d-link doesn't do it and you may get out of
* HW spec so don't do it.
*/
/*
* On the DNS-323 A1 and B1 the following devices are attached via I2C:
*
* i2c addr | chip | description
* 0x3e | GMT G760Af | fan speed PWM controller
* 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
* 0x68 | ST M41T80 | RTC w/ alarm
*/
static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
{
I2C_BOARD_INFO("g760a", 0x3e),
}, {
I2C_BOARD_INFO("lm75", 0x48),
}, {
I2C_BOARD_INFO("m41t80", 0x68),
},
};
/*
* On the DNS-323 C1 the following devices are attached via I2C:
*
* i2c addr | chip | description
* 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
* 0x68 | ST M41T80 | RTC w/ alarm
*/
static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
{
I2C_BOARD_INFO("lm75", 0x48),
}, {
I2C_BOARD_INFO("m41t80", 0x68),
},
};
/* DNS-323 rev. A specific power off method */
static void dns323a_power_off(void)
{
pr_info("DNS-323: Triggering power-off...\n");
gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
}
/* DNS-323 rev B specific power off method */
static void dns323b_power_off(void)
{
pr_info("DNS-323: Triggering power-off...\n");
/* Pin has to be changed to 1 and back to 0 to do actual power off. */
gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
mdelay(100);
gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
}
/* DNS-323 rev. C specific power off method */
static void dns323c_power_off(void)
{
pr_info("DNS-323: Triggering power-off...\n");
gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
}
static int dns323c_phy_fixup(struct phy_device *phy)
{
phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
return 0;
}
static int __init dns323_identify_rev(void)
{
u32 dev, rev, i, reg;
pr_debug("DNS-323: Identifying board ... \n");
/* Rev A1 has a 5181 */
orion5x_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID) {
pr_debug("DNS-323: 5181 found, board is A1\n");
return DNS323_REV_A1;
}
pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
/* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
* a bit gross but we want to do that without links into the eth
* driver so let's poke at it directly. We default to rev B1 in
* case the accesses fail
*/
#define ETH_SMI_REG (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
#define SMI_BUSY 0x10000000
#define SMI_READ_VALID 0x08000000
#define SMI_OPCODE_READ 0x04000000
#define SMI_OPCODE_WRITE 0x00000000
for (i = 0; i < 1000; i++) {
reg = readl(ETH_SMI_REG);
if (!(reg & SMI_BUSY))
break;
}
if (i >= 1000) {
pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n");
return DNS323_REV_B1;
}
writel((3 << 21) /* phy ID reg */ |
(8 << 16) /* phy addr */ |
SMI_OPCODE_READ, ETH_SMI_REG);
for (i = 0; i < 1000; i++) {
reg = readl(ETH_SMI_REG);
if (reg & SMI_READ_VALID)
break;
}
if (i >= 1000) {
pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n");
return DNS323_REV_B1;
}
pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
/* Note: the Marvell tools mask the ID with 0x3f0 before comparison
* but I don't see that making a difference here, at least with
* any known Marvell PHY ID
*/
switch(reg & 0xfff0) {
case 0x0cc0: /* MV88E1111 */
return DNS323_REV_B1;
case 0x0e10: /* MV88E1118 */
return DNS323_REV_C1;
default:
pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
reg & 0xffff);
}
return DNS323_REV_B1;
}
static void __init dns323_init(void)
{
/* Setup basic Orion functions. Need to be called early. */
orion5x_init();
/* Identify revision */
system_rev = dns323_identify_rev();
pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
/* Just to be tricky, the 5182 has a completely different
* set of MPP modes to the 5181.
*/
switch(system_rev) {
case DNS323_REV_A1:
orion5x_mpp_conf(dns323a_mpp_modes);
writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
break;
case DNS323_REV_B1:
orion5x_mpp_conf(dns323b_mpp_modes);
break;
case DNS323_REV_C1:
orion5x_mpp_conf(dns323c_mpp_modes);
break;
}
/* setup flash mapping
* CS3 holds a 8 MB Spansion S29GL064M90TFIR4
*/
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
DNS323_NOR_BOOT_BASE,
DNS323_NOR_BOOT_SIZE);
platform_device_register(&dns323_nor_flash);
/* Sort out LEDs, Buttons and i2c devices */
switch(system_rev) {
case DNS323_REV_A1:
/* The 5181 power LED is active low and requires
* DNS323_GPIO_LED_POWER1 to also be low.
*/
dns323ab_leds[0].active_low = 1;
gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
fallthrough;
case DNS323_REV_B1:
i2c_register_board_info(0, dns323ab_i2c_devices,
ARRAY_SIZE(dns323ab_i2c_devices));
break;
case DNS323_REV_C1:
/* Hookup LEDs & Buttons */
dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
dns323_button_device.dev.platform_data = &dns323c_button_data;
/* Hookup i2c devices and fan driver */
i2c_register_board_info(0, dns323c_i2c_devices,
ARRAY_SIZE(dns323c_i2c_devices));
platform_device_register_simple("dns323c-fan", 0, NULL, 0);
/* Register fixup for the PHY LEDs */
if (!IS_BUILTIN(CONFIG_PHYLIB))
break;
phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
MARVELL_PHY_ID_MASK,
dns323c_phy_fixup);
}
platform_device_register(&dns323_gpio_leds);
platform_device_register(&dns323_button_device);
/*
* Configure peripherals.
*/
if (dns323_read_mac_addr() < 0)
printk("DNS-323: Failed to read MAC address\n");
orion5x_ehci0_init();
orion5x_eth_init(&dns323_eth_data);
orion5x_i2c_init();
orion5x_uart0_init();
/* Remaining GPIOs */
switch(system_rev) {
case DNS323_REV_A1:
/* Poweroff GPIO */
if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
pr_err("DNS-323: failed to setup power-off GPIO\n");
pm_power_off = dns323a_power_off;
break;
case DNS323_REV_B1:
/* 5182 built-in SATA init */
orion5x_sata_init(&dns323_sata_data);
/* The DNS323 rev B1 has flag to indicate the system is up.
* Without this flag set, power LED will flash and cannot be
* controlled via leds-gpio.
*/
if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
/* Poweroff GPIO */
if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
pr_err("DNS-323: failed to setup power-off GPIO\n");
pm_power_off = dns323b_power_off;
break;
case DNS323_REV_C1:
/* 5182 built-in SATA init */
orion5x_sata_init(&dns323_sata_data);
/* Poweroff GPIO */
if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
pr_err("DNS-323: failed to setup power-off GPIO\n");
pm_power_off = dns323c_power_off;
/* Now, -this- should theoretically be done by the sata_mv driver
* once I figure out what's going on there. Maybe the behaviour
* of the LEDs should be somewhat passed via the platform_data.
* for now, just whack the register and make the LEDs happy
*
* Note: AFAIK, rev B1 needs the same treatment but I'll let
* somebody else test it.
*/
writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
break;
}
}
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = dns323_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/dns323-setup.c |
/*
* Copyright (C) 2007 Herbert Valerio Riedel <[email protected]>
* Copyright (C) 2008 Martin Michlmayr <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
#define MV2120_NOR_BOOT_BASE 0xf4000000
#define MV2120_NOR_BOOT_SIZE SZ_512K
#define MV2120_GPIO_RTC_IRQ 3
#define MV2120_GPIO_KEY_RESET 17
#define MV2120_GPIO_KEY_POWER 18
#define MV2120_GPIO_POWER_OFF 19
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data mv2120_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
static struct mv_sata_platform_data mv2120_sata_data = {
.n_ports = 2,
};
static struct mtd_partition mv2120_partitions[] = {
{
.name = "firmware",
.size = 0x00080000,
.offset = 0,
},
};
static struct physmap_flash_data mv2120_nor_flash_data = {
.width = 1,
.parts = mv2120_partitions,
.nr_parts = ARRAY_SIZE(mv2120_partitions)
};
static struct resource mv2120_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = MV2120_NOR_BOOT_BASE,
.end = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
};
static struct platform_device mv2120_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &mv2120_nor_flash_data,
},
.resource = &mv2120_nor_flash_resource,
.num_resources = 1,
};
static struct gpio_keys_button mv2120_buttons[] = {
{
.code = KEY_RESTART,
.gpio = MV2120_GPIO_KEY_RESET,
.desc = "reset",
.active_low = 1,
}, {
.code = KEY_POWER,
.gpio = MV2120_GPIO_KEY_POWER,
.desc = "power",
.active_low = 1,
},
};
static struct gpio_keys_platform_data mv2120_button_data = {
.buttons = mv2120_buttons,
.nbuttons = ARRAY_SIZE(mv2120_buttons),
};
static struct platform_device mv2120_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &mv2120_button_data,
},
};
/****************************************************************************
* General Setup
****************************************************************************/
static unsigned int mv2120_mpp_modes[] __initdata = {
MPP0_GPIO, /* Sys status LED */
MPP1_GPIO, /* Sys error LED */
MPP2_GPIO, /* OverTemp interrupt */
MPP3_GPIO, /* RTC interrupt */
MPP4_GPIO, /* V_LED 5V */
MPP5_GPIO, /* V_LED 3.3V */
MPP6_UNUSED,
MPP7_UNUSED,
MPP8_GPIO, /* SATA 0 fail LED */
MPP9_GPIO, /* SATA 1 fail LED */
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_SATA_LED, /* SATA 0 presence */
MPP13_SATA_LED, /* SATA 1 presence */
MPP14_SATA_LED, /* SATA 0 active */
MPP15_SATA_LED, /* SATA 1 active */
MPP16_UNUSED,
MPP17_GPIO, /* Reset button */
MPP18_GPIO, /* Power button */
MPP19_GPIO, /* Power off */
0,
};
static struct i2c_board_info __initdata mv2120_i2c_rtc = {
I2C_BOARD_INFO("pcf8563", 0x51),
.irq = 0,
};
static struct gpio_led mv2120_led_pins[] = {
{
.name = "mv2120:blue:health",
.gpio = 0,
},
{
.name = "mv2120:red:health",
.gpio = 1,
},
{
.name = "mv2120:led:bright",
.gpio = 4,
.default_trigger = "default-on",
},
{
.name = "mv2120:led:dimmed",
.gpio = 5,
},
{
.name = "mv2120:red:sata0",
.gpio = 8,
.active_low = 1,
},
{
.name = "mv2120:red:sata1",
.gpio = 9,
.active_low = 1,
},
};
static struct gpio_led_platform_data mv2120_led_data = {
.leds = mv2120_led_pins,
.num_leds = ARRAY_SIZE(mv2120_led_pins),
};
static struct platform_device mv2120_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &mv2120_led_data,
}
};
static void mv2120_power_off(void)
{
pr_info("%s: triggering power-off...\n", __func__);
gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
}
static void __init mv2120_init(void)
{
/* Setup basic Orion functions. Need to be called early. */
orion5x_init();
orion5x_mpp_conf(mv2120_mpp_modes);
/*
* Configure peripherals.
*/
orion5x_ehci0_init();
orion5x_ehci1_init();
orion5x_eth_init(&mv2120_eth_data);
orion5x_i2c_init();
orion5x_sata_init(&mv2120_sata_data);
orion5x_uart0_init();
orion5x_xor_init();
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
MV2120_NOR_BOOT_BASE,
MV2120_NOR_BOOT_SIZE);
platform_device_register(&mv2120_nor_flash);
platform_device_register(&mv2120_button_device);
if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
else
gpio_free(MV2120_GPIO_RTC_IRQ);
}
i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
platform_device_register(&mv2120_leds);
/* register mv2120 specific power-off method */
if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
pr_err("mv2120: failed to setup power-off GPIO\n");
pm_power_off = mv2120_power_off;
}
/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(MV2120, "HP Media Vault mv2120")
/* Maintainer: Martin Michlmayr <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = mv2120_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/mv2120-setup.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* QNAP TS-x09 Boards common functions
*
* Maintainers: Lennert Buytenhek <[email protected]>
* Byron Bradley <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mv643xx_eth.h>
#include <linux/timex.h>
#include <linux/serial_reg.h>
#include "orion5x.h"
#include "tsx09-common.h"
#include "common.h"
/*****************************************************************************
* QNAP TS-x09 specific power off method via UART1-attached PIC
****************************************************************************/
#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
void qnap_tsx09_power_off(void)
{
/* 19200 baud divisor */
const unsigned divisor = ((orion5x_tclk + (8 * 19200)) / (16 * 19200));
pr_info("%s: triggering power-off...\n", __func__);
/* hijack uart1 and reset into sane state (19200,8n1) */
writel(0x83, UART1_REG(LCR));
writel(divisor & 0xff, UART1_REG(DLL));
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
writel(0x03, UART1_REG(LCR));
writel(0x00, UART1_REG(IER));
writel(0x00, UART1_REG(FCR));
writel(0x00, UART1_REG(MCR));
/* send the power-off command 'A' to PIC */
writel('A', UART1_REG(TX));
}
/*****************************************************************************
* Ethernet
****************************************************************************/
struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
static int __init qnap_tsx09_parse_hex_nibble(char n)
{
if (n >= '0' && n <= '9')
return n - '0';
if (n >= 'A' && n <= 'F')
return n - 'A' + 10;
if (n >= 'a' && n <= 'f')
return n - 'a' + 10;
return -1;
}
static int __init qnap_tsx09_parse_hex_byte(const char *b)
{
int hi;
int lo;
hi = qnap_tsx09_parse_hex_nibble(b[0]);
lo = qnap_tsx09_parse_hex_nibble(b[1]);
if (hi < 0 || lo < 0)
return -1;
return (hi << 4) | lo;
}
static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
{
u_int8_t addr[6];
int i;
for (i = 0; i < 6; i++) {
int byte;
/*
* Enforce "xx:xx:xx:xx:xx:xx\n" format.
*/
if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
return -1;
byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
if (byte < 0)
return -1;
addr[i] = byte;
}
printk(KERN_INFO "tsx09: found ethernet mac address %pM\n", addr);
memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
return 0;
}
/*
* The 'NAS Config' flash partition has an ext2 filesystem which
* contains a file that has the ethernet MAC address in plain text
* (format "xx:xx:xx:xx:xx:xx\n").
*/
void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
{
unsigned long addr;
for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
char *nor_page;
int ret = 0;
nor_page = ioremap(addr, 1024);
if (nor_page != NULL) {
ret = qnap_tsx09_check_mac_addr(nor_page);
iounmap(nor_page);
}
if (ret == 0)
break;
}
}
| linux-master | arch/arm/mach-orion5x/tsx09-common.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/ts78xx-setup.c
*
* Maintainer: Alexander Clouter <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sysfs.h>
#include <linux/platform_device.h>
#include <linux/mv643xx_eth.h>
#include <linux/ata_platform.h>
#include <linux/mtd/platnand.h>
#include <linux/timeriomem-rng.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
#include "ts78xx-fpga.h"
/*****************************************************************************
* TS-78xx Info
****************************************************************************/
/*
* FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
*/
#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
#define TS78XX_FPGA_REGS_VIRT_BASE IOMEM(0xff900000)
#define TS78XX_FPGA_REGS_SIZE SZ_1M
static struct ts78xx_fpga_data ts78xx_fpga = {
.id = 0,
.state = 1,
/* .supports = ... - populated by ts78xx_fpga_supports() */
};
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
static struct map_desc ts78xx_io_desc[] __initdata = {
{
.virtual = (unsigned long)TS78XX_FPGA_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
.length = TS78XX_FPGA_REGS_SIZE,
.type = MT_DEVICE,
},
};
static void __init ts78xx_map_io(void)
{
orion5x_map_io();
iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
}
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data ts78xx_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data ts78xx_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
****************************************************************************/
#define TS_RTC_CTRL (TS78XX_FPGA_REGS_PHYS_BASE + 0x808)
#define TS_RTC_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x80c)
static struct resource ts78xx_ts_rtc_resources[] = {
DEFINE_RES_MEM(TS_RTC_CTRL, 0x01),
DEFINE_RES_MEM(TS_RTC_DATA, 0x01),
};
static struct platform_device ts78xx_ts_rtc_device = {
.name = "rtc-m48t86",
.id = -1,
.resource = ts78xx_ts_rtc_resources,
.num_resources = ARRAY_SIZE(ts78xx_ts_rtc_resources),
};
static int ts78xx_ts_rtc_load(void)
{
int rc;
if (ts78xx_fpga.supports.ts_rtc.init == 0) {
rc = platform_device_register(&ts78xx_ts_rtc_device);
if (!rc)
ts78xx_fpga.supports.ts_rtc.init = 1;
} else {
rc = platform_device_add(&ts78xx_ts_rtc_device);
}
if (rc)
pr_info("RTC could not be registered: %d\n", rc);
return rc;
}
static void ts78xx_ts_rtc_unload(void)
{
platform_device_del(&ts78xx_ts_rtc_device);
}
/*****************************************************************************
* NAND Flash
****************************************************************************/
#define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE + 0x800) /* VIRT */
#define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE + 0x804) /* PHYS */
/*
* hardware specific access to control-lines
*
* ctrl:
* NAND_NCE: bit 0 -> bit 2
* NAND_CLE: bit 1 -> bit 1
* NAND_ALE: bit 2 -> bit 0
*/
static void ts78xx_ts_nand_cmd_ctrl(struct nand_chip *this, int cmd,
unsigned int ctrl)
{
if (ctrl & NAND_CTRL_CHANGE) {
unsigned char bits;
bits = (ctrl & NAND_NCE) << 2;
bits |= ctrl & NAND_CLE;
bits |= (ctrl & NAND_ALE) >> 2;
writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->legacy.IO_ADDR_W);
}
static int ts78xx_ts_nand_dev_ready(struct nand_chip *chip)
{
return readb(TS_NAND_CTRL) & 0x20;
}
static void ts78xx_ts_nand_write_buf(struct nand_chip *chip,
const uint8_t *buf, int len)
{
void __iomem *io_base = chip->legacy.IO_ADDR_W;
unsigned long off = ((unsigned long)buf & 3);
int sz;
if (off) {
sz = min_t(int, 4 - off, len);
writesb(io_base, buf, sz);
buf += sz;
len -= sz;
}
sz = len >> 2;
if (sz) {
u32 *buf32 = (u32 *)buf;
writesl(io_base, buf32, sz);
buf += sz << 2;
len -= sz << 2;
}
if (len)
writesb(io_base, buf, len);
}
static void ts78xx_ts_nand_read_buf(struct nand_chip *chip,
uint8_t *buf, int len)
{
void __iomem *io_base = chip->legacy.IO_ADDR_R;
unsigned long off = ((unsigned long)buf & 3);
int sz;
if (off) {
sz = min_t(int, 4 - off, len);
readsb(io_base, buf, sz);
buf += sz;
len -= sz;
}
sz = len >> 2;
if (sz) {
u32 *buf32 = (u32 *)buf;
readsl(io_base, buf32, sz);
buf += sz << 2;
len -= sz << 2;
}
if (len)
readsb(io_base, buf, len);
}
static struct mtd_partition ts78xx_ts_nand_parts[] = {
{
.name = "mbr",
.offset = 0,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
}, {
.name = "initrd",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
}, {
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
}
};
static struct platform_nand_data ts78xx_ts_nand_data = {
.chip = {
.nr_chips = 1,
.partitions = ts78xx_ts_nand_parts,
.nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts),
.chip_delay = 15,
.bbt_options = NAND_BBT_USE_FLASH,
},
.ctrl = {
/*
* The HW ECC offloading functions, used to give about a 9%
* performance increase for 'dd if=/dev/mtdblockX' and 5% for
* nanddump. This all however was changed by git commit
* e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is
* no performance advantage to be had so we no longer bother
*/
.cmd_ctrl = ts78xx_ts_nand_cmd_ctrl,
.dev_ready = ts78xx_ts_nand_dev_ready,
.write_buf = ts78xx_ts_nand_write_buf,
.read_buf = ts78xx_ts_nand_read_buf,
},
};
static struct resource ts78xx_ts_nand_resources
= DEFINE_RES_MEM(TS_NAND_DATA, 4);
static struct platform_device ts78xx_ts_nand_device = {
.name = "gen_nand",
.id = -1,
.dev = {
.platform_data = &ts78xx_ts_nand_data,
},
.resource = &ts78xx_ts_nand_resources,
.num_resources = 1,
};
static int ts78xx_ts_nand_load(void)
{
int rc;
if (ts78xx_fpga.supports.ts_nand.init == 0) {
rc = platform_device_register(&ts78xx_ts_nand_device);
if (!rc)
ts78xx_fpga.supports.ts_nand.init = 1;
} else
rc = platform_device_add(&ts78xx_ts_nand_device);
if (rc)
pr_info("NAND could not be registered: %d\n", rc);
return rc;
};
static void ts78xx_ts_nand_unload(void)
{
platform_device_del(&ts78xx_ts_nand_device);
}
/*****************************************************************************
* HW RNG
****************************************************************************/
#define TS_RNG_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
static struct resource ts78xx_ts_rng_resource
= DEFINE_RES_MEM(TS_RNG_DATA, 4);
static struct timeriomem_rng_data ts78xx_ts_rng_data = {
.period = 1000000, /* one second */
};
static struct platform_device ts78xx_ts_rng_device = {
.name = "timeriomem_rng",
.id = -1,
.dev = {
.platform_data = &ts78xx_ts_rng_data,
},
.resource = &ts78xx_ts_rng_resource,
.num_resources = 1,
};
static int ts78xx_ts_rng_load(void)
{
int rc;
if (ts78xx_fpga.supports.ts_rng.init == 0) {
rc = platform_device_register(&ts78xx_ts_rng_device);
if (!rc)
ts78xx_fpga.supports.ts_rng.init = 1;
} else
rc = platform_device_add(&ts78xx_ts_rng_device);
if (rc)
pr_info("RNG could not be registered: %d\n", rc);
return rc;
};
static void ts78xx_ts_rng_unload(void)
{
platform_device_del(&ts78xx_ts_rng_device);
}
/*****************************************************************************
* FPGA 'hotplug' support code
****************************************************************************/
static void ts78xx_fpga_devices_zero_init(void)
{
ts78xx_fpga.supports.ts_rtc.init = 0;
ts78xx_fpga.supports.ts_nand.init = 0;
ts78xx_fpga.supports.ts_rng.init = 0;
}
static void ts78xx_fpga_supports(void)
{
/* TODO: put this 'table' into ts78xx-fpga.h */
switch (ts78xx_fpga.id) {
case TS7800_REV_1:
case TS7800_REV_2:
case TS7800_REV_3:
case TS7800_REV_4:
case TS7800_REV_5:
case TS7800_REV_6:
case TS7800_REV_7:
case TS7800_REV_8:
case TS7800_REV_9:
ts78xx_fpga.supports.ts_rtc.present = 1;
ts78xx_fpga.supports.ts_nand.present = 1;
ts78xx_fpga.supports.ts_rng.present = 1;
break;
default:
/* enable devices if magic matches */
switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
case TS7800_FPGA_MAGIC:
pr_warn("unrecognised FPGA revision 0x%.2x\n",
ts78xx_fpga.id & 0xff);
ts78xx_fpga.supports.ts_rtc.present = 1;
ts78xx_fpga.supports.ts_nand.present = 1;
ts78xx_fpga.supports.ts_rng.present = 1;
break;
default:
ts78xx_fpga.supports.ts_rtc.present = 0;
ts78xx_fpga.supports.ts_nand.present = 0;
ts78xx_fpga.supports.ts_rng.present = 0;
}
}
}
static int ts78xx_fpga_load_devices(void)
{
int tmp, ret = 0;
if (ts78xx_fpga.supports.ts_rtc.present == 1) {
tmp = ts78xx_ts_rtc_load();
if (tmp)
ts78xx_fpga.supports.ts_rtc.present = 0;
ret |= tmp;
}
if (ts78xx_fpga.supports.ts_nand.present == 1) {
tmp = ts78xx_ts_nand_load();
if (tmp)
ts78xx_fpga.supports.ts_nand.present = 0;
ret |= tmp;
}
if (ts78xx_fpga.supports.ts_rng.present == 1) {
tmp = ts78xx_ts_rng_load();
if (tmp)
ts78xx_fpga.supports.ts_rng.present = 0;
ret |= tmp;
}
return ret;
}
static int ts78xx_fpga_unload_devices(void)
{
if (ts78xx_fpga.supports.ts_rtc.present == 1)
ts78xx_ts_rtc_unload();
if (ts78xx_fpga.supports.ts_nand.present == 1)
ts78xx_ts_nand_unload();
if (ts78xx_fpga.supports.ts_rng.present == 1)
ts78xx_ts_rng_unload();
return 0;
}
static int ts78xx_fpga_load(void)
{
ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
(ts78xx_fpga.id >> 8) & 0xffffff,
ts78xx_fpga.id & 0xff);
ts78xx_fpga_supports();
if (ts78xx_fpga_load_devices()) {
ts78xx_fpga.state = -1;
return -EBUSY;
}
return 0;
};
static int ts78xx_fpga_unload(void)
{
unsigned int fpga_id;
fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
/*
* There does not seem to be a feasible way to block access to the GPIO
* pins from userspace (/dev/mem). This if clause should hopefully warn
* those foolish enough not to follow 'policy' :)
*
* UrJTAG SVN since r1381 can be used to reprogram the FPGA
*/
if (ts78xx_fpga.id != fpga_id) {
pr_err("FPGA magic/rev mismatch\n"
"TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
(ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
(fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
ts78xx_fpga.state = -1;
return -EBUSY;
}
if (ts78xx_fpga_unload_devices()) {
ts78xx_fpga.state = -1;
return -EBUSY;
}
return 0;
};
static ssize_t ts78xx_fpga_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
if (ts78xx_fpga.state < 0)
return sprintf(buf, "borked\n");
return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline");
}
static ssize_t ts78xx_fpga_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t n)
{
int value, ret;
if (ts78xx_fpga.state < 0) {
pr_err("FPGA borked, you must powercycle ASAP\n");
return -EBUSY;
}
if (strncmp(buf, "online", sizeof("online") - 1) == 0)
value = 1;
else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
value = 0;
else
return -EINVAL;
if (ts78xx_fpga.state == value)
return n;
ret = (ts78xx_fpga.state == 0)
? ts78xx_fpga_load()
: ts78xx_fpga_unload();
if (!(ret < 0))
ts78xx_fpga.state = value;
return n;
}
static struct kobj_attribute ts78xx_fpga_attr =
__ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store);
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int ts78xx_mpp_modes[] __initdata = {
MPP0_UNUSED,
MPP1_GPIO, /* JTAG Clock */
MPP2_GPIO, /* JTAG Data In */
MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
MPP4_GPIO, /* JTAG Data Out */
MPP5_GPIO, /* JTAG TMS */
MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
MPP8_UNUSED,
MPP9_UNUSED,
MPP10_UNUSED,
MPP11_UNUSED,
MPP12_UNUSED,
MPP13_UNUSED,
MPP14_UNUSED,
MPP15_UNUSED,
MPP16_UART,
MPP17_UART,
MPP18_UART,
MPP19_UART,
/*
* MPP[20] PCI Clock Out 1
* MPP[21] PCI Clock Out 0
* MPP[22] Unused
* MPP[23] Unused
* MPP[24] Unused
* MPP[25] Unused
*/
0,
};
static void __init ts78xx_init(void)
{
int ret;
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(ts78xx_mpp_modes);
/*
* Configure peripherals.
*/
orion5x_ehci0_init();
orion5x_ehci1_init();
orion5x_eth_init(&ts78xx_eth_data);
orion5x_sata_init(&ts78xx_sata_data);
orion5x_uart0_init();
orion5x_uart1_init();
orion5x_xor_init();
/* FPGA init */
ts78xx_fpga_devices_zero_init();
ret = ts78xx_fpga_load();
ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
if (ret)
pr_err("sysfs_create_file failed: %d\n", ret);
}
MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
/* Maintainer: Alexander Clouter <[email protected]> */
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = ts78xx_init,
.map_io = ts78xx_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/ts78xx-setup.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* arch/arm/mach-orion5x/net2big-setup.c
*
* LaCie 2Big Network NAS setup
*
* Copyright (C) 2009 Simon Guinot <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/leds.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/ata_platform.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <plat/orion-gpio.h>
#include "common.h"
#include "mpp.h"
#include "orion5x.h"
/*****************************************************************************
* LaCie 2Big Network Info
****************************************************************************/
/*
* 512KB NOR flash Device bus boot chip select
*/
#define NET2BIG_NOR_BOOT_BASE 0xfff80000
#define NET2BIG_NOR_BOOT_SIZE SZ_512K
/*****************************************************************************
* 512KB NOR Flash on Boot Device
****************************************************************************/
/*
* TODO: Check write support on flash MX29LV400CBTC-70G
*/
static struct mtd_partition net2big_partitions[] = {
{
.name = "Full512kb",
.size = MTDPART_SIZ_FULL,
.offset = 0x00000000,
.mask_flags = MTD_WRITEABLE,
},
};
static struct physmap_flash_data net2big_nor_flash_data = {
.width = 1,
.parts = net2big_partitions,
.nr_parts = ARRAY_SIZE(net2big_partitions),
};
static struct resource net2big_nor_flash_resource = {
.flags = IORESOURCE_MEM,
.start = NET2BIG_NOR_BOOT_BASE,
.end = NET2BIG_NOR_BOOT_BASE
+ NET2BIG_NOR_BOOT_SIZE - 1,
};
static struct platform_device net2big_nor_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &net2big_nor_flash_data,
},
.num_resources = 1,
.resource = &net2big_nor_flash_resource,
};
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data net2big_eth_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
/*****************************************************************************
* I2C devices
****************************************************************************/
/*
* i2c addr | chip | description
* 0x32 | Ricoh 5C372b | RTC
* 0x50 | HT24LC08 | eeprom (1kB)
*/
static struct i2c_board_info __initdata net2big_i2c_devices[] = {
{
I2C_BOARD_INFO("rs5c372b", 0x32),
}, {
I2C_BOARD_INFO("24c08", 0x50),
},
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data net2big_sata_data = {
.n_ports = 2,
};
#define NET2BIG_GPIO_SATA_POWER_REQ 19
#define NET2BIG_GPIO_SATA0_POWER 23
#define NET2BIG_GPIO_SATA1_POWER 25
static void __init net2big_sata_power_init(void)
{
int err;
/* Configure GPIOs over MPP max number. */
orion_gpio_set_valid(NET2BIG_GPIO_SATA0_POWER, 1);
orion_gpio_set_valid(NET2BIG_GPIO_SATA1_POWER, 1);
err = gpio_request(NET2BIG_GPIO_SATA0_POWER, "SATA0 power status");
if (err == 0) {
err = gpio_direction_input(NET2BIG_GPIO_SATA0_POWER);
if (err)
gpio_free(NET2BIG_GPIO_SATA0_POWER);
}
if (err) {
pr_err("net2big: failed to setup SATA0 power GPIO\n");
return;
}
err = gpio_request(NET2BIG_GPIO_SATA1_POWER, "SATA1 power status");
if (err == 0) {
err = gpio_direction_input(NET2BIG_GPIO_SATA1_POWER);
if (err)
gpio_free(NET2BIG_GPIO_SATA1_POWER);
}
if (err) {
pr_err("net2big: failed to setup SATA1 power GPIO\n");
goto err_free_1;
}
err = gpio_request(NET2BIG_GPIO_SATA_POWER_REQ, "SATA power request");
if (err == 0) {
err = gpio_direction_output(NET2BIG_GPIO_SATA_POWER_REQ, 0);
if (err)
gpio_free(NET2BIG_GPIO_SATA_POWER_REQ);
}
if (err) {
pr_err("net2big: failed to setup SATA power request GPIO\n");
goto err_free_2;
}
if (gpio_get_value(NET2BIG_GPIO_SATA0_POWER) &&
gpio_get_value(NET2BIG_GPIO_SATA1_POWER)) {
return;
}
/*
* SATA power up on both disk is done by pulling high the CPLD power
* request line. The 300ms delay is related to the CPLD clock and is
* needed to be sure that the CPLD has take into account the low line
* status.
*/
msleep(300);
gpio_set_value(NET2BIG_GPIO_SATA_POWER_REQ, 1);
pr_info("net2big: power up SATA hard disks\n");
return;
err_free_2:
gpio_free(NET2BIG_GPIO_SATA1_POWER);
err_free_1:
gpio_free(NET2BIG_GPIO_SATA0_POWER);
return;
}
/*****************************************************************************
* GPIO LEDs
****************************************************************************/
/*
* The power front LEDs (blue and red) and SATA red LEDs are controlled via a
* single GPIO line and are compatible with the leds-gpio driver.
*
* The SATA blue LEDs have some hardware blink capabilities which are detailed
* in the following array:
*
* SATAx blue LED | SATAx activity | LED state
* | |
* 0 | 0 | blink (rate 300ms)
* 1 | 0 | off
* ? | 1 | on
*
* Notes: The blue and the red front LED's can't be on at the same time.
* Blue LED have priority.
*/
#define NET2BIG_GPIO_PWR_RED_LED 6
#define NET2BIG_GPIO_PWR_BLUE_LED 16
#define NET2BIG_GPIO_PWR_LED_BLINK_STOP 7
#define NET2BIG_GPIO_SATA0_RED_LED 11
#define NET2BIG_GPIO_SATA1_RED_LED 10
#define NET2BIG_GPIO_SATA0_BLUE_LED 17
#define NET2BIG_GPIO_SATA1_BLUE_LED 13
static struct gpio_led net2big_leds[] = {
{
.name = "net2big:red:power",
.gpio = NET2BIG_GPIO_PWR_RED_LED,
},
{
.name = "net2big:blue:power",
.gpio = NET2BIG_GPIO_PWR_BLUE_LED,
},
{
.name = "net2big:red:sata0",
.gpio = NET2BIG_GPIO_SATA0_RED_LED,
},
{
.name = "net2big:red:sata1",
.gpio = NET2BIG_GPIO_SATA1_RED_LED,
},
};
static struct gpio_led_platform_data net2big_led_data = {
.num_leds = ARRAY_SIZE(net2big_leds),
.leds = net2big_leds,
};
static struct platform_device net2big_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &net2big_led_data,
},
};
static void __init net2big_gpio_leds_init(void)
{
int err;
/* Stop initial CPLD slow red/blue blinking on power LED. */
err = gpio_request(NET2BIG_GPIO_PWR_LED_BLINK_STOP,
"Power LED blink stop");
if (err == 0) {
err = gpio_direction_output(NET2BIG_GPIO_PWR_LED_BLINK_STOP, 1);
if (err)
gpio_free(NET2BIG_GPIO_PWR_LED_BLINK_STOP);
}
if (err)
pr_err("net2big: failed to setup power LED blink GPIO\n");
/*
* Configure SATA0 and SATA1 blue LEDs to blink in relation with the
* hard disk activity.
*/
err = gpio_request(NET2BIG_GPIO_SATA0_BLUE_LED,
"SATA0 blue LED control");
if (err == 0) {
err = gpio_direction_output(NET2BIG_GPIO_SATA0_BLUE_LED, 1);
if (err)
gpio_free(NET2BIG_GPIO_SATA0_BLUE_LED);
}
if (err)
pr_err("net2big: failed to setup SATA0 blue LED GPIO\n");
err = gpio_request(NET2BIG_GPIO_SATA1_BLUE_LED,
"SATA1 blue LED control");
if (err == 0) {
err = gpio_direction_output(NET2BIG_GPIO_SATA1_BLUE_LED, 1);
if (err)
gpio_free(NET2BIG_GPIO_SATA1_BLUE_LED);
}
if (err)
pr_err("net2big: failed to setup SATA1 blue LED GPIO\n");
platform_device_register(&net2big_gpio_leds);
}
/****************************************************************************
* GPIO keys
****************************************************************************/
#define NET2BIG_GPIO_PUSH_BUTTON 18
#define NET2BIG_GPIO_POWER_SWITCH_ON 8
#define NET2BIG_GPIO_POWER_SWITCH_OFF 9
#define NET2BIG_SWITCH_POWER_ON 0x1
#define NET2BIG_SWITCH_POWER_OFF 0x2
static struct gpio_keys_button net2big_buttons[] = {
{
.type = EV_SW,
.code = NET2BIG_SWITCH_POWER_OFF,
.gpio = NET2BIG_GPIO_POWER_SWITCH_OFF,
.desc = "Power rocker switch (auto|off)",
.active_low = 0,
},
{
.type = EV_SW,
.code = NET2BIG_SWITCH_POWER_ON,
.gpio = NET2BIG_GPIO_POWER_SWITCH_ON,
.desc = "Power rocker switch (on|auto)",
.active_low = 0,
},
{
.type = EV_KEY,
.code = KEY_POWER,
.gpio = NET2BIG_GPIO_PUSH_BUTTON,
.desc = "Front Push Button",
.active_low = 0,
},
};
static struct gpio_keys_platform_data net2big_button_data = {
.buttons = net2big_buttons,
.nbuttons = ARRAY_SIZE(net2big_buttons),
};
static struct platform_device net2big_gpio_buttons = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &net2big_button_data,
},
};
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int net2big_mpp_modes[] __initdata = {
MPP0_GPIO, /* Raid mode (bit 0) */
MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
MPP2_GPIO, /* Raid mode (bit 1) */
MPP3_GPIO, /* Board ID (bit 0) */
MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
MPP5_GPIO, /* Fan fail detection */
MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
MPP7_GPIO, /* Disable initial blinking on front LED */
MPP8_GPIO, /* Rear power switch (on|auto) */
MPP9_GPIO, /* Rear power switch (auto|off) */
MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
MPP12_GPIO, /* Board ID (bit 1) */
MPP13_GPIO, /* SATA 1 blue LED blink control */
MPP14_SATA_LED,
MPP15_SATA_LED,
MPP16_GPIO, /* Blue front LED control */
MPP17_GPIO, /* SATA 0 blue LED blink control */
MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
MPP19_GPIO, /* SATA{0,1} power On/Off request */
0,
/* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
/* 23: SATA 0 power status */
/* 24: Board power off */
/* 25: SATA 1 power status */
};
#define NET2BIG_GPIO_POWER_OFF 24
static void net2big_power_off(void)
{
gpio_set_value(NET2BIG_GPIO_POWER_OFF, 1);
}
static void __init net2big_init(void)
{
/*
* Setup basic Orion functions. Need to be called early.
*/
orion5x_init();
orion5x_mpp_conf(net2big_mpp_modes);
/*
* Configure peripherals.
*/
orion5x_ehci0_init();
orion5x_ehci1_init();
orion5x_eth_init(&net2big_eth_data);
orion5x_i2c_init();
orion5x_uart0_init();
orion5x_xor_init();
net2big_sata_power_init();
orion5x_sata_init(&net2big_sata_data);
mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
ORION_MBUS_DEVBUS_BOOT_ATTR,
NET2BIG_NOR_BOOT_BASE,
NET2BIG_NOR_BOOT_SIZE);
platform_device_register(&net2big_nor_flash);
platform_device_register(&net2big_gpio_buttons);
net2big_gpio_leds_init();
i2c_register_board_info(0, net2big_i2c_devices,
ARRAY_SIZE(net2big_i2c_devices));
orion_gpio_set_valid(NET2BIG_GPIO_POWER_OFF, 1);
if (gpio_request(NET2BIG_GPIO_POWER_OFF, "power-off") == 0 &&
gpio_direction_output(NET2BIG_GPIO_POWER_OFF, 0) == 0)
pm_power_off = net2big_power_off;
else
pr_err("net2big: failed to configure power-off GPIO\n");
pr_notice("net2big: Flash writing is not yet supported.\n");
}
/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
MACHINE_START(NET2BIG, "LaCie 2Big Network")
.atag_offset = 0x100,
.nr_irqs = ORION5X_NR_IRQS,
.init_machine = net2big_init,
.map_io = orion5x_map_io,
.init_early = orion5x_init_early,
.init_irq = orion5x_init_irq,
.init_time = orion5x_timer_init,
.fixup = tag_fixup_mem32,
.restart = orion5x_restart,
MACHINE_END
| linux-master | arch/arm/mach-orion5x/net2big-setup.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Maxtor Shared Storage II Board Setup
*
* Maintainer: Sylver Bruneau <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include "orion5x.h"
#include "bridge-regs.h"
#include "common.h"
/*****************************************************************************
* Maxtor Shared Storage II Info
****************************************************************************/
/****************************************************************************
* PCI setup
****************************************************************************/
static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
if (irq != -1)
return irq;
return -1;
}
static struct hw_pci mss2_pci __initdata = {
.nr_controllers = 2,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = mss2_pci_map_irq,
};
static int __init mss2_pci_init(void)
{
if (machine_is_mss2())
pci_common_init(&mss2_pci);
return 0;
}
subsys_initcall(mss2_pci_init);
/*****************************************************************************
* MSS2 power off method
****************************************************************************/
/*
* On the Maxtor Shared Storage II, the shutdown process is the following :
* - Userland modifies U-boot env to tell U-boot to go idle at next boot
* - The board reboots
* - U-boot starts and go into an idle mode until the user press "power"
*/
static void mss2_power_off(void)
{
u32 reg;
/*
* Enable and issue soft reset
*/
reg = readl(RSTOUTn_MASK);
reg |= 1 << 2;
writel(reg, RSTOUTn_MASK);
reg = readl(CPU_SOFT_RESET);
reg |= 1;
writel(reg, CPU_SOFT_RESET);
}
void __init mss2_init(void)
{
/* register mss2 specific power-off method */
pm_power_off = mss2_power_off;
}
| linux-master | arch/arm/mach-orion5x/board-mss2.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Device Tree support for Rockchip SoCs
*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "core.h"
#include "pm.h"
#define RK3288_TIMER6_7_PHYS 0xff810000
static void __init rockchip_timer_init(void)
{
if (of_machine_is_compatible("rockchip,rk3288")) {
void __iomem *reg_base;
/*
* Most/all uboot versions for rk3288 don't enable timer7
* which is needed for the architected timer to work.
* So make sure it is running during early boot.
*/
reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
if (reg_base) {
writel(0, reg_base + 0x30);
writel(0xffffffff, reg_base + 0x20);
writel(0xffffffff, reg_base + 0x24);
writel(1, reg_base + 0x30);
dsb();
iounmap(reg_base);
} else {
pr_err("rockchip: could not map timer7 registers\n");
}
}
of_clk_init(NULL);
timer_probe();
}
static void __init rockchip_dt_init(void)
{
rockchip_suspend_init();
}
static const char * const rockchip_board_dt_compat[] = {
"rockchip,rk2928",
"rockchip,rk3066a",
"rockchip,rk3066b",
"rockchip,rk3188",
"rockchip,rk3228",
"rockchip,rk3288",
"rockchip,rv1108",
NULL,
};
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.init_time = rockchip_timer_init,
.dt_compat = rockchip_board_dt_compat,
.init_machine = rockchip_dt_init,
MACHINE_END
| linux-master | arch/arm/mach-rockchip/rockchip.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
* Author: Tony Xie <[email protected]>
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/suspend.h>
#include <linux/mfd/syscon.h>
#include <linux/regulator/machine.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/suspend.h>
#include "pm.h"
/* These enum are option of low power mode */
enum {
ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
};
struct rockchip_pm_data {
const struct platform_suspend_ops *ops;
int (*init)(struct device_node *np);
};
static void __iomem *rk3288_bootram_base;
static phys_addr_t rk3288_bootram_phy;
static struct regmap *pmu_regmap;
static struct regmap *sgrf_regmap;
static struct regmap *grf_regmap;
static u32 rk3288_pmu_pwr_mode_con;
static u32 rk3288_sgrf_soc_con0;
static u32 rk3288_sgrf_cpu_con0;
static inline u32 rk3288_l2_config(void)
{
u32 l2ctlr;
asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
return l2ctlr;
}
static void __init rk3288_config_bootdata(void)
{
rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
rkpm_bootdata_l2ctlr_f = 1;
rkpm_bootdata_l2ctlr = rk3288_l2_config();
}
#define GRF_UOC0_CON0 0x320
#define GRF_UOC1_CON0 0x334
#define GRF_UOC2_CON0 0x348
#define GRF_SIDDQ BIT(13)
static bool rk3288_slp_disable_osc(void)
{
static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
GRF_UOC2_CON0 };
u32 reg, i;
/*
* if any usb phy is still on(GRF_SIDDQ==0), that means we need the
* function of usb wakeup, so do not switch to 32khz, since the usb phy
* clk does not connect to 32khz osc
*/
for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
regmap_read(grf_regmap, reg_offset[i], ®);
if (!(reg & GRF_SIDDQ))
return false;
}
return true;
}
static void rk3288_slp_mode_set(int level)
{
u32 mode_set, mode_set1;
bool osc_disable = rk3288_slp_disable_osc();
regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
&rk3288_pmu_pwr_mode_con);
/*
* SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
* PCLK_WDT_GATE - disable WDT during suspend.
*/
regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
| SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
/*
* The dapswjdp can not auto reset before resume, that cause it may
* access some illegal address during resume. Let's disable it before
* suspend, and the MASKROM will enable it back.
*/
regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
/* booting address of resuming system is from this register value */
regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
rk3288_bootram_phy);
mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
BIT(PMU_SCU_EN);
mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
/* arm off, logic deep sleep */
mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) |
BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
if (osc_disable)
mode_set |= BIT(PMU_OSC_24M_DIS);
mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
PMU_ARMINT_WAKEUP_EN);
/*
* In deep suspend we use PMU_PMU_USE_LF to let the rk3288
* switch its main clock supply to the alternative 32kHz
* source. Therefore set 30ms on a 32kHz clock for pmic
* stabilization. Similar 30ms on 24MHz for the other
* mode below.
*/
regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
/* only wait for stabilization, if we turned the osc off */
regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
osc_disable ? 32 * 30 : 0);
} else {
/*
* arm off, logic normal
* if pmu_clk_core_src_gate_en is not set,
* wakeup will be error
*/
mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);
/* 30ms on a 24MHz clock for pmic stabilization */
regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
/* oscillator is still running, so no need to wait */
regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
}
regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
}
static void rk3288_slp_mode_set_resume(void)
{
regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
rk3288_pmu_pwr_mode_con);
regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
| SGRF_FAST_BOOT_EN_WRITE);
}
static int rockchip_lpmode_enter(unsigned long arg)
{
flush_cache_all();
cpu_do_idle();
pr_err("%s: Failed to suspend\n", __func__);
return 1;
}
static int rk3288_suspend_enter(suspend_state_t state)
{
local_fiq_disable();
rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
cpu_suspend(0, rockchip_lpmode_enter);
rk3288_slp_mode_set_resume();
local_fiq_enable();
return 0;
}
static int rk3288_suspend_prepare(void)
{
return regulator_suspend_prepare(PM_SUSPEND_MEM);
}
static void rk3288_suspend_finish(void)
{
if (regulator_suspend_finish())
pr_err("%s: Suspend finish failed\n", __func__);
}
static int __init rk3288_suspend_init(struct device_node *np)
{
struct device_node *sram_np;
struct resource res;
int ret;
pmu_regmap = syscon_node_to_regmap(np);
if (IS_ERR(pmu_regmap)) {
pr_err("%s: could not find pmu regmap\n", __func__);
return PTR_ERR(pmu_regmap);
}
sgrf_regmap = syscon_regmap_lookup_by_compatible(
"rockchip,rk3288-sgrf");
if (IS_ERR(sgrf_regmap)) {
pr_err("%s: could not find sgrf regmap\n", __func__);
return PTR_ERR(sgrf_regmap);
}
grf_regmap = syscon_regmap_lookup_by_compatible(
"rockchip,rk3288-grf");
if (IS_ERR(grf_regmap)) {
pr_err("%s: could not find grf regmap\n", __func__);
return PTR_ERR(grf_regmap);
}
sram_np = of_find_compatible_node(NULL, NULL,
"rockchip,rk3288-pmu-sram");
if (!sram_np) {
pr_err("%s: could not find bootram dt node\n", __func__);
return -ENODEV;
}
rk3288_bootram_base = of_iomap(sram_np, 0);
if (!rk3288_bootram_base) {
pr_err("%s: could not map bootram base\n", __func__);
of_node_put(sram_np);
return -ENOMEM;
}
ret = of_address_to_resource(sram_np, 0, &res);
if (ret) {
pr_err("%s: could not get bootram phy addr\n", __func__);
of_node_put(sram_np);
return ret;
}
rk3288_bootram_phy = res.start;
of_node_put(sram_np);
rk3288_config_bootdata();
/* copy resume code and data to bootsram */
memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
rk3288_bootram_sz);
return 0;
}
static const struct platform_suspend_ops rk3288_suspend_ops = {
.enter = rk3288_suspend_enter,
.valid = suspend_valid_only_mem,
.prepare = rk3288_suspend_prepare,
.finish = rk3288_suspend_finish,
};
static const struct rockchip_pm_data rk3288_pm_data __initconst = {
.ops = &rk3288_suspend_ops,
.init = rk3288_suspend_init,
};
static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
{
.compatible = "rockchip,rk3288-pmu",
.data = &rk3288_pm_data,
},
{ /* sentinel */ },
};
void __init rockchip_suspend_init(void)
{
const struct rockchip_pm_data *pm_data;
const struct of_device_id *match;
struct device_node *np;
int ret;
np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
&match);
if (!match) {
pr_err("Failed to find PMU node\n");
goto out_put;
}
pm_data = (struct rockchip_pm_data *) match->data;
if (pm_data->init) {
ret = pm_data->init(np);
if (ret) {
pr_err("%s: matches init error %d\n", __func__, ret);
goto out_put;
}
}
suspend_set_ops(pm_data->ops);
out_put:
of_node_put(np);
}
| linux-master | arch/arm/mach-rockchip/pm.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <[email protected]>
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/reset.h>
#include <linux/cpu.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include <asm/mach/map.h>
#include "core.h"
static void __iomem *scu_base_addr;
static void __iomem *sram_base_addr;
static int ncores;
#define PMU_PWRDN_CON 0x08
#define PMU_PWRDN_ST 0x0c
#define PMU_PWRDN_SCU 4
static struct regmap *pmu;
static int has_pmu = true;
static int pmu_power_domain_is_on(int pd)
{
u32 val;
int ret;
ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
if (ret < 0)
return ret;
return !(val & BIT(pd));
}
static struct reset_control *rockchip_get_core_reset(int cpu)
{
struct device *dev = get_cpu_device(cpu);
struct device_node *np;
/* The cpu device is only available after the initial core bringup */
if (dev)
np = dev->of_node;
else
np = of_get_cpu_node(cpu, NULL);
return of_reset_control_get_exclusive(np, NULL);
}
static int pmu_set_power_domain(int pd, bool on)
{
u32 val = (on) ? 0 : BIT(pd);
struct reset_control *rstc = rockchip_get_core_reset(pd);
int ret;
if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
pr_err("%s: could not get reset control for core %d\n",
__func__, pd);
return PTR_ERR(rstc);
}
/*
* We need to soft reset the cpu when we turn off the cpu power domain,
* or else the active processors might be stalled when the individual
* processor is powered down.
*/
if (!IS_ERR(rstc) && !on)
reset_control_assert(rstc);
if (has_pmu) {
ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
pr_err("%s: could not update power domain\n",
__func__);
return ret;
}
ret = -1;
while (ret != on) {
ret = pmu_power_domain_is_on(pd);
if (ret < 0) {
pr_err("%s: could not read power domain state\n",
__func__);
return ret;
}
}
}
if (!IS_ERR(rstc)) {
if (on)
reset_control_deassert(rstc);
reset_control_put(rstc);
}
return 0;
}
/*
* Handling of CPU cores
*/
static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int ret;
if (!sram_base_addr || (has_pmu && !pmu)) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
if (cpu >= ncores) {
pr_err("%s: cpu %d outside maximum number of cpus %d\n",
__func__, cpu, ncores);
return -ENXIO;
}
/* start the core */
ret = pmu_set_power_domain(0 + cpu, true);
if (ret < 0)
return ret;
if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
/*
* We communicate with the bootrom to active the cpus other
* than cpu0, after a blob of initialize code, they will
* stay at wfe state, once they are activated, they will check
* the mailbox:
* sram_base_addr + 4: 0xdeadbeaf
* sram_base_addr + 8: start address for pc
* The cpu0 need to wait the other cpus other than cpu0 entering
* the wfe state.The wait time is affected by many aspects.
* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
*/
mdelay(1); /* ensure the cpus other than cpu0 to startup */
writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
return 0;
}
/**
* rockchip_smp_prepare_sram - populate necessary sram block
* Starting cores execute the code residing at the start of the on-chip sram
* after power-on. Therefore make sure, this sram region is reserved and
* big enough. After this check, copy the trampoline code that directs the
* core to the real startup code in ram into the sram-region.
* @node: mmio-sram device node
*/
static int __init rockchip_smp_prepare_sram(struct device_node *node)
{
unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
&rockchip_secondary_trampoline;
struct resource res;
unsigned int rsize;
int ret;
ret = of_address_to_resource(node, 0, &res);
if (ret < 0) {
pr_err("%s: could not get address for node %pOF\n",
__func__, node);
return ret;
}
rsize = resource_size(&res);
if (rsize < trampoline_sz) {
pr_err("%s: reserved block with size 0x%x is too small for trampoline size 0x%x\n",
__func__, rsize, trampoline_sz);
return -EINVAL;
}
/* set the boot function for the sram code */
rockchip_boot_fn = __pa_symbol(secondary_startup);
/* copy the trampoline to sram, that runs during startup of the core */
memcpy_toio(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
flush_cache_all();
outer_clean_range(0, trampoline_sz);
dsb_sev();
return 0;
}
static const struct regmap_config rockchip_pmu_regmap_config = {
.name = "rockchip-pmu",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static int __init rockchip_smp_prepare_pmu(void)
{
struct device_node *node;
void __iomem *pmu_base;
/*
* This function is only called via smp_ops->smp_prepare_cpu().
* That only happens if a "/cpus" device tree node exists
* and has an "enable-method" property that selects the SMP
* operations defined herein.
*/
node = of_find_node_by_path("/cpus");
pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
of_node_put(node);
if (!IS_ERR(pmu))
return 0;
pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
if (!IS_ERR(pmu))
return 0;
/* fallback, create our own regmap for the pmu area */
pmu = NULL;
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
if (!node) {
pr_err("%s: could not find pmu dt node\n", __func__);
return -ENODEV;
}
pmu_base = of_iomap(node, 0);
of_node_put(node);
if (!pmu_base) {
pr_err("%s: could not map pmu registers\n", __func__);
return -ENOMEM;
}
pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
if (IS_ERR(pmu)) {
int ret = PTR_ERR(pmu);
iounmap(pmu_base);
pmu = NULL;
pr_err("%s: regmap init failed\n", __func__);
return ret;
}
return 0;
}
static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *node;
unsigned int i;
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
if (!node) {
pr_err("%s: could not find sram dt node\n", __func__);
return;
}
sram_base_addr = of_iomap(node, 0);
if (!sram_base_addr) {
pr_err("%s: could not map sram registers\n", __func__);
of_node_put(node);
return;
}
if (has_pmu && rockchip_smp_prepare_pmu()) {
of_node_put(node);
return;
}
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
if (rockchip_smp_prepare_sram(node)) {
of_node_put(node);
return;
}
/* enable the SCU power domain */
pmu_set_power_domain(PMU_PWRDN_SCU, true);
of_node_put(node);
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!node) {
pr_err("%s: missing scu\n", __func__);
return;
}
scu_base_addr = of_iomap(node, 0);
if (!scu_base_addr) {
pr_err("%s: could not map scu registers\n", __func__);
of_node_put(node);
return;
}
/*
* While the number of cpus is gathered from dt, also get the
* number of cores from the scu to verify this value when
* booting the cores.
*/
ncores = scu_get_core_count(scu_base_addr);
pr_err("%s: ncores %d\n", __func__, ncores);
scu_enable(scu_base_addr);
} else {
unsigned int l2ctlr;
asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
ncores = ((l2ctlr >> 24) & 0x3) + 1;
}
of_node_put(node);
/* Make sure that all cores except the first are really off */
for (i = 1; i < ncores; i++)
pmu_set_power_domain(0 + i, false);
}
static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
{
has_pmu = false;
rockchip_smp_prepare_cpus(max_cpus);
}
#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
/*
* We need a delay here to ensure that the dying CPU can finish
* executing v7_coherency_exit() and reach the WFI/WFE state
* prior to having the power domain disabled.
*/
mdelay(1);
pmu_set_power_domain(0 + cpu, false);
return 1;
}
static void rockchip_cpu_die(unsigned int cpu)
{
v7_exit_coherency_flush(louis);
while (1)
cpu_do_idle();
}
#endif
static const struct smp_operations rk3036_smp_ops __initconst = {
.smp_prepare_cpus = rk3036_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = rockchip_cpu_kill,
.cpu_die = rockchip_cpu_die,
#endif
};
static const struct smp_operations rockchip_smp_ops __initconst = {
.smp_prepare_cpus = rockchip_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = rockchip_cpu_kill,
.cpu_die = rockchip_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
| linux-master | arch/arm/mach-rockchip/platsmp.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Gemini Device Tree boot support
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <asm/proc-fns.h>
#ifdef CONFIG_DEBUG_GEMINI
/* This is needed for LL-debug/earlyprintk/debug-macro.S */
static struct map_desc gemini_io_desc[] __initdata = {
{
.virtual = CONFIG_DEBUG_UART_VIRT,
.pfn = __phys_to_pfn(CONFIG_DEBUG_UART_PHYS),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void __init gemini_map_io(void)
{
iotable_init(gemini_io_desc, ARRAY_SIZE(gemini_io_desc));
}
#else
#define gemini_map_io NULL
#endif
static void gemini_idle(void)
{
/*
* Because of broken hardware we have to enable interrupts or the CPU
* will never wakeup... Acctualy it is not very good to enable
* interrupts first since scheduler can miss a tick, but there is
* no other way around this. Platforms that needs it for power saving
* should enable it in init code, since by default it is
* disabled.
*/
/* FIXME: Enabling interrupts here is racy! */
raw_local_irq_enable();
cpu_do_idle();
raw_local_irq_disable();
}
static void __init gemini_init_machine(void)
{
arm_pm_idle = gemini_idle;
}
static const char *gemini_board_compat[] = {
"cortina,gemini",
NULL,
};
DT_MACHINE_START(GEMINI_DT, "Gemini (Device Tree)")
.map_io = gemini_map_io,
.init_machine = gemini_init_machine,
.dt_compat = gemini_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-gemini/board-dt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MX31 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <[email protected]>
*/
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include "common.h"
#include "hardware.h"
#include "iim.h"
static int mx31_cpu_rev = -1;
static struct {
u8 srev;
const char *name;
unsigned int rev;
} mx31_cpu_type[] = {
{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
{ .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 },
{ .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 },
{ .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 },
{ .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 },
};
static int mx31_read_cpu_rev(void)
{
void __iomem *iim_base;
struct device_node *np;
u32 i, srev;
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
iim_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!iim_base);
/* read SREV register from IIM module */
srev = imx_readl(iim_base + MXC_IIMSREV);
srev &= 0xff;
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev) {
imx_print_silicon_rev(mx31_cpu_type[i].name,
mx31_cpu_type[i].rev);
return mx31_cpu_type[i].rev;
}
imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
return IMX_CHIP_REVISION_UNKNOWN;
}
int mx31_revision(void)
{
if (mx31_cpu_rev == -1)
mx31_cpu_rev = mx31_read_cpu_rev();
return mx31_cpu_rev;
}
EXPORT_SYMBOL(mx31_revision);
| linux-master | arch/arm/mach-imx/cpu-imx31.c |
/*
* i.MX27 Power Management Routines
*
* Based on Freescale's BSP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*/
#include <linux/of_address.h>
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
#include "common.h"
#include "hardware.h"
static int mx27_suspend_enter(suspend_state_t state)
{
void __iomem *ccm_base;
struct device_node *np;
u32 cscr;
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
ccm_base = of_iomap(np, 0);
BUG_ON(!ccm_base);
switch (state) {
case PM_SUSPEND_MEM:
/* Clear MPEN and SPEN to disable MPLL/SPLL */
cscr = imx_readl(ccm_base);
cscr &= 0xFFFFFFFC;
imx_writel(cscr, ccm_base);
/* Executes WFI */
cpu_do_idle();
break;
default:
return -EINVAL;
}
return 0;
}
static const struct platform_suspend_ops mx27_suspend_ops = {
.enter = mx27_suspend_enter,
.valid = suspend_valid_only_mem,
};
void __init imx27_pm_init(void)
{
suspend_set_ops(&mx27_suspend_ops);
}
| linux-master | arch/arm/mach-imx/pm-imx27.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This file contains the CPU initialization code.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "hardware.h"
#include "common.h"
static int mx5_cpu_rev = -1;
#define IIM_SREV 0x24
static u32 imx5_read_srev_reg(const char *compat)
{
void __iomem *iim_base;
struct device_node *np;
u32 srev;
np = of_find_compatible_node(NULL, NULL, compat);
iim_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!iim_base);
srev = readl(iim_base + IIM_SREV) & 0xff;
iounmap(iim_base);
return srev;
}
static int get_mx51_srev(void)
{
u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
switch (rev) {
case 0x0:
return IMX_CHIP_REVISION_2_0;
case 0x10:
return IMX_CHIP_REVISION_3_0;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
}
/*
* Returns:
* the silicon revision of the cpu
*/
int mx51_revision(void)
{
if (mx5_cpu_rev == -1)
mx5_cpu_rev = get_mx51_srev();
return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx51_revision);
#ifdef CONFIG_NEON
/*
* All versions of the silicon before Rev. 3 have broken NEON implementations.
* Dependent on link order - so the assumption is that vfp_init is called
* before us.
*/
int __init mx51_neon_fixup(void)
{
if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
(elf_hwcap & HWCAP_NEON)) {
elf_hwcap &= ~HWCAP_NEON;
pr_info("Turning off NEON support, detected broken NEON implementation\n");
}
return 0;
}
#endif
static int get_mx53_srev(void)
{
u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
switch (rev) {
case 0x0:
return IMX_CHIP_REVISION_1_0;
case 0x2:
return IMX_CHIP_REVISION_2_0;
case 0x3:
return IMX_CHIP_REVISION_2_1;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
}
/*
* Returns:
* the silicon revision of the cpu
*/
int mx53_revision(void)
{
if (mx5_cpu_rev == -1)
mx5_cpu_rev = get_mx53_srev();
return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx53_revision);
#define ARM_GPC 0x4
#define DBGEN BIT(16)
/*
* This enables the DBGEN bit in ARM_GPC register, which is
* required for accessing some performance counter features.
* Technically it is only required while perf is used, but to
* keep the source code simple we just enable it all the time
* when the kernel configuration allows using the feature.
*/
void __init imx5_pmu_init(void)
{
void __iomem *tigerp_base;
struct device_node *np;
u32 gpc;
if (!IS_ENABLED(CONFIG_ARM_PMU))
return;
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
if (!np)
return;
if (!of_property_read_bool(np, "secure-reg-access"))
goto exit;
of_node_put(np);
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp");
if (!np)
return;
tigerp_base = of_iomap(np, 0);
if (!tigerp_base)
goto exit;
gpc = readl_relaxed(tigerp_base + ARM_GPC);
gpc |= DBGEN;
writel_relaxed(gpc, tigerp_base + ARM_GPC);
iounmap(tigerp_base);
exit:
of_node_put(np);
}
| linux-master | arch/arm/mach-imx/cpu-imx5.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*/
#include <linux/clk/imx.h>
#include <linux/cpuidle.h>
#include <linux/module.h>
#include <asm/cpuidle.h>
#include "common.h"
#include "cpuidle.h"
static __cpuidle int imx6sl_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
imx6_set_lpm(WAIT_UNCLOCKED);
/*
* Software workaround for ERR005311, see function
* description for details.
*/
imx6sl_set_wait_clk(true);
cpu_do_idle();
imx6sl_set_wait_clk(false);
imx6_set_lpm(WAIT_CLOCKED);
return index;
}
static struct cpuidle_driver imx6sl_cpuidle_driver = {
.name = "imx6sl_cpuidle",
.owner = THIS_MODULE,
.states = {
/* WFI */
ARM_CPUIDLE_WFI_STATE,
/* WAIT */
{
.exit_latency = 50,
.target_residency = 75,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sl_enter_wait,
.name = "WAIT",
.desc = "Clock off",
},
},
.state_count = 2,
.safe_state_index = 0,
};
int __init imx6sl_cpuidle_init(void)
{
return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
}
| linux-master | arch/arm/mach-imx/cpuidle-imx6sl.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Sascha Hauer, Pengutronix
*/
#include <asm/mach/arch.h>
#include "common.h"
#include "hardware.h"
static void __init imx25_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX25);
}
static void __init imx25_dt_init(void)
{
imx_aips_allow_unprivileged_access("fsl,imx25-aips");
}
static const char * const imx25_dt_board_compat[] __initconst = {
"fsl,imx25",
NULL
};
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
.init_early = imx25_init_early,
.init_machine = imx25_dt_init,
.init_late = imx25_pm_init,
.dt_compat = imx25_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-imx/mach-imx25.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) BitBox Ltd 2010
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/platform_data/asoc-imx-ssi.h>
#include "irq-common.h"
int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{
struct irq_chip_generic *gc;
struct mxc_extra_irq *exirq;
int ret;
ret = -ENOSYS;
gc = irq_get_chip_data(irq);
if (gc && gc->private) {
exirq = gc->private;
if (exirq->set_irq_fiq) {
struct irq_data *d = irq_get_irq_data(irq);
ret = exirq->set_irq_fiq(irqd_to_hwirq(d), type);
}
}
return ret;
}
EXPORT_SYMBOL(mxc_set_irq_fiq);
| linux-master | arch/arm/mach-imx/irq-common.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MX35 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <[email protected]>
*/
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include "hardware.h"
#include "iim.h"
static int mx35_cpu_rev = -1;
static int mx35_read_cpu_rev(void)
{
void __iomem *iim_base;
struct device_node *np;
u32 rev;
np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim");
iim_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!iim_base);
rev = imx_readl(iim_base + MXC_IIMSREV);
switch (rev) {
case 0x00:
return IMX_CHIP_REVISION_1_0;
case 0x10:
return IMX_CHIP_REVISION_2_0;
case 0x11:
return IMX_CHIP_REVISION_2_1;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
}
int mx35_revision(void)
{
if (mx35_cpu_rev == -1)
mx35_cpu_rev = mx35_read_cpu_rev();
return mx35_cpu_rev;
}
EXPORT_SYMBOL(mx35_revision);
| linux-master | arch/arm/mach-imx/cpu-imx35.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2012 Steffen Trumtrar, Pengutronix
*
* based on imx27-dt.c
*/
#include <asm/mach/arch.h>
#include "common.h"
#include "mx35.h"
static const char * const imx35_dt_board_compat[] __initconst = {
"fsl,imx35",
NULL
};
DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.dt_compat = imx35_dt_board_compat,
MACHINE_END
| linux-master | arch/arm/mach-imx/mach-imx35.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include "common.h"
#include "hardware.h"
#include "irq-common.h"
/*
*****************************************
* TZIC Registers *
*****************************************
*/
#define TZIC_INTCNTL 0x0000 /* Control register */
#define TZIC_INTTYPE 0x0004 /* Controller Type register */
#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
#define TZIC_PND0 0x0D00 /* Pending Register 0 */
#define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
static void __iomem *tzic_base;
static struct irq_domain *domain;
#define TZIC_NUM_IRQS 128
#ifdef CONFIG_FIQ
static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type)
{
unsigned int index, mask, value;
index = hwirq >> 5;
if (unlikely(index >= 4))
return -EINVAL;
mask = 1U << (hwirq & 0x1F);
value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
if (type)
value &= ~mask;
imx_writel(value, tzic_base + TZIC_INTSEC0(index));
return 0;
}
#else
#define tzic_set_irq_fiq NULL
#endif
#ifdef CONFIG_PM
static void tzic_irq_suspend(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int idx = d->hwirq >> 5;
imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
}
static void tzic_irq_resume(struct irq_data *d)
{
int idx = d->hwirq >> 5;
imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
tzic_base + TZIC_WAKEUP0(idx));
}
#else
#define tzic_irq_suspend NULL
#define tzic_irq_resume NULL
#endif
static struct mxc_extra_irq tzic_extra_irq = {
#ifdef CONFIG_FIQ
.set_irq_fiq = tzic_set_irq_fiq,
#endif
};
static __init void tzic_init_gc(int idx, unsigned int irq_start)
{
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
handle_level_irq);
gc->private = &tzic_extra_irq;
gc->wake_enabled = IRQ_MSK(32);
ct = gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
ct->chip.irq_set_wake = irq_gc_set_wake;
ct->chip.irq_suspend = tzic_irq_suspend;
ct->chip.irq_resume = tzic_irq_resume;
ct->regs.disable = TZIC_ENCLEAR0(idx);
ct->regs.enable = TZIC_ENSET0(idx);
irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}
static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
{
u32 stat;
int i, irqofs, handled;
do {
handled = 0;
for (i = 0; i < 4; i++) {
stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
imx_readl(tzic_base + TZIC_INTSEC0(i));
while (stat) {
handled = 1;
irqofs = fls(stat) - 1;
generic_handle_domain_irq(domain, irqofs + i * 32);
stat &= ~(1 << irqofs);
}
}
} while (handled);
}
/*
* This function initializes the TZIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
static int __init tzic_init_dt(struct device_node *np, struct device_node *p)
{
int irq_base;
int i;
tzic_base = of_iomap(np, 0);
WARN_ON(!tzic_base);
/* put the TZIC into the reset value with
* all interrupts disabled
*/
i = imx_readl(tzic_base + TZIC_INTCNTL);
imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
for (i = 0; i < 4; i++)
imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
/* disable all interrupts */
for (i = 0; i < 4; i++)
imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
/* all IRQ no FIQ Warning :: No selection */
irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
WARN_ON(irq_base < 0);
domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
&irq_domain_simple_ops, NULL);
WARN_ON(!domain);
for (i = 0; i < 4; i++, irq_base += 32)
tzic_init_gc(i, irq_base);
set_handle_irq(tzic_handle_irq);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ(FIQ_START);
#endif
pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
return 0;
}
IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt);
/**
* tzic_enable_wake() - enable wakeup interrupt
*
* @return 0 if successful; non-zero otherwise
*
* This function provides an interrupt synchronization point that is required
* by tzic enabled platforms before entering imx specific low power modes (ie,
* those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
*/
int tzic_enable_wake(void)
{
unsigned int i;
imx_writel(1, tzic_base + TZIC_DSMINT);
if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
return -EAGAIN;
for (i = 0; i < 4; i++)
imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
tzic_base + TZIC_WAKEUP0(i));
return 0;
}
| linux-master | arch/arm/mach-imx/tzic.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Pengutronix, Oleksij Rempel <[email protected]>
*/
#include <linux/kernel.h>
#include <asm/v7m.h>
#include <asm/mach/arch.h>
static const char * const imx7d_cm4_dt_compat[] __initconst = {
"fsl,imx7d-cm4",
NULL,
};
DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
.dt_compat = imx7d_cm4_dt_compat,
.restart = armv7m_restart,
MACHINE_END
| linux-master | arch/arm/mach-imx/mach-imx7d-cm4.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <[email protected]>
*/
#include <linux/kernel.h>
#include <asm/mach/arch.h>
#include <asm/v7m.h>
static const char *const imxrt_compat[] __initconst = {
"fsl,imxrt1050",
NULL
};
DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)")
.dt_compat = imxrt_compat,
.restart = armv7m_restart,
MACHINE_END
| linux-master | arch/arm/mach-imx/mach-imxrt.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MX25 CPU type detection
*
* Copyright (c) 2009 Daniel Mack <[email protected]>
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "iim.h"
#include "hardware.h"
static int mx25_cpu_rev = -1;
static int mx25_read_cpu_rev(void)
{
u32 rev;
void __iomem *iim_base;
struct device_node *np;
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim");
iim_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!iim_base);
rev = readl(iim_base + MXC_IIMSREV);
iounmap(iim_base);
switch (rev) {
case 0x00:
return IMX_CHIP_REVISION_1_0;
case 0x01:
return IMX_CHIP_REVISION_1_1;
case 0x02:
return IMX_CHIP_REVISION_1_2;
default:
return IMX_CHIP_REVISION_UNKNOWN;
}
}
int mx25_revision(void)
{
if (mx25_cpu_rev == -1)
mx25_cpu_rev = mx25_read_cpu_rev();
return mx25_cpu_rev;
}
EXPORT_SYMBOL(mx25_revision);
| linux-master | arch/arm/mach-imx/cpu-imx25.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include "common.h"
#include "hardware.h"
#define REG_SET 0x4
#define REG_CLR 0x8
#define ANADIG_REG_2P5 0x130
#define ANADIG_REG_CORE 0x140
#define ANADIG_ANA_MISC0 0x150
#define ANADIG_DIGPROG 0x260
#define ANADIG_DIGPROG_IMX6SL 0x280
#define ANADIG_DIGPROG_IMX7D 0x800
#define SRC_SBMR2 0x1c
#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
static struct regmap *anatop;
static void imx_anatop_enable_weak2p5(bool enable)
{
u32 reg, val;
regmap_read(anatop, ANADIG_ANA_MISC0, &val);
/* can only be enabled when stop_mode_config is clear. */
reg = ANADIG_REG_2P5;
reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
REG_SET : REG_CLR;
regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
}
static void imx_anatop_enable_fet_odrive(bool enable)
{
regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
BM_ANADIG_REG_CORE_FET_ODRIVE);
}
static inline void imx_anatop_enable_2p5_pulldown(bool enable)
{
regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
}
static inline void imx_anatop_disconnect_high_snvs(bool enable)
{
regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
}
void imx_anatop_pre_suspend(void)
{
if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
imx_anatop_enable_2p5_pulldown(true);
else
imx_anatop_enable_weak2p5(true);
imx_anatop_enable_fet_odrive(true);
if (cpu_is_imx6sl())
imx_anatop_disconnect_high_snvs(true);
}
void imx_anatop_post_resume(void)
{
if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
imx_anatop_enable_2p5_pulldown(false);
else
imx_anatop_enable_weak2p5(false);
imx_anatop_enable_fet_odrive(false);
if (cpu_is_imx6sl())
imx_anatop_disconnect_high_snvs(false);
}
void __init imx_init_revision_from_anatop(void)
{
struct device_node *np, *src_np;
void __iomem *anatop_base;
unsigned int revision;
u32 digprog;
u16 offset = ANADIG_DIGPROG;
u8 major_part, minor_part;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = of_iomap(np, 0);
WARN_ON(!anatop_base);
if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
offset = ANADIG_DIGPROG_IMX6SL;
if (of_device_is_compatible(np, "fsl,imx7d-anatop"))
offset = ANADIG_DIGPROG_IMX7D;
digprog = readl_relaxed(anatop_base + offset);
iounmap(anatop_base);
/*
* On i.MX7D digprog value match linux version format, so
* it needn't map again and we can use register value directly.
*/
if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {
revision = digprog & 0xff;
} else {
/*
* MAJOR: [15:8], the major silicon revison;
* MINOR: [7: 0], the minor silicon revison;
*
* please refer to the i.MX RM for the detailed
* silicon revison bit define.
* format the major part and minor part to match the
* linux kernel soc version format.
*/
major_part = (digprog >> 8) & 0xf;
minor_part = digprog & 0xf;
revision = ((major_part + 1) << 4) | minor_part;
if ((digprog >> 16) == MXC_CPU_IMX6ULL) {
void __iomem *src_base;
u32 sbmr2;
src_np = of_find_compatible_node(NULL, NULL,
"fsl,imx6ul-src");
src_base = of_iomap(src_np, 0);
of_node_put(src_np);
WARN_ON(!src_base);
sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
iounmap(src_base);
/* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */
if (sbmr2 & (1 << 6)) {
digprog &= ~(0xff << 16);
digprog |= (MXC_CPU_IMX6ULZ << 16);
}
}
}
of_node_put(np);
mxc_set_cpu_type(digprog >> 16 & 0xff);
imx_set_soc_revision(revision);
}
void __init imx_anatop_init(void)
{
anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
if (IS_ERR(anatop))
pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
}
| linux-master | arch/arm/mach-imx/anatop.c |
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