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// SPDX-License-Identifier: GPL-2.0
/*
* printf.c: Internal prom library printf facility.
*
* Copyright (C) 1995 David S. Miller ([email protected])
*/
/* This routine is internal to the prom library, no one else should know
* about or use it! It's simple and smelly anyway....
*/
#include <linux/kernel.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#ifdef CONFIG_KGDB
extern int kgdb_initialized;
#endif
static char ppbuf[1024];
void
prom_printf(char *fmt, ...)
{
va_list args;
char ch, *bptr;
int i;
va_start(args, fmt);
#ifdef CONFIG_KGDB
ppbuf[0] = 'O';
i = vsprintf(ppbuf + 1, fmt, args) + 1;
#else
i = vsprintf(ppbuf, fmt, args);
#endif
bptr = ppbuf;
#ifdef CONFIG_KGDB
if (kgdb_initialized) {
pr_info("kgdb_initialized = %d\n", kgdb_initialized);
putpacket(bptr, 1);
} else
#else
while((ch = *(bptr++)) != 0) {
if(ch == '\n')
prom_putchar('\r');
prom_putchar(ch);
}
#endif
va_end(args);
return;
}
| linux-master | arch/m68k/sun3/prom/printf.c |
// SPDX-License-Identifier: GPL-2.0
/*
* init.c: Initialize internal variables used by the PROM
* library functions.
*
* Copyright (C) 1995 David S. Miller ([email protected])
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
struct linux_romvec *romvec;
enum prom_major_version prom_vers;
unsigned int prom_rev, prom_prev;
/* The root node of the prom device tree. */
int prom_root_node;
/* Pointer to the device tree operations structure. */
struct linux_nodeops *prom_nodeops;
/* You must call prom_init() before you attempt to use any of the
* routines in the prom library.
* It gets passed the pointer to the PROM vector.
*/
void __init prom_init(struct linux_romvec *rp)
{
romvec = rp;
/* Initialization successful. */
return;
}
| linux-master | arch/m68k/sun3/prom/init.c |
// SPDX-License-Identifier: GPL-2.0
/*
* console.c: Routines that deal with sending and receiving IO
* to/from the current console device using the PROM.
*
* Copyright (C) 1995 David S. Miller ([email protected])
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#include <linux/string.h>
/* Non blocking get character from console input device, returns -1
* if no input was taken. This can be used for polling.
*/
int
prom_nbgetchar(void)
{
int i = -1;
unsigned long flags;
local_irq_save(flags);
i = (*(romvec->pv_nbgetchar))();
local_irq_restore(flags);
return i; /* Ugh, we could spin forever on unsupported proms ;( */
}
/* Non blocking put character to console device, returns -1 if
* unsuccessful.
*/
int
prom_nbputchar(char c)
{
unsigned long flags;
int i = -1;
local_irq_save(flags);
i = (*(romvec->pv_nbputchar))(c);
local_irq_restore(flags);
return i; /* Ugh, we could spin forever on unsupported proms ;( */
}
/* Blocking version of get character routine above. */
char
prom_getchar(void)
{
int character;
while((character = prom_nbgetchar()) == -1) ;
return (char) character;
}
/* Blocking version of put character routine above. */
void
prom_putchar(char c)
{
while(prom_nbputchar(c) == -1) ;
return;
}
/* Query for input device type */
#if 0
enum prom_input_device
prom_query_input_device()
{
unsigned long flags;
int st_p;
char propb[64];
char *p;
switch(prom_vers) {
case PROM_V0:
case PROM_V2:
default:
switch(*romvec->pv_stdin) {
case PROMDEV_KBD: return PROMDEV_IKBD;
case PROMDEV_TTYA: return PROMDEV_ITTYA;
case PROMDEV_TTYB: return PROMDEV_ITTYB;
default:
return PROMDEV_I_UNK;
};
case PROM_V3:
case PROM_P1275:
local_irq_save(flags);
st_p = (*romvec->pv_v2devops.v2_inst2pkg)(*romvec->pv_v2bootargs.fd_stdin);
__asm__ __volatile__("ld [%0], %%g6\n\t" : :
"r" (¤t_set[smp_processor_id()]) :
"memory");
local_irq_restore(flags);
if(prom_node_has_property(st_p, "keyboard"))
return PROMDEV_IKBD;
prom_getproperty(st_p, "device_type", propb, sizeof(propb));
if(strncmp(propb, "serial", sizeof("serial")))
return PROMDEV_I_UNK;
prom_getproperty(prom_root_node, "stdin-path", propb, sizeof(propb));
p = propb;
while(*p) p++; p -= 2;
if(p[0] == ':') {
if(p[1] == 'a')
return PROMDEV_ITTYA;
else if(p[1] == 'b')
return PROMDEV_ITTYB;
}
return PROMDEV_I_UNK;
};
}
#endif
/* Query for output device type */
#if 0
enum prom_output_device
prom_query_output_device()
{
unsigned long flags;
int st_p;
char propb[64];
char *p;
int propl;
switch(prom_vers) {
case PROM_V0:
switch(*romvec->pv_stdin) {
case PROMDEV_SCREEN: return PROMDEV_OSCREEN;
case PROMDEV_TTYA: return PROMDEV_OTTYA;
case PROMDEV_TTYB: return PROMDEV_OTTYB;
};
break;
case PROM_V2:
case PROM_V3:
case PROM_P1275:
local_irq_save(flags);
st_p = (*romvec->pv_v2devops.v2_inst2pkg)(*romvec->pv_v2bootargs.fd_stdout);
__asm__ __volatile__("ld [%0], %%g6\n\t" : :
"r" (¤t_set[smp_processor_id()]) :
"memory");
local_irq_restore(flags);
propl = prom_getproperty(st_p, "device_type", propb, sizeof(propb));
if (propl >= 0 && propl == sizeof("display") &&
strncmp("display", propb, sizeof("display")) == 0)
{
return PROMDEV_OSCREEN;
}
if(prom_vers == PROM_V3) {
if(strncmp("serial", propb, sizeof("serial")))
return PROMDEV_O_UNK;
prom_getproperty(prom_root_node, "stdout-path", propb, sizeof(propb));
p = propb;
while(*p) p++; p -= 2;
if(p[0]==':') {
if(p[1] == 'a')
return PROMDEV_OTTYA;
else if(p[1] == 'b')
return PROMDEV_OTTYB;
}
return PROMDEV_O_UNK;
} else {
/* This works on SS-2 (an early OpenFirmware) still. */
switch(*romvec->pv_stdin) {
case PROMDEV_TTYA: return PROMDEV_OTTYA;
case PROMDEV_TTYB: return PROMDEV_OTTYB;
};
}
break;
};
return PROMDEV_O_UNK;
}
#endif
| linux-master | arch/m68k/sun3/prom/console.c |
// SPDX-License-Identifier: GPL-2.0
/*
* misc.c: Miscellaneous prom functions that don't belong
* anywhere else.
*
* Copyright (C) 1995 David S. Miller ([email protected])
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <asm/sun3-head.h>
#include <asm/idprom.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#include <asm/movs.h>
/* Reset and reboot the machine with the command 'bcommand'. */
void
prom_reboot(char *bcommand)
{
unsigned long flags;
local_irq_save(flags);
(*(romvec->pv_reboot))(bcommand);
local_irq_restore(flags);
}
/* Drop into the prom, with the chance to continue with the 'go'
* prom command.
*/
void
prom_cmdline(void)
{
}
/* Drop into the prom, but completely terminate the program.
* No chance of continuing.
*/
void
prom_halt(void)
{
unsigned long flags;
again:
local_irq_save(flags);
(*(romvec->pv_halt))();
local_irq_restore(flags);
goto again; /* PROM is out to get me -DaveM */
}
typedef void (*sfunc_t)(void);
/* Get the idprom and stuff it into buffer 'idbuf'. Returns the
* format type. 'num_bytes' is the number of bytes that your idbuf
* has space for. Returns 0xff on error.
*/
unsigned char
prom_get_idprom(char *idbuf, int num_bytes)
{
int i, oldsfc;
GET_SFC(oldsfc);
SET_SFC(FC_CONTROL);
for(i=0;i<num_bytes; i++)
{
/* There is a problem with the GET_CONTROL_BYTE
macro; defining the extra variable
gets around it.
*/
int c;
GET_CONTROL_BYTE(SUN3_IDPROM_BASE + i, c);
idbuf[i] = c;
}
SET_SFC(oldsfc);
return idbuf[0];
}
/* Get the major prom version number. */
int
prom_version(void)
{
return romvec->pv_romvers;
}
/* Get the prom plugin-revision. */
int
prom_getrev(void)
{
return prom_rev;
}
/* Get the prom firmware print revision. */
int
prom_getprev(void)
{
return prom_prev;
}
| linux-master | arch/m68k/sun3/prom/misc.c |
/*
* amcore.c -- Support for Sysam AMCORE open board
*
* (C) Copyright 2016, Angelo Dureghello <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/io.h>
#if IS_ENABLED(CONFIG_DM9000)
#define DM9000_IRQ 25
#define DM9000_ADDR 0x30000000
/*
* DEVICES and related device RESOURCES
*/
static struct resource dm9000_resources[] = {
/* physical address of the address register (CMD [A2] to 0)*/
[0] = {
.start = DM9000_ADDR,
.end = DM9000_ADDR,
.flags = IORESOURCE_MEM,
},
/*
* physical address of the data register (CMD [A2] to 1),
* driver wants a range >=4 to assume a 32bit data bus
*/
[1] = {
.start = DM9000_ADDR + 4,
.end = DM9000_ADDR + 7,
.flags = IORESOURCE_MEM,
},
/* IRQ line the device's interrupt pin is connected to */
[2] = {
.start = DM9000_IRQ,
.end = DM9000_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct dm9000_plat_data dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_platdata,
}
};
#endif
static void __init dm9000_pre_init(void)
{
/* Set the dm9000 interrupt to be auto-vectored */
mcf_autovector(DM9000_IRQ);
}
/*
* Partitioning of parallel NOR flash (39VF3201B)
*/
static struct mtd_partition amcore_partitions[] = {
{
.name = "U-Boot (128K)",
.size = 0x20000,
.offset = 0x0
},
{
.name = "Kernel+ROMfs (2994K)",
.size = 0x2E0000,
.offset = MTDPART_OFS_APPEND
},
{
.name = "Flash Free Space (1024K)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND
}
};
static struct physmap_flash_data flash_data = {
.parts = amcore_partitions,
.nr_parts = ARRAY_SIZE(amcore_partitions),
.width = 2,
};
static struct resource flash_resource = {
.start = 0xffc00000,
.end = 0xffffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct platform_device rtc_device = {
.name = "rtc-ds1307",
.id = -1,
};
static struct i2c_board_info amcore_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("ds1338", 0x68),
},
};
static struct platform_device *amcore_devices[] __initdata = {
#if IS_ENABLED(CONFIG_DM9000)
&dm9000_device,
#endif
&flash_device,
&rtc_device,
};
static int __init init_amcore(void)
{
#if IS_ENABLED(CONFIG_DM9000)
dm9000_pre_init();
#endif
/* Add i2c RTC Dallas chip supprt */
i2c_register_board_info(0, amcore_i2c_info,
ARRAY_SIZE(amcore_i2c_info));
platform_add_devices(amcore_devices, ARRAY_SIZE(amcore_devices));
return 0;
}
arch_initcall(init_amcore);
| linux-master | arch/m68k/coldfire/amcore.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m5407.c -- platform support for ColdFire 5407 based boards
*
* Copyright (C) 1999-2002, Greg Ungerer ([email protected])
* Copyright (C) 2000, Lineo (www.lineo.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m5407_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m5407_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
/* Only support the external interrupts on their primary level */
mcf_mapirq2imr(25, MCFINTC_EINT1);
mcf_mapirq2imr(27, MCFINTC_EINT3);
mcf_mapirq2imr(29, MCFINTC_EINT5);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5407_i2c_init();
clkdev_add_table(m5407_clk_lookup, ARRAY_SIZE(m5407_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m5407.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m5272.c -- platform support for ColdFire 5272 based boards
*
* Copyright (C) 1999-2002, Greg Ungerer ([email protected])
* Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
/*
* Some platforms need software versions of the GPIO data registers.
*/
unsigned short ppdata;
unsigned char ledbank = 0xff;
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m5272_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.2", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.3", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m5272_uarts_init(void)
{
u32 v;
/* Enable the output lines for the serial ports */
v = readl(MCFSIM_PBCNT);
v = (v & ~0x000000ff) | 0x00000055;
writel(v, MCFSIM_PBCNT);
v = readl(MCFSIM_PDCNT);
v = (v & ~0x000003fc) | 0x000002a8;
writel(v, MCFSIM_PDCNT);
}
/***************************************************************************/
static void m5272_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to reset, and enabled */
__raw_writew(0, MCFSIM_WIRR);
__raw_writew(1, MCFSIM_WRRR);
__raw_writew(0, MCFSIM_WCR);
for (;;)
/* wait for watchdog to timeout */;
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
#if defined (CONFIG_MOD5272)
/* Set base of device vectors to be 64 */
writeb(0x40, MCFSIM_PIVR);
#endif
#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
commandp[size-1] = 0;
#elif defined(CONFIG_CANCam)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0010000, size);
commandp[size-1] = 0;
#endif
mach_reset = m5272_cpu_reset;
mach_sched_init = hw_timer_init;
}
/***************************************************************************/
/*
* Some 5272 based boards have the FEC ethernet directly connected to
* an ethernet switch. In this case we need to use the fixed phy type,
* and we need to declare it early in boot.
*/
static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
.link = 1,
.speed = 100,
.duplex = 0,
};
/***************************************************************************/
static int __init init_BSP(void)
{
m5272_uarts_init();
fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup));
return 0;
}
arch_initcall(init_BSP);
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m5272.c |
/*
* intc-simr.c
*
* Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
*
* (C) Copyright 2009-2011, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/traps.h>
/*
* The EDGE Port interrupts are the fixed 7 external interrupts.
* They need some special treatment, for example they need to be acked.
*/
#ifdef CONFIG_M520x
/*
* The 520x parts only support a limited range of these external
* interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67).
*/
#define EINT0 64 /* Is not actually used, but spot reserved for it */
#define EINT1 65 /* EDGE Port interrupt 1 */
#define EINT4 66 /* EDGE Port interrupt 4 */
#define EINT7 67 /* EDGE Port interrupt 7 */
static unsigned int irqebitmap[] = { 0, 1, 4, 7 };
static inline unsigned int irq2ebit(unsigned int irq)
{
return irqebitmap[irq - EINT0];
}
#else
/*
* Most of the ColdFire parts with the EDGE Port module just have
* a strait direct mapping of the 7 external interrupts. Although
* there is a bit reserved for 0, it is not used.
*/
#define EINT0 64 /* Is not actually used, but spot reserved for it */
#define EINT1 65 /* EDGE Port interrupt 1 */
#define EINT7 71 /* EDGE Port interrupt 7 */
static inline unsigned int irq2ebit(unsigned int irq)
{
return irq - EINT0;
}
#endif
/*
* There maybe one, two or three interrupt control units, each has 64
* interrupts. If there is no second or third unit then MCFINTC1_* or
* MCFINTC2_* defines will be 0 (and code for them optimized away).
*/
static void intc_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC2_SIMR && (irq > 127))
__raw_writeb(irq - 128, MCFINTC2_SIMR);
else if (MCFINTC1_SIMR && (irq > 63))
__raw_writeb(irq - 64, MCFINTC1_SIMR);
else
__raw_writeb(irq, MCFINTC0_SIMR);
}
static void intc_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC2_CIMR && (irq > 127))
__raw_writeb(irq - 128, MCFINTC2_CIMR);
else if (MCFINTC1_CIMR && (irq > 63))
__raw_writeb(irq - 64, MCFINTC1_CIMR);
else
__raw_writeb(irq, MCFINTC0_CIMR);
}
static void intc_irq_ack(struct irq_data *d)
{
unsigned int ebit = irq2ebit(d->irq);
__raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
}
static unsigned int intc_irq_startup(struct irq_data *d)
{
unsigned int irq = d->irq;
if ((irq >= EINT1) && (irq <= EINT7)) {
unsigned int ebit = irq2ebit(irq);
u8 v;
#if defined(MCFEPORT_EPDDR)
/* Set EPORT line as input */
v = __raw_readb(MCFEPORT_EPDDR);
__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
#endif
/* Set EPORT line as interrupt source */
v = __raw_readb(MCFEPORT_EPIER);
__raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
}
irq -= MCFINT_VECBASE;
if (MCFINTC2_ICR0 && (irq > 127))
__raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
else if (MCFINTC1_ICR0 && (irq > 63))
__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
else
__raw_writeb(5, MCFINTC0_ICR0 + irq);
intc_irq_unmask(d);
return 0;
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int ebit, irq = d->irq;
u16 pa, tb;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
tb = 0x1;
break;
case IRQ_TYPE_EDGE_FALLING:
tb = 0x2;
break;
case IRQ_TYPE_EDGE_BOTH:
tb = 0x3;
break;
default:
/* Level triggered */
tb = 0;
break;
}
if (tb)
irq_set_handler(irq, handle_edge_irq);
ebit = irq2ebit(irq) * 2;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
__raw_writew(pa, MCFEPORT_EPPAR);
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
};
static struct irq_chip intc_irq_chip_edge_port = {
.name = "CF-INTC-EP",
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_ack = intc_irq_ack,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
{
int irq, eirq;
/* Mask all interrupt sources */
__raw_writeb(0xff, MCFINTC0_SIMR);
if (MCFINTC1_SIMR)
__raw_writeb(0xff, MCFINTC1_SIMR);
if (MCFINTC2_SIMR)
__raw_writeb(0xff, MCFINTC2_SIMR);
eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
(MCFINTC2_ICR0 ? 64 : 0);
for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
if ((irq >= EINT1) && (irq <= EINT7))
irq_set_chip(irq, &intc_irq_chip_edge_port);
else
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
| linux-master | arch/m68k/coldfire/intc-simr.c |
/*
* intc2.c -- support for the 2nd INTC controller of the 525x
*
* (C) Copyright 2012, Steven King <[email protected]>
* (C) Copyright 2009, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
static void intc2_irq_gpio_mask(struct irq_data *d)
{
u32 imr = readl(MCFSIM2_GPIOINTENABLE);
u32 type = irqd_get_trigger_type(d);
int irq = d->irq - MCF_IRQ_GPIO0;
if (type & IRQ_TYPE_EDGE_RISING)
imr &= ~(0x001 << irq);
if (type & IRQ_TYPE_EDGE_FALLING)
imr &= ~(0x100 << irq);
writel(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_unmask(struct irq_data *d)
{
u32 imr = readl(MCFSIM2_GPIOINTENABLE);
u32 type = irqd_get_trigger_type(d);
int irq = d->irq - MCF_IRQ_GPIO0;
if (type & IRQ_TYPE_EDGE_RISING)
imr |= (0x001 << irq);
if (type & IRQ_TYPE_EDGE_FALLING)
imr |= (0x100 << irq);
writel(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_ack(struct irq_data *d)
{
u32 imr = 0;
u32 type = irqd_get_trigger_type(d);
int irq = d->irq - MCF_IRQ_GPIO0;
if (type & IRQ_TYPE_EDGE_RISING)
imr |= (0x001 << irq);
if (type & IRQ_TYPE_EDGE_FALLING)
imr |= (0x100 << irq);
writel(imr, MCFSIM2_GPIOINTCLEAR);
}
static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
{
if (f & ~IRQ_TYPE_EDGE_BOTH)
return -EINVAL;
return 0;
}
static struct irq_chip intc2_irq_gpio_chip = {
.name = "CF-INTC2",
.irq_mask = intc2_irq_gpio_mask,
.irq_unmask = intc2_irq_gpio_unmask,
.irq_ack = intc2_irq_gpio_ack,
.irq_set_type = intc2_irq_gpio_set_type,
};
static int __init mcf_intc2_init(void)
{
int irq;
/* set the interrupt base for the second interrupt controller */
writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
/* GPIO interrupt sources */
for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
irq_set_chip(irq, &intc2_irq_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
}
return 0;
}
arch_initcall(mcf_intc2_init);
| linux-master | arch/m68k/coldfire/intc-525x.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m5249.c -- platform support for ColdFire 5249 based boards
*
* Copyright (C) 2002, Greg Ungerer ([email protected])
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
struct clk_lookup m5249_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
};
/***************************************************************************/
#ifdef CONFIG_M5249C3
static struct resource m5249_smc91x_resources[] = {
{
.start = 0xe0000300,
.end = 0xe0000300 + 0x100,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_GPIO6,
.end = MCF_IRQ_GPIO6,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device m5249_smc91x = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(m5249_smc91x_resources),
.resource = m5249_smc91x_resources,
};
#endif /* CONFIG_M5249C3 */
static struct platform_device *m5249_devices[] __initdata = {
#ifdef CONFIG_M5249C3
&m5249_smc91x,
#endif
};
/***************************************************************************/
static void __init m5249_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
/***************************************************************************/
static void __init m5249_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* CONFIG_I2C_IMX */
}
/***************************************************************************/
#ifdef CONFIG_M5249C3
static void __init m5249_smc91x_init(void)
{
u32 gpio;
/* Set the GPIO line as interrupt source for smc91x device */
gpio = readl(MCFSIM2_GPIOINTENABLE);
writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
gpio = readl(MCFINTC2_INTPRI5);
writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
}
#endif /* CONFIG_M5249C3 */
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
#ifdef CONFIG_M5249C3
m5249_smc91x_init();
#endif
m5249_qspi_init();
m5249_i2c_init();
clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup));
}
/***************************************************************************/
static int __init init_BSP(void)
{
platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
return 0;
}
arch_initcall(init_BSP);
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m5249.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m5307.c -- platform support for ColdFire 5307 based boards
*
* Copyright (C) 1999-2002, Greg Ungerer ([email protected])
* Copyright (C) 2000, Lineo (www.lineo.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfwdebug.h>
#include <asm/mcfclk.h>
/***************************************************************************/
/*
* Some platforms need software versions of the GPIO data registers.
*/
unsigned short ppdata;
unsigned char ledbank = 0xff;
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m5307_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m5307_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel) || \
defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
commandp[size-1] = 0;
#endif
mach_sched_init = hw_timer_init;
/* Only support the external interrupts on their primary level */
mcf_mapirq2imr(25, MCFINTC_EINT1);
mcf_mapirq2imr(27, MCFINTC_EINT3);
mcf_mapirq2imr(29, MCFINTC_EINT5);
mcf_mapirq2imr(31, MCFINTC_EINT7);
#ifdef CONFIG_BDM_DISABLE
/*
* Disable the BDM clocking. This also turns off most of the rest of
* the BDM device. This is good for EMC reasons. This option is not
* incompatible with the memory protection option.
*/
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
m5307_i2c_init();
clkdev_add_table(m5307_clk_lookup, ARRAY_SIZE(m5307_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m5307.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Coldfire generic GPIO support.
*
* (C) Copyright 2009, Steven King <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfgpio.h>
int __mcfgpio_get_value(unsigned gpio)
{
return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
}
EXPORT_SYMBOL(__mcfgpio_get_value);
void __mcfgpio_set_value(unsigned gpio, int value)
{
if (gpio < MCFGPIO_SCR_START) {
unsigned long flags;
MCFGPIO_PORTTYPE data;
local_irq_save(flags);
data = mcfgpio_read(__mcfgpio_podr(gpio));
if (value)
data |= mcfgpio_bit(gpio);
else
data &= ~mcfgpio_bit(gpio);
mcfgpio_write(data, __mcfgpio_podr(gpio));
local_irq_restore(flags);
} else {
if (value)
mcfgpio_write(mcfgpio_bit(gpio),
MCFGPIO_SETR_PORT(gpio));
else
mcfgpio_write(~mcfgpio_bit(gpio),
MCFGPIO_CLRR_PORT(gpio));
}
}
EXPORT_SYMBOL(__mcfgpio_set_value);
int __mcfgpio_direction_input(unsigned gpio)
{
unsigned long flags;
MCFGPIO_PORTTYPE dir;
local_irq_save(flags);
dir = mcfgpio_read(__mcfgpio_pddr(gpio));
dir &= ~mcfgpio_bit(gpio);
mcfgpio_write(dir, __mcfgpio_pddr(gpio));
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL(__mcfgpio_direction_input);
int __mcfgpio_direction_output(unsigned gpio, int value)
{
unsigned long flags;
MCFGPIO_PORTTYPE data;
local_irq_save(flags);
data = mcfgpio_read(__mcfgpio_pddr(gpio));
data |= mcfgpio_bit(gpio);
mcfgpio_write(data, __mcfgpio_pddr(gpio));
/* now set the data to output */
if (gpio < MCFGPIO_SCR_START) {
data = mcfgpio_read(__mcfgpio_podr(gpio));
if (value)
data |= mcfgpio_bit(gpio);
else
data &= ~mcfgpio_bit(gpio);
mcfgpio_write(data, __mcfgpio_podr(gpio));
} else {
if (value)
mcfgpio_write(mcfgpio_bit(gpio),
MCFGPIO_SETR_PORT(gpio));
else
mcfgpio_write(~mcfgpio_bit(gpio),
MCFGPIO_CLRR_PORT(gpio));
}
local_irq_restore(flags);
return 0;
}
EXPORT_SYMBOL(__mcfgpio_direction_output);
int __mcfgpio_request(unsigned gpio)
{
return 0;
}
EXPORT_SYMBOL(__mcfgpio_request);
void __mcfgpio_free(unsigned gpio)
{
__mcfgpio_direction_input(gpio);
}
EXPORT_SYMBOL(__mcfgpio_free);
#ifdef CONFIG_GPIOLIB
static int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return __mcfgpio_direction_input(offset);
}
static int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset)
{
return !!__mcfgpio_get_value(offset);
}
static int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
return __mcfgpio_direction_output(offset, value);
}
static void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset,
int value)
{
__mcfgpio_set_value(offset, value);
}
static int mcfgpio_request(struct gpio_chip *chip, unsigned offset)
{
return __mcfgpio_request(offset);
}
static void mcfgpio_free(struct gpio_chip *chip, unsigned offset)
{
__mcfgpio_free(offset);
}
static int mcfgpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
#if defined(MCFGPIO_IRQ_MIN)
if ((offset >= MCFGPIO_IRQ_MIN) && (offset < MCFGPIO_IRQ_MAX))
#else
if (offset < MCFGPIO_IRQ_MAX)
#endif
return MCFGPIO_IRQ_VECBASE + offset;
else
return -EINVAL;
}
static struct gpio_chip mcfgpio_chip = {
.label = "mcfgpio",
.request = mcfgpio_request,
.free = mcfgpio_free,
.direction_input = mcfgpio_direction_input,
.direction_output = mcfgpio_direction_output,
.get = mcfgpio_get_value,
.set = mcfgpio_set_value,
.to_irq = mcfgpio_to_irq,
.base = 0,
.ngpio = MCFGPIO_PIN_MAX,
};
static int __init mcfgpio_sysinit(void)
{
return gpiochip_add_data(&mcfgpio_chip, NULL);
}
core_initcall(mcfgpio_sysinit);
#endif
| linux-master | arch/m68k/coldfire/gpio.c |
/*
* pci.c -- PCI bus support for ColdFire processors
*
* (C) Copyright 2012, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/m54xxpci.h>
/*
* Memory and IO mappings. We use a 1:1 mapping for local host memory to
* PCI bus memory (no reason not to really). IO space is mapped in its own
* separate address region. The device configuration space is mapped over
* the IO map space when we enable it in the PCICAR register.
*/
static struct pci_bus *rootbus;
static unsigned long iospace;
/*
* We need to be careful probing on bus 0 (directly connected to host
* bridge). We should only access the well defined possible devices in
* use, ignore aliases and the like.
*/
static unsigned char mcf_host_slot2sid[32] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 2, 0, 3, 4, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
};
static unsigned char mcf_host_irq[] = {
0, 69, 69, 71, 71,
};
/*
* Configuration space access functions. Configuration space access is
* through the IO mapping window, enabling it via the PCICAR register.
*/
static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
{
return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
}
static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
{
unsigned long addr;
*value = 0xffffffff;
if (bus->number == 0) {
if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
return PCIBIOS_SUCCESSFUL;
}
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
case 1:
*value = __raw_readb(addr);
break;
case 2:
*value = le16_to_cpu(__raw_readw(addr));
break;
default:
*value = le32_to_cpu(__raw_readl(addr));
break;
}
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 value)
{
unsigned long addr;
if (bus->number == 0) {
if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
return PCIBIOS_SUCCESSFUL;
}
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
case 1:
__raw_writeb(value, addr);
break;
case 2:
__raw_writew(cpu_to_le16(value), addr);
break;
default:
__raw_writel(cpu_to_le32(value), addr);
break;
}
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops mcf_pci_ops = {
.read = mcf_pci_readconfig,
.write = mcf_pci_writeconfig,
};
/*
* Initialize the PCI bus registers, and scan the bus.
*/
static struct resource mcf_pci_mem = {
.name = "PCI Memory space",
.start = PCI_MEM_PA,
.end = PCI_MEM_PA + PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct resource mcf_pci_io = {
.name = "PCI IO space",
.start = 0x400,
.end = 0x10000 - 1,
.flags = IORESOURCE_IO,
};
static struct resource busn_resource = {
.name = "PCI busn",
.start = 0,
.end = 255,
.flags = IORESOURCE_BUS,
};
/*
* Interrupt mapping and setting.
*/
static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int sid;
sid = mcf_host_slot2sid[slot];
if (sid)
return mcf_host_irq[sid];
return 0;
}
static int __init mcf_pci_init(void)
{
struct pci_host_bridge *bridge;
int ret;
bridge = pci_alloc_host_bridge(0);
if (!bridge)
return -ENOMEM;
pr_info("ColdFire: PCI bus initialization...\n");
/* Reset the external PCI bus */
__raw_writel(PCIGSCR_RESET, PCIGSCR);
__raw_writel(0, PCITCR);
request_resource(&iomem_resource, &mcf_pci_mem);
request_resource(&iomem_resource, &mcf_pci_io);
/* Configure PCI arbiter */
__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
PACR_EXTMINTE(0x1f), PACR);
/* Set required multi-function pins for PCI bus use */
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
/* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_INVALIDATE, PCISCR);
__raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
__raw_writel(0, PCICR2);
/*
* Set up the initiator windows for memory and IO mapping.
* These give the CPU bus access onto the PCI bus. One for each of
* PCI memory and IO address spaces.
*/
__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
PCIIW0BTAR);
__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
PCIIW1BTAR);
__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
/*
* Set up the target windows for access from the PCI bus back to the
* CPU bus. All we need is access to system RAM (for mastering).
*/
__raw_writel(CONFIG_RAMBASE, PCIBAR1);
__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
/* Keep a virtual mapping to IO/config space active */
iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
if (iospace == 0) {
pci_free_host_bridge(bridge);
return -ENODEV;
}
pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
(u32) iospace);
/* Turn of PCI reset, and wait for devices to settle */
__raw_writel(0, PCIGSCR);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(200));
pci_add_resource(&bridge->windows, &ioport_resource);
pci_add_resource(&bridge->windows, &iomem_resource);
pci_add_resource(&bridge->windows, &busn_resource);
bridge->dev.parent = NULL;
bridge->sysdata = NULL;
bridge->busnr = 0;
bridge->ops = &mcf_pci_ops;
bridge->swizzle_irq = pci_common_swizzle;
bridge->map_irq = mcf_pci_map_irq;
ret = pci_scan_root_bus_bridge(bridge);
if (ret) {
pci_free_host_bridge(bridge);
return ret;
}
rootbus = bridge->bus;
rootbus->resource[0] = &mcf_pci_io;
rootbus->resource[1] = &mcf_pci_mem;
pci_bus_size_bridges(rootbus);
pci_bus_assign_resources(rootbus);
pci_bus_add_devices(rootbus);
return 0;
}
subsys_initcall(mcf_pci_init);
| linux-master | arch/m68k/coldfire/pci.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* 525x.c -- platform support for ColdFire 525x based boards
*
* Copyright (C) 2012, Steven King <[email protected]>
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m525x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m525x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* set the GPIO function for the qspi cs gpios */
/* FIXME: replace with pinmux/pinctl support */
u32 f = readl(MCFSIM2_GPIOFUNC);
f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
writel(f, MCFSIM2_GPIOFUNC);
/* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
static void __init m525x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
m525x_qspi_init();
m525x_i2c_init();
clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m525x.c |
/*
* intc2.c -- support for the 2nd INTC controller of the 5249
*
* (C) Copyright 2009, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
static void intc2_irq_gpio_mask(struct irq_data *d)
{
u32 imr;
imr = readl(MCFSIM2_GPIOINTENABLE);
imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
writel(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_unmask(struct irq_data *d)
{
u32 imr;
imr = readl(MCFSIM2_GPIOINTENABLE);
imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
writel(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_ack(struct irq_data *d)
{
writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
}
static struct irq_chip intc2_irq_gpio_chip = {
.name = "CF-INTC2",
.irq_mask = intc2_irq_gpio_mask,
.irq_unmask = intc2_irq_gpio_unmask,
.irq_ack = intc2_irq_gpio_ack,
};
static int __init mcf_intc2_init(void)
{
int irq;
/* GPIO interrupt sources */
for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
irq_set_chip(irq, &intc2_irq_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
}
return 0;
}
arch_initcall(mcf_intc2_init);
| linux-master | arch/m68k/coldfire/intc-5249.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* sltimers.c -- generic ColdFire slice timer support.
*
* Copyright (C) 2009-2010, Philippe De Muyter <[email protected]>
* based on
* timers.c -- generic ColdFire hardware timer support.
* Copyright (C) 1999-2008, Greg Ungerer <[email protected]>
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/profile.h>
#include <linux/clocksource.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfslt.h>
#include <asm/mcfsim.h>
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/*
* By default use Slice Timer 1 as the profiler clock timer.
*/
#define PA(a) (MCFSLT_TIMER1 + (a))
/*
* Choose a reasonably fast profile timer. Make it an odd value to
* try and get good coverage of kernel operations.
*/
#define PROFILEHZ 1013
irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
{
/* Reset Slice Timer 1 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
if (current->pid)
profile_tick(CPU_PROFILING);
return IRQ_HANDLED;
}
void mcfslt_profile_init(void)
{
int ret;
printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
PROFILEHZ);
ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER,
"profile timer", NULL);
if (ret) {
pr_err("Failed to request irq %d (profile timer): %pe\n",
MCF_IRQ_PROFILER, ERR_PTR(ret));
}
/* Set up TIMER 2 as high speed profile clock */
__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
PA(MCFSLT_SCR));
}
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
/*
* By default use Slice Timer 0 as the system clock timer.
*/
#define TA(a) (MCFSLT_TIMER0 + (a))
static u32 mcfslt_cycles_per_jiffy;
static u32 mcfslt_cnt;
static irqreturn_t mcfslt_tick(int irq, void *dummy)
{
/* Reset Slice Timer 0 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
mcfslt_cnt += mcfslt_cycles_per_jiffy;
legacy_timer_tick(1);
return IRQ_HANDLED;
}
static u64 mcfslt_read_clk(struct clocksource *cs)
{
unsigned long flags;
u32 cycles, scnt;
local_irq_save(flags);
scnt = __raw_readl(TA(MCFSLT_SCNT));
cycles = mcfslt_cnt;
if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
cycles += mcfslt_cycles_per_jiffy;
scnt = __raw_readl(TA(MCFSLT_SCNT));
}
local_irq_restore(flags);
/* subtract because slice timers count down */
return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt);
}
static struct clocksource mcfslt_clk = {
.name = "slt",
.rating = 250,
.read = mcfslt_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
void hw_timer_init(void)
{
int r;
mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
/*
* The coldfire slice timer (SLT) runs from STCNT to 0 included,
* then STCNT again and so on. It counts thus actually
* STCNT + 1 steps for 1 tick, not STCNT. So if you want
* n cycles, initialize STCNT with n - 1.
*/
__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
TA(MCFSLT_SCR));
/* initialize mcfslt_cnt knowing that slice timers count down */
mcfslt_cnt = mcfslt_cycles_per_jiffy;
r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL);
if (r) {
pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
ERR_PTR(r));
}
clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
#ifdef CONFIG_HIGHPROFILE
mcfslt_profile_init();
#endif
}
| linux-master | arch/m68k/coldfire/sltimers.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m520x.c -- platform support for ColdFire 520x based boards
*
* Copyright (C) 2005, Freescale (www.freescale.com)
* Copyright (C) 2005, Intec Automation ([email protected])
* Copyright (C) 1999-2007, Greg Ungerer ([email protected])
* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
static struct clk_lookup m520x_clk_lookup[] = {
CLKDEV_INIT(NULL, "flexbus", &__clk_0_2),
CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_34),
CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_35),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_36),
CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
CLKDEV_INIT("sdram.0", NULL, &__clk_0_42),
};
static struct clk * const enable_clks[] __initconst = {
&__clk_0_2, /* flexbus */
&__clk_0_18, /* intc.0 */
&__clk_0_21, /* iack.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_34, /* mcfeport.0 */
&__clk_0_36, /* pll.0 */
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* sdram.0 */
};
static struct clk * const disable_clks[] __initconst = {
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_35, /* mcfwdt.0 */
};
static void __init m520x_clk_init(void)
{
unsigned i;
/* make sure these clocks are enabled */
for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
__clk_init_enabled(enable_clks[i]);
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m520x_clk_lookup, ARRAY_SIZE(m520x_clk_lookup));
}
/***************************************************************************/
static void __init m520x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
u16 par;
/* setup Port QS for QSPI with gpio CS control */
writeb(0x3f, MCF_GPIO_PAR_QSPI);
/* make U1CTS and U2RTS gpio for cs_control */
par = readw(MCF_GPIO_PAR_UART);
par &= 0x00ff;
writew(par, MCF_GPIO_PAR_UART);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
/***************************************************************************/
static void __init m520x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u8 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCF_GPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCF_GPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m520x_uarts_init(void)
{
u16 par;
u8 par2;
/* UART0 and UART1 GPIO pin setup */
par = readw(MCF_GPIO_PAR_UART);
par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
writew(par, MCF_GPIO_PAR_UART);
/* UART1 GPIO pin setup */
par2 = readb(MCF_GPIO_PAR_FECI2C);
par2 &= ~0x0F;
par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
writeb(par2, MCF_GPIO_PAR_FECI2C);
}
/***************************************************************************/
static void __init m520x_fec_init(void)
{
u8 v;
/* Set multi-function pins to ethernet mode */
v = readb(MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
v = readb(MCF_GPIO_PAR_FECI2C);
writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
m520x_clk_init();
m520x_uarts_init();
m520x_fec_init();
m520x_qspi_init();
m520x_i2c_init();
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m520x.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* nettel.c -- startup code support for the NETtel boards
*
* Copyright (C) 2009, Greg Ungerer ([email protected])
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/nettel.h>
/***************************************************************************/
/*
* Define the IO and interrupt resources of the 2 SMC9196 interfaces.
*/
#define NETTEL_SMC0_ADDR 0x30600300
#define NETTEL_SMC0_IRQ 29
#define NETTEL_SMC1_ADDR 0x30600000
#define NETTEL_SMC1_IRQ 27
/*
* We need some access into the SMC9196 registers. Define those registers
* we will need here (including the smc91x.h doesn't seem to give us these
* in a simple form).
*/
#define SMC91xx_BANKSELECT 14
#define SMC91xx_BASEADDR 2
#define SMC91xx_BASEMAC 4
/***************************************************************************/
static struct resource nettel_smc91x_0_resources[] = {
{
.start = NETTEL_SMC0_ADDR,
.end = NETTEL_SMC0_ADDR + 0x20,
.flags = IORESOURCE_MEM,
},
{
.start = NETTEL_SMC0_IRQ,
.end = NETTEL_SMC0_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource nettel_smc91x_1_resources[] = {
{
.start = NETTEL_SMC1_ADDR,
.end = NETTEL_SMC1_ADDR + 0x20,
.flags = IORESOURCE_MEM,
},
{
.start = NETTEL_SMC1_IRQ,
.end = NETTEL_SMC1_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device nettel_smc91x[] = {
{
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(nettel_smc91x_0_resources),
.resource = nettel_smc91x_0_resources,
},
{
.name = "smc91x",
.id = 1,
.num_resources = ARRAY_SIZE(nettel_smc91x_1_resources),
.resource = nettel_smc91x_1_resources,
},
};
static struct platform_device *nettel_devices[] __initdata = {
&nettel_smc91x[0],
&nettel_smc91x[1],
};
/***************************************************************************/
static u8 nettel_macdefault[] __initdata = {
0x00, 0xd0, 0xcf, 0x00, 0x00, 0x01,
};
/*
* Set flash contained MAC address into SMC9196 core. Make sure the flash
* MAC address is sane, and not an empty flash. If no good use the Moreton
* Bay default MAC address instead.
*/
static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr)
{
u16 *macp;
macp = (u16 *) flashaddr;
if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
macp = (u16 *) &nettel_macdefault[0];
writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
writew(macp[0], ioaddr + SMC91xx_BASEMAC);
writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
}
/***************************************************************************/
/*
* Re-map the address space of at least one of the SMC ethernet
* parts. Both parts power up decoding the same address, so we
* need to move one of them first, before doing anything else.
*/
static void __init nettel_smc91x_init(void)
{
writew(0x00ec, MCFSIM_PADDR);
mcf_setppdata(0, 0x0080);
writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
mcf_setppdata(0x0080, 0);
/* Set correct chip select timing for SMC9196 accesses */
writew(0x1180, MCFSIM_CSCR3);
/* Set the SMC interrupts to be auto-vectored */
mcf_autovector(NETTEL_SMC0_IRQ);
mcf_autovector(NETTEL_SMC1_IRQ);
/* Set MAC addresses from flash for both interfaces */
nettel_smc91x_setmac(NETTEL_SMC0_ADDR, 0xf0006000);
nettel_smc91x_setmac(NETTEL_SMC1_ADDR, 0xf0006006);
}
/***************************************************************************/
static int __init init_nettel(void)
{
nettel_smc91x_init();
platform_add_devices(nettel_devices, ARRAY_SIZE(nettel_devices));
return 0;
}
arch_initcall(init_nettel);
/***************************************************************************/
| linux-master | arch/m68k/coldfire/nettel.c |
/*
* reset.c -- common ColdFire SoC reset support
*
* (C) Copyright 2012, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/*
* There are 2 common methods amongst the ColdFure parts for reseting
* the CPU. But there are couple of exceptions, the 5272 and the 547x
* have something completely special to them, and we let their specific
* subarch code handle them.
*/
#ifdef MCFSIM_SYPCR
static void mcf_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to soft reset, and enabled */
__raw_writeb(0xc0, MCFSIM_SYPCR);
for (;;)
/* wait for watchdog to timeout */;
}
#endif
#ifdef MCF_RCR
static void mcf_cpu_reset(void)
{
local_irq_disable();
__raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
}
#endif
static int __init mcf_setup_reset(void)
{
mach_reset = mcf_cpu_reset;
return 0;
}
arch_initcall(mcf_setup_reset);
| linux-master | arch/m68k/coldfire/reset.c |
/*
* intc.c -- interrupt controller or ColdFire 5272 SoC
*
* (C) Copyright 2009, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/traps.h>
/*
* The 5272 ColdFire interrupt controller is nothing like any other
* ColdFire interrupt controller - it truly is completely different.
* Given its age it is unlikely to be used on any other ColdFire CPU.
*/
/*
* The masking and priproty setting of interrupts on the 5272 is done
* via a set of 4 "Interrupt Controller Registers" (ICR). There is a
* loose mapping of vector number to register and internal bits, but
* a table is the easiest and quickest way to map them.
*
* Note that the external interrupts are edge triggered (unlike the
* internal interrupt sources which are level triggered). Which means
* they also need acknowledging via acknowledge bits.
*/
struct irqmap {
unsigned int icr;
unsigned char index;
unsigned char ack;
};
static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
/*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
/*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
/*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
/*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
/*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
/*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
/*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
/*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
/*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
/*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
/*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
/*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
/*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
/*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
/*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
/*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
/*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
/*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
/*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
/*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
/*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
/*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
/*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
/*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
/*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
/*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
/*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
/*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
/*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
};
/*
* The act of masking the interrupt also has a side effect of 'ack'ing
* an interrupt on this irq (for the external irqs). So this mask function
* is also an ack_mask function.
*/
static void intc_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
u32 v;
irq -= MCFINT_VECBASE;
v = 0x8 << intc_irqmap[irq].index;
writel(v, intc_irqmap[irq].icr);
}
}
static void intc_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
u32 v;
irq -= MCFINT_VECBASE;
v = 0xd << intc_irqmap[irq].index;
writel(v, intc_irqmap[irq].icr);
}
}
static void intc_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
/* Only external interrupts are acked */
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(intc_irqmap[irq].icr);
v &= (0x7 << intc_irqmap[irq].index);
v |= (0x8 << intc_irqmap[irq].index);
writel(v, intc_irqmap[irq].icr);
}
}
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int irq = d->irq;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(MCFSIM_PITR);
if (type == IRQ_TYPE_EDGE_FALLING)
v &= ~(0x1 << (32 - irq));
else
v |= (0x1 << (32 - irq));
writel(v, MCFSIM_PITR);
}
}
return 0;
}
/*
* Simple flow handler to deal with the external edge triggered interrupts.
* We need to be careful with the masking/acking due to the side effects
* of masking an interrupt.
*/
static void intc_external_irq(struct irq_desc *desc)
{
irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
handle_simple_irq(desc);
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_mask_ack = intc_irq_mask,
.irq_ack = intc_irq_ack,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
{
int irq, edge;
/* Mask all interrupt sources */
writel(0x88888888, MCFSIM_ICR1);
writel(0x88888888, MCFSIM_ICR2);
writel(0x88888888, MCFSIM_ICR3);
writel(0x88888888, MCFSIM_ICR4);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip);
edge = 0;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
if (edge) {
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
irq_set_handler(irq, intc_external_irq);
} else {
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
}
| linux-master | arch/m68k/coldfire/intc-5272.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m527x.c -- platform support for ColdFire 527x based boards
*
* Sub-architcture dependent initialization code for the Freescale
* 5270/5271 and 5274/5275 CPUs.
*
* Copyright (C) 1999-2004, Greg Ungerer ([email protected])
* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m527x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("fec.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m527x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
#if defined(CONFIG_M5271)
u16 par;
/* setup QSPS pins for QSPI with gpio CS control */
writeb(0x1f, MCFGPIO_PAR_QSPI);
/* and CS2 & CS3 as gpio */
par = readw(MCFGPIO_PAR_TIMER);
par &= 0x3f3f;
writew(par, MCFGPIO_PAR_TIMER);
#elif defined(CONFIG_M5275)
/* setup QSPS pins for QSPI with gpio CS control */
writew(0x003e, MCFGPIO_PAR_QSPI);
#endif
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
/***************************************************************************/
static void __init m527x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
#if defined(CONFIG_M5271)
u8 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
#elif defined(CONFIG_M5275)
u16 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readw(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writew(par, MCFGPIO_PAR_FECI2C);
#endif
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m527x_uarts_init(void)
{
u16 sepmask;
/*
* External Pin Mask Setting & Enable External Pin for Interface
*/
sepmask = readw(MCFGPIO_PAR_UART);
sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
writew(sepmask, MCFGPIO_PAR_UART);
}
/***************************************************************************/
static void __init m527x_fec_init(void)
{
u8 v;
/* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271)
v = readb(MCFGPIO_PAR_FECI2C);
writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
#else
u16 par;
par = readw(MCFGPIO_PAR_FECI2C);
writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC0HL);
writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
/* Set multi-function pins to ethernet mode for fec1 */
par = readw(MCFGPIO_PAR_FECI2C);
writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC1HL);
writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
#endif
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
m527x_uarts_init();
m527x_fec_init();
m527x_qspi_init();
m527x_i2c_init();
clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m527x.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************/
/*
* m53xx.c -- platform support for ColdFire 53xx based boards
*
* Copyright (C) 1999-2002, Greg Ungerer ([email protected])
* Copyright (C) 2000, Lineo (www.lineo.com)
* Yaroslav Vinogradov [email protected]
* Copyright Freescale Semiconductor, Inc 2006
* Copyright (c) 2006, emlix, Sebastian Hess <[email protected]>
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfdma.h>
#include <asm/mcfwdebug.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
static struct clk_lookup m53xx_clk_lookup[] = {
CLKDEV_INIT("flexbus", NULL, &__clk_0_2),
CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("intc.1", NULL, &__clk_0_19),
CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfpwm.0", NULL, &__clk_0_36),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_38),
CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcflcd.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
CLKDEV_INIT("sdram.0", NULL, &__clk_0_46),
CLKDEV_INIT("ssi.0", NULL, &__clk_0_47),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
CLKDEV_INIT("mdha.0", NULL, &__clk_1_32),
CLKDEV_INIT("skha.0", NULL, &__clk_1_33),
CLKDEV_INIT("rng.0", NULL, &__clk_1_34),
};
static struct clk * const enable_clks[] __initconst = {
&__clk_0_2, /* flexbus */
&__clk_0_18, /* intc.0 */
&__clk_0_19, /* intc.1 */
&__clk_0_21, /* iack.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_37, /* mcfeport.0 */
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_46, /* sdram.0 */
&__clk_0_48, /* pll.0 */
};
static struct clk * const disable_clks[] __initconst = {
&__clk_0_8, /* mcfcan.0 */
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_34, /* mcfpit.2 */
&__clk_0_35, /* mcfpit.3 */
&__clk_0_36, /* mcfpwm.0 */
&__clk_0_38, /* mcfwdt.0 */
&__clk_0_42, /* mcfrtc.0 */
&__clk_0_43, /* mcflcd.0 */
&__clk_0_44, /* mcfusb-otg.0 */
&__clk_0_45, /* mcfusb-host.0 */
&__clk_0_47, /* ssi.0 */
&__clk_1_32, /* mdha.0 */
&__clk_1_33, /* skha.0 */
&__clk_1_34, /* rng.0 */
};
static void __init m53xx_clk_init(void)
{
unsigned i;
/* make sure these clocks are enabled */
for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
__clk_init_enabled(enable_clks[i]);
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m53xx_clk_lookup, ARRAY_SIZE(m53xx_clk_lookup));
}
/***************************************************************************/
static void __init m53xx_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* setup QSPS pins for QSPI with gpio CS control */
writew(0x01f0, MCFGPIO_PAR_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
/***************************************************************************/
static void __init m53xx_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
u8 r = readb(MCFGPIO_PAR_FECI2C);
r |= 0x0f;
writeb(r, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m53xx_uarts_init(void)
{
/* UART GPIO initialization */
writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
}
/***************************************************************************/
static void __init m53xx_fec_init(void)
{
u8 v;
/* Set multi-function pins to ethernet mode for fec0 */
v = readb(MCFGPIO_PAR_FECI2C);
v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
writeb(v, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC);
v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
writeb(v, MCFGPIO_PAR_FEC);
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
#if !defined(CONFIG_BOOTPARAM)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0x4000, 4);
if(strncmp(commandp, "kcl ", 4) == 0){
memcpy(commandp, (char *) 0x4004, size);
commandp[size-1] = 0;
} else {
memset(commandp, 0, size);
}
#endif
mach_sched_init = hw_timer_init;
m53xx_clk_init();
m53xx_uarts_init();
m53xx_fec_init();
m53xx_qspi_init();
m53xx_i2c_init();
#ifdef CONFIG_BDM_DISABLE
/*
* Disable the BDM clocking. This also turns off most of the rest of
* the BDM device. This is good for EMC reasons. This option is not
* incompatible with the memory protection option.
*/
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
}
/***************************************************************************/
/* Board initialization */
/***************************************************************************/
/*
* PLL min/max specifications
*/
#define MAX_FVCO 500000 /* KHz */
#define MAX_FSYS 80000 /* KHz */
#define MIN_FSYS 58333 /* KHz */
#define FREF 16000 /* KHz */
#define MAX_MFD 135 /* Multiplier */
#define MIN_MFD 88 /* Multiplier */
#define BUSDIV 6 /* Divider */
/*
* Low Power Divider specifications
*/
#define MIN_LPD (1 << 0) /* Divider (not encoded) */
#define MAX_LPD (1 << 15) /* Divider (not encoded) */
#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
#define SYS_CLK_KHZ 80000
#define SYSTEM_PERIOD 12.5
/*
* SDRAM Timing Parameters
*/
#define SDRAM_BL 8 /* # of beats in a burst */
#define SDRAM_TWR 2 /* in clocks */
#define SDRAM_CASL 2.5 /* CASL in clocks */
#define SDRAM_TRCD 2 /* in clocks */
#define SDRAM_TRP 2 /* in clocks */
#define SDRAM_TRFC 7 /* in clocks */
#define SDRAM_TREFI 7800 /* in ns */
#define EXT_SRAM_ADDRESS (0xC0000000)
#define FLASH_ADDRESS (0x00000000)
#define SDRAM_ADDRESS (0x40000000)
#define NAND_FLASH_ADDRESS (0xD0000000)
void wtm_init(void);
void scm_init(void);
void gpio_init(void);
void fbcs_init(void);
void sdramc_init(void);
int clock_pll (int fsys, int flags);
int clock_limp (int);
int clock_exit_limp (void);
int get_sys_clock (void);
asmlinkage void __init sysinit(void)
{
clock_pll(0, 0);
wtm_init();
scm_init();
gpio_init();
fbcs_init();
sdramc_init();
}
void wtm_init(void)
{
/* Disable watchdog timer */
writew(0, MCF_WTM_WCR);
}
#define MCF_SCM_BCR_GBW (0x00000100)
#define MCF_SCM_BCR_GBR (0x00000200)
void scm_init(void)
{
/* All masters are trusted */
writel(0x77777777, MCF_SCM_MPR);
/* Allow supervisor/user, read/write, and trusted/untrusted
access to all slaves */
writel(0, MCF_SCM_PACRA);
writel(0, MCF_SCM_PACRB);
writel(0, MCF_SCM_PACRC);
writel(0, MCF_SCM_PACRD);
writel(0, MCF_SCM_PACRE);
writel(0, MCF_SCM_PACRF);
/* Enable bursts */
writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
}
void fbcs_init(void)
{
writeb(0x3E, MCFGPIO_PAR_CS);
/* Latch chip select */
writel(0x10080000, MCF_FBCS1_CSAR);
writel(0x002A3780, MCF_FBCS1_CSCR);
writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Initialize latch to drive signals to inactive states */
writew(0xffff, 0x10080000);
/* External SRAM */
writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
writel(MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_SBM |
MCF_FBCS_CSCR_WS(1),
MCF_FBCS1_CSCR);
writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Boot Flash connected to FBCS0 */
writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
writel(MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_BEM |
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_SBM |
MCF_FBCS_CSCR_WS(7),
MCF_FBCS0_CSCR);
writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
}
void sdramc_init(void)
{
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
/* SDRAM chip select initialization */
/* Initialize SDRAM chip select */
writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
MCF_SDRAMC_SDCS0);
/*
* Basic configuration and initialization
*/
writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
MCF_SDRAMC_SDCFG1_WTLAT(3),
MCF_SDRAMC_SDCFG1);
writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
MCF_SDRAMC_SDCFG2);
/*
* Precharge and enable write to SDMR
*/
writel(MCF_SDRAMC_SDCR_MODE_EN |
MCF_SDRAMC_SDCR_CKE |
MCF_SDRAMC_SDCR_DDR |
MCF_SDRAMC_SDCR_MUX(1) |
MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
MCF_SDRAMC_SDCR_PS_16 |
MCF_SDRAMC_SDCR_IPALL,
MCF_SDRAMC_SDCR);
/*
* Write extended mode register
*/
writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD,
MCF_SDRAMC_SDMR);
/*
* Write mode register and reset DLL
*/
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
MCF_SDRAMC_SDMR_AD(0x163) |
MCF_SDRAMC_SDMR_CMD,
MCF_SDRAMC_SDMR);
/*
* Execute a PALL command
*/
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
/*
* Perform two REF cycles
*/
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
/*
* Write mode register and clear reset DLL
*/
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
MCF_SDRAMC_SDMR_AD(0x063) |
MCF_SDRAMC_SDMR_CMD,
MCF_SDRAMC_SDMR);
/*
* Enable auto refresh and lock SDMR
*/
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
MCF_SDRAMC_SDCR);
writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
MCF_SDRAMC_SDCR);
}
}
void gpio_init(void)
{
/* Enable UART0 pins */
writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
MCFGPIO_PAR_UART);
/*
* Initialize TIN3 as a GPIO output to enable the write
* half of the latch.
*/
writeb(0x00, MCFGPIO_PAR_TIMER);
writeb(0x08, MCFGPIO_PDDR_TIMER);
writeb(0x00, MCFGPIO_PCLRR_TIMER);
}
int clock_pll(int fsys, int flags)
{
int fref, temp, fout, mfd;
u32 i;
fref = FREF;
if (fsys == 0) {
/* Return current PLL output */
mfd = readb(MCF_PLL_PFDR);
return (fref * mfd / (BUSDIV * 4));
}
/* Check bounds of requested system clock */
if (fsys > MAX_FSYS)
fsys = MAX_FSYS;
if (fsys < MIN_FSYS)
fsys = MIN_FSYS;
/* Multiplying by 100 when calculating the temp value,
and then dividing by 100 to calculate the mfd allows
for exact values without needing to include floating
point libraries. */
temp = 100 * fsys / fref;
mfd = 4 * BUSDIV * temp / 100;
/* Determine the output frequency for selected values */
fout = (fref * mfd / (BUSDIV * 4));
/*
* Check to see if the SDRAM has already been initialized.
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
/* Put SDRAM into self refresh mode */
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/*
* Initialize the PLL to generate the new system clock frequency.
* The device must be put into LIMP mode to reprogram the PLL.
*/
/* Enter LIMP mode */
clock_limp(DEFAULT_LPD);
/* Reprogram PLL for desired fsys */
writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
MCF_PLL_PODR);
writeb(mfd, MCF_PLL_PFDR);
/* Exit LIMP mode */
clock_exit_limp();
/*
* Return the SDRAM to normal operation if it is in use.
*/
if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
/* Exit self refresh mode */
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/* Errata - workaround for SDRAM operation after exiting LIMP mode */
writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
/* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++)
;
return fout;
}
int clock_limp(int div)
{
u32 temp;
/* Check bounds of divider */
if (div < MIN_LPD)
div = MIN_LPD;
if (div > MAX_LPD)
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't
overwrite the value*/
temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
/* Apply the divider to the system clock */
writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
return (FREF/(3*(1 << div)));
}
int clock_exit_limp(void)
{
int fout;
/* Exit LIMP mode */
writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
/* Wait for PLL to lock */
while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
;
fout = get_sys_clock();
return fout;
}
int get_sys_clock(void)
{
int divider;
/* Test to see if device is in LIMP mode */
if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
return (FREF/(2 << divider));
}
else
return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
}
| linux-master | arch/m68k/coldfire/m53xx.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* clk.c -- general ColdFire CPU kernel clk handling
*
* Copyright (C) 2009, Greg Ungerer ([email protected])
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
static DEFINE_SPINLOCK(clk_lock);
#ifdef MCFPM_PPMCR0
/*
* For more advanced ColdFire parts that have clocks that can be enabled
* we supply enable/disable functions. These must properly define their
* clocks in their platform specific code.
*/
void __clk_init_enabled(struct clk *clk)
{
clk->enabled = 1;
clk->clk_ops->enable(clk);
}
void __clk_init_disabled(struct clk *clk)
{
clk->enabled = 0;
clk->clk_ops->disable(clk);
}
static void __clk_enable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR0);
}
static void __clk_disable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR0);
}
struct clk_ops clk_ops0 = {
.enable = __clk_enable0,
.disable = __clk_disable0,
};
#ifdef MCFPM_PPMCR1
static void __clk_enable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR1);
}
static void __clk_disable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR1);
}
struct clk_ops clk_ops1 = {
.enable = __clk_enable1,
.disable = __clk_disable1,
};
#endif /* MCFPM_PPMCR1 */
#endif /* MCFPM_PPMCR0 */
int clk_enable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return 0;
spin_lock_irqsave(&clk_lock, flags);
if ((clk->enabled++ == 0) && clk->clk_ops)
clk->clk_ops->enable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
unsigned long flags;
if (!clk)
return;
spin_lock_irqsave(&clk_lock, flags);
if ((--clk->enabled == 0) && clk->clk_ops)
clk->clk_ops->disable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
/* dummy functions, should not be called */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);
/***************************************************************************/
| linux-master | arch/m68k/coldfire/clk.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m523x.c -- platform support for ColdFire 523x based boards
*
* Sub-architcture dependent initialization code for the Freescale
* 523x CPUs.
*
* Copyright (C) 1999-2005, Greg Ungerer ([email protected])
* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m523x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m523x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
u16 par;
/* setup QSPS pins for QSPI with gpio CS control */
writeb(0x1f, MCFGPIO_PAR_QSPI);
/* and CS2 & CS3 as gpio */
par = readw(MCFGPIO_PAR_TIMER);
par &= 0x3f3f;
writew(par, MCFGPIO_PAR_TIMER);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
/***************************************************************************/
static void __init m523x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u8 par;
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m523x_fec_init(void)
{
/* Set multi-function pins to ethernet use */
writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
m523x_fec_init();
m523x_qspi_init();
m523x_i2c_init();
clkdev_add_table(m523x_clk_lookup, ARRAY_SIZE(m523x_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m523x.c |
/*
* intc.c -- support for the old ColdFire interrupt controller
*
* (C) Copyright 2009, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/traps.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/*
* The mapping of irq number to a mask register bit is not one-to-one.
* The irq numbers are either based on "level" of interrupt or fixed
* for an autovector-able interrupt. So we keep a local data structure
* that maps from irq to mask register. Not all interrupts will have
* an IMR bit.
*/
unsigned char mcf_irq2imr[NR_IRQS];
/*
* Define the minimum and maximum external interrupt numbers.
* This is also used as the "level" interrupt numbers.
*/
#define EIRQ1 25
#define EIRQ7 31
/*
* In the early version 2 core ColdFire parts the IMR register was 16 bits
* in size. Version 3 (and later version 2) core parts have a 32 bit
* sized IMR register. Provide some size independent methods to access the
* IMR register.
*/
#ifdef MCFSIM_IMR_IS_16BITS
void mcf_setimr(int index)
{
u16 imr;
imr = __raw_readw(MCFSIM_IMR);
__raw_writew(imr | (0x1 << index), MCFSIM_IMR);
}
void mcf_clrimr(int index)
{
u16 imr;
imr = __raw_readw(MCFSIM_IMR);
__raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
}
void mcf_maskimr(unsigned int mask)
{
u16 imr;
imr = __raw_readw(MCFSIM_IMR);
imr |= mask;
__raw_writew(imr, MCFSIM_IMR);
}
#else
void mcf_setimr(int index)
{
u32 imr;
imr = __raw_readl(MCFSIM_IMR);
__raw_writel(imr | (0x1 << index), MCFSIM_IMR);
}
void mcf_clrimr(int index)
{
u32 imr;
imr = __raw_readl(MCFSIM_IMR);
__raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
}
void mcf_maskimr(unsigned int mask)
{
u32 imr;
imr = __raw_readl(MCFSIM_IMR);
imr |= mask;
__raw_writel(imr, MCFSIM_IMR);
}
#endif
/*
* Interrupts can be "vectored" on the ColdFire cores that support this old
* interrupt controller. That is, the device raising the interrupt can also
* supply the vector number to interrupt through. The AVR register of the
* interrupt controller enables or disables this for each external interrupt,
* so provide generic support for this. Setting this up is out-of-band for
* the interrupt system API's, and needs to be done by the driver that
* supports this device. Very few devices actually use this.
*/
void mcf_autovector(int irq)
{
#ifdef MCFSIM_AVR
if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
u8 avec;
avec = __raw_readb(MCFSIM_AVR);
avec |= (0x1 << (irq - EIRQ1 + 1));
__raw_writeb(avec, MCFSIM_AVR);
}
#endif
}
static void intc_irq_mask(struct irq_data *d)
{
if (mcf_irq2imr[d->irq])
mcf_setimr(mcf_irq2imr[d->irq]);
}
static void intc_irq_unmask(struct irq_data *d)
{
if (mcf_irq2imr[d->irq])
mcf_clrimr(mcf_irq2imr[d->irq]);
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
{
int irq;
mcf_maskimr(0xffffffff);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
| linux-master | arch/m68k/coldfire/intc.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* timers.c -- generic ColdFire hardware timer support.
*
* Copyright (C) 1999-2008, Greg Ungerer <[email protected]>
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/profile.h>
#include <linux/clocksource.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcftimer.h>
#include <asm/mcfsim.h>
/***************************************************************************/
/*
* By default use timer1 as the system clock timer.
*/
#define FREQ (MCF_BUSCLK / 16)
#define TA(a) (MCFTIMER_BASE1 + (a))
/*
* These provide the underlying interrupt vector support.
* Unfortunately it is a little different on each ColdFire.
*/
void coldfire_profile_init(void);
#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#define __raw_readtrr __raw_readl
#define __raw_writetrr __raw_writel
#else
#define __raw_readtrr __raw_readw
#define __raw_writetrr __raw_writew
#endif
static u32 mcftmr_cycles_per_jiffy;
static u32 mcftmr_cnt;
/***************************************************************************/
static void init_timer_irq(void)
{
#ifdef MCFSIM_ICR_AUTOVEC
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCFSIM_TIMER1ICR);
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCFSIM_TIMER2ICR);
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif
#endif /* MCFSIM_ICR_AUTOVEC */
}
/***************************************************************************/
static irqreturn_t mcftmr_tick(int irq, void *dummy)
{
/* Reset the ColdFire timer */
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
mcftmr_cnt += mcftmr_cycles_per_jiffy;
legacy_timer_tick(1);
return IRQ_HANDLED;
}
/***************************************************************************/
static u64 mcftmr_read_clk(struct clocksource *cs)
{
unsigned long flags;
u32 cycles;
u16 tcn;
local_irq_save(flags);
tcn = __raw_readw(TA(MCFTIMER_TCN));
cycles = mcftmr_cnt;
local_irq_restore(flags);
return cycles + tcn;
}
/***************************************************************************/
static struct clocksource mcftmr_clk = {
.name = "tmr",
.rating = 250,
.read = mcftmr_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/***************************************************************************/
void hw_timer_init(void)
{
int r;
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
mcftmr_cycles_per_jiffy = FREQ / HZ;
/*
* The coldfire timer runs from 0 to TRR included, then 0
* again and so on. It counts thus actually TRR + 1 steps
* for 1 tick, not TRR. So if you want n cycles,
* initialize TRR with n - 1.
*/
__raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
clocksource_register_hz(&mcftmr_clk, FREQ);
init_timer_irq();
r = request_irq(MCF_IRQ_TIMER, mcftmr_tick, IRQF_TIMER, "timer", NULL);
if (r) {
pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
ERR_PTR(r));
}
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
}
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/***************************************************************************/
/*
* By default use timer2 as the profiler clock timer.
*/
#define PA(a) (MCFTIMER_BASE2 + (a))
/*
* Choose a reasonably fast profile timer. Make it an odd value to
* try and get good coverage of kernel operations.
*/
#define PROFILEHZ 1013
/*
* Use the other timer to provide high accuracy profiling info.
*/
irqreturn_t coldfire_profile_tick(int irq, void *dummy)
{
/* Reset ColdFire timer2 */
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
if (current->pid)
profile_tick(CPU_PROFILING);
return IRQ_HANDLED;
}
/***************************************************************************/
void coldfire_profile_init(void)
{
int ret;
printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
PROFILEHZ);
/* Set up TIMER 2 as high speed profile clock */
__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
__raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
ret = request_irq(MCF_IRQ_PROFILER, coldfire_profile_tick, IRQF_TIMER,
"profile timer", NULL);
if (ret) {
pr_err("Failed to request irq %d (profile timer): %pe\n",
MCF_IRQ_PROFILER, ERR_PTR(ret));
}
}
/***************************************************************************/
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
| linux-master | arch/m68k/coldfire/timers.c |
/*
* mcf8390.c -- platform support for 8390 ethernet on many boards
*
* (C) Copyright 2012, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/resource.h>
#include <linux/platform_device.h>
#include <asm/mcf8390.h>
static struct resource mcf8390_resources[] = {
{
.start = NE2000_ADDR,
.end = NE2000_ADDR + NE2000_ADDRSIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = NE2000_IRQ_VECTOR,
.end = NE2000_IRQ_VECTOR,
.flags = IORESOURCE_IRQ,
},
};
static int __init mcf8390_platform_init(void)
{
platform_device_register_simple("mcf8390", -1, mcf8390_resources,
ARRAY_SIZE(mcf8390_resources));
return 0;
}
arch_initcall(mcf8390_platform_init);
| linux-master | arch/m68k/coldfire/mcf8390.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m54xx.c -- platform support for ColdFire 54xx based boards
*
* Copyright (C) 2010, Philippe De Muyter <[email protected]>
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/clk.h>
#include <linux/memblock.h>
#include <asm/pgalloc.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/m54xxsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
#include <asm/m54xxgpt.h>
#ifdef CONFIG_MMU
#include <asm/mmu_context.h>
#endif
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m54xx_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfslt.0", NULL, &clk_sys),
CLKDEV_INIT("mcfslt.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.3", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m54xx_uarts_init(void)
{
/* enable io pins */
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
MCFGPIO_PAR_PSC1);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
}
/***************************************************************************/
static void __init m54xx_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* set the fec/i2c/irq pin assignment register for i2c */
r = readl(MCF_PAR_FECI2CIRQ);
r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
writel(r, MCF_PAR_FECI2CIRQ);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void mcf54xx_reset(void)
{
/* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n");
__raw_writel(0, MCF_GPT_GMS0);
__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
MCF_GPT_GMS0);
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_reset = mcf54xx_reset;
mach_sched_init = hw_timer_init;
m54xx_uarts_init();
m54xx_i2c_init();
clkdev_add_table(m54xx_clk_lookup, ARRAY_SIZE(m54xx_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m54xx.c |
/*
* stmark2.c -- Support for Sysam AMCORE open board
*
* (C) Copyright 2017, Angelo Dureghello <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-fsl-dspi.h>
#include <linux/spi/flash.h>
#include <linux/dma-mapping.h>
#include <asm/mcfsim.h>
/*
* Partitioning of parallel NOR flash (39VF3201B)
*/
static struct mtd_partition stmark2_partitions[] = {
{
.name = "U-Boot (1024K)",
.size = 0x100000,
.offset = 0x0
}, {
.name = "Kernel+initramfs (7168K)",
.size = 0x700000,
.offset = MTDPART_OFS_APPEND
}, {
.name = "Flash Free Space (8192K)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND
}
};
static struct flash_platform_data stmark2_spi_flash_data = {
.name = "is25lp128",
.parts = stmark2_partitions,
.nr_parts = ARRAY_SIZE(stmark2_partitions),
.type = "is25lp128",
};
static struct spi_board_info stmark2_board_info[] __initdata = {
{
.modalias = "m25p80",
.max_speed_hz = 5000000,
.bus_num = 0,
.chip_select = 1,
.platform_data = &stmark2_spi_flash_data,
.mode = SPI_MODE_3,
}
};
/* SPI controller data, SPI (0) */
static struct fsl_dspi_platform_data dspi_spi0_info = {
.cs_num = 4,
.bus_num = 0,
.sck_cs_delay = 100,
.cs_sck_delay = 100,
};
static struct resource dspi_spi0_resource[] = {
[0] = {
.start = MCFDSPI_BASE0,
.end = MCFDSPI_BASE0 + 0xFF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 12,
.end = 13,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = MCF_IRQ_DSPI0,
.end = MCF_IRQ_DSPI0,
.flags = IORESOURCE_IRQ,
},
};
static u64 stmark2_dspi_mask = DMA_BIT_MASK(32);
/* SPI controller, id = bus number */
static struct platform_device dspi_spi0_device = {
.name = "fsl-dspi",
.id = 0,
.num_resources = ARRAY_SIZE(dspi_spi0_resource),
.resource = dspi_spi0_resource,
.dev = {
.platform_data = &dspi_spi0_info,
.dma_mask = &stmark2_dspi_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct platform_device *stmark2_devices[] __initdata = {
&dspi_spi0_device,
};
/*
* Note: proper pin-mux setup is mandatory for proper SPI functionality.
*/
static int __init init_stmark2(void)
{
/* DSPI0, all pins as DSPI, and using CS1 */
__raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
__raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
/* Board gpio setup */
__raw_writeb(0x00, MCFGPIO_PAR_BE);
__raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
__raw_writeb(0x00, MCFGPIO_PAR_CS);
/* CAN pads */
__raw_writeb(0x50, MCFGPIO_PAR_CANI2C);
platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
spi_register_board_info(stmark2_board_info,
ARRAY_SIZE(stmark2_board_info));
return 0;
}
device_initcall(init_stmark2);
| linux-master | arch/m68k/coldfire/stmark2.c |
/*
* device.c -- common ColdFire SoC device support
*
* (C) Copyright 2011, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/fec.h>
#include <linux/dmaengine.h>
#include <asm/traps.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfqspi.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/dma-mcf-edma.h>
#include <linux/platform_data/mmc-esdhc-mcf.h>
/*
* All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
*/
static struct mcf_platform_uart mcf_uart_platform_data[] = {
{
.mapbase = MCFUART_BASE0,
.irq = MCF_IRQ_UART0,
},
{
.mapbase = MCFUART_BASE1,
.irq = MCF_IRQ_UART1,
},
#ifdef MCFUART_BASE2
{
.mapbase = MCFUART_BASE2,
.irq = MCF_IRQ_UART2,
},
#endif
#ifdef MCFUART_BASE3
{
.mapbase = MCFUART_BASE3,
.irq = MCF_IRQ_UART3,
},
#endif
#ifdef MCFUART_BASE4
{
.mapbase = MCFUART_BASE4,
.irq = MCF_IRQ_UART4,
},
#endif
#ifdef MCFUART_BASE5
{
.mapbase = MCFUART_BASE5,
.irq = MCF_IRQ_UART5,
},
#endif
#ifdef MCFUART_BASE6
{
.mapbase = MCFUART_BASE6,
.irq = MCF_IRQ_UART6,
},
#endif
#ifdef MCFUART_BASE7
{
.mapbase = MCFUART_BASE7,
.irq = MCF_IRQ_UART7,
},
#endif
#ifdef MCFUART_BASE8
{
.mapbase = MCFUART_BASE8,
.irq = MCF_IRQ_UART8,
},
#endif
#ifdef MCFUART_BASE9
{
.mapbase = MCFUART_BASE9,
.irq = MCF_IRQ_UART9,
},
#endif
{ },
};
static struct platform_device mcf_uart = {
.name = "mcfuart",
.id = 0,
.dev.platform_data = mcf_uart_platform_data,
};
#if IS_ENABLED(CONFIG_FEC)
#ifdef CONFIG_M5441x
#define FEC_NAME "enet-fec"
static struct fec_platform_data fec_pdata = {
.phy = PHY_INTERFACE_MODE_RMII,
};
#define FEC_PDATA (&fec_pdata)
#else
#define FEC_NAME "fec"
#define FEC_PDATA NULL
#endif
/*
* Some ColdFire cores contain the Fast Ethernet Controller (FEC)
* block. It is Freescale's own hardware block. Some ColdFires
* have 2 of these.
*/
static struct resource mcf_fec0_resources[] = {
{
.start = MCFFEC_BASE0,
.end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_FECRX0,
.end = MCF_IRQ_FECRX0,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_FECTX0,
.end = MCF_IRQ_FECTX0,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_FECENTC0,
.end = MCF_IRQ_FECENTC0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_fec0 = {
.name = FEC_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mcf_fec0_resources),
.resource = mcf_fec0_resources,
.dev = {
.dma_mask = &mcf_fec0.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = FEC_PDATA,
}
};
#ifdef MCFFEC_BASE1
static struct resource mcf_fec1_resources[] = {
{
.start = MCFFEC_BASE1,
.end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_FECRX1,
.end = MCF_IRQ_FECRX1,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_FECTX1,
.end = MCF_IRQ_FECTX1,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_FECENTC1,
.end = MCF_IRQ_FECENTC1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_fec1 = {
.name = FEC_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mcf_fec1_resources),
.resource = mcf_fec1_resources,
.dev = {
.dma_mask = &mcf_fec1.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = FEC_PDATA,
}
};
#endif /* MCFFEC_BASE1 */
#endif /* CONFIG_FEC */
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/*
* The ColdFire QSPI module is an SPI protocol hardware block used
* on a number of different ColdFire CPUs.
*/
static struct resource mcf_qspi_resources[] = {
{
.start = MCFQSPI_BASE,
.end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_QSPI,
.end = MCF_IRQ_QSPI,
.flags = IORESOURCE_IRQ,
},
};
static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
{
int status;
status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
if (status) {
pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
goto fail0;
}
status = gpio_direction_output(MCFQSPI_CS0, 1);
if (status) {
pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
goto fail1;
}
status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
if (status) {
pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
goto fail1;
}
status = gpio_direction_output(MCFQSPI_CS1, 1);
if (status) {
pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
goto fail2;
}
status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
if (status) {
pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
goto fail2;
}
status = gpio_direction_output(MCFQSPI_CS2, 1);
if (status) {
pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
goto fail3;
}
#ifdef MCFQSPI_CS3
status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
if (status) {
pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
goto fail3;
}
status = gpio_direction_output(MCFQSPI_CS3, 1);
if (status) {
pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
gpio_free(MCFQSPI_CS3);
goto fail3;
}
#endif
return 0;
fail3:
gpio_free(MCFQSPI_CS2);
fail2:
gpio_free(MCFQSPI_CS1);
fail1:
gpio_free(MCFQSPI_CS0);
fail0:
return status;
}
static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
{
#ifdef MCFQSPI_CS3
gpio_free(MCFQSPI_CS3);
#endif
gpio_free(MCFQSPI_CS2);
gpio_free(MCFQSPI_CS1);
gpio_free(MCFQSPI_CS0);
}
static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
u8 chip_select, bool cs_high)
{
switch (chip_select) {
case 0:
gpio_set_value(MCFQSPI_CS0, cs_high);
break;
case 1:
gpio_set_value(MCFQSPI_CS1, cs_high);
break;
case 2:
gpio_set_value(MCFQSPI_CS2, cs_high);
break;
#ifdef MCFQSPI_CS3
case 3:
gpio_set_value(MCFQSPI_CS3, cs_high);
break;
#endif
}
}
static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
u8 chip_select, bool cs_high)
{
switch (chip_select) {
case 0:
gpio_set_value(MCFQSPI_CS0, !cs_high);
break;
case 1:
gpio_set_value(MCFQSPI_CS1, !cs_high);
break;
case 2:
gpio_set_value(MCFQSPI_CS2, !cs_high);
break;
#ifdef MCFQSPI_CS3
case 3:
gpio_set_value(MCFQSPI_CS3, !cs_high);
break;
#endif
}
}
static struct mcfqspi_cs_control mcf_cs_control = {
.setup = mcf_cs_setup,
.teardown = mcf_cs_teardown,
.select = mcf_cs_select,
.deselect = mcf_cs_deselect,
};
static struct mcfqspi_platform_data mcf_qspi_data = {
.bus_num = 0,
.num_chipselect = 4,
.cs_control = &mcf_cs_control,
};
static struct platform_device mcf_qspi = {
.name = "mcfqspi",
.id = 0,
.num_resources = ARRAY_SIZE(mcf_qspi_resources),
.resource = mcf_qspi_resources,
.dev.platform_data = &mcf_qspi_data,
};
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
#if IS_ENABLED(CONFIG_I2C_IMX)
static struct resource mcf_i2c0_resources[] = {
{
.start = MCFI2C_BASE0,
.end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C0,
.end = MCF_IRQ_I2C0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c0 = {
.name = "imx1-i2c",
.id = 0,
.num_resources = ARRAY_SIZE(mcf_i2c0_resources),
.resource = mcf_i2c0_resources,
};
#ifdef MCFI2C_BASE1
static struct resource mcf_i2c1_resources[] = {
{
.start = MCFI2C_BASE1,
.end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C1,
.end = MCF_IRQ_I2C1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c1 = {
.name = "imx1-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(mcf_i2c1_resources),
.resource = mcf_i2c1_resources,
};
#endif /* MCFI2C_BASE1 */
#ifdef MCFI2C_BASE2
static struct resource mcf_i2c2_resources[] = {
{
.start = MCFI2C_BASE2,
.end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C2,
.end = MCF_IRQ_I2C2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c2 = {
.name = "imx1-i2c",
.id = 2,
.num_resources = ARRAY_SIZE(mcf_i2c2_resources),
.resource = mcf_i2c2_resources,
};
#endif /* MCFI2C_BASE2 */
#ifdef MCFI2C_BASE3
static struct resource mcf_i2c3_resources[] = {
{
.start = MCFI2C_BASE3,
.end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C3,
.end = MCF_IRQ_I2C3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c3 = {
.name = "imx1-i2c",
.id = 3,
.num_resources = ARRAY_SIZE(mcf_i2c3_resources),
.resource = mcf_i2c3_resources,
};
#endif /* MCFI2C_BASE3 */
#ifdef MCFI2C_BASE4
static struct resource mcf_i2c4_resources[] = {
{
.start = MCFI2C_BASE4,
.end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C4,
.end = MCF_IRQ_I2C4,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c4 = {
.name = "imx1-i2c",
.id = 4,
.num_resources = ARRAY_SIZE(mcf_i2c4_resources),
.resource = mcf_i2c4_resources,
};
#endif /* MCFI2C_BASE4 */
#ifdef MCFI2C_BASE5
static struct resource mcf_i2c5_resources[] = {
{
.start = MCFI2C_BASE5,
.end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C5,
.end = MCF_IRQ_I2C5,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c5 = {
.name = "imx1-i2c",
.id = 5,
.num_resources = ARRAY_SIZE(mcf_i2c5_resources),
.resource = mcf_i2c5_resources,
};
#endif /* MCFI2C_BASE5 */
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
#ifdef MCFEDMA_BASE
static const struct dma_slave_map mcf_edma_map[] = {
{ "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
{ "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
{ "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
{ "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
{ "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
{ "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
{ "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
{ "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
{ "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
{ "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
{ "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
{ "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
{ "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
{ "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
{ "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
{ "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
};
static struct mcf_edma_platform_data mcf_edma_data = {
.dma_channels = 64,
.slave_map = mcf_edma_map,
.slavecnt = ARRAY_SIZE(mcf_edma_map),
};
static struct resource mcf_edma_resources[] = {
{
.start = MCFEDMA_BASE,
.end = MCFEDMA_BASE + MCFEDMA_SIZE - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCFEDMA_IRQ_INTR0,
.end = MCFEDMA_IRQ_INTR0 + 15,
.flags = IORESOURCE_IRQ,
.name = "edma-tx-00-15",
},
{
.start = MCFEDMA_IRQ_INTR16,
.end = MCFEDMA_IRQ_INTR16 + 39,
.flags = IORESOURCE_IRQ,
.name = "edma-tx-16-55",
},
{
.start = MCFEDMA_IRQ_INTR56,
.end = MCFEDMA_IRQ_INTR56,
.flags = IORESOURCE_IRQ,
.name = "edma-tx-56-63",
},
{
.start = MCFEDMA_IRQ_ERR,
.end = MCFEDMA_IRQ_ERR,
.flags = IORESOURCE_IRQ,
.name = "edma-err",
},
};
static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
static struct platform_device mcf_edma = {
.name = "mcf-edma",
.id = 0,
.num_resources = ARRAY_SIZE(mcf_edma_resources),
.resource = mcf_edma_resources,
.dev = {
.dma_mask = &mcf_edma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &mcf_edma_data,
}
};
#endif /* MCFEDMA_BASE */
#ifdef MCFSDHC_BASE
static struct mcf_esdhc_platform_data mcf_esdhc_data = {
.max_bus_width = 4,
.cd_type = ESDHC_CD_NONE,
};
static struct resource mcf_esdhc_resources[] = {
{
.start = MCFSDHC_BASE,
.end = MCFSDHC_BASE + MCFSDHC_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MCF_IRQ_SDHC,
.end = MCF_IRQ_SDHC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_esdhc = {
.name = "sdhci-esdhc-mcf",
.id = 0,
.num_resources = ARRAY_SIZE(mcf_esdhc_resources),
.resource = mcf_esdhc_resources,
.dev.platform_data = &mcf_esdhc_data,
};
#endif /* MCFSDHC_BASE */
#ifdef MCFFLEXCAN_SIZE
#include <linux/can/platform/flexcan.h>
static struct flexcan_platform_data mcf5441x_flexcan_info = {
.clk_src = 1,
.clock_frequency = 120000000,
};
static struct resource mcf5441x_flexcan0_resource[] = {
{
.start = MCFFLEXCAN_BASE0,
.end = MCFFLEXCAN_BASE0 + MCFFLEXCAN_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_IFL0,
.end = MCF_IRQ_IFL0,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_BOFF0,
.end = MCF_IRQ_BOFF0,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_ERR0,
.end = MCF_IRQ_ERR0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_flexcan0 = {
.name = "flexcan-mcf5441x",
.id = 0,
.num_resources = ARRAY_SIZE(mcf5441x_flexcan0_resource),
.resource = mcf5441x_flexcan0_resource,
.dev.platform_data = &mcf5441x_flexcan_info,
};
#endif /* MCFFLEXCAN_SIZE */
static struct platform_device *mcf_devices[] __initdata = {
&mcf_uart,
#if IS_ENABLED(CONFIG_FEC)
&mcf_fec0,
#ifdef MCFFEC_BASE1
&mcf_fec1,
#endif
#endif
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
&mcf_qspi,
#endif
#if IS_ENABLED(CONFIG_I2C_IMX)
&mcf_i2c0,
#ifdef MCFI2C_BASE1
&mcf_i2c1,
#endif
#ifdef MCFI2C_BASE2
&mcf_i2c2,
#endif
#ifdef MCFI2C_BASE3
&mcf_i2c3,
#endif
#ifdef MCFI2C_BASE4
&mcf_i2c4,
#endif
#ifdef MCFI2C_BASE5
&mcf_i2c5,
#endif
#endif
#ifdef MCFEDMA_BASE
&mcf_edma,
#endif
#ifdef MCFSDHC_BASE
&mcf_esdhc,
#endif
#ifdef MCFFLEXCAN_SIZE
&mcf_flexcan0,
#endif
};
/*
* Some ColdFire UARTs let you set the IRQ line to use.
*/
static void __init mcf_uart_set_irq(void)
{
#ifdef MCFUART_UIVR
/* UART0 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
/* UART1 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
#endif
}
static int __init mcf_init_devices(void)
{
mcf_uart_set_irq();
platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
return 0;
}
arch_initcall(mcf_init_devices);
| linux-master | arch/m68k/coldfire/device.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* cache.c -- general ColdFire Cache maintenance code
*
* Copyright (C) 2010, Greg Ungerer ([email protected])
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/***************************************************************************/
#ifdef CACHE_PUSH
/***************************************************************************/
/*
* Use cpushl to push all dirty cache lines back to memory.
* Older versions of GAS don't seem to know how to generate the
* ColdFire cpushl instruction... Oh well, bit stuff it for now.
*/
void mcf_cache_push(void)
{
__asm__ __volatile__ (
"clrl %%d0\n\t"
"1:\n\t"
"movel %%d0,%%a0\n\t"
"2:\n\t"
".word 0xf468\n\t"
"addl %0,%%a0\n\t"
"cmpl %1,%%a0\n\t"
"blt 2b\n\t"
"addql #1,%%d0\n\t"
"cmpil %2,%%d0\n\t"
"bne 1b\n\t"
: /* No output */
: "i" (CACHE_LINE_SIZE),
"i" (DCACHE_SIZE / CACHE_WAYS),
"i" (CACHE_WAYS)
: "d0", "a0" );
}
/***************************************************************************/
#endif /* CACHE_PUSH */
/***************************************************************************/
| linux-master | arch/m68k/coldfire/cache.c |
// SPDX-License-Identifier: GPL-2.0
/*
* m5441x.c -- support for Coldfire m5441x processors
*
* (C) Copyright Steven King <[email protected]>
*/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfdma.h>
#include <asm/mcfclk.h>
DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
DEFINE_CLK(0, "flexcan.0", 8, MCF_CLK);
DEFINE_CLK(0, "flexcan.1", 9, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK);
DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
DEFINE_CLK(2, "ipg.0", 0, MCF_CLK);
DEFINE_CLK(2, "ahb.0", 1, MCF_CLK);
DEFINE_CLK(2, "per.0", 2, MCF_CLK);
static struct clk_lookup m5411x_clk_lookup[] = {
CLKDEV_INIT("flexbus", NULL, &__clk_0_2),
CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
CLKDEV_INIT("mcfcan.1", NULL, &__clk_0_9),
CLKDEV_INIT("imx1-i2c.1", NULL, &__clk_0_14),
CLKDEV_INIT("mcfdspi.1", NULL, &__clk_0_15),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("intc.1", NULL, &__clk_0_19),
CLKDEV_INIT("intc.2", NULL, &__clk_0_20),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("fsl-dspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcfuart.3", NULL, &__clk_0_27),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfadc.0", NULL, &__clk_0_38),
CLKDEV_INIT("mcfdac.0", NULL, &__clk_0_39),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcfsim.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
CLKDEV_INIT("mcfddr-sram.0", NULL, &__clk_0_46),
CLKDEV_INIT("mcfssi.0", NULL, &__clk_0_47),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
CLKDEV_INIT("mcfrng.0", NULL, &__clk_0_49),
CLKDEV_INIT("mcfssi.1", NULL, &__clk_0_50),
CLKDEV_INIT("sdhci-esdhc-mcf.0", NULL, &__clk_0_51),
CLKDEV_INIT("enet-fec.0", NULL, &__clk_0_53),
CLKDEV_INIT("enet-fec.1", NULL, &__clk_0_54),
CLKDEV_INIT("switch.0", NULL, &__clk_0_55),
CLKDEV_INIT("switch.1", NULL, &__clk_0_56),
CLKDEV_INIT("nand.0", NULL, &__clk_0_63),
CLKDEV_INIT("mcfow.0", NULL, &__clk_1_2),
CLKDEV_INIT("imx1-i2c.2", NULL, &__clk_1_4),
CLKDEV_INIT("imx1-i2c.3", NULL, &__clk_1_5),
CLKDEV_INIT("imx1-i2c.4", NULL, &__clk_1_6),
CLKDEV_INIT("imx1-i2c.5", NULL, &__clk_1_7),
CLKDEV_INIT("mcfuart.4", NULL, &__clk_1_24),
CLKDEV_INIT("mcfuart.5", NULL, &__clk_1_25),
CLKDEV_INIT("mcfuart.6", NULL, &__clk_1_26),
CLKDEV_INIT("mcfuart.7", NULL, &__clk_1_27),
CLKDEV_INIT("mcfuart.8", NULL, &__clk_1_28),
CLKDEV_INIT("mcfuart.9", NULL, &__clk_1_29),
CLKDEV_INIT("mcfpwm.0", NULL, &__clk_1_34),
CLKDEV_INIT(NULL, "sys.0", &__clk_1_36),
CLKDEV_INIT("gpio.0", NULL, &__clk_1_37),
CLKDEV_INIT("ipg.0", NULL, &__clk_2_0),
CLKDEV_INIT("ahb.0", NULL, &__clk_2_1),
CLKDEV_INIT("per.0", NULL, &__clk_2_2),
};
static struct clk * const enable_clks[] __initconst = {
/* make sure these clocks are enabled */
&__clk_0_8, /* flexcan.0 */
&__clk_0_9, /* flexcan.1 */
&__clk_0_15, /* dspi.1 */
&__clk_0_17, /* eDMA */
&__clk_0_18, /* intc0 */
&__clk_0_19, /* intc0 */
&__clk_0_20, /* intc0 */
&__clk_0_23, /* dspi.0 */
&__clk_0_24, /* uart0 */
&__clk_0_25, /* uart1 */
&__clk_0_26, /* uart2 */
&__clk_0_27, /* uart3 */
&__clk_0_33, /* pit.1 */
&__clk_0_37, /* eport */
&__clk_0_48, /* pll */
&__clk_0_51, /* esdhc */
&__clk_1_36, /* CCM/reset module/Power management */
&__clk_1_37, /* gpio */
};
static struct clk * const disable_clks[] __initconst = {
&__clk_0_14, /* i2c.1 */
&__clk_0_22, /* i2c.0 */
&__clk_0_23, /* dspi.0 */
&__clk_0_28, /* tmr.1 */
&__clk_0_29, /* tmr.2 */
&__clk_0_30, /* tmr.2 */
&__clk_0_31, /* tmr.3 */
&__clk_0_32, /* pit.0 */
&__clk_0_34, /* pit.2 */
&__clk_0_35, /* pit.3 */
&__clk_0_38, /* adc */
&__clk_0_39, /* dac */
&__clk_0_44, /* usb otg */
&__clk_0_45, /* usb host */
&__clk_0_47, /* ssi.0 */
&__clk_0_49, /* rng */
&__clk_0_50, /* ssi.1 */
&__clk_0_53, /* enet-fec */
&__clk_0_54, /* enet-fec */
&__clk_0_55, /* switch.0 */
&__clk_0_56, /* switch.1 */
&__clk_1_2, /* 1-wire */
&__clk_1_4, /* i2c.2 */
&__clk_1_5, /* i2c.3 */
&__clk_1_6, /* i2c.4 */
&__clk_1_7, /* i2c.5 */
&__clk_1_24, /* uart 4 */
&__clk_1_25, /* uart 5 */
&__clk_1_26, /* uart 6 */
&__clk_1_27, /* uart 7 */
&__clk_1_28, /* uart 8 */
&__clk_1_29, /* uart 9 */
};
static void __clk_enable2(struct clk *clk)
{
__raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
}
static void __clk_disable2(struct clk *clk)
{
__raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
}
struct clk_ops clk_ops2 = {
.enable = __clk_enable2,
.disable = __clk_disable2,
};
static void __init m5441x_clk_init(void)
{
unsigned i;
for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
__clk_init_enabled(enable_clks[i]);
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m5411x_clk_lookup, ARRAY_SIZE(m5411x_clk_lookup));
}
static void __init m5441x_uarts_init(void)
{
__raw_writeb(0x0f, MCFGPIO_PAR_UART0);
__raw_writeb(0x00, MCFGPIO_PAR_UART1);
__raw_writeb(0x00, MCFGPIO_PAR_UART2);
}
static void __init m5441x_fec_init(void)
{
__raw_writeb(0x03, MCFGPIO_PAR_FEC);
}
void __init config_BSP(char *commandp, int size)
{
m5441x_clk_init();
mach_sched_init = hw_timer_init;
m5441x_uarts_init();
m5441x_fec_init();
}
| linux-master | arch/m68k/coldfire/m5441x.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m528x.c -- platform support for ColdFire 528x based boards
*
* Sub-architcture dependent initialization code for the Freescale
* 5280, 5281 and 5282 CPUs.
*
* Copyright (C) 1999-2003, Greg Ungerer ([email protected])
* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfuart.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m528x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m528x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* setup Port QS for QSPI with gpio CS control */
__raw_writeb(0x07, MCFGPIO_PQSPAR);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
/***************************************************************************/
static void __init m528x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u16 paspar;
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
paspar = readw(MCFGPIO_PASPAR);
paspar |= 0xF;
writew(paspar, MCFGPIO_PASPAR);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m528x_uarts_init(void)
{
u8 port;
/* make sure PUAPAR is set for UART0 and UART1 */
port = readb(MCFGPIO_PUAPAR);
port |= 0x03 | (0x03 << 2);
writeb(port, MCFGPIO_PUAPAR);
}
/***************************************************************************/
static void __init m528x_fec_init(void)
{
u16 v16;
/* Set multi-function pins to ethernet mode for fec0 */
v16 = readw(MCFGPIO_PASPAR);
writew(v16 | 0xf00, MCFGPIO_PASPAR);
writeb(0xc0, MCFGPIO_PEHLPAR);
}
/***************************************************************************/
#ifdef CONFIG_WILDFIRE
void wildfire_halt(void)
{
writeb(0, 0x30000007);
writeb(0x2, 0x30000007);
}
#endif
#ifdef CONFIG_WILDFIREMOD
void wildfiremod_halt(void)
{
printk(KERN_INFO "WildFireMod hibernating...\n");
/* Set portE.5 to Digital IO */
writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
/* Make portE.5 an output */
writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
/* Now toggle portE.5 from low to high */
writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
printk(KERN_EMERG "Failed to hibernate. Halting!\n");
}
#endif
void __init config_BSP(char *commandp, int size)
{
#ifdef CONFIG_WILDFIRE
mach_halt = wildfire_halt;
#endif
#ifdef CONFIG_WILDFIREMOD
mach_halt = wildfiremod_halt;
#endif
mach_sched_init = hw_timer_init;
m528x_uarts_init();
m528x_fec_init();
m528x_qspi_init();
m528x_i2c_init();
clkdev_add_table(m528x_clk_lookup, ARRAY_SIZE(m528x_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m528x.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* firebee.c -- extra startup code support for the FireBee boards
*
* Copyright (C) 2011, Greg Ungerer ([email protected])
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/***************************************************************************/
/*
* 8MB of NOR flash fitted to the FireBee board.
*/
#define FLASH_PHYS_ADDR 0xe0000000 /* Physical address of flash */
#define FLASH_PHYS_SIZE 0x00800000 /* Size of flash */
#define PART_BOOT_START 0x00000000 /* Start at bottom of flash */
#define PART_BOOT_SIZE 0x00040000 /* 256k in size */
#define PART_IMAGE_START 0x00040000 /* Start after boot loader */
#define PART_IMAGE_SIZE 0x006c0000 /* Most of flash */
#define PART_FPGA_START 0x00700000 /* Start at offset 7MB */
#define PART_FPGA_SIZE 0x00100000 /* 1MB in size */
static struct mtd_partition firebee_flash_parts[] = {
{
.name = "dBUG",
.offset = PART_BOOT_START,
.size = PART_BOOT_SIZE,
},
{
.name = "FPGA",
.offset = PART_FPGA_START,
.size = PART_FPGA_SIZE,
},
{
.name = "image",
.offset = PART_IMAGE_START,
.size = PART_IMAGE_SIZE,
},
};
static struct physmap_flash_data firebee_flash_data = {
.width = 2,
.nr_parts = ARRAY_SIZE(firebee_flash_parts),
.parts = firebee_flash_parts,
};
static struct resource firebee_flash_resource = {
.start = FLASH_PHYS_ADDR,
.end = FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device firebee_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &firebee_flash_data,
},
.num_resources = 1,
.resource = &firebee_flash_resource,
};
/***************************************************************************/
static int __init init_firebee(void)
{
platform_device_register(&firebee_flash);
return 0;
}
arch_initcall(init_firebee);
/***************************************************************************/
| linux-master | arch/m68k/coldfire/firebee.c |
/*
* intc-2.c
*
* General interrupt controller code for the many ColdFire cores that use
* interrupt controllers with 63 interrupt sources, organized as 56 fully-
* programmable + 7 fixed-level interrupt sources. This includes the 523x
* family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
* controllers, and the 547x and 548x families which have only one of them.
*
* The external 7 fixed interrupts are part of the Edge Port unit of these
* ColdFire parts. They can be configured as level or edge triggered.
*
* (C) Copyright 2009-2011, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/traps.h>
/*
* Bit definitions for the ICR family of registers.
*/
#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
/*
* The EDGE Port interrupts are the fixed 7 external interrupts.
* They need some special treatment, for example they need to be acked.
*/
#define EINT0 64 /* Is not actually used, but spot reserved for it */
#define EINT1 65 /* EDGE Port interrupt 1 */
#define EINT7 71 /* EDGE Port interrupt 7 */
#ifdef MCFICM_INTC1
#define NR_VECS 128
#else
#define NR_VECS 64
#endif
static void intc_irq_mask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
unsigned long imraddr;
u32 val, imrbit;
#ifdef MCFICM_INTC1
imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
imraddr = MCFICM_INTC0;
#endif
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
imrbit = 0x1 << (irq & 0x1f);
val = __raw_readl(imraddr);
__raw_writel(val | imrbit, imraddr);
}
static void intc_irq_unmask(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
unsigned long imraddr;
u32 val, imrbit;
#ifdef MCFICM_INTC1
imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
imraddr = MCFICM_INTC0;
#endif
imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
imrbit = 0x1 << (irq & 0x1f);
/* Don't set the "maskall" bit! */
if ((irq & 0x20) == 0)
imrbit |= 0x1;
val = __raw_readl(imraddr);
__raw_writel(val & ~imrbit, imraddr);
}
/*
* Only the external (or EDGE Port) interrupts need to be acknowledged
* here, as part of the IRQ handler. They only really need to be ack'ed
* if they are in edge triggered mode, but there is no harm in doing it
* for all types.
*/
static void intc_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
__raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
}
/*
* Each vector needs a unique priority and level associated with it.
* We don't really care so much what they are, we don't rely on the
* traditional priority interrupt scheme of the m68k/ColdFire. This
* only needs to be set once for an interrupt, and we will never change
* these values once we have set them.
*/
static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
static unsigned int intc_irq_startup(struct irq_data *d)
{
unsigned int irq = d->irq - MCFINT_VECBASE;
unsigned long icraddr;
#ifdef MCFICM_INTC1
icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
icraddr = MCFICM_INTC0;
#endif
icraddr += MCFINTC_ICR0 + (irq & 0x3f);
if (__raw_readb(icraddr) == 0)
__raw_writeb(intc_intpri--, icraddr);
irq = d->irq;
if ((irq >= EINT1) && (irq <= EINT7)) {
u8 v;
irq -= EINT0;
/* Set EPORT line as input */
v = __raw_readb(MCFEPORT_EPDDR);
__raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
/* Set EPORT line as interrupt source */
v = __raw_readb(MCFEPORT_EPIER);
__raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
}
intc_irq_unmask(d);
return 0;
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int irq = d->irq;
u16 pa, tb;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
tb = 0x1;
break;
case IRQ_TYPE_EDGE_FALLING:
tb = 0x2;
break;
case IRQ_TYPE_EDGE_BOTH:
tb = 0x3;
break;
default:
/* Level triggered */
tb = 0;
break;
}
if (tb)
irq_set_handler(irq, handle_edge_irq);
irq -= EINT0;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
__raw_writew(pa, MCFEPORT_EPPAR);
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
};
static struct irq_chip intc_irq_chip_edge_port = {
.name = "CF-INTC-EP",
.irq_startup = intc_irq_startup,
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
.irq_ack = intc_irq_ack,
.irq_set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
{
int irq;
/* Mask all interrupt sources */
__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
#ifdef MCFICM_INTC1
__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
#endif
for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
if ((irq >= EINT1) && (irq <=EINT7))
irq_set_chip(irq, &intc_irq_chip_edge_port);
else
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
| linux-master | arch/m68k/coldfire/intc-2.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* pit.c -- Freescale ColdFire PIT timer. Currently this type of
* hardware timer only exists in the Freescale ColdFire
* 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
* family members will probably use it too.
*
* Copyright (C) 1999-2008, Greg Ungerer ([email protected])
* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/coldfire.h>
#include <asm/mcfpit.h>
#include <asm/mcfsim.h>
/***************************************************************************/
/*
* By default use timer1 as the system clock timer.
*/
#define FREQ ((MCF_CLK / 2) / 64)
#define TA(a) (MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
static u32 pit_cnt;
/*
* Initialize the PIT timer.
*
* This is also called after resume to bring the PIT into operation again.
*/
static int cf_pit_set_periodic(struct clock_event_device *evt)
{
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
return 0;
}
static int cf_pit_set_oneshot(struct clock_event_device *evt)
{
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
return 0;
}
static int cf_pit_shutdown(struct clock_event_device *evt)
{
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
return 0;
}
/*
* Program the next event in oneshot mode
*
* Delta is given in PIT ticks
*/
static int cf_pit_next_event(unsigned long delta,
struct clock_event_device *evt)
{
__raw_writew(delta, TA(MCFPIT_PMR));
return 0;
}
struct clock_event_device cf_pit_clockevent = {
.name = "pit",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = cf_pit_shutdown,
.set_state_periodic = cf_pit_set_periodic,
.set_state_oneshot = cf_pit_set_oneshot,
.set_next_event = cf_pit_next_event,
.shift = 32,
.irq = MCF_IRQ_PIT1,
};
/***************************************************************************/
static irqreturn_t pit_tick(int irq, void *dummy)
{
struct clock_event_device *evt = &cf_pit_clockevent;
u16 pcsr;
/* Reset the ColdFire timer */
pcsr = __raw_readw(TA(MCFPIT_PCSR));
__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
pit_cnt += PIT_CYCLES_PER_JIFFY;
evt->event_handler(evt);
return IRQ_HANDLED;
}
/***************************************************************************/
static u64 pit_read_clk(struct clocksource *cs)
{
unsigned long flags;
u32 cycles;
u16 pcntr;
local_irq_save(flags);
pcntr = __raw_readw(TA(MCFPIT_PCNTR));
cycles = pit_cnt;
local_irq_restore(flags);
return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
}
/***************************************************************************/
static struct clocksource pit_clk = {
.name = "pit",
.rating = 100,
.read = pit_read_clk,
.mask = CLOCKSOURCE_MASK(32),
};
/***************************************************************************/
void hw_timer_init(void)
{
int ret;
cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
cf_pit_clockevent.max_delta_ns =
clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
cf_pit_clockevent.max_delta_ticks = 0xFFFF;
cf_pit_clockevent.min_delta_ns =
clockevent_delta2ns(0x3f, &cf_pit_clockevent);
cf_pit_clockevent.min_delta_ticks = 0x3f;
clockevents_register_device(&cf_pit_clockevent);
ret = request_irq(MCF_IRQ_PIT1, pit_tick, IRQF_TIMER, "timer", NULL);
if (ret) {
pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_PIT1,
ERR_PTR(ret));
}
clocksource_register_hz(&pit_clk, FREQ);
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/pit.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* m5206.c -- platform support for ColdFire 5206 based boards
*
* Copyright (C) 1999-2002, Greg Ungerer ([email protected])
* Copyright (C) 2000-2001, Lineo Inc. (www.lineo.com)
*/
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfclk.h>
/***************************************************************************/
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
static struct clk_lookup m5206_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
static void __init m5206_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
commandp[size-1] = 0;
#endif /* CONFIG_NETtel */
mach_sched_init = hw_timer_init;
/* Only support the external interrupts on their primary level */
mcf_mapirq2imr(25, MCFINTC_EINT1);
mcf_mapirq2imr(28, MCFINTC_EINT4);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5206_i2c_init();
clkdev_add_table(m5206_clk_lookup, ARRAY_SIZE(m5206_clk_lookup));
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/m5206.c |
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* vectors.c -- high level trap setup for ColdFire
*
* Copyright (C) 1999-2007, Greg Ungerer <[email protected]>
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfwdebug.h>
/***************************************************************************/
#ifdef TRAP_DBG_INTERRUPT
asmlinkage void dbginterrupt_c(struct frame *fp)
{
extern void dump(struct pt_regs *fp);
printk(KERN_DEBUG "%s(%d): BUS ERROR TRAP\n", __FILE__, __LINE__);
dump((struct pt_regs *) fp);
asm("halt");
}
#endif
/***************************************************************************/
/* Assembler routines */
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void system_call(void);
asmlinkage void inthandler(void);
void __init trap_init(void)
{
int i;
/*
* There is a common trap handler and common interrupt
* handler that handle almost every vector. We treat
* the system call and bus error special, they get their
* own first level handlers.
*/
for (i = 3; (i <= 23); i++)
_ramvec[i] = trap;
for (i = 33; (i <= 63); i++)
_ramvec[i] = trap;
for (i = 24; (i <= 31); i++)
_ramvec[i] = inthandler;
for (i = 64; (i < 255); i++)
_ramvec[i] = inthandler;
_ramvec[255] = 0;
_ramvec[2] = buserr;
_ramvec[32] = system_call;
#ifdef TRAP_DBG_INTERRUPT
_ramvec[12] = dbginterrupt;
#endif
}
/***************************************************************************/
| linux-master | arch/m68k/coldfire/vectors.c |
// SPDX-License-Identifier: GPL-2.0
/*
* dma_timer.c -- Freescale ColdFire DMA Timer.
*
* Copyright (C) 2007, Benedikt Spranger <[email protected]>
* Copyright (C) 2008. Sebastian Siewior, Linutronix
*
*/
#include <linux/clocksource.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfpit.h>
#include <asm/mcfsim.h>
#define DMA_TIMER_0 (0x00)
#define DMA_TIMER_1 (0x40)
#define DMA_TIMER_2 (0x80)
#define DMA_TIMER_3 (0xc0)
#define DTMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x400)
#define DTXMR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x402)
#define DTER0 (MCF_IPSBAR + DMA_TIMER_0 + 0x403)
#define DTRR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x404)
#define DTCR0 (MCF_IPSBAR + DMA_TIMER_0 + 0x408)
#define DTCN0 (MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
#define DMA_FREQ ((MCF_CLK / 2) / 16)
/* DTMR */
#define DMA_DTMR_RESTART (1 << 3)
#define DMA_DTMR_CLK_DIV_1 (1 << 1)
#define DMA_DTMR_CLK_DIV_16 (2 << 1)
#define DMA_DTMR_ENABLE (1 << 0)
static u64 cf_dt_get_cycles(struct clocksource *cs)
{
return __raw_readl(DTCN0);
}
static struct clocksource clocksource_cf_dt = {
.name = "coldfire_dma_timer",
.rating = 200,
.read = cf_dt_get_cycles,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static int __init init_cf_dt_clocksource(void)
{
/*
* We setup DMA timer 0 in free run mode. This incrementing counter is
* used as a highly precious clock source. With MCF_CLOCK = 150 MHz we
* get a ~213 ns resolution and the 32bit register will overflow almost
* every 15 minutes.
*/
__raw_writeb(0x00, DTXMR0);
__raw_writeb(0x00, DTER0);
__raw_writel(0x00000000, DTRR0);
__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
}
arch_initcall(init_cf_dt_clocksource);
#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
#define CYC2NS_SCALE ((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000))
static unsigned long long cycles2ns(unsigned long cycl)
{
return (unsigned long long) ((unsigned long long)cycl *
CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR;
}
unsigned long long sched_clock(void)
{
unsigned long cycl = __raw_readl(DTCN0);
return cycles2ns(cycl);
}
| linux-master | arch/m68k/coldfire/dma_timer.c |
/*
* arch/m68k/q40/q40ints.c
*
* Copyright (C) 1999,2001 Richard Zidlicky
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* .. used to be loosely based on bvme6000ints.c
*
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/machdep.h>
#include <asm/ptrace.h>
#include <asm/traps.h>
#include <asm/q40_master.h>
#include <asm/q40ints.h>
/*
* Q40 IRQs are defined as follows:
* 3,4,5,6,7,10,11,14,15 : ISA dev IRQs
* 16-31: reserved
* 32 : keyboard int
* 33 : frame int (50/200 Hz periodic timer)
* 34 : sample int (10/20 KHz periodic timer)
*
*/
static void q40_irq_handler(unsigned int, struct pt_regs *fp);
static void q40_irq_enable(struct irq_data *data);
static void q40_irq_disable(struct irq_data *data);
unsigned short q40_ablecount[35];
unsigned short q40_state[35];
static unsigned int q40_irq_startup(struct irq_data *data)
{
unsigned int irq = data->irq;
/* test for ISA ints not implemented by HW */
switch (irq) {
case 1: case 2: case 8: case 9:
case 11: case 12: case 13:
pr_warn("%s: ISA IRQ %d not implemented by HW\n", __func__,
irq);
/* FIXME return -ENXIO; */
}
return 0;
}
static void q40_irq_shutdown(struct irq_data *data)
{
}
static struct irq_chip q40_irq_chip = {
.name = "q40",
.irq_startup = q40_irq_startup,
.irq_shutdown = q40_irq_shutdown,
.irq_enable = q40_irq_enable,
.irq_disable = q40_irq_disable,
};
/*
* void q40_init_IRQ (void)
*
* Parameters: None
*
* Returns: Nothing
*
* This function is called during kernel startup to initialize
* the q40 IRQ handling routines.
*/
static int disabled;
void __init q40_init_IRQ(void)
{
m68k_setup_irq_controller(&q40_irq_chip, handle_simple_irq, 1,
Q40_IRQ_MAX);
/* setup handler for ISA ints */
m68k_setup_auto_interrupt(q40_irq_handler);
m68k_irq_startup_irq(IRQ_AUTO_2);
m68k_irq_startup_irq(IRQ_AUTO_4);
/* now enable some ints.. */
master_outb(1, EXT_ENABLE_REG); /* ISA IRQ 5-15 */
/* make sure keyboard IRQ is disabled */
master_outb(0, KEY_IRQ_ENABLE_REG);
}
/*
* this stuff doesn't really belong here..
*/
int ql_ticks; /* 200Hz ticks since last jiffie */
static int sound_ticks;
#define SVOL 45
void q40_mksound(unsigned int hz, unsigned int ticks)
{
/* for now ignore hz, except that hz==0 switches off sound */
/* simply alternate the ampl (128-SVOL)-(128+SVOL)-..-.. at 200Hz */
if (hz == 0) {
if (sound_ticks)
sound_ticks = 1;
*DAC_LEFT = 128;
*DAC_RIGHT = 128;
return;
}
/* sound itself is done in q40_timer_int */
if (sound_ticks == 0)
sound_ticks = 1000; /* pretty long beep */
sound_ticks = ticks << 1;
}
static irqreturn_t q40_timer_int(int irq, void *dev_id)
{
ql_ticks = ql_ticks ? 0 : 1;
if (sound_ticks) {
unsigned char sval=(sound_ticks & 1) ? 128-SVOL : 128+SVOL;
sound_ticks--;
*DAC_LEFT=sval;
*DAC_RIGHT=sval;
}
if (!ql_ticks) {
unsigned long flags;
local_irq_save(flags);
legacy_timer_tick(1);
timer_heartbeat();
local_irq_restore(flags);
}
return IRQ_HANDLED;
}
void q40_sched_init (void)
{
int timer_irq;
timer_irq = Q40_IRQ_FRAME;
if (request_irq(timer_irq, q40_timer_int, 0, "timer", NULL))
panic("Couldn't register timer int");
master_outb(-1, FRAME_CLEAR_REG);
master_outb( 1, FRAME_RATE_REG);
}
/*
* tables to translate bits into IRQ numbers
* it is a good idea to order the entries by priority
*
*/
struct IRQ_TABLE{ unsigned mask; int irq ;};
#if 0
static struct IRQ_TABLE iirqs[]={
{Q40_IRQ_FRAME_MASK,Q40_IRQ_FRAME},
{Q40_IRQ_KEYB_MASK,Q40_IRQ_KEYBOARD},
{0,0}};
#endif
static struct IRQ_TABLE eirqs[] = {
{ .mask = Q40_IRQ3_MASK, .irq = 3 }, /* ser 1 */
{ .mask = Q40_IRQ4_MASK, .irq = 4 }, /* ser 2 */
{ .mask = Q40_IRQ14_MASK, .irq = 14 }, /* IDE 1 */
{ .mask = Q40_IRQ15_MASK, .irq = 15 }, /* IDE 2 */
{ .mask = Q40_IRQ6_MASK, .irq = 6 }, /* floppy, handled elsewhere */
{ .mask = Q40_IRQ7_MASK, .irq = 7 }, /* par */
{ .mask = Q40_IRQ5_MASK, .irq = 5 },
{ .mask = Q40_IRQ10_MASK, .irq = 10 },
{0,0}
};
/* complain only this many times about spurious ints : */
static int ccleirq=60; /* ISA dev IRQs*/
/*static int cclirq=60;*/ /* internal */
/* FIXME: add shared ints,mask,unmask,probing.... */
#define IRQ_INPROGRESS 1
/*static unsigned short saved_mask;*/
//static int do_tint=0;
#define DEBUG_Q40INT
/*#define IP_USE_DISABLE *//* would be nice, but crashes ???? */
static int mext_disabled; /* ext irq disabled by master chip? */
static int aliased_irq; /* how many times inside handler ?*/
/* got interrupt, dispatch to ISA or keyboard/timer IRQs */
static void q40_irq_handler(unsigned int irq, struct pt_regs *fp)
{
unsigned mir, mer;
int i;
//repeat:
mir = master_inb(IIRQ_REG);
#ifdef CONFIG_BLK_DEV_FD
if ((mir & Q40_IRQ_EXT_MASK) &&
(master_inb(EIRQ_REG) & Q40_IRQ6_MASK)) {
floppy_hardint();
return;
}
#endif
switch (irq) {
case 4:
case 6:
do_IRQ(Q40_IRQ_SAMPLE, fp);
return;
}
if (mir & Q40_IRQ_FRAME_MASK) {
do_IRQ(Q40_IRQ_FRAME, fp);
master_outb(-1, FRAME_CLEAR_REG);
}
if ((mir & Q40_IRQ_SER_MASK) || (mir & Q40_IRQ_EXT_MASK)) {
mer = master_inb(EIRQ_REG);
for (i = 0; eirqs[i].mask; i++) {
if (mer & eirqs[i].mask) {
irq = eirqs[i].irq;
/*
* There is a little mess wrt which IRQ really caused this irq request. The
* main problem is that IIRQ_REG and EIRQ_REG reflect the state when they
* are read - which is long after the request came in. In theory IRQs should
* not just go away but they occasionally do
*/
if (irq > 4 && irq <= 15 && mext_disabled) {
/*aliased_irq++;*/
goto iirq;
}
if (q40_state[irq] & IRQ_INPROGRESS) {
/* some handlers do local_irq_enable() for irq latency reasons, */
/* however reentering an active irq handler is not permitted */
#ifdef IP_USE_DISABLE
/* in theory this is the better way to do it because it still */
/* lets through eg the serial irqs, unfortunately it crashes */
disable_irq(irq);
disabled = 1;
#else
/*pr_warn("IRQ_INPROGRESS detected for irq %d, disabling - %s disabled\n",
irq, disabled ? "already" : "not yet"); */
fp->sr = (((fp->sr) & (~0x700))+0x200);
disabled = 1;
#endif
goto iirq;
}
q40_state[irq] |= IRQ_INPROGRESS;
do_IRQ(irq, fp);
q40_state[irq] &= ~IRQ_INPROGRESS;
/* naively enable everything, if that fails than */
/* this function will be reentered immediately thus */
/* getting another chance to disable the IRQ */
if (disabled) {
#ifdef IP_USE_DISABLE
if (irq > 4) {
disabled = 0;
enable_irq(irq);
}
#else
disabled = 0;
/*pr_info("reenabling irq %d\n", irq); */
#endif
}
// used to do 'goto repeat;' here, this delayed bh processing too long
return;
}
}
if (mer && ccleirq > 0 && !aliased_irq) {
pr_warn("ISA interrupt from unknown source? EIRQ_REG = %x\n",
mer);
ccleirq--;
}
}
iirq:
mir = master_inb(IIRQ_REG);
/* should test whether keyboard irq is really enabled, doing it in defhand */
if (mir & Q40_IRQ_KEYB_MASK)
do_IRQ(Q40_IRQ_KEYBOARD, fp);
return;
}
void q40_irq_enable(struct irq_data *data)
{
unsigned int irq = data->irq;
if (irq >= 5 && irq <= 15) {
mext_disabled--;
if (mext_disabled > 0)
pr_warn("q40_irq_enable : nested disable/enable\n");
if (mext_disabled == 0)
master_outb(1, EXT_ENABLE_REG);
}
}
void q40_irq_disable(struct irq_data *data)
{
unsigned int irq = data->irq;
/* disable ISA iqs : only do something if the driver has been
* verified to be Q40 "compatible" - right now IDE, NE2K
* Any driver should not attempt to sleep across disable_irq !!
*/
if (irq >= 5 && irq <= 15) {
master_outb(0, EXT_ENABLE_REG);
mext_disabled++;
if (mext_disabled > 1)
pr_info("disable_irq nesting count %d\n",
mext_disabled);
}
}
| linux-master | arch/m68k/q40/q40ints.c |
/*
* arch/m68k/q40/config.c
*
* Copyright (C) 1999 Richard Zidlicky
*
* originally based on:
*
* linux/bvme/config.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file README.legal in the main directory of this archive
* for more details.
*/
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/console.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/serial_reg.h>
#include <linux/rtc.h>
#include <linux/vt_kern.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/q40_master.h>
#include <asm/config.h>
extern void q40_init_IRQ(void);
static void q40_get_model(char *model);
extern void q40_sched_init(void);
static int q40_hwclk(int, struct rtc_time *);
static int q40_get_rtc_pll(struct rtc_pll_info *pll);
static int q40_set_rtc_pll(struct rtc_pll_info *pll);
extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/);
static void q40_mem_console_write(struct console *co, const char *b,
unsigned int count);
extern int ql_ticks;
static struct console q40_console_driver = {
.name = "debug",
.write = q40_mem_console_write,
.flags = CON_PRINTBUFFER,
.index = -1,
};
/* early debugging function:*/
extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
static int _cpleft;
static void q40_mem_console_write(struct console *co, const char *s,
unsigned int count)
{
const char *p = s;
if (count < _cpleft) {
while (count-- > 0) {
*q40_mem_cptr = *p++;
q40_mem_cptr += 4;
_cpleft--;
}
}
}
static int __init q40_debug_setup(char *arg)
{
/* useful for early debugging stages - writes kernel messages into SRAM */
if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) {
/*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
_cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4;
register_console(&q40_console_driver);
}
return 0;
}
early_param("debug", q40_debug_setup);
#if 0
void printq40(char *str)
{
int l = strlen(str);
char *p = q40_mem_cptr;
while (l-- > 0 && _cpleft-- > 0) {
*p = *str++;
p += 4;
}
q40_mem_cptr = p;
}
#endif
static int halted;
#ifdef CONFIG_HEARTBEAT
static void q40_heartbeat(int on)
{
if (halted)
return;
if (on)
Q40_LED_ON();
else
Q40_LED_OFF();
}
#endif
static void q40_reset(void)
{
halted = 1;
pr_info("*******************************************\n"
"Called q40_reset : press the RESET button!!\n"
"*******************************************\n");
Q40_LED_ON();
while (1)
;
}
static void q40_halt(void)
{
halted = 1;
pr_info("*******************\n"
" Called q40_halt\n"
"*******************\n");
Q40_LED_ON();
while (1)
;
}
static void q40_get_model(char *model)
{
sprintf(model, "Q40");
}
static unsigned int serports[] =
{
0x3f8,0x2f8,0x3e8,0x2e8,0
};
static void __init q40_disable_irqs(void)
{
unsigned i, j;
j = 0;
while ((i = serports[j++]))
outb(0, i + UART_IER);
master_outb(0, EXT_ENABLE_REG);
master_outb(0, KEY_IRQ_ENABLE_REG);
}
void __init config_q40(void)
{
mach_sched_init = q40_sched_init;
mach_init_IRQ = q40_init_IRQ;
mach_hwclk = q40_hwclk;
mach_get_rtc_pll = q40_get_rtc_pll;
mach_set_rtc_pll = q40_set_rtc_pll;
mach_reset = q40_reset;
mach_get_model = q40_get_model;
#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
mach_beep = q40_mksound;
#endif
#ifdef CONFIG_HEARTBEAT
mach_heartbeat = q40_heartbeat;
#endif
mach_halt = q40_halt;
/* disable a few things that SMSQ might have left enabled */
q40_disable_irqs();
}
int __init q40_parse_bootinfo(const struct bi_record *rec)
{
return 1;
}
/*
* Looks like op is non-zero for setting the clock, and zero for
* reading the clock.
*
* struct hwclk_time {
* unsigned sec; 0..59
* unsigned min; 0..59
* unsigned hour; 0..23
* unsigned day; 1..31
* unsigned mon; 0..11
* unsigned year; 00...
* int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
* };
*/
static int q40_hwclk(int op, struct rtc_time *t)
{
if (op) {
/* Write.... */
Q40_RTC_CTRL |= Q40_RTC_WRITE;
Q40_RTC_SECS = bin2bcd(t->tm_sec);
Q40_RTC_MINS = bin2bcd(t->tm_min);
Q40_RTC_HOUR = bin2bcd(t->tm_hour);
Q40_RTC_DATE = bin2bcd(t->tm_mday);
Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
if (t->tm_wday >= 0)
Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
} else {
/* Read.... */
Q40_RTC_CTRL |= Q40_RTC_READ;
t->tm_year = bcd2bin (Q40_RTC_YEAR);
t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
t->tm_mday = bcd2bin (Q40_RTC_DATE);
t->tm_hour = bcd2bin (Q40_RTC_HOUR);
t->tm_min = bcd2bin (Q40_RTC_MINS);
t->tm_sec = bcd2bin (Q40_RTC_SECS);
Q40_RTC_CTRL &= ~(Q40_RTC_READ);
if (t->tm_year < 70)
t->tm_year += 100;
t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
}
return 0;
}
/* get and set PLL calibration of RTC clock */
#define Q40_RTC_PLL_MASK ((1<<5)-1)
#define Q40_RTC_PLL_SIGN (1<<5)
static int q40_get_rtc_pll(struct rtc_pll_info *pll)
{
int tmp = Q40_RTC_CTRL;
pll->pll_ctrl = 0;
pll->pll_value = tmp & Q40_RTC_PLL_MASK;
if (tmp & Q40_RTC_PLL_SIGN)
pll->pll_value = -pll->pll_value;
pll->pll_max = 31;
pll->pll_min = -31;
pll->pll_posmult = 512;
pll->pll_negmult = 256;
pll->pll_clock = 125829120;
return 0;
}
static int q40_set_rtc_pll(struct rtc_pll_info *pll)
{
if (!pll->pll_ctrl) {
/* the docs are a bit unclear so I am doublesetting */
/* RTC_WRITE here ... */
int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
Q40_RTC_WRITE;
Q40_RTC_CTRL |= Q40_RTC_WRITE;
Q40_RTC_CTRL = tmp;
Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
return 0;
} else
return -EINVAL;
}
#define PCIDE_BASE1 0x1f0
#define PCIDE_BASE2 0x170
#define PCIDE_CTL 0x206
static const struct resource q40_pata_rsrc_0[] __initconst = {
DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38),
DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2),
DEFINE_RES_IO(PCIDE_BASE1, 8),
DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1),
DEFINE_RES_IRQ(14),
};
static const struct resource q40_pata_rsrc_1[] __initconst = {
DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38),
DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2),
DEFINE_RES_IO(PCIDE_BASE2, 8),
DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1),
DEFINE_RES_IRQ(15),
};
static __init int q40_platform_init(void)
{
if (!MACH_IS_Q40)
return -ENODEV;
platform_device_register_simple("q40kbd", -1, NULL, 0);
platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0,
ARRAY_SIZE(q40_pata_rsrc_0));
platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1,
ARRAY_SIZE(q40_pata_rsrc_1));
return 0;
}
arch_initcall(q40_platform_init);
| linux-master | arch/m68k/q40/config.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <asm/hwtest.h>
#include <asm/irq.h>
#include <asm/irq_regs.h>
#include <asm/processor.h>
#include <asm/virt.h>
#define GFPIC_REG_IRQ_PENDING 0x04
#define GFPIC_REG_IRQ_DISABLE_ALL 0x08
#define GFPIC_REG_IRQ_DISABLE 0x0c
#define GFPIC_REG_IRQ_ENABLE 0x10
static struct resource picres[6];
static const char *picname[6] = {
"goldfish_pic.0",
"goldfish_pic.1",
"goldfish_pic.2",
"goldfish_pic.3",
"goldfish_pic.4",
"goldfish_pic.5"
};
/*
* 6 goldfish-pic for CPU IRQ #1 to IRQ #6
* CPU IRQ #1 -> PIC #1
* IRQ #1 to IRQ #31 -> unused
* IRQ #32 -> goldfish-tty
* CPU IRQ #2 -> PIC #2
* IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32
* CPU IRQ #3 -> PIC #3
* IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64
* CPU IRQ #4 -> PIC #4
* IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96
* CPU IRQ #5 -> PIC #5
* IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128
* CPU IRQ #6 -> PIC #6
* IRQ #1 -> goldfish-timer
* IRQ #2 -> goldfish-rtc
* IRQ #3 to IRQ #32 -> unused
* CPU IRQ #7 -> NMI
*/
static u32 gfpic_read(int pic, int reg)
{
void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
pic * 0x1000);
return ioread32be(base + reg);
}
static void gfpic_write(u32 value, int pic, int reg)
{
void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
pic * 0x1000);
iowrite32be(value, base + reg);
}
#define GF_PIC(irq) ((irq - IRQ_USER) / 32)
#define GF_IRQ(irq) ((irq - IRQ_USER) % 32)
static void virt_irq_enable(struct irq_data *data)
{
gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq),
GFPIC_REG_IRQ_ENABLE);
}
static void virt_irq_disable(struct irq_data *data)
{
gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq),
GFPIC_REG_IRQ_DISABLE);
}
static unsigned int virt_irq_startup(struct irq_data *data)
{
virt_irq_enable(data);
return 0;
}
static irqreturn_t virt_nmi_handler(int irq, void *dev_id)
{
static int in_nmi;
if (READ_ONCE(in_nmi))
return IRQ_HANDLED;
WRITE_ONCE(in_nmi, 1);
pr_warn("Non-Maskable Interrupt\n");
show_registers(get_irq_regs());
WRITE_ONCE(in_nmi, 0);
return IRQ_HANDLED;
}
static struct irq_chip virt_irq_chip = {
.name = "virt",
.irq_enable = virt_irq_enable,
.irq_disable = virt_irq_disable,
.irq_startup = virt_irq_startup,
.irq_shutdown = virt_irq_disable,
};
static void goldfish_pic_irq(struct irq_desc *desc)
{
u32 irq_pending;
unsigned int irq_num;
unsigned int pic = desc->irq_data.irq - 1;
irq_pending = gfpic_read(pic, GFPIC_REG_IRQ_PENDING);
irq_num = IRQ_USER + pic * 32;
do {
if (irq_pending & 1)
generic_handle_irq(irq_num);
++irq_num;
irq_pending >>= 1;
} while (irq_pending);
}
void __init virt_init_IRQ(void)
{
unsigned int i;
m68k_setup_irq_controller(&virt_irq_chip, handle_simple_irq, IRQ_USER,
NUM_VIRT_SOURCES - IRQ_USER);
for (i = 0; i < 6; i++) {
picres[i] = (struct resource)
DEFINE_RES_MEM_NAMED(virt_bi_data.pic.mmio + i * 0x1000,
0x1000, picname[i]);
if (request_resource(&iomem_resource, &picres[i])) {
pr_err("Cannot allocate %s resource\n", picname[i]);
return;
}
irq_set_chained_handler(virt_bi_data.pic.irq + i,
goldfish_pic_irq);
}
if (request_irq(IRQ_AUTO_7, virt_nmi_handler, 0, "NMI",
virt_nmi_handler))
pr_err("Couldn't register NMI\n");
}
| linux-master | arch/m68k/virt/ints.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/memblock.h>
#include <asm/virt.h>
#include <asm/irq.h>
#define VIRTIO_BUS_NB 128
static struct platform_device * __init virt_virtio_init(unsigned int id)
{
const struct resource res[] = {
DEFINE_RES_MEM(virt_bi_data.virtio.mmio + id * 0x200, 0x200),
DEFINE_RES_IRQ(virt_bi_data.virtio.irq + id),
};
return platform_device_register_simple("virtio-mmio", id,
res, ARRAY_SIZE(res));
}
static int __init virt_platform_init(void)
{
const struct resource goldfish_tty_res[] = {
DEFINE_RES_MEM(virt_bi_data.tty.mmio, 1),
DEFINE_RES_IRQ(virt_bi_data.tty.irq),
};
/* this is the second gf-rtc, the first one is used by the scheduler */
const struct resource goldfish_rtc_res[] = {
DEFINE_RES_MEM(virt_bi_data.rtc.mmio + 0x1000, 0x1000),
DEFINE_RES_IRQ(virt_bi_data.rtc.irq + 1),
};
struct platform_device *pdev1, *pdev2;
struct platform_device *pdevs[VIRTIO_BUS_NB];
unsigned int i;
int ret = 0;
if (!MACH_IS_VIRT)
return -ENODEV;
/* We need this to have DMA'able memory provided to goldfish-tty */
min_low_pfn = 0;
pdev1 = platform_device_register_simple("goldfish_tty",
PLATFORM_DEVID_NONE,
goldfish_tty_res,
ARRAY_SIZE(goldfish_tty_res));
if (IS_ERR(pdev1))
return PTR_ERR(pdev1);
pdev2 = platform_device_register_simple("goldfish_rtc",
PLATFORM_DEVID_NONE,
goldfish_rtc_res,
ARRAY_SIZE(goldfish_rtc_res));
if (IS_ERR(pdev2)) {
ret = PTR_ERR(pdev2);
goto err_unregister_tty;
}
for (i = 0; i < VIRTIO_BUS_NB; i++) {
pdevs[i] = virt_virtio_init(i);
if (IS_ERR(pdevs[i])) {
ret = PTR_ERR(pdevs[i]);
goto err_unregister_rtc_virtio;
}
}
return 0;
err_unregister_rtc_virtio:
while (i > 0)
platform_device_unregister(pdevs[--i]);
platform_device_unregister(pdev2);
err_unregister_tty:
platform_device_unregister(pdev1);
return ret;
}
arch_initcall(virt_platform_init);
| linux-master | arch/m68k/virt/platform.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/reboot.h>
#include <linux/serial_core.h>
#include <clocksource/timer-goldfish.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-virt.h>
#include <asm/byteorder.h>
#include <asm/machdep.h>
#include <asm/virt.h>
#include <asm/config.h>
struct virt_booter_data virt_bi_data;
#define VIRT_CTRL_REG_FEATURES 0x00
#define VIRT_CTRL_REG_CMD 0x04
static struct resource ctrlres;
enum {
CMD_NOOP,
CMD_RESET,
CMD_HALT,
CMD_PANIC,
};
static void virt_get_model(char *str)
{
/* str is 80 characters long */
sprintf(str, "QEMU Virtual M68K Machine (%u.%u.%u)",
(u8)(virt_bi_data.qemu_version >> 24),
(u8)(virt_bi_data.qemu_version >> 16),
(u8)(virt_bi_data.qemu_version >> 8));
}
static void virt_halt(void)
{
void __iomem *base = (void __iomem *)virt_bi_data.ctrl.mmio;
iowrite32be(CMD_HALT, base + VIRT_CTRL_REG_CMD);
local_irq_disable();
while (1)
;
}
static void virt_reset(void)
{
void __iomem *base = (void __iomem *)virt_bi_data.ctrl.mmio;
iowrite32be(CMD_RESET, base + VIRT_CTRL_REG_CMD);
local_irq_disable();
while (1)
;
}
/*
* Parse a virtual-m68k-specific record in the bootinfo
*/
int __init virt_parse_bootinfo(const struct bi_record *record)
{
int unknown = 0;
const void *data = record->data;
switch (be16_to_cpu(record->tag)) {
case BI_VIRT_QEMU_VERSION:
virt_bi_data.qemu_version = be32_to_cpup(data);
break;
case BI_VIRT_GF_PIC_BASE:
virt_bi_data.pic.mmio = be32_to_cpup(data);
data += 4;
virt_bi_data.pic.irq = be32_to_cpup(data);
break;
case BI_VIRT_GF_RTC_BASE:
virt_bi_data.rtc.mmio = be32_to_cpup(data);
data += 4;
virt_bi_data.rtc.irq = be32_to_cpup(data);
break;
case BI_VIRT_GF_TTY_BASE:
virt_bi_data.tty.mmio = be32_to_cpup(data);
data += 4;
virt_bi_data.tty.irq = be32_to_cpup(data);
break;
case BI_VIRT_CTRL_BASE:
virt_bi_data.ctrl.mmio = be32_to_cpup(data);
data += 4;
virt_bi_data.ctrl.irq = be32_to_cpup(data);
break;
case BI_VIRT_VIRTIO_BASE:
virt_bi_data.virtio.mmio = be32_to_cpup(data);
data += 4;
virt_bi_data.virtio.irq = be32_to_cpup(data);
break;
default:
unknown = 1;
break;
}
return unknown;
}
static void __init virt_sched_init(void)
{
goldfish_timer_init(virt_bi_data.rtc.irq,
(void __iomem *)virt_bi_data.rtc.mmio);
}
void __init config_virt(void)
{
char earlycon[24];
snprintf(earlycon, sizeof(earlycon), "early_gf_tty,0x%08x",
virt_bi_data.tty.mmio);
setup_earlycon(earlycon);
ctrlres = (struct resource)
DEFINE_RES_MEM_NAMED(virt_bi_data.ctrl.mmio, 0x100,
"virtctrl");
if (request_resource(&iomem_resource, &ctrlres)) {
pr_err("Cannot allocate virt controller resource\n");
return;
}
mach_init_IRQ = virt_init_IRQ;
mach_sched_init = virt_sched_init;
mach_get_model = virt_get_model;
mach_reset = virt_reset;
mach_halt = virt_halt;
register_platform_power_off(virt_halt);
}
| linux-master | arch/m68k/virt/config.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Mac bong noise generator. Note - we ought to put a boingy noise
* here 8)
*
* ----------------------------------------------------------------------
* 16.11.98:
* rewrote some functions, added support for Enhanced ASC (Quadras)
* after the NetBSD asc.c console bell patch by Colin Wood/Frederick Bruck
* Juergen Mellinger ([email protected])
*/
#include <linux/sched.h>
#include <linux/timer.h>
#include <asm/macintosh.h>
#include <asm/mac_asc.h>
static int mac_asc_inited;
/*
* dumb triangular wave table
*/
static __u8 mac_asc_wave_tab[ 0x800 ];
/*
* Alan's original sine table; needs interpolating to 0x800
* (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
*/
static const signed char sine_data[] = {
0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
0, -39, -75, -103, -121, -127, -121, -103, -75, -39
};
/*
* where the ASC hides ...
*/
static volatile __u8* mac_asc_regs = ( void* )0x50F14000;
/*
* sample rate; is this a good default value?
*/
static unsigned long mac_asc_samplespersec = 11050;
static int mac_bell_duration;
static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
static unsigned long mac_bell_phasepersample;
/*
* some function protos
*/
static void mac_init_asc( void );
static void mac_nosound(struct timer_list *);
static void mac_quadra_start_bell( unsigned int, unsigned int, unsigned int );
static void mac_quadra_ring_bell(struct timer_list *);
static void mac_av_start_bell( unsigned int, unsigned int, unsigned int );
static void ( *mac_special_bell )( unsigned int, unsigned int, unsigned int );
/*
* our timer to start/continue/stop the bell
*/
static DEFINE_TIMER(mac_sound_timer, mac_nosound);
/*
* Sort of initialize the sound chip (called from mac_mksound on the first
* beep).
*/
static void mac_init_asc( void )
{
int i;
/*
* do some machine specific initialization
* BTW:
* the NetBSD Quadra patch identifies the Enhanced Apple Sound Chip via
* mac_asc_regs[ 0x800 ] & 0xF0 != 0
* this makes no sense here, because we have to set the default sample
* rate anyway if we want correct frequencies
*/
switch ( macintosh_config->ident )
{
case MAC_MODEL_IIFX:
/*
* The IIfx is always special ...
*/
mac_asc_regs = ( void* )0x50010000;
break;
/*
* not sure about how correct this list is
* machines with the EASC enhanced apple sound chip
*/
case MAC_MODEL_Q630:
case MAC_MODEL_P475:
mac_special_bell = mac_quadra_start_bell;
mac_asc_samplespersec = 22150;
break;
case MAC_MODEL_C660:
case MAC_MODEL_Q840:
/*
* The Quadra 660AV and 840AV use the "Singer" custom ASIC for sound I/O.
* It appears to be similar to the "AWACS" custom ASIC in the Power Mac
* [678]100. Because Singer and AWACS may have a similar hardware
* interface, this would imply that the code in drivers/sound/dmasound.c
* for AWACS could be used as a basis for Singer support. All we have to
* do is figure out how to do DMA on the 660AV/840AV through the PSC and
* figure out where the Singer hardware sits in memory. (I'd look in the
* vicinity of the AWACS location in a Power Mac [678]100 first, or the
* current location of the Apple Sound Chip--ASC--in other Macs.) The
* Power Mac [678]100 info can be found in MkLinux Mach kernel sources.
*
* Quoted from Apple's Tech Info Library, article number 16405:
* "Among desktop Macintosh computers, only the 660AV, 840AV, and Power
* Macintosh models have 16-bit audio input and output capability
* because of the AT&T DSP3210 hardware circuitry and the 16-bit Singer
* codec circuitry in the AVs. The Audio Waveform Amplifier and
* Converter (AWAC) chip in the Power Macintosh performs the same
* 16-bit I/O functionality. The PowerBook 500 series computers
* support 16-bit stereo output, but only mono input."
*
* Technical Information Library (TIL) article number 16405.
* https://support.apple.com/kb/TA32601
*
* --David Kilzer
*/
mac_special_bell = mac_av_start_bell;
break;
case MAC_MODEL_Q650:
case MAC_MODEL_Q700:
case MAC_MODEL_Q800:
case MAC_MODEL_Q900:
case MAC_MODEL_Q950:
/*
* Currently not implemented!
*/
mac_special_bell = NULL;
break;
default:
/*
* Every switch needs a default
*/
mac_special_bell = NULL;
break;
}
/*
* init the wave table with a simple triangular wave
* A sine wave would sure be nicer here ...
*/
for ( i = 0; i < 0x400; i++ )
{
mac_asc_wave_tab[ i ] = i / 4;
mac_asc_wave_tab[ i + 0x400 ] = 0xFF - i / 4;
}
mac_asc_inited = 1;
}
/*
* Called to make noise; current single entry to the boing driver.
* Does the job for simple ASC, calls other routines else.
* XXX Fixme:
* Should be split into asc_mksound, easc_mksound, av_mksound and
* function pointer set in mac_init_asc which would be called at
* init time.
* _This_ is rather ugly ...
*/
void mac_mksound( unsigned int freq, unsigned int length )
{
__u32 cfreq = ( freq << 5 ) / 468;
unsigned long flags;
int i;
if ( mac_special_bell == NULL )
{
/* Do nothing */
return;
}
if ( !mac_asc_inited )
mac_init_asc();
if ( mac_special_bell )
{
mac_special_bell( freq, length, 128 );
return;
}
if ( freq < 20 || freq > 20000 || length == 0 )
{
mac_nosound( 0 );
return;
}
local_irq_save(flags);
del_timer( &mac_sound_timer );
for ( i = 0; i < 0x800; i++ )
mac_asc_regs[ i ] = 0;
for ( i = 0; i < 0x800; i++ )
mac_asc_regs[ i ] = mac_asc_wave_tab[ i ];
for ( i = 0; i < 8; i++ )
*( __u32* )( ( __u32 )mac_asc_regs + ASC_CONTROL + 0x814 + 8 * i ) = cfreq;
mac_asc_regs[ 0x807 ] = 0;
mac_asc_regs[ ASC_VOLUME ] = 128;
mac_asc_regs[ 0x805 ] = 0;
mac_asc_regs[ 0x80F ] = 0;
mac_asc_regs[ ASC_MODE ] = ASC_MODE_SAMPLE;
mac_asc_regs[ ASC_ENABLE ] = ASC_ENABLE_SAMPLE;
mac_sound_timer.expires = jiffies + length;
add_timer( &mac_sound_timer );
local_irq_restore(flags);
}
/*
* regular ASC: stop whining ..
*/
static void mac_nosound(struct timer_list *unused)
{
mac_asc_regs[ ASC_ENABLE ] = 0;
}
/*
* EASC entry; init EASC, don't load wavetable, schedule 'start whining'.
*/
static void mac_quadra_start_bell( unsigned int freq, unsigned int length, unsigned int volume )
{
unsigned long flags;
/* if the bell is already ringing, ring longer */
if ( mac_bell_duration > 0 )
{
mac_bell_duration += length;
return;
}
mac_bell_duration = length;
mac_bell_phase = 0;
mac_bell_phasepersample = ( freq * sizeof( mac_asc_wave_tab ) ) / mac_asc_samplespersec;
/* this is reasonably big for small frequencies */
local_irq_save(flags);
/* set the volume */
mac_asc_regs[ 0x806 ] = volume;
/* set up the ASC registers */
if ( mac_asc_regs[ 0x801 ] != 1 )
{
/* select mono mode */
mac_asc_regs[ 0x807 ] = 0;
/* select sampled sound mode */
mac_asc_regs[ 0x802 ] = 0;
/* ??? */
mac_asc_regs[ 0x801 ] = 1;
mac_asc_regs[ 0x803 ] |= 0x80;
mac_asc_regs[ 0x803 ] &= 0x7F;
}
mac_sound_timer.function = mac_quadra_ring_bell;
mac_sound_timer.expires = jiffies + 1;
add_timer( &mac_sound_timer );
local_irq_restore(flags);
}
/*
* EASC 'start/continue whining'; I'm not sure why the above function didn't
* already load the wave table, or at least call this one...
* This piece keeps reloading the wave table until done.
*/
static void mac_quadra_ring_bell(struct timer_list *unused)
{
int i, count = mac_asc_samplespersec / HZ;
unsigned long flags;
/*
* we neither want a sound buffer overflow nor underflow, so we need to match
* the number of samples per timer interrupt as exactly as possible.
* using the asc interrupt will give better results in the future
* ...and the possibility to use a real sample (a boingy noise, maybe...)
*/
local_irq_save(flags);
del_timer( &mac_sound_timer );
if ( mac_bell_duration-- > 0 )
{
for ( i = 0; i < count; i++ )
{
mac_bell_phase += mac_bell_phasepersample;
mac_asc_regs[ 0 ] = mac_asc_wave_tab[ mac_bell_phase & ( sizeof( mac_asc_wave_tab ) - 1 ) ];
}
mac_sound_timer.expires = jiffies + 1;
add_timer( &mac_sound_timer );
}
else
mac_asc_regs[ 0x801 ] = 0;
local_irq_restore(flags);
}
/*
* AV code - please fill in.
*/
static void mac_av_start_bell( unsigned int freq, unsigned int length, unsigned int volume )
{
}
| linux-master | arch/m68k/mac/macboing.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Macintosh interrupts
*
* General design:
* In contrary to the Amiga and Atari platforms, the Mac hardware seems to
* exclusively use the autovector interrupts (the 'generic level0-level7'
* interrupts with exception vectors 0x19-0x1f). The following interrupt levels
* are used:
* 1 - VIA1
* - slot 0: one second interrupt (CA2)
* - slot 1: VBlank (CA1)
* - slot 2: ADB data ready (SR full)
* - slot 3: ADB data (CB2)
* - slot 4: ADB clock (CB1)
* - slot 5: timer 2
* - slot 6: timer 1
* - slot 7: status of IRQ; signals 'any enabled int.'
*
* 2 - VIA2 or RBV
* - slot 0: SCSI DRQ (CA2)
* - slot 1: NUBUS IRQ (CA1) need to read port A to find which
* - slot 2: /EXP IRQ (only on IIci)
* - slot 3: SCSI IRQ (CB2)
* - slot 4: ASC IRQ (CB1)
* - slot 5: timer 2 (not on IIci)
* - slot 6: timer 1 (not on IIci)
* - slot 7: status of IRQ; signals 'any enabled int.'
*
* Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
*
* 3 - unused (?)
*
* 4 - SCC
*
* 5 - unused (?)
* [serial errors or special conditions seem to raise level 6
* interrupts on some models (LC4xx?)]
*
* 6 - off switch (?)
*
* Machines with Quadra-like VIA hardware, except PSC and PMU machines, support
* an alternate interrupt mapping, as used by A/UX. It spreads ethernet and
* sound out to their own autovector IRQs and gives VIA1 a higher priority:
*
* 1 - unused (?)
*
* 3 - on-board SONIC
*
* 5 - Apple Sound Chip (ASC)
*
* 6 - VIA1
*
* For OSS Macintoshes (IIfx only), we apply an interrupt mapping similar to
* the Quadra (A/UX) mapping:
*
* 1 - ISM IOP (ADB)
*
* 2 - SCSI
*
* 3 - NuBus
*
* 4 - SCC IOP
*
* 6 - VIA1
*
* For PSC Macintoshes (660AV, 840AV):
*
* 3 - PSC level 3
* - slot 0: MACE
*
* 4 - PSC level 4
* - slot 1: SCC channel A interrupt
* - slot 2: SCC channel B interrupt
* - slot 3: MACE DMA
*
* 5 - PSC level 5
*
* 6 - PSC level 6
*
* Finally we have good 'ole level 7, the non-maskable interrupt:
*
* 7 - NMI (programmer's switch on the back of some Macs)
* Also RAM parity error on models which support it (IIc, IIfx?)
*
* The current interrupt logic looks something like this:
*
* - We install dispatchers for the autovector interrupts (1-7). These
* dispatchers are responsible for querying the hardware (the
* VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
* this information a machspec interrupt number is generated by placing the
* index of the interrupt hardware into the low three bits and the original
* autovector interrupt number in the upper 5 bits. The handlers for the
* resulting machspec interrupt are then called.
*
* - Nubus is a special case because its interrupts are hidden behind two
* layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
* which translates to IRQ number 17. In this spot we install _another_
* dispatcher. This dispatcher finds the interrupting slot number (9-F) and
* then forms a new machspec interrupt number as above with the slot number
* minus 9 in the low three bits and the pseudo-level 7 in the upper five
* bits. The handlers for this new machspec interrupt number are then
* called. This puts Nubus interrupts into the range 56-62.
*
* - The Baboon interrupts (used on some PowerBooks) are an even more special
* case. They're hidden behind the Nubus slot $C interrupt thus adding a
* third layer of indirection. Why oh why did the Apple engineers do that?
*
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/irq.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_via.h>
#include <asm/mac_psc.h>
#include <asm/mac_oss.h>
#include <asm/mac_iop.h>
#include <asm/mac_baboon.h>
#include <asm/hwtest.h>
#include <asm/irq_regs.h>
#include <asm/processor.h>
static unsigned int mac_irq_startup(struct irq_data *);
static void mac_irq_shutdown(struct irq_data *);
static struct irq_chip mac_irq_chip = {
.name = "mac",
.irq_enable = mac_irq_enable,
.irq_disable = mac_irq_disable,
.irq_startup = mac_irq_startup,
.irq_shutdown = mac_irq_shutdown,
};
static irqreturn_t mac_nmi_handler(int irq, void *dev_id)
{
static volatile int in_nmi;
if (in_nmi)
return IRQ_HANDLED;
in_nmi = 1;
pr_info("Non-Maskable Interrupt\n");
show_registers(get_irq_regs());
in_nmi = 0;
return IRQ_HANDLED;
}
void __init mac_init_IRQ(void)
{
m68k_setup_irq_controller(&mac_irq_chip, handle_simple_irq, IRQ_USER,
NUM_MAC_SOURCES - IRQ_USER);
/*
* Now register the handlers for the master IRQ handlers
* at levels 1-7. Most of the work is done elsewhere.
*/
if (oss_present)
oss_register_interrupts();
else
via_register_interrupts();
if (psc)
psc_register_interrupts();
if (baboon_present)
baboon_register_interrupts();
iop_register_interrupts();
if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
mac_nmi_handler))
pr_err("Couldn't register NMI\n");
}
/*
* mac_irq_enable - enable an interrupt source
* mac_irq_disable - disable an interrupt source
*
* These routines are just dispatchers to the VIA/OSS/PSC routines.
*/
void mac_irq_enable(struct irq_data *data)
{
int irq = data->irq;
int irq_src = IRQ_SRC(irq);
switch(irq_src) {
case 1:
case 2:
case 7:
if (oss_present)
oss_irq_enable(irq);
else
via_irq_enable(irq);
break;
case 3:
case 4:
case 5:
case 6:
if (psc)
psc_irq_enable(irq);
else if (oss_present)
oss_irq_enable(irq);
break;
case 8:
if (baboon_present)
baboon_irq_enable(irq);
break;
}
}
void mac_irq_disable(struct irq_data *data)
{
int irq = data->irq;
int irq_src = IRQ_SRC(irq);
switch(irq_src) {
case 1:
case 2:
case 7:
if (oss_present)
oss_irq_disable(irq);
else
via_irq_disable(irq);
break;
case 3:
case 4:
case 5:
case 6:
if (psc)
psc_irq_disable(irq);
else if (oss_present)
oss_irq_disable(irq);
break;
case 8:
if (baboon_present)
baboon_irq_disable(irq);
break;
}
}
static unsigned int mac_irq_startup(struct irq_data *data)
{
int irq = data->irq;
if (IRQ_SRC(irq) == 7 && !oss_present)
via_nubus_irq_startup(irq);
else
mac_irq_enable(data);
return 0;
}
static void mac_irq_shutdown(struct irq_data *data)
{
int irq = data->irq;
if (IRQ_SRC(irq) == 7 && !oss_present)
via_nubus_irq_shutdown(irq);
else
mac_irq_disable(data);
}
| linux-master | arch/m68k/mac/macints.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Baboon Custom IC Management
*
* The Baboon custom IC controls the IDE, PCMCIA and media bay on the
* PowerBook 190. It multiplexes multiple interrupt sources onto the
* Nubus slot $C interrupt.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/irq.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_baboon.h>
int baboon_present;
static volatile struct baboon *baboon;
/*
* Baboon initialization.
*/
void __init baboon_init(void)
{
if (macintosh_config->ident != MAC_MODEL_PB190) {
baboon = NULL;
baboon_present = 0;
return;
}
baboon = (struct baboon *) BABOON_BASE;
baboon_present = 1;
pr_debug("Baboon detected at %p\n", baboon);
}
/*
* Baboon interrupt handler.
* XXX how do you clear a pending IRQ? is it even necessary?
*/
static void baboon_irq(struct irq_desc *desc)
{
short events, irq_bit;
int irq_num;
events = baboon->mb_ifr & 0x07;
irq_num = IRQ_BABOON_0;
irq_bit = 1;
do {
if (events & irq_bit) {
events &= ~irq_bit;
generic_handle_irq(irq_num);
}
++irq_num;
irq_bit <<= 1;
} while (events);
}
/*
* Register the Baboon interrupt dispatcher on nubus slot $C.
*/
void __init baboon_register_interrupts(void)
{
irq_set_chained_handler(IRQ_NUBUS_C, baboon_irq);
}
/*
* The means for masking individual Baboon interrupts remains a mystery.
* However, since we only use the IDE IRQ, we can just enable/disable all
* Baboon interrupts. If/when we handle more than one Baboon IRQ, we must
* either figure out how to mask them individually or else implement the
* same workaround that's used for NuBus slots (see nubus_disabled and
* via_nubus_irq_shutdown).
*/
void baboon_irq_enable(int irq)
{
mac_irq_enable(irq_get_irq_data(IRQ_NUBUS_C));
}
void baboon_irq_disable(int irq)
{
mac_irq_disable(irq_get_irq_data(IRQ_NUBUS_C));
}
| linux-master | arch/m68k/mac/baboon.c |
// SPDX-License-Identifier: GPL-2.0
/*
* 6522 Versatile Interface Adapter (VIA)
*
* There are two of these on the Mac II. Some IRQs are vectored
* via them as are assorted bits and bobs - eg RTC, ADB.
*
* CSA: Motorola seems to have removed documentation on the 6522 from
* their web site; try
* http://nerini.drf.com/vectrex/other/text/chips/6522/
* http://www.zymurgy.net/classic/vic20/vicdet1.htm
* and
* http://193.23.168.87/mikro_laborversuche/via_iobaustein/via6522_1.html
* for info. A full-text web search on 6522 AND VIA will probably also
* net some usefulness. <[email protected]> 20apr1999
*
* Additional data is here (the SY6522 was used in the Mac II etc):
* http://www.6502.org/documents/datasheets/synertek/synertek_sy6522.pdf
* http://www.6502.org/documents/datasheets/synertek/synertek_sy6522_programming_reference.pdf
*
* PRAM/RTC access algorithms are from the NetBSD RTC toolkit version 1.08b
* by Erik Vogan and adapted to Linux by Joshua M. Thompson ([email protected])
*
*/
#include <linux/clocksource.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_via.h>
#include <asm/mac_psc.h>
#include <asm/mac_oss.h>
volatile __u8 *via1, *via2;
int rbv_present;
int via_alt_mapping;
EXPORT_SYMBOL(via_alt_mapping);
static __u8 rbv_clear;
/*
* Globals for accessing the VIA chip registers without having to
* check if we're hitting a real VIA or an RBV. Normally you could
* just hit the combined register (ie, vIER|rIER) but that seems to
* break on AV Macs...probably because they actually decode more than
* eight address bits. Why can't Apple engineers at least be
* _consistently_ lazy? - 1999-05-21 (jmt)
*/
static int gIER,gIFR,gBufA,gBufB;
/*
* On Macs with a genuine VIA chip there is no way to mask an individual slot
* interrupt. This limitation also seems to apply to VIA clone logic cores in
* Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)
*
* We used to fake it by configuring the relevant VIA pin as an output
* (to mask the interrupt) or input (to unmask). That scheme did not work on
* (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector
* circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,
* p. 10-11 etc) but VIA outputs are not (see datasheet).
*
* Driving these outputs high must cause the VIA to source current and the
* card to sink current when it asserts /NMRQ. Current will flow but the pin
* voltage is uncertain and so the /NMRQ condition may still cause a transition
* at the VIA2 CA1 input (which explains the lost interrupts). A side effect
* is that a disabled slot IRQ can never be tested as pending or not.
*
* Driving these outputs low doesn't work either. All the slot /NMRQ lines are
* (active low) OR'd together to generate the CA1 (aka "SLOTS") interrupt (see
* The Guide To Macintosh Family Hardware, 2nd edition p. 167). If we drive a
* disabled /NMRQ line low, the falling edge immediately triggers a CA1
* interrupt and all slot interrupts after that will generate no transition
* and therefore no interrupt, even after being re-enabled.
*
* So we make the VIA port A I/O lines inputs and use nubus_disabled to keep
* track of their states. When any slot IRQ becomes disabled we mask the CA1
* umbrella interrupt. Only when all slot IRQs become enabled do we unmask
* the CA1 interrupt. It must remain enabled even when cards have no interrupt
* handler registered. Drivers must therefore disable a slot interrupt at the
* device before they call free_irq (like shared and autovector interrupts).
*
* There is also a related problem when MacOS is used to boot Linux. A network
* card brought up by a MacOS driver may raise an interrupt while Linux boots.
* This can be fatal since it can't be handled until the right driver loads
* (if such a driver exists at all). Apparently related to this hardware
* limitation, "Designing Cards and Drivers", p. 9-8, says that a slot
* interrupt with no driver would crash MacOS (the book was written before
* the appearance of Macs with RBV or OSS).
*/
static u8 nubus_disabled;
void via_debug_dump(void);
static void via_nubus_init(void);
/*
* Initialize the VIAs
*
* First we figure out where they actually _are_ as well as what type of
* VIA we have for VIA2 (it could be a real VIA or an RBV or even an OSS.)
* Then we pretty much clear them out and disable all IRQ sources.
*/
void __init via_init(void)
{
via1 = (void *)VIA1_BASE;
pr_debug("VIA1 detected at %p\n", via1);
if (oss_present) {
via2 = NULL;
rbv_present = 0;
} else {
switch (macintosh_config->via_type) {
/* IIci, IIsi, IIvx, IIvi (P6xx), LC series */
case MAC_VIA_IICI:
via2 = (void *)RBV_BASE;
pr_debug("VIA2 (RBV) detected at %p\n", via2);
rbv_present = 1;
if (macintosh_config->ident == MAC_MODEL_LCIII) {
rbv_clear = 0x00;
} else {
/* on most RBVs (& unlike the VIAs), you */
/* need to set bit 7 when you write to IFR */
/* in order for your clear to occur. */
rbv_clear = 0x80;
}
gIER = rIER;
gIFR = rIFR;
gBufA = rSIFR;
gBufB = rBufB;
break;
/* Quadra and early MacIIs agree on the VIA locations */
case MAC_VIA_QUADRA:
case MAC_VIA_II:
via2 = (void *) VIA2_BASE;
pr_debug("VIA2 detected at %p\n", via2);
rbv_present = 0;
rbv_clear = 0x00;
gIER = vIER;
gIFR = vIFR;
gBufA = vBufA;
gBufB = vBufB;
break;
default:
panic("UNKNOWN VIA TYPE");
}
}
#ifdef DEBUG_VIA
via_debug_dump();
#endif
/*
* Shut down all IRQ sources, reset the timers, and
* kill the timer latch on VIA1.
*/
via1[vIER] = 0x7F;
via1[vIFR] = 0x7F;
via1[vT1CL] = 0;
via1[vT1CH] = 0;
via1[vT2CL] = 0;
via1[vT2CH] = 0;
via1[vACR] &= ~0xC0; /* setup T1 timer with no PB7 output */
via1[vACR] &= ~0x03; /* disable port A & B latches */
/*
* SE/30: disable video IRQ
*/
if (macintosh_config->ident == MAC_MODEL_SE30) {
via1[vDirB] |= 0x40;
via1[vBufB] |= 0x40;
}
switch (macintosh_config->adb_type) {
case MAC_ADB_IOP:
case MAC_ADB_II:
case MAC_ADB_PB1:
/*
* Set the RTC bits to a known state: all lines to outputs and
* RTC disabled (yes that's 0 to enable and 1 to disable).
*/
via1[vDirB] |= VIA1B_vRTCEnb | VIA1B_vRTCClk | VIA1B_vRTCData;
via1[vBufB] |= VIA1B_vRTCEnb | VIA1B_vRTCClk;
break;
}
/* Everything below this point is VIA2/RBV only... */
if (oss_present)
return;
if ((macintosh_config->via_type == MAC_VIA_QUADRA) &&
(macintosh_config->adb_type != MAC_ADB_PB1) &&
(macintosh_config->adb_type != MAC_ADB_PB2) &&
(macintosh_config->ident != MAC_MODEL_C660) &&
(macintosh_config->ident != MAC_MODEL_Q840)) {
via_alt_mapping = 1;
via1[vDirB] |= 0x40;
via1[vBufB] &= ~0x40;
} else {
via_alt_mapping = 0;
}
/*
* Now initialize VIA2. For RBV we just kill all interrupts;
* for a regular VIA we also reset the timers and stuff.
*/
via2[gIER] = 0x7F;
via2[gIFR] = 0x7F | rbv_clear;
if (!rbv_present) {
via2[vT1CL] = 0;
via2[vT1CH] = 0;
via2[vT2CL] = 0;
via2[vT2CH] = 0;
via2[vACR] &= ~0xC0; /* setup T1 timer with no PB7 output */
via2[vACR] &= ~0x03; /* disable port A & B latches */
}
via_nubus_init();
/* Everything below this point is VIA2 only... */
if (rbv_present)
return;
/*
* Set vPCR for control line interrupts.
*
* CA1 (SLOTS IRQ), CB1 (ASC IRQ): negative edge trigger.
*
* Macs with ESP SCSI have a negative edge triggered SCSI interrupt.
* Testing reveals that PowerBooks do too. However, the SE/30
* schematic diagram shows an active high NCR5380 IRQ line.
*/
pr_debug("VIA2 vPCR is 0x%02X\n", via2[vPCR]);
if (macintosh_config->via_type == MAC_VIA_II) {
/* CA2 (SCSI DRQ), CB2 (SCSI IRQ): indep. input, pos. edge */
via2[vPCR] = 0x66;
} else {
/* CA2 (SCSI DRQ), CB2 (SCSI IRQ): indep. input, neg. edge */
via2[vPCR] = 0x22;
}
}
/*
* Debugging dump, used in various places to see what's going on.
*/
void via_debug_dump(void)
{
printk(KERN_DEBUG "VIA1: DDRA = 0x%02X DDRB = 0x%02X ACR = 0x%02X\n",
(uint) via1[vDirA], (uint) via1[vDirB], (uint) via1[vACR]);
printk(KERN_DEBUG " PCR = 0x%02X IFR = 0x%02X IER = 0x%02X\n",
(uint) via1[vPCR], (uint) via1[vIFR], (uint) via1[vIER]);
if (!via2)
return;
if (rbv_present) {
printk(KERN_DEBUG "VIA2: IFR = 0x%02X IER = 0x%02X\n",
(uint) via2[rIFR], (uint) via2[rIER]);
printk(KERN_DEBUG " SIFR = 0x%02X SIER = 0x%02X\n",
(uint) via2[rSIFR], (uint) via2[rSIER]);
} else {
printk(KERN_DEBUG "VIA2: DDRA = 0x%02X DDRB = 0x%02X ACR = 0x%02X\n",
(uint) via2[vDirA], (uint) via2[vDirB],
(uint) via2[vACR]);
printk(KERN_DEBUG " PCR = 0x%02X IFR = 0x%02X IER = 0x%02X\n",
(uint) via2[vPCR],
(uint) via2[vIFR], (uint) via2[vIER]);
}
}
/*
* Flush the L2 cache on Macs that have it by flipping
* the system into 24-bit mode for an instant.
*/
void via_l2_flush(int writeback)
{
unsigned long flags;
local_irq_save(flags);
via2[gBufB] &= ~VIA2B_vMode32;
via2[gBufB] |= VIA2B_vMode32;
local_irq_restore(flags);
}
/*
* Initialize VIA2 for Nubus access
*/
static void __init via_nubus_init(void)
{
/* unlock nubus transactions */
if ((macintosh_config->adb_type != MAC_ADB_PB1) &&
(macintosh_config->adb_type != MAC_ADB_PB2)) {
/* set the line to be an output on non-RBV machines */
if (!rbv_present)
via2[vDirB] |= 0x02;
/* this seems to be an ADB bit on PMU machines */
/* according to MkLinux. -- jmt */
via2[gBufB] |= 0x02;
}
/*
* Disable the slot interrupts. On some hardware that's not possible.
* On some hardware it's unclear what all of these I/O lines do.
*/
switch (macintosh_config->via_type) {
case MAC_VIA_II:
case MAC_VIA_QUADRA:
pr_debug("VIA2 vDirA is 0x%02X\n", via2[vDirA]);
break;
case MAC_VIA_IICI:
/* RBV. Disable all the slot interrupts. SIER works like IER. */
via2[rSIER] = 0x7F;
break;
}
}
void via_nubus_irq_startup(int irq)
{
int irq_idx = IRQ_IDX(irq);
switch (macintosh_config->via_type) {
case MAC_VIA_II:
case MAC_VIA_QUADRA:
/* Make the port A line an input. Probably redundant. */
if (macintosh_config->via_type == MAC_VIA_II) {
/* The top two bits are RAM size outputs. */
via2[vDirA] &= 0xC0 | ~(1 << irq_idx);
} else {
/* Allow NuBus slots 9 through F. */
via2[vDirA] &= 0x80 | ~(1 << irq_idx);
}
fallthrough;
case MAC_VIA_IICI:
via_irq_enable(irq);
break;
}
}
void via_nubus_irq_shutdown(int irq)
{
switch (macintosh_config->via_type) {
case MAC_VIA_II:
case MAC_VIA_QUADRA:
/* Ensure that the umbrella CA1 interrupt remains enabled. */
via_irq_enable(irq);
break;
case MAC_VIA_IICI:
via_irq_disable(irq);
break;
}
}
/*
* The generic VIA interrupt routines (shamelessly stolen from Alan Cox's
* via6522.c :-), disable/pending masks added.
*/
#define VIA_TIMER_1_INT BIT(6)
void via1_irq(struct irq_desc *desc)
{
int irq_num;
unsigned char irq_bit, events;
events = via1[vIFR] & via1[vIER] & 0x7F;
if (!events)
return;
irq_num = IRQ_MAC_TIMER_1;
irq_bit = VIA_TIMER_1_INT;
if (events & irq_bit) {
unsigned long flags;
local_irq_save(flags);
via1[vIFR] = irq_bit;
generic_handle_irq(irq_num);
local_irq_restore(flags);
events &= ~irq_bit;
if (!events)
return;
}
irq_num = VIA1_SOURCE_BASE;
irq_bit = 1;
do {
if (events & irq_bit) {
via1[vIFR] = irq_bit;
generic_handle_irq(irq_num);
}
++irq_num;
irq_bit <<= 1;
} while (events >= irq_bit);
}
static void via2_irq(struct irq_desc *desc)
{
int irq_num;
unsigned char irq_bit, events;
events = via2[gIFR] & via2[gIER] & 0x7F;
if (!events)
return;
irq_num = VIA2_SOURCE_BASE;
irq_bit = 1;
do {
if (events & irq_bit) {
via2[gIFR] = irq_bit | rbv_clear;
generic_handle_irq(irq_num);
}
++irq_num;
irq_bit <<= 1;
} while (events >= irq_bit);
}
/*
* Dispatch Nubus interrupts. We are called as a secondary dispatch by the
* VIA2 dispatcher as a fast interrupt handler.
*/
static void via_nubus_irq(struct irq_desc *desc)
{
int slot_irq;
unsigned char slot_bit, events;
events = ~via2[gBufA] & 0x7F;
if (rbv_present)
events &= via2[rSIER];
else
events &= ~via2[vDirA];
if (!events)
return;
do {
slot_irq = IRQ_NUBUS_F;
slot_bit = 0x40;
do {
if (events & slot_bit) {
events &= ~slot_bit;
generic_handle_irq(slot_irq);
}
--slot_irq;
slot_bit >>= 1;
} while (events);
/* clear the CA1 interrupt and make certain there's no more. */
via2[gIFR] = 0x02 | rbv_clear;
events = ~via2[gBufA] & 0x7F;
if (rbv_present)
events &= via2[rSIER];
else
events &= ~via2[vDirA];
} while (events);
}
/*
* Register the interrupt dispatchers for VIA or RBV machines only.
*/
void __init via_register_interrupts(void)
{
if (via_alt_mapping) {
/* software interrupt */
irq_set_chained_handler(IRQ_AUTO_1, via1_irq);
/* via1 interrupt */
irq_set_chained_handler(IRQ_AUTO_6, via1_irq);
} else {
irq_set_chained_handler(IRQ_AUTO_1, via1_irq);
}
irq_set_chained_handler(IRQ_AUTO_2, via2_irq);
irq_set_chained_handler(IRQ_MAC_NUBUS, via_nubus_irq);
}
void via_irq_enable(int irq) {
int irq_src = IRQ_SRC(irq);
int irq_idx = IRQ_IDX(irq);
if (irq_src == 1) {
via1[vIER] = IER_SET_BIT(irq_idx);
} else if (irq_src == 2) {
if (irq != IRQ_MAC_NUBUS || nubus_disabled == 0)
via2[gIER] = IER_SET_BIT(irq_idx);
} else if (irq_src == 7) {
switch (macintosh_config->via_type) {
case MAC_VIA_II:
case MAC_VIA_QUADRA:
nubus_disabled &= ~(1 << irq_idx);
/* Enable the CA1 interrupt when no slot is disabled. */
if (!nubus_disabled)
via2[gIER] = IER_SET_BIT(1);
break;
case MAC_VIA_IICI:
/* On RBV, enable the slot interrupt.
* SIER works like IER.
*/
via2[rSIER] = IER_SET_BIT(irq_idx);
break;
}
}
}
void via_irq_disable(int irq) {
int irq_src = IRQ_SRC(irq);
int irq_idx = IRQ_IDX(irq);
if (irq_src == 1) {
via1[vIER] = IER_CLR_BIT(irq_idx);
} else if (irq_src == 2) {
via2[gIER] = IER_CLR_BIT(irq_idx);
} else if (irq_src == 7) {
switch (macintosh_config->via_type) {
case MAC_VIA_II:
case MAC_VIA_QUADRA:
nubus_disabled |= 1 << irq_idx;
if (nubus_disabled)
via2[gIER] = IER_CLR_BIT(1);
break;
case MAC_VIA_IICI:
via2[rSIER] = IER_CLR_BIT(irq_idx);
break;
}
}
}
void via1_set_head(int head)
{
if (head == 0)
via1[vBufA] &= ~VIA1A_vHeadSel;
else
via1[vBufA] |= VIA1A_vHeadSel;
}
EXPORT_SYMBOL(via1_set_head);
int via2_scsi_drq_pending(void)
{
return via2[gIFR] & (1 << IRQ_IDX(IRQ_MAC_SCSIDRQ));
}
EXPORT_SYMBOL(via2_scsi_drq_pending);
/* timer and clock source */
#define VIA_CLOCK_FREQ 783360 /* VIA "phase 2" clock in Hz */
#define VIA_TIMER_CYCLES (VIA_CLOCK_FREQ / HZ) /* clock cycles per jiffy */
#define VIA_TC (VIA_TIMER_CYCLES - 2) /* including 0 and -1 */
#define VIA_TC_LOW (VIA_TC & 0xFF)
#define VIA_TC_HIGH (VIA_TC >> 8)
static u64 mac_read_clk(struct clocksource *cs);
static struct clocksource mac_clk = {
.name = "via1",
.rating = 250,
.read = mac_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static u32 clk_total, clk_offset;
static irqreturn_t via_timer_handler(int irq, void *dev_id)
{
clk_total += VIA_TIMER_CYCLES;
clk_offset = 0;
legacy_timer_tick(1);
return IRQ_HANDLED;
}
void __init via_init_clock(void)
{
if (request_irq(IRQ_MAC_TIMER_1, via_timer_handler, IRQF_TIMER, "timer",
NULL)) {
pr_err("Couldn't register %s interrupt\n", "timer");
return;
}
via1[vT1CL] = VIA_TC_LOW;
via1[vT1CH] = VIA_TC_HIGH;
via1[vACR] |= 0x40;
clocksource_register_hz(&mac_clk, VIA_CLOCK_FREQ);
}
static u64 mac_read_clk(struct clocksource *cs)
{
unsigned long flags;
u8 count_high;
u16 count;
u32 ticks;
/*
* Timer counter wrap-around is detected with the timer interrupt flag
* but reading the counter low byte (vT1CL) would reset the flag.
* Also, accessing both counter registers is essentially a data race.
* These problems are avoided by ignoring the low byte. Clock accuracy
* is 256 times worse (error can reach 0.327 ms) but CPU overhead is
* reduced by avoiding slow VIA register accesses.
*/
local_irq_save(flags);
count_high = via1[vT1CH];
if (count_high == 0xFF)
count_high = 0;
if (count_high > 0 && (via1[vIFR] & VIA_TIMER_1_INT))
clk_offset = VIA_TIMER_CYCLES;
count = count_high << 8;
ticks = VIA_TIMER_CYCLES - count;
ticks += clk_offset + clk_total;
local_irq_restore(flags);
return ticks;
}
| linux-master | arch/m68k/mac/via.c |
/*
* linux/arch/m68k/mac/config.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/*
* Miscellaneous linux stuff
*/
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/console.h>
#include <linux/interrupt.h>
/* keyb */
#include <linux/random.h>
#include <linux/delay.h>
/* keyb */
#include <linux/init.h>
#include <linux/vt_kern.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/adb.h>
#include <linux/cuda.h>
#include <linux/pmu.h>
#include <linux/rtc.h>
#include <asm/setup.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-mac.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/machw.h>
#include <asm/mac_iop.h>
#include <asm/mac_via.h>
#include <asm/mac_oss.h>
#include <asm/mac_psc.h>
#include <asm/config.h>
/* Mac bootinfo struct */
struct mac_booter_data mac_bi_data;
/* The phys. video addr. - might be bogus on some machines */
static unsigned long mac_orig_videoaddr;
extern int mac_hwclk(int, struct rtc_time *);
extern void iop_init(void);
extern void via_init(void);
extern void via_init_clock(void);
extern void oss_init(void);
extern void psc_init(void);
extern void baboon_init(void);
extern void mac_mksound(unsigned int, unsigned int);
static void mac_get_model(char *str);
static void mac_identify(void);
static void mac_report_hardware(void);
static void __init mac_sched_init(void)
{
via_init_clock();
}
/*
* Parse a Macintosh-specific record in the bootinfo
*/
int __init mac_parse_bootinfo(const struct bi_record *record)
{
int unknown = 0;
const void *data = record->data;
switch (be16_to_cpu(record->tag)) {
case BI_MAC_MODEL:
mac_bi_data.id = be32_to_cpup(data);
break;
case BI_MAC_VADDR:
mac_bi_data.videoaddr = be32_to_cpup(data);
break;
case BI_MAC_VDEPTH:
mac_bi_data.videodepth = be32_to_cpup(data);
break;
case BI_MAC_VROW:
mac_bi_data.videorow = be32_to_cpup(data);
break;
case BI_MAC_VDIM:
mac_bi_data.dimensions = be32_to_cpup(data);
break;
case BI_MAC_VLOGICAL:
mac_orig_videoaddr = be32_to_cpup(data);
mac_bi_data.videological =
VIDEOMEMBASE + (mac_orig_videoaddr & ~VIDEOMEMMASK);
break;
case BI_MAC_SCCBASE:
mac_bi_data.sccbase = be32_to_cpup(data);
break;
case BI_MAC_BTIME:
mac_bi_data.boottime = be32_to_cpup(data);
break;
case BI_MAC_GMTBIAS:
mac_bi_data.gmtbias = be32_to_cpup(data);
break;
case BI_MAC_MEMSIZE:
mac_bi_data.memsize = be32_to_cpup(data);
break;
case BI_MAC_CPUID:
mac_bi_data.cpuid = be32_to_cpup(data);
break;
case BI_MAC_ROMBASE:
mac_bi_data.rombase = be32_to_cpup(data);
break;
default:
unknown = 1;
break;
}
return unknown;
}
void __init config_mac(void)
{
if (!MACH_IS_MAC)
pr_err("ERROR: no Mac, but config_mac() called!!\n");
mach_sched_init = mac_sched_init;
mach_init_IRQ = mac_init_IRQ;
mach_get_model = mac_get_model;
mach_hwclk = mac_hwclk;
mach_reset = mac_reset;
mach_halt = mac_poweroff;
#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
mach_beep = mac_mksound;
#endif
/*
* Determine hardware present
*/
mac_identify();
mac_report_hardware();
/*
* AFAIK only the IIci takes a cache card. The IIfx has onboard
* cache ... someone needs to figure out how to tell if it's on or
* not.
*/
if (macintosh_config->ident == MAC_MODEL_IICI)
mach_l2_flush = via_l2_flush;
register_platform_power_off(mac_poweroff);
}
/*
* Macintosh Table: hardcoded model configuration data.
*
* Much of this was defined by Alan, based on who knows what docs.
* I've added a lot more, and some of that was pure guesswork based
* on hardware pages present on the Mac web site. Possibly wildly
* inaccurate, so look here if a new Mac model won't run. Example: if
* a Mac crashes immediately after the VIA1 registers have been dumped
* to the screen, it probably died attempting to read DirB on a RBV.
* Meaning it should have MAC_VIA_IICI here :-)
*/
struct mac_model *macintosh_config;
EXPORT_SYMBOL(macintosh_config);
static struct mac_model mac_data_table[] = {
/*
* We'll pretend to be a Macintosh II, that's pretty safe.
*/
{
.ident = MAC_MODEL_II,
.name = "Unknown",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_II,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_UNSUPPORTED, /* IWM */
},
/*
* Original Mac II hardware
*/
{
.ident = MAC_MODEL_II,
.name = "II",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_II,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_UNSUPPORTED, /* IWM */
}, {
.ident = MAC_MODEL_IIX,
.name = "IIx",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_II,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_IICX,
.name = "IIcx",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_II,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_SE30,
.name = "SE/30",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_II,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
},
/*
* Weirdified Mac II hardware - all subtly different. Gee thanks
* Apple. All these boxes seem to have VIA2 in a different place to
* the Mac II (+1A000 rather than +4000)
* CSA: see http://developer.apple.com/technotes/hw/hw_09.html
*/
{
.ident = MAC_MODEL_IICI,
.name = "IIci",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_IIFX,
.name = "IIfx",
.adb_type = MAC_ADB_IOP,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_IIFX,
.scc_type = MAC_SCC_IOP,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_SWIM_IOP, /* SWIM */
}, {
.ident = MAC_MODEL_IISI,
.name = "IIsi",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_IIVI,
.name = "IIvi",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM */
}, {
.ident = MAC_MODEL_IIVX,
.name = "IIvx",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM */
},
/*
* Classic models (guessing: similar to SE/30? Nope, similar to LC...)
*/
{
.ident = MAC_MODEL_CLII,
.name = "Classic II",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.floppy_type = MAC_FLOPPY_LC, /* SWIM */
}, {
.ident = MAC_MODEL_CCL,
.name = "Color Classic",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
}, {
.ident = MAC_MODEL_CCLII,
.name = "Color Classic II",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
},
/*
* Some Mac LC machines. Basically the same as the IIci, ADB like IIsi
*/
{
.ident = MAC_MODEL_LC,
.name = "LC",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM */
}, {
.ident = MAC_MODEL_LCII,
.name = "LC II",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM */
}, {
.ident = MAC_MODEL_LCIII,
.name = "LC III",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
},
/*
* Quadra. Video is at 0xF9000000, via is like a MacII. We label it
* differently as some of the stuff connected to VIA2 seems different.
* Better SCSI chip and onboard ethernet using a NatSemi SONIC except
* the 660AV and 840AV which use an AMD 79C940 (MACE).
* The 700, 900 and 950 have some I/O chips in the wrong place to
* confuse us. The 840AV has a SCSI location of its own (same as
* the 660AV).
*/
{
.ident = MAC_MODEL_Q605,
.name = "Quadra 605",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_Q605_ACC,
.name = "Quadra 605",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_Q610,
.name = "Quadra 610",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_Q630,
.name = "Quadra 630",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.ide_type = MAC_IDE_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_PDS_COMM,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_Q650,
.name = "Quadra 650",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
},
/* The Q700 does have a NS Sonic */
{
.ident = MAC_MODEL_Q700,
.name = "Quadra 700",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA2,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM */
}, {
.ident = MAC_MODEL_Q800,
.name = "Quadra 800",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_Q840,
.name = "Quadra 840AV",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA3,
.scc_type = MAC_SCC_PSC,
.ether_type = MAC_ETHER_MACE,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_UNSUPPORTED, /* New Age */
}, {
.ident = MAC_MODEL_Q900,
.name = "Quadra 900",
.adb_type = MAC_ADB_IOP,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA2,
.scc_type = MAC_SCC_IOP,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_SWIM_IOP, /* SWIM */
}, {
.ident = MAC_MODEL_Q950,
.name = "Quadra 950",
.adb_type = MAC_ADB_IOP,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA2,
.scc_type = MAC_SCC_IOP,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_SWIM_IOP, /* SWIM */
},
/*
* Performa - more LC type machines
*/
{
.ident = MAC_MODEL_P460,
.name = "Performa 460",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
}, {
.ident = MAC_MODEL_P475,
.name = "Performa 475",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_P475F,
.name = "Performa 475",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_P520,
.name = "Performa 520",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
}, {
.ident = MAC_MODEL_P550,
.name = "Performa 550",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
},
/* These have the comm slot, and therefore possibly SONIC ethernet */
{
.ident = MAC_MODEL_P575,
.name = "Performa 575",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS_COMM,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_P588,
.name = "Performa 588",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.ide_type = MAC_IDE_QUADRA,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_PDS_COMM,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_TV,
.name = "TV",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.floppy_type = MAC_FLOPPY_LC, /* SWIM 2 */
}, {
.ident = MAC_MODEL_P600,
.name = "Performa 600",
.adb_type = MAC_ADB_EGRET,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_LC,
.scc_type = MAC_SCC_II,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_LC, /* SWIM */
},
/*
* Centris - just guessing again; maybe like Quadra.
* The C610 may or may not have SONIC. We probe to make sure.
*/
{
.ident = MAC_MODEL_C610,
.name = "Centris 610",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_C650,
.name = "Centris 650",
.adb_type = MAC_ADB_II,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_QUADRA, /* SWIM 2 */
}, {
.ident = MAC_MODEL_C660,
.name = "Centris 660AV",
.adb_type = MAC_ADB_CUDA,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_QUADRA3,
.scc_type = MAC_SCC_PSC,
.ether_type = MAC_ETHER_MACE,
.expansion_type = MAC_EXP_PDS_NUBUS,
.floppy_type = MAC_FLOPPY_UNSUPPORTED, /* New Age */
},
/*
* The PowerBooks all the same "Combo" custom IC for SCSI and SCC
* and a PMU (in two variations?) for ADB. Most of them use the
* Quadra-style VIAs. A few models also have IDE from hell.
*/
{
.ident = MAC_MODEL_PB140,
.name = "PowerBook 140",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB145,
.name = "PowerBook 145",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB150,
.name = "PowerBook 150",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_OLD,
.ide_type = MAC_IDE_PB,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB160,
.name = "PowerBook 160",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB165,
.name = "PowerBook 165",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB165C,
.name = "PowerBook 165c",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB170,
.name = "PowerBook 170",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB180,
.name = "PowerBook 180",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB180C,
.name = "PowerBook 180c",
.adb_type = MAC_ADB_PB1,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB190,
.name = "PowerBook 190",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.ide_type = MAC_IDE_BABOON,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM 2 */
}, {
.ident = MAC_MODEL_PB520,
.name = "PowerBook 520",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_QUADRA,
.scsi_type = MAC_SCSI_OLD,
.scc_type = MAC_SCC_QUADRA,
.ether_type = MAC_ETHER_SONIC,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM 2 */
},
/*
* PowerBook Duos are pretty much like normal PowerBooks
* All of these probably have onboard SONIC in the Dock which
* means we'll have to probe for it eventually.
*/
{
.ident = MAC_MODEL_PB210,
.name = "PowerBook Duo 210",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_DUO,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB230,
.name = "PowerBook Duo 230",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_DUO,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB250,
.name = "PowerBook Duo 250",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_DUO,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB270C,
.name = "PowerBook Duo 270c",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_DUO,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB280,
.name = "PowerBook Duo 280",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_DUO,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
}, {
.ident = MAC_MODEL_PB280C,
.name = "PowerBook Duo 280c",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_IICI,
.scsi_type = MAC_SCSI_DUO,
.scc_type = MAC_SCC_QUADRA,
.expansion_type = MAC_EXP_NUBUS,
.floppy_type = MAC_FLOPPY_OLD, /* SWIM */
},
/*
* Other stuff?
*/
{
.ident = -1
}
};
static struct resource scc_a_rsrcs[] = {
{ .flags = IORESOURCE_MEM },
{ .flags = IORESOURCE_IRQ },
};
static struct resource scc_b_rsrcs[] = {
{ .flags = IORESOURCE_MEM },
{ .flags = IORESOURCE_IRQ },
};
struct platform_device scc_a_pdev = {
.name = "scc",
.id = 0,
};
EXPORT_SYMBOL(scc_a_pdev);
struct platform_device scc_b_pdev = {
.name = "scc",
.id = 1,
};
EXPORT_SYMBOL(scc_b_pdev);
static void __init mac_identify(void)
{
struct mac_model *m;
/* Penguin data useful? */
int model = mac_bi_data.id;
if (!model) {
/* no bootinfo model id -> NetBSD booter was used! */
/* XXX FIXME: breaks for model > 31 */
model = (mac_bi_data.cpuid >> 2) & 63;
pr_warn("No bootinfo model ID, using cpuid instead (obsolete bootloader?)\n");
}
macintosh_config = mac_data_table;
for (m = macintosh_config; m->ident != -1; m++) {
if (m->ident == model) {
macintosh_config = m;
break;
}
}
/* Set up serial port resources for the console initcall. */
scc_a_rsrcs[0].start = (resource_size_t)mac_bi_data.sccbase + 2;
scc_a_rsrcs[0].end = scc_a_rsrcs[0].start;
scc_a_pdev.num_resources = ARRAY_SIZE(scc_a_rsrcs);
scc_a_pdev.resource = scc_a_rsrcs;
scc_b_rsrcs[0].start = (resource_size_t)mac_bi_data.sccbase;
scc_b_rsrcs[0].end = scc_b_rsrcs[0].start;
scc_b_pdev.num_resources = ARRAY_SIZE(scc_b_rsrcs);
scc_b_pdev.resource = scc_b_rsrcs;
switch (macintosh_config->scc_type) {
case MAC_SCC_PSC:
scc_a_rsrcs[1].start = scc_a_rsrcs[1].end = IRQ_MAC_SCC_A;
scc_b_rsrcs[1].start = scc_b_rsrcs[1].end = IRQ_MAC_SCC_B;
break;
default:
/* On non-PSC machines, the serial ports share an IRQ. */
if (macintosh_config->ident == MAC_MODEL_IIFX) {
scc_a_rsrcs[1].start = scc_a_rsrcs[1].end = IRQ_MAC_SCC;
scc_b_rsrcs[1].start = scc_b_rsrcs[1].end = IRQ_MAC_SCC;
} else {
scc_a_rsrcs[1].start = scc_a_rsrcs[1].end = IRQ_AUTO_4;
scc_b_rsrcs[1].start = scc_b_rsrcs[1].end = IRQ_AUTO_4;
}
break;
}
pr_info("Detected Macintosh model: %d\n", model);
/*
* Report booter data:
*/
printk(KERN_DEBUG " Penguin bootinfo data:\n");
printk(KERN_DEBUG " Video: addr 0x%lx row 0x%lx depth %lx dimensions %ld x %ld\n",
mac_bi_data.videoaddr, mac_bi_data.videorow,
mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF,
mac_bi_data.dimensions >> 16);
printk(KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx\n",
mac_bi_data.videological, mac_orig_videoaddr,
mac_bi_data.sccbase);
printk(KERN_DEBUG " Boottime: 0x%lx GMTBias: 0x%lx\n",
mac_bi_data.boottime, mac_bi_data.gmtbias);
printk(KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx\n",
mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize);
iop_init();
oss_init();
via_init();
psc_init();
baboon_init();
#ifdef CONFIG_ADB_CUDA
find_via_cuda();
#endif
#ifdef CONFIG_ADB_PMU
find_via_pmu();
#endif
}
static void __init mac_report_hardware(void)
{
pr_info("Apple Macintosh %s\n", macintosh_config->name);
}
static void mac_get_model(char *str)
{
strcpy(str, "Macintosh ");
strcat(str, macintosh_config->name);
}
static const struct resource mac_scsi_iifx_rsrc[] __initconst = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_MAC_SCSI,
.end = IRQ_MAC_SCSI,
}, {
.flags = IORESOURCE_MEM,
.start = 0x50008000,
.end = 0x50009FFF,
}, {
.flags = IORESOURCE_MEM,
.start = 0x50008000,
.end = 0x50009FFF,
},
};
static const struct resource mac_scsi_duo_rsrc[] __initconst = {
{
.flags = IORESOURCE_MEM,
.start = 0xFEE02000,
.end = 0xFEE03FFF,
},
};
static const struct resource mac_scsi_old_rsrc[] __initconst = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_MAC_SCSI,
.end = IRQ_MAC_SCSI,
}, {
.flags = IORESOURCE_MEM,
.start = 0x50010000,
.end = 0x50011FFF,
}, {
.flags = IORESOURCE_MEM,
.start = 0x50006000,
.end = 0x50007FFF,
},
};
static const struct resource mac_scsi_ccl_rsrc[] __initconst = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_MAC_SCSI,
.end = IRQ_MAC_SCSI,
}, {
.flags = IORESOURCE_MEM,
.start = 0x50F10000,
.end = 0x50F11FFF,
}, {
.flags = IORESOURCE_MEM,
.start = 0x50F06000,
.end = 0x50F07FFF,
},
};
static const struct resource mac_pata_quadra_rsrc[] __initconst = {
DEFINE_RES_MEM(0x50F1A000, 0x38),
DEFINE_RES_MEM(0x50F1A038, 0x04),
DEFINE_RES_IRQ(IRQ_NUBUS_F),
};
static const struct resource mac_pata_pb_rsrc[] __initconst = {
DEFINE_RES_MEM(0x50F1A000, 0x38),
DEFINE_RES_MEM(0x50F1A038, 0x04),
DEFINE_RES_IRQ(IRQ_NUBUS_C),
};
static const struct resource mac_pata_baboon_rsrc[] __initconst = {
DEFINE_RES_MEM(0x50F1A000, 0x38),
DEFINE_RES_MEM(0x50F1A038, 0x04),
DEFINE_RES_IRQ(IRQ_BABOON_1),
};
static const struct pata_platform_info mac_pata_data __initconst = {
.ioport_shift = 2,
};
int __init mac_platform_init(void)
{
phys_addr_t swim_base = 0;
if (!MACH_IS_MAC)
return -ENODEV;
/*
* Serial devices
*/
platform_device_register(&scc_a_pdev);
platform_device_register(&scc_b_pdev);
/*
* Floppy device
*/
switch (macintosh_config->floppy_type) {
case MAC_FLOPPY_QUADRA:
swim_base = 0x5001E000;
break;
case MAC_FLOPPY_OLD:
swim_base = 0x50016000;
break;
case MAC_FLOPPY_LC:
swim_base = 0x50F16000;
break;
}
if (swim_base) {
struct resource swim_rsrc = {
.flags = IORESOURCE_MEM,
.start = swim_base,
.end = swim_base + 0x1FFF,
};
platform_device_register_simple("swim", -1, &swim_rsrc, 1);
}
/*
* SCSI device(s)
*/
switch (macintosh_config->scsi_type) {
case MAC_SCSI_QUADRA:
case MAC_SCSI_QUADRA3:
platform_device_register_simple("mac_esp", 0, NULL, 0);
break;
case MAC_SCSI_QUADRA2:
platform_device_register_simple("mac_esp", 0, NULL, 0);
if ((macintosh_config->ident == MAC_MODEL_Q900) ||
(macintosh_config->ident == MAC_MODEL_Q950))
platform_device_register_simple("mac_esp", 1, NULL, 0);
break;
case MAC_SCSI_IIFX:
/* Addresses from The Guide to Mac Family Hardware.
* $5000 8000 - $5000 9FFF: SCSI DMA
* $5000 A000 - $5000 BFFF: Alternate SCSI
* $5000 C000 - $5000 DFFF: Alternate SCSI (DMA)
* $5000 E000 - $5000 FFFF: Alternate SCSI (Hsk)
* The A/UX header file sys/uconfig.h says $50F0 8000.
* The "SCSI DMA" custom IC embeds the 53C80 core and
* supports Programmed IO, DMA and PDMA (hardware handshake).
*/
platform_device_register_simple("mac_scsi", 0,
mac_scsi_iifx_rsrc, ARRAY_SIZE(mac_scsi_iifx_rsrc));
break;
case MAC_SCSI_DUO:
/* Addresses from the Duo Dock II Developer Note.
* $FEE0 2000 - $FEE0 3FFF: normal mode
* $FEE0 4000 - $FEE0 5FFF: pseudo DMA without /DRQ
* $FEE0 6000 - $FEE0 7FFF: pseudo DMA with /DRQ
* The NetBSD code indicates that both 5380 chips share
* an IRQ (?) which would need careful handling (see mac_esp).
*/
platform_device_register_simple("mac_scsi", 1,
mac_scsi_duo_rsrc, ARRAY_SIZE(mac_scsi_duo_rsrc));
fallthrough;
case MAC_SCSI_OLD:
/* Addresses from Developer Notes for Duo System,
* PowerBook 180 & 160, 140 & 170, Macintosh IIsi
* and also from The Guide to Mac Family Hardware for
* SE/30, II, IIx, IIcx, IIci.
* $5000 6000 - $5000 7FFF: pseudo-DMA with /DRQ
* $5001 0000 - $5001 1FFF: normal mode
* $5001 2000 - $5001 3FFF: pseudo-DMA without /DRQ
* GMFH says that $5000 0000 - $50FF FFFF "wraps
* $5000 0000 - $5001 FFFF eight times" (!)
* mess.org says IIci and Color Classic do not alias
* I/O address space.
*/
platform_device_register_simple("mac_scsi", 0,
mac_scsi_old_rsrc, ARRAY_SIZE(mac_scsi_old_rsrc));
break;
case MAC_SCSI_LC:
/* Addresses from Mac LC data in Designing Cards & Drivers 3ed.
* Also from the Developer Notes for Classic II, LC III,
* Color Classic and IIvx.
* $50F0 6000 - $50F0 7FFF: SCSI handshake
* $50F1 0000 - $50F1 1FFF: SCSI
* $50F1 2000 - $50F1 3FFF: SCSI DMA
*/
platform_device_register_simple("mac_scsi", 0,
mac_scsi_ccl_rsrc, ARRAY_SIZE(mac_scsi_ccl_rsrc));
break;
}
/*
* IDE device
*/
switch (macintosh_config->ide_type) {
case MAC_IDE_QUADRA:
platform_device_register_resndata(NULL, "pata_platform", -1,
mac_pata_quadra_rsrc, ARRAY_SIZE(mac_pata_quadra_rsrc),
&mac_pata_data, sizeof(mac_pata_data));
break;
case MAC_IDE_PB:
platform_device_register_resndata(NULL, "pata_platform", -1,
mac_pata_pb_rsrc, ARRAY_SIZE(mac_pata_pb_rsrc),
&mac_pata_data, sizeof(mac_pata_data));
break;
case MAC_IDE_BABOON:
platform_device_register_resndata(NULL, "pata_platform", -1,
mac_pata_baboon_rsrc, ARRAY_SIZE(mac_pata_baboon_rsrc),
&mac_pata_data, sizeof(mac_pata_data));
break;
}
/*
* Ethernet device
*/
if (macintosh_config->ether_type == MAC_ETHER_SONIC ||
macintosh_config->expansion_type == MAC_EXP_PDS_COMM)
platform_device_register_simple("macsonic", -1, NULL, 0);
if (macintosh_config->expansion_type == MAC_EXP_PDS ||
macintosh_config->expansion_type == MAC_EXP_PDS_COMM)
platform_device_register_simple("mac89x0", -1, NULL, 0);
if (macintosh_config->ether_type == MAC_ETHER_MACE)
platform_device_register_simple("macmace", -1, NULL, 0);
return 0;
}
arch_initcall(mac_platform_init);
| linux-master | arch/m68k/mac/config.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Operating System Services (OSS) chip handling
* Written by Joshua M. Thompson ([email protected])
*
*
* This chip is used in the IIfx in place of VIA #2. It acts like a fancy
* VIA chip with prorammable interrupt levels.
*
* 990502 (jmt) - Major rewrite for new interrupt architecture as well as some
* recent insights into OSS operational details.
* 990610 (jmt) - Now taking full advantage of the OSS. Interrupts are mapped
* to mostly match the A/UX interrupt scheme supported on the
* VIA side. Also added support for enabling the ISM irq again
* since we now have a functional IOP manager.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_via.h>
#include <asm/mac_oss.h>
int oss_present;
volatile struct mac_oss *oss;
/*
* Initialize the OSS
*/
void __init oss_init(void)
{
int i;
if (macintosh_config->ident != MAC_MODEL_IIFX)
return;
oss = (struct mac_oss *) OSS_BASE;
pr_debug("OSS detected at %p", oss);
oss_present = 1;
/* Disable all interrupts. Unlike a VIA it looks like we */
/* do this by setting the source's interrupt level to zero. */
for (i = 0; i < OSS_NUM_SOURCES; i++)
oss->irq_level[i] = 0;
}
/*
* Handle OSS interrupts.
* XXX how do you clear a pending IRQ? is it even necessary?
*/
static void oss_iopism_irq(struct irq_desc *desc)
{
generic_handle_irq(IRQ_MAC_ADB);
}
static void oss_scsi_irq(struct irq_desc *desc)
{
generic_handle_irq(IRQ_MAC_SCSI);
}
static void oss_nubus_irq(struct irq_desc *desc)
{
u16 events, irq_bit;
int irq_num;
events = oss->irq_pending & OSS_IP_NUBUS;
irq_num = NUBUS_SOURCE_BASE + 5;
irq_bit = OSS_IP_NUBUS5;
do {
if (events & irq_bit) {
events &= ~irq_bit;
generic_handle_irq(irq_num);
}
--irq_num;
irq_bit >>= 1;
} while (events);
}
static void oss_iopscc_irq(struct irq_desc *desc)
{
generic_handle_irq(IRQ_MAC_SCC);
}
/*
* Register the OSS and NuBus interrupt dispatchers.
*
* This IRQ mapping is laid out with two things in mind: first, we try to keep
* things on their own levels to avoid having to do double-dispatches. Second,
* the levels match as closely as possible the alternate IRQ mapping mode (aka
* "A/UX mode") available on some VIA machines.
*/
#define OSS_IRQLEV_IOPISM IRQ_AUTO_1
#define OSS_IRQLEV_SCSI IRQ_AUTO_2
#define OSS_IRQLEV_NUBUS IRQ_AUTO_3
#define OSS_IRQLEV_IOPSCC IRQ_AUTO_4
#define OSS_IRQLEV_VIA1 IRQ_AUTO_6
void __init oss_register_interrupts(void)
{
irq_set_chained_handler(OSS_IRQLEV_IOPISM, oss_iopism_irq);
irq_set_chained_handler(OSS_IRQLEV_SCSI, oss_scsi_irq);
irq_set_chained_handler(OSS_IRQLEV_NUBUS, oss_nubus_irq);
irq_set_chained_handler(OSS_IRQLEV_IOPSCC, oss_iopscc_irq);
irq_set_chained_handler(OSS_IRQLEV_VIA1, via1_irq);
/* OSS_VIA1 gets enabled here because it has no machspec interrupt. */
oss->irq_level[OSS_VIA1] = OSS_IRQLEV_VIA1;
}
/*
* Enable an OSS interrupt
*
* It looks messy but it's rather straightforward. The switch() statement
* just maps the machspec interrupt numbers to the right OSS interrupt
* source (if the OSS handles that interrupt) and then sets the interrupt
* level for that source to nonzero, thus enabling the interrupt.
*/
void oss_irq_enable(int irq) {
switch(irq) {
case IRQ_MAC_SCC:
oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_IOPSCC;
return;
case IRQ_MAC_ADB:
oss->irq_level[OSS_IOPISM] = OSS_IRQLEV_IOPISM;
return;
case IRQ_MAC_SCSI:
oss->irq_level[OSS_SCSI] = OSS_IRQLEV_SCSI;
return;
case IRQ_NUBUS_9:
case IRQ_NUBUS_A:
case IRQ_NUBUS_B:
case IRQ_NUBUS_C:
case IRQ_NUBUS_D:
case IRQ_NUBUS_E:
irq -= NUBUS_SOURCE_BASE;
oss->irq_level[irq] = OSS_IRQLEV_NUBUS;
return;
}
if (IRQ_SRC(irq) == 1)
via_irq_enable(irq);
}
/*
* Disable an OSS interrupt
*
* Same as above except we set the source's interrupt level to zero,
* to disable the interrupt.
*/
void oss_irq_disable(int irq) {
switch(irq) {
case IRQ_MAC_SCC:
oss->irq_level[OSS_IOPSCC] = 0;
return;
case IRQ_MAC_ADB:
oss->irq_level[OSS_IOPISM] = 0;
return;
case IRQ_MAC_SCSI:
oss->irq_level[OSS_SCSI] = 0;
return;
case IRQ_NUBUS_9:
case IRQ_NUBUS_A:
case IRQ_NUBUS_B:
case IRQ_NUBUS_C:
case IRQ_NUBUS_D:
case IRQ_NUBUS_E:
irq -= NUBUS_SOURCE_BASE;
oss->irq_level[irq] = 0;
return;
}
if (IRQ_SRC(irq) == 1)
via_irq_disable(irq);
}
| linux-master | arch/m68k/mac/oss.c |
/*
* I/O Processor (IOP) management
* Written and (C) 1999 by Joshua M. Thompson ([email protected])
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice and this list of conditions.
* 2. Redistributions in binary form must reproduce the above copyright
* notice and this list of conditions in the documentation and/or other
* materials provided with the distribution.
*/
/*
* The IOP chips are used in the IIfx and some Quadras (900, 950) to manage
* serial and ADB. They are actually a 6502 processor and some glue logic.
*
* 990429 (jmt) - Initial implementation, just enough to knock the SCC IOP
* into compatible mode so nobody has to fiddle with the
* Serial Switch control panel anymore.
* 990603 (jmt) - Added code to grab the correct ISM IOP interrupt for OSS
* and non-OSS machines (at least I hope it's correct on a
* non-OSS machine -- someone with a Q900 or Q950 needs to
* check this.)
* 990605 (jmt) - Rearranged things a bit wrt IOP detection; iop_present is
* gone, IOP base addresses are now in an array and the
* globally-visible functions take an IOP number instead of
* an actual base address.
* 990610 (jmt) - Finished the message passing framework and it seems to work.
* Sending _definitely_ works; my adb-bus.c mods can send
* messages and receive the MSG_COMPLETED status back from the
* IOP. The trick now is figuring out the message formats.
* 990611 (jmt) - More cleanups. Fixed problem where unclaimed messages on a
* receive channel were never properly acknowledged. Bracketed
* the remaining debug printk's with #ifdef's and disabled
* debugging. I can now type on the console.
* 990612 (jmt) - Copyright notice added. Reworked the way replies are handled.
* It turns out that replies are placed back in the send buffer
* for that channel; messages on the receive channels are always
* unsolicited messages from the IOP (and our replies to them
* should go back in the receive channel.) Also added tracking
* of device names to the listener functions ala the interrupt
* handlers.
* 990729 (jmt) - Added passing of pt_regs structure to IOP handlers. This is
* used by the new unified ADB driver.
*
* TODO:
*
* o The SCC IOP has to be placed in bypass mode before the serial console
* gets initialized. iop_init() would be one place to do that. Or the
* bootloader could do that. For now, the Serial Switch control panel
* is needed for that -- contrary to the changelog above.
* o Something should be periodically checking iop_alive() to make sure the
* IOP hasn't died.
* o Some of the IOP manager routines need better error checking and
* return codes. Nothing major, just prettying up.
*/
/*
* -----------------------
* IOP Message Passing 101
* -----------------------
*
* The host talks to the IOPs using a rather simple message-passing scheme via
* a shared memory area in the IOP RAM. Each IOP has seven "channels"; each
* channel is connected to a specific software driver on the IOP. For example
* on the SCC IOP there is one channel for each serial port. Each channel has
* an incoming and an outgoing message queue with a depth of one.
*
* A message is 32 bytes plus a state byte for the channel (MSG_IDLE, MSG_NEW,
* MSG_RCVD, MSG_COMPLETE). To send a message you copy the message into the
* buffer, set the state to MSG_NEW and signal the IOP by setting the IRQ flag
* in the IOP control to 1. The IOP will move the state to MSG_RCVD when it
* receives the message and then to MSG_COMPLETE when the message processing
* has completed. It is the host's responsibility at that point to read the
* reply back out of the send channel buffer and reset the channel state back
* to MSG_IDLE.
*
* To receive message from the IOP the same procedure is used except the roles
* are reversed. That is, the IOP puts message in the channel with a state of
* MSG_NEW, and the host receives the message and move its state to MSG_RCVD
* and then to MSG_COMPLETE when processing is completed and the reply (if any)
* has been placed back in the receive channel. The IOP will then reset the
* channel state to MSG_IDLE.
*
* Two sets of host interrupts are provided, INT0 and INT1. Both appear on one
* interrupt level; they are distinguished by a pair of bits in the IOP status
* register. The IOP will raise INT0 when one or more messages in the send
* channels have gone to the MSG_COMPLETE state and it will raise INT1 when one
* or more messages on the receive channels have gone to the MSG_NEW state.
*
* Since each channel handles only one message we have to implement a small
* interrupt-driven queue on our end. Messages to be sent are placed on the
* queue for sending and contain a pointer to an optional callback function.
* The handler for a message is called when the message state goes to
* MSG_COMPLETE.
*
* For receiving message we maintain a list of handler functions to call when
* a message is received on that IOP/channel combination. The handlers are
* called much like an interrupt handler and are passed a copy of the message
* from the IOP. The message state will be in MSG_RCVD while the handler runs;
* it is the handler's responsibility to call iop_complete_message() when
* finished; this function moves the message state to MSG_COMPLETE and signals
* the IOP. This two-step process is provided to allow the handler to defer
* message processing to a bottom-half handler if the processing will take
* a significant amount of time (handlers are called at interrupt time so they
* should execute quickly.)
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_iop.h>
#ifdef DEBUG
#define iop_pr_debug(fmt, ...) \
printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__)
#define iop_pr_cont(fmt, ...) \
printk(KERN_CONT fmt, ##__VA_ARGS__)
#else
#define iop_pr_debug(fmt, ...) \
no_printk(KERN_DEBUG "%s: " fmt, __func__, ##__VA_ARGS__)
#define iop_pr_cont(fmt, ...) \
no_printk(KERN_CONT fmt, ##__VA_ARGS__)
#endif
/* Non-zero if the IOPs are present */
int iop_scc_present, iop_ism_present;
/* structure for tracking channel listeners */
struct listener {
const char *devname;
void (*handler)(struct iop_msg *);
};
/*
* IOP structures for the two IOPs
*
* The SCC IOP controls both serial ports (A and B) as its two functions.
* The ISM IOP controls the SWIM (floppy drive) and ADB.
*/
static volatile struct mac_iop *iop_base[NUM_IOPS];
/*
* IOP message queues
*/
static struct iop_msg iop_msg_pool[NUM_IOP_MSGS];
static struct iop_msg *iop_send_queue[NUM_IOPS][NUM_IOP_CHAN];
static struct listener iop_listeners[NUM_IOPS][NUM_IOP_CHAN];
irqreturn_t iop_ism_irq(int, void *);
/*
* Private access functions
*/
static __inline__ void iop_loadaddr(volatile struct mac_iop *iop, __u16 addr)
{
iop->ram_addr_lo = addr;
iop->ram_addr_hi = addr >> 8;
}
static __inline__ __u8 iop_readb(volatile struct mac_iop *iop, __u16 addr)
{
iop->ram_addr_lo = addr;
iop->ram_addr_hi = addr >> 8;
return iop->ram_data;
}
static __inline__ void iop_writeb(volatile struct mac_iop *iop, __u16 addr, __u8 data)
{
iop->ram_addr_lo = addr;
iop->ram_addr_hi = addr >> 8;
iop->ram_data = data;
}
static __inline__ void iop_stop(volatile struct mac_iop *iop)
{
iop->status_ctrl = IOP_AUTOINC;
}
static __inline__ void iop_start(volatile struct mac_iop *iop)
{
iop->status_ctrl = IOP_RUN | IOP_AUTOINC;
}
static __inline__ void iop_interrupt(volatile struct mac_iop *iop)
{
iop->status_ctrl = IOP_IRQ | IOP_RUN | IOP_AUTOINC;
}
static int iop_alive(volatile struct mac_iop *iop)
{
int retval;
retval = (iop_readb(iop, IOP_ADDR_ALIVE) == 0xFF);
iop_writeb(iop, IOP_ADDR_ALIVE, 0);
return retval;
}
static struct iop_msg *iop_get_unused_msg(void)
{
int i;
unsigned long flags;
local_irq_save(flags);
for (i = 0 ; i < NUM_IOP_MSGS ; i++) {
if (iop_msg_pool[i].status == IOP_MSGSTATUS_UNUSED) {
iop_msg_pool[i].status = IOP_MSGSTATUS_WAITING;
local_irq_restore(flags);
return &iop_msg_pool[i];
}
}
local_irq_restore(flags);
return NULL;
}
/*
* Initialize the IOPs, if present.
*/
void __init iop_init(void)
{
int i;
if (macintosh_config->scc_type == MAC_SCC_IOP) {
if (macintosh_config->ident == MAC_MODEL_IIFX)
iop_base[IOP_NUM_SCC] = (struct mac_iop *)SCC_IOP_BASE_IIFX;
else
iop_base[IOP_NUM_SCC] = (struct mac_iop *)SCC_IOP_BASE_QUADRA;
iop_scc_present = 1;
pr_debug("SCC IOP detected at %p\n", iop_base[IOP_NUM_SCC]);
}
if (macintosh_config->adb_type == MAC_ADB_IOP) {
if (macintosh_config->ident == MAC_MODEL_IIFX)
iop_base[IOP_NUM_ISM] = (struct mac_iop *)ISM_IOP_BASE_IIFX;
else
iop_base[IOP_NUM_ISM] = (struct mac_iop *)ISM_IOP_BASE_QUADRA;
iop_ism_present = 1;
pr_debug("ISM IOP detected at %p\n", iop_base[IOP_NUM_ISM]);
iop_stop(iop_base[IOP_NUM_ISM]);
iop_start(iop_base[IOP_NUM_ISM]);
iop_alive(iop_base[IOP_NUM_ISM]); /* clears the alive flag */
}
/* Make the whole pool available and empty the queues */
for (i = 0 ; i < NUM_IOP_MSGS ; i++) {
iop_msg_pool[i].status = IOP_MSGSTATUS_UNUSED;
}
for (i = 0 ; i < NUM_IOP_CHAN ; i++) {
iop_send_queue[IOP_NUM_SCC][i] = NULL;
iop_send_queue[IOP_NUM_ISM][i] = NULL;
iop_listeners[IOP_NUM_SCC][i].devname = NULL;
iop_listeners[IOP_NUM_SCC][i].handler = NULL;
iop_listeners[IOP_NUM_ISM][i].devname = NULL;
iop_listeners[IOP_NUM_ISM][i].handler = NULL;
}
}
/*
* Register the interrupt handler for the IOPs.
*/
void __init iop_register_interrupts(void)
{
if (iop_ism_present) {
if (macintosh_config->ident == MAC_MODEL_IIFX) {
if (request_irq(IRQ_MAC_ADB, iop_ism_irq, 0,
"ISM IOP", (void *)IOP_NUM_ISM))
pr_err("Couldn't register ISM IOP interrupt\n");
} else {
if (request_irq(IRQ_VIA2_0, iop_ism_irq, 0, "ISM IOP",
(void *)IOP_NUM_ISM))
pr_err("Couldn't register ISM IOP interrupt\n");
}
if (!iop_alive(iop_base[IOP_NUM_ISM])) {
pr_warn("IOP: oh my god, they killed the ISM IOP!\n");
} else {
pr_warn("IOP: the ISM IOP seems to be alive.\n");
}
}
}
/*
* Register or unregister a listener for a specific IOP and channel
*
* If the handler pointer is NULL the current listener (if any) is
* unregistered. Otherwise the new listener is registered provided
* there is no existing listener registered.
*/
int iop_listen(uint iop_num, uint chan,
void (*handler)(struct iop_msg *),
const char *devname)
{
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL;
if (chan >= NUM_IOP_CHAN) return -EINVAL;
if (iop_listeners[iop_num][chan].handler && handler) return -EINVAL;
iop_listeners[iop_num][chan].devname = devname;
iop_listeners[iop_num][chan].handler = handler;
return 0;
}
/*
* Complete reception of a message, which just means copying the reply
* into the buffer, setting the channel state to MSG_COMPLETE and
* notifying the IOP.
*/
void iop_complete_message(struct iop_msg *msg)
{
int iop_num = msg->iop_num;
int chan = msg->channel;
int i,offset;
iop_pr_debug("iop_num %d chan %d reply %*ph\n",
msg->iop_num, msg->channel, IOP_MSG_LEN, msg->reply);
offset = IOP_ADDR_RECV_MSG + (msg->channel * IOP_MSG_LEN);
for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) {
iop_writeb(iop_base[iop_num], offset, msg->reply[i]);
}
iop_writeb(iop_base[iop_num],
IOP_ADDR_RECV_STATE + chan, IOP_MSG_COMPLETE);
iop_interrupt(iop_base[msg->iop_num]);
msg->status = IOP_MSGSTATUS_UNUSED;
}
/*
* Actually put a message into a send channel buffer
*/
static void iop_do_send(struct iop_msg *msg)
{
volatile struct mac_iop *iop = iop_base[msg->iop_num];
int i,offset;
iop_pr_debug("iop_num %d chan %d message %*ph\n",
msg->iop_num, msg->channel, IOP_MSG_LEN, msg->message);
offset = IOP_ADDR_SEND_MSG + (msg->channel * IOP_MSG_LEN);
for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) {
iop_writeb(iop, offset, msg->message[i]);
}
iop_writeb(iop, IOP_ADDR_SEND_STATE + msg->channel, IOP_MSG_NEW);
iop_interrupt(iop);
}
/*
* Handle sending a message on a channel that
* has gone into the IOP_MSG_COMPLETE state.
*/
static void iop_handle_send(uint iop_num, uint chan)
{
volatile struct mac_iop *iop = iop_base[iop_num];
struct iop_msg *msg;
int i,offset;
iop_writeb(iop, IOP_ADDR_SEND_STATE + chan, IOP_MSG_IDLE);
if (!(msg = iop_send_queue[iop_num][chan])) return;
msg->status = IOP_MSGSTATUS_COMPLETE;
offset = IOP_ADDR_SEND_MSG + (chan * IOP_MSG_LEN);
for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) {
msg->reply[i] = iop_readb(iop, offset);
}
iop_pr_debug("iop_num %d chan %d reply %*ph\n",
iop_num, chan, IOP_MSG_LEN, msg->reply);
if (msg->handler) (*msg->handler)(msg);
msg->status = IOP_MSGSTATUS_UNUSED;
msg = msg->next;
iop_send_queue[iop_num][chan] = msg;
if (msg && iop_readb(iop, IOP_ADDR_SEND_STATE + chan) == IOP_MSG_IDLE)
iop_do_send(msg);
}
/*
* Handle reception of a message on a channel that has
* gone into the IOP_MSG_NEW state.
*/
static void iop_handle_recv(uint iop_num, uint chan)
{
volatile struct mac_iop *iop = iop_base[iop_num];
int i,offset;
struct iop_msg *msg;
msg = iop_get_unused_msg();
msg->iop_num = iop_num;
msg->channel = chan;
msg->status = IOP_MSGSTATUS_UNSOL;
msg->handler = iop_listeners[iop_num][chan].handler;
offset = IOP_ADDR_RECV_MSG + (chan * IOP_MSG_LEN);
for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) {
msg->message[i] = iop_readb(iop, offset);
}
iop_pr_debug("iop_num %d chan %d message %*ph\n",
iop_num, chan, IOP_MSG_LEN, msg->message);
iop_writeb(iop, IOP_ADDR_RECV_STATE + chan, IOP_MSG_RCVD);
/* If there is a listener, call it now. Otherwise complete */
/* the message ourselves to avoid possible stalls. */
if (msg->handler) {
(*msg->handler)(msg);
} else {
memset(msg->reply, 0, IOP_MSG_LEN);
iop_complete_message(msg);
}
}
/*
* Send a message
*
* The message is placed at the end of the send queue. Afterwards if the
* channel is idle we force an immediate send of the next message in the
* queue.
*/
int iop_send_message(uint iop_num, uint chan, void *privdata,
uint msg_len, __u8 *msg_data,
void (*handler)(struct iop_msg *))
{
struct iop_msg *msg, *q;
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL;
if (chan >= NUM_IOP_CHAN) return -EINVAL;
if (msg_len > IOP_MSG_LEN) return -EINVAL;
msg = iop_get_unused_msg();
if (!msg) return -ENOMEM;
msg->next = NULL;
msg->status = IOP_MSGSTATUS_WAITING;
msg->iop_num = iop_num;
msg->channel = chan;
msg->caller_priv = privdata;
memcpy(msg->message, msg_data, msg_len);
msg->handler = handler;
if (!(q = iop_send_queue[iop_num][chan])) {
iop_send_queue[iop_num][chan] = msg;
iop_do_send(msg);
} else {
while (q->next) q = q->next;
q->next = msg;
}
return 0;
}
/*
* Upload code to the shared RAM of an IOP.
*/
void iop_upload_code(uint iop_num, __u8 *code_start,
uint code_len, __u16 shared_ram_start)
{
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return;
iop_loadaddr(iop_base[iop_num], shared_ram_start);
while (code_len--) {
iop_base[iop_num]->ram_data = *code_start++;
}
}
/*
* Download code from the shared RAM of an IOP.
*/
void iop_download_code(uint iop_num, __u8 *code_start,
uint code_len, __u16 shared_ram_start)
{
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return;
iop_loadaddr(iop_base[iop_num], shared_ram_start);
while (code_len--) {
*code_start++ = iop_base[iop_num]->ram_data;
}
}
/*
* Compare the code in the shared RAM of an IOP with a copy in system memory
* and return 0 on match or the first nonmatching system memory address on
* failure.
*/
__u8 *iop_compare_code(uint iop_num, __u8 *code_start,
uint code_len, __u16 shared_ram_start)
{
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return code_start;
iop_loadaddr(iop_base[iop_num], shared_ram_start);
while (code_len--) {
if (*code_start != iop_base[iop_num]->ram_data) {
return code_start;
}
code_start++;
}
return (__u8 *) 0;
}
/*
* Handle an ISM IOP interrupt
*/
irqreturn_t iop_ism_irq(int irq, void *dev_id)
{
uint iop_num = (uint) dev_id;
volatile struct mac_iop *iop = iop_base[iop_num];
int i,state;
u8 events = iop->status_ctrl & (IOP_INT0 | IOP_INT1);
do {
iop_pr_debug("iop_num %d status %02X\n", iop_num,
iop->status_ctrl);
/* INT0 indicates state change on an outgoing message channel */
if (events & IOP_INT0) {
iop->status_ctrl = IOP_INT0 | IOP_RUN | IOP_AUTOINC;
for (i = 0; i < NUM_IOP_CHAN; i++) {
state = iop_readb(iop, IOP_ADDR_SEND_STATE + i);
if (state == IOP_MSG_COMPLETE)
iop_handle_send(iop_num, i);
else if (state != IOP_MSG_IDLE)
iop_pr_debug("chan %d send state %02X\n",
i, state);
}
}
/* INT1 for incoming messages */
if (events & IOP_INT1) {
iop->status_ctrl = IOP_INT1 | IOP_RUN | IOP_AUTOINC;
for (i = 0; i < NUM_IOP_CHAN; i++) {
state = iop_readb(iop, IOP_ADDR_RECV_STATE + i);
if (state == IOP_MSG_NEW)
iop_handle_recv(iop_num, i);
else if (state != IOP_MSG_IDLE)
iop_pr_debug("chan %d recv state %02X\n",
i, state);
}
}
events = iop->status_ctrl & (IOP_INT0 | IOP_INT1);
} while (events);
return IRQ_HANDLED;
}
void iop_ism_irq_poll(uint iop_num)
{
unsigned long flags;
local_irq_save(flags);
iop_ism_irq(0, (void *)iop_num);
local_irq_restore(flags);
}
| linux-master | arch/m68k/mac/iop.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Apple Peripheral System Controller (PSC)
*
* The PSC is used on the AV Macs to control IO functions not handled
* by the VIAs (Ethernet, DSP, SCC).
*
* TO DO:
*
* Try to figure out what's going on in pIFR5 and pIFR6. There seem to be
* persisant interrupt conditions in those registers and I have no idea what
* they are. Granted it doesn't affect since we're not enabling any interrupts
* on those levels at the moment, but it would be nice to know. I have a feeling
* they aren't actually interrupt lines but data lines (to the DSP?)
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/traps.h>
#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_psc.h>
#define DEBUG_PSC
volatile __u8 *psc;
EXPORT_SYMBOL_GPL(psc);
/*
* Debugging dump, used in various places to see what's going on.
*/
static void psc_debug_dump(void)
{
int i;
if (!psc)
return;
for (i = 0x30 ; i < 0x70 ; i += 0x10) {
printk(KERN_DEBUG "PSC #%d: IFR = 0x%02X IER = 0x%02X\n",
i >> 4,
(int) psc_read_byte(pIFRbase + i),
(int) psc_read_byte(pIERbase + i));
}
}
/*
* Try to kill all DMA channels on the PSC. Not sure how this his
* supposed to work; this is code lifted from macmace.c and then
* expanded to cover what I think are the other 7 channels.
*/
static __init void psc_dma_die_die_die(void)
{
int i;
for (i = 0 ; i < 9 ; i++) {
psc_write_word(PSC_CTL_BASE + (i << 4), 0x8800);
psc_write_word(PSC_CTL_BASE + (i << 4), 0x1000);
psc_write_word(PSC_CMD_BASE + (i << 5), 0x1100);
psc_write_word(PSC_CMD_BASE + (i << 5) + 0x10, 0x1100);
}
}
/*
* Initialize the PSC. For now this just involves shutting down all
* interrupt sources using the IERs.
*/
void __init psc_init(void)
{
int i;
if (macintosh_config->ident != MAC_MODEL_C660
&& macintosh_config->ident != MAC_MODEL_Q840)
{
psc = NULL;
return;
}
/*
* The PSC is always at the same spot, but using psc
* keeps things consistent with the psc_xxxx functions.
*/
psc = (void *) PSC_BASE;
pr_debug("PSC detected at %p\n", psc);
psc_dma_die_die_die();
#ifdef DEBUG_PSC
psc_debug_dump();
#endif
/*
* Mask and clear all possible interrupts
*/
for (i = 0x30 ; i < 0x70 ; i += 0x10) {
psc_write_byte(pIERbase + i, 0x0F);
psc_write_byte(pIFRbase + i, 0x0F);
}
}
/*
* PSC interrupt handler. It's a lot like the VIA interrupt handler.
*/
static void psc_irq(struct irq_desc *desc)
{
unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc);
unsigned int irq = irq_desc_get_irq(desc);
int pIFR = pIFRbase + offset;
int pIER = pIERbase + offset;
int irq_num;
unsigned char irq_bit, events;
events = psc_read_byte(pIFR) & psc_read_byte(pIER) & 0xF;
if (!events)
return;
irq_num = irq << 3;
irq_bit = 1;
do {
if (events & irq_bit) {
psc_write_byte(pIFR, irq_bit);
generic_handle_irq(irq_num);
}
irq_num++;
irq_bit <<= 1;
} while (events >= irq_bit);
}
/*
* Register the PSC interrupt dispatchers for autovector interrupts 3-6.
*/
void __init psc_register_interrupts(void)
{
irq_set_chained_handler_and_data(IRQ_AUTO_3, psc_irq, (void *)0x30);
irq_set_chained_handler_and_data(IRQ_AUTO_4, psc_irq, (void *)0x40);
irq_set_chained_handler_and_data(IRQ_AUTO_5, psc_irq, (void *)0x50);
irq_set_chained_handler_and_data(IRQ_AUTO_6, psc_irq, (void *)0x60);
}
void psc_irq_enable(int irq) {
int irq_src = IRQ_SRC(irq);
int irq_idx = IRQ_IDX(irq);
int pIER = pIERbase + (irq_src << 4);
psc_write_byte(pIER, (1 << irq_idx) | 0x80);
}
void psc_irq_disable(int irq) {
int irq_src = IRQ_SRC(irq);
int irq_idx = IRQ_IDX(irq);
int pIER = pIERbase + (irq_src << 4);
psc_write_byte(pIER, 1 << irq_idx);
}
| linux-master | arch/m68k/mac/psc.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Miscellaneous Mac68K-specific stuff
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/mm.h>
#include <linux/adb.h>
#include <linux/cuda.h>
#include <linux/pmu.h>
#include <linux/uaccess.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/macintosh.h>
#include <asm/mac_via.h>
#include <asm/mac_oss.h>
#include <asm/machdep.h>
/*
* Offset between Unix time (1970-based) and Mac time (1904-based). Cuda and PMU
* times wrap in 2040. If we need to handle later times, the read_time functions
* need to be changed to interpret wrapped times as post-2040.
*/
#define RTC_OFFSET 2082844800
static void (*rom_reset)(void);
#if IS_ENABLED(CONFIG_NVRAM)
#ifdef CONFIG_ADB_CUDA
static unsigned char cuda_pram_read_byte(int offset)
{
struct adb_request req;
if (cuda_request(&req, NULL, 4, CUDA_PACKET, CUDA_GET_PRAM,
(offset >> 8) & 0xFF, offset & 0xFF) < 0)
return 0;
while (!req.complete)
cuda_poll();
return req.reply[3];
}
static void cuda_pram_write_byte(unsigned char data, int offset)
{
struct adb_request req;
if (cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_SET_PRAM,
(offset >> 8) & 0xFF, offset & 0xFF, data) < 0)
return;
while (!req.complete)
cuda_poll();
}
#endif /* CONFIG_ADB_CUDA */
#ifdef CONFIG_ADB_PMU
static unsigned char pmu_pram_read_byte(int offset)
{
struct adb_request req;
if (pmu_request(&req, NULL, 3, PMU_READ_XPRAM,
offset & 0xFF, 1) < 0)
return 0;
pmu_wait_complete(&req);
return req.reply[0];
}
static void pmu_pram_write_byte(unsigned char data, int offset)
{
struct adb_request req;
if (pmu_request(&req, NULL, 4, PMU_WRITE_XPRAM,
offset & 0xFF, 1, data) < 0)
return;
pmu_wait_complete(&req);
}
#endif /* CONFIG_ADB_PMU */
#endif /* CONFIG_NVRAM */
/*
* VIA PRAM/RTC access routines
*
* Must be called with interrupts disabled and
* the RTC should be enabled.
*/
static __u8 via_rtc_recv(void)
{
int i, reg;
__u8 data;
reg = via1[vBufB] & ~VIA1B_vRTCClk;
/* Set the RTC data line to be an input. */
via1[vDirB] &= ~VIA1B_vRTCData;
/* The bits of the byte come out in MSB order */
data = 0;
for (i = 0 ; i < 8 ; i++) {
via1[vBufB] = reg;
via1[vBufB] = reg | VIA1B_vRTCClk;
data = (data << 1) | (via1[vBufB] & VIA1B_vRTCData);
}
/* Return RTC data line to output state */
via1[vDirB] |= VIA1B_vRTCData;
return data;
}
static void via_rtc_send(__u8 data)
{
int i, reg, bit;
reg = via1[vBufB] & ~(VIA1B_vRTCClk | VIA1B_vRTCData);
/* The bits of the byte go into the RTC in MSB order */
for (i = 0 ; i < 8 ; i++) {
bit = data & 0x80? 1 : 0;
data <<= 1;
via1[vBufB] = reg | bit;
via1[vBufB] = reg | bit | VIA1B_vRTCClk;
}
}
/*
* These values can be found in Inside Macintosh vol. III ch. 2
* which has a description of the RTC chip in the original Mac.
*/
#define RTC_FLG_READ BIT(7)
#define RTC_FLG_WRITE_PROTECT BIT(7)
#define RTC_CMD_READ(r) (RTC_FLG_READ | (r << 2))
#define RTC_CMD_WRITE(r) (r << 2)
#define RTC_REG_SECONDS_0 0
#define RTC_REG_SECONDS_1 1
#define RTC_REG_SECONDS_2 2
#define RTC_REG_SECONDS_3 3
#define RTC_REG_WRITE_PROTECT 13
/*
* Inside Mac has no information about two-byte RTC commands but
* the MAME/MESS source code has the essentials.
*/
#define RTC_REG_XPRAM 14
#define RTC_CMD_XPRAM_READ (RTC_CMD_READ(RTC_REG_XPRAM) << 8)
#define RTC_CMD_XPRAM_WRITE (RTC_CMD_WRITE(RTC_REG_XPRAM) << 8)
#define RTC_CMD_XPRAM_ARG(a) (((a & 0xE0) << 3) | ((a & 0x1F) << 2))
/*
* Execute a VIA PRAM/RTC command. For read commands
* data should point to a one-byte buffer for the
* resulting data. For write commands it should point
* to the data byte to for the command.
*
* This function disables all interrupts while running.
*/
static void via_rtc_command(int command, __u8 *data)
{
unsigned long flags;
int is_read;
local_irq_save(flags);
/* The least significant bits must be 0b01 according to Inside Mac */
command = (command & ~3) | 1;
/* Enable the RTC and make sure the strobe line is high */
via1[vBufB] = (via1[vBufB] | VIA1B_vRTCClk) & ~VIA1B_vRTCEnb;
if (command & 0xFF00) { /* extended (two-byte) command */
via_rtc_send((command & 0xFF00) >> 8);
via_rtc_send(command & 0xFF);
is_read = command & (RTC_FLG_READ << 8);
} else { /* one-byte command */
via_rtc_send(command);
is_read = command & RTC_FLG_READ;
}
if (is_read) {
*data = via_rtc_recv();
} else {
via_rtc_send(*data);
}
/* All done, disable the RTC */
via1[vBufB] |= VIA1B_vRTCEnb;
local_irq_restore(flags);
}
#if IS_ENABLED(CONFIG_NVRAM)
static unsigned char via_pram_read_byte(int offset)
{
unsigned char temp;
via_rtc_command(RTC_CMD_XPRAM_READ | RTC_CMD_XPRAM_ARG(offset), &temp);
return temp;
}
static void via_pram_write_byte(unsigned char data, int offset)
{
unsigned char temp;
temp = 0x55;
via_rtc_command(RTC_CMD_WRITE(RTC_REG_WRITE_PROTECT), &temp);
temp = data;
via_rtc_command(RTC_CMD_XPRAM_WRITE | RTC_CMD_XPRAM_ARG(offset), &temp);
temp = 0x55 | RTC_FLG_WRITE_PROTECT;
via_rtc_command(RTC_CMD_WRITE(RTC_REG_WRITE_PROTECT), &temp);
}
#endif /* CONFIG_NVRAM */
/*
* Return the current time in seconds since January 1, 1904.
*
* This only works on machines with the VIA-based PRAM/RTC, which
* is basically any machine with Mac II-style ADB.
*/
static time64_t via_read_time(void)
{
union {
__u8 cdata[4];
__u32 idata;
} result, last_result;
int count = 1;
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_0), &last_result.cdata[3]);
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_1), &last_result.cdata[2]);
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_2), &last_result.cdata[1]);
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_3), &last_result.cdata[0]);
/*
* The NetBSD guys say to loop until you get the same reading
* twice in a row.
*/
while (1) {
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_0),
&result.cdata[3]);
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_1),
&result.cdata[2]);
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_2),
&result.cdata[1]);
via_rtc_command(RTC_CMD_READ(RTC_REG_SECONDS_3),
&result.cdata[0]);
if (result.idata == last_result.idata)
return (time64_t)result.idata - RTC_OFFSET;
if (++count > 10)
break;
last_result.idata = result.idata;
}
pr_err("%s: failed to read a stable value; got 0x%08x then 0x%08x\n",
__func__, last_result.idata, result.idata);
return 0;
}
/*
* Set the current time to a number of seconds since January 1, 1904.
*
* This only works on machines with the VIA-based PRAM/RTC, which
* is basically any machine with Mac II-style ADB.
*/
static void via_set_rtc_time(struct rtc_time *tm)
{
union {
__u8 cdata[4];
__u32 idata;
} data;
__u8 temp;
time64_t time;
time = mktime64(tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
/* Clear the write protect bit */
temp = 0x55;
via_rtc_command(RTC_CMD_WRITE(RTC_REG_WRITE_PROTECT), &temp);
data.idata = lower_32_bits(time + RTC_OFFSET);
via_rtc_command(RTC_CMD_WRITE(RTC_REG_SECONDS_0), &data.cdata[3]);
via_rtc_command(RTC_CMD_WRITE(RTC_REG_SECONDS_1), &data.cdata[2]);
via_rtc_command(RTC_CMD_WRITE(RTC_REG_SECONDS_2), &data.cdata[1]);
via_rtc_command(RTC_CMD_WRITE(RTC_REG_SECONDS_3), &data.cdata[0]);
/* Set the write protect bit */
temp = 0x55 | RTC_FLG_WRITE_PROTECT;
via_rtc_command(RTC_CMD_WRITE(RTC_REG_WRITE_PROTECT), &temp);
}
static void via_shutdown(void)
{
if (rbv_present) {
via2[rBufB] &= ~0x04;
} else {
/* Direction of vDirB is output */
via2[vDirB] |= 0x04;
/* Send a value of 0 on that line */
via2[vBufB] &= ~0x04;
mdelay(1000);
}
}
static void oss_shutdown(void)
{
oss->rom_ctrl = OSS_POWEROFF;
}
#ifdef CONFIG_ADB_CUDA
static void cuda_restart(void)
{
struct adb_request req;
if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_RESET_SYSTEM) < 0)
return;
while (!req.complete)
cuda_poll();
}
static void cuda_shutdown(void)
{
struct adb_request req;
if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_POWERDOWN) < 0)
return;
/* Avoid infinite polling loop when PSU is not under Cuda control */
switch (macintosh_config->ident) {
case MAC_MODEL_C660:
case MAC_MODEL_Q605:
case MAC_MODEL_Q605_ACC:
case MAC_MODEL_P475:
case MAC_MODEL_P475F:
return;
}
while (!req.complete)
cuda_poll();
}
#endif /* CONFIG_ADB_CUDA */
/*
*-------------------------------------------------------------------
* Below this point are the generic routines; they'll dispatch to the
* correct routine for the hardware on which we're running.
*-------------------------------------------------------------------
*/
#if IS_ENABLED(CONFIG_NVRAM)
unsigned char mac_pram_read_byte(int addr)
{
switch (macintosh_config->adb_type) {
case MAC_ADB_IOP:
case MAC_ADB_II:
case MAC_ADB_PB1:
return via_pram_read_byte(addr);
#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
return cuda_pram_read_byte(addr);
#endif
#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
return pmu_pram_read_byte(addr);
#endif
default:
return 0xFF;
}
}
void mac_pram_write_byte(unsigned char val, int addr)
{
switch (macintosh_config->adb_type) {
case MAC_ADB_IOP:
case MAC_ADB_II:
case MAC_ADB_PB1:
via_pram_write_byte(val, addr);
break;
#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
cuda_pram_write_byte(val, addr);
break;
#endif
#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
pmu_pram_write_byte(val, addr);
break;
#endif
default:
break;
}
}
ssize_t mac_pram_get_size(void)
{
return 256;
}
#endif /* CONFIG_NVRAM */
void mac_poweroff(void)
{
if (oss_present) {
oss_shutdown();
} else if (macintosh_config->adb_type == MAC_ADB_II) {
via_shutdown();
#ifdef CONFIG_ADB_CUDA
} else if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_shutdown();
#endif
#ifdef CONFIG_ADB_PMU
} else if (macintosh_config->adb_type == MAC_ADB_PB2) {
pmu_shutdown();
#endif
}
pr_crit("It is now safe to turn off your Macintosh.\n");
local_irq_disable();
while(1);
}
void mac_reset(void)
{
if (macintosh_config->adb_type == MAC_ADB_II &&
macintosh_config->ident != MAC_MODEL_SE30) {
/* need ROMBASE in booter */
/* indeed, plus need to MAP THE ROM !! */
if (mac_bi_data.rombase == 0)
mac_bi_data.rombase = 0x40800000;
/* works on some */
rom_reset = (void *) (mac_bi_data.rombase + 0xa);
local_irq_disable();
rom_reset();
#ifdef CONFIG_ADB_CUDA
} else if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_restart();
#endif
#ifdef CONFIG_ADB_PMU
} else if (macintosh_config->adb_type == MAC_ADB_PB2) {
pmu_restart();
#endif
} else if (CPU_IS_030) {
/* 030-specific reset routine. The idea is general, but the
* specific registers to reset are '030-specific. Until I
* have a non-030 machine, I can't test anything else.
* -- C. Scott Ananian <[email protected]>
*/
unsigned long rombase = 0x40000000;
/* make a 1-to-1 mapping, using the transparent tran. reg. */
unsigned long virt = (unsigned long) mac_reset;
unsigned long phys = virt_to_phys(mac_reset);
unsigned long addr = (phys&0xFF000000)|0x8777;
unsigned long offset = phys-virt;
local_irq_disable(); /* lets not screw this up, ok? */
__asm__ __volatile__(".chip 68030\n\t"
"pmove %0,%/tt0\n\t"
".chip 68k"
: : "m" (addr));
/* Now jump to physical address so we can disable MMU */
__asm__ __volatile__(
".chip 68030\n\t"
"lea %/pc@(1f),%/a0\n\t"
"addl %0,%/a0\n\t"/* fixup target address and stack ptr */
"addl %0,%/sp\n\t"
"pflusha\n\t"
"jmp %/a0@\n\t" /* jump into physical memory */
"0:.long 0\n\t" /* a constant zero. */
/* OK. Now reset everything and jump to reset vector. */
"1:\n\t"
"lea %/pc@(0b),%/a0\n\t"
"pmove %/a0@, %/tc\n\t" /* disable mmu */
"pmove %/a0@, %/tt0\n\t" /* disable tt0 */
"pmove %/a0@, %/tt1\n\t" /* disable tt1 */
"movel #0, %/a0\n\t"
"movec %/a0, %/vbr\n\t" /* clear vector base register */
"movec %/a0, %/cacr\n\t" /* disable caches */
"movel #0x0808,%/a0\n\t"
"movec %/a0, %/cacr\n\t" /* flush i&d caches */
"movew #0x2700,%/sr\n\t" /* set up status register */
"movel %1@(0x0),%/a0\n\t"/* load interrupt stack pointer */
"movec %/a0, %/isp\n\t"
"movel %1@(0x4),%/a0\n\t" /* load reset vector */
"reset\n\t" /* reset external devices */
"jmp %/a0@\n\t" /* jump to the reset vector */
".chip 68k"
: : "r" (offset), "a" (rombase) : "a0");
}
/* should never get here */
pr_crit("Restart failed. Please restart manually.\n");
local_irq_disable();
while(1);
}
/*
* This function translates seconds since 1970 into a proper date.
*
* Algorithm cribbed from glibc2.1, __offtime().
*
* This is roughly same as rtc_time64_to_tm(), which we should probably
* use here, but it's only available when CONFIG_RTC_LIB is enabled.
*/
#define SECS_PER_MINUTE (60)
#define SECS_PER_HOUR (SECS_PER_MINUTE * 60)
#define SECS_PER_DAY (SECS_PER_HOUR * 24)
static void unmktime(time64_t time, long offset,
int *yearp, int *monp, int *dayp,
int *hourp, int *minp, int *secp)
{
/* How many days come before each month (0-12). */
static const unsigned short int __mon_yday[2][13] =
{
/* Normal years. */
{ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 },
/* Leap years. */
{ 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335, 366 }
};
int days, rem, y, wday, yday;
const unsigned short int *ip;
days = div_u64_rem(time, SECS_PER_DAY, &rem);
rem += offset;
while (rem < 0) {
rem += SECS_PER_DAY;
--days;
}
while (rem >= SECS_PER_DAY) {
rem -= SECS_PER_DAY;
++days;
}
*hourp = rem / SECS_PER_HOUR;
rem %= SECS_PER_HOUR;
*minp = rem / SECS_PER_MINUTE;
*secp = rem % SECS_PER_MINUTE;
/* January 1, 1970 was a Thursday. */
wday = (4 + days) % 7; /* Day in the week. Not currently used */
if (wday < 0) wday += 7;
y = 1970;
#define DIV(a, b) ((a) / (b) - ((a) % (b) < 0))
#define LEAPS_THRU_END_OF(y) (DIV (y, 4) - DIV (y, 100) + DIV (y, 400))
#define __isleap(year) \
((year) % 4 == 0 && ((year) % 100 != 0 || (year) % 400 == 0))
while (days < 0 || days >= (__isleap (y) ? 366 : 365))
{
/* Guess a corrected year, assuming 365 days per year. */
long int yg = y + days / 365 - (days % 365 < 0);
/* Adjust DAYS and Y to match the guessed year. */
days -= (yg - y) * 365 +
LEAPS_THRU_END_OF(yg - 1) - LEAPS_THRU_END_OF(y - 1);
y = yg;
}
*yearp = y - 1900;
yday = days; /* day in the year. Not currently used. */
ip = __mon_yday[__isleap(y)];
for (y = 11; days < (long int) ip[y]; --y)
continue;
days -= ip[y];
*monp = y;
*dayp = days + 1; /* day in the month */
return;
}
/*
* Read/write the hardware clock.
*/
int mac_hwclk(int op, struct rtc_time *t)
{
time64_t now;
if (!op) { /* read */
switch (macintosh_config->adb_type) {
case MAC_ADB_IOP:
case MAC_ADB_II:
case MAC_ADB_PB1:
now = via_read_time();
break;
#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
now = cuda_get_time();
break;
#endif
#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
now = pmu_get_time();
break;
#endif
default:
now = 0;
}
t->tm_wday = 0;
unmktime(now, 0,
&t->tm_year, &t->tm_mon, &t->tm_mday,
&t->tm_hour, &t->tm_min, &t->tm_sec);
pr_debug("%s: read %ptR\n", __func__, t);
} else { /* write */
pr_debug("%s: tried to write %ptR\n", __func__, t);
switch (macintosh_config->adb_type) {
case MAC_ADB_IOP:
case MAC_ADB_II:
case MAC_ADB_PB1:
via_set_rtc_time(t);
break;
#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
cuda_set_rtc_time(t);
break;
#endif
#ifdef CONFIG_ADB_PMU
case MAC_ADB_PB2:
pmu_set_rtc_time(t);
break;
#endif
default:
return -ENODEV;
}
}
return 0;
}
| linux-master | arch/m68k/mac/misc.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/traps.h>
#include <asm/apollohw.h>
unsigned int apollo_irq_startup(struct irq_data *data)
{
unsigned int irq = data->irq;
if (irq < 8)
*(volatile unsigned char *)(pica+1) &= ~(1 << irq);
else
*(volatile unsigned char *)(picb+1) &= ~(1 << (irq - 8));
return 0;
}
void apollo_irq_shutdown(struct irq_data *data)
{
unsigned int irq = data->irq;
if (irq < 8)
*(volatile unsigned char *)(pica+1) |= (1 << irq);
else
*(volatile unsigned char *)(picb+1) |= (1 << (irq - 8));
}
void apollo_irq_eoi(struct irq_data *data)
{
*(volatile unsigned char *)(pica) = 0x20;
*(volatile unsigned char *)(picb) = 0x20;
}
static struct irq_chip apollo_irq_chip = {
.name = "apollo",
.irq_startup = apollo_irq_startup,
.irq_shutdown = apollo_irq_shutdown,
.irq_eoi = apollo_irq_eoi,
};
void __init dn_init_IRQ(void)
{
m68k_setup_user_interrupt(VEC_USER + 96, 16);
m68k_setup_irq_controller(&apollo_irq_chip, handle_fasteoi_irq,
IRQ_APOLLO, 16);
}
| linux-master | arch/m68k/apollo/dn_ints.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/console.h>
#include <linux/rtc.h>
#include <linux/vt_kern.h>
#include <linux/interrupt.h>
#include <asm/setup.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-apollo.h>
#include <asm/byteorder.h>
#include <asm/apollohw.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/config.h>
u_long sio01_physaddr;
u_long sio23_physaddr;
u_long rtc_physaddr;
u_long pica_physaddr;
u_long picb_physaddr;
u_long cpuctrl_physaddr;
u_long timer_physaddr;
u_long apollo_model;
extern void dn_sched_init(void);
extern void dn_init_IRQ(void);
extern int dn_dummy_hwclk(int, struct rtc_time *);
extern void dn_dummy_reset(void);
#ifdef CONFIG_HEARTBEAT
static void dn_heartbeat(int on);
#endif
static irqreturn_t dn_timer_int(int irq,void *);
static void dn_get_model(char *model);
static const char *apollo_models[] = {
[APOLLO_DN3000-APOLLO_DN3000] = "DN3000 (Otter)",
[APOLLO_DN3010-APOLLO_DN3000] = "DN3010 (Otter)",
[APOLLO_DN3500-APOLLO_DN3000] = "DN3500 (Cougar II)",
[APOLLO_DN4000-APOLLO_DN3000] = "DN4000 (Mink)",
[APOLLO_DN4500-APOLLO_DN3000] = "DN4500 (Roadrunner)"
};
int __init apollo_parse_bootinfo(const struct bi_record *record)
{
int unknown = 0;
const void *data = record->data;
switch (be16_to_cpu(record->tag)) {
case BI_APOLLO_MODEL:
apollo_model = be32_to_cpup(data);
break;
default:
unknown=1;
}
return unknown;
}
static void __init dn_setup_model(void)
{
pr_info("Apollo hardware found: [%s]\n",
apollo_models[apollo_model - APOLLO_DN3000]);
switch(apollo_model) {
case APOLLO_UNKNOWN:
panic("Unknown apollo model");
break;
case APOLLO_DN3000:
case APOLLO_DN3010:
sio01_physaddr=SAU8_SIO01_PHYSADDR;
rtc_physaddr=SAU8_RTC_PHYSADDR;
pica_physaddr=SAU8_PICA;
picb_physaddr=SAU8_PICB;
cpuctrl_physaddr=SAU8_CPUCTRL;
timer_physaddr=SAU8_TIMER;
break;
case APOLLO_DN4000:
sio01_physaddr=SAU7_SIO01_PHYSADDR;
sio23_physaddr=SAU7_SIO23_PHYSADDR;
rtc_physaddr=SAU7_RTC_PHYSADDR;
pica_physaddr=SAU7_PICA;
picb_physaddr=SAU7_PICB;
cpuctrl_physaddr=SAU7_CPUCTRL;
timer_physaddr=SAU7_TIMER;
break;
case APOLLO_DN4500:
panic("Apollo model not yet supported");
break;
case APOLLO_DN3500:
sio01_physaddr=SAU7_SIO01_PHYSADDR;
sio23_physaddr=SAU7_SIO23_PHYSADDR;
rtc_physaddr=SAU7_RTC_PHYSADDR;
pica_physaddr=SAU7_PICA;
picb_physaddr=SAU7_PICB;
cpuctrl_physaddr=SAU7_CPUCTRL;
timer_physaddr=SAU7_TIMER;
break;
default:
panic("Undefined apollo model");
break;
}
}
int dn_serial_console_wait_key(struct console *co) {
while(!(sio01.srb_csrb & 1))
barrier();
return sio01.rhrb_thrb;
}
void dn_serial_console_write (struct console *co, const char *str,unsigned int count)
{
while(count--) {
if (*str == '\n') {
sio01.rhrb_thrb = (unsigned char)'\r';
while (!(sio01.srb_csrb & 0x4))
;
}
sio01.rhrb_thrb = (unsigned char)*str++;
while (!(sio01.srb_csrb & 0x4))
;
}
}
void dn_serial_print (const char *str)
{
while (*str) {
if (*str == '\n') {
sio01.rhrb_thrb = (unsigned char)'\r';
while (!(sio01.srb_csrb & 0x4))
;
}
sio01.rhrb_thrb = (unsigned char)*str++;
while (!(sio01.srb_csrb & 0x4))
;
}
}
void __init config_apollo(void)
{
int i;
dn_setup_model();
mach_sched_init=dn_sched_init; /* */
mach_init_IRQ=dn_init_IRQ;
mach_hwclk = dn_dummy_hwclk; /* */
mach_reset = dn_dummy_reset; /* */
#ifdef CONFIG_HEARTBEAT
mach_heartbeat = dn_heartbeat;
#endif
mach_get_model = dn_get_model;
cpuctrl=0xaa00;
/* clear DMA translation table */
for(i=0;i<0x400;i++)
addr_xlat_map[i]=0;
}
irqreturn_t dn_timer_int(int irq, void *dev_id)
{
volatile unsigned char x;
legacy_timer_tick(1);
timer_heartbeat();
x = *(volatile unsigned char *)(apollo_timer + 3);
x = *(volatile unsigned char *)(apollo_timer + 5);
return IRQ_HANDLED;
}
void dn_sched_init(void)
{
/* program timer 1 */
*(volatile unsigned char *)(apollo_timer + 3) = 0x01;
*(volatile unsigned char *)(apollo_timer + 1) = 0x40;
*(volatile unsigned char *)(apollo_timer + 5) = 0x09;
*(volatile unsigned char *)(apollo_timer + 7) = 0xc4;
/* enable IRQ of PIC B */
*(volatile unsigned char *)(pica+1)&=(~8);
#if 0
pr_info("*(0x10803) %02x\n",
*(volatile unsigned char *)(apollo_timer + 0x3));
pr_info("*(0x10803) %02x\n",
*(volatile unsigned char *)(apollo_timer + 0x3));
#endif
if (request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", NULL))
pr_err("Couldn't register timer interrupt\n");
}
int dn_dummy_hwclk(int op, struct rtc_time *t) {
if(!op) { /* read */
t->tm_sec=rtc->second;
t->tm_min=rtc->minute;
t->tm_hour=rtc->hours;
t->tm_mday=rtc->day_of_month;
t->tm_wday=rtc->day_of_week;
t->tm_mon = rtc->month - 1;
t->tm_year=rtc->year;
if (t->tm_year < 70)
t->tm_year += 100;
} else {
rtc->second=t->tm_sec;
rtc->minute=t->tm_min;
rtc->hours=t->tm_hour;
rtc->day_of_month=t->tm_mday;
if(t->tm_wday!=-1)
rtc->day_of_week=t->tm_wday;
rtc->month = t->tm_mon + 1;
rtc->year = t->tm_year % 100;
}
return 0;
}
void dn_dummy_reset(void) {
dn_serial_print("The end !\n");
for(;;);
}
void dn_dummy_waitbut(void) {
dn_serial_print("waitbut\n");
}
static void dn_get_model(char *model)
{
strcpy(model, "Apollo ");
if (apollo_model >= APOLLO_DN3000 && apollo_model <= APOLLO_DN4500)
strcat(model, apollo_models[apollo_model - APOLLO_DN3000]);
}
#ifdef CONFIG_HEARTBEAT
static int dn_cpuctrl=0xff00;
static void dn_heartbeat(int on) {
if(on) {
dn_cpuctrl&=~0x100;
cpuctrl=dn_cpuctrl;
}
else {
dn_cpuctrl&=~0x100;
dn_cpuctrl|=0x100;
cpuctrl=dn_cpuctrl;
}
}
#endif
| linux-master | arch/m68k/apollo/config.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Real Time Clock interface for Linux on the MVME16x
*
* Based on the PC driver by Paul Gortmaker.
*/
#define RTC_VERSION "1.00"
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/ioport.h>
#include <linux/capability.h>
#include <linux/fcntl.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/rtc.h> /* For struct rtc_time and ioctls, etc */
#include <linux/bcd.h>
#include <asm/mvme16xhw.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <asm/setup.h>
/*
* We sponge a minor off of the misc major. No need slurping
* up another valuable major dev number for this. If you add
* an ioctl, make sure you don't conflict with SPARC's RTC
* ioctls.
*/
static const unsigned char days_in_mo[] =
{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
static atomic_t rtc_ready = ATOMIC_INIT(1);
static long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
volatile MK48T08ptr_t rtc = (MK48T08ptr_t)MVME_RTC_BASE;
unsigned long flags;
struct rtc_time wtime;
void __user *argp = (void __user *)arg;
switch (cmd) {
case RTC_RD_TIME: /* Read the time/date from RTC */
{
local_irq_save(flags);
/* Ensure clock and real-time-mode-register are accessible */
rtc->ctrl = RTC_READ;
memset(&wtime, 0, sizeof(struct rtc_time));
wtime.tm_sec = bcd2bin(rtc->bcd_sec);
wtime.tm_min = bcd2bin(rtc->bcd_min);
wtime.tm_hour = bcd2bin(rtc->bcd_hr);
wtime.tm_mday = bcd2bin(rtc->bcd_dom);
wtime.tm_mon = bcd2bin(rtc->bcd_mth)-1;
wtime.tm_year = bcd2bin(rtc->bcd_year);
if (wtime.tm_year < 70)
wtime.tm_year += 100;
wtime.tm_wday = bcd2bin(rtc->bcd_dow)-1;
rtc->ctrl = 0;
local_irq_restore(flags);
return copy_to_user(argp, &wtime, sizeof wtime) ?
-EFAULT : 0;
}
case RTC_SET_TIME: /* Set the RTC */
{
struct rtc_time rtc_tm;
unsigned char mon, day, hrs, min, sec, leap_yr;
unsigned int yrs;
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
if (copy_from_user(&rtc_tm, argp, sizeof(struct rtc_time)))
return -EFAULT;
yrs = rtc_tm.tm_year;
if (yrs < 1900)
yrs += 1900;
mon = rtc_tm.tm_mon + 1; /* tm_mon starts at zero */
day = rtc_tm.tm_mday;
hrs = rtc_tm.tm_hour;
min = rtc_tm.tm_min;
sec = rtc_tm.tm_sec;
leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400));
if ((mon > 12) || (day == 0))
return -EINVAL;
if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr)))
return -EINVAL;
if ((hrs >= 24) || (min >= 60) || (sec >= 60))
return -EINVAL;
if (yrs >= 2070)
return -EINVAL;
local_irq_save(flags);
rtc->ctrl = RTC_WRITE;
rtc->bcd_sec = bin2bcd(sec);
rtc->bcd_min = bin2bcd(min);
rtc->bcd_hr = bin2bcd(hrs);
rtc->bcd_dom = bin2bcd(day);
rtc->bcd_mth = bin2bcd(mon);
rtc->bcd_year = bin2bcd(yrs%100);
rtc->ctrl = 0;
local_irq_restore(flags);
return 0;
}
default:
return -EINVAL;
}
}
/*
* We enforce only one user at a time here with the open/close.
*/
static int rtc_open(struct inode *inode, struct file *file)
{
if( !atomic_dec_and_test(&rtc_ready) )
{
atomic_inc( &rtc_ready );
return -EBUSY;
}
return 0;
}
static int rtc_release(struct inode *inode, struct file *file)
{
atomic_inc( &rtc_ready );
return 0;
}
/*
* The various file operations we support.
*/
static const struct file_operations rtc_fops = {
.unlocked_ioctl = rtc_ioctl,
.open = rtc_open,
.release = rtc_release,
.llseek = noop_llseek,
};
static struct miscdevice rtc_dev=
{
.minor = RTC_MINOR,
.name = "rtc",
.fops = &rtc_fops
};
static int __init rtc_MK48T08_init(void)
{
if (!MACH_IS_MVME16x)
return -ENODEV;
pr_info("MK48T08 Real Time Clock Driver v%s\n", RTC_VERSION);
return misc_register(&rtc_dev);
}
device_initcall(rtc_MK48T08_init);
| linux-master | arch/m68k/mvme16x/rtc.c |
/*
* arch/m68k/mvme16x/config.c
*
* Copyright (C) 1995 Richard Hirst [[email protected]]
*
* Based on:
*
* linux/amiga/config.c
*
* Copyright (C) 1993 Hamish Macdonald
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file README.legal in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/seq_file.h>
#include <linux/tty.h>
#include <linux/clocksource.h>
#include <linux/console.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/rtc.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-vme.h>
#include <asm/byteorder.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/mvme16xhw.h>
#include <asm/config.h>
extern t_bdid mvme_bdid;
static MK48T08ptr_t volatile rtc = (MK48T08ptr_t)MVME_RTC_BASE;
static void mvme16x_get_model(char *model);
extern void mvme16x_sched_init(void);
extern int mvme16x_hwclk (int, struct rtc_time *);
extern void mvme16x_reset (void);
int bcd2int (unsigned char b);
unsigned short mvme16x_config;
EXPORT_SYMBOL(mvme16x_config);
int __init mvme16x_parse_bootinfo(const struct bi_record *bi)
{
uint16_t tag = be16_to_cpu(bi->tag);
if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO)
return 0;
else
return 1;
}
void mvme16x_reset(void)
{
pr_info("\r\n\nCalled mvme16x_reset\r\n"
"\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r");
/* The string of returns is to delay the reset until the whole
* message is output. Assert reset bit in GCSR */
*(volatile char *)0xfff40107 = 0x80;
}
static void mvme16x_get_model(char *model)
{
p_bdid p = &mvme_bdid;
char suf[4];
suf[1] = p->brdsuffix[0];
suf[2] = p->brdsuffix[1];
suf[3] = '\0';
suf[0] = suf[1] ? '-' : '\0';
sprintf(model, "Motorola MVME%x%s", be16_to_cpu(p->brdno), suf);
}
static void mvme16x_get_hardware_list(struct seq_file *m)
{
uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
if (brdno == 0x0162 || brdno == 0x0172)
{
unsigned char rev = *(unsigned char *)MVME162_VERSION_REG;
seq_printf (m, "VMEchip2 %spresent\n",
rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : "");
seq_printf (m, "SCSI interface %spresent\n",
rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : "");
seq_printf (m, "Ethernet i/f %spresent\n",
rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : "");
}
}
/*
* This function is called during kernel startup to initialize
* the mvme16x IRQ handling routines. Should probably ensure
* that the base vectors for the VMEChip2 and PCCChip2 are valid.
*/
static void __init mvme16x_init_IRQ (void)
{
m68k_setup_user_interrupt(VEC_USER, 192);
}
#define PCC2CHIP (0xfff42000)
#define PCCSCCMICR (PCC2CHIP + 0x1d)
#define PCCSCCTICR (PCC2CHIP + 0x1e)
#define PCCSCCRICR (PCC2CHIP + 0x1f)
#define PCCTPIACKR (PCC2CHIP + 0x25)
#ifdef CONFIG_EARLY_PRINTK
/**** cd2401 registers ****/
#define CD2401_ADDR (0xfff45000)
#define CyGFRCR (0x81)
#define CyCCR (0x13)
#define CyCLR_CHAN (0x40)
#define CyINIT_CHAN (0x20)
#define CyCHIP_RESET (0x10)
#define CyENB_XMTR (0x08)
#define CyDIS_XMTR (0x04)
#define CyENB_RCVR (0x02)
#define CyDIS_RCVR (0x01)
#define CyCAR (0xee)
#define CyIER (0x11)
#define CyMdmCh (0x80)
#define CyRxExc (0x20)
#define CyRxData (0x08)
#define CyTxMpty (0x02)
#define CyTxRdy (0x01)
#define CyLICR (0x26)
#define CyRISR (0x89)
#define CyTIMEOUT (0x80)
#define CySPECHAR (0x70)
#define CyOVERRUN (0x08)
#define CyPARITY (0x04)
#define CyFRAME (0x02)
#define CyBREAK (0x01)
#define CyREOIR (0x84)
#define CyTEOIR (0x85)
#define CyMEOIR (0x86)
#define CyNOTRANS (0x08)
#define CyRFOC (0x30)
#define CyRDR (0xf8)
#define CyTDR (0xf8)
#define CyMISR (0x8b)
#define CyRISR (0x89)
#define CyTISR (0x8a)
#define CyMSVR1 (0xde)
#define CyMSVR2 (0xdf)
#define CyDSR (0x80)
#define CyDCD (0x40)
#define CyCTS (0x20)
#define CyDTR (0x02)
#define CyRTS (0x01)
#define CyRTPRL (0x25)
#define CyRTPRH (0x24)
#define CyCOR1 (0x10)
#define CyPARITY_NONE (0x00)
#define CyPARITY_E (0x40)
#define CyPARITY_O (0xC0)
#define Cy_5_BITS (0x04)
#define Cy_6_BITS (0x05)
#define Cy_7_BITS (0x06)
#define Cy_8_BITS (0x07)
#define CyCOR2 (0x17)
#define CyETC (0x20)
#define CyCtsAE (0x02)
#define CyCOR3 (0x16)
#define Cy_1_STOP (0x02)
#define Cy_2_STOP (0x04)
#define CyCOR4 (0x15)
#define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
#define CyCOR5 (0x14)
#define CyCOR6 (0x18)
#define CyCOR7 (0x07)
#define CyRBPR (0xcb)
#define CyRCOR (0xc8)
#define CyTBPR (0xc3)
#define CyTCOR (0xc0)
#define CySCHR1 (0x1f)
#define CySCHR2 (0x1e)
#define CyTPR (0xda)
#define CyPILR1 (0xe3)
#define CyPILR2 (0xe0)
#define CyPILR3 (0xe1)
#define CyCMR (0x1b)
#define CyASYNC (0x02)
#define CyLICR (0x26)
#define CyLIVR (0x09)
#define CySCRL (0x23)
#define CySCRH (0x22)
#define CyTFTC (0x80)
void mvme16x_cons_write(struct console *co, const char *str, unsigned count)
{
volatile unsigned char *base_addr = (u_char *)CD2401_ADDR;
volatile u_char sink;
u_char ier;
int port;
u_char do_lf = 0;
int i = 0;
/* Ensure transmitter is enabled! */
port = 0;
base_addr[CyCAR] = (u_char)port;
while (base_addr[CyCCR])
;
base_addr[CyCCR] = CyENB_XMTR;
ier = base_addr[CyIER];
base_addr[CyIER] = CyTxMpty;
while (1) {
if (in_8(PCCSCCTICR) & 0x20)
{
/* We have a Tx int. Acknowledge it */
sink = in_8(PCCTPIACKR);
if ((base_addr[CyLICR] >> 2) == port) {
if (i == count) {
/* Last char of string is now output */
base_addr[CyTEOIR] = CyNOTRANS;
break;
}
if (do_lf) {
base_addr[CyTDR] = '\n';
str++;
i++;
do_lf = 0;
}
else if (*str == '\n') {
base_addr[CyTDR] = '\r';
do_lf = 1;
}
else {
base_addr[CyTDR] = *str++;
i++;
}
base_addr[CyTEOIR] = 0;
}
else
base_addr[CyTEOIR] = CyNOTRANS;
}
}
base_addr[CyIER] = ier;
}
#endif
void __init config_mvme16x(void)
{
p_bdid p = &mvme_bdid;
char id[40];
uint16_t brdno = be16_to_cpu(p->brdno);
mach_sched_init = mvme16x_sched_init;
mach_init_IRQ = mvme16x_init_IRQ;
mach_hwclk = mvme16x_hwclk;
mach_reset = mvme16x_reset;
mach_get_model = mvme16x_get_model;
mach_get_hardware_list = mvme16x_get_hardware_list;
/* Report board revision */
if (strncmp("BDID", p->bdid, 4))
{
pr_crit("Bug call .BRD_ID returned garbage - giving up\n");
while (1)
;
}
/* Board type is only set by newer versions of vmelilo/tftplilo */
if (vme_brdtype == 0)
vme_brdtype = brdno;
mvme16x_get_model(id);
pr_info("BRD_ID: %s BUG %x.%x %02x/%02x/%02x\n", id, p->rev >> 4,
p->rev & 0xf, p->yr, p->mth, p->day);
if (brdno == 0x0162 || brdno == 0x172)
{
unsigned char rev = *(unsigned char *)MVME162_VERSION_REG;
mvme16x_config = rev | MVME16x_CONFIG_GOT_SCCA;
pr_info("MVME%x Hardware status:\n", brdno);
pr_info(" CPU Type 68%s040\n",
rev & MVME16x_CONFIG_GOT_FPU ? "" : "LC");
pr_info(" CPU clock %dMHz\n",
rev & MVME16x_CONFIG_SPEED_32 ? 32 : 25);
pr_info(" VMEchip2 %spresent\n",
rev & MVME16x_CONFIG_NO_VMECHIP2 ? "NOT " : "");
pr_info(" SCSI interface %spresent\n",
rev & MVME16x_CONFIG_NO_SCSICHIP ? "NOT " : "");
pr_info(" Ethernet interface %spresent\n",
rev & MVME16x_CONFIG_NO_ETHERNET ? "NOT " : "");
}
else
{
mvme16x_config = MVME16x_CONFIG_GOT_LP | MVME16x_CONFIG_GOT_CD2401;
}
}
static irqreturn_t mvme16x_abort_int (int irq, void *dev_id)
{
unsigned long *new = (unsigned long *)vectors;
unsigned long *old = (unsigned long *)0xffe00000;
volatile unsigned char uc, *ucp;
uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
if (brdno == 0x0162 || brdno == 0x172)
{
ucp = (volatile unsigned char *)0xfff42043;
uc = *ucp | 8;
*ucp = uc;
}
else
{
*(volatile unsigned long *)0xfff40074 = 0x40000000;
}
*(new+4) = *(old+4); /* Illegal instruction */
*(new+9) = *(old+9); /* Trace */
*(new+47) = *(old+47); /* Trap #15 */
if (brdno == 0x0162 || brdno == 0x172)
*(new+0x5e) = *(old+0x5e); /* ABORT switch */
else
*(new+0x6e) = *(old+0x6e); /* ABORT switch */
return IRQ_HANDLED;
}
static u64 mvme16x_read_clk(struct clocksource *cs);
static struct clocksource mvme16x_clk = {
.name = "pcc",
.rating = 250,
.read = mvme16x_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static u32 clk_total;
#define PCC_TIMER_CLOCK_FREQ 1000000
#define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ)
#define PCCTCMP1 (PCC2CHIP + 0x04)
#define PCCTCNT1 (PCC2CHIP + 0x08)
#define PCCTOVR1 (PCC2CHIP + 0x17)
#define PCCTIC1 (PCC2CHIP + 0x1b)
#define PCCTOVR1_TIC_EN 0x01
#define PCCTOVR1_COC_EN 0x02
#define PCCTOVR1_OVR_CLR 0x04
#define PCCTIC1_INT_LEVEL 6
#define PCCTIC1_INT_CLR 0x08
#define PCCTIC1_INT_EN 0x10
static irqreturn_t mvme16x_timer_int (int irq, void *dev_id)
{
unsigned long flags;
local_irq_save(flags);
out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL);
clk_total += PCC_TIMER_CYCLES;
legacy_timer_tick(1);
local_irq_restore(flags);
return IRQ_HANDLED;
}
void mvme16x_sched_init(void)
{
uint16_t brdno = be16_to_cpu(mvme_bdid.brdno);
int irq;
/* Using PCCchip2 or MC2 chip tick timer 1 */
if (request_irq(MVME16x_IRQ_TIMER, mvme16x_timer_int, IRQF_TIMER, "timer",
NULL))
panic ("Couldn't register timer int");
out_be32(PCCTCNT1, 0);
out_be32(PCCTCMP1, PCC_TIMER_CYCLES);
out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL);
clocksource_register_hz(&mvme16x_clk, PCC_TIMER_CLOCK_FREQ);
if (brdno == 0x0162 || brdno == 0x172)
irq = MVME162_IRQ_ABORT;
else
irq = MVME167_IRQ_ABORT;
if (request_irq(irq, mvme16x_abort_int, 0,
"abort", mvme16x_abort_int))
panic ("Couldn't register abort int");
}
static u64 mvme16x_read_clk(struct clocksource *cs)
{
unsigned long flags;
u8 overflow, tmp;
u32 ticks;
local_irq_save(flags);
tmp = in_8(PCCTOVR1) >> 4;
ticks = in_be32(PCCTCNT1);
overflow = in_8(PCCTOVR1) >> 4;
if (overflow != tmp)
ticks = in_be32(PCCTCNT1);
ticks += overflow * PCC_TIMER_CYCLES;
ticks += clk_total;
local_irq_restore(flags);
return ticks;
}
int bcd2int (unsigned char b)
{
return ((b>>4)*10 + (b&15));
}
int mvme16x_hwclk(int op, struct rtc_time *t)
{
if (!op) {
rtc->ctrl = RTC_READ;
t->tm_year = bcd2int (rtc->bcd_year);
t->tm_mon = bcd2int(rtc->bcd_mth) - 1;
t->tm_mday = bcd2int (rtc->bcd_dom);
t->tm_hour = bcd2int (rtc->bcd_hr);
t->tm_min = bcd2int (rtc->bcd_min);
t->tm_sec = bcd2int (rtc->bcd_sec);
rtc->ctrl = 0;
if (t->tm_year < 70)
t->tm_year += 100;
} else {
/* FIXME Setting the time is not yet supported */
return -EOPNOTSUPP;
}
return 0;
}
| linux-master | arch/m68k/mvme16x/config.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne
* Copyright (C) 2001 Georges Menie, Ken Desmet
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <asm/bootstd.h>
#include <asm/machdep.h>
#include <asm/MC68VZ328.h>
#include "m68328.h"
static int errno;
static _bsc0(char *, getserialnum)
static _bsc1(unsigned char *, gethwaddr, int, a)
static _bsc1(char *, getbenv, char *, a)
void __init init_ucsimm(char *command, int size)
{
char *p;
pr_info("uCsimm/uCdimm serial string [%s]\n", getserialnum());
p = gethwaddr(0);
pr_info("uCsimm/uCdimm hwaddr %pM\n", p);
p = getbenv("APPEND");
if (p)
strcpy(p, command);
else
command[0] = 0;
}
| linux-master | arch/m68k/68000/ucsimm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne
* Copyright (C) 2001 Georges Menie, Ken Desmet
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <asm/machdep.h>
#include <asm/MC68VZ328.h>
#include "m68328.h"
#include "screen.h"
/***************************************************************************/
/* Init Dragon Engine II hardware */
/***************************************************************************/
static void dragen2_reset(void)
{
local_irq_disable();
#ifdef CONFIG_INIT_LCD
PBDATA |= 0x20; /* disable CCFL light */
PKDATA |= 0x4; /* disable LCD controller */
LCKCON = 0;
#endif
__asm__ __volatile__(
"reset\n\t"
"moveal #0x04000000, %a0\n\t"
"moveal 0(%a0), %sp\n\t"
"moveal 4(%a0), %a0\n\t"
"jmp (%a0)"
);
}
void __init init_dragen2(char *command, int size)
{
mach_reset = dragen2_reset;
#ifdef CONFIG_DIRECT_IO_ACCESS
SCR = 0x10; /* allow user access to internal registers */
#endif
/* CSGB Init */
CSGBB = 0x4000;
CSB = 0x1a1;
/* CS8900 init */
/* PK3: hardware sleep function pin, active low */
PKSEL |= PK(3); /* select pin as I/O */
PKDIR |= PK(3); /* select pin as output */
PKDATA |= PK(3); /* set pin high */
/* PF5: hardware reset function pin, active high */
PFSEL |= PF(5); /* select pin as I/O */
PFDIR |= PF(5); /* select pin as output */
PFDATA &= ~PF(5); /* set pin low */
/* cs8900 hardware reset */
PFDATA |= PF(5);
{ int i; for (i = 0; i < 32000; ++i); }
PFDATA &= ~PF(5);
/* INT1 enable (cs8900 IRQ) */
PDPOL &= ~PD(1); /* active high signal */
PDIQEG &= ~PD(1);
PDIRQEN |= PD(1); /* IRQ enabled */
#ifdef CONFIG_INIT_LCD
/* initialize LCD controller */
LSSA = (long) screen_bits;
LVPW = 0x14;
LXMAX = 0x140;
LYMAX = 0xef;
LRRA = 0;
LPXCD = 3;
LPICF = 0x08;
LPOLCF = 0;
LCKCON = 0x80;
PCPDEN = 0xff;
PCSEL = 0;
/* Enable LCD controller */
PKDIR |= 0x4;
PKSEL |= 0x4;
PKDATA &= ~0x4;
/* Enable CCFL backlighting circuit */
PBDIR |= 0x20;
PBSEL |= 0x20;
PBDATA &= ~0x20;
/* contrast control register */
PFDIR |= 0x1;
PFSEL &= ~0x1;
PWMR = 0x037F;
#endif
}
| linux-master | arch/m68k/68000/dragen2.c |
/*
* ints.c - Generic interrupt controller support
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Copyright 1996 Roman Zippel
* Copyright 1999 D. Jeff Dionne <[email protected]>
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/machdep.h>
#if defined(CONFIG_M68EZ328)
#include <asm/MC68EZ328.h>
#elif defined(CONFIG_M68VZ328)
#include <asm/MC68VZ328.h>
#else
#include <asm/MC68328.h>
#endif
/* assembler routines */
asmlinkage void system_call(void);
asmlinkage void buserr(void);
asmlinkage void trap(void);
asmlinkage void trap3(void);
asmlinkage void trap4(void);
asmlinkage void trap5(void);
asmlinkage void trap6(void);
asmlinkage void trap7(void);
asmlinkage void trap8(void);
asmlinkage void trap9(void);
asmlinkage void trap10(void);
asmlinkage void trap11(void);
asmlinkage void trap12(void);
asmlinkage void trap13(void);
asmlinkage void trap14(void);
asmlinkage void trap15(void);
asmlinkage void trap33(void);
asmlinkage void trap34(void);
asmlinkage void trap35(void);
asmlinkage void trap36(void);
asmlinkage void trap37(void);
asmlinkage void trap38(void);
asmlinkage void trap39(void);
asmlinkage void trap40(void);
asmlinkage void trap41(void);
asmlinkage void trap42(void);
asmlinkage void trap43(void);
asmlinkage void trap44(void);
asmlinkage void trap45(void);
asmlinkage void trap46(void);
asmlinkage void trap47(void);
asmlinkage irqreturn_t bad_interrupt(int, void *);
asmlinkage irqreturn_t inthandler(void);
asmlinkage irqreturn_t inthandler1(void);
asmlinkage irqreturn_t inthandler2(void);
asmlinkage irqreturn_t inthandler3(void);
asmlinkage irqreturn_t inthandler4(void);
asmlinkage irqreturn_t inthandler5(void);
asmlinkage irqreturn_t inthandler6(void);
asmlinkage irqreturn_t inthandler7(void);
/* The 68k family did not have a good way to determine the source
* of interrupts until later in the family. The EC000 core does
* not provide the vector number on the stack, we vector everything
* into one vector and look in the blasted mask register...
* This code is designed to be fast, almost constant time, not clean!
*/
void process_int(int vec, struct pt_regs *fp)
{
int irq;
int mask;
unsigned long pend = ISR;
while (pend) {
if (pend & 0x0000ffff) {
if (pend & 0x000000ff) {
if (pend & 0x0000000f) {
mask = 0x00000001;
irq = 0;
} else {
mask = 0x00000010;
irq = 4;
}
} else {
if (pend & 0x00000f00) {
mask = 0x00000100;
irq = 8;
} else {
mask = 0x00001000;
irq = 12;
}
}
} else {
if (pend & 0x00ff0000) {
if (pend & 0x000f0000) {
mask = 0x00010000;
irq = 16;
} else {
mask = 0x00100000;
irq = 20;
}
} else {
if (pend & 0x0f000000) {
mask = 0x01000000;
irq = 24;
} else {
mask = 0x10000000;
irq = 28;
}
}
}
while (! (mask & pend)) {
mask <<=1;
irq++;
}
do_IRQ(irq, fp);
pend &= ~mask;
}
}
static void intc_irq_unmask(struct irq_data *d)
{
IMR &= ~(1 << d->irq);
}
static void intc_irq_mask(struct irq_data *d)
{
IMR |= (1 << d->irq);
}
static struct irq_chip intc_irq_chip = {
.name = "M68K-INTC",
.irq_mask = intc_irq_mask,
.irq_unmask = intc_irq_unmask,
};
/*
* This function should be called during kernel startup to initialize
* the machine vector table.
*/
void __init trap_init(void)
{
int i;
/* set up the vectors */
for (i = 72; i < 256; ++i)
_ramvec[i] = (e_vector) bad_interrupt;
_ramvec[32] = system_call;
_ramvec[65] = (e_vector) inthandler1;
_ramvec[66] = (e_vector) inthandler2;
_ramvec[67] = (e_vector) inthandler3;
_ramvec[68] = (e_vector) inthandler4;
_ramvec[69] = (e_vector) inthandler5;
_ramvec[70] = (e_vector) inthandler6;
_ramvec[71] = (e_vector) inthandler7;
}
void __init init_IRQ(void)
{
int i;
IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
/* turn off all interrupts */
IMR = ~0;
for (i = 0; (i < NR_IRQS); i++) {
irq_set_chip(i, &intc_irq_chip);
irq_set_handler(i, handle_level_irq);
}
}
| linux-master | arch/m68k/68000/ints.c |
/***************************************************************************/
/*
* timers.c - Generic hardware timer support.
*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne
* Copyright (C) 2001 Georges Menie, Ken Desmet
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/***************************************************************************/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/rtc.h>
#include <asm/setup.h>
#include <asm/machdep.h>
#include <asm/MC68VZ328.h>
/***************************************************************************/
#if defined(CONFIG_DRAGEN2)
/* with a 33.16 MHz clock, this will give usec resolution to the time functions */
#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK
#define CLOCK_PRE 7
#define TICKS_PER_JIFFY 41450
#elif defined(CONFIG_XCOPILOT_BUGS)
/*
* The only thing I know is that CLK32 is not available on Xcopilot
* I have little idea about what frequency SYSCLK has on Xcopilot.
* The values for prescaler and compare registers were simply
* taken from the original source
*/
#define CLOCK_SOURCE TCTL_CLKSOURCE_SYSCLK
#define CLOCK_PRE 2
#define TICKS_PER_JIFFY 0xd7e4
#else
/* default to using the 32Khz clock */
#define CLOCK_SOURCE TCTL_CLKSOURCE_32KHZ
#define CLOCK_PRE 31
#define TICKS_PER_JIFFY 10
#endif
static u32 m68328_tick_cnt;
/***************************************************************************/
static irqreturn_t hw_tick(int irq, void *dummy)
{
/* Reset Timer1 */
TSTAT &= 0;
m68328_tick_cnt += TICKS_PER_JIFFY;
legacy_timer_tick(1);
return IRQ_HANDLED;
}
/***************************************************************************/
static u64 m68328_read_clk(struct clocksource *cs)
{
unsigned long flags;
u32 cycles;
local_irq_save(flags);
cycles = m68328_tick_cnt + TCN;
local_irq_restore(flags);
return cycles;
}
/***************************************************************************/
static struct clocksource m68328_clk = {
.name = "timer",
.rating = 250,
.read = m68328_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
/***************************************************************************/
void hw_timer_init(void)
{
int ret;
/* disable timer 1 */
TCTL = 0;
/* set ISR */
ret = request_irq(TMR_IRQ_NUM, hw_tick, IRQF_TIMER, "timer", NULL);
if (ret) {
pr_err("Failed to request irq %d (timer): %pe\n", TMR_IRQ_NUM,
ERR_PTR(ret));
}
/* Restart mode, Enable int, Set clock source */
TCTL = TCTL_OM | TCTL_IRQEN | CLOCK_SOURCE;
TPRER = CLOCK_PRE;
TCMP = TICKS_PER_JIFFY;
/* Enable timer 1 */
TCTL |= TCTL_TEN;
clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
}
/***************************************************************************/
int m68328_hwclk(int set, struct rtc_time *t)
{
if (!set) {
long now = RTCTIME;
t->tm_year = 1;
t->tm_mon = 0;
t->tm_mday = 1;
t->tm_hour = (now >> 24) % 24;
t->tm_min = (now >> 16) % 60;
t->tm_sec = now % 60;
}
return 0;
}
/***************************************************************************/
| linux-master | arch/m68k/68000/timers.c |
/***************************************************************************/
/*
* m68328.c - 68328/68EZ328/68VZ328 specific config
*
* Copyright (C) 1993 Hamish Macdonald
* Copyright (C) 1999 D. Jeff Dionne
* Copyright (C) 2001 Georges Menie, Ken Desmet
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* VZ Support/Fixes Evan Stawnyczy <[email protected]>
*/
/***************************************************************************/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/rtc.h>
#include <asm/machdep.h>
#if defined(CONFIG_INIT_LCD) && defined(CONFIG_M68VZ328)
#include "bootlogo-vz.h"
#elif defined(CONFIG_PILOT) || defined(CONFIG_INIT_LCD)
#include "bootlogo.h"
#endif
#include "m68328.h"
/***************************************************************************/
static void m68328_reset(void)
{
local_irq_disable();
asm volatile ("moveal #0x10c00000, %a0;\n\t"
"moveb #0, 0xFFFFF300;\n\t"
"moveal 0(%a0), %sp;\n\t"
"moveal 4(%a0), %a0;\n\t"
"jmp (%a0);");
}
/***************************************************************************/
void __init config_BSP(char *command, int len)
{
mach_sched_init = hw_timer_init;
mach_hwclk = m68328_hwclk;
mach_reset = m68328_reset;
#if defined(CONFIG_PILOT) && defined(CONFIG_M68328)
mach_sched_init = NULL;
#elif defined(CONFIG_UCSIMM)
init_ucsimm(command, len);
#elif defined(CONFIG_UCDIMM)
init_ucsimm(command, len);
#elif defined(CONFIG_DRAGEN2)
init_dragen2(command, len);
#endif
}
/***************************************************************************/
| linux-master | arch/m68k/68000/m68328.c |
// SPDX-License-Identifier: GPL-2.0
/*
** linux/amiga/chipram.c
**
** Modified 03-May-94 by Geert Uytterhoeven <[email protected]>
** - 64-bit aligned allocations for full AGA compatibility
**
** Rewritten 15/9/2000 by Geert to use resource management
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/module.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/amigahw.h>
unsigned long amiga_chip_size;
EXPORT_SYMBOL(amiga_chip_size);
static struct resource chipram_res = {
.name = "Chip RAM", .start = CHIP_PHYSADDR
};
static atomic_t chipavail;
void __init amiga_chip_init(void)
{
if (!AMIGAHW_PRESENT(CHIP_RAM))
return;
chipram_res.end = CHIP_PHYSADDR + amiga_chip_size - 1;
request_resource(&iomem_resource, &chipram_res);
atomic_set(&chipavail, amiga_chip_size);
}
void *amiga_chip_alloc(unsigned long size, const char *name)
{
struct resource *res;
void *p;
res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
return NULL;
res->name = name;
p = amiga_chip_alloc_res(size, res);
if (!p) {
kfree(res);
return NULL;
}
return p;
}
EXPORT_SYMBOL(amiga_chip_alloc);
/*
* Warning:
* amiga_chip_alloc_res is meant only for drivers that need to
* allocate Chip RAM before kmalloc() is functional. As a consequence,
* those drivers must not free that Chip RAM afterwards.
*/
void *amiga_chip_alloc_res(unsigned long size, struct resource *res)
{
int error;
/* round up */
size = PAGE_ALIGN(size);
pr_debug("amiga_chip_alloc_res: allocate %lu bytes\n", size);
error = allocate_resource(&chipram_res, res, size, 0, UINT_MAX,
PAGE_SIZE, NULL, NULL);
if (error < 0) {
pr_err("amiga_chip_alloc_res: allocate_resource() failed %d!\n",
error);
return NULL;
}
atomic_sub(size, &chipavail);
pr_debug("amiga_chip_alloc_res: returning %pR\n", res);
return ZTWO_VADDR(res->start);
}
void amiga_chip_free(void *ptr)
{
unsigned long start = ZTWO_PADDR(ptr);
struct resource *res;
unsigned long size;
res = lookup_resource(&chipram_res, start);
if (!res) {
pr_err("amiga_chip_free: trying to free nonexistent region at "
"%p\n", ptr);
return;
}
size = resource_size(res);
pr_debug("amiga_chip_free: free %lu bytes at %p\n", size, ptr);
atomic_add(size, &chipavail);
release_resource(res);
kfree(res);
}
EXPORT_SYMBOL(amiga_chip_free);
unsigned long amiga_chip_avail(void)
{
unsigned long n = atomic_read(&chipavail);
pr_debug("amiga_chip_avail : %lu bytes\n", n);
return n;
}
EXPORT_SYMBOL(amiga_chip_avail);
| linux-master | arch/m68k/amiga/chipram.c |
/*
* Amiga Linux interrupt handling code
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/amigahw.h>
#include <asm/amigaints.h>
#include <asm/amipcmcia.h>
/*
* Enable/disable a particular machine specific interrupt source.
* Note that this may affect other interrupts in case of a shared interrupt.
* This function should only be called for a _very_ short time to change some
* internal data, that may not be changed by the interrupt at the same time.
*/
static void amiga_irq_enable(struct irq_data *data)
{
amiga_custom.intena = IF_SETCLR | (1 << (data->irq - IRQ_USER));
}
static void amiga_irq_disable(struct irq_data *data)
{
amiga_custom.intena = 1 << (data->irq - IRQ_USER);
}
static struct irq_chip amiga_irq_chip = {
.name = "amiga",
.irq_enable = amiga_irq_enable,
.irq_disable = amiga_irq_disable,
};
/*
* The builtin Amiga hardware interrupt handlers.
*/
static void ami_int1(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
/* if serial transmit buffer empty, interrupt */
if (ints & IF_TBE) {
amiga_custom.intreq = IF_TBE;
generic_handle_irq(IRQ_AMIGA_TBE);
}
/* if floppy disk transfer complete, interrupt */
if (ints & IF_DSKBLK) {
amiga_custom.intreq = IF_DSKBLK;
generic_handle_irq(IRQ_AMIGA_DSKBLK);
}
/* if software interrupt set, interrupt */
if (ints & IF_SOFT) {
amiga_custom.intreq = IF_SOFT;
generic_handle_irq(IRQ_AMIGA_SOFT);
}
}
static void ami_int3(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
/* if a blitter interrupt */
if (ints & IF_BLIT) {
amiga_custom.intreq = IF_BLIT;
generic_handle_irq(IRQ_AMIGA_BLIT);
}
/* if a copper interrupt */
if (ints & IF_COPER) {
amiga_custom.intreq = IF_COPER;
generic_handle_irq(IRQ_AMIGA_COPPER);
}
/* if a vertical blank interrupt */
if (ints & IF_VERTB) {
amiga_custom.intreq = IF_VERTB;
generic_handle_irq(IRQ_AMIGA_VERTB);
}
}
static void ami_int4(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
/* if audio 0 interrupt */
if (ints & IF_AUD0) {
amiga_custom.intreq = IF_AUD0;
generic_handle_irq(IRQ_AMIGA_AUD0);
}
/* if audio 1 interrupt */
if (ints & IF_AUD1) {
amiga_custom.intreq = IF_AUD1;
generic_handle_irq(IRQ_AMIGA_AUD1);
}
/* if audio 2 interrupt */
if (ints & IF_AUD2) {
amiga_custom.intreq = IF_AUD2;
generic_handle_irq(IRQ_AMIGA_AUD2);
}
/* if audio 3 interrupt */
if (ints & IF_AUD3) {
amiga_custom.intreq = IF_AUD3;
generic_handle_irq(IRQ_AMIGA_AUD3);
}
}
static void ami_int5(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
/* if serial receive buffer full interrupt */
if (ints & IF_RBF) {
/* acknowledge of IF_RBF must be done by the serial interrupt */
generic_handle_irq(IRQ_AMIGA_RBF);
}
/* if a disk sync interrupt */
if (ints & IF_DSKSYN) {
amiga_custom.intreq = IF_DSKSYN;
generic_handle_irq(IRQ_AMIGA_DSKSYN);
}
}
/*
* void amiga_init_IRQ(void)
*
* Parameters: None
*
* Returns: Nothing
*
* This function should be called during kernel startup to initialize
* the amiga IRQ handling routines.
*/
void __init amiga_init_IRQ(void)
{
m68k_setup_irq_controller(&amiga_irq_chip, handle_simple_irq, IRQ_USER,
AMI_STD_IRQS);
irq_set_chained_handler(IRQ_AUTO_1, ami_int1);
irq_set_chained_handler(IRQ_AUTO_3, ami_int3);
irq_set_chained_handler(IRQ_AUTO_4, ami_int4);
irq_set_chained_handler(IRQ_AUTO_5, ami_int5);
/* turn off PCMCIA interrupts */
if (AMIGAHW_PRESENT(PCMCIA))
gayle.inten = GAYLE_IRQ_IDE;
/* turn off all interrupts and enable the master interrupt bit */
amiga_custom.intena = 0x7fff;
amiga_custom.intreq = 0x7fff;
amiga_custom.intena = IF_SETCLR | IF_INTEN;
cia_init_IRQ(&ciaa_base);
cia_init_IRQ(&ciab_base);
}
| linux-master | arch/m68k/amiga/amiints.c |
/*
* Copyright (C) 2007-2009 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/zorro.h>
#include <asm/amigahw.h>
#include <asm/amigayle.h>
#include <asm/byteorder.h>
#ifdef CONFIG_ZORRO
static const struct resource zorro_resources[] __initconst = {
/* Zorro II regions (on Zorro II/III) */
{
.name = "Zorro II exp",
.start = 0x00e80000,
.end = 0x00efffff,
.flags = IORESOURCE_MEM,
}, {
.name = "Zorro II mem",
.start = 0x00200000,
.end = 0x009fffff,
.flags = IORESOURCE_MEM,
},
/* Zorro III regions (on Zorro III only) */
{
.name = "Zorro III exp",
.start = 0xff000000,
.end = 0xffffffff,
.flags = IORESOURCE_MEM,
}, {
.name = "Zorro III cfg",
.start = 0x40000000,
.end = 0x7fffffff,
.flags = IORESOURCE_MEM,
}
};
static int __init amiga_init_bus(void)
{
struct platform_device *pdev;
unsigned int n;
if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO))
return -ENODEV;
n = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2;
pdev = platform_device_register_simple("amiga-zorro", -1,
zorro_resources, n);
return PTR_ERR_OR_ZERO(pdev);
}
subsys_initcall(amiga_init_bus);
static int __init z_dev_present(zorro_id id)
{
unsigned int i;
for (i = 0; i < zorro_num_autocon; i++) {
const struct ExpansionRom *rom = &zorro_autocon_init[i].rom;
if (be16_to_cpu(rom->er_Manufacturer) == ZORRO_MANUF(id) &&
rom->er_Product == ZORRO_PROD(id))
return 1;
}
return 0;
}
#else /* !CONFIG_ZORRO */
static inline int z_dev_present(zorro_id id) { return 0; }
#endif /* !CONFIG_ZORRO */
static const struct resource a3000_scsi_resource __initconst = {
.start = 0xdd0000,
.end = 0xdd00ff,
.flags = IORESOURCE_MEM,
};
static const struct resource a4000t_scsi_resource __initconst = {
.start = 0xdd0000,
.end = 0xdd0fff,
.flags = IORESOURCE_MEM,
};
static const struct resource a1200_ide_resource __initconst = {
.start = 0xda0000,
.end = 0xda1fff,
.flags = IORESOURCE_MEM,
};
static const struct gayle_ide_platform_data a1200_ide_pdata __initconst = {
.base = 0xda0000,
.irqport = 0xda9000,
.explicit_ack = 1,
};
static const struct resource a4000_ide_resource __initconst = {
.start = 0xdd2000,
.end = 0xdd3fff,
.flags = IORESOURCE_MEM,
};
static const struct gayle_ide_platform_data a4000_ide_pdata __initconst = {
.base = 0xdd2020,
.irqport = 0xdd3020,
.explicit_ack = 0,
};
static const struct resource amiga_rtc_resource __initconst = {
.start = 0x00dc0000,
.end = 0x00dcffff,
.flags = IORESOURCE_MEM,
};
static int __init amiga_init_devices(void)
{
struct platform_device *pdev;
int error;
if (!MACH_IS_AMIGA)
return -ENODEV;
/* video hardware */
if (AMIGAHW_PRESENT(AMI_VIDEO)) {
pdev = platform_device_register_simple("amiga-video", -1, NULL,
0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
/* sound hardware */
if (AMIGAHW_PRESENT(AMI_AUDIO)) {
pdev = platform_device_register_simple("amiga-audio", -1, NULL,
0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
/* storage interfaces */
if (AMIGAHW_PRESENT(AMI_FLOPPY)) {
pdev = platform_device_register_simple("amiga-floppy", -1,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(A3000_SCSI)) {
pdev = platform_device_register_simple("amiga-a3000-scsi", -1,
&a3000_scsi_resource, 1);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(A4000_SCSI)) {
pdev = platform_device_register_simple("amiga-a4000t-scsi", -1,
&a4000t_scsi_resource,
1);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(A1200_IDE) ||
z_dev_present(ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE)) {
pdev = platform_device_register_simple("amiga-gayle-ide", -1,
&a1200_ide_resource, 1);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
error = platform_device_add_data(pdev, &a1200_ide_pdata,
sizeof(a1200_ide_pdata));
if (error)
return error;
}
if (AMIGAHW_PRESENT(A4000_IDE)) {
pdev = platform_device_register_simple("amiga-gayle-ide", -1,
&a4000_ide_resource, 1);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
error = platform_device_add_data(pdev, &a4000_ide_pdata,
sizeof(a4000_ide_pdata));
if (error)
return error;
}
/* other I/O hardware */
if (AMIGAHW_PRESENT(AMI_KEYBOARD)) {
pdev = platform_device_register_simple("amiga-keyboard", -1,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(AMI_MOUSE)) {
pdev = platform_device_register_simple("amiga-mouse", -1, NULL,
0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(AMI_SERIAL)) {
pdev = platform_device_register_simple("amiga-serial", -1,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(AMI_PARALLEL)) {
pdev = platform_device_register_simple("amiga-parallel", -1,
NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
/* real time clocks */
if (AMIGAHW_PRESENT(A2000_CLK)) {
pdev = platform_device_register_simple("rtc-msm6242", -1,
&amiga_rtc_resource, 1);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
if (AMIGAHW_PRESENT(A3000_CLK)) {
pdev = platform_device_register_simple("rtc-rp5c01", -1,
&amiga_rtc_resource, 1);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
return 0;
}
arch_initcall(amiga_init_devices);
| linux-master | arch/m68k/amiga/platform.c |
/*
* linux/arch/m68k/amiga/config.c
*
* Copyright (C) 1993 Hamish Macdonald
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/*
* Miscellaneous Amiga stuff
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/seq_file.h>
#include <linux/tty.h>
#include <linux/clocksource.h>
#include <linux/console.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/vt_kern.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/zorro.h>
#include <linux/module.h>
#include <linux/keyboard.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-amiga.h>
#include <asm/byteorder.h>
#include <asm/setup.h>
#include <asm/amigahw.h>
#include <asm/amigaints.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/config.h>
static unsigned long amiga_model;
unsigned long amiga_eclock;
EXPORT_SYMBOL(amiga_eclock);
unsigned long amiga_colorclock;
EXPORT_SYMBOL(amiga_colorclock);
unsigned long amiga_chipset;
EXPORT_SYMBOL(amiga_chipset);
unsigned char amiga_vblank;
EXPORT_SYMBOL(amiga_vblank);
static unsigned char amiga_psfreq;
struct amiga_hw_present amiga_hw_present;
EXPORT_SYMBOL(amiga_hw_present);
static char s_a500[] __initdata = "A500";
static char s_a500p[] __initdata = "A500+";
static char s_a600[] __initdata = "A600";
static char s_a1000[] __initdata = "A1000";
static char s_a1200[] __initdata = "A1200";
static char s_a2000[] __initdata = "A2000";
static char s_a2500[] __initdata = "A2500";
static char s_a3000[] __initdata = "A3000";
static char s_a3000t[] __initdata = "A3000T";
static char s_a3000p[] __initdata = "A3000+";
static char s_a4000[] __initdata = "A4000";
static char s_a4000t[] __initdata = "A4000T";
static char s_cdtv[] __initdata = "CDTV";
static char s_cd32[] __initdata = "CD32";
static char s_draco[] __initdata = "Draco";
static char *amiga_models[] __initdata = {
[AMI_500-AMI_500] = s_a500,
[AMI_500PLUS-AMI_500] = s_a500p,
[AMI_600-AMI_500] = s_a600,
[AMI_1000-AMI_500] = s_a1000,
[AMI_1200-AMI_500] = s_a1200,
[AMI_2000-AMI_500] = s_a2000,
[AMI_2500-AMI_500] = s_a2500,
[AMI_3000-AMI_500] = s_a3000,
[AMI_3000T-AMI_500] = s_a3000t,
[AMI_3000PLUS-AMI_500] = s_a3000p,
[AMI_4000-AMI_500] = s_a4000,
[AMI_4000T-AMI_500] = s_a4000t,
[AMI_CDTV-AMI_500] = s_cdtv,
[AMI_CD32-AMI_500] = s_cd32,
[AMI_DRACO-AMI_500] = s_draco,
};
static char amiga_model_name[13] = "Amiga ";
static void amiga_sched_init(void);
static void amiga_get_model(char *model);
static void amiga_get_hardware_list(struct seq_file *m);
extern void amiga_mksound(unsigned int count, unsigned int ticks);
static void amiga_reset(void);
extern void amiga_init_sound(void);
static void amiga_mem_console_write(struct console *co, const char *b,
unsigned int count);
#ifdef CONFIG_HEARTBEAT
static void amiga_heartbeat(int on);
#endif
static struct console amiga_console_driver = {
.name = "debug",
.flags = CON_PRINTBUFFER,
.index = -1,
};
/*
* Motherboard Resources present in all Amiga models
*/
static struct {
struct resource _ciab, _ciaa, _custom, _kickstart;
} mb_resources = {
._ciab = {
.name = "CIA B", .start = 0x00bfd000, .end = 0x00bfdfff
},
._ciaa = {
.name = "CIA A", .start = 0x00bfe000, .end = 0x00bfefff
},
._custom = {
.name = "Custom I/O", .start = 0x00dff000, .end = 0x00dfffff
},
._kickstart = {
.name = "Kickstart ROM", .start = 0x00f80000, .end = 0x00ffffff
}
};
static struct resource ram_resource[NUM_MEMINFO];
/*
* Parse an Amiga-specific record in the bootinfo
*/
int __init amiga_parse_bootinfo(const struct bi_record *record)
{
int unknown = 0;
const void *data = record->data;
switch (be16_to_cpu(record->tag)) {
case BI_AMIGA_MODEL:
amiga_model = be32_to_cpup(data);
break;
case BI_AMIGA_ECLOCK:
amiga_eclock = be32_to_cpup(data);
break;
case BI_AMIGA_CHIPSET:
amiga_chipset = be32_to_cpup(data);
break;
case BI_AMIGA_CHIP_SIZE:
amiga_chip_size = be32_to_cpup(data);
break;
case BI_AMIGA_VBLANK:
amiga_vblank = *(const __u8 *)data;
break;
case BI_AMIGA_PSFREQ:
amiga_psfreq = *(const __u8 *)data;
break;
case BI_AMIGA_AUTOCON:
#ifdef CONFIG_ZORRO
if (zorro_num_autocon < ZORRO_NUM_AUTO) {
const struct ConfigDev *cd = data;
struct zorro_dev_init *dev = &zorro_autocon_init[zorro_num_autocon++];
dev->rom = cd->cd_Rom;
dev->slotaddr = be16_to_cpu(cd->cd_SlotAddr);
dev->slotsize = be16_to_cpu(cd->cd_SlotSize);
dev->boardaddr = be32_to_cpu(cd->cd_BoardAddr);
dev->boardsize = be32_to_cpu(cd->cd_BoardSize);
} else
pr_warn("amiga_parse_bootinfo: too many AutoConfig devices\n");
#endif /* CONFIG_ZORRO */
break;
case BI_AMIGA_SERPER:
/* serial port period: ignored here */
break;
default:
unknown = 1;
}
return unknown;
}
/*
* Identify builtin hardware
*/
static void __init amiga_identify(void)
{
/* Fill in some default values, if necessary */
if (amiga_eclock == 0)
amiga_eclock = 709379;
memset(&amiga_hw_present, 0, sizeof(amiga_hw_present));
pr_info("Amiga hardware found: ");
if (amiga_model >= AMI_500 && amiga_model <= AMI_DRACO) {
pr_cont("[%s] ", amiga_models[amiga_model-AMI_500]);
strcat(amiga_model_name, amiga_models[amiga_model-AMI_500]);
}
switch (amiga_model) {
case AMI_UNKNOWN:
break;
case AMI_600:
case AMI_1200:
AMIGAHW_SET(A1200_IDE);
AMIGAHW_SET(PCMCIA);
fallthrough;
case AMI_500:
case AMI_500PLUS:
case AMI_1000:
case AMI_2000:
case AMI_2500:
AMIGAHW_SET(A2000_CLK); /* Is this correct for all models? */
break;
case AMI_3000:
case AMI_3000T:
AMIGAHW_SET(AMBER_FF);
AMIGAHW_SET(MAGIC_REKICK);
fallthrough;
case AMI_3000PLUS:
AMIGAHW_SET(A3000_SCSI);
AMIGAHW_SET(A3000_CLK);
AMIGAHW_SET(ZORRO3);
break;
case AMI_4000T:
AMIGAHW_SET(A4000_SCSI);
fallthrough;
case AMI_4000:
AMIGAHW_SET(A4000_IDE);
AMIGAHW_SET(A3000_CLK);
AMIGAHW_SET(ZORRO3);
break;
case AMI_CDTV:
case AMI_CD32:
AMIGAHW_SET(CD_ROM);
AMIGAHW_SET(A2000_CLK); /* Is this correct? */
break;
case AMI_DRACO:
panic("No support for Draco yet");
default:
panic("Unknown Amiga Model");
}
AMIGAHW_SET(AMI_VIDEO);
AMIGAHW_SET(AMI_BLITTER);
AMIGAHW_SET(AMI_AUDIO);
AMIGAHW_SET(AMI_FLOPPY);
AMIGAHW_SET(AMI_KEYBOARD);
AMIGAHW_SET(AMI_MOUSE);
AMIGAHW_SET(AMI_SERIAL);
AMIGAHW_SET(AMI_PARALLEL);
AMIGAHW_SET(CHIP_RAM);
AMIGAHW_SET(PAULA);
switch (amiga_chipset) {
case CS_OCS:
case CS_ECS:
case CS_AGA:
switch (amiga_custom.deniseid & 0xf) {
case 0x0c:
AMIGAHW_SET(DENISE_HR);
break;
case 0x08:
AMIGAHW_SET(LISA);
break;
default:
AMIGAHW_SET(DENISE);
break;
}
break;
}
switch ((amiga_custom.vposr>>8) & 0x7f) {
case 0x00:
AMIGAHW_SET(AGNUS_PAL);
break;
case 0x10:
AMIGAHW_SET(AGNUS_NTSC);
break;
case 0x20:
case 0x21:
AMIGAHW_SET(AGNUS_HR_PAL);
break;
case 0x30:
case 0x31:
AMIGAHW_SET(AGNUS_HR_NTSC);
break;
case 0x22:
case 0x23:
AMIGAHW_SET(ALICE_PAL);
break;
case 0x32:
case 0x33:
AMIGAHW_SET(ALICE_NTSC);
break;
}
AMIGAHW_SET(ZORRO);
#define AMIGAHW_ANNOUNCE(name, str) \
if (AMIGAHW_PRESENT(name)) \
pr_cont(str)
AMIGAHW_ANNOUNCE(AMI_VIDEO, "VIDEO ");
AMIGAHW_ANNOUNCE(AMI_BLITTER, "BLITTER ");
AMIGAHW_ANNOUNCE(AMBER_FF, "AMBER_FF ");
AMIGAHW_ANNOUNCE(AMI_AUDIO, "AUDIO ");
AMIGAHW_ANNOUNCE(AMI_FLOPPY, "FLOPPY ");
AMIGAHW_ANNOUNCE(A3000_SCSI, "A3000_SCSI ");
AMIGAHW_ANNOUNCE(A4000_SCSI, "A4000_SCSI ");
AMIGAHW_ANNOUNCE(A1200_IDE, "A1200_IDE ");
AMIGAHW_ANNOUNCE(A4000_IDE, "A4000_IDE ");
AMIGAHW_ANNOUNCE(CD_ROM, "CD_ROM ");
AMIGAHW_ANNOUNCE(AMI_KEYBOARD, "KEYBOARD ");
AMIGAHW_ANNOUNCE(AMI_MOUSE, "MOUSE ");
AMIGAHW_ANNOUNCE(AMI_SERIAL, "SERIAL ");
AMIGAHW_ANNOUNCE(AMI_PARALLEL, "PARALLEL ");
AMIGAHW_ANNOUNCE(A2000_CLK, "A2000_CLK ");
AMIGAHW_ANNOUNCE(A3000_CLK, "A3000_CLK ");
AMIGAHW_ANNOUNCE(CHIP_RAM, "CHIP_RAM ");
AMIGAHW_ANNOUNCE(PAULA, "PAULA ");
AMIGAHW_ANNOUNCE(DENISE, "DENISE ");
AMIGAHW_ANNOUNCE(DENISE_HR, "DENISE_HR ");
AMIGAHW_ANNOUNCE(LISA, "LISA ");
AMIGAHW_ANNOUNCE(AGNUS_PAL, "AGNUS_PAL ");
AMIGAHW_ANNOUNCE(AGNUS_NTSC, "AGNUS_NTSC ");
AMIGAHW_ANNOUNCE(AGNUS_HR_PAL, "AGNUS_HR_PAL ");
AMIGAHW_ANNOUNCE(AGNUS_HR_NTSC, "AGNUS_HR_NTSC ");
AMIGAHW_ANNOUNCE(ALICE_PAL, "ALICE_PAL ");
AMIGAHW_ANNOUNCE(ALICE_NTSC, "ALICE_NTSC ");
AMIGAHW_ANNOUNCE(MAGIC_REKICK, "MAGIC_REKICK ");
AMIGAHW_ANNOUNCE(PCMCIA, "PCMCIA ");
if (AMIGAHW_PRESENT(ZORRO))
pr_cont("ZORRO%s ", AMIGAHW_PRESENT(ZORRO3) ? "3" : "");
pr_cont("\n");
#undef AMIGAHW_ANNOUNCE
}
static unsigned long amiga_random_get_entropy(void)
{
/* VPOSR/VHPOSR provide at least 17 bits of data changing at 1.79 MHz */
return *(unsigned long *)&amiga_custom.vposr;
}
/*
* Setup the Amiga configuration info
*/
void __init config_amiga(void)
{
int i;
amiga_identify();
/* Yuk, we don't have PCI memory */
iomem_resource.name = "Memory";
for (i = 0; i < 4; i++)
request_resource(&iomem_resource, &((struct resource *)&mb_resources)[i]);
mach_sched_init = amiga_sched_init;
mach_init_IRQ = amiga_init_IRQ;
mach_get_model = amiga_get_model;
mach_get_hardware_list = amiga_get_hardware_list;
mach_reset = amiga_reset;
#if IS_ENABLED(CONFIG_INPUT_M68K_BEEP)
mach_beep = amiga_mksound;
#endif
#ifdef CONFIG_HEARTBEAT
mach_heartbeat = amiga_heartbeat;
#endif
mach_random_get_entropy = amiga_random_get_entropy;
/* Fill in the clock value (based on the 700 kHz E-Clock) */
amiga_colorclock = 5*amiga_eclock; /* 3.5 MHz */
/* clear all DMA bits */
amiga_custom.dmacon = DMAF_ALL;
/* ensure that the DMA master bit is set */
amiga_custom.dmacon = DMAF_SETCLR | DMAF_MASTER;
/* don't use Z2 RAM as system memory on Z3 capable machines */
if (AMIGAHW_PRESENT(ZORRO3)) {
int i, j;
u32 disabled_z2mem = 0;
for (i = 0; i < m68k_num_memory; i++) {
if (m68k_memory[i].addr < 16*1024*1024) {
if (i == 0) {
/* don't cut off the branch we're sitting on */
pr_warn("Warning: kernel runs in Zorro II memory\n");
continue;
}
disabled_z2mem += m68k_memory[i].size;
m68k_num_memory--;
for (j = i; j < m68k_num_memory; j++)
m68k_memory[j] = m68k_memory[j+1];
i--;
}
}
if (disabled_z2mem)
pr_info("%dK of Zorro II memory will not be used as system memory\n",
disabled_z2mem>>10);
}
/* request all RAM */
for (i = 0; i < m68k_num_memory; i++) {
ram_resource[i].name =
(m68k_memory[i].addr >= 0x01000000) ? "32-bit Fast RAM" :
(m68k_memory[i].addr < 0x00c00000) ? "16-bit Fast RAM" :
"16-bit Slow RAM";
ram_resource[i].start = m68k_memory[i].addr;
ram_resource[i].end = m68k_memory[i].addr+m68k_memory[i].size-1;
request_resource(&iomem_resource, &ram_resource[i]);
}
/* initialize chipram allocator */
amiga_chip_init();
/* our beloved beeper */
if (AMIGAHW_PRESENT(AMI_AUDIO))
amiga_init_sound();
/*
* if it is an A3000, set the magic bit that forces
* a hard rekick
*/
if (AMIGAHW_PRESENT(MAGIC_REKICK))
*(unsigned char *)ZTWO_VADDR(0xde0002) |= 0x80;
}
static u64 amiga_read_clk(struct clocksource *cs);
static struct clocksource amiga_clk = {
.name = "ciab",
.rating = 250,
.read = amiga_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static unsigned short jiffy_ticks;
static u32 clk_total, clk_offset;
static irqreturn_t ciab_timer_handler(int irq, void *dev_id)
{
clk_total += jiffy_ticks;
clk_offset = 0;
legacy_timer_tick(1);
timer_heartbeat();
return IRQ_HANDLED;
}
static void __init amiga_sched_init(void)
{
static struct resource sched_res = {
.name = "timer", .start = 0x00bfd400, .end = 0x00bfd5ff,
};
jiffy_ticks = DIV_ROUND_CLOSEST(amiga_eclock, HZ);
if (request_resource(&mb_resources._ciab, &sched_res))
pr_warn("Cannot allocate ciab.ta{lo,hi}\n");
ciab.cra &= 0xC0; /* turn off timer A, continuous mode, from Eclk */
ciab.talo = jiffy_ticks % 256;
ciab.tahi = jiffy_ticks / 256;
/* install interrupt service routine for CIAB Timer A
*
* Please don't change this to use ciaa, as it interferes with the
* SCSI code. We'll have to take a look at this later
*/
if (request_irq(IRQ_AMIGA_CIAB_TA, ciab_timer_handler, IRQF_TIMER,
"timer", NULL))
pr_err("Couldn't register timer interrupt\n");
/* start timer */
ciab.cra |= 0x11;
clocksource_register_hz(&amiga_clk, amiga_eclock);
}
static u64 amiga_read_clk(struct clocksource *cs)
{
unsigned short hi, lo, hi2;
unsigned long flags;
u32 ticks;
local_irq_save(flags);
/* read CIA B timer A current value */
hi = ciab.tahi;
lo = ciab.talo;
hi2 = ciab.tahi;
if (hi != hi2) {
lo = ciab.talo;
hi = hi2;
}
ticks = hi << 8 | lo;
if (ticks > jiffy_ticks / 2)
/* check for pending interrupt */
if (cia_set_irq(&ciab_base, 0) & CIA_ICR_TA)
clk_offset = jiffy_ticks;
ticks = jiffy_ticks - ticks;
ticks += clk_offset + clk_total;
local_irq_restore(flags);
return ticks;
}
static void amiga_reset(void) __noreturn;
static void amiga_reset(void)
{
unsigned long jmp_addr040 = virt_to_phys(&&jmp_addr_label040);
unsigned long jmp_addr = virt_to_phys(&&jmp_addr_label);
local_irq_disable();
if (CPU_IS_040_OR_060)
/* Setup transparent translation registers for mapping
* of 16 MB kernel segment before disabling translation
*/
asm volatile ("\n"
" move.l %0,%%d0\n"
" and.l #0xff000000,%%d0\n"
" or.w #0xe020,%%d0\n" /* map 16 MB, enable, cacheable */
" .chip 68040\n"
" movec %%d0,%%itt0\n"
" movec %%d0,%%dtt0\n"
" .chip 68k\n"
" jmp %0@\n"
: /* no outputs */
: "a" (jmp_addr040)
: "d0");
else
/* for 680[23]0, just disable translation and jump to the physical
* address of the label
*/
asm volatile ("\n"
" pmove %%tc,%@\n"
" bclr #7,%@\n"
" pmove %@,%%tc\n"
" jmp %0@\n"
: /* no outputs */
: "a" (jmp_addr));
jmp_addr_label040:
/* disable translation on '040 now */
asm volatile ("\n"
" moveq #0,%%d0\n"
" .chip 68040\n"
" movec %%d0,%%tc\n" /* disable MMU */
" .chip 68k\n"
: /* no outputs */
: /* no inputs */
: "d0");
jmp_addr_label:
/* pickup reset address from AmigaOS ROM, reset devices and jump
* to reset address
*/
asm volatile ("\n"
" move.w #0x2700,%sr\n"
" lea 0x01000000,%a0\n"
" sub.l %a0@(-0x14),%a0\n"
" move.l %a0@(4),%a0\n"
" subq.l #2,%a0\n"
" jra 1f\n"
/* align on a longword boundary */
" " __ALIGN_STR "\n"
"1:\n"
" reset\n"
" jmp %a0@");
for (;;)
;
}
/*
* Debugging
*/
#define SAVEKMSG_MAXMEM 128*1024
#define SAVEKMSG_MAGIC1 0x53415645 /* 'SAVE' */
#define SAVEKMSG_MAGIC2 0x4B4D5347 /* 'KMSG' */
struct savekmsg {
unsigned long magic1; /* SAVEKMSG_MAGIC1 */
unsigned long magic2; /* SAVEKMSG_MAGIC2 */
unsigned long magicptr; /* address of magic1 */
unsigned long size;
char data[];
};
static struct savekmsg *savekmsg;
static void amiga_mem_console_write(struct console *co, const char *s,
unsigned int count)
{
if (savekmsg->size + count <= SAVEKMSG_MAXMEM-sizeof(struct savekmsg)) {
memcpy(savekmsg->data + savekmsg->size, s, count);
savekmsg->size += count;
}
}
static int __init amiga_savekmsg_setup(char *arg)
{
bool registered;
if (!MACH_IS_AMIGA || strcmp(arg, "mem"))
return 0;
if (amiga_chip_size < SAVEKMSG_MAXMEM) {
pr_err("Not enough chipram for debugging\n");
return -ENOMEM;
}
/* Just steal the block, the chipram allocator isn't functional yet */
amiga_chip_size -= SAVEKMSG_MAXMEM;
savekmsg = ZTWO_VADDR(CHIP_PHYSADDR + amiga_chip_size);
savekmsg->magic1 = SAVEKMSG_MAGIC1;
savekmsg->magic2 = SAVEKMSG_MAGIC2;
savekmsg->magicptr = ZTWO_PADDR(savekmsg);
savekmsg->size = 0;
registered = !!amiga_console_driver.write;
amiga_console_driver.write = amiga_mem_console_write;
if (!registered)
register_console(&amiga_console_driver);
return 0;
}
early_param("debug", amiga_savekmsg_setup);
static void amiga_serial_putc(char c)
{
amiga_custom.serdat = (unsigned char)c | 0x100;
while (!(amiga_custom.serdatr & 0x2000))
;
}
static void amiga_serial_console_write(struct console *co, const char *s,
unsigned int count)
{
while (count--) {
if (*s == '\n')
amiga_serial_putc('\r');
amiga_serial_putc(*s++);
}
}
#if 0
void amiga_serial_puts(const char *s)
{
amiga_serial_console_write(NULL, s, strlen(s));
}
int amiga_serial_console_wait_key(struct console *co)
{
int ch;
while (!(amiga_custom.intreqr & IF_RBF))
barrier();
ch = amiga_custom.serdatr & 0xff;
/* clear the interrupt, so that another character can be read */
amiga_custom.intreq = IF_RBF;
return ch;
}
void amiga_serial_gets(struct console *co, char *s, int len)
{
int ch, cnt = 0;
while (1) {
ch = amiga_serial_console_wait_key(co);
/* Check for backspace. */
if (ch == 8 || ch == 127) {
if (cnt == 0) {
amiga_serial_putc('\007');
continue;
}
cnt--;
amiga_serial_puts("\010 \010");
continue;
}
/* Check for enter. */
if (ch == 10 || ch == 13)
break;
/* See if line is too long. */
if (cnt >= len + 1) {
amiga_serial_putc(7);
cnt--;
continue;
}
/* Store and echo character. */
s[cnt++] = ch;
amiga_serial_putc(ch);
}
/* Print enter. */
amiga_serial_puts("\r\n");
s[cnt] = 0;
}
#endif
static int __init amiga_debug_setup(char *arg)
{
bool registered;
if (!MACH_IS_AMIGA || strcmp(arg, "ser"))
return 0;
/* no initialization required (?) */
registered = !!amiga_console_driver.write;
amiga_console_driver.write = amiga_serial_console_write;
if (!registered)
register_console(&amiga_console_driver);
return 0;
}
early_param("debug", amiga_debug_setup);
#ifdef CONFIG_HEARTBEAT
static void amiga_heartbeat(int on)
{
if (on)
ciaa.pra &= ~2;
else
ciaa.pra |= 2;
}
#endif
/*
* Amiga specific parts of /proc
*/
static void amiga_get_model(char *model)
{
strcpy(model, amiga_model_name);
}
static void amiga_get_hardware_list(struct seq_file *m)
{
if (AMIGAHW_PRESENT(CHIP_RAM))
seq_printf(m, "Chip RAM:\t%ldK\n", amiga_chip_size>>10);
seq_printf(m, "PS Freq:\t%dHz\nEClock Freq:\t%ldHz\n",
amiga_psfreq, amiga_eclock);
if (AMIGAHW_PRESENT(AMI_VIDEO)) {
char *type;
switch (amiga_chipset) {
case CS_OCS:
type = "OCS";
break;
case CS_ECS:
type = "ECS";
break;
case CS_AGA:
type = "AGA";
break;
default:
type = "Old or Unknown";
break;
}
seq_printf(m, "Graphics:\t%s\n", type);
}
#define AMIGAHW_ANNOUNCE(name, str) \
if (AMIGAHW_PRESENT(name)) \
seq_printf (m, "\t%s\n", str)
seq_puts(m, "Detected hardware:\n");
AMIGAHW_ANNOUNCE(AMI_VIDEO, "Amiga Video");
AMIGAHW_ANNOUNCE(AMI_BLITTER, "Blitter");
AMIGAHW_ANNOUNCE(AMBER_FF, "Amber Flicker Fixer");
AMIGAHW_ANNOUNCE(AMI_AUDIO, "Amiga Audio");
AMIGAHW_ANNOUNCE(AMI_FLOPPY, "Floppy Controller");
AMIGAHW_ANNOUNCE(A3000_SCSI, "SCSI Controller WD33C93 (A3000 style)");
AMIGAHW_ANNOUNCE(A4000_SCSI, "SCSI Controller NCR53C710 (A4000T style)");
AMIGAHW_ANNOUNCE(A1200_IDE, "IDE Interface (A1200 style)");
AMIGAHW_ANNOUNCE(A4000_IDE, "IDE Interface (A4000 style)");
AMIGAHW_ANNOUNCE(CD_ROM, "Internal CD ROM drive");
AMIGAHW_ANNOUNCE(AMI_KEYBOARD, "Keyboard");
AMIGAHW_ANNOUNCE(AMI_MOUSE, "Mouse Port");
AMIGAHW_ANNOUNCE(AMI_SERIAL, "Serial Port");
AMIGAHW_ANNOUNCE(AMI_PARALLEL, "Parallel Port");
AMIGAHW_ANNOUNCE(A2000_CLK, "Hardware Clock (A2000 style)");
AMIGAHW_ANNOUNCE(A3000_CLK, "Hardware Clock (A3000 style)");
AMIGAHW_ANNOUNCE(CHIP_RAM, "Chip RAM");
AMIGAHW_ANNOUNCE(PAULA, "Paula 8364");
AMIGAHW_ANNOUNCE(DENISE, "Denise 8362");
AMIGAHW_ANNOUNCE(DENISE_HR, "Denise 8373");
AMIGAHW_ANNOUNCE(LISA, "Lisa 8375");
AMIGAHW_ANNOUNCE(AGNUS_PAL, "Normal/Fat PAL Agnus 8367/8371");
AMIGAHW_ANNOUNCE(AGNUS_NTSC, "Normal/Fat NTSC Agnus 8361/8370");
AMIGAHW_ANNOUNCE(AGNUS_HR_PAL, "Fat Hires PAL Agnus 8372");
AMIGAHW_ANNOUNCE(AGNUS_HR_NTSC, "Fat Hires NTSC Agnus 8372");
AMIGAHW_ANNOUNCE(ALICE_PAL, "PAL Alice 8374");
AMIGAHW_ANNOUNCE(ALICE_NTSC, "NTSC Alice 8374");
AMIGAHW_ANNOUNCE(MAGIC_REKICK, "Magic Hard Rekick");
AMIGAHW_ANNOUNCE(PCMCIA, "PCMCIA Slot");
#ifdef CONFIG_ZORRO
if (AMIGAHW_PRESENT(ZORRO))
seq_printf(m, "\tZorro II%s AutoConfig: %d Expansion "
"Device%s\n",
AMIGAHW_PRESENT(ZORRO3) ? "I" : "",
zorro_num_autocon, zorro_num_autocon == 1 ? "" : "s");
#endif /* CONFIG_ZORRO */
#undef AMIGAHW_ANNOUNCE
}
/*
* The Amiga keyboard driver needs key_maps, but we cannot export it in
* drivers/char/defkeymap.c, as it is autogenerated
*/
#ifdef CONFIG_HW_CONSOLE
EXPORT_SYMBOL_GPL(key_maps);
#endif
| linux-master | arch/m68k/amiga/config.c |
/*
* linux/arch/m68k/amiga/cia.c - CIA support
*
* Copyright (C) 1996 Roman Zippel
*
* The concept of some functions bases on the original Amiga OS function
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq.h>
#include <asm/amigahw.h>
#include <asm/amigaints.h>
struct ciabase {
volatile struct CIA *cia;
unsigned char icr_mask, icr_data;
unsigned short int_mask;
int handler_irq, cia_irq, server_irq;
char *name;
} ciaa_base = {
.cia = &ciaa,
.int_mask = IF_PORTS,
.handler_irq = IRQ_AMIGA_PORTS,
.cia_irq = IRQ_AMIGA_CIAA,
.name = "CIAA"
}, ciab_base = {
.cia = &ciab,
.int_mask = IF_EXTER,
.handler_irq = IRQ_AMIGA_EXTER,
.cia_irq = IRQ_AMIGA_CIAB,
.name = "CIAB"
};
/*
* Cause or clear CIA interrupts, return old interrupt status.
*/
unsigned char cia_set_irq(struct ciabase *base, unsigned char mask)
{
unsigned char old;
old = (base->icr_data |= base->cia->icr);
if (mask & CIA_ICR_SETCLR)
base->icr_data |= mask;
else
base->icr_data &= ~mask;
if (base->icr_data & base->icr_mask)
amiga_custom.intreq = IF_SETCLR | base->int_mask;
return old & base->icr_mask;
}
/*
* Enable or disable CIA interrupts, return old interrupt mask,
*/
unsigned char cia_able_irq(struct ciabase *base, unsigned char mask)
{
unsigned char old;
old = base->icr_mask;
base->icr_data |= base->cia->icr;
base->cia->icr = mask;
if (mask & CIA_ICR_SETCLR)
base->icr_mask |= mask;
else
base->icr_mask &= ~mask;
base->icr_mask &= CIA_ICR_ALL;
if (base->icr_data & base->icr_mask)
amiga_custom.intreq = IF_SETCLR | base->int_mask;
return old;
}
static irqreturn_t cia_handler(int irq, void *dev_id)
{
struct ciabase *base = dev_id;
int mach_irq;
unsigned char ints;
unsigned long flags;
/* Interrupts get disabled while the timer irq flag is cleared and
* the timer interrupt serviced.
*/
mach_irq = base->cia_irq;
local_irq_save(flags);
ints = cia_set_irq(base, CIA_ICR_ALL);
amiga_custom.intreq = base->int_mask;
if (ints & 1)
generic_handle_irq(mach_irq);
local_irq_restore(flags);
mach_irq++, ints >>= 1;
for (; ints; mach_irq++, ints >>= 1) {
if (ints & 1)
generic_handle_irq(mach_irq);
}
return IRQ_HANDLED;
}
static void cia_irq_enable(struct irq_data *data)
{
unsigned int irq = data->irq;
unsigned char mask;
if (irq >= IRQ_AMIGA_CIAB) {
mask = 1 << (irq - IRQ_AMIGA_CIAB);
cia_set_irq(&ciab_base, mask);
cia_able_irq(&ciab_base, CIA_ICR_SETCLR | mask);
} else {
mask = 1 << (irq - IRQ_AMIGA_CIAA);
cia_set_irq(&ciaa_base, mask);
cia_able_irq(&ciaa_base, CIA_ICR_SETCLR | mask);
}
}
static void cia_irq_disable(struct irq_data *data)
{
unsigned int irq = data->irq;
if (irq >= IRQ_AMIGA_CIAB)
cia_able_irq(&ciab_base, 1 << (irq - IRQ_AMIGA_CIAB));
else
cia_able_irq(&ciaa_base, 1 << (irq - IRQ_AMIGA_CIAA));
}
static struct irq_chip cia_irq_chip = {
.name = "cia",
.irq_enable = cia_irq_enable,
.irq_disable = cia_irq_disable,
};
/*
* Override auto irq 2 & 6 and use them as general chain
* for external interrupts, we link the CIA interrupt sources
* into this chain.
*/
static void auto_irq_enable(struct irq_data *data)
{
switch (data->irq) {
case IRQ_AUTO_2:
amiga_custom.intena = IF_SETCLR | IF_PORTS;
break;
case IRQ_AUTO_6:
amiga_custom.intena = IF_SETCLR | IF_EXTER;
break;
}
}
static void auto_irq_disable(struct irq_data *data)
{
switch (data->irq) {
case IRQ_AUTO_2:
amiga_custom.intena = IF_PORTS;
break;
case IRQ_AUTO_6:
amiga_custom.intena = IF_EXTER;
break;
}
}
static struct irq_chip auto_irq_chip = {
.name = "auto",
.irq_enable = auto_irq_enable,
.irq_disable = auto_irq_disable,
};
void __init cia_init_IRQ(struct ciabase *base)
{
m68k_setup_irq_controller(&cia_irq_chip, handle_simple_irq,
base->cia_irq, CIA_IRQS);
/* clear any pending interrupt and turn off all interrupts */
cia_set_irq(base, CIA_ICR_ALL);
cia_able_irq(base, CIA_ICR_ALL);
/* override auto int and install CIA handler */
m68k_setup_irq_controller(&auto_irq_chip, handle_simple_irq,
base->handler_irq, 1);
m68k_irq_startup_irq(base->handler_irq);
if (request_irq(base->handler_irq, cia_handler, IRQF_SHARED,
base->name, base))
pr_err("Couldn't register %s interrupt\n", base->name);
}
| linux-master | arch/m68k/amiga/cia.c |
/*
* linux/arch/m68k/amiga/amisound.c
*
* amiga sound driver for Linux/m68k
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/jiffies.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/module.h>
#include <asm/amigahw.h>
static unsigned short *snd_data;
static const signed char sine_data[] = {
0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
0, -39, -75, -103, -121, -127, -121, -103, -75, -39
};
#define DATA_SIZE ARRAY_SIZE(sine_data)
#define custom amiga_custom
/*
* The minimum period for audio may be modified by the frame buffer
* device since it depends on htotal (for OCS/ECS/AGA)
*/
volatile unsigned short amiga_audio_min_period = 124; /* Default for pre-OCS */
EXPORT_SYMBOL(amiga_audio_min_period);
#define MAX_PERIOD (65535)
/*
* Current period (set by dmasound.c)
*/
unsigned short amiga_audio_period = MAX_PERIOD;
EXPORT_SYMBOL(amiga_audio_period);
static unsigned long clock_constant;
void __init amiga_init_sound(void)
{
static struct resource beep_res = { .name = "Beep" };
snd_data = amiga_chip_alloc_res(sizeof(sine_data), &beep_res);
if (!snd_data) {
pr_crit("amiga init_sound: failed to allocate chipmem\n");
return;
}
memcpy (snd_data, sine_data, sizeof(sine_data));
/* setup divisor */
clock_constant = (amiga_colorclock+DATA_SIZE/2)/DATA_SIZE;
/* without amifb, turn video off and enable high quality sound */
#ifndef CONFIG_FB_AMIGA
amifb_video_off();
#endif
}
static void nosound(struct timer_list *unused);
static DEFINE_TIMER(sound_timer, nosound);
void amiga_mksound( unsigned int hz, unsigned int ticks )
{
unsigned long flags;
if (!snd_data)
return;
local_irq_save(flags);
del_timer( &sound_timer );
if (hz > 20 && hz < 32767) {
unsigned long period = (clock_constant / hz);
if (period < amiga_audio_min_period)
period = amiga_audio_min_period;
if (period > MAX_PERIOD)
period = MAX_PERIOD;
/* setup pointer to data, period, length and volume */
custom.aud[2].audlc = snd_data;
custom.aud[2].audlen = sizeof(sine_data)/2;
custom.aud[2].audper = (unsigned short)period;
custom.aud[2].audvol = 32; /* 50% of maxvol */
if (ticks) {
sound_timer.expires = jiffies + ticks;
add_timer( &sound_timer );
}
/* turn on DMA for audio channel 2 */
custom.dmacon = DMAF_SETCLR | DMAF_AUD2;
} else
nosound( 0 );
local_irq_restore(flags);
}
static void nosound(struct timer_list *unused)
{
/* turn off DMA for audio channel 2 */
custom.dmacon = DMAF_AUD2;
/* restore period to previous value after beeping */
custom.aud[2].audper = amiga_audio_period;
}
| linux-master | arch/m68k/amiga/amisound.c |
/*
** asm-m68k/pcmcia.c -- Amiga Linux PCMCIA support
** most information was found by disassembling card.resource
** I'm still looking for an official doc !
**
** Copyright 1997 by Alain Malek
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 12/10/97 by Alain Malek
*/
#include <linux/types.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
#include <linux/module.h>
#include <asm/amigayle.h>
#include <asm/amipcmcia.h>
/* gayle config byte for program voltage and access speed */
static unsigned char cfg_byte = GAYLE_CFG_0V|GAYLE_CFG_150NS;
void pcmcia_reset(void)
{
unsigned long reset_start_time = jiffies;
unsigned char b;
gayle_reset = 0x00;
while (time_before(jiffies, reset_start_time + 1*HZ/100));
b = gayle_reset;
}
EXPORT_SYMBOL(pcmcia_reset);
/* copy a tuple, including tuple header. return nb bytes copied */
/* be careful as this may trigger a GAYLE_IRQ_WR interrupt ! */
int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len)
{
unsigned char id, *dest;
int cnt, pos, len;
dest = tuple;
pos = 0;
id = gayle_attribute[pos];
while((id != CISTPL_END) && (pos < 0x10000)) {
len = (int)gayle_attribute[pos+2] + 2;
if (id == tuple_id) {
len = (len > max_len)?max_len:len;
for (cnt = 0; cnt < len; cnt++) {
*dest++ = gayle_attribute[pos+(cnt<<1)];
}
return len;
}
pos += len<<1;
id = gayle_attribute[pos];
}
return 0;
}
EXPORT_SYMBOL(pcmcia_copy_tuple);
void pcmcia_program_voltage(int voltage)
{
unsigned char v;
switch (voltage) {
case PCMCIA_0V:
v = GAYLE_CFG_0V;
break;
case PCMCIA_5V:
v = GAYLE_CFG_5V;
break;
case PCMCIA_12V:
v = GAYLE_CFG_12V;
break;
default:
v = GAYLE_CFG_0V;
}
cfg_byte = (cfg_byte & 0xfc) | v;
gayle.config = cfg_byte;
}
EXPORT_SYMBOL(pcmcia_program_voltage);
void pcmcia_access_speed(int speed)
{
unsigned char s;
if (speed <= PCMCIA_SPEED_100NS)
s = GAYLE_CFG_100NS;
else if (speed <= PCMCIA_SPEED_150NS)
s = GAYLE_CFG_150NS;
else if (speed <= PCMCIA_SPEED_250NS)
s = GAYLE_CFG_250NS;
else
s = GAYLE_CFG_720NS;
cfg_byte = (cfg_byte & 0xf3) | s;
gayle.config = cfg_byte;
}
EXPORT_SYMBOL(pcmcia_access_speed);
void pcmcia_write_enable(void)
{
gayle.cardstatus = GAYLE_CS_WR|GAYLE_CS_DA;
}
EXPORT_SYMBOL(pcmcia_write_enable);
void pcmcia_write_disable(void)
{
gayle.cardstatus = 0;
}
EXPORT_SYMBOL(pcmcia_write_disable);
| linux-master | arch/m68k/amiga/pcmcia.c |
/* lshrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */
/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. */
#include <linux/compiler.h>
#include <linux/export.h>
#define BITS_PER_UNIT 8
typedef int SItype __mode(SI);
typedef unsigned int USItype __mode(SI);
typedef int DItype __mode(DI);
typedef int word_type __mode(__word__);
struct DIstruct {SItype high, low;};
typedef union
{
struct DIstruct s;
DItype ll;
} DIunion;
DItype
__lshrdi3 (DItype u, word_type b)
{
DIunion w;
word_type bm;
DIunion uu;
if (b == 0)
return u;
uu.ll = u;
bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
if (bm <= 0)
{
w.s.high = 0;
w.s.low = (USItype)uu.s.high >> -bm;
}
else
{
USItype carries = (USItype)uu.s.high << bm;
w.s.high = (USItype)uu.s.high >> b;
w.s.low = ((USItype)uu.s.low >> b) | carries;
}
return w.ll;
}
EXPORT_SYMBOL(__lshrdi3);
| linux-master | arch/m68k/lib/lshrdi3.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/string.h>
void *memcpy(void *to, const void *from, size_t n)
{
void *xto = to;
size_t temp;
if (!n)
return xto;
if ((long)to & 1) {
char *cto = to;
const char *cfrom = from;
*cto++ = *cfrom++;
to = cto;
from = cfrom;
n--;
}
#if defined(CONFIG_M68000)
if ((long)from & 1) {
char *cto = to;
const char *cfrom = from;
for (; n; n--)
*cto++ = *cfrom++;
return xto;
}
#endif
if (n > 2 && (long)to & 2) {
short *sto = to;
const short *sfrom = from;
*sto++ = *sfrom++;
to = sto;
from = sfrom;
n -= 2;
}
temp = n >> 2;
if (temp) {
long *lto = to;
const long *lfrom = from;
#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
for (; temp; temp--)
*lto++ = *lfrom++;
#else
size_t temp1;
asm volatile (
" movel %2,%3\n"
" andw #7,%3\n"
" lsrl #3,%2\n"
" negw %3\n"
" jmp %%pc@(1f,%3:w:2)\n"
"4: movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
" movel %0@+,%1@+\n"
"1: dbra %2,4b\n"
" clrw %2\n"
" subql #1,%2\n"
" jpl 4b"
: "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1)
: "0" (lfrom), "1" (lto), "2" (temp));
#endif
to = lto;
from = lfrom;
}
if (n & 2) {
short *sto = to;
const short *sfrom = from;
*sto++ = *sfrom++;
to = sto;
from = sfrom;
}
if (n & 1) {
char *cto = to;
const char *cfrom = from;
*cto = *cfrom;
}
return xto;
}
EXPORT_SYMBOL(memcpy);
| linux-master | arch/m68k/lib/memcpy.c |
/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
gcc-2.7.2.3/longlong.h which is: */
/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. */
#include <linux/compiler.h>
#include <linux/export.h>
#ifdef CONFIG_CPU_HAS_NO_MULDIV64
#define SI_TYPE_SIZE 32
#define __BITS4 (SI_TYPE_SIZE / 4)
#define __ll_B (1L << (SI_TYPE_SIZE / 2))
#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
#define __ll_highpart(t) ((USItype) (t) / __ll_B)
#define umul_ppmm(w1, w0, u, v) \
do { \
USItype __x0, __x1, __x2, __x3; \
USItype __ul, __vl, __uh, __vh; \
\
__ul = __ll_lowpart (u); \
__uh = __ll_highpart (u); \
__vl = __ll_lowpart (v); \
__vh = __ll_highpart (v); \
\
__x0 = (USItype) __ul * __vl; \
__x1 = (USItype) __ul * __vh; \
__x2 = (USItype) __uh * __vl; \
__x3 = (USItype) __uh * __vh; \
\
__x1 += __ll_highpart (__x0);/* this can't give carry */ \
__x1 += __x2; /* but this indeed can */ \
if (__x1 < __x2) /* did we get it? */ \
__x3 += __ll_B; /* yes, add it in the proper pos. */ \
\
(w1) = __x3 + __ll_highpart (__x1); \
(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
} while (0)
#else
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
: "=d" ((USItype)(w0)), \
"=d" ((USItype)(w1)) \
: "%0" ((USItype)(u)), \
"dmi" ((USItype)(v)))
#endif
#define __umulsidi3(u, v) \
({DIunion __w; \
umul_ppmm (__w.s.high, __w.s.low, u, v); \
__w.ll; })
typedef int SItype __mode(SI);
typedef unsigned int USItype __mode(SI);
typedef int DItype __mode(DI);
typedef int word_type __mode(__word__);
struct DIstruct {SItype high, low;};
typedef union
{
struct DIstruct s;
DItype ll;
} DIunion;
DItype
__muldi3 (DItype u, DItype v)
{
DIunion w;
DIunion uu, vv;
uu.ll = u;
vv.ll = v;
w.ll = __umulsidi3 (uu.s.low, vv.s.low);
w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+ (USItype) uu.s.high * (USItype) vv.s.low);
return w.ll;
}
EXPORT_SYMBOL(__muldi3);
| linux-master | arch/m68k/lib/muldi3.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* INET An implementation of the TCP/IP protocol suite for the LINUX
* operating system. INET is implemented using the BSD Socket
* interface as the means of communication with the user level.
*
* IP/TCP/UDP checksumming routines
*
* Authors: Jorge Cwik, <[email protected]>
* Arnt Gulbrandsen, <[email protected]>
* Tom May, <[email protected]>
* Andreas Schwab, <[email protected]>
* Lots of code moved from tcp.c and ip.c; see those files
* for more names.
*
* 03/02/96 Jes Sorensen, Andreas Schwab, Roman Hodek:
* Fixed some nasty bugs, causing some horrible crashes.
* A: At some points, the sum (%0) was used as
* length-counter instead of the length counter
* (%1). Thanks to Roman Hodek for pointing this out.
* B: GCC seems to mess up if one uses too many
* data-registers to hold input values and one tries to
* specify d0 and d1 as scratch registers. Letting gcc
* choose these registers itself solves the problem.
*
* 1998/8/31 Andreas Schwab:
* Zero out rest of buffer on exception in
* csum_partial_copy_from_user.
*/
#include <linux/module.h>
#include <net/checksum.h>
/*
* computes a partial checksum, e.g. for TCP/UDP fragments
*/
__wsum csum_partial(const void *buff, int len, __wsum sum)
{
unsigned long tmp1, tmp2;
/*
* Experiments with ethernet and slip connections show that buff
* is aligned on either a 2-byte or 4-byte boundary.
*/
__asm__("movel %2,%3\n\t"
"btst #1,%3\n\t" /* Check alignment */
"jeq 2f\n\t"
"subql #2,%1\n\t" /* buff%4==2: treat first word */
"jgt 1f\n\t"
"addql #2,%1\n\t" /* len was == 2, treat only rest */
"jra 4f\n"
"1:\t"
"addw %2@+,%0\n\t" /* add first word to sum */
"clrl %3\n\t"
"addxl %3,%0\n" /* add X bit */
"2:\t"
/* unrolled loop for the main part: do 8 longs at once */
"movel %1,%3\n\t" /* save len in tmp1 */
"lsrl #5,%1\n\t" /* len/32 */
"jeq 2f\n\t" /* not enough... */
"subql #1,%1\n"
"1:\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"dbra %1,1b\n\t"
"clrl %4\n\t"
"addxl %4,%0\n\t" /* add X bit */
"clrw %1\n\t"
"subql #1,%1\n\t"
"jcc 1b\n"
"2:\t"
"movel %3,%1\n\t" /* restore len from tmp1 */
"andw #0x1c,%3\n\t" /* number of rest longs */
"jeq 4f\n\t"
"lsrw #2,%3\n\t"
"subqw #1,%3\n"
"3:\t"
/* loop for rest longs */
"movel %2@+,%4\n\t"
"addxl %4,%0\n\t"
"dbra %3,3b\n\t"
"clrl %4\n\t"
"addxl %4,%0\n" /* add X bit */
"4:\t"
/* now check for rest bytes that do not fit into longs */
"andw #3,%1\n\t"
"jeq 7f\n\t"
"clrl %4\n\t" /* clear tmp2 for rest bytes */
"subqw #2,%1\n\t"
"jlt 5f\n\t"
"movew %2@+,%4\n\t" /* have rest >= 2: get word */
"swap %4\n\t" /* into bits 16..31 */
"tstw %1\n\t" /* another byte? */
"jeq 6f\n"
"5:\t"
"moveb %2@,%4\n\t" /* have odd rest: get byte */
"lslw #8,%4\n\t" /* into bits 8..15; 16..31 untouched */
"6:\t"
"addl %4,%0\n\t" /* now add rest long to sum */
"clrl %4\n\t"
"addxl %4,%0\n" /* add X bit */
"7:\t"
: "=d" (sum), "=d" (len), "=a" (buff),
"=&d" (tmp1), "=&d" (tmp2)
: "0" (sum), "1" (len), "2" (buff)
);
return(sum);
}
EXPORT_SYMBOL(csum_partial);
/*
* copy from user space while checksumming, with exception handling.
*/
__wsum
csum_and_copy_from_user(const void __user *src, void *dst, int len)
{
/*
* GCC doesn't like more than 10 operands for the asm
* statements so we have to use tmp2 for the error
* code.
*/
unsigned long tmp1, tmp2;
__wsum sum = ~0U;
__asm__("movel %2,%4\n\t"
"btst #1,%4\n\t" /* Check alignment */
"jeq 2f\n\t"
"subql #2,%1\n\t" /* buff%4==2: treat first word */
"jgt 1f\n\t"
"addql #2,%1\n\t" /* len was == 2, treat only rest */
"jra 4f\n"
"1:\n"
"10:\t"
"movesw %2@+,%4\n\t" /* add first word to sum */
"addw %4,%0\n\t"
"movew %4,%3@+\n\t"
"clrl %4\n\t"
"addxl %4,%0\n" /* add X bit */
"2:\t"
/* unrolled loop for the main part: do 8 longs at once */
"movel %1,%4\n\t" /* save len in tmp1 */
"lsrl #5,%1\n\t" /* len/32 */
"jeq 2f\n\t" /* not enough... */
"subql #1,%1\n"
"1:\n"
"11:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"12:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"13:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"14:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"15:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"16:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"17:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"18:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"dbra %1,1b\n\t"
"clrl %5\n\t"
"addxl %5,%0\n\t" /* add X bit */
"clrw %1\n\t"
"subql #1,%1\n\t"
"jcc 1b\n"
"2:\t"
"movel %4,%1\n\t" /* restore len from tmp1 */
"andw #0x1c,%4\n\t" /* number of rest longs */
"jeq 4f\n\t"
"lsrw #2,%4\n\t"
"subqw #1,%4\n"
"3:\n"
/* loop for rest longs */
"19:\t"
"movesl %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"dbra %4,3b\n\t"
"clrl %5\n\t"
"addxl %5,%0\n" /* add X bit */
"4:\t"
/* now check for rest bytes that do not fit into longs */
"andw #3,%1\n\t"
"jeq 7f\n\t"
"clrl %5\n\t" /* clear tmp2 for rest bytes */
"subqw #2,%1\n\t"
"jlt 5f\n\t"
"20:\t"
"movesw %2@+,%5\n\t" /* have rest >= 2: get word */
"movew %5,%3@+\n\t"
"swap %5\n\t" /* into bits 16..31 */
"tstw %1\n\t" /* another byte? */
"jeq 6f\n"
"5:\n"
"21:\t"
"movesb %2@,%5\n\t" /* have odd rest: get byte */
"moveb %5,%3@+\n\t"
"lslw #8,%5\n\t" /* into bits 8..15; 16..31 untouched */
"6:\t"
"addl %5,%0\n\t" /* now add rest long to sum */
"clrl %5\n\t"
"addxl %5,%0\n\t" /* add X bit */
"7:\t"
".section .fixup,\"ax\"\n"
".even\n"
/* If any exception occurs, return 0 */
"90:\t"
"clrl %0\n"
"jra 7b\n"
".previous\n"
".section __ex_table,\"a\"\n"
".long 10b,90b\n"
".long 11b,90b\n"
".long 12b,90b\n"
".long 13b,90b\n"
".long 14b,90b\n"
".long 15b,90b\n"
".long 16b,90b\n"
".long 17b,90b\n"
".long 18b,90b\n"
".long 19b,90b\n"
".long 20b,90b\n"
".long 21b,90b\n"
".previous"
: "=d" (sum), "=d" (len), "=a" (src), "=a" (dst),
"=&d" (tmp1), "=d" (tmp2)
: "0" (sum), "1" (len), "2" (src), "3" (dst)
);
return sum;
}
/*
* copy from kernel space while checksumming, otherwise like csum_partial
*/
__wsum
csum_partial_copy_nocheck(const void *src, void *dst, int len)
{
unsigned long tmp1, tmp2;
__wsum sum = 0;
__asm__("movel %2,%4\n\t"
"btst #1,%4\n\t" /* Check alignment */
"jeq 2f\n\t"
"subql #2,%1\n\t" /* buff%4==2: treat first word */
"jgt 1f\n\t"
"addql #2,%1\n\t" /* len was == 2, treat only rest */
"jra 4f\n"
"1:\t"
"movew %2@+,%4\n\t" /* add first word to sum */
"addw %4,%0\n\t"
"movew %4,%3@+\n\t"
"clrl %4\n\t"
"addxl %4,%0\n" /* add X bit */
"2:\t"
/* unrolled loop for the main part: do 8 longs at once */
"movel %1,%4\n\t" /* save len in tmp1 */
"lsrl #5,%1\n\t" /* len/32 */
"jeq 2f\n\t" /* not enough... */
"subql #1,%1\n"
"1:\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"dbra %1,1b\n\t"
"clrl %5\n\t"
"addxl %5,%0\n\t" /* add X bit */
"clrw %1\n\t"
"subql #1,%1\n\t"
"jcc 1b\n"
"2:\t"
"movel %4,%1\n\t" /* restore len from tmp1 */
"andw #0x1c,%4\n\t" /* number of rest longs */
"jeq 4f\n\t"
"lsrw #2,%4\n\t"
"subqw #1,%4\n"
"3:\t"
/* loop for rest longs */
"movel %2@+,%5\n\t"
"addxl %5,%0\n\t"
"movel %5,%3@+\n\t"
"dbra %4,3b\n\t"
"clrl %5\n\t"
"addxl %5,%0\n" /* add X bit */
"4:\t"
/* now check for rest bytes that do not fit into longs */
"andw #3,%1\n\t"
"jeq 7f\n\t"
"clrl %5\n\t" /* clear tmp2 for rest bytes */
"subqw #2,%1\n\t"
"jlt 5f\n\t"
"movew %2@+,%5\n\t" /* have rest >= 2: get word */
"movew %5,%3@+\n\t"
"swap %5\n\t" /* into bits 16..31 */
"tstw %1\n\t" /* another byte? */
"jeq 6f\n"
"5:\t"
"moveb %2@,%5\n\t" /* have odd rest: get byte */
"moveb %5,%3@+\n\t"
"lslw #8,%5\n" /* into bits 8..15; 16..31 untouched */
"6:\t"
"addl %5,%0\n\t" /* now add rest long to sum */
"clrl %5\n\t"
"addxl %5,%0\n" /* add X bit */
"7:\t"
: "=d" (sum), "=d" (len), "=a" (src), "=a" (dst),
"=&d" (tmp1), "=&d" (tmp2)
: "0" (sum), "1" (len), "2" (src), "3" (dst)
);
return(sum);
}
EXPORT_SYMBOL(csum_partial_copy_nocheck);
| linux-master | arch/m68k/lib/checksum.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/string.h>
void *memmove(void *dest, const void *src, size_t n)
{
void *xdest = dest;
size_t temp;
if (!n)
return xdest;
if (dest < src) {
if ((long)dest & 1) {
char *cdest = dest;
const char *csrc = src;
*cdest++ = *csrc++;
dest = cdest;
src = csrc;
n--;
}
if (n > 2 && (long)dest & 2) {
short *sdest = dest;
const short *ssrc = src;
*sdest++ = *ssrc++;
dest = sdest;
src = ssrc;
n -= 2;
}
temp = n >> 2;
if (temp) {
long *ldest = dest;
const long *lsrc = src;
temp--;
do
*ldest++ = *lsrc++;
while (temp--);
dest = ldest;
src = lsrc;
}
if (n & 2) {
short *sdest = dest;
const short *ssrc = src;
*sdest++ = *ssrc++;
dest = sdest;
src = ssrc;
}
if (n & 1) {
char *cdest = dest;
const char *csrc = src;
*cdest = *csrc;
}
} else {
dest = (char *)dest + n;
src = (const char *)src + n;
if ((long)dest & 1) {
char *cdest = dest;
const char *csrc = src;
*--cdest = *--csrc;
dest = cdest;
src = csrc;
n--;
}
if (n > 2 && (long)dest & 2) {
short *sdest = dest;
const short *ssrc = src;
*--sdest = *--ssrc;
dest = sdest;
src = ssrc;
n -= 2;
}
temp = n >> 2;
if (temp) {
long *ldest = dest;
const long *lsrc = src;
temp--;
do
*--ldest = *--lsrc;
while (temp--);
dest = ldest;
src = lsrc;
}
if (n & 2) {
short *sdest = dest;
const short *ssrc = src;
*--sdest = *--ssrc;
dest = sdest;
src = ssrc;
}
if (n & 1) {
char *cdest = dest;
const char *csrc = src;
*--cdest = *--csrc;
}
}
return xdest;
}
EXPORT_SYMBOL(memmove);
| linux-master | arch/m68k/lib/memmove.c |
/* ashrdi3.c extracted from gcc-2.95.2/libgcc2.c which is: */
/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. */
#include <linux/compiler.h>
#include <linux/export.h>
#define BITS_PER_UNIT 8
typedef int SItype __mode(SI);
typedef unsigned int USItype __mode(SI);
typedef int DItype __mode(DI);
typedef int word_type __mode(__word__);
struct DIstruct {SItype high, low;};
typedef union
{
struct DIstruct s;
DItype ll;
} DIunion;
DItype
__ashldi3 (DItype u, word_type b)
{
DIunion w;
word_type bm;
DIunion uu;
if (b == 0)
return u;
uu.ll = u;
bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
if (bm <= 0)
{
w.s.low = 0;
w.s.high = (USItype)uu.s.low << -bm;
}
else
{
USItype carries = (USItype)uu.s.low >> bm;
w.s.low = (USItype)uu.s.low << b;
w.s.high = ((USItype)uu.s.high << b) | carries;
}
return w.ll;
}
EXPORT_SYMBOL(__ashldi3);
| linux-master | arch/m68k/lib/ashldi3.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/string.h>
void *memset(void *s, int c, size_t count)
{
void *xs = s;
size_t temp;
if (!count)
return xs;
c &= 0xff;
c |= c << 8;
c |= c << 16;
if ((long)s & 1) {
char *cs = s;
*cs++ = c;
s = cs;
count--;
}
if (count > 2 && (long)s & 2) {
short *ss = s;
*ss++ = c;
s = ss;
count -= 2;
}
temp = count >> 2;
if (temp) {
long *ls = s;
#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
for (; temp; temp--)
*ls++ = c;
#else
size_t temp1;
asm volatile (
" movel %1,%2\n"
" andw #7,%2\n"
" lsrl #3,%1\n"
" negw %2\n"
" jmp %%pc@(2f,%2:w:2)\n"
"1: movel %3,%0@+\n"
" movel %3,%0@+\n"
" movel %3,%0@+\n"
" movel %3,%0@+\n"
" movel %3,%0@+\n"
" movel %3,%0@+\n"
" movel %3,%0@+\n"
" movel %3,%0@+\n"
"2: dbra %1,1b\n"
" clrw %1\n"
" subql #1,%1\n"
" jpl 1b"
: "=a" (ls), "=d" (temp), "=&d" (temp1)
: "d" (c), "0" (ls), "1" (temp));
#endif
s = ls;
}
if (count & 2) {
short *ss = s;
*ss++ = c;
s = ss;
}
if (count & 1) {
char *cs = s;
*cs = c;
}
return xs;
}
EXPORT_SYMBOL(memset);
| linux-master | arch/m68k/lib/memset.c |
/* ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */
/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. */
#include <linux/compiler.h>
#include <linux/export.h>
#define BITS_PER_UNIT 8
typedef int SItype __mode(SI);
typedef unsigned int USItype __mode(SI);
typedef int DItype __mode(DI);
typedef int word_type __mode(__word__);
struct DIstruct {SItype high, low;};
typedef union
{
struct DIstruct s;
DItype ll;
} DIunion;
DItype
__ashrdi3 (DItype u, word_type b)
{
DIunion w;
word_type bm;
DIunion uu;
if (b == 0)
return u;
uu.ll = u;
bm = (sizeof (SItype) * BITS_PER_UNIT) - b;
if (bm <= 0)
{
/* w.s.high = 1..1 or 0..0 */
w.s.high = uu.s.high >> (sizeof (SItype) * BITS_PER_UNIT - 1);
w.s.low = uu.s.high >> -bm;
}
else
{
USItype carries = (USItype)uu.s.high << bm;
w.s.high = uu.s.high >> b;
w.s.low = ((USItype)uu.s.low >> b) | carries;
}
return w.ll;
}
EXPORT_SYMBOL(__ashrdi3);
| linux-master | arch/m68k/lib/ashrdi3.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/uaccess.h>
unsigned long __generic_copy_from_user(void *to, const void __user *from,
unsigned long n)
{
unsigned long tmp, res;
asm volatile ("\n"
" tst.l %0\n"
" jeq 2f\n"
"1: "MOVES".l (%1)+,%3\n"
" move.l %3,(%2)+\n"
" subq.l #1,%0\n"
" jne 1b\n"
"2: btst #1,%5\n"
" jeq 4f\n"
"3: "MOVES".w (%1)+,%3\n"
" move.w %3,(%2)+\n"
"4: btst #0,%5\n"
" jeq 6f\n"
"5: "MOVES".b (%1)+,%3\n"
" move.b %3,(%2)+\n"
"6:\n"
" .section .fixup,\"ax\"\n"
" .even\n"
"10: lsl.l #2,%0\n"
" btst #1,%5\n"
" jeq 8f\n"
"30: addq.l #2,%0\n"
"8: btst #0,%5\n"
" jeq 6b\n"
"50: addq.l #1,%0\n"
" jra 6b\n"
" .previous\n"
"\n"
" .section __ex_table,\"a\"\n"
" .align 4\n"
" .long 1b,10b\n"
" .long 3b,30b\n"
" .long 5b,50b\n"
" .previous"
: "=d" (res), "+a" (from), "+a" (to), "=&d" (tmp)
: "0" (n / 4), "d" (n & 3));
return res;
}
EXPORT_SYMBOL(__generic_copy_from_user);
unsigned long __generic_copy_to_user(void __user *to, const void *from,
unsigned long n)
{
unsigned long tmp, res;
asm volatile ("\n"
" tst.l %0\n"
" jeq 4f\n"
"1: move.l (%1)+,%3\n"
"2: "MOVES".l %3,(%2)+\n"
"3: subq.l #1,%0\n"
" jne 1b\n"
"4: btst #1,%5\n"
" jeq 6f\n"
" move.w (%1)+,%3\n"
"5: "MOVES".w %3,(%2)+\n"
"6: btst #0,%5\n"
" jeq 8f\n"
" move.b (%1)+,%3\n"
"7: "MOVES".b %3,(%2)+\n"
"8:\n"
" .section .fixup,\"ax\"\n"
" .even\n"
"20: lsl.l #2,%0\n"
"50: add.l %5,%0\n"
" jra 8b\n"
" .previous\n"
"\n"
" .section __ex_table,\"a\"\n"
" .align 4\n"
" .long 2b,20b\n"
" .long 3b,20b\n"
" .long 5b,50b\n"
" .long 6b,50b\n"
" .long 7b,50b\n"
" .long 8b,50b\n"
" .previous"
: "=d" (res), "+a" (from), "+a" (to), "=&d" (tmp)
: "0" (n / 4), "d" (n & 3));
return res;
}
EXPORT_SYMBOL(__generic_copy_to_user);
/*
* Zero Userspace
*/
unsigned long __clear_user(void __user *to, unsigned long n)
{
unsigned long res;
asm volatile ("\n"
" tst.l %0\n"
" jeq 3f\n"
"1: "MOVES".l %2,(%1)+\n"
"2: subq.l #1,%0\n"
" jne 1b\n"
"3: btst #1,%4\n"
" jeq 5f\n"
"4: "MOVES".w %2,(%1)+\n"
"5: btst #0,%4\n"
" jeq 7f\n"
"6: "MOVES".b %2,(%1)\n"
"7:\n"
" .section .fixup,\"ax\"\n"
" .even\n"
"10: lsl.l #2,%0\n"
"40: add.l %4,%0\n"
" jra 7b\n"
" .previous\n"
"\n"
" .section __ex_table,\"a\"\n"
" .align 4\n"
" .long 1b,10b\n"
" .long 2b,10b\n"
" .long 4b,40b\n"
" .long 5b,40b\n"
" .long 6b,40b\n"
" .long 7b,40b\n"
" .previous"
: "=d" (res), "+a" (to)
: "d" (0), "0" (n / 4), "d" (n & 3));
return res;
}
EXPORT_SYMBOL(__clear_user);
| linux-master | arch/m68k/lib/uaccess.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Based upon linux/arch/m68k/mm/sun3mmu.c
* Based upon linux/arch/ppc/mm/mmu_context.c
*
* Implementations of mm routines specific to the Coldfire MMU.
*
* Copyright (c) 2008 Freescale Semiconductor, Inc.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/memblock.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/mmu_context.h>
#include <asm/mcf_pgalloc.h>
#include <asm/tlbflush.h>
#include <asm/pgalloc.h>
#define KMAPAREA(x) ((x >= VMALLOC_START) && (x < KMAP_END))
mm_context_t next_mmu_context;
unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
atomic_t nr_free_contexts;
struct mm_struct *context_mm[LAST_CONTEXT+1];
unsigned long num_pages;
/*
* ColdFire paging_init derived from sun3.
*/
void __init paging_init(void)
{
pgd_t *pg_dir;
pte_t *pg_table;
unsigned long address, size;
unsigned long next_pgtable, bootmem_end;
unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
int i;
empty_zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!empty_zero_page)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
pg_dir = swapper_pg_dir;
memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
size = num_pages * sizeof(pte_t);
size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
next_pgtable = (unsigned long) memblock_alloc(size, PAGE_SIZE);
if (!next_pgtable)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, size, PAGE_SIZE);
bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK;
pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
address = PAGE_OFFSET;
while (address < (unsigned long)high_memory) {
pg_table = (pte_t *) next_pgtable;
next_pgtable += PTRS_PER_PTE * sizeof(pte_t);
pgd_val(*pg_dir) = (unsigned long) pg_table;
pg_dir++;
/* now change pg_table to kernel virtual addresses */
for (i = 0; i < PTRS_PER_PTE; ++i, ++pg_table) {
pte_t pte = pfn_pte(virt_to_pfn((void *)address),
PAGE_INIT);
if (address >= (unsigned long) high_memory)
pte_val(pte) = 0;
set_pte(pg_table, pte);
address += PAGE_SIZE;
}
}
current->mm = NULL;
max_zone_pfn[ZONE_DMA] = PFN_DOWN(_ramend);
free_area_init(max_zone_pfn);
}
int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
{
unsigned long flags, mmuar, mmutr;
struct mm_struct *mm;
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte = NULL;
int ret = -1;
int asid;
local_irq_save(flags);
mmuar = (dtlb) ? mmu_read(MMUAR) :
regs->pc + (extension_word * sizeof(long));
mm = (!user_mode(regs) && KMAPAREA(mmuar)) ? &init_mm : current->mm;
if (!mm)
goto out;
pgd = pgd_offset(mm, mmuar);
if (pgd_none(*pgd))
goto out;
p4d = p4d_offset(pgd, mmuar);
if (p4d_none(*p4d))
goto out;
pud = pud_offset(p4d, mmuar);
if (pud_none(*pud))
goto out;
pmd = pmd_offset(pud, mmuar);
if (pmd_none(*pmd))
goto out;
pte = (KMAPAREA(mmuar)) ? pte_offset_kernel(pmd, mmuar)
: pte_offset_map(pmd, mmuar);
if (!pte || pte_none(*pte) || !pte_present(*pte))
goto out;
if (write) {
if (!pte_write(*pte))
goto out;
set_pte(pte, pte_mkdirty(*pte));
}
set_pte(pte, pte_mkyoung(*pte));
asid = mm->context & 0xff;
if (!pte_dirty(*pte) && !KMAPAREA(mmuar))
set_pte(pte, pte_wrprotect(*pte));
mmutr = (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) | MMUTR_V;
if ((mmuar < TASK_UNMAPPED_BASE) || (mmuar >= TASK_SIZE))
mmutr |= (pte->pte & CF_PAGE_MMUTR_MASK) >> CF_PAGE_MMUTR_SHIFT;
mmu_write(MMUTR, mmutr);
mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) |
((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X);
if (dtlb)
mmu_write(MMUOR, MMUOR_ACC | MMUOR_UAA);
else
mmu_write(MMUOR, MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA);
ret = 0;
out:
if (pte && !KMAPAREA(mmuar))
pte_unmap(pte);
local_irq_restore(flags);
return ret;
}
void __init cf_bootmem_alloc(void)
{
unsigned long memstart;
/* _rambase and _ramend will be naturally page aligned */
m68k_memory[0].addr = _rambase;
m68k_memory[0].size = _ramend - _rambase;
memblock_add_node(m68k_memory[0].addr, m68k_memory[0].size, 0,
MEMBLOCK_NONE);
/* compute total pages in system */
num_pages = PFN_DOWN(_ramend - _rambase);
/* page numbers */
memstart = PAGE_ALIGN(_ramstart);
min_low_pfn = PFN_DOWN(_rambase);
max_pfn = max_low_pfn = PFN_DOWN(_ramend);
high_memory = (void *)_ramend;
/* Reserve kernel text/data/bss */
memblock_reserve(_rambase, memstart - _rambase);
m68k_virt_to_node_shift = fls(_ramend - 1) - 6;
module_fixup(NULL, __start_fixup, __stop_fixup);
/* setup node data */
m68k_setup_node(0);
}
/*
* Initialize the context management stuff.
* The following was taken from arch/ppc/mmu_context.c
*/
void __init cf_mmu_context_init(void)
{
/*
* Some processors have too few contexts to reserve one for
* init_mm, and require using context 0 for a normal task.
* Other processors reserve the use of context zero for the kernel.
* This code assumes FIRST_CONTEXT < 32.
*/
context_map[0] = (1 << FIRST_CONTEXT) - 1;
next_mmu_context = FIRST_CONTEXT;
atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
}
/*
* Steal a context from a task that has one at the moment.
* This isn't an LRU system, it just frees up each context in
* turn (sort-of pseudo-random replacement :). This would be the
* place to implement an LRU scheme if anyone was motivated to do it.
* -- paulus
*/
void steal_context(void)
{
struct mm_struct *mm;
/*
* free up context `next_mmu_context'
* if we shouldn't free context 0, don't...
*/
if (next_mmu_context < FIRST_CONTEXT)
next_mmu_context = FIRST_CONTEXT;
mm = context_mm[next_mmu_context];
flush_tlb_mm(mm);
destroy_context(mm);
}
static const pgprot_t protection_map[16] = {
[VM_NONE] = PAGE_NONE,
[VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE),
[VM_WRITE] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_WRITABLE),
[VM_WRITE | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE |
CF_PAGE_WRITABLE),
[VM_EXEC] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_EXEC),
[VM_EXEC | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE |
CF_PAGE_EXEC),
[VM_EXEC | VM_WRITE] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_WRITABLE |
CF_PAGE_EXEC),
[VM_EXEC | VM_WRITE | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE |
CF_PAGE_WRITABLE |
CF_PAGE_EXEC),
[VM_SHARED] = PAGE_NONE,
[VM_SHARED | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE),
[VM_SHARED | VM_WRITE] = PAGE_SHARED,
[VM_SHARED | VM_WRITE | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE |
CF_PAGE_SHARED),
[VM_SHARED | VM_EXEC] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_EXEC),
[VM_SHARED | VM_EXEC | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE |
CF_PAGE_EXEC),
[VM_SHARED | VM_EXEC | VM_WRITE] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_SHARED |
CF_PAGE_EXEC),
[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = __pgprot(CF_PAGE_VALID |
CF_PAGE_ACCESSED |
CF_PAGE_READABLE |
CF_PAGE_SHARED |
CF_PAGE_EXEC)
};
DECLARE_VM_GET_PAGE_PROT
| linux-master | arch/m68k/mm/mcfmmu.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/sun3mmu.c
*
* Implementations of mm routines specific to the sun3 MMU.
*
* Moved here 8/20/1999 Sam Creasey
*
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/memblock.h>
#include <asm/setup.h>
#include <linux/uaccess.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/io.h>
extern void mmu_emu_init (unsigned long bootmem_end);
const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n";
extern unsigned long num_pages;
/* For the sun3 we try to follow the i386 paging_init() more closely */
/* start_mem and end_mem have PAGE_OFFSET added already */
/* now sets up tables using sun3 PTEs rather than i386 as before. --m */
void __init paging_init(void)
{
pgd_t * pg_dir;
pte_t * pg_table;
int i;
unsigned long address;
unsigned long next_pgtable;
unsigned long bootmem_end;
unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0, };
unsigned long size;
empty_zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!empty_zero_page)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
address = PAGE_OFFSET;
pg_dir = swapper_pg_dir;
memset (swapper_pg_dir, 0, sizeof (swapper_pg_dir));
memset (kernel_pg_dir, 0, sizeof (kernel_pg_dir));
size = num_pages * sizeof(pte_t);
size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
next_pgtable = (unsigned long)memblock_alloc(size, PAGE_SIZE);
if (!next_pgtable)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, size, PAGE_SIZE);
bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK;
/* Map whole memory from PAGE_OFFSET (0x0E000000) */
pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
while (address < (unsigned long)high_memory) {
pg_table = (pte_t *) __pa (next_pgtable);
next_pgtable += PTRS_PER_PTE * sizeof (pte_t);
pgd_val(*pg_dir) = (unsigned long) pg_table;
pg_dir++;
/* now change pg_table to kernel virtual addresses */
pg_table = (pte_t *) __va ((unsigned long) pg_table);
for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table) {
pte_t pte = pfn_pte(virt_to_pfn((void *)address), PAGE_INIT);
if (address >= (unsigned long)high_memory)
pte_val (pte) = 0;
set_pte (pg_table, pte);
address += PAGE_SIZE;
}
}
mmu_emu_init(bootmem_end);
current->mm = NULL;
/* memory sizing is a hack stolen from motorola.c.. hope it works for us */
max_zone_pfn[ZONE_DMA] = ((unsigned long)high_memory) >> PAGE_SHIFT;
/* I really wish I knew why the following change made things better... -- Sam */
free_area_init(max_zone_pfn);
}
static const pgprot_t protection_map[16] = {
[VM_NONE] = PAGE_NONE,
[VM_READ] = PAGE_READONLY,
[VM_WRITE] = PAGE_COPY,
[VM_WRITE | VM_READ] = PAGE_COPY,
[VM_EXEC] = PAGE_READONLY,
[VM_EXEC | VM_READ] = PAGE_READONLY,
[VM_EXEC | VM_WRITE] = PAGE_COPY,
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY,
[VM_SHARED] = PAGE_NONE,
[VM_SHARED | VM_READ] = PAGE_READONLY,
[VM_SHARED | VM_WRITE] = PAGE_SHARED,
[VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED,
[VM_SHARED | VM_EXEC] = PAGE_READONLY,
[VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY,
[VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED,
[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED
};
DECLARE_VM_GET_PAGE_PROT
| linux-master | arch/m68k/mm/sun3mmu.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/kmap.c
*
* Copyright (C) 1997 Roman Hodek
*
* 10/01/99 cleaned up the code and changing to the same interface
* used by other architectures /Roman Zippel
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/tlbflush.h>
#undef DEBUG
/*
* For 040/060 we can use the virtual memory area like other architectures,
* but for 020/030 we want to use early termination page descriptors and we
* can't mix this with normal page descriptors, so we have to copy that code
* (mm/vmalloc.c) and return appropriately aligned addresses.
*/
#ifdef CPU_M68040_OR_M68060_ONLY
#define IO_SIZE PAGE_SIZE
static inline struct vm_struct *get_io_area(unsigned long size)
{
return get_vm_area(size, VM_IOREMAP);
}
static inline void free_io_area(void *addr)
{
vfree((void *)(PAGE_MASK & (unsigned long)addr));
}
#else
#define IO_SIZE PMD_SIZE
static struct vm_struct *iolist;
/*
* __free_io_area unmaps nearly everything, so be careful
* Currently it doesn't free pointer/page tables anymore but this
* wasn't used anyway and might be added later.
*/
static void __free_io_area(void *addr, unsigned long size)
{
unsigned long virtaddr = (unsigned long)addr;
pgd_t *pgd_dir;
p4d_t *p4d_dir;
pud_t *pud_dir;
pmd_t *pmd_dir;
pte_t *pte_dir;
while ((long)size > 0) {
pgd_dir = pgd_offset_k(virtaddr);
p4d_dir = p4d_offset(pgd_dir, virtaddr);
pud_dir = pud_offset(p4d_dir, virtaddr);
if (pud_bad(*pud_dir)) {
printk("iounmap: bad pud(%08lx)\n", pud_val(*pud_dir));
pud_clear(pud_dir);
return;
}
pmd_dir = pmd_offset(pud_dir, virtaddr);
#if CONFIG_PGTABLE_LEVELS == 3
if (CPU_IS_020_OR_030) {
int pmd_type = pmd_val(*pmd_dir) & _DESCTYPE_MASK;
if (pmd_type == _PAGE_PRESENT) {
pmd_clear(pmd_dir);
virtaddr += PMD_SIZE;
size -= PMD_SIZE;
} else if (pmd_type == 0)
continue;
}
#endif
if (pmd_bad(*pmd_dir)) {
printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
pmd_clear(pmd_dir);
return;
}
pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
pte_val(*pte_dir) = 0;
virtaddr += PAGE_SIZE;
size -= PAGE_SIZE;
}
flush_tlb_all();
}
static struct vm_struct *get_io_area(unsigned long size)
{
unsigned long addr;
struct vm_struct **p, *tmp, *area;
area = kmalloc(sizeof(*area), GFP_KERNEL);
if (!area)
return NULL;
addr = KMAP_START;
for (p = &iolist; (tmp = *p) ; p = &tmp->next) {
if (size + addr < (unsigned long)tmp->addr)
break;
if (addr > KMAP_END-size) {
kfree(area);
return NULL;
}
addr = tmp->size + (unsigned long)tmp->addr;
}
area->addr = (void *)addr;
area->size = size + IO_SIZE;
area->next = *p;
*p = area;
return area;
}
static inline void free_io_area(void *addr)
{
struct vm_struct **p, *tmp;
if (!addr)
return;
addr = (void *)((unsigned long)addr & -IO_SIZE);
for (p = &iolist ; (tmp = *p) ; p = &tmp->next) {
if (tmp->addr == addr) {
*p = tmp->next;
/* remove gap added in get_io_area() */
__free_io_area(tmp->addr, tmp->size - IO_SIZE);
kfree(tmp);
return;
}
}
}
#endif
/*
* Map some physical address range into the kernel address space.
*/
/* Rewritten by Andreas Schwab to remove all races. */
void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
{
struct vm_struct *area;
unsigned long virtaddr, retaddr;
long offset;
pgd_t *pgd_dir;
p4d_t *p4d_dir;
pud_t *pud_dir;
pmd_t *pmd_dir;
pte_t *pte_dir;
/*
* Don't allow mappings that wrap..
*/
if (!size || physaddr > (unsigned long)(-size))
return NULL;
#ifdef CONFIG_AMIGA
if (MACH_IS_AMIGA) {
if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000)
&& (cacheflag == IOMAP_NOCACHE_SER))
return (void __iomem *)physaddr;
}
#endif
#ifdef CONFIG_VIRT
if (MACH_IS_VIRT) {
if (physaddr >= 0xff000000 && cacheflag == IOMAP_NOCACHE_SER)
return (void __iomem *)physaddr;
}
#endif
#ifdef CONFIG_COLDFIRE
if (__cf_internalio(physaddr))
return (void __iomem *) physaddr;
#endif
#ifdef DEBUG
printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
#endif
/*
* Mappings have to be aligned
*/
offset = physaddr & (IO_SIZE - 1);
physaddr &= -IO_SIZE;
size = (size + offset + IO_SIZE - 1) & -IO_SIZE;
/*
* Ok, go for it..
*/
area = get_io_area(size);
if (!area)
return NULL;
virtaddr = (unsigned long)area->addr;
retaddr = virtaddr + offset;
#ifdef DEBUG
printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr);
#endif
/*
* add cache and table flags to physical address
*/
if (CPU_IS_040_OR_060) {
physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 |
_PAGE_ACCESSED | _PAGE_DIRTY);
switch (cacheflag) {
case IOMAP_FULL_CACHING:
physaddr |= _PAGE_CACHE040;
break;
case IOMAP_NOCACHE_SER:
default:
physaddr |= _PAGE_NOCACHE_S;
break;
case IOMAP_NOCACHE_NONSER:
physaddr |= _PAGE_NOCACHE;
break;
case IOMAP_WRITETHROUGH:
physaddr |= _PAGE_CACHE040W;
break;
}
} else {
physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED |
_PAGE_DIRTY | _PAGE_READWRITE);
switch (cacheflag) {
case IOMAP_NOCACHE_SER:
case IOMAP_NOCACHE_NONSER:
default:
physaddr |= _PAGE_NOCACHE030;
break;
case IOMAP_FULL_CACHING:
case IOMAP_WRITETHROUGH:
break;
}
}
while ((long)size > 0) {
#ifdef DEBUG
if (!(virtaddr & (PMD_SIZE-1)))
printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr);
#endif
pgd_dir = pgd_offset_k(virtaddr);
p4d_dir = p4d_offset(pgd_dir, virtaddr);
pud_dir = pud_offset(p4d_dir, virtaddr);
pmd_dir = pmd_alloc(&init_mm, pud_dir, virtaddr);
if (!pmd_dir) {
printk("ioremap: no mem for pmd_dir\n");
return NULL;
}
#if CONFIG_PGTABLE_LEVELS == 3
if (CPU_IS_020_OR_030) {
pmd_val(*pmd_dir) = physaddr;
physaddr += PMD_SIZE;
virtaddr += PMD_SIZE;
size -= PMD_SIZE;
} else
#endif
{
pte_dir = pte_alloc_kernel(pmd_dir, virtaddr);
if (!pte_dir) {
printk("ioremap: no mem for pte_dir\n");
return NULL;
}
pte_val(*pte_dir) = physaddr;
virtaddr += PAGE_SIZE;
physaddr += PAGE_SIZE;
size -= PAGE_SIZE;
}
}
#ifdef DEBUG
printk("\n");
#endif
flush_tlb_all();
return (void __iomem *)retaddr;
}
EXPORT_SYMBOL(__ioremap);
/*
* Unmap an ioremap()ed region again
*/
void iounmap(void __iomem *addr)
{
#ifdef CONFIG_AMIGA
if (MACH_IS_AMIGA &&
((unsigned long)addr >= 0x40000000) &&
((unsigned long)addr < 0x60000000))
return;
#endif
#ifdef CONFIG_VIRT
if (MACH_IS_VIRT && (unsigned long)addr >= 0xff000000)
return;
#endif
#ifdef CONFIG_COLDFIRE
if (cf_internalio(addr))
return;
#endif
free_io_area((__force void *)addr);
}
EXPORT_SYMBOL(iounmap);
/*
* Set new cache mode for some kernel address space.
* The caller must push data for that range itself, if such data may already
* be in the cache.
*/
void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
{
unsigned long virtaddr = (unsigned long)addr;
pgd_t *pgd_dir;
p4d_t *p4d_dir;
pud_t *pud_dir;
pmd_t *pmd_dir;
pte_t *pte_dir;
if (CPU_IS_040_OR_060) {
switch (cmode) {
case IOMAP_FULL_CACHING:
cmode = _PAGE_CACHE040;
break;
case IOMAP_NOCACHE_SER:
default:
cmode = _PAGE_NOCACHE_S;
break;
case IOMAP_NOCACHE_NONSER:
cmode = _PAGE_NOCACHE;
break;
case IOMAP_WRITETHROUGH:
cmode = _PAGE_CACHE040W;
break;
}
} else {
switch (cmode) {
case IOMAP_NOCACHE_SER:
case IOMAP_NOCACHE_NONSER:
default:
cmode = _PAGE_NOCACHE030;
break;
case IOMAP_FULL_CACHING:
case IOMAP_WRITETHROUGH:
cmode = 0;
}
}
while ((long)size > 0) {
pgd_dir = pgd_offset_k(virtaddr);
p4d_dir = p4d_offset(pgd_dir, virtaddr);
pud_dir = pud_offset(p4d_dir, virtaddr);
if (pud_bad(*pud_dir)) {
printk("iocachemode: bad pud(%08lx)\n", pud_val(*pud_dir));
pud_clear(pud_dir);
return;
}
pmd_dir = pmd_offset(pud_dir, virtaddr);
#if CONFIG_PGTABLE_LEVELS == 3
if (CPU_IS_020_OR_030) {
unsigned long pmd = pmd_val(*pmd_dir);
if ((pmd & _DESCTYPE_MASK) == _PAGE_PRESENT) {
*pmd_dir = __pmd((pmd & _CACHEMASK040) | cmode);
virtaddr += PMD_SIZE;
size -= PMD_SIZE;
continue;
}
}
#endif
if (pmd_bad(*pmd_dir)) {
printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
pmd_clear(pmd_dir);
return;
}
pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode;
virtaddr += PAGE_SIZE;
size -= PAGE_SIZE;
}
flush_tlb_all();
}
EXPORT_SYMBOL(kernel_set_cachemode);
| linux-master | arch/m68k/mm/kmap.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/memory.c
*
* Copyright (C) 1995 Hamish Macdonald
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/gfp.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/traps.h>
#include <asm/machdep.h>
/* invalidate page in both caches */
static inline void clear040(unsigned long paddr)
{
asm volatile (
"nop\n\t"
".chip 68040\n\t"
"cinvp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (paddr));
}
/* invalidate page in i-cache */
static inline void cleari040(unsigned long paddr)
{
asm volatile (
"nop\n\t"
".chip 68040\n\t"
"cinvp %%ic,(%0)\n\t"
".chip 68k"
: : "a" (paddr));
}
/* push page in both caches */
/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
static inline void push040(unsigned long paddr)
{
asm volatile (
"nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (paddr));
}
/* push and invalidate page in both caches, must disable ints
* to avoid invalidating valid data */
static inline void pushcl040(unsigned long paddr)
{
unsigned long flags;
local_irq_save(flags);
push040(paddr);
if (CPU_IS_060)
clear040(paddr);
local_irq_restore(flags);
}
/*
* 040: Hit every page containing an address in the range paddr..paddr+len-1.
* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
* Hit every page until there is a page or less to go. Hit the next page,
* and the one after that if the range hits it.
*/
/* ++roman: A little bit more care is required here: The CINVP instruction
* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
* and the end of the region must be treated differently if they are not
* exactly at the beginning or end of a page boundary. Else, maybe too much
* data becomes invalidated and thus lost forever. CPUSHP does what we need:
* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
* for discovering the problem!)
*/
/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
* the DPI bit in the CACR; would it cause problems with temporarily changing
* this?). So we have to push first and then additionally to invalidate.
*/
/*
* cache_clear() semantics: Clear any cache entries for the area in question,
* without writing back dirty entries first. This is useful if the data will
* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
* _physical_ address.
*/
void cache_clear (unsigned long paddr, int len)
{
if (CPU_IS_COLDFIRE) {
clear_cf_bcache(0, DCACHE_MAX_ADDR);
} else if (CPU_IS_040_OR_060) {
int tmp;
/*
* We need special treatment for the first page, in case it
* is not page-aligned. Page align the addresses to work
* around bug I17 in the 68060.
*/
if ((tmp = -paddr & (PAGE_SIZE - 1))) {
pushcl040(paddr & PAGE_MASK);
if ((len -= tmp) <= 0)
return;
paddr += tmp;
}
tmp = PAGE_SIZE;
paddr &= PAGE_MASK;
while ((len -= tmp) >= 0) {
clear040(paddr);
paddr += tmp;
}
if ((len += tmp))
/* a page boundary gets crossed at the end */
pushcl040(paddr);
}
else /* 68030 or 68020 */
asm volatile ("movec %/cacr,%/d0\n\t"
"oriw %0,%/d0\n\t"
"movec %/d0,%/cacr"
: : "i" (FLUSH_I_AND_D)
: "d0");
#ifdef CONFIG_M68K_L2_CACHE
if(mach_l2_flush)
mach_l2_flush(0);
#endif
}
EXPORT_SYMBOL(cache_clear);
/*
* cache_push() semantics: Write back any dirty cache data in the given area,
* and invalidate the range in the instruction cache. It needs not (but may)
* invalidate those entries also in the data cache. The range is defined by a
* _physical_ address.
*/
void cache_push (unsigned long paddr, int len)
{
if (CPU_IS_COLDFIRE) {
flush_cf_bcache(0, DCACHE_MAX_ADDR);
} else if (CPU_IS_040_OR_060) {
int tmp = PAGE_SIZE;
/*
* on 68040 or 68060, push cache lines for pages in the range;
* on the '040 this also invalidates the pushed lines, but not on
* the '060!
*/
len += paddr & (PAGE_SIZE - 1);
/*
* Work around bug I17 in the 68060 affecting some instruction
* lines not being invalidated properly.
*/
paddr &= PAGE_MASK;
do {
push040(paddr);
paddr += tmp;
} while ((len -= tmp) > 0);
}
/*
* 68030/68020 have no writeback cache. On the other hand,
* cache_push is actually a superset of cache_clear (the lines
* get written back and invalidated), so we should make sure
* to perform the corresponding actions. After all, this is getting
* called in places where we've just loaded code, or whatever, so
* flushing the icache is appropriate; flushing the dcache shouldn't
* be required.
*/
else /* 68030 or 68020 */
asm volatile ("movec %/cacr,%/d0\n\t"
"oriw %0,%/d0\n\t"
"movec %/d0,%/cacr"
: : "i" (FLUSH_I)
: "d0");
#ifdef CONFIG_M68K_L2_CACHE
if(mach_l2_flush)
mach_l2_flush(1);
#endif
}
EXPORT_SYMBOL(cache_push);
| linux-master | arch/m68k/mm/memory.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/init.c
*
* Copyright (C) 1995 Hamish Macdonald
*
* Contains common initialization routines, specific init code moved
* to motorola.c and sun3mmu.c
*/
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/gfp.h>
#include <asm/setup.h>
#include <linux/uaccess.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/io.h>
#ifdef CONFIG_ATARI
#include <asm/atari_stram.h>
#endif
#include <asm/sections.h>
#include <asm/tlb.h>
/*
* ZERO_PAGE is a special page that is used for zero-initialized
* data and COW.
*/
void *empty_zero_page;
EXPORT_SYMBOL(empty_zero_page);
#ifdef CONFIG_MMU
int m68k_virt_to_node_shift;
void __init m68k_setup_node(int node)
{
node_set_online(node);
}
#else /* CONFIG_MMU */
/*
* paging_init() continues the virtual memory environment setup which
* was begun by the code in arch/head.S.
* The parameters are pointers to where to stick the starting and ending
* addresses of available kernel virtual memory.
*/
void __init paging_init(void)
{
/*
* Make sure start_mem is page aligned, otherwise bootmem and
* page_alloc get different views of the world.
*/
unsigned long end_mem = memory_end & PAGE_MASK;
unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0, };
high_memory = (void *) end_mem;
empty_zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!empty_zero_page)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
max_zone_pfn[ZONE_DMA] = end_mem >> PAGE_SHIFT;
free_area_init(max_zone_pfn);
}
#endif /* CONFIG_MMU */
void free_initmem(void)
{
#ifndef CONFIG_MMU_SUN3
free_initmem_default(-1);
#endif /* CONFIG_MMU_SUN3 */
}
#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE)
#define VECTORS &vectors[0]
#else
#define VECTORS _ramvec
#endif
static inline void init_pointer_tables(void)
{
#if defined(CONFIG_MMU) && !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
int i, j;
/* insert pointer tables allocated so far into the tablelist */
init_pointer_table(kernel_pg_dir, TABLE_PGD);
for (i = 0; i < PTRS_PER_PGD; i++) {
pud_t *pud = (pud_t *)&kernel_pg_dir[i];
pmd_t *pmd_dir;
if (!pud_present(*pud))
continue;
pmd_dir = (pmd_t *)pgd_page_vaddr(kernel_pg_dir[i]);
init_pointer_table(pmd_dir, TABLE_PMD);
for (j = 0; j < PTRS_PER_PMD; j++) {
pmd_t *pmd = &pmd_dir[j];
pte_t *pte_dir;
if (!pmd_present(*pmd))
continue;
pte_dir = (pte_t *)pmd_page_vaddr(*pmd);
init_pointer_table(pte_dir, TABLE_PTE);
}
}
#endif
}
void __init mem_init(void)
{
/* this will put all memory onto the freelists */
memblock_free_all();
init_pointer_tables();
}
| linux-master | arch/m68k/mm/init.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/motorola.c
*
* Routines specific to the Motorola MMU, originally from:
* linux/arch/m68k/init.c
* which are Copyright (C) 1995 Hamish Macdonald
*
* Moved 8/20/1999 Sam Creasey
*/
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/memblock.h>
#include <linux/gfp.h>
#include <asm/setup.h>
#include <linux/uaccess.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/machdep.h>
#include <asm/io.h>
#ifdef CONFIG_ATARI
#include <asm/atari_stram.h>
#endif
#include <asm/sections.h>
#undef DEBUG
#ifndef mm_cachebits
/*
* Bits to add to page descriptors for "normal" caching mode.
* For 68020/030 this is 0.
* For 68040, this is _PAGE_CACHE040 (cachable, copyback)
*/
unsigned long mm_cachebits;
EXPORT_SYMBOL(mm_cachebits);
#endif
/* Prior to calling these routines, the page should have been flushed
* from both the cache and ATC, or the CPU might not notice that the
* cache setting for the page has been changed. -jskov
*/
static inline void nocache_page(void *vaddr)
{
unsigned long addr = (unsigned long)vaddr;
if (CPU_IS_040_OR_060) {
pte_t *ptep = virt_to_kpte(addr);
*ptep = pte_mknocache(*ptep);
}
}
static inline void cache_page(void *vaddr)
{
unsigned long addr = (unsigned long)vaddr;
if (CPU_IS_040_OR_060) {
pte_t *ptep = virt_to_kpte(addr);
*ptep = pte_mkcache(*ptep);
}
}
/*
* Motorola 680x0 user's manual recommends using uncached memory for address
* translation tables.
*
* Seeing how the MMU can be external on (some of) these chips, that seems like
* a very important recommendation to follow. Provide some helpers to combat
* 'variation' amongst the users of this.
*/
void mmu_page_ctor(void *page)
{
__flush_pages_to_ram(page, 1);
flush_tlb_kernel_page(page);
nocache_page(page);
}
void mmu_page_dtor(void *page)
{
cache_page(page);
}
/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
struct page instead of separately kmalloced struct. Stolen from
arch/sparc/mm/srmmu.c ... */
typedef struct list_head ptable_desc;
static struct list_head ptable_list[2] = {
LIST_HEAD_INIT(ptable_list[0]),
LIST_HEAD_INIT(ptable_list[1]),
};
#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page((void *)(page))->lru))
#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
#define PD_MARKBITS(dp) (*(unsigned int *)&PD_PAGE(dp)->index)
static const int ptable_shift[2] = {
7+2, /* PGD, PMD */
6+2, /* PTE */
};
#define ptable_size(type) (1U << ptable_shift[type])
#define ptable_mask(type) ((1U << (PAGE_SIZE / ptable_size(type))) - 1)
void __init init_pointer_table(void *table, int type)
{
ptable_desc *dp;
unsigned long ptable = (unsigned long)table;
unsigned long page = ptable & PAGE_MASK;
unsigned int mask = 1U << ((ptable - page)/ptable_size(type));
dp = PD_PTABLE(page);
if (!(PD_MARKBITS(dp) & mask)) {
PD_MARKBITS(dp) = ptable_mask(type);
list_add(dp, &ptable_list[type]);
}
PD_MARKBITS(dp) &= ~mask;
pr_debug("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
/* unreserve the page so it's possible to free that page */
__ClearPageReserved(PD_PAGE(dp));
init_page_count(PD_PAGE(dp));
return;
}
void *get_pointer_table(int type)
{
ptable_desc *dp = ptable_list[type].next;
unsigned int mask = list_empty(&ptable_list[type]) ? 0 : PD_MARKBITS(dp);
unsigned int tmp, off;
/*
* For a pointer table for a user process address space, a
* table is taken from a page allocated for the purpose. Each
* page can hold 8 pointer tables. The page is remapped in
* virtual address space to be noncacheable.
*/
if (mask == 0) {
void *page;
ptable_desc *new;
if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
return NULL;
if (type == TABLE_PTE) {
/*
* m68k doesn't have SPLIT_PTE_PTLOCKS for not having
* SMP.
*/
pagetable_pte_ctor(virt_to_ptdesc(page));
}
mmu_page_ctor(page);
new = PD_PTABLE(page);
PD_MARKBITS(new) = ptable_mask(type) - 1;
list_add_tail(new, dp);
return (pmd_t *)page;
}
for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += ptable_size(type))
;
PD_MARKBITS(dp) = mask & ~tmp;
if (!PD_MARKBITS(dp)) {
/* move to end of list */
list_move_tail(dp, &ptable_list[type]);
}
return page_address(PD_PAGE(dp)) + off;
}
int free_pointer_table(void *table, int type)
{
ptable_desc *dp;
unsigned long ptable = (unsigned long)table;
unsigned long page = ptable & PAGE_MASK;
unsigned int mask = 1U << ((ptable - page)/ptable_size(type));
dp = PD_PTABLE(page);
if (PD_MARKBITS (dp) & mask)
panic ("table already free!");
PD_MARKBITS (dp) |= mask;
if (PD_MARKBITS(dp) == ptable_mask(type)) {
/* all tables in page are free, free page */
list_del(dp);
mmu_page_dtor((void *)page);
if (type == TABLE_PTE)
pagetable_pte_dtor(virt_to_ptdesc((void *)page));
free_page (page);
return 1;
} else if (ptable_list[type].next != dp) {
/*
* move this descriptor to the front of the list, since
* it has one or more free tables.
*/
list_move(dp, &ptable_list[type]);
}
return 0;
}
/* size of memory already mapped in head.S */
extern __initdata unsigned long m68k_init_mapped_size;
extern unsigned long availmem;
static pte_t *last_pte_table __initdata = NULL;
static pte_t * __init kernel_page_table(void)
{
pte_t *pte_table = last_pte_table;
if (PAGE_ALIGNED(last_pte_table)) {
pte_table = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE);
if (!pte_table) {
panic("%s: Failed to allocate %lu bytes align=%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
}
clear_page(pte_table);
mmu_page_ctor(pte_table);
last_pte_table = pte_table;
}
last_pte_table += PTRS_PER_PTE;
return pte_table;
}
static pmd_t *last_pmd_table __initdata = NULL;
static pmd_t * __init kernel_ptr_table(void)
{
if (!last_pmd_table) {
unsigned long pmd, last;
int i;
/* Find the last ptr table that was used in head.S and
* reuse the remaining space in that page for further
* ptr tables.
*/
last = (unsigned long)kernel_pg_dir;
for (i = 0; i < PTRS_PER_PGD; i++) {
pud_t *pud = (pud_t *)(&kernel_pg_dir[i]);
if (!pud_present(*pud))
continue;
pmd = pgd_page_vaddr(kernel_pg_dir[i]);
if (pmd > last)
last = pmd;
}
last_pmd_table = (pmd_t *)last;
#ifdef DEBUG
printk("kernel_ptr_init: %p\n", last_pmd_table);
#endif
}
last_pmd_table += PTRS_PER_PMD;
if (PAGE_ALIGNED(last_pmd_table)) {
last_pmd_table = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE);
if (!last_pmd_table)
panic("%s: Failed to allocate %lu bytes align=%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
clear_page(last_pmd_table);
mmu_page_ctor(last_pmd_table);
}
return last_pmd_table;
}
static void __init map_node(int node)
{
unsigned long physaddr, virtaddr, size;
pgd_t *pgd_dir;
p4d_t *p4d_dir;
pud_t *pud_dir;
pmd_t *pmd_dir;
pte_t *pte_dir;
size = m68k_memory[node].size;
physaddr = m68k_memory[node].addr;
virtaddr = (unsigned long)phys_to_virt(physaddr);
physaddr |= m68k_supervisor_cachemode |
_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY;
if (CPU_IS_040_OR_060)
physaddr |= _PAGE_GLOBAL040;
while (size > 0) {
#ifdef DEBUG
if (!(virtaddr & (PMD_SIZE-1)))
printk ("\npa=%#lx va=%#lx ", physaddr & PAGE_MASK,
virtaddr);
#endif
pgd_dir = pgd_offset_k(virtaddr);
if (virtaddr && CPU_IS_020_OR_030) {
if (!(virtaddr & (PGDIR_SIZE-1)) &&
size >= PGDIR_SIZE) {
#ifdef DEBUG
printk ("[very early term]");
#endif
pgd_val(*pgd_dir) = physaddr;
size -= PGDIR_SIZE;
virtaddr += PGDIR_SIZE;
physaddr += PGDIR_SIZE;
continue;
}
}
p4d_dir = p4d_offset(pgd_dir, virtaddr);
pud_dir = pud_offset(p4d_dir, virtaddr);
if (!pud_present(*pud_dir)) {
pmd_dir = kernel_ptr_table();
#ifdef DEBUG
printk ("[new pointer %p]", pmd_dir);
#endif
pud_set(pud_dir, pmd_dir);
} else
pmd_dir = pmd_offset(pud_dir, virtaddr);
if (CPU_IS_020_OR_030) {
if (virtaddr) {
#ifdef DEBUG
printk ("[early term]");
#endif
pmd_val(*pmd_dir) = physaddr;
physaddr += PMD_SIZE;
} else {
int i;
#ifdef DEBUG
printk ("[zero map]");
#endif
pte_dir = kernel_page_table();
pmd_set(pmd_dir, pte_dir);
pte_val(*pte_dir++) = 0;
physaddr += PAGE_SIZE;
for (i = 1; i < PTRS_PER_PTE; physaddr += PAGE_SIZE, i++)
pte_val(*pte_dir++) = physaddr;
}
size -= PMD_SIZE;
virtaddr += PMD_SIZE;
} else {
if (!pmd_present(*pmd_dir)) {
#ifdef DEBUG
printk ("[new table]");
#endif
pte_dir = kernel_page_table();
pmd_set(pmd_dir, pte_dir);
}
pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
if (virtaddr) {
if (!pte_present(*pte_dir))
pte_val(*pte_dir) = physaddr;
} else
pte_val(*pte_dir) = 0;
size -= PAGE_SIZE;
virtaddr += PAGE_SIZE;
physaddr += PAGE_SIZE;
}
}
#ifdef DEBUG
printk("\n");
#endif
}
/*
* Alternate definitions that are compile time constants, for
* initializing protection_map. The cachebits are fixed later.
*/
#define PAGE_NONE_C __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
#define PAGE_SHARED_C __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
#define PAGE_COPY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
#define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
static pgprot_t protection_map[16] __ro_after_init = {
[VM_NONE] = PAGE_NONE_C,
[VM_READ] = PAGE_READONLY_C,
[VM_WRITE] = PAGE_COPY_C,
[VM_WRITE | VM_READ] = PAGE_COPY_C,
[VM_EXEC] = PAGE_READONLY_C,
[VM_EXEC | VM_READ] = PAGE_READONLY_C,
[VM_EXEC | VM_WRITE] = PAGE_COPY_C,
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_C,
[VM_SHARED] = PAGE_NONE_C,
[VM_SHARED | VM_READ] = PAGE_READONLY_C,
[VM_SHARED | VM_WRITE] = PAGE_SHARED_C,
[VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED_C,
[VM_SHARED | VM_EXEC] = PAGE_READONLY_C,
[VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_C,
[VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_C,
[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_C
};
DECLARE_VM_GET_PAGE_PROT
/*
* paging_init() continues the virtual memory environment setup which
* was begun by the code in arch/head.S.
*/
void __init paging_init(void)
{
unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0, };
unsigned long min_addr, max_addr;
unsigned long addr;
int i;
#ifdef DEBUG
printk ("start of paging_init (%p, %lx)\n", kernel_pg_dir, availmem);
#endif
/* Fix the cache mode in the page descriptors for the 680[46]0. */
if (CPU_IS_040_OR_060) {
int i;
#ifndef mm_cachebits
mm_cachebits = _PAGE_CACHE040;
#endif
for (i = 0; i < 16; i++)
pgprot_val(protection_map[i]) |= _PAGE_CACHE040;
}
min_addr = m68k_memory[0].addr;
max_addr = min_addr + m68k_memory[0].size - 1;
memblock_add_node(m68k_memory[0].addr, m68k_memory[0].size, 0,
MEMBLOCK_NONE);
for (i = 1; i < m68k_num_memory;) {
if (m68k_memory[i].addr < min_addr) {
printk("Ignoring memory chunk at 0x%lx:0x%lx before the first chunk\n",
m68k_memory[i].addr, m68k_memory[i].size);
printk("Fix your bootloader or use a memfile to make use of this area!\n");
m68k_num_memory--;
memmove(m68k_memory + i, m68k_memory + i + 1,
(m68k_num_memory - i) * sizeof(struct m68k_mem_info));
continue;
}
memblock_add_node(m68k_memory[i].addr, m68k_memory[i].size, i,
MEMBLOCK_NONE);
addr = m68k_memory[i].addr + m68k_memory[i].size - 1;
if (addr > max_addr)
max_addr = addr;
i++;
}
m68k_memoffset = min_addr - PAGE_OFFSET;
m68k_virt_to_node_shift = fls(max_addr - min_addr) - 6;
module_fixup(NULL, __start_fixup, __stop_fixup);
flush_icache();
high_memory = phys_to_virt(max_addr) + 1;
min_low_pfn = availmem >> PAGE_SHIFT;
max_pfn = max_low_pfn = (max_addr >> PAGE_SHIFT) + 1;
/* Reserve kernel text/data/bss and the memory allocated in head.S */
memblock_reserve(m68k_memory[0].addr, availmem - m68k_memory[0].addr);
/*
* Map the physical memory available into the kernel virtual
* address space. Make sure memblock will not try to allocate
* pages beyond the memory we already mapped in head.S
*/
memblock_set_bottom_up(true);
for (i = 0; i < m68k_num_memory; i++) {
m68k_setup_node(i);
map_node(i);
}
flush_tlb_all();
early_memtest(min_addr, max_addr);
/*
* initialize the bad page table and bad page to point
* to a couple of allocated pages
*/
empty_zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
if (!empty_zero_page)
panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
__func__, PAGE_SIZE, PAGE_SIZE);
/*
* Set up SFC/DFC registers
*/
set_fc(USER_DATA);
#ifdef DEBUG
printk ("before free_area_init\n");
#endif
for (i = 0; i < m68k_num_memory; i++)
if (node_present_pages(i))
node_set_state(i, N_NORMAL_MEMORY);
max_zone_pfn[ZONE_DMA] = memblock_end_of_DRAM();
free_area_init(max_zone_pfn);
}
| linux-master | arch/m68k/mm/motorola.c |
/*
* linux/arch/m68k/mm/sun3kmap.c
*
* Copyright (C) 2002 Sam Creasey <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <asm/page.h>
#include <asm/io.h>
#include <asm/sun3mmu.h>
#undef SUN3_KMAP_DEBUG
#ifdef SUN3_KMAP_DEBUG
extern void print_pte_vaddr(unsigned long vaddr);
#endif
extern void mmu_emu_map_pmeg (int context, int vaddr);
static inline void do_page_mapin(unsigned long phys, unsigned long virt,
unsigned long type)
{
unsigned long pte;
pte_t ptep;
ptep = pfn_pte(phys >> PAGE_SHIFT, PAGE_KERNEL);
pte = pte_val(ptep);
pte |= type;
sun3_put_pte(virt, pte);
#ifdef SUN3_KMAP_DEBUG
pr_info("mapin:");
print_pte_vaddr(virt);
#endif
}
static inline void do_pmeg_mapin(unsigned long phys, unsigned long virt,
unsigned long type, int pages)
{
if(sun3_get_segmap(virt & ~SUN3_PMEG_MASK) == SUN3_INVALID_PMEG)
mmu_emu_map_pmeg(sun3_get_context(), virt);
while(pages) {
do_page_mapin(phys, virt, type);
phys += PAGE_SIZE;
virt += PAGE_SIZE;
pages--;
}
}
void __iomem *sun3_ioremap(unsigned long phys, unsigned long size,
unsigned long type)
{
struct vm_struct *area;
unsigned long offset, virt, ret;
int pages;
if(!size)
return NULL;
/* page align */
offset = phys & (PAGE_SIZE-1);
phys &= ~(PAGE_SIZE-1);
size += offset;
size = PAGE_ALIGN(size);
if((area = get_vm_area(size, VM_IOREMAP)) == NULL)
return NULL;
#ifdef SUN3_KMAP_DEBUG
pr_info("ioremap: got virt %p size %lx(%lx)\n", area->addr, size,
area->size);
#endif
pages = size / PAGE_SIZE;
virt = (unsigned long)area->addr;
ret = virt + offset;
while(pages) {
int seg_pages;
seg_pages = (SUN3_PMEG_SIZE - (virt & SUN3_PMEG_MASK)) / PAGE_SIZE;
if(seg_pages > pages)
seg_pages = pages;
do_pmeg_mapin(phys, virt, type, seg_pages);
pages -= seg_pages;
phys += seg_pages * PAGE_SIZE;
virt += seg_pages * PAGE_SIZE;
}
return (void __iomem *)ret;
}
EXPORT_SYMBOL(sun3_ioremap);
void __iomem *__ioremap(unsigned long phys, unsigned long size, int cache)
{
return sun3_ioremap(phys, size, SUN3_PAGE_TYPE_IO);
}
EXPORT_SYMBOL(__ioremap);
void iounmap(void __iomem *addr)
{
vfree((void *)(PAGE_MASK & (unsigned long)addr));
}
EXPORT_SYMBOL(iounmap);
/* sun3_map_test(addr, val) -- Reads a byte from addr, storing to val,
* trapping the potential read fault. Returns 0 if the access faulted,
* 1 on success.
*
* This function is primarily used to check addresses on the VME bus.
*
* Mucking with the page fault handler seems a little hackish to me, but
* SunOS, NetBSD, and Mach all implemented this check in such a manner,
* so I figure we're allowed.
*/
int sun3_map_test(unsigned long addr, char *val)
{
int ret = 0;
__asm__ __volatile__
(".globl _sun3_map_test_start\n"
"_sun3_map_test_start:\n"
"1: moveb (%2), (%0)\n"
" moveq #1, %1\n"
"2:\n"
".section .fixup,\"ax\"\n"
".even\n"
"3: moveq #0, %1\n"
" jmp 2b\n"
".previous\n"
".section __ex_table,\"a\"\n"
".align 4\n"
".long 1b,3b\n"
".previous\n"
".globl _sun3_map_test_end\n"
"_sun3_map_test_end:\n"
: "=a"(val), "=r"(ret)
: "a"(addr));
return ret;
}
EXPORT_SYMBOL(sun3_map_test);
| linux-master | arch/m68k/mm/sun3kmap.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/cache.c
*
* Instruction cache handling
*
* Copyright (C) 1995 Hamish Macdonald
*/
#include <linux/module.h>
#include <asm/cacheflush.h>
#include <asm/traps.h>
static unsigned long virt_to_phys_slow(unsigned long vaddr)
{
if (CPU_IS_060) {
unsigned long paddr;
/* The PLPAR instruction causes an access error if the translation
* is not possible. To catch this we use the same exception mechanism
* as for user space accesses in <asm/uaccess.h>. */
asm volatile (".chip 68060\n"
"1: plpar (%0)\n"
".chip 68k\n"
"2:\n"
".section .fixup,\"ax\"\n"
" .even\n"
"3: sub.l %0,%0\n"
" jra 2b\n"
".previous\n"
".section __ex_table,\"a\"\n"
" .align 4\n"
" .long 1b,3b\n"
".previous"
: "=a" (paddr)
: "0" (vaddr));
return paddr;
} else if (CPU_IS_040) {
unsigned long mmusr;
asm volatile (".chip 68040\n\t"
"ptestr (%1)\n\t"
"movec %%mmusr, %0\n\t"
".chip 68k"
: "=r" (mmusr)
: "a" (vaddr));
if (mmusr & MMU_R_040)
return (mmusr & PAGE_MASK) | (vaddr & ~PAGE_MASK);
} else {
WARN_ON_ONCE(!CPU_IS_040_OR_060);
}
return 0;
}
/* Push n pages at kernel virtual address and clear the icache */
/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
void flush_icache_user_range(unsigned long address, unsigned long endaddr)
{
if (CPU_IS_COLDFIRE) {
unsigned long start, end;
start = address & ICACHE_SET_MASK;
end = endaddr & ICACHE_SET_MASK;
if (start > end) {
flush_cf_icache(0, end);
end = ICACHE_MAX_ADDR;
}
flush_cf_icache(start, end);
} else if (CPU_IS_040_OR_060) {
address &= PAGE_MASK;
do {
asm volatile ("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (virt_to_phys_slow(address)));
address += PAGE_SIZE;
} while (address < endaddr);
} else {
unsigned long tmp;
asm volatile ("movec %%cacr,%0\n\t"
"orw %1,%0\n\t"
"movec %0,%%cacr"
: "=&d" (tmp)
: "di" (FLUSH_I));
}
}
void flush_icache_range(unsigned long address, unsigned long endaddr)
{
set_fc(SUPER_DATA);
flush_icache_user_range(address, endaddr);
set_fc(USER_DATA);
}
EXPORT_SYMBOL(flush_icache_range);
void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len)
{
if (CPU_IS_COLDFIRE) {
unsigned long start, end;
start = addr & ICACHE_SET_MASK;
end = (addr + len) & ICACHE_SET_MASK;
if (start > end) {
flush_cf_icache(0, end);
end = ICACHE_MAX_ADDR;
}
flush_cf_icache(start, end);
} else if (CPU_IS_040_OR_060) {
asm volatile ("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
: : "a" (page_to_phys(page)));
} else {
unsigned long tmp;
asm volatile ("movec %%cacr,%0\n\t"
"orw %1,%0\n\t"
"movec %0,%%cacr"
: "=&d" (tmp)
: "di" (FLUSH_I));
}
}
| linux-master | arch/m68k/mm/cache.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/mm/fault.c
*
* Copyright (C) 1995 Hamish Macdonald
*/
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/uaccess.h>
#include <linux/perf_event.h>
#include <asm/setup.h>
#include <asm/traps.h>
extern void die_if_kernel(char *, struct pt_regs *, long);
int send_fault_sig(struct pt_regs *regs)
{
int signo, si_code;
void __user *addr;
signo = current->thread.signo;
si_code = current->thread.code;
addr = (void __user *)current->thread.faddr;
pr_debug("send_fault_sig: %p,%d,%d\n", addr, signo, si_code);
if (user_mode(regs)) {
force_sig_fault(signo, si_code, addr);
} else {
if (fixup_exception(regs))
return -1;
//if (signo == SIGBUS)
// force_sig_fault(si_signo, si_code, addr);
/*
* Oops. The kernel tried to access some bad page. We'll have to
* terminate things with extreme prejudice.
*/
if ((unsigned long)addr < PAGE_SIZE)
pr_alert("Unable to handle kernel NULL pointer dereference");
else
pr_alert("Unable to handle kernel access");
pr_cont(" at virtual address %p\n", addr);
die_if_kernel("Oops", regs, 0 /*error_code*/);
make_task_dead(SIGKILL);
}
return 1;
}
/*
* This routine handles page faults. It determines the problem, and
* then passes it off to one of the appropriate routines.
*
* error_code:
* bit 0 == 0 means no page found, 1 means protection fault
* bit 1 == 0 means read, 1 means write
*
* If this routine detects a bad access, it returns 1, otherwise it
* returns 0.
*/
int do_page_fault(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
struct mm_struct *mm = current->mm;
struct vm_area_struct * vma;
vm_fault_t fault;
unsigned int flags = FAULT_FLAG_DEFAULT;
pr_debug("do page fault:\nregs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld, %p\n",
regs->sr, regs->pc, address, error_code, mm ? mm->pgd : NULL);
/*
* If we're in an interrupt or have no user
* context, we must not take the fault..
*/
if (faulthandler_disabled() || !mm)
goto no_context;
if (user_mode(regs))
flags |= FAULT_FLAG_USER;
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
retry:
mmap_read_lock(mm);
vma = find_vma(mm, address);
if (!vma)
goto map_err;
if (vma->vm_start <= address)
goto good_area;
if (!(vma->vm_flags & VM_GROWSDOWN))
goto map_err;
if (user_mode(regs)) {
/* Accessing the stack below usp is always a bug. The
"+ 256" is there due to some instructions doing
pre-decrement on the stack and that doesn't show up
until later. */
if (address + 256 < rdusp())
goto map_err;
}
vma = expand_stack(mm, address);
if (!vma)
goto map_err_nosemaphore;
/*
* Ok, we have a good vm_area for this memory access, so
* we can handle it..
*/
good_area:
pr_debug("do_page_fault: good_area\n");
switch (error_code & 3) {
default: /* 3: write, present */
fallthrough;
case 2: /* write, not present */
if (!(vma->vm_flags & VM_WRITE))
goto acc_err;
flags |= FAULT_FLAG_WRITE;
break;
case 1: /* read, present */
goto acc_err;
case 0: /* read, not present */
if (unlikely(!vma_is_accessible(vma)))
goto acc_err;
}
/*
* If for any reason at all we couldn't handle the fault,
* make sure we exit gracefully rather than endlessly redo
* the fault.
*/
fault = handle_mm_fault(vma, address, flags, regs);
pr_debug("handle_mm_fault returns %x\n", fault);
if (fault_signal_pending(fault, regs)) {
if (!user_mode(regs))
goto no_context;
return 0;
}
/* The fault is fully completed (including releasing mmap lock) */
if (fault & VM_FAULT_COMPLETED)
return 0;
if (unlikely(fault & VM_FAULT_ERROR)) {
if (fault & VM_FAULT_OOM)
goto out_of_memory;
else if (fault & VM_FAULT_SIGSEGV)
goto map_err;
else if (fault & VM_FAULT_SIGBUS)
goto bus_err;
BUG();
}
if (fault & VM_FAULT_RETRY) {
flags |= FAULT_FLAG_TRIED;
/*
* No need to mmap_read_unlock(mm) as we would
* have already released it in __lock_page_or_retry
* in mm/filemap.c.
*/
goto retry;
}
mmap_read_unlock(mm);
return 0;
/*
* We ran out of memory, or some other thing happened to us that made
* us unable to handle the page fault gracefully.
*/
out_of_memory:
mmap_read_unlock(mm);
if (!user_mode(regs))
goto no_context;
pagefault_out_of_memory();
return 0;
no_context:
current->thread.signo = SIGBUS;
current->thread.faddr = address;
return send_fault_sig(regs);
bus_err:
current->thread.signo = SIGBUS;
current->thread.code = BUS_ADRERR;
current->thread.faddr = address;
goto send_sig;
map_err:
mmap_read_unlock(mm);
map_err_nosemaphore:
current->thread.signo = SIGSEGV;
current->thread.code = SEGV_MAPERR;
current->thread.faddr = address;
return send_fault_sig(regs);
acc_err:
current->thread.signo = SIGSEGV;
current->thread.code = SEGV_ACCERR;
current->thread.faddr = address;
send_sig:
mmap_read_unlock(mm);
return send_fault_sig(regs);
}
| linux-master | arch/m68k/mm/fault.c |
// SPDX-License-Identifier: GPL-2.0
/* Tests for presence or absence of hardware registers.
* This code was originally in atari/config.c, but I noticed
* that it was also in drivers/nubus/nubus.c and I wanted to
* use it in hp300/config.c, so it seemed sensible to pull it
* out into its own file.
*
* The test is for use when trying to read a hardware register
* that isn't present would cause a bus error. We set up a
* temporary handler so that this doesn't kill the kernel.
*
* There is a test-by-reading and a test-by-writing; I present
* them here complete with the comments from the original atari
* config.c...
* -- PMM <[email protected]>, 05/1998
*/
/* This function tests for the presence of an address, specially a
* hardware register address. It is called very early in the kernel
* initialization process, when the VBR register isn't set up yet. On
* an Atari, it still points to address 0, which is unmapped. So a bus
* error would cause another bus error while fetching the exception
* vector, and the CPU would do nothing at all. So we needed to set up
* a temporary VBR and a vector table for the duration of the test.
*/
#include <linux/module.h>
int hwreg_present(volatile void *regp)
{
int ret = 0;
unsigned long flags;
long save_sp, save_vbr;
long tmp_vectors[3];
local_irq_save(flags);
__asm__ __volatile__ (
"movec %/vbr,%2\n\t"
"movel #Lberr1,%4@(8)\n\t"
"movec %4,%/vbr\n\t"
"movel %/sp,%1\n\t"
"moveq #0,%0\n\t"
"tstb %3@\n\t"
"nop\n\t"
"moveq #1,%0\n"
"Lberr1:\n\t"
"movel %1,%/sp\n\t"
"movec %2,%/vbr"
: "=&d" (ret), "=&r" (save_sp), "=&r" (save_vbr)
: "a" (regp), "a" (tmp_vectors)
);
local_irq_restore(flags);
return ret;
}
EXPORT_SYMBOL(hwreg_present);
/* Basically the same, but writes a value into a word register, protected
* by a bus error handler. Returns 1 if successful, 0 otherwise.
*/
int hwreg_write(volatile void *regp, unsigned short val)
{
int ret;
unsigned long flags;
long save_sp, save_vbr;
long tmp_vectors[3];
local_irq_save(flags);
__asm__ __volatile__ (
"movec %/vbr,%2\n\t"
"movel #Lberr2,%4@(8)\n\t"
"movec %4,%/vbr\n\t"
"movel %/sp,%1\n\t"
"moveq #0,%0\n\t"
"movew %5,%3@\n\t"
"nop\n\t"
/*
* If this nop isn't present, 'ret' may already be loaded
* with 1 at the time the bus error happens!
*/
"moveq #1,%0\n"
"Lberr2:\n\t"
"movel %1,%/sp\n\t"
"movec %2,%/vbr"
: "=&d" (ret), "=&r" (save_sp), "=&r" (save_vbr)
: "a" (regp), "a" (tmp_vectors), "g" (val)
);
local_irq_restore(flags);
return ret;
}
EXPORT_SYMBOL(hwreg_write);
| linux-master | arch/m68k/mm/hwtest.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/hp300/time.c
*
* Copyright (C) 1998 Philip Blundell <[email protected]>
*
* This file contains the HP300-specific time handling code.
*/
#include <asm/ptrace.h>
#include <linux/clocksource.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/blinken.h>
static u64 hp300_read_clk(struct clocksource *cs);
static struct clocksource hp300_clk = {
.name = "timer",
.rating = 250,
.read = hp300_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static u32 clk_total, clk_offset;
/* Clock hardware definitions */
#define CLOCKBASE 0xf05f8000
#define CLKCR1 0x1
#define CLKCR2 0x3
#define CLKCR3 CLKCR1
#define CLKSR CLKCR2
#define CLKMSB1 0x5
#define CLKLSB1 0x7
#define CLKMSB2 0x9
#define CLKMSB3 0xD
#define CLKSR_INT1 BIT(0)
/* This is for machines which generate the exact clock. */
#define HP300_TIMER_CLOCK_FREQ 250000
#define HP300_TIMER_CYCLES (HP300_TIMER_CLOCK_FREQ / HZ)
#define INTVAL (HP300_TIMER_CYCLES - 1)
static irqreturn_t hp300_tick(int irq, void *dev_id)
{
unsigned long flags;
unsigned long tmp;
local_irq_save(flags);
in_8(CLOCKBASE + CLKSR);
asm volatile ("movpw %1@(5),%0" : "=d" (tmp) : "a" (CLOCKBASE));
clk_total += INTVAL;
clk_offset = 0;
legacy_timer_tick(1);
timer_heartbeat();
local_irq_restore(flags);
/* Turn off the network and SCSI leds */
blinken_leds(0, 0xe0);
return IRQ_HANDLED;
}
static u64 hp300_read_clk(struct clocksource *cs)
{
unsigned long flags;
unsigned char lsb, msb, msb_new;
u32 ticks;
local_irq_save(flags);
/* Read current timer 1 value */
msb = in_8(CLOCKBASE + CLKMSB1);
again:
if ((in_8(CLOCKBASE + CLKSR) & CLKSR_INT1) && msb > 0)
clk_offset = INTVAL;
lsb = in_8(CLOCKBASE + CLKLSB1);
msb_new = in_8(CLOCKBASE + CLKMSB1);
if (msb_new != msb) {
msb = msb_new;
goto again;
}
ticks = INTVAL - ((msb << 8) | lsb);
ticks += clk_offset + clk_total;
local_irq_restore(flags);
return ticks;
}
void __init hp300_sched_init(void)
{
out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */
out_8(CLOCKBASE + CLKCR1, 0x1); /* reset */
asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE));
if (request_irq(IRQ_AUTO_6, hp300_tick, IRQF_TIMER, "timer tick", NULL))
pr_err("Couldn't register timer interrupt\n");
out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */
out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */
clocksource_register_hz(&hp300_clk, HP300_TIMER_CLOCK_FREQ);
}
| linux-master | arch/m68k/hp300/time.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/hp300/config.c
*
* Copyright (C) 1998 Philip Blundell <[email protected]>
*
* This file contains the HP300-specific initialisation code. It gets
* called by setup.c.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/rtc.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-hp300.h>
#include <asm/byteorder.h>
#include <asm/machdep.h>
#include <asm/blinken.h>
#include <asm/io.h> /* readb() and writeb() */
#include <asm/hp300hw.h>
#include <asm/config.h>
#include "time.h"
unsigned long hp300_model;
unsigned long hp300_uart_scode = -1;
unsigned char hp300_ledstate;
EXPORT_SYMBOL(hp300_ledstate);
static char s_hp330[] __initdata = "330";
static char s_hp340[] __initdata = "340";
static char s_hp345[] __initdata = "345";
static char s_hp360[] __initdata = "360";
static char s_hp370[] __initdata = "370";
static char s_hp375[] __initdata = "375";
static char s_hp380[] __initdata = "380";
static char s_hp385[] __initdata = "385";
static char s_hp400[] __initdata = "400";
static char s_hp425t[] __initdata = "425t";
static char s_hp425s[] __initdata = "425s";
static char s_hp425e[] __initdata = "425e";
static char s_hp433t[] __initdata = "433t";
static char s_hp433s[] __initdata = "433s";
static char *hp300_models[] __initdata = {
[HP_320] = NULL,
[HP_330] = s_hp330,
[HP_340] = s_hp340,
[HP_345] = s_hp345,
[HP_350] = NULL,
[HP_360] = s_hp360,
[HP_370] = s_hp370,
[HP_375] = s_hp375,
[HP_380] = s_hp380,
[HP_385] = s_hp385,
[HP_400] = s_hp400,
[HP_425T] = s_hp425t,
[HP_425S] = s_hp425s,
[HP_425E] = s_hp425e,
[HP_433T] = s_hp433t,
[HP_433S] = s_hp433s,
};
static char hp300_model_name[13] = "HP9000/";
extern void hp300_reset(void);
#ifdef CONFIG_SERIAL_8250_CONSOLE
extern int hp300_setup_serial_console(void) __init;
#endif
int __init hp300_parse_bootinfo(const struct bi_record *record)
{
int unknown = 0;
const void *data = record->data;
switch (be16_to_cpu(record->tag)) {
case BI_HP300_MODEL:
hp300_model = be32_to_cpup(data);
break;
case BI_HP300_UART_SCODE:
hp300_uart_scode = be32_to_cpup(data);
break;
case BI_HP300_UART_ADDR:
/* serial port address: ignored here */
break;
default:
unknown = 1;
}
return unknown;
}
#ifdef CONFIG_HEARTBEAT
static void hp300_pulse(int x)
{
if (x)
blinken_leds(0x10, 0);
else
blinken_leds(0, 0x10);
}
#endif
static void hp300_get_model(char *model)
{
strcpy(model, hp300_model_name);
}
#define RTCBASE 0xf0420000
#define RTC_DATA 0x1
#define RTC_CMD 0x3
#define RTC_BUSY 0x02
#define RTC_DATA_RDY 0x01
#define rtc_busy() (in_8(RTCBASE + RTC_CMD) & RTC_BUSY)
#define rtc_data_available() (in_8(RTCBASE + RTC_CMD) & RTC_DATA_RDY)
#define rtc_status() (in_8(RTCBASE + RTC_CMD))
#define rtc_command(x) out_8(RTCBASE + RTC_CMD, (x))
#define rtc_read_data() (in_8(RTCBASE + RTC_DATA))
#define rtc_write_data(x) out_8(RTCBASE + RTC_DATA, (x))
#define RTC_SETREG 0xe0
#define RTC_WRITEREG 0xc2
#define RTC_READREG 0xc3
#define RTC_REG_SEC2 0
#define RTC_REG_SEC1 1
#define RTC_REG_MIN2 2
#define RTC_REG_MIN1 3
#define RTC_REG_HOUR2 4
#define RTC_REG_HOUR1 5
#define RTC_REG_WDAY 6
#define RTC_REG_DAY2 7
#define RTC_REG_DAY1 8
#define RTC_REG_MON2 9
#define RTC_REG_MON1 10
#define RTC_REG_YEAR2 11
#define RTC_REG_YEAR1 12
#define RTC_HOUR1_24HMODE 0x8
#define RTC_STAT_MASK 0xf0
#define RTC_STAT_RDY 0x40
static inline unsigned char hp300_rtc_read(unsigned char reg)
{
unsigned char s, ret;
unsigned long flags;
local_irq_save(flags);
while (rtc_busy());
rtc_command(RTC_SETREG);
while (rtc_busy());
rtc_write_data(reg);
while (rtc_busy());
rtc_command(RTC_READREG);
do {
while (!rtc_data_available());
s = rtc_status();
ret = rtc_read_data();
} while ((s & RTC_STAT_MASK) != RTC_STAT_RDY);
local_irq_restore(flags);
return ret;
}
static inline unsigned char hp300_rtc_write(unsigned char reg,
unsigned char val)
{
unsigned char s, ret;
unsigned long flags;
local_irq_save(flags);
while (rtc_busy());
rtc_command(RTC_SETREG);
while (rtc_busy());
rtc_write_data((val << 4) | reg);
while (rtc_busy());
rtc_command(RTC_WRITEREG);
while (rtc_busy());
rtc_command(RTC_READREG);
do {
while (!rtc_data_available());
s = rtc_status();
ret = rtc_read_data();
} while ((s & RTC_STAT_MASK) != RTC_STAT_RDY);
local_irq_restore(flags);
return ret;
}
static int hp300_hwclk(int op, struct rtc_time *t)
{
if (!op) { /* read */
t->tm_sec = hp300_rtc_read(RTC_REG_SEC1) * 10 +
hp300_rtc_read(RTC_REG_SEC2);
t->tm_min = hp300_rtc_read(RTC_REG_MIN1) * 10 +
hp300_rtc_read(RTC_REG_MIN2);
t->tm_hour = (hp300_rtc_read(RTC_REG_HOUR1) & 3) * 10 +
hp300_rtc_read(RTC_REG_HOUR2);
t->tm_wday = -1;
t->tm_mday = hp300_rtc_read(RTC_REG_DAY1) * 10 +
hp300_rtc_read(RTC_REG_DAY2);
t->tm_mon = hp300_rtc_read(RTC_REG_MON1) * 10 +
hp300_rtc_read(RTC_REG_MON2) - 1;
t->tm_year = hp300_rtc_read(RTC_REG_YEAR1) * 10 +
hp300_rtc_read(RTC_REG_YEAR2);
if (t->tm_year <= 69)
t->tm_year += 100;
} else {
hp300_rtc_write(RTC_REG_SEC1, t->tm_sec / 10);
hp300_rtc_write(RTC_REG_SEC2, t->tm_sec % 10);
hp300_rtc_write(RTC_REG_MIN1, t->tm_min / 10);
hp300_rtc_write(RTC_REG_MIN2, t->tm_min % 10);
hp300_rtc_write(RTC_REG_HOUR1,
((t->tm_hour / 10) & 3) | RTC_HOUR1_24HMODE);
hp300_rtc_write(RTC_REG_HOUR2, t->tm_hour % 10);
hp300_rtc_write(RTC_REG_DAY1, t->tm_mday / 10);
hp300_rtc_write(RTC_REG_DAY2, t->tm_mday % 10);
hp300_rtc_write(RTC_REG_MON1, (t->tm_mon + 1) / 10);
hp300_rtc_write(RTC_REG_MON2, (t->tm_mon + 1) % 10);
if (t->tm_year >= 100)
t->tm_year -= 100;
hp300_rtc_write(RTC_REG_YEAR1, t->tm_year / 10);
hp300_rtc_write(RTC_REG_YEAR2, t->tm_year % 10);
}
return 0;
}
static void __init hp300_init_IRQ(void)
{
}
void __init config_hp300(void)
{
mach_sched_init = hp300_sched_init;
mach_init_IRQ = hp300_init_IRQ;
mach_get_model = hp300_get_model;
mach_hwclk = hp300_hwclk;
mach_reset = hp300_reset;
#ifdef CONFIG_HEARTBEAT
mach_heartbeat = hp300_pulse;
#endif
if (hp300_model >= HP_330 && hp300_model <= HP_433S &&
hp300_model != HP_350) {
pr_info("Detected HP9000 model %s\n",
hp300_models[hp300_model-HP_320]);
strcat(hp300_model_name, hp300_models[hp300_model-HP_320]);
} else {
panic("Unknown HP9000 Model");
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
hp300_setup_serial_console();
#endif
}
| linux-master | arch/m68k/hp300/config.c |
/*
* arch/m68k/mvme147/config.c
*
* Copyright (C) 1996 Dave Frascone [[email protected]]
* Cloned from Richard Hirst [[email protected]]
*
* Based on:
*
* Copyright (C) 1993 Hamish Macdonald
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file README.legal in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/clocksource.h>
#include <linux/console.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/major.h>
#include <linux/rtc.h>
#include <linux/interrupt.h>
#include <asm/bootinfo.h>
#include <asm/bootinfo-vme.h>
#include <asm/byteorder.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/mvme147hw.h>
#include <asm/config.h>
static void mvme147_get_model(char *model);
extern void mvme147_sched_init(void);
extern int mvme147_hwclk (int, struct rtc_time *);
extern void mvme147_reset (void);
static int bcd2int (unsigned char b);
int __init mvme147_parse_bootinfo(const struct bi_record *bi)
{
uint16_t tag = be16_to_cpu(bi->tag);
if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO)
return 0;
else
return 1;
}
void mvme147_reset(void)
{
pr_info("\r\n\nCalled mvme147_reset\r\n");
m147_pcc->watchdog = 0x0a; /* Clear timer */
m147_pcc->watchdog = 0xa5; /* Enable watchdog - 100ms to reset */
while (1)
;
}
static void mvme147_get_model(char *model)
{
sprintf(model, "Motorola MVME147");
}
/*
* This function is called during kernel startup to initialize
* the mvme147 IRQ handling routines.
*/
void __init mvme147_init_IRQ(void)
{
m68k_setup_user_interrupt(VEC_USER, 192);
}
void __init config_mvme147(void)
{
mach_sched_init = mvme147_sched_init;
mach_init_IRQ = mvme147_init_IRQ;
mach_hwclk = mvme147_hwclk;
mach_reset = mvme147_reset;
mach_get_model = mvme147_get_model;
/* Board type is only set by newer versions of vmelilo/tftplilo */
if (!vme_brdtype)
vme_brdtype = VME_TYPE_MVME147;
}
static u64 mvme147_read_clk(struct clocksource *cs);
static struct clocksource mvme147_clk = {
.name = "pcc",
.rating = 250,
.read = mvme147_read_clk,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static u32 clk_total;
#define PCC_TIMER_CLOCK_FREQ 160000
#define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ)
#define PCC_TIMER_PRELOAD (0x10000 - PCC_TIMER_CYCLES)
/* Using pcc tick timer 1 */
static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
{
unsigned long flags;
local_irq_save(flags);
m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
PCC_TIMER_TIC_EN;
m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
PCC_LEVEL_TIMER1;
clk_total += PCC_TIMER_CYCLES;
legacy_timer_tick(1);
local_irq_restore(flags);
return IRQ_HANDLED;
}
void mvme147_sched_init (void)
{
if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQF_TIMER,
"timer 1", NULL))
pr_err("Couldn't register timer interrupt\n");
/* Init the clock with a value */
/* The clock counter increments until 0xFFFF then reloads */
m147_pcc->t1_preload = PCC_TIMER_PRELOAD;
m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
PCC_TIMER_TIC_EN;
m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
PCC_LEVEL_TIMER1;
clocksource_register_hz(&mvme147_clk, PCC_TIMER_CLOCK_FREQ);
}
static u64 mvme147_read_clk(struct clocksource *cs)
{
unsigned long flags;
u8 overflow, tmp;
u16 count;
u32 ticks;
local_irq_save(flags);
tmp = m147_pcc->t1_cntrl >> 4;
count = m147_pcc->t1_count;
overflow = m147_pcc->t1_cntrl >> 4;
if (overflow != tmp)
count = m147_pcc->t1_count;
count -= PCC_TIMER_PRELOAD;
ticks = count + overflow * PCC_TIMER_CYCLES;
ticks += clk_total;
local_irq_restore(flags);
return ticks;
}
static int bcd2int (unsigned char b)
{
return ((b>>4)*10 + (b&15));
}
int mvme147_hwclk(int op, struct rtc_time *t)
{
if (!op) {
m147_rtc->ctrl = RTC_READ;
t->tm_year = bcd2int (m147_rtc->bcd_year);
t->tm_mon = bcd2int(m147_rtc->bcd_mth) - 1;
t->tm_mday = bcd2int (m147_rtc->bcd_dom);
t->tm_hour = bcd2int (m147_rtc->bcd_hr);
t->tm_min = bcd2int (m147_rtc->bcd_min);
t->tm_sec = bcd2int (m147_rtc->bcd_sec);
m147_rtc->ctrl = 0;
if (t->tm_year < 70)
t->tm_year += 100;
} else {
/* FIXME Setting the time is not yet supported */
return -EOPNOTSUPP;
}
return 0;
}
| linux-master | arch/m68k/mvme147/config.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/sun3x/time.c
*
* Sun3x-specific time handling
*/
#include <linux/types.h>
#include <linux/kd.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/traps.h>
#include <asm/sun3x.h>
#include <asm/sun3ints.h>
#include "time.h"
#define M_CONTROL 0xf8
#define M_SEC 0xf9
#define M_MIN 0xfa
#define M_HOUR 0xfb
#define M_DAY 0xfc
#define M_DATE 0xfd
#define M_MONTH 0xfe
#define M_YEAR 0xff
#define C_WRITE 0x80
#define C_READ 0x40
#define C_SIGN 0x20
#define C_CALIB 0x1f
int sun3x_hwclk(int set, struct rtc_time *t)
{
volatile struct mostek_dt *h =
(struct mostek_dt *)(SUN3X_EEPROM+M_CONTROL);
unsigned long flags;
local_irq_save(flags);
if(set) {
h->csr |= C_WRITE;
h->sec = bin2bcd(t->tm_sec);
h->min = bin2bcd(t->tm_min);
h->hour = bin2bcd(t->tm_hour);
h->wday = bin2bcd(t->tm_wday);
h->mday = bin2bcd(t->tm_mday);
h->month = bin2bcd(t->tm_mon + 1);
h->year = bin2bcd(t->tm_year % 100);
h->csr &= ~C_WRITE;
} else {
h->csr |= C_READ;
t->tm_sec = bcd2bin(h->sec);
t->tm_min = bcd2bin(h->min);
t->tm_hour = bcd2bin(h->hour);
t->tm_wday = bcd2bin(h->wday);
t->tm_mday = bcd2bin(h->mday);
t->tm_mon = bcd2bin(h->month) - 1;
t->tm_year = bcd2bin(h->year);
h->csr &= ~C_READ;
if (t->tm_year < 70)
t->tm_year += 100;
}
local_irq_restore(flags);
return 0;
}
#if 0
static irqreturn_t sun3x_timer_tick(int irq, void *dev_id)
{
unsigned long flags;
local_irq_save(flags);
/* Clear the pending interrupt - pulse the enable line low */
disable_irq(5);
enable_irq(5);
legacy_timer_tick(1);
local_irq_restore(flags);
return IRQ_HANDLED;
}
#endif
void __init sun3x_sched_init(void)
{
sun3_disable_interrupts();
/* Pulse enable low to get the clock started */
sun3_disable_irq(5);
sun3_enable_irq(5);
sun3_enable_interrupts();
}
| linux-master | arch/m68k/sun3x/time.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Setup kernel for a Sun3x machine
*
* (C) 1999 Thomas Bogendoerfer ([email protected])
*
* based on code from Oliver Jowett <[email protected]>
*/
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/seq_file.h>
#include <linux/console.h>
#include <linux/init.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/sun3xprom.h>
#include <asm/sun3ints.h>
#include <asm/setup.h>
#include <asm/oplib.h>
#include "time.h"
volatile char *clock_va;
extern void sun3_get_model(char *model);
void sun3_leds(unsigned int i)
{
}
static void sun3x_get_hardware_list(struct seq_file *m)
{
seq_printf(m, "PROM Revision:\t%s\n", romvec->pv_monid);
}
/*
* Setup the sun3x configuration info
*/
void __init config_sun3x(void)
{
sun3x_prom_init();
mach_sched_init = sun3x_sched_init;
mach_init_IRQ = sun3_init_IRQ;
mach_reset = sun3x_reboot;
mach_hwclk = sun3x_hwclk;
mach_get_model = sun3_get_model;
mach_get_hardware_list = sun3x_get_hardware_list;
sun3_intreg = (unsigned char *)SUN3X_INTREG;
/* only the serial console is known to work anyway... */
#if 0
switch (*(unsigned char *)SUN3X_EEPROM_CONS) {
case 0x10:
serial_console = 1;
conswitchp = NULL;
break;
case 0x11:
serial_console = 2;
conswitchp = NULL;
break;
default:
serial_console = 0;
break;
}
#endif
}
| linux-master | arch/m68k/sun3x/config.c |
// SPDX-License-Identifier: GPL-2.0
/* Prom access routines for the sun3x */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/tty.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/traps.h>
#include <asm/sun3xprom.h>
#include <asm/idprom.h>
#include <asm/sun3ints.h>
#include <asm/openprom.h>
#include <asm/machines.h>
void (*sun3x_putchar)(int);
int (*sun3x_getchar)(void);
int (*sun3x_mayget)(void);
int (*sun3x_mayput)(int);
void (*sun3x_prom_reboot)(void);
e_vector sun3x_prom_abort;
struct linux_romvec *romvec;
/* prom vector table */
e_vector *sun3x_prom_vbr;
/* Handle returning to the prom */
void sun3x_halt(void)
{
unsigned long flags;
/* Disable interrupts while we mess with things */
local_irq_save(flags);
/* Restore prom vbr */
asm volatile ("movec %0,%%vbr" : : "r" ((void*)sun3x_prom_vbr));
/* Restore prom NMI clock */
// sun3x_disable_intreg(5);
sun3_enable_irq(7);
/* Let 'er rip */
asm volatile ("trap #14");
/* Restore everything */
sun3_disable_irq(7);
sun3_enable_irq(5);
asm volatile ("movec %0,%%vbr" : : "r" ((void*)vectors));
local_irq_restore(flags);
}
void sun3x_reboot(void)
{
/* This never returns, don't bother saving things */
local_irq_disable();
/* Restore prom vbr */
asm volatile ("movec %0,%%vbr" : : "r" ((void*)sun3x_prom_vbr));
/* Restore prom NMI clock */
sun3_disable_irq(5);
sun3_enable_irq(7);
/* Let 'er rip */
(*romvec->pv_reboot)("vmlinux");
}
static void sun3x_prom_write(struct console *co, const char *s,
unsigned int count)
{
while (count--) {
if (*s == '\n')
sun3x_putchar('\r');
sun3x_putchar(*s++);
}
}
/* debug console - write-only */
static struct console sun3x_debug = {
.name = "debug",
.write = sun3x_prom_write,
.flags = CON_PRINTBUFFER,
.index = -1,
};
void __init sun3x_prom_init(void)
{
/* Read the vector table */
sun3x_putchar = *(void (**)(int)) (SUN3X_P_PUTCHAR);
sun3x_getchar = *(int (**)(void)) (SUN3X_P_GETCHAR);
sun3x_mayget = *(int (**)(void)) (SUN3X_P_MAYGET);
sun3x_mayput = *(int (**)(int)) (SUN3X_P_MAYPUT);
sun3x_prom_reboot = *(void (**)(void)) (SUN3X_P_REBOOT);
sun3x_prom_abort = *(e_vector *) (SUN3X_P_ABORT);
romvec = (struct linux_romvec *)SUN3X_PROM_BASE;
idprom_init();
if (!((idprom->id_machtype & SM_ARCH_MASK) == SM_SUN3X)) {
pr_warn("Machine reports strange type %02x\n",
idprom->id_machtype);
pr_warn("Pretending it's a 3/80, but very afraid...\n");
idprom->id_machtype = SM_SUN3X | SM_3_80;
}
/* point trap #14 at abort.
* XXX this is futile since we restore the vbr first - oops
*/
vectors[VEC_TRAP14] = sun3x_prom_abort;
}
static int __init sun3x_debug_setup(char *arg)
{
/* If debug=prom was specified, start the debug console */
if (MACH_IS_SUN3X && !strcmp(arg, "prom"))
register_console(&sun3x_debug);
return 0;
}
early_param("debug", sun3x_debug_setup);
/* some prom functions to export */
int prom_getintdefault(int node, char *property, int deflt)
{
return deflt;
}
int prom_getbool (int node, char *prop)
{
return 1;
}
void prom_printf(char *fmt, ...)
{
}
void prom_halt (void)
{
sun3x_halt();
}
/* Get the idprom and stuff it into buffer 'idbuf'. Returns the
* format type. 'num_bytes' is the number of bytes that your idbuf
* has space for. Returns 0xff on error.
*/
unsigned char
prom_get_idprom(char *idbuf, int num_bytes)
{
int i;
/* make a copy of the idprom structure */
for (i = 0; i < num_bytes; i++)
idbuf[i] = ((char *)SUN3X_IDPROM)[i];
return idbuf[0];
}
| linux-master | arch/m68k/sun3x/prom.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Virtual DMA allocation
*
* (C) 1999 Thomas Bogendoerfer ([email protected])
*
* 11/26/2000 -- disabled the existing code because it didn't work for
* me in 2.4. Replaced with a significantly more primitive version
* similar to the sun3 code. the old functionality was probably more
* desirable, but.... -- Sam Creasey ([email protected])
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <linux/memblock.h>
#include <linux/vmalloc.h>
#include <asm/sun3x.h>
#include <asm/dvma.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/tlbflush.h>
/* IOMMU support */
#define IOMMU_ADDR_MASK 0x03ffe000
#define IOMMU_CACHE_INHIBIT 0x00000040
#define IOMMU_FULL_BLOCK 0x00000020
#define IOMMU_MODIFIED 0x00000010
#define IOMMU_USED 0x00000008
#define IOMMU_WRITE_PROTECT 0x00000004
#define IOMMU_DT_MASK 0x00000003
#define IOMMU_DT_INVALID 0x00000000
#define IOMMU_DT_VALID 0x00000001
#define IOMMU_DT_BAD 0x00000002
static volatile unsigned long *iommu_pte = (unsigned long *)SUN3X_IOMMU;
#define dvma_entry_paddr(index) (iommu_pte[index] & IOMMU_ADDR_MASK)
#define dvma_entry_vaddr(index,paddr) ((index << DVMA_PAGE_SHIFT) | \
(paddr & (DVMA_PAGE_SIZE-1)))
#if 0
#define dvma_entry_set(index,addr) (iommu_pte[index] = \
(addr & IOMMU_ADDR_MASK) | \
IOMMU_DT_VALID | IOMMU_CACHE_INHIBIT)
#else
#define dvma_entry_set(index,addr) (iommu_pte[index] = \
(addr & IOMMU_ADDR_MASK) | \
IOMMU_DT_VALID)
#endif
#define dvma_entry_clr(index) (iommu_pte[index] = IOMMU_DT_INVALID)
#define dvma_entry_hash(addr) ((addr >> DVMA_PAGE_SHIFT) ^ \
((addr & 0x03c00000) >> \
(DVMA_PAGE_SHIFT+4)))
#ifdef DEBUG
/* code to print out a dvma mapping for debugging purposes */
void dvma_print (unsigned long dvma_addr)
{
unsigned long index;
index = dvma_addr >> DVMA_PAGE_SHIFT;
pr_info("idx %lx dvma_addr %08lx paddr %08lx\n", index, dvma_addr,
dvma_entry_paddr(index));
}
#endif
/* create a virtual mapping for a page assigned within the IOMMU
so that the cpu can reach it easily */
inline int dvma_map_cpu(unsigned long kaddr,
unsigned long vaddr, int len)
{
pgd_t *pgd;
p4d_t *p4d;
pud_t *pud;
unsigned long end;
int ret = 0;
kaddr &= PAGE_MASK;
vaddr &= PAGE_MASK;
end = PAGE_ALIGN(vaddr + len);
pr_debug("dvma: mapping kern %08lx to virt %08lx\n", kaddr, vaddr);
pgd = pgd_offset_k(vaddr);
p4d = p4d_offset(pgd, vaddr);
pud = pud_offset(p4d, vaddr);
do {
pmd_t *pmd;
unsigned long end2;
if((pmd = pmd_alloc(&init_mm, pud, vaddr)) == NULL) {
ret = -ENOMEM;
goto out;
}
if((end & PGDIR_MASK) > (vaddr & PGDIR_MASK))
end2 = (vaddr + (PGDIR_SIZE-1)) & PGDIR_MASK;
else
end2 = end;
do {
pte_t *pte;
unsigned long end3;
if((pte = pte_alloc_kernel(pmd, vaddr)) == NULL) {
ret = -ENOMEM;
goto out;
}
if((end2 & PMD_MASK) > (vaddr & PMD_MASK))
end3 = (vaddr + (PMD_SIZE-1)) & PMD_MASK;
else
end3 = end2;
do {
pr_debug("mapping %08lx phys to %08lx\n",
__pa(kaddr), vaddr);
set_pte(pte, pfn_pte(virt_to_pfn((void *)kaddr),
PAGE_KERNEL));
pte++;
kaddr += PAGE_SIZE;
vaddr += PAGE_SIZE;
} while(vaddr < end3);
} while(vaddr < end2);
} while(vaddr < end);
flush_tlb_all();
out:
return ret;
}
inline int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
int len)
{
unsigned long end, index;
index = baddr >> DVMA_PAGE_SHIFT;
end = ((baddr+len) >> DVMA_PAGE_SHIFT);
if(len & ~DVMA_PAGE_MASK)
end++;
for(; index < end ; index++) {
// if(dvma_entry_use(index))
// BUG();
// pr_info("mapping pa %lx to ba %lx\n", __pa(kaddr),
// index << DVMA_PAGE_SHIFT);
dvma_entry_set(index, __pa(kaddr));
iommu_pte[index] |= IOMMU_FULL_BLOCK;
// dvma_entry_inc(index);
kaddr += DVMA_PAGE_SIZE;
}
#ifdef DEBUG
for(index = (baddr >> DVMA_PAGE_SHIFT); index < end; index++)
dvma_print(index << DVMA_PAGE_SHIFT);
#endif
return 0;
}
void dvma_unmap_iommu(unsigned long baddr, int len)
{
int index, end;
index = baddr >> DVMA_PAGE_SHIFT;
end = (DVMA_PAGE_ALIGN(baddr+len) >> DVMA_PAGE_SHIFT);
for(; index < end ; index++) {
pr_debug("freeing bus mapping %08x\n",
index << DVMA_PAGE_SHIFT);
#if 0
if(!dvma_entry_use(index))
pr_info("dvma_unmap freeing unused entry %04x\n",
index);
else
dvma_entry_dec(index);
#endif
dvma_entry_clr(index);
}
}
| linux-master | arch/m68k/sun3x/dvma.c |
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2014 Finn Thain
*/
#include <linux/kernel.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/string.h>
#include <asm/setup.h>
extern void mvme16x_cons_write(struct console *co,
const char *str, unsigned count);
asmlinkage void __init debug_cons_nputs(const char *s, unsigned n);
static void __ref debug_cons_write(struct console *c,
const char *s, unsigned n)
{
#if !(defined(CONFIG_SUN3) || defined(CONFIG_M68000) || \
defined(CONFIG_COLDFIRE))
if (MACH_IS_MVME16x)
mvme16x_cons_write(c, s, n);
else
debug_cons_nputs(s, n);
#endif
}
static struct console early_console_instance = {
.name = "debug",
.write = debug_cons_write,
.flags = CON_PRINTBUFFER | CON_BOOT,
.index = -1
};
static int __init setup_early_printk(char *buf)
{
if (early_console || buf)
return 0;
early_console = &early_console_instance;
register_console(early_console);
return 0;
}
early_param("earlyprintk", setup_early_printk);
/*
* debug_cons_nputs() defined in arch/m68k/kernel/head.S cannot be called
* after init sections are discarded (for platforms that use it).
*/
#if !(defined(CONFIG_SUN3) || defined(CONFIG_M68000) || \
defined(CONFIG_COLDFIRE))
static int __init unregister_early_console(void)
{
if (!early_console || MACH_IS_MVME16x)
return 0;
return unregister_console(early_console);
}
late_initcall(unregister_early_console);
#endif
| linux-master | arch/m68k/kernel/early_printk.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68knommu/kernel/setup.c
*
* Copyright (C) 1999-2007 Greg Ungerer ([email protected])
* Copyright (C) 1998,1999 D. Jeff Dionne <[email protected]>
* Copyleft ()) 2000 James D. Schettine {[email protected]}
* Copyright (C) 1998 Kenneth Albanowski <[email protected]>
* Copyright (C) 1995 Hamish Macdonald
* Copyright (C) 2000 Lineo Inc. (www.lineo.com)
* Copyright (C) 2001 Lineo, Inc. <www.lineo.com>
*
* 68VZ328 Fixes/support Evan Stawnyczy <[email protected]>
*/
/*
* This file handles the architecture-dependent parts of system setup
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/console.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/memblock.h>
#include <linux/seq_file.h>
#include <linux/init.h>
#include <linux/initrd.h>
#include <linux/root_dev.h>
#include <linux/rtc.h>
#include <asm/setup.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/sections.h>
unsigned long memory_start;
unsigned long memory_end;
EXPORT_SYMBOL(memory_start);
EXPORT_SYMBOL(memory_end);
char __initdata command_line[COMMAND_LINE_SIZE];
/* machine dependent timer functions */
void (*mach_sched_init)(void) __initdata = NULL;
/* machine dependent reboot functions */
void (*mach_reset)(void);
void (*mach_halt)(void);
#ifdef CONFIG_M68000
#if defined(CONFIG_M68328)
#define CPU_NAME "MC68328"
#elif defined(CONFIG_M68EZ328)
#define CPU_NAME "MC68EZ328"
#elif defined(CONFIG_M68VZ328)
#define CPU_NAME "MC68VZ328"
#else
#define CPU_NAME "MC68000"
#endif
#endif /* CONFIG_M68000 */
#ifndef CPU_NAME
#define CPU_NAME "UNKNOWN"
#endif
/*
* Different cores have different instruction execution timings.
* The old/traditional 68000 cores are basically all the same, at 16.
* The ColdFire cores vary a little, their values are defined in their
* headers. We default to the standard 68000 value here.
*/
#ifndef CPU_INSTR_PER_JIFFY
#define CPU_INSTR_PER_JIFFY 16
#endif
void __init setup_arch(char **cmdline_p)
{
memory_start = PAGE_ALIGN(_ramstart);
memory_end = _ramend;
setup_initial_init_mm(_stext, _etext, _edata, NULL);
config_BSP(&command_line[0], sizeof(command_line));
#if defined(CONFIG_BOOTPARAM)
strscpy(&command_line[0], CONFIG_BOOTPARAM_STRING, sizeof(command_line));
#endif /* CONFIG_BOOTPARAM */
process_uboot_commandline(&command_line[0], sizeof(command_line));
pr_info("uClinux with CPU " CPU_NAME "\n");
#ifdef CONFIG_UCDIMM
pr_info("uCdimm by Lineo, Inc. <www.lineo.com>\n");
#endif
#ifdef CONFIG_M68328
pr_info("68328 support D. Jeff Dionne <[email protected]>\n");
pr_info("68328 support Kenneth Albanowski <[email protected]>\n");
#endif
#ifdef CONFIG_M68EZ328
pr_info("68EZ328 DragonBallEZ support (C) 1999 Rt-Control, Inc\n");
#endif
#ifdef CONFIG_M68VZ328
pr_info("M68VZ328 support by Evan Stawnyczy <[email protected]>\n");
pr_info("68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n");
#endif
#ifdef CONFIG_COLDFIRE
pr_info("COLDFIRE port done by Greg Ungerer, [email protected]\n");
#ifdef CONFIG_M5307
pr_info("Modified for M5307 by Dave Miller, [email protected]\n");
#endif
#ifdef CONFIG_ELITE
pr_info("Modified for M5206eLITE by Rob Scott, [email protected]\n");
#endif
#endif
pr_info("Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne\n");
#if defined( CONFIG_PILOT ) && defined( CONFIG_M68328 )
pr_info("68328/Pilot support Bernhard Kuhn <[email protected]>\n");
pr_info("TRG SuperPilot FLASH card support <[email protected]>\n");
#endif
#if defined( CONFIG_PILOT ) && defined( CONFIG_M68EZ328 )
pr_info("PalmV support by Lineo Inc. <[email protected]>\n");
#endif
#ifdef CONFIG_DRAGEN2
pr_info("DragonEngine II board support by Georges Menie\n");
#endif
#ifdef CONFIG_M5235EVB
pr_info("Motorola M5235EVB support (C)2005 Syn-tech Systems, Inc. (Jate Sujjavanich)\n");
#endif
pr_debug("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n",
_stext, _etext, _sdata, _edata, __bss_start, __bss_stop);
pr_debug("MEMORY -> ROMFS=0x%p-0x%06lx MEM=0x%06lx-0x%06lx\n ",
__bss_stop, memory_start, memory_start, memory_end);
memblock_add(_rambase, memory_end - _rambase);
memblock_reserve(_rambase, memory_start - _rambase);
/* Keep a copy of command line */
*cmdline_p = &command_line[0];
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE-1] = 0;
/*
* Give all the memory to the bootmap allocator, tell it to put the
* boot mem_map at the start of memory.
*/
min_low_pfn = PFN_DOWN(memory_start);
max_pfn = max_low_pfn = PFN_DOWN(memory_end);
#if defined(CONFIG_UBOOT) && defined(CONFIG_BLK_DEV_INITRD)
if ((initrd_start > 0) && (initrd_start < initrd_end) &&
(initrd_end < memory_end))
memblock_reserve(initrd_start, initrd_end - initrd_start);
#endif /* if defined(CONFIG_BLK_DEV_INITRD) */
/*
* Get kmalloc into gear.
*/
paging_init();
}
/*
* Get CPU information for use by the procfs.
*/
static int show_cpuinfo(struct seq_file *m, void *v)
{
char *cpu, *mmu, *fpu;
u_long clockfreq;
cpu = CPU_NAME;
mmu = "none";
fpu = "none";
clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY;
seq_printf(m, "CPU:\t\t%s\n"
"MMU:\t\t%s\n"
"FPU:\t\t%s\n"
"Clocking:\t%lu.%1luMHz\n"
"BogoMips:\t%lu.%02lu\n"
"Calibration:\t%lu loops\n",
cpu, mmu, fpu,
clockfreq / 1000000,
(clockfreq / 100000) % 10,
(loops_per_jiffy * HZ) / 500000,
((loops_per_jiffy * HZ) / 5000) % 100,
(loops_per_jiffy * HZ));
return 0;
}
static void *c_start(struct seq_file *m, loff_t *pos)
{
return *pos < NR_CPUS ? ((void *) 0x12345678) : NULL;
}
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
++*pos;
return c_start(m, pos);
}
static void c_stop(struct seq_file *m, void *v)
{
}
const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
.show = show_cpuinfo,
};
| linux-master | arch/m68k/kernel/setup_no.c |
// SPDX-License-Identifier: GPL-2.0
/*
* linux/arch/m68k/kernel/process.c
*
* Copyright (C) 1995 Hamish Macdonald
*
* 68060 fixes by Jesper Skov
*/
/*
* This file handles the architecture-dependent parts of process handling..
*/
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/sched/task.h>
#include <linux/sched/task_stack.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/smp.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/user.h>
#include <linux/reboot.h>
#include <linux/init_task.h>
#include <linux/mqueue.h>
#include <linux/rcupdate.h>
#include <linux/syscalls.h>
#include <linux/uaccess.h>
#include <linux/elfcore.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/setup.h>
asmlinkage void ret_from_fork(void);
asmlinkage void ret_from_kernel_thread(void);
void arch_cpu_idle(void)
{
#if defined(MACH_ATARI_ONLY)
/* block out HSYNC on the atari (falcon) */
__asm__("stop #0x2200" : : : "cc");
#else
__asm__("stop #0x2000" : : : "cc");
#endif
}
void machine_restart(char * __unused)
{
if (mach_reset)
mach_reset();
for (;;);
}
void machine_halt(void)
{
if (mach_halt)
mach_halt();
for (;;);
}
void machine_power_off(void)
{
do_kernel_power_off();
for (;;);
}
void (*pm_power_off)(void);
EXPORT_SYMBOL(pm_power_off);
void show_regs(struct pt_regs * regs)
{
pr_info("Format %02x Vector: %04x PC: %08lx Status: %04x %s\n",
regs->format, regs->vector, regs->pc, regs->sr,
print_tainted());
pr_info("ORIG_D0: %08lx D0: %08lx A2: %08lx A1: %08lx\n",
regs->orig_d0, regs->d0, regs->a2, regs->a1);
pr_info("A0: %08lx D5: %08lx D4: %08lx\n", regs->a0, regs->d5,
regs->d4);
pr_info("D3: %08lx D2: %08lx D1: %08lx\n", regs->d3, regs->d2,
regs->d1);
if (!(regs->sr & PS_S))
pr_info("USP: %08lx\n", rdusp());
}
void flush_thread(void)
{
current->thread.fc = USER_DATA;
#ifdef CONFIG_FPU
if (!FPU_IS_EMU) {
unsigned long zero = 0;
asm volatile("frestore %0": :"m" (zero));
}
#endif
}
/*
* Why not generic sys_clone, you ask? m68k passes all arguments on stack.
* And we need all registers saved, which means a bunch of stuff pushed
* on top of pt_regs, which means that sys_clone() arguments would be
* buried. We could, of course, copy them, but it's too costly for no
* good reason - generic clone() would have to copy them *again* for
* kernel_clone() anyway. So in this case it's actually better to pass pt_regs *
* and extract arguments for kernel_clone() from there. Eventually we might
* go for calling kernel_clone() directly from the wrapper, but only after we
* are finished with kernel_clone() prototype conversion.
*/
asmlinkage int m68k_clone(struct pt_regs *regs)
{
/* regs will be equal to current_pt_regs() */
struct kernel_clone_args args = {
.flags = regs->d1 & ~CSIGNAL,
.pidfd = (int __user *)regs->d3,
.child_tid = (int __user *)regs->d4,
.parent_tid = (int __user *)regs->d3,
.exit_signal = regs->d1 & CSIGNAL,
.stack = regs->d2,
.tls = regs->d5,
};
return kernel_clone(&args);
}
/*
* Because extra registers are saved on the stack after the sys_clone3()
* arguments, this C wrapper extracts them from pt_regs * and then calls the
* generic sys_clone3() implementation.
*/
asmlinkage int m68k_clone3(struct pt_regs *regs)
{
return sys_clone3((struct clone_args __user *)regs->d1, regs->d2);
}
int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
{
unsigned long clone_flags = args->flags;
unsigned long usp = args->stack;
unsigned long tls = args->tls;
struct fork_frame {
struct switch_stack sw;
struct pt_regs regs;
} *frame;
frame = (struct fork_frame *) (task_stack_page(p) + THREAD_SIZE) - 1;
p->thread.ksp = (unsigned long)frame;
p->thread.esp0 = (unsigned long)&frame->regs;
/*
* Must save the current SFC/DFC value, NOT the value when
* the parent was last descheduled - RGH 10-08-96
*/
p->thread.fc = USER_DATA;
if (unlikely(args->fn)) {
/* kernel thread */
memset(frame, 0, sizeof(struct fork_frame));
frame->regs.sr = PS_S;
frame->sw.a3 = (unsigned long)args->fn;
frame->sw.d7 = (unsigned long)args->fn_arg;
frame->sw.retpc = (unsigned long)ret_from_kernel_thread;
p->thread.usp = 0;
return 0;
}
memcpy(frame, container_of(current_pt_regs(), struct fork_frame, regs),
sizeof(struct fork_frame));
frame->regs.d0 = 0;
frame->sw.retpc = (unsigned long)ret_from_fork;
p->thread.usp = usp ?: rdusp();
if (clone_flags & CLONE_SETTLS)
task_thread_info(p)->tp_value = tls;
#ifdef CONFIG_FPU
if (!FPU_IS_EMU) {
/* Copy the current fpu state */
asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) {
if (CPU_IS_COLDFIRE) {
asm volatile ("fmovemd %/fp0-%/fp7,%0\n\t"
"fmovel %/fpiar,%1\n\t"
"fmovel %/fpcr,%2\n\t"
"fmovel %/fpsr,%3"
:
: "m" (p->thread.fp[0]),
"m" (p->thread.fpcntl[0]),
"m" (p->thread.fpcntl[1]),
"m" (p->thread.fpcntl[2])
: "memory");
} else {
asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
"fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
:
: "m" (p->thread.fp[0]),
"m" (p->thread.fpcntl[0])
: "memory");
}
}
/* Restore the state in case the fpu was busy */
asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
}
#endif /* CONFIG_FPU */
return 0;
}
/* Fill in the fpu structure for a core dump. */
int elf_core_copy_task_fpregs(struct task_struct *t, elf_fpregset_t *fpu)
{
if (FPU_IS_EMU) {
int i;
memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
memcpy(fpu->fpregs, current->thread.fp, 96);
/* Convert internal fpu reg representation
* into long double format
*/
for (i = 0; i < 24; i += 3)
fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
((fpu->fpregs[i] & 0x0000ffff) << 16);
return 1;
}
if (IS_ENABLED(CONFIG_FPU)) {
char fpustate[216];
/* First dump the fpu context to avoid protocol violation. */
asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
return 0;
if (CPU_IS_COLDFIRE) {
asm volatile ("fmovel %/fpiar,%0\n\t"
"fmovel %/fpcr,%1\n\t"
"fmovel %/fpsr,%2\n\t"
"fmovemd %/fp0-%/fp7,%3"
:
: "m" (fpu->fpcntl[0]),
"m" (fpu->fpcntl[1]),
"m" (fpu->fpcntl[2]),
"m" (fpu->fpregs[0])
: "memory");
} else {
asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
:
: "m" (fpu->fpcntl[0])
: "memory");
asm volatile ("fmovemx %/fp0-%/fp7,%0"
:
: "m" (fpu->fpregs[0])
: "memory");
}
}
return 1;
}
unsigned long __get_wchan(struct task_struct *p)
{
unsigned long fp, pc;
unsigned long stack_page;
int count = 0;
stack_page = (unsigned long)task_stack_page(p);
fp = ((struct switch_stack *)p->thread.ksp)->a6;
do {
if (fp < stack_page+sizeof(struct thread_info) ||
fp >= 8184+stack_page)
return 0;
pc = ((unsigned long *)fp)[1];
if (!in_sched_functions(pc))
return pc;
fp = *(unsigned long *) fp;
} while (count++ < 16);
return 0;
}
| linux-master | arch/m68k/kernel/process.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pci.c -- basic PCI support code
*
* (C) Copyright 2011, Greg Ungerer <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/pci.h>
/*
* From arch/i386/kernel/pci-i386.c:
*
* We need to avoid collisions with `mirrored' VGA ports
* and other strange ISA hardware, so we always want the
* addresses to be allocated in the 0x000-0x0ff region
* modulo 0x400.
*
* Why? Because some silly external IO cards only decode
* the low 10 bits of the IO address. The 0x00-0xff region
* is reserved for motherboard devices that decode all 16
* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
* but we want to try to avoid allocating at 0x2900-0x2bff
* which might be mirrored at 0x0100-0x03ff..
*/
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
{
resource_size_t start = res->start;
if ((res->flags & IORESOURCE_IO) && (start & 0x300))
start = (start + 0x3ff) & ~0x3ff;
start = (start + align - 1) & ~(align - 1);
return start;
}
/*
* This is taken from the ARM code for this.
*/
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
struct resource *r;
u16 cmd, newcmd;
int idx;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
newcmd = cmd;
for (idx = 0; idx < 6; idx++) {
/* Only set up the requested stuff */
if (!(mask & (1 << idx)))
continue;
r = dev->resource + idx;
if (!r->start && r->end) {
pr_err("PCI: Device %s not available because of resource collisions\n",
pci_name(dev));
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
newcmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
newcmd |= PCI_COMMAND_MEMORY;
}
/*
* Bridges (eg, cardbus bridges) need to be fully enabled
*/
if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
if (newcmd != cmd) {
pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
pci_name(dev), cmd, newcmd);
pci_write_config_word(dev, PCI_COMMAND, newcmd);
}
return 0;
}
void pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev;
list_for_each_entry(dev, &bus->devices, bus_list) {
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
}
}
| linux-master | arch/m68k/kernel/pcibios.c |
/*
* irq.c
*
* (C) Copyright 2007, Greg Ungerer <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <asm/traps.h>
asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
{
struct pt_regs *oldregs = set_irq_regs(regs);
irq_enter();
generic_handle_irq(irq);
irq_exit();
set_irq_regs(oldregs);
}
/* The number of spurious interrupts */
atomic_t irq_err_count;
int arch_show_interrupts(struct seq_file *p, int prec)
{
seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
return 0;
}
| linux-master | arch/m68k/kernel/irq.c |
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