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// SPDX-License-Identifier: GPL-2.0-only
/*
* RTC client/driver for the Maxim/Dallas DS1374 Real-Time Clock over I2C
*
* Based on code by Randy Vinson <[email protected]>,
* which was based on the m41t00.c by Mark Greer <[email protected]>.
*
* Copyright (C) 2014 Rose Technology
* Copyright (C) 2006-2007 Freescale Semiconductor
* Copyright (c) 2005 MontaVista Software, Inc.
*/
/*
* It would be more efficient to use i2c msgs/i2c_transfer directly but, as
* recommended in .../Documentation/i2c/writing-clients.rst section
* "Sending and receiving", using SMBus level communication is preferred.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <linux/pm.h>
#ifdef CONFIG_RTC_DRV_DS1374_WDT
#include <linux/fs.h>
#include <linux/ioctl.h>
#include <linux/miscdevice.h>
#include <linux/reboot.h>
#include <linux/watchdog.h>
#endif
#define DS1374_REG_TOD0 0x00 /* Time of Day */
#define DS1374_REG_TOD1 0x01
#define DS1374_REG_TOD2 0x02
#define DS1374_REG_TOD3 0x03
#define DS1374_REG_WDALM0 0x04 /* Watchdog/Alarm */
#define DS1374_REG_WDALM1 0x05
#define DS1374_REG_WDALM2 0x06
#define DS1374_REG_CR 0x07 /* Control */
#define DS1374_REG_CR_AIE 0x01 /* Alarm Int. Enable */
#define DS1374_REG_CR_WDSTR 0x08 /* 1=INT, 0=RST */
#define DS1374_REG_CR_WDALM 0x20 /* 1=Watchdog, 0=Alarm */
#define DS1374_REG_CR_WACE 0x40 /* WD/Alarm counter enable */
#define DS1374_REG_SR 0x08 /* Status */
#define DS1374_REG_SR_OSF 0x80 /* Oscillator Stop Flag */
#define DS1374_REG_SR_AF 0x01 /* Alarm Flag */
#define DS1374_REG_TCR 0x09 /* Trickle Charge */
static const struct i2c_device_id ds1374_id[] = {
{ "ds1374", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ds1374_id);
#ifdef CONFIG_OF
static const struct of_device_id ds1374_of_match[] = {
{ .compatible = "dallas,ds1374" },
{ }
};
MODULE_DEVICE_TABLE(of, ds1374_of_match);
#endif
struct ds1374 {
struct i2c_client *client;
struct rtc_device *rtc;
struct work_struct work;
#ifdef CONFIG_RTC_DRV_DS1374_WDT
struct watchdog_device wdt;
#endif
/* The mutex protects alarm operations, and prevents a race
* between the enable_irq() in the workqueue and the free_irq()
* in the remove function.
*/
struct mutex mutex;
int exiting;
};
static struct i2c_driver ds1374_driver;
static int ds1374_read_rtc(struct i2c_client *client, u32 *time,
int reg, int nbytes)
{
u8 buf[4];
int ret;
int i;
if (WARN_ON(nbytes > 4))
return -EINVAL;
ret = i2c_smbus_read_i2c_block_data(client, reg, nbytes, buf);
if (ret < 0)
return ret;
if (ret < nbytes)
return -EIO;
for (i = nbytes - 1, *time = 0; i >= 0; i--)
*time = (*time << 8) | buf[i];
return 0;
}
static int ds1374_write_rtc(struct i2c_client *client, u32 time,
int reg, int nbytes)
{
u8 buf[4];
int i;
if (nbytes > 4) {
WARN_ON(1);
return -EINVAL;
}
for (i = 0; i < nbytes; i++) {
buf[i] = time & 0xff;
time >>= 8;
}
return i2c_smbus_write_i2c_block_data(client, reg, nbytes, buf);
}
static int ds1374_check_rtc_status(struct i2c_client *client)
{
int ret = 0;
int control, stat;
stat = i2c_smbus_read_byte_data(client, DS1374_REG_SR);
if (stat < 0)
return stat;
if (stat & DS1374_REG_SR_OSF)
dev_warn(&client->dev,
"oscillator discontinuity flagged, time unreliable\n");
stat &= ~(DS1374_REG_SR_OSF | DS1374_REG_SR_AF);
ret = i2c_smbus_write_byte_data(client, DS1374_REG_SR, stat);
if (ret < 0)
return ret;
/* If the alarm is pending, clear it before requesting
* the interrupt, so an interrupt event isn't reported
* before everything is initialized.
*/
control = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (control < 0)
return control;
control &= ~(DS1374_REG_CR_WACE | DS1374_REG_CR_AIE);
return i2c_smbus_write_byte_data(client, DS1374_REG_CR, control);
}
static int ds1374_read_time(struct device *dev, struct rtc_time *time)
{
struct i2c_client *client = to_i2c_client(dev);
u32 itime;
int ret;
ret = ds1374_read_rtc(client, &itime, DS1374_REG_TOD0, 4);
if (!ret)
rtc_time64_to_tm(itime, time);
return ret;
}
static int ds1374_set_time(struct device *dev, struct rtc_time *time)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned long itime = rtc_tm_to_time64(time);
return ds1374_write_rtc(client, itime, DS1374_REG_TOD0, 4);
}
#ifndef CONFIG_RTC_DRV_DS1374_WDT
/* The ds1374 has a decrementer for an alarm, rather than a comparator.
* If the time of day is changed, then the alarm will need to be
* reset.
*/
static int ds1374_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct i2c_client *client = to_i2c_client(dev);
struct ds1374 *ds1374 = i2c_get_clientdata(client);
u32 now, cur_alarm;
int cr, sr;
int ret = 0;
if (client->irq <= 0)
return -EINVAL;
mutex_lock(&ds1374->mutex);
cr = ret = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (ret < 0)
goto out;
sr = ret = i2c_smbus_read_byte_data(client, DS1374_REG_SR);
if (ret < 0)
goto out;
ret = ds1374_read_rtc(client, &now, DS1374_REG_TOD0, 4);
if (ret)
goto out;
ret = ds1374_read_rtc(client, &cur_alarm, DS1374_REG_WDALM0, 3);
if (ret)
goto out;
rtc_time64_to_tm(now + cur_alarm, &alarm->time);
alarm->enabled = !!(cr & DS1374_REG_CR_WACE);
alarm->pending = !!(sr & DS1374_REG_SR_AF);
out:
mutex_unlock(&ds1374->mutex);
return ret;
}
static int ds1374_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct i2c_client *client = to_i2c_client(dev);
struct ds1374 *ds1374 = i2c_get_clientdata(client);
struct rtc_time now;
unsigned long new_alarm, itime;
int cr;
int ret = 0;
if (client->irq <= 0)
return -EINVAL;
ret = ds1374_read_time(dev, &now);
if (ret < 0)
return ret;
new_alarm = rtc_tm_to_time64(&alarm->time);
itime = rtc_tm_to_time64(&now);
/* This can happen due to races, in addition to dates that are
* truly in the past. To avoid requiring the caller to check for
* races, dates in the past are assumed to be in the recent past
* (i.e. not something that we'd rather the caller know about via
* an error), and the alarm is set to go off as soon as possible.
*/
if (time_before_eq(new_alarm, itime))
new_alarm = 1;
else
new_alarm -= itime;
mutex_lock(&ds1374->mutex);
ret = cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (ret < 0)
goto out;
/* Disable any existing alarm before setting the new one
* (or lack thereof). */
cr &= ~DS1374_REG_CR_WACE;
ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
if (ret < 0)
goto out;
ret = ds1374_write_rtc(client, new_alarm, DS1374_REG_WDALM0, 3);
if (ret)
goto out;
if (alarm->enabled) {
cr |= DS1374_REG_CR_WACE | DS1374_REG_CR_AIE;
cr &= ~DS1374_REG_CR_WDALM;
ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
}
out:
mutex_unlock(&ds1374->mutex);
return ret;
}
#endif
static irqreturn_t ds1374_irq(int irq, void *dev_id)
{
struct i2c_client *client = dev_id;
struct ds1374 *ds1374 = i2c_get_clientdata(client);
disable_irq_nosync(irq);
schedule_work(&ds1374->work);
return IRQ_HANDLED;
}
static void ds1374_work(struct work_struct *work)
{
struct ds1374 *ds1374 = container_of(work, struct ds1374, work);
struct i2c_client *client = ds1374->client;
int stat, control;
mutex_lock(&ds1374->mutex);
stat = i2c_smbus_read_byte_data(client, DS1374_REG_SR);
if (stat < 0)
goto unlock;
if (stat & DS1374_REG_SR_AF) {
stat &= ~DS1374_REG_SR_AF;
i2c_smbus_write_byte_data(client, DS1374_REG_SR, stat);
control = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (control < 0)
goto out;
control &= ~(DS1374_REG_CR_WACE | DS1374_REG_CR_AIE);
i2c_smbus_write_byte_data(client, DS1374_REG_CR, control);
rtc_update_irq(ds1374->rtc, 1, RTC_AF | RTC_IRQF);
}
out:
if (!ds1374->exiting)
enable_irq(client->irq);
unlock:
mutex_unlock(&ds1374->mutex);
}
#ifndef CONFIG_RTC_DRV_DS1374_WDT
static int ds1374_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct i2c_client *client = to_i2c_client(dev);
struct ds1374 *ds1374 = i2c_get_clientdata(client);
int ret;
mutex_lock(&ds1374->mutex);
ret = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (ret < 0)
goto out;
if (enabled) {
ret |= DS1374_REG_CR_WACE | DS1374_REG_CR_AIE;
ret &= ~DS1374_REG_CR_WDALM;
} else {
ret &= ~DS1374_REG_CR_WACE;
}
ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, ret);
out:
mutex_unlock(&ds1374->mutex);
return ret;
}
#endif
static const struct rtc_class_ops ds1374_rtc_ops = {
.read_time = ds1374_read_time,
.set_time = ds1374_set_time,
#ifndef CONFIG_RTC_DRV_DS1374_WDT
.read_alarm = ds1374_read_alarm,
.set_alarm = ds1374_set_alarm,
.alarm_irq_enable = ds1374_alarm_irq_enable,
#endif
};
#ifdef CONFIG_RTC_DRV_DS1374_WDT
/*
*****************************************************************************
*
* Watchdog Driver
*
*****************************************************************************
*/
/* Default margin */
#define TIMER_MARGIN_DEFAULT 32
#define TIMER_MARGIN_MIN 1
#define TIMER_MARGIN_MAX 4095 /* 24-bit value */
static int wdt_margin;
module_param(wdt_margin, int, 0);
MODULE_PARM_DESC(wdt_margin, "Watchdog timeout in seconds (default 32s)");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default ="
__MODULE_STRING(WATCHDOG_NOWAYOUT)")");
static const struct watchdog_info ds1374_wdt_info = {
.identity = "DS1374 Watchdog",
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE,
};
static int ds1374_wdt_settimeout(struct watchdog_device *wdt, unsigned int timeout)
{
struct ds1374 *ds1374 = watchdog_get_drvdata(wdt);
struct i2c_client *client = ds1374->client;
int ret, cr;
wdt->timeout = timeout;
cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (cr < 0)
return cr;
/* Disable any existing watchdog/alarm before setting the new one */
cr &= ~DS1374_REG_CR_WACE;
ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
if (ret < 0)
return ret;
/* Set new watchdog time */
timeout = timeout * 4096;
ret = ds1374_write_rtc(client, timeout, DS1374_REG_WDALM0, 3);
if (ret)
return ret;
/* Enable watchdog timer */
cr |= DS1374_REG_CR_WACE | DS1374_REG_CR_WDALM;
cr &= ~DS1374_REG_CR_WDSTR;/* for RST PIN */
cr &= ~DS1374_REG_CR_AIE;
ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
if (ret < 0)
return ret;
return 0;
}
/*
* Reload the watchdog timer. (ie, pat the watchdog)
*/
static int ds1374_wdt_start(struct watchdog_device *wdt)
{
struct ds1374 *ds1374 = watchdog_get_drvdata(wdt);
u32 val;
return ds1374_read_rtc(ds1374->client, &val, DS1374_REG_WDALM0, 3);
}
static int ds1374_wdt_stop(struct watchdog_device *wdt)
{
struct ds1374 *ds1374 = watchdog_get_drvdata(wdt);
struct i2c_client *client = ds1374->client;
int cr;
cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
if (cr < 0)
return cr;
/* Disable watchdog timer */
cr &= ~DS1374_REG_CR_WACE;
return i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
}
static const struct watchdog_ops ds1374_wdt_ops = {
.owner = THIS_MODULE,
.start = ds1374_wdt_start,
.stop = ds1374_wdt_stop,
.set_timeout = ds1374_wdt_settimeout,
};
#endif /*CONFIG_RTC_DRV_DS1374_WDT*/
/*
*****************************************************************************
*
* Driver Interface
*
*****************************************************************************
*/
static int ds1374_probe(struct i2c_client *client)
{
struct ds1374 *ds1374;
int ret;
ds1374 = devm_kzalloc(&client->dev, sizeof(struct ds1374), GFP_KERNEL);
if (!ds1374)
return -ENOMEM;
ds1374->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(ds1374->rtc))
return PTR_ERR(ds1374->rtc);
ds1374->client = client;
i2c_set_clientdata(client, ds1374);
INIT_WORK(&ds1374->work, ds1374_work);
mutex_init(&ds1374->mutex);
ret = ds1374_check_rtc_status(client);
if (ret)
return ret;
if (client->irq > 0) {
ret = devm_request_irq(&client->dev, client->irq, ds1374_irq, 0,
"ds1374", client);
if (ret) {
dev_err(&client->dev, "unable to request IRQ\n");
return ret;
}
device_set_wakeup_capable(&client->dev, 1);
}
ds1374->rtc->ops = &ds1374_rtc_ops;
ds1374->rtc->range_max = U32_MAX;
ret = devm_rtc_register_device(ds1374->rtc);
if (ret)
return ret;
#ifdef CONFIG_RTC_DRV_DS1374_WDT
ds1374->wdt.info = &ds1374_wdt_info;
ds1374->wdt.ops = &ds1374_wdt_ops;
ds1374->wdt.timeout = TIMER_MARGIN_DEFAULT;
ds1374->wdt.min_timeout = TIMER_MARGIN_MIN;
ds1374->wdt.max_timeout = TIMER_MARGIN_MAX;
watchdog_init_timeout(&ds1374->wdt, wdt_margin, &client->dev);
watchdog_set_nowayout(&ds1374->wdt, nowayout);
watchdog_stop_on_reboot(&ds1374->wdt);
watchdog_stop_on_unregister(&ds1374->wdt);
watchdog_set_drvdata(&ds1374->wdt, ds1374);
ds1374_wdt_settimeout(&ds1374->wdt, ds1374->wdt.timeout);
ret = devm_watchdog_register_device(&client->dev, &ds1374->wdt);
if (ret)
return ret;
#endif
return 0;
}
static void ds1374_remove(struct i2c_client *client)
{
struct ds1374 *ds1374 = i2c_get_clientdata(client);
if (client->irq > 0) {
mutex_lock(&ds1374->mutex);
ds1374->exiting = 1;
mutex_unlock(&ds1374->mutex);
devm_free_irq(&client->dev, client->irq, client);
cancel_work_sync(&ds1374->work);
}
}
#ifdef CONFIG_PM_SLEEP
static int ds1374_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
if (client->irq > 0 && device_may_wakeup(&client->dev))
enable_irq_wake(client->irq);
return 0;
}
static int ds1374_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
if (client->irq > 0 && device_may_wakeup(&client->dev))
disable_irq_wake(client->irq);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(ds1374_pm, ds1374_suspend, ds1374_resume);
static struct i2c_driver ds1374_driver = {
.driver = {
.name = "rtc-ds1374",
.of_match_table = of_match_ptr(ds1374_of_match),
.pm = &ds1374_pm,
},
.probe = ds1374_probe,
.remove = ds1374_remove,
.id_table = ds1374_id,
};
module_i2c_driver(ds1374_driver);
MODULE_AUTHOR("Scott Wood <[email protected]>");
MODULE_DESCRIPTION("Maxim/Dallas DS1374 RTC Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-ds1374.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RTC driver for the Armada 38x Marvell SoCs
*
* Copyright (C) 2015 Marvell
*
* Gregory Clement <[email protected]>
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#define RTC_STATUS 0x0
#define RTC_STATUS_ALARM1 BIT(0)
#define RTC_STATUS_ALARM2 BIT(1)
#define RTC_IRQ1_CONF 0x4
#define RTC_IRQ2_CONF 0x8
#define RTC_IRQ_AL_EN BIT(0)
#define RTC_IRQ_FREQ_EN BIT(1)
#define RTC_IRQ_FREQ_1HZ BIT(2)
#define RTC_CCR 0x18
#define RTC_CCR_MODE BIT(15)
#define RTC_CONF_TEST 0x1C
#define RTC_NOMINAL_TIMING BIT(13)
#define RTC_TIME 0xC
#define RTC_ALARM1 0x10
#define RTC_ALARM2 0x14
/* Armada38x SoC registers */
#define RTC_38X_BRIDGE_TIMING_CTL 0x0
#define RTC_38X_PERIOD_OFFS 0
#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS)
#define RTC_38X_READ_DELAY_OFFS 26
#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS)
/* Armada 7K/8K registers */
#define RTC_8K_BRIDGE_TIMING_CTL0 0x0
#define RTC_8K_WRCLK_PERIOD_OFFS 0
#define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
#define RTC_8K_WRCLK_SETUP_OFFS 16
#define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
#define RTC_8K_BRIDGE_TIMING_CTL1 0x4
#define RTC_8K_READ_DELAY_OFFS 0
#define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS)
#define RTC_8K_ISR 0x10
#define RTC_8K_IMR 0x14
#define RTC_8K_ALARM2 BIT(0)
#define SOC_RTC_INTERRUPT 0x8
#define SOC_RTC_ALARM1 BIT(0)
#define SOC_RTC_ALARM2 BIT(1)
#define SOC_RTC_ALARM1_MASK BIT(2)
#define SOC_RTC_ALARM2_MASK BIT(3)
#define SAMPLE_NR 100
struct value_to_freq {
u32 value;
u8 freq;
};
struct armada38x_rtc {
struct rtc_device *rtc_dev;
void __iomem *regs;
void __iomem *regs_soc;
spinlock_t lock;
int irq;
bool initialized;
struct value_to_freq *val_to_freq;
const struct armada38x_rtc_data *data;
};
#define ALARM1 0
#define ALARM2 1
#define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32))
struct armada38x_rtc_data {
/* Initialize the RTC-MBUS bridge timing */
void (*update_mbus_timing)(struct armada38x_rtc *rtc);
u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
void (*clear_isr)(struct armada38x_rtc *rtc);
void (*unmask_interrupt)(struct armada38x_rtc *rtc);
u32 alarm;
};
/*
* According to the datasheet, the OS should wait 5us after every
* register write to the RTC hard macro so that the required update
* can occur without holding off the system bus
* According to errata RES-3124064, Write to any RTC register
* may fail. As a workaround, before writing to RTC
* register, issue a dummy write of 0x0 twice to RTC Status
* register.
*/
static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
{
writel(0, rtc->regs + RTC_STATUS);
writel(0, rtc->regs + RTC_STATUS);
writel(val, rtc->regs + offset);
udelay(5);
}
/* Update RTC-MBUS bridge timing parameters */
static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
{
u32 reg;
reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
reg &= ~RTC_38X_PERIOD_MASK;
reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
reg &= ~RTC_38X_READ_DELAY_MASK;
reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
}
static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
{
u32 reg;
reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
reg &= ~RTC_8K_WRCLK_SETUP_MASK;
reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
reg &= ~RTC_8K_READ_DELAY_MASK;
reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
}
static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
{
return readl(rtc->regs + rtc_reg);
}
static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
{
int i, index_max = 0, max = 0;
for (i = 0; i < SAMPLE_NR; i++) {
rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
rtc->val_to_freq[i].freq = 0;
}
for (i = 0; i < SAMPLE_NR; i++) {
int j = 0;
u32 value = rtc->val_to_freq[i].value;
while (rtc->val_to_freq[j].freq) {
if (rtc->val_to_freq[j].value == value) {
rtc->val_to_freq[j].freq++;
break;
}
j++;
}
if (!rtc->val_to_freq[j].freq) {
rtc->val_to_freq[j].value = value;
rtc->val_to_freq[j].freq = 1;
}
if (rtc->val_to_freq[j].freq > max) {
index_max = j;
max = rtc->val_to_freq[j].freq;
}
/*
* If a value already has half of the sample this is the most
* frequent one and we can stop the research right now
*/
if (max > SAMPLE_NR / 2)
break;
}
return rtc->val_to_freq[index_max].value;
}
static void armada38x_clear_isr(struct armada38x_rtc *rtc)
{
u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
}
static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
{
u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
}
static void armada8k_clear_isr(struct armada38x_rtc *rtc)
{
writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
}
static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
{
writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
}
static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
unsigned long time, flags;
spin_lock_irqsave(&rtc->lock, flags);
time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
spin_unlock_irqrestore(&rtc->lock, flags);
rtc_time64_to_tm(time, tm);
return 0;
}
static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
{
u32 reg;
reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
/* If bits [7:0] are non-zero, assume RTC was uninitialized */
if (reg & 0xff) {
rtc_delayed_write(0, rtc, RTC_CONF_TEST);
msleep(500); /* Oscillator startup time */
rtc_delayed_write(0, rtc, RTC_TIME);
rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
RTC_STATUS);
rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
}
rtc->initialized = true;
}
static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
unsigned long time, flags;
time = rtc_tm_to_time64(tm);
if (!rtc->initialized)
armada38x_rtc_reset(rtc);
spin_lock_irqsave(&rtc->lock, flags);
rtc_delayed_write(time, rtc, RTC_TIME);
spin_unlock_irqrestore(&rtc->lock, flags);
return 0;
}
static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
unsigned long time, flags;
u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
u32 val;
spin_lock_irqsave(&rtc->lock, flags);
time = rtc->data->read_rtc_reg(rtc, reg);
val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
spin_unlock_irqrestore(&rtc->lock, flags);
alrm->enabled = val ? 1 : 0;
rtc_time64_to_tm(time, &alrm->time);
return 0;
}
static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
unsigned long time, flags;
time = rtc_tm_to_time64(&alrm->time);
spin_lock_irqsave(&rtc->lock, flags);
rtc_delayed_write(time, rtc, reg);
if (alrm->enabled) {
rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
rtc->data->unmask_interrupt(rtc);
}
spin_unlock_irqrestore(&rtc->lock, flags);
return 0;
}
static int armada38x_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
unsigned long flags;
spin_lock_irqsave(&rtc->lock, flags);
if (enabled)
rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
else
rtc_delayed_write(0, rtc, reg_irq);
spin_unlock_irqrestore(&rtc->lock, flags);
return 0;
}
static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
{
struct armada38x_rtc *rtc = data;
u32 val;
int event = RTC_IRQF | RTC_AF;
u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
spin_lock(&rtc->lock);
rtc->data->clear_isr(rtc);
val = rtc->data->read_rtc_reg(rtc, reg_irq);
/* disable all the interrupts for alarm*/
rtc_delayed_write(0, rtc, reg_irq);
/* Ack the event */
rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
spin_unlock(&rtc->lock);
if (val & RTC_IRQ_FREQ_EN) {
if (val & RTC_IRQ_FREQ_1HZ)
event |= RTC_UF;
else
event |= RTC_PF;
}
rtc_update_irq(rtc->rtc_dev, 1, event);
return IRQ_HANDLED;
}
/*
* The information given in the Armada 388 functional spec is complex.
* They give two different formulas for calculating the offset value,
* but when considering "Offset" as an 8-bit signed integer, they both
* reduce down to (we shall rename "Offset" as "val" here):
*
* val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768
*
* Converting to time, f = 1/t:
* val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768
*
* => t_measured / t_ideal = val * resolution + 1
*
* "offset" in the RTC interface is defined as:
* t = t0 * (1 + offset * 1e-9)
* where t is the desired period, t0 is the measured period with a zero
* offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
* offset = (t_ideal / t_measured - 1) / 1e-9
*
* => t_ideal / t_measured = offset * 1e-9 + 1
*
* so:
*
* offset * 1e-9 + 1 = 1 / (val * resolution + 1)
*
* We want "resolution" to be an integer, so resolution = R * 1e-9, giving
* offset = 1e18 / (val * R + 1e9) - 1e9
* val = (1e18 / (offset + 1e9) - 1e9) / R
* with a common transformation:
* f(x) = 1e18 / (x + 1e9) - 1e9
* offset = f(val * R)
* val = f(offset) / R
*
* Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
*/
static long armada38x_ppb_convert(long ppb)
{
long div = ppb + 1000000000L;
return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
}
static int armada38x_rtc_read_offset(struct device *dev, long *offset)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
unsigned long ccr, flags;
long ppb_cor;
spin_lock_irqsave(&rtc->lock, flags);
ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
spin_unlock_irqrestore(&rtc->lock, flags);
ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
/* ppb_cor + 1000000000L can never be zero */
*offset = armada38x_ppb_convert(ppb_cor);
return 0;
}
static int armada38x_rtc_set_offset(struct device *dev, long offset)
{
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
unsigned long ccr = 0;
long ppb_cor, off;
/*
* The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
* need to clamp the input. This equates to -484270 .. 488558.
* Not only is this to stop out of range "off" but also to
* avoid the division by zero in armada38x_ppb_convert().
*/
offset = clamp(offset, -484270L, 488558L);
ppb_cor = armada38x_ppb_convert(offset);
/*
* Use low update mode where possible, which gives a better
* resolution of correction.
*/
off = DIV_ROUND_CLOSEST(ppb_cor, 954);
if (off > 127 || off < -128) {
ccr = RTC_CCR_MODE;
off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
}
/*
* Armada 388 requires a bit pattern in bits 14..8 depending on
* the sign bit: { 0, ~S, S, S, S, S, S }
*/
ccr |= (off & 0x3fff) ^ 0x2000;
rtc_delayed_write(ccr, rtc, RTC_CCR);
return 0;
}
static const struct rtc_class_ops armada38x_rtc_ops = {
.read_time = armada38x_rtc_read_time,
.set_time = armada38x_rtc_set_time,
.read_alarm = armada38x_rtc_read_alarm,
.set_alarm = armada38x_rtc_set_alarm,
.alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
.read_offset = armada38x_rtc_read_offset,
.set_offset = armada38x_rtc_set_offset,
};
static const struct armada38x_rtc_data armada38x_data = {
.update_mbus_timing = rtc_update_38x_mbus_timing_params,
.read_rtc_reg = read_rtc_register_38x_wa,
.clear_isr = armada38x_clear_isr,
.unmask_interrupt = armada38x_unmask_interrupt,
.alarm = ALARM1,
};
static const struct armada38x_rtc_data armada8k_data = {
.update_mbus_timing = rtc_update_8k_mbus_timing_params,
.read_rtc_reg = read_rtc_register,
.clear_isr = armada8k_clear_isr,
.unmask_interrupt = armada8k_unmask_interrupt,
.alarm = ALARM2,
};
static const struct of_device_id armada38x_rtc_of_match_table[] = {
{
.compatible = "marvell,armada-380-rtc",
.data = &armada38x_data,
},
{
.compatible = "marvell,armada-8k-rtc",
.data = &armada8k_data,
},
{}
};
MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
static __init int armada38x_rtc_probe(struct platform_device *pdev)
{
struct armada38x_rtc *rtc;
rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->data = of_device_get_match_data(&pdev->dev);
rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
sizeof(struct value_to_freq), GFP_KERNEL);
if (!rtc->val_to_freq)
return -ENOMEM;
spin_lock_init(&rtc->lock);
rtc->regs = devm_platform_ioremap_resource_byname(pdev, "rtc");
if (IS_ERR(rtc->regs))
return PTR_ERR(rtc->regs);
rtc->regs_soc = devm_platform_ioremap_resource_byname(pdev, "rtc-soc");
if (IS_ERR(rtc->regs_soc))
return PTR_ERR(rtc->regs_soc);
rtc->irq = platform_get_irq(pdev, 0);
if (rtc->irq < 0)
return rtc->irq;
rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc_dev))
return PTR_ERR(rtc->rtc_dev);
if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
0, pdev->name, rtc) < 0) {
dev_warn(&pdev->dev, "Interrupt not available.\n");
rtc->irq = -1;
}
platform_set_drvdata(pdev, rtc);
if (rtc->irq != -1)
device_init_wakeup(&pdev->dev, 1);
else
clear_bit(RTC_FEATURE_ALARM, rtc->rtc_dev->features);
/* Update RTC-MBUS bridge timing parameters */
rtc->data->update_mbus_timing(rtc);
rtc->rtc_dev->ops = &armada38x_rtc_ops;
rtc->rtc_dev->range_max = U32_MAX;
return devm_rtc_register_device(rtc->rtc_dev);
}
#ifdef CONFIG_PM_SLEEP
static int armada38x_rtc_suspend(struct device *dev)
{
if (device_may_wakeup(dev)) {
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
return enable_irq_wake(rtc->irq);
}
return 0;
}
static int armada38x_rtc_resume(struct device *dev)
{
if (device_may_wakeup(dev)) {
struct armada38x_rtc *rtc = dev_get_drvdata(dev);
/* Update RTC-MBUS bridge timing parameters */
rtc->data->update_mbus_timing(rtc);
return disable_irq_wake(rtc->irq);
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
armada38x_rtc_suspend, armada38x_rtc_resume);
static struct platform_driver armada38x_rtc_driver = {
.driver = {
.name = "armada38x-rtc",
.pm = &armada38x_rtc_pm_ops,
.of_match_table = armada38x_rtc_of_match_table,
},
};
module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
MODULE_AUTHOR("Gregory CLEMENT <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-armada38x.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* APM X-Gene SoC Real Time Clock Driver
*
* Copyright (c) 2014, Applied Micro Circuits Corporation
* Author: Rameshwar Prasad Sahu <[email protected]>
* Loc Ho <[email protected]>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/slab.h>
/* RTC CSR Registers */
#define RTC_CCVR 0x00
#define RTC_CMR 0x04
#define RTC_CLR 0x08
#define RTC_CCR 0x0C
#define RTC_CCR_IE BIT(0)
#define RTC_CCR_MASK BIT(1)
#define RTC_CCR_EN BIT(2)
#define RTC_CCR_WEN BIT(3)
#define RTC_STAT 0x10
#define RTC_STAT_BIT BIT(0)
#define RTC_RSTAT 0x14
#define RTC_EOI 0x18
#define RTC_VER 0x1C
struct xgene_rtc_dev {
struct rtc_device *rtc;
void __iomem *csr_base;
struct clk *clk;
unsigned int irq_wake;
unsigned int irq_enabled;
};
static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
return 0;
}
static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
/*
* NOTE: After the following write, the RTC_CCVR is only reflected
* after the update cycle of 1 seconds.
*/
writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
return 0;
}
static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
/* If possible, CMR should be read here */
rtc_time64_to_tm(0, &alrm->time);
alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
return 0;
}
static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
{
struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
u32 ccr;
ccr = readl(pdata->csr_base + RTC_CCR);
if (enabled) {
ccr &= ~RTC_CCR_MASK;
ccr |= RTC_CCR_IE;
} else {
ccr &= ~RTC_CCR_IE;
ccr |= RTC_CCR_MASK;
}
writel(ccr, pdata->csr_base + RTC_CCR);
return 0;
}
static int xgene_rtc_alarm_irq_enabled(struct device *dev)
{
struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
}
static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
return 0;
}
static const struct rtc_class_ops xgene_rtc_ops = {
.read_time = xgene_rtc_read_time,
.set_time = xgene_rtc_set_time,
.read_alarm = xgene_rtc_read_alarm,
.set_alarm = xgene_rtc_set_alarm,
.alarm_irq_enable = xgene_rtc_alarm_irq_enable,
};
static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
{
struct xgene_rtc_dev *pdata = id;
/* Check if interrupt asserted */
if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
return IRQ_NONE;
/* Clear interrupt */
readl(pdata->csr_base + RTC_EOI);
rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static int xgene_rtc_probe(struct platform_device *pdev)
{
struct xgene_rtc_dev *pdata;
int ret;
int irq;
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
platform_set_drvdata(pdev, pdata);
pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdata->csr_base))
return PTR_ERR(pdata->csr_base);
pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pdata->rtc))
return PTR_ERR(pdata->rtc);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
dev_name(&pdev->dev), pdata);
if (ret) {
dev_err(&pdev->dev, "Could not request IRQ\n");
return ret;
}
pdata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pdata->clk)) {
dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
return -ENODEV;
}
ret = clk_prepare_enable(pdata->clk);
if (ret)
return ret;
/* Turn on the clock and the crystal */
writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
ret = device_init_wakeup(&pdev->dev, 1);
if (ret) {
clk_disable_unprepare(pdata->clk);
return ret;
}
pdata->rtc->ops = &xgene_rtc_ops;
pdata->rtc->range_max = U32_MAX;
ret = devm_rtc_register_device(pdata->rtc);
if (ret) {
clk_disable_unprepare(pdata->clk);
return ret;
}
return 0;
}
static void xgene_rtc_remove(struct platform_device *pdev)
{
struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
device_init_wakeup(&pdev->dev, 0);
clk_disable_unprepare(pdata->clk);
}
static int __maybe_unused xgene_rtc_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
int irq;
irq = platform_get_irq(pdev, 0);
/*
* If this RTC alarm will be used for waking the system up,
* don't disable it of course. Else we just disable the alarm
* and await suspension.
*/
if (device_may_wakeup(&pdev->dev)) {
if (!enable_irq_wake(irq))
pdata->irq_wake = 1;
} else {
pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
xgene_rtc_alarm_irq_enable(dev, 0);
clk_disable_unprepare(pdata->clk);
}
return 0;
}
static int __maybe_unused xgene_rtc_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
int irq;
int rc;
irq = platform_get_irq(pdev, 0);
if (device_may_wakeup(&pdev->dev)) {
if (pdata->irq_wake) {
disable_irq_wake(irq);
pdata->irq_wake = 0;
}
} else {
rc = clk_prepare_enable(pdata->clk);
if (rc) {
dev_err(dev, "Unable to enable clock error %d\n", rc);
return rc;
}
xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);
#ifdef CONFIG_OF
static const struct of_device_id xgene_rtc_of_match[] = {
{.compatible = "apm,xgene-rtc" },
{ }
};
MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
#endif
static struct platform_driver xgene_rtc_driver = {
.probe = xgene_rtc_probe,
.remove_new = xgene_rtc_remove,
.driver = {
.name = "xgene-rtc",
.pm = &xgene_rtc_pm_ops,
.of_match_table = of_match_ptr(xgene_rtc_of_match),
},
};
module_platform_driver(xgene_rtc_driver);
MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
MODULE_AUTHOR("Rameshwar Sahu <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-xgene.c |
// SPDX-License-Identifier: GPL-2.0
/*
* MOXA ART RTC driver.
*
* Copyright (C) 2013 Jonas Jensen
*
* Jonas Jensen <[email protected]>
*
* Based on code from
* Moxa Technology Co., Ltd. <www.moxa.com>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/gpio/consumer.h>
#define GPIO_RTC_RESERVED 0x0C
#define GPIO_RTC_DATA_SET 0x10
#define GPIO_RTC_DATA_CLEAR 0x14
#define GPIO_RTC_PIN_PULL_ENABLE 0x18
#define GPIO_RTC_PIN_PULL_TYPE 0x1C
#define GPIO_RTC_INT_ENABLE 0x20
#define GPIO_RTC_INT_RAW_STATE 0x24
#define GPIO_RTC_INT_MASKED_STATE 0x28
#define GPIO_RTC_INT_MASK 0x2C
#define GPIO_RTC_INT_CLEAR 0x30
#define GPIO_RTC_INT_TRIGGER 0x34
#define GPIO_RTC_INT_BOTH 0x38
#define GPIO_RTC_INT_RISE_NEG 0x3C
#define GPIO_RTC_BOUNCE_ENABLE 0x40
#define GPIO_RTC_BOUNCE_PRE_SCALE 0x44
#define GPIO_RTC_PROTECT_W 0x8E
#define GPIO_RTC_PROTECT_R 0x8F
#define GPIO_RTC_YEAR_W 0x8C
#define GPIO_RTC_YEAR_R 0x8D
#define GPIO_RTC_DAY_W 0x8A
#define GPIO_RTC_DAY_R 0x8B
#define GPIO_RTC_MONTH_W 0x88
#define GPIO_RTC_MONTH_R 0x89
#define GPIO_RTC_DATE_W 0x86
#define GPIO_RTC_DATE_R 0x87
#define GPIO_RTC_HOURS_W 0x84
#define GPIO_RTC_HOURS_R 0x85
#define GPIO_RTC_MINUTES_W 0x82
#define GPIO_RTC_MINUTES_R 0x83
#define GPIO_RTC_SECONDS_W 0x80
#define GPIO_RTC_SECONDS_R 0x81
#define GPIO_RTC_DELAY_TIME 8
struct moxart_rtc {
struct rtc_device *rtc;
spinlock_t rtc_lock;
struct gpio_desc *gpio_data;
struct gpio_desc *gpio_sclk;
struct gpio_desc *gpio_reset;
};
static int day_of_year[12] = { 0, 31, 59, 90, 120, 151, 181,
212, 243, 273, 304, 334 };
static void moxart_rtc_write_byte(struct device *dev, u8 data)
{
struct moxart_rtc *moxart_rtc = dev_get_drvdata(dev);
int i;
for (i = 0; i < 8; i++, data >>= 1) {
gpiod_set_value(moxart_rtc->gpio_sclk, 0);
gpiod_set_value(moxart_rtc->gpio_data, ((data & 1) == 1));
udelay(GPIO_RTC_DELAY_TIME);
gpiod_set_value(moxart_rtc->gpio_sclk, 1);
udelay(GPIO_RTC_DELAY_TIME);
}
}
static u8 moxart_rtc_read_byte(struct device *dev)
{
struct moxart_rtc *moxart_rtc = dev_get_drvdata(dev);
int i;
u8 data = 0;
for (i = 0; i < 8; i++) {
gpiod_set_value(moxart_rtc->gpio_sclk, 0);
udelay(GPIO_RTC_DELAY_TIME);
gpiod_set_value(moxart_rtc->gpio_sclk, 1);
udelay(GPIO_RTC_DELAY_TIME);
if (gpiod_get_value(moxart_rtc->gpio_data))
data |= (1 << i);
udelay(GPIO_RTC_DELAY_TIME);
}
return data;
}
static u8 moxart_rtc_read_register(struct device *dev, u8 cmd)
{
struct moxart_rtc *moxart_rtc = dev_get_drvdata(dev);
u8 data;
unsigned long flags;
local_irq_save(flags);
gpiod_direction_output(moxart_rtc->gpio_data, 0);
gpiod_set_value(moxart_rtc->gpio_reset, 1);
udelay(GPIO_RTC_DELAY_TIME);
moxart_rtc_write_byte(dev, cmd);
gpiod_direction_input(moxart_rtc->gpio_data);
udelay(GPIO_RTC_DELAY_TIME);
data = moxart_rtc_read_byte(dev);
gpiod_set_value(moxart_rtc->gpio_sclk, 0);
gpiod_set_value(moxart_rtc->gpio_reset, 0);
udelay(GPIO_RTC_DELAY_TIME);
local_irq_restore(flags);
return data;
}
static void moxart_rtc_write_register(struct device *dev, u8 cmd, u8 data)
{
struct moxart_rtc *moxart_rtc = dev_get_drvdata(dev);
unsigned long flags;
local_irq_save(flags);
gpiod_direction_output(moxart_rtc->gpio_data, 0);
gpiod_set_value(moxart_rtc->gpio_reset, 1);
udelay(GPIO_RTC_DELAY_TIME);
moxart_rtc_write_byte(dev, cmd);
moxart_rtc_write_byte(dev, data);
gpiod_set_value(moxart_rtc->gpio_sclk, 0);
gpiod_set_value(moxart_rtc->gpio_reset, 0);
udelay(GPIO_RTC_DELAY_TIME);
local_irq_restore(flags);
}
static int moxart_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct moxart_rtc *moxart_rtc = dev_get_drvdata(dev);
spin_lock_irq(&moxart_rtc->rtc_lock);
moxart_rtc_write_register(dev, GPIO_RTC_PROTECT_W, 0);
moxart_rtc_write_register(dev, GPIO_RTC_YEAR_W,
(((tm->tm_year - 100) / 10) << 4) |
((tm->tm_year - 100) % 10));
moxart_rtc_write_register(dev, GPIO_RTC_MONTH_W,
(((tm->tm_mon + 1) / 10) << 4) |
((tm->tm_mon + 1) % 10));
moxart_rtc_write_register(dev, GPIO_RTC_DATE_W,
((tm->tm_mday / 10) << 4) |
(tm->tm_mday % 10));
moxart_rtc_write_register(dev, GPIO_RTC_HOURS_W,
((tm->tm_hour / 10) << 4) |
(tm->tm_hour % 10));
moxart_rtc_write_register(dev, GPIO_RTC_MINUTES_W,
((tm->tm_min / 10) << 4) |
(tm->tm_min % 10));
moxart_rtc_write_register(dev, GPIO_RTC_SECONDS_W,
((tm->tm_sec / 10) << 4) |
(tm->tm_sec % 10));
moxart_rtc_write_register(dev, GPIO_RTC_PROTECT_W, 0x80);
spin_unlock_irq(&moxart_rtc->rtc_lock);
dev_dbg(dev, "%s: success tm_year=%d tm_mon=%d\n"
"tm_mday=%d tm_hour=%d tm_min=%d tm_sec=%d\n",
__func__, tm->tm_year, tm->tm_mon, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
return 0;
}
static int moxart_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct moxart_rtc *moxart_rtc = dev_get_drvdata(dev);
unsigned char v;
spin_lock_irq(&moxart_rtc->rtc_lock);
v = moxart_rtc_read_register(dev, GPIO_RTC_SECONDS_R);
tm->tm_sec = (((v & 0x70) >> 4) * 10) + (v & 0x0F);
v = moxart_rtc_read_register(dev, GPIO_RTC_MINUTES_R);
tm->tm_min = (((v & 0x70) >> 4) * 10) + (v & 0x0F);
v = moxart_rtc_read_register(dev, GPIO_RTC_HOURS_R);
if (v & 0x80) { /* 12-hour mode */
tm->tm_hour = (((v & 0x10) >> 4) * 10) + (v & 0x0F);
if (v & 0x20) { /* PM mode */
tm->tm_hour += 12;
if (tm->tm_hour >= 24)
tm->tm_hour = 0;
}
} else { /* 24-hour mode */
tm->tm_hour = (((v & 0x30) >> 4) * 10) + (v & 0x0F);
}
v = moxart_rtc_read_register(dev, GPIO_RTC_DATE_R);
tm->tm_mday = (((v & 0x30) >> 4) * 10) + (v & 0x0F);
v = moxart_rtc_read_register(dev, GPIO_RTC_MONTH_R);
tm->tm_mon = (((v & 0x10) >> 4) * 10) + (v & 0x0F);
tm->tm_mon--;
v = moxart_rtc_read_register(dev, GPIO_RTC_YEAR_R);
tm->tm_year = (((v & 0xF0) >> 4) * 10) + (v & 0x0F);
tm->tm_year += 100;
if (tm->tm_year <= 69)
tm->tm_year += 100;
v = moxart_rtc_read_register(dev, GPIO_RTC_DAY_R);
tm->tm_wday = (v & 0x0f) - 1;
tm->tm_yday = day_of_year[tm->tm_mon];
tm->tm_yday += (tm->tm_mday - 1);
if (tm->tm_mon >= 2) {
if (!(tm->tm_year % 4) && (tm->tm_year % 100))
tm->tm_yday++;
}
tm->tm_isdst = 0;
spin_unlock_irq(&moxart_rtc->rtc_lock);
return 0;
}
static const struct rtc_class_ops moxart_rtc_ops = {
.read_time = moxart_rtc_read_time,
.set_time = moxart_rtc_set_time,
};
static int moxart_rtc_probe(struct platform_device *pdev)
{
struct moxart_rtc *moxart_rtc;
int ret = 0;
moxart_rtc = devm_kzalloc(&pdev->dev, sizeof(*moxart_rtc), GFP_KERNEL);
if (!moxart_rtc)
return -ENOMEM;
moxart_rtc->gpio_data = devm_gpiod_get(&pdev->dev, "rtc-data",
GPIOD_IN);
ret = PTR_ERR_OR_ZERO(moxart_rtc->gpio_data);
if (ret) {
dev_err(&pdev->dev, "can't get rtc data gpio: %d\n", ret);
return ret;
}
moxart_rtc->gpio_sclk = devm_gpiod_get(&pdev->dev, "rtc-sclk",
GPIOD_ASIS);
ret = PTR_ERR_OR_ZERO(moxart_rtc->gpio_sclk);
if (ret) {
dev_err(&pdev->dev, "can't get rtc sclk gpio: %d\n", ret);
return ret;
}
moxart_rtc->gpio_reset = devm_gpiod_get(&pdev->dev, "rtc-reset",
GPIOD_ASIS);
ret = PTR_ERR_OR_ZERO(moxart_rtc->gpio_reset);
if (ret) {
dev_err(&pdev->dev, "can't get rtc reset gpio: %d\n", ret);
return ret;
}
spin_lock_init(&moxart_rtc->rtc_lock);
platform_set_drvdata(pdev, moxart_rtc);
moxart_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
&moxart_rtc_ops,
THIS_MODULE);
if (IS_ERR(moxart_rtc->rtc)) {
dev_err(&pdev->dev, "devm_rtc_device_register failed\n");
return PTR_ERR(moxart_rtc->rtc);
}
return 0;
}
static const struct of_device_id moxart_rtc_match[] = {
{ .compatible = "moxa,moxart-rtc" },
{ },
};
MODULE_DEVICE_TABLE(of, moxart_rtc_match);
static struct platform_driver moxart_rtc_driver = {
.probe = moxart_rtc_probe,
.driver = {
.name = "moxart-rtc",
.of_match_table = moxart_rtc_match,
},
};
module_platform_driver(moxart_rtc_driver);
MODULE_DESCRIPTION("MOXART RTC driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jonas Jensen <[email protected]>");
| linux-master | drivers/rtc/rtc-moxart.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/rtc/rtc-pl030.c
*
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/io.h>
#include <linux/slab.h>
#define RTC_DR (0)
#define RTC_MR (4)
#define RTC_STAT (8)
#define RTC_EOI (8)
#define RTC_LR (12)
#define RTC_CR (16)
#define RTC_CR_MIE (1 << 0)
struct pl030_rtc {
struct rtc_device *rtc;
void __iomem *base;
};
static irqreturn_t pl030_interrupt(int irq, void *dev_id)
{
struct pl030_rtc *rtc = dev_id;
writel(0, rtc->base + RTC_EOI);
return IRQ_HANDLED;
}
static int pl030_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pl030_rtc *rtc = dev_get_drvdata(dev);
rtc_time64_to_tm(readl(rtc->base + RTC_MR), &alrm->time);
return 0;
}
static int pl030_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pl030_rtc *rtc = dev_get_drvdata(dev);
writel(rtc_tm_to_time64(&alrm->time), rtc->base + RTC_MR);
return 0;
}
static int pl030_read_time(struct device *dev, struct rtc_time *tm)
{
struct pl030_rtc *rtc = dev_get_drvdata(dev);
rtc_time64_to_tm(readl(rtc->base + RTC_DR), tm);
return 0;
}
/*
* Set the RTC time. Unfortunately, we can't accurately set
* the point at which the counter updates.
*
* Also, since RTC_LR is transferred to RTC_CR on next rising
* edge of the 1Hz clock, we must write the time one second
* in advance.
*/
static int pl030_set_time(struct device *dev, struct rtc_time *tm)
{
struct pl030_rtc *rtc = dev_get_drvdata(dev);
writel(rtc_tm_to_time64(tm) + 1, rtc->base + RTC_LR);
return 0;
}
static const struct rtc_class_ops pl030_ops = {
.read_time = pl030_read_time,
.set_time = pl030_set_time,
.read_alarm = pl030_read_alarm,
.set_alarm = pl030_set_alarm,
};
static int pl030_probe(struct amba_device *dev, const struct amba_id *id)
{
struct pl030_rtc *rtc;
int ret;
ret = amba_request_regions(dev, NULL);
if (ret)
goto err_req;
rtc = devm_kzalloc(&dev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc) {
ret = -ENOMEM;
goto err_rtc;
}
rtc->rtc = devm_rtc_allocate_device(&dev->dev);
if (IS_ERR(rtc->rtc)) {
ret = PTR_ERR(rtc->rtc);
goto err_rtc;
}
rtc->rtc->ops = &pl030_ops;
rtc->rtc->range_max = U32_MAX;
rtc->base = ioremap(dev->res.start, resource_size(&dev->res));
if (!rtc->base) {
ret = -ENOMEM;
goto err_rtc;
}
__raw_writel(0, rtc->base + RTC_CR);
__raw_writel(0, rtc->base + RTC_EOI);
amba_set_drvdata(dev, rtc);
ret = request_irq(dev->irq[0], pl030_interrupt, 0,
"rtc-pl030", rtc);
if (ret)
goto err_irq;
ret = devm_rtc_register_device(rtc->rtc);
if (ret)
goto err_reg;
return 0;
err_reg:
free_irq(dev->irq[0], rtc);
err_irq:
iounmap(rtc->base);
err_rtc:
amba_release_regions(dev);
err_req:
return ret;
}
static void pl030_remove(struct amba_device *dev)
{
struct pl030_rtc *rtc = amba_get_drvdata(dev);
writel(0, rtc->base + RTC_CR);
free_irq(dev->irq[0], rtc);
iounmap(rtc->base);
amba_release_regions(dev);
}
static struct amba_id pl030_ids[] = {
{
.id = 0x00041030,
.mask = 0x000fffff,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl030_ids);
static struct amba_driver pl030_driver = {
.drv = {
.name = "rtc-pl030",
},
.probe = pl030_probe,
.remove = pl030_remove,
.id_table = pl030_ids,
};
module_amba_driver(pl030_driver);
MODULE_AUTHOR("Russell King <[email protected]>");
MODULE_DESCRIPTION("ARM AMBA PL030 RTC Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pl030.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* A SPI driver for the Ricoh RS5C348 RTC
*
* Copyright (C) 2006 Atsushi Nemoto <[email protected]>
*
* The board specific init code should provide characteristics of this
* device:
* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS
*/
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#define RS5C348_REG_SECS 0
#define RS5C348_REG_MINS 1
#define RS5C348_REG_HOURS 2
#define RS5C348_REG_WDAY 3
#define RS5C348_REG_DAY 4
#define RS5C348_REG_MONTH 5
#define RS5C348_REG_YEAR 6
#define RS5C348_REG_CTL1 14
#define RS5C348_REG_CTL2 15
#define RS5C348_SECS_MASK 0x7f
#define RS5C348_MINS_MASK 0x7f
#define RS5C348_HOURS_MASK 0x3f
#define RS5C348_WDAY_MASK 0x03
#define RS5C348_DAY_MASK 0x3f
#define RS5C348_MONTH_MASK 0x1f
#define RS5C348_BIT_PM 0x20 /* REG_HOURS */
#define RS5C348_BIT_Y2K 0x80 /* REG_MONTH */
#define RS5C348_BIT_24H 0x20 /* REG_CTL1 */
#define RS5C348_BIT_XSTP 0x10 /* REG_CTL2 */
#define RS5C348_BIT_VDET 0x40 /* REG_CTL2 */
#define RS5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
#define RS5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
#define RS5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
#define RS5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
struct rs5c348_plat_data {
struct rtc_device *rtc;
int rtc_24h;
};
static int
rs5c348_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
u8 txbuf[5+7], *txp;
int ret;
ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
if (ret < 0)
return ret;
if (ret & RS5C348_BIT_XSTP) {
txbuf[0] = RS5C348_CMD_W(RS5C348_REG_CTL2);
txbuf[1] = 0;
ret = spi_write_then_read(spi, txbuf, 2, NULL, 0);
if (ret < 0)
return ret;
}
/* Transfer 5 bytes before writing SEC. This gives 31us for carry. */
txp = txbuf;
txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
txbuf[1] = 0; /* dummy */
txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
txbuf[3] = 0; /* dummy */
txbuf[4] = RS5C348_CMD_MW(RS5C348_REG_SECS); /* cmd, sec, ... */
txp = &txbuf[5];
txp[RS5C348_REG_SECS] = bin2bcd(tm->tm_sec);
txp[RS5C348_REG_MINS] = bin2bcd(tm->tm_min);
if (pdata->rtc_24h) {
txp[RS5C348_REG_HOURS] = bin2bcd(tm->tm_hour);
} else {
/* hour 0 is AM12, noon is PM12 */
txp[RS5C348_REG_HOURS] = bin2bcd((tm->tm_hour + 11) % 12 + 1) |
(tm->tm_hour >= 12 ? RS5C348_BIT_PM : 0);
}
txp[RS5C348_REG_WDAY] = bin2bcd(tm->tm_wday);
txp[RS5C348_REG_DAY] = bin2bcd(tm->tm_mday);
txp[RS5C348_REG_MONTH] = bin2bcd(tm->tm_mon + 1) |
(tm->tm_year >= 100 ? RS5C348_BIT_Y2K : 0);
txp[RS5C348_REG_YEAR] = bin2bcd(tm->tm_year % 100);
/* write in one transfer to avoid data inconsistency */
ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), NULL, 0);
udelay(62); /* Tcsr 62us */
return ret;
}
static int
rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
u8 txbuf[5], rxbuf[7];
int ret;
ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
if (ret < 0)
return ret;
if (ret & RS5C348_BIT_VDET)
dev_warn(&spi->dev, "voltage-low detected.\n");
if (ret & RS5C348_BIT_XSTP) {
dev_warn(&spi->dev, "oscillator-stop detected.\n");
return -EINVAL;
}
/* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
txbuf[1] = 0; /* dummy */
txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
txbuf[3] = 0; /* dummy */
txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */
/* read in one transfer to avoid data inconsistency */
ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
rxbuf, sizeof(rxbuf));
udelay(62); /* Tcsr 62us */
if (ret < 0)
return ret;
tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK);
tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK);
tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK);
if (!pdata->rtc_24h) {
if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) {
tm->tm_hour -= 20;
tm->tm_hour %= 12;
tm->tm_hour += 12;
} else
tm->tm_hour %= 12;
}
tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK);
tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK);
tm->tm_mon =
bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1;
/* year is 1900 + tm->tm_year */
tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) +
((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0);
return 0;
}
static const struct rtc_class_ops rs5c348_rtc_ops = {
.read_time = rs5c348_rtc_read_time,
.set_time = rs5c348_rtc_set_time,
};
static int rs5c348_probe(struct spi_device *spi)
{
int ret;
struct rtc_device *rtc;
struct rs5c348_plat_data *pdata;
pdata = devm_kzalloc(&spi->dev, sizeof(struct rs5c348_plat_data),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
spi->dev.platform_data = pdata;
/* Check D7 of SECOND register */
ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_SECS));
if (ret < 0 || (ret & 0x80)) {
dev_err(&spi->dev, "not found.\n");
return ret;
}
dev_info(&spi->dev, "spiclk %u KHz.\n",
(spi->max_speed_hz + 500) / 1000);
ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL1));
if (ret < 0)
return ret;
if (ret & RS5C348_BIT_24H)
pdata->rtc_24h = 1;
rtc = devm_rtc_allocate_device(&spi->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
pdata->rtc = rtc;
rtc->ops = &rs5c348_rtc_ops;
return devm_rtc_register_device(rtc);
}
static struct spi_driver rs5c348_driver = {
.driver = {
.name = "rtc-rs5c348",
},
.probe = rs5c348_probe,
};
module_spi_driver(rs5c348_driver);
MODULE_AUTHOR("Atsushi Nemoto <[email protected]>");
MODULE_DESCRIPTION("Ricoh RS5C348 RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rtc-rs5c348");
| linux-master | drivers/rtc/rtc-rs5c348.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* PIC32 RTC driver
*
* Joshua Henderson <[email protected]>
* Copyright (C) 2016 Microchip Technology Inc. All rights reserved.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <asm/mach-pic32/pic32.h>
#define PIC32_RTCCON 0x00
#define PIC32_RTCCON_ON BIT(15)
#define PIC32_RTCCON_SIDL BIT(13)
#define PIC32_RTCCON_RTCCLKSEL (3 << 9)
#define PIC32_RTCCON_RTCCLKON BIT(6)
#define PIC32_RTCCON_RTCWREN BIT(3)
#define PIC32_RTCCON_RTCSYNC BIT(2)
#define PIC32_RTCCON_HALFSEC BIT(1)
#define PIC32_RTCCON_RTCOE BIT(0)
#define PIC32_RTCALRM 0x10
#define PIC32_RTCALRM_ALRMEN BIT(15)
#define PIC32_RTCALRM_CHIME BIT(14)
#define PIC32_RTCALRM_PIV BIT(13)
#define PIC32_RTCALRM_ALARMSYNC BIT(12)
#define PIC32_RTCALRM_AMASK 0x0F00
#define PIC32_RTCALRM_ARPT 0xFF
#define PIC32_RTCHOUR 0x23
#define PIC32_RTCMIN 0x22
#define PIC32_RTCSEC 0x21
#define PIC32_RTCYEAR 0x33
#define PIC32_RTCMON 0x32
#define PIC32_RTCDAY 0x31
#define PIC32_ALRMTIME 0x40
#define PIC32_ALRMDATE 0x50
#define PIC32_ALRMHOUR 0x43
#define PIC32_ALRMMIN 0x42
#define PIC32_ALRMSEC 0x41
#define PIC32_ALRMYEAR 0x53
#define PIC32_ALRMMON 0x52
#define PIC32_ALRMDAY 0x51
struct pic32_rtc_dev {
struct rtc_device *rtc;
void __iomem *reg_base;
struct clk *clk;
spinlock_t alarm_lock;
int alarm_irq;
bool alarm_clk_enabled;
};
static void pic32_rtc_alarm_clk_enable(struct pic32_rtc_dev *pdata,
bool enable)
{
unsigned long flags;
spin_lock_irqsave(&pdata->alarm_lock, flags);
if (enable) {
if (!pdata->alarm_clk_enabled) {
clk_enable(pdata->clk);
pdata->alarm_clk_enabled = true;
}
} else {
if (pdata->alarm_clk_enabled) {
clk_disable(pdata->clk);
pdata->alarm_clk_enabled = false;
}
}
spin_unlock_irqrestore(&pdata->alarm_lock, flags);
}
static irqreturn_t pic32_rtc_alarmirq(int irq, void *id)
{
struct pic32_rtc_dev *pdata = (struct pic32_rtc_dev *)id;
clk_enable(pdata->clk);
rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
clk_disable(pdata->clk);
pic32_rtc_alarm_clk_enable(pdata, false);
return IRQ_HANDLED;
}
static int pic32_rtc_setaie(struct device *dev, unsigned int enabled)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
void __iomem *base = pdata->reg_base;
clk_enable(pdata->clk);
writel(PIC32_RTCALRM_ALRMEN,
base + (enabled ? PIC32_SET(PIC32_RTCALRM) :
PIC32_CLR(PIC32_RTCALRM)));
clk_disable(pdata->clk);
pic32_rtc_alarm_clk_enable(pdata, enabled);
return 0;
}
static int pic32_rtc_setfreq(struct device *dev, int freq)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
void __iomem *base = pdata->reg_base;
clk_enable(pdata->clk);
writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM));
writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM));
writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM));
clk_disable(pdata->clk);
return 0;
}
static int pic32_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
void __iomem *base = pdata->reg_base;
unsigned int tries = 0;
clk_enable(pdata->clk);
do {
rtc_tm->tm_hour = readb(base + PIC32_RTCHOUR);
rtc_tm->tm_min = readb(base + PIC32_RTCMIN);
rtc_tm->tm_mon = readb(base + PIC32_RTCMON);
rtc_tm->tm_mday = readb(base + PIC32_RTCDAY);
rtc_tm->tm_year = readb(base + PIC32_RTCYEAR);
rtc_tm->tm_sec = readb(base + PIC32_RTCSEC);
/*
* The only way to work out whether the system was mid-update
* when we read it is to check the second counter, and if it
* is zero, then we re-try the entire read.
*/
tries += 1;
} while (rtc_tm->tm_sec == 0 && tries < 2);
rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon) - 1;
rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
rtc_tm->tm_year += 100;
dev_dbg(dev, "read time %ptR\n", rtc_tm);
clk_disable(pdata->clk);
return 0;
}
static int pic32_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
void __iomem *base = pdata->reg_base;
dev_dbg(dev, "set time %ptR\n", tm);
clk_enable(pdata->clk);
writeb(bin2bcd(tm->tm_sec), base + PIC32_RTCSEC);
writeb(bin2bcd(tm->tm_min), base + PIC32_RTCMIN);
writeb(bin2bcd(tm->tm_hour), base + PIC32_RTCHOUR);
writeb(bin2bcd(tm->tm_mday), base + PIC32_RTCDAY);
writeb(bin2bcd(tm->tm_mon + 1), base + PIC32_RTCMON);
writeb(bin2bcd(tm->tm_year - 100), base + PIC32_RTCYEAR);
clk_disable(pdata->clk);
return 0;
}
static int pic32_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
struct rtc_time *alm_tm = &alrm->time;
void __iomem *base = pdata->reg_base;
unsigned int alm_en;
clk_enable(pdata->clk);
alm_tm->tm_sec = readb(base + PIC32_ALRMSEC);
alm_tm->tm_min = readb(base + PIC32_ALRMMIN);
alm_tm->tm_hour = readb(base + PIC32_ALRMHOUR);
alm_tm->tm_mon = readb(base + PIC32_ALRMMON);
alm_tm->tm_mday = readb(base + PIC32_ALRMDAY);
alm_tm->tm_year = readb(base + PIC32_ALRMYEAR);
alm_en = readb(base + PIC32_RTCALRM);
alrm->enabled = (alm_en & PIC32_RTCALRM_ALRMEN) ? 1 : 0;
dev_dbg(dev, "getalarm: %d, %ptR\n", alm_en, alm_tm);
alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon) - 1;
alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
clk_disable(pdata->clk);
return 0;
}
static int pic32_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
void __iomem *base = pdata->reg_base;
clk_enable(pdata->clk);
dev_dbg(dev, "setalarm: %d, %ptR\n", alrm->enabled, tm);
writel(0x00, base + PIC32_ALRMTIME);
writel(0x00, base + PIC32_ALRMDATE);
pic32_rtc_setaie(dev, alrm->enabled);
clk_disable(pdata->clk);
return 0;
}
static int pic32_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
void __iomem *base = pdata->reg_base;
unsigned int repeat;
clk_enable(pdata->clk);
repeat = readw(base + PIC32_RTCALRM);
repeat &= PIC32_RTCALRM_ARPT;
seq_printf(seq, "periodic_IRQ\t: %s\n", repeat ? "yes" : "no");
clk_disable(pdata->clk);
return 0;
}
static const struct rtc_class_ops pic32_rtcops = {
.read_time = pic32_rtc_gettime,
.set_time = pic32_rtc_settime,
.read_alarm = pic32_rtc_getalarm,
.set_alarm = pic32_rtc_setalarm,
.proc = pic32_rtc_proc,
.alarm_irq_enable = pic32_rtc_setaie,
};
static void pic32_rtc_enable(struct pic32_rtc_dev *pdata, int en)
{
void __iomem *base = pdata->reg_base;
if (!base)
return;
clk_enable(pdata->clk);
if (!en) {
writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON));
} else {
pic32_syskey_unlock();
writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON));
writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON));
if (!(readl(base + PIC32_RTCCON) & PIC32_RTCCON_ON))
writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON));
}
clk_disable(pdata->clk);
}
static void pic32_rtc_remove(struct platform_device *pdev)
{
struct pic32_rtc_dev *pdata = platform_get_drvdata(pdev);
pic32_rtc_setaie(&pdev->dev, 0);
clk_unprepare(pdata->clk);
pdata->clk = NULL;
}
static int pic32_rtc_probe(struct platform_device *pdev)
{
struct pic32_rtc_dev *pdata;
int ret;
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
platform_set_drvdata(pdev, pdata);
pdata->alarm_irq = platform_get_irq(pdev, 0);
if (pdata->alarm_irq < 0)
return pdata->alarm_irq;
pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdata->reg_base))
return PTR_ERR(pdata->reg_base);
pdata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pdata->clk)) {
dev_err(&pdev->dev, "failed to find rtc clock source\n");
ret = PTR_ERR(pdata->clk);
pdata->clk = NULL;
return ret;
}
spin_lock_init(&pdata->alarm_lock);
pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pdata->rtc))
return PTR_ERR(pdata->rtc);
clk_prepare_enable(pdata->clk);
pic32_rtc_enable(pdata, 1);
device_init_wakeup(&pdev->dev, 1);
pdata->rtc->ops = &pic32_rtcops;
pdata->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
pdata->rtc->range_max = RTC_TIMESTAMP_END_2099;
ret = devm_rtc_register_device(pdata->rtc);
if (ret)
goto err_nortc;
pdata->rtc->max_user_freq = 128;
pic32_rtc_setfreq(&pdev->dev, 1);
ret = devm_request_irq(&pdev->dev, pdata->alarm_irq,
pic32_rtc_alarmirq, 0,
dev_name(&pdev->dev), pdata);
if (ret) {
dev_err(&pdev->dev,
"IRQ %d error %d\n", pdata->alarm_irq, ret);
goto err_nortc;
}
clk_disable(pdata->clk);
return 0;
err_nortc:
pic32_rtc_enable(pdata, 0);
clk_disable_unprepare(pdata->clk);
return ret;
}
static const struct of_device_id pic32_rtc_dt_ids[] = {
{ .compatible = "microchip,pic32mzda-rtc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pic32_rtc_dt_ids);
static struct platform_driver pic32_rtc_driver = {
.probe = pic32_rtc_probe,
.remove_new = pic32_rtc_remove,
.driver = {
.name = "pic32-rtc",
.of_match_table = of_match_ptr(pic32_rtc_dt_ids),
},
};
module_platform_driver(pic32_rtc_driver);
MODULE_DESCRIPTION("Microchip PIC32 RTC Driver");
MODULE_AUTHOR("Joshua Henderson <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pic32.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Intersil ISL1208 rtc class driver
*
* Copyright 2005,2006 Hebert Valerio Riedel <[email protected]>
*/
#include <linux/bcd.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/rtc.h>
/* Register map */
/* rtc section */
#define ISL1208_REG_SC 0x00
#define ISL1208_REG_MN 0x01
#define ISL1208_REG_HR 0x02
#define ISL1208_REG_HR_MIL (1<<7) /* 24h/12h mode */
#define ISL1208_REG_HR_PM (1<<5) /* PM/AM bit in 12h mode */
#define ISL1208_REG_DT 0x03
#define ISL1208_REG_MO 0x04
#define ISL1208_REG_YR 0x05
#define ISL1208_REG_DW 0x06
#define ISL1208_RTC_SECTION_LEN 7
/* control/status section */
#define ISL1208_REG_SR 0x07
#define ISL1208_REG_SR_ARST (1<<7) /* auto reset */
#define ISL1208_REG_SR_XTOSCB (1<<6) /* crystal oscillator */
#define ISL1208_REG_SR_WRTC (1<<4) /* write rtc */
#define ISL1208_REG_SR_EVT (1<<3) /* event */
#define ISL1208_REG_SR_ALM (1<<2) /* alarm */
#define ISL1208_REG_SR_BAT (1<<1) /* battery */
#define ISL1208_REG_SR_RTCF (1<<0) /* rtc fail */
#define ISL1208_REG_INT 0x08
#define ISL1208_REG_INT_ALME (1<<6) /* alarm enable */
#define ISL1208_REG_INT_IM (1<<7) /* interrupt/alarm mode */
#define ISL1219_REG_EV 0x09
#define ISL1219_REG_EV_EVEN (1<<4) /* event detection enable */
#define ISL1219_REG_EV_EVIENB (1<<7) /* event in pull-up disable */
#define ISL1208_REG_ATR 0x0a
#define ISL1208_REG_DTR 0x0b
/* alarm section */
#define ISL1208_REG_SCA 0x0c
#define ISL1208_REG_MNA 0x0d
#define ISL1208_REG_HRA 0x0e
#define ISL1208_REG_DTA 0x0f
#define ISL1208_REG_MOA 0x10
#define ISL1208_REG_DWA 0x11
#define ISL1208_ALARM_SECTION_LEN 6
/* user section */
#define ISL1208_REG_USR1 0x12
#define ISL1208_REG_USR2 0x13
#define ISL1208_USR_SECTION_LEN 2
/* event section */
#define ISL1219_REG_SCT 0x14
#define ISL1219_REG_MNT 0x15
#define ISL1219_REG_HRT 0x16
#define ISL1219_REG_DTT 0x17
#define ISL1219_REG_MOT 0x18
#define ISL1219_REG_YRT 0x19
#define ISL1219_EVT_SECTION_LEN 6
static struct i2c_driver isl1208_driver;
/* Chip capabilities table */
struct isl1208_config {
unsigned int nvmem_length;
unsigned has_tamper:1;
unsigned has_timestamp:1;
unsigned has_inverted_osc_bit:1;
};
static const struct isl1208_config config_isl1208 = {
.nvmem_length = 2,
.has_tamper = false,
.has_timestamp = false
};
static const struct isl1208_config config_isl1209 = {
.nvmem_length = 2,
.has_tamper = true,
.has_timestamp = false
};
static const struct isl1208_config config_isl1218 = {
.nvmem_length = 8,
.has_tamper = false,
.has_timestamp = false
};
static const struct isl1208_config config_isl1219 = {
.nvmem_length = 2,
.has_tamper = true,
.has_timestamp = true
};
static const struct isl1208_config config_raa215300_a0 = {
.nvmem_length = 2,
.has_tamper = false,
.has_timestamp = false,
.has_inverted_osc_bit = true
};
static const struct i2c_device_id isl1208_id[] = {
{ "isl1208", .driver_data = (kernel_ulong_t)&config_isl1208 },
{ "isl1209", .driver_data = (kernel_ulong_t)&config_isl1209 },
{ "isl1218", .driver_data = (kernel_ulong_t)&config_isl1218 },
{ "isl1219", .driver_data = (kernel_ulong_t)&config_isl1219 },
{ "raa215300_a0", .driver_data = (kernel_ulong_t)&config_raa215300_a0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, isl1208_id);
static const __maybe_unused struct of_device_id isl1208_of_match[] = {
{ .compatible = "isil,isl1208", .data = &config_isl1208 },
{ .compatible = "isil,isl1209", .data = &config_isl1209 },
{ .compatible = "isil,isl1218", .data = &config_isl1218 },
{ .compatible = "isil,isl1219", .data = &config_isl1219 },
{ }
};
MODULE_DEVICE_TABLE(of, isl1208_of_match);
/* Device state */
struct isl1208_state {
struct nvmem_config nvmem_config;
struct rtc_device *rtc;
const struct isl1208_config *config;
};
/* block read */
static int
isl1208_i2c_read_regs(struct i2c_client *client, u8 reg, u8 buf[],
unsigned len)
{
int ret;
WARN_ON(reg > ISL1219_REG_YRT);
WARN_ON(reg + len > ISL1219_REG_YRT + 1);
ret = i2c_smbus_read_i2c_block_data(client, reg, len, buf);
return (ret < 0) ? ret : 0;
}
/* block write */
static int
isl1208_i2c_set_regs(struct i2c_client *client, u8 reg, u8 const buf[],
unsigned len)
{
int ret;
WARN_ON(reg > ISL1219_REG_YRT);
WARN_ON(reg + len > ISL1219_REG_YRT + 1);
ret = i2c_smbus_write_i2c_block_data(client, reg, len, buf);
return (ret < 0) ? ret : 0;
}
/* simple check to see whether we have a isl1208 */
static int
isl1208_i2c_validate_client(struct i2c_client *client)
{
u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, };
u8 zero_mask[ISL1208_RTC_SECTION_LEN] = {
0x80, 0x80, 0x40, 0xc0, 0xe0, 0x00, 0xf8
};
int i;
int ret;
ret = isl1208_i2c_read_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN);
if (ret < 0)
return ret;
for (i = 0; i < ISL1208_RTC_SECTION_LEN; ++i) {
if (regs[i] & zero_mask[i]) /* check if bits are cleared */
return -ENODEV;
}
return 0;
}
static int isl1208_set_xtoscb(struct i2c_client *client, int sr, int xtosb_val)
{
/* Do nothing if bit is already set to desired value */
if (!!(sr & ISL1208_REG_SR_XTOSCB) == xtosb_val)
return 0;
if (xtosb_val)
sr |= ISL1208_REG_SR_XTOSCB;
else
sr &= ~ISL1208_REG_SR_XTOSCB;
return i2c_smbus_write_byte_data(client, ISL1208_REG_SR, sr);
}
static int
isl1208_i2c_get_sr(struct i2c_client *client)
{
return i2c_smbus_read_byte_data(client, ISL1208_REG_SR);
}
static int
isl1208_i2c_get_atr(struct i2c_client *client)
{
int atr = i2c_smbus_read_byte_data(client, ISL1208_REG_ATR);
if (atr < 0)
return atr;
/* The 6bit value in the ATR register controls the load
* capacitance C_load * in steps of 0.25pF
*
* bit (1<<5) of the ATR register is inverted
*
* C_load(ATR=0x20) = 4.50pF
* C_load(ATR=0x00) = 12.50pF
* C_load(ATR=0x1f) = 20.25pF
*
*/
atr &= 0x3f; /* mask out lsb */
atr ^= 1 << 5; /* invert 6th bit */
atr += 2 * 9; /* add offset of 4.5pF; unit[atr] = 0.25pF */
return atr;
}
/* returns adjustment value + 100 */
static int
isl1208_i2c_get_dtr(struct i2c_client *client)
{
int dtr = i2c_smbus_read_byte_data(client, ISL1208_REG_DTR);
if (dtr < 0)
return -EIO;
/* dtr encodes adjustments of {-60,-40,-20,0,20,40,60} ppm */
dtr = ((dtr & 0x3) * 20) * (dtr & (1 << 2) ? -1 : 1);
return dtr + 100;
}
static int
isl1208_i2c_get_usr(struct i2c_client *client)
{
u8 buf[ISL1208_USR_SECTION_LEN] = { 0, };
int ret;
ret = isl1208_i2c_read_regs(client, ISL1208_REG_USR1, buf,
ISL1208_USR_SECTION_LEN);
if (ret < 0)
return ret;
return (buf[1] << 8) | buf[0];
}
static int
isl1208_i2c_set_usr(struct i2c_client *client, u16 usr)
{
u8 buf[ISL1208_USR_SECTION_LEN];
buf[0] = usr & 0xff;
buf[1] = (usr >> 8) & 0xff;
return isl1208_i2c_set_regs(client, ISL1208_REG_USR1, buf,
ISL1208_USR_SECTION_LEN);
}
static int
isl1208_rtc_toggle_alarm(struct i2c_client *client, int enable)
{
int icr = i2c_smbus_read_byte_data(client, ISL1208_REG_INT);
if (icr < 0) {
dev_err(&client->dev, "%s: reading INT failed\n", __func__);
return icr;
}
if (enable)
icr |= ISL1208_REG_INT_ALME | ISL1208_REG_INT_IM;
else
icr &= ~(ISL1208_REG_INT_ALME | ISL1208_REG_INT_IM);
icr = i2c_smbus_write_byte_data(client, ISL1208_REG_INT, icr);
if (icr < 0) {
dev_err(&client->dev, "%s: writing INT failed\n", __func__);
return icr;
}
return 0;
}
static int
isl1208_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct i2c_client *const client = to_i2c_client(dev);
int sr, dtr, atr, usr;
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(&client->dev, "%s: reading SR failed\n", __func__);
return sr;
}
seq_printf(seq, "status_reg\t:%s%s%s%s%s%s (0x%.2x)\n",
(sr & ISL1208_REG_SR_RTCF) ? " RTCF" : "",
(sr & ISL1208_REG_SR_BAT) ? " BAT" : "",
(sr & ISL1208_REG_SR_ALM) ? " ALM" : "",
(sr & ISL1208_REG_SR_WRTC) ? " WRTC" : "",
(sr & ISL1208_REG_SR_XTOSCB) ? " XTOSCB" : "",
(sr & ISL1208_REG_SR_ARST) ? " ARST" : "", sr);
seq_printf(seq, "batt_status\t: %s\n",
(sr & ISL1208_REG_SR_RTCF) ? "bad" : "okay");
dtr = isl1208_i2c_get_dtr(client);
if (dtr >= 0)
seq_printf(seq, "digital_trim\t: %d ppm\n", dtr - 100);
atr = isl1208_i2c_get_atr(client);
if (atr >= 0)
seq_printf(seq, "analog_trim\t: %d.%.2d pF\n",
atr >> 2, (atr & 0x3) * 25);
usr = isl1208_i2c_get_usr(client);
if (usr >= 0)
seq_printf(seq, "user_data\t: 0x%.4x\n", usr);
return 0;
}
static int
isl1208_i2c_read_time(struct i2c_client *client, struct rtc_time *tm)
{
int sr;
u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, };
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(&client->dev, "%s: reading SR failed\n", __func__);
return -EIO;
}
sr = isl1208_i2c_read_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN);
if (sr < 0) {
dev_err(&client->dev, "%s: reading RTC section failed\n",
__func__);
return sr;
}
tm->tm_sec = bcd2bin(regs[ISL1208_REG_SC]);
tm->tm_min = bcd2bin(regs[ISL1208_REG_MN]);
/* HR field has a more complex interpretation */
{
const u8 _hr = regs[ISL1208_REG_HR];
if (_hr & ISL1208_REG_HR_MIL) /* 24h format */
tm->tm_hour = bcd2bin(_hr & 0x3f);
else {
/* 12h format */
tm->tm_hour = bcd2bin(_hr & 0x1f);
if (_hr & ISL1208_REG_HR_PM) /* PM flag set */
tm->tm_hour += 12;
}
}
tm->tm_mday = bcd2bin(regs[ISL1208_REG_DT]);
tm->tm_mon = bcd2bin(regs[ISL1208_REG_MO]) - 1; /* rtc starts at 1 */
tm->tm_year = bcd2bin(regs[ISL1208_REG_YR]) + 100;
tm->tm_wday = bcd2bin(regs[ISL1208_REG_DW]);
return 0;
}
static int
isl1208_i2c_read_alarm(struct i2c_client *client, struct rtc_wkalrm *alarm)
{
struct rtc_time *const tm = &alarm->time;
u8 regs[ISL1208_ALARM_SECTION_LEN] = { 0, };
int icr, yr, sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(&client->dev, "%s: reading SR failed\n", __func__);
return sr;
}
sr = isl1208_i2c_read_regs(client, ISL1208_REG_SCA, regs,
ISL1208_ALARM_SECTION_LEN);
if (sr < 0) {
dev_err(&client->dev, "%s: reading alarm section failed\n",
__func__);
return sr;
}
/* MSB of each alarm register is an enable bit */
tm->tm_sec = bcd2bin(regs[ISL1208_REG_SCA - ISL1208_REG_SCA] & 0x7f);
tm->tm_min = bcd2bin(regs[ISL1208_REG_MNA - ISL1208_REG_SCA] & 0x7f);
tm->tm_hour = bcd2bin(regs[ISL1208_REG_HRA - ISL1208_REG_SCA] & 0x3f);
tm->tm_mday = bcd2bin(regs[ISL1208_REG_DTA - ISL1208_REG_SCA] & 0x3f);
tm->tm_mon =
bcd2bin(regs[ISL1208_REG_MOA - ISL1208_REG_SCA] & 0x1f) - 1;
tm->tm_wday = bcd2bin(regs[ISL1208_REG_DWA - ISL1208_REG_SCA] & 0x03);
/* The alarm doesn't store the year so get it from the rtc section */
yr = i2c_smbus_read_byte_data(client, ISL1208_REG_YR);
if (yr < 0) {
dev_err(&client->dev, "%s: reading RTC YR failed\n", __func__);
return yr;
}
tm->tm_year = bcd2bin(yr) + 100;
icr = i2c_smbus_read_byte_data(client, ISL1208_REG_INT);
if (icr < 0) {
dev_err(&client->dev, "%s: reading INT failed\n", __func__);
return icr;
}
alarm->enabled = !!(icr & ISL1208_REG_INT_ALME);
return 0;
}
static int
isl1208_i2c_set_alarm(struct i2c_client *client, struct rtc_wkalrm *alarm)
{
struct rtc_time *alarm_tm = &alarm->time;
u8 regs[ISL1208_ALARM_SECTION_LEN] = { 0, };
const int offs = ISL1208_REG_SCA;
struct rtc_time rtc_tm;
int err, enable;
err = isl1208_i2c_read_time(client, &rtc_tm);
if (err)
return err;
/* If the alarm time is before the current time disable the alarm */
if (!alarm->enabled || rtc_tm_sub(alarm_tm, &rtc_tm) <= 0)
enable = 0x00;
else
enable = 0x80;
/* Program the alarm and enable it for each setting */
regs[ISL1208_REG_SCA - offs] = bin2bcd(alarm_tm->tm_sec) | enable;
regs[ISL1208_REG_MNA - offs] = bin2bcd(alarm_tm->tm_min) | enable;
regs[ISL1208_REG_HRA - offs] = bin2bcd(alarm_tm->tm_hour) |
ISL1208_REG_HR_MIL | enable;
regs[ISL1208_REG_DTA - offs] = bin2bcd(alarm_tm->tm_mday) | enable;
regs[ISL1208_REG_MOA - offs] = bin2bcd(alarm_tm->tm_mon + 1) | enable;
regs[ISL1208_REG_DWA - offs] = bin2bcd(alarm_tm->tm_wday & 7) | enable;
/* write ALARM registers */
err = isl1208_i2c_set_regs(client, offs, regs,
ISL1208_ALARM_SECTION_LEN);
if (err < 0) {
dev_err(&client->dev, "%s: writing ALARM section failed\n",
__func__);
return err;
}
err = isl1208_rtc_toggle_alarm(client, enable);
if (err)
return err;
return 0;
}
static int
isl1208_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
return isl1208_i2c_read_time(to_i2c_client(dev), tm);
}
static int
isl1208_i2c_set_time(struct i2c_client *client, struct rtc_time const *tm)
{
int sr;
u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, };
/* The clock has an 8 bit wide bcd-coded register (they never learn)
* for the year. tm_year is an offset from 1900 and we are interested
* in the 2000-2099 range, so any value less than 100 is invalid.
*/
if (tm->tm_year < 100)
return -EINVAL;
regs[ISL1208_REG_SC] = bin2bcd(tm->tm_sec);
regs[ISL1208_REG_MN] = bin2bcd(tm->tm_min);
regs[ISL1208_REG_HR] = bin2bcd(tm->tm_hour) | ISL1208_REG_HR_MIL;
regs[ISL1208_REG_DT] = bin2bcd(tm->tm_mday);
regs[ISL1208_REG_MO] = bin2bcd(tm->tm_mon + 1);
regs[ISL1208_REG_YR] = bin2bcd(tm->tm_year - 100);
regs[ISL1208_REG_DW] = bin2bcd(tm->tm_wday & 7);
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(&client->dev, "%s: reading SR failed\n", __func__);
return sr;
}
/* set WRTC */
sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR,
sr | ISL1208_REG_SR_WRTC);
if (sr < 0) {
dev_err(&client->dev, "%s: writing SR failed\n", __func__);
return sr;
}
/* write RTC registers */
sr = isl1208_i2c_set_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN);
if (sr < 0) {
dev_err(&client->dev, "%s: writing RTC section failed\n",
__func__);
return sr;
}
/* clear WRTC again */
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(&client->dev, "%s: reading SR failed\n", __func__);
return sr;
}
sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR,
sr & ~ISL1208_REG_SR_WRTC);
if (sr < 0) {
dev_err(&client->dev, "%s: writing SR failed\n", __func__);
return sr;
}
return 0;
}
static int
isl1208_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
return isl1208_i2c_set_time(to_i2c_client(dev), tm);
}
static int
isl1208_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
return isl1208_i2c_read_alarm(to_i2c_client(dev), alarm);
}
static int
isl1208_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
return isl1208_i2c_set_alarm(to_i2c_client(dev), alarm);
}
static ssize_t timestamp0_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct i2c_client *client = to_i2c_client(dev->parent);
int sr;
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(dev, "%s: reading SR failed\n", __func__);
return sr;
}
sr &= ~ISL1208_REG_SR_EVT;
sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR, sr);
if (sr < 0)
dev_err(dev, "%s: writing SR failed\n",
__func__);
return count;
};
static ssize_t timestamp0_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct i2c_client *client = to_i2c_client(dev->parent);
u8 regs[ISL1219_EVT_SECTION_LEN] = { 0, };
struct rtc_time tm;
int sr;
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(dev, "%s: reading SR failed\n", __func__);
return sr;
}
if (!(sr & ISL1208_REG_SR_EVT))
return 0;
sr = isl1208_i2c_read_regs(client, ISL1219_REG_SCT, regs,
ISL1219_EVT_SECTION_LEN);
if (sr < 0) {
dev_err(dev, "%s: reading event section failed\n",
__func__);
return 0;
}
/* MSB of each alarm register is an enable bit */
tm.tm_sec = bcd2bin(regs[ISL1219_REG_SCT - ISL1219_REG_SCT] & 0x7f);
tm.tm_min = bcd2bin(regs[ISL1219_REG_MNT - ISL1219_REG_SCT] & 0x7f);
tm.tm_hour = bcd2bin(regs[ISL1219_REG_HRT - ISL1219_REG_SCT] & 0x3f);
tm.tm_mday = bcd2bin(regs[ISL1219_REG_DTT - ISL1219_REG_SCT] & 0x3f);
tm.tm_mon =
bcd2bin(regs[ISL1219_REG_MOT - ISL1219_REG_SCT] & 0x1f) - 1;
tm.tm_year = bcd2bin(regs[ISL1219_REG_YRT - ISL1219_REG_SCT]) + 100;
sr = rtc_valid_tm(&tm);
if (sr)
return sr;
return sprintf(buf, "%llu\n",
(unsigned long long)rtc_tm_to_time64(&tm));
};
static DEVICE_ATTR_RW(timestamp0);
static irqreturn_t
isl1208_rtc_interrupt(int irq, void *data)
{
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
struct i2c_client *client = data;
struct isl1208_state *isl1208 = i2c_get_clientdata(client);
int handled = 0, sr, err;
/*
* I2C reads get NAK'ed if we read straight away after an interrupt?
* Using a mdelay/msleep didn't seem to help either, so we work around
* this by continually trying to read the register for a short time.
*/
while (1) {
sr = isl1208_i2c_get_sr(client);
if (sr >= 0)
break;
if (time_after(jiffies, timeout)) {
dev_err(&client->dev, "%s: reading SR failed\n",
__func__);
return sr;
}
}
if (sr & ISL1208_REG_SR_ALM) {
dev_dbg(&client->dev, "alarm!\n");
rtc_update_irq(isl1208->rtc, 1, RTC_IRQF | RTC_AF);
/* Clear the alarm */
sr &= ~ISL1208_REG_SR_ALM;
sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR, sr);
if (sr < 0)
dev_err(&client->dev, "%s: writing SR failed\n",
__func__);
else
handled = 1;
/* Disable the alarm */
err = isl1208_rtc_toggle_alarm(client, 0);
if (err)
return err;
}
if (isl1208->config->has_tamper && (sr & ISL1208_REG_SR_EVT)) {
dev_warn(&client->dev, "event detected");
handled = 1;
if (isl1208->config->has_timestamp)
sysfs_notify(&isl1208->rtc->dev.kobj, NULL,
dev_attr_timestamp0.attr.name);
}
return handled ? IRQ_HANDLED : IRQ_NONE;
}
static const struct rtc_class_ops isl1208_rtc_ops = {
.proc = isl1208_rtc_proc,
.read_time = isl1208_rtc_read_time,
.set_time = isl1208_rtc_set_time,
.read_alarm = isl1208_rtc_read_alarm,
.set_alarm = isl1208_rtc_set_alarm,
};
/* sysfs interface */
static ssize_t
isl1208_sysfs_show_atrim(struct device *dev,
struct device_attribute *attr, char *buf)
{
int atr = isl1208_i2c_get_atr(to_i2c_client(dev->parent));
if (atr < 0)
return atr;
return sprintf(buf, "%d.%.2d pF\n", atr >> 2, (atr & 0x3) * 25);
}
static DEVICE_ATTR(atrim, S_IRUGO, isl1208_sysfs_show_atrim, NULL);
static ssize_t
isl1208_sysfs_show_dtrim(struct device *dev,
struct device_attribute *attr, char *buf)
{
int dtr = isl1208_i2c_get_dtr(to_i2c_client(dev->parent));
if (dtr < 0)
return dtr;
return sprintf(buf, "%d ppm\n", dtr - 100);
}
static DEVICE_ATTR(dtrim, S_IRUGO, isl1208_sysfs_show_dtrim, NULL);
static ssize_t
isl1208_sysfs_show_usr(struct device *dev,
struct device_attribute *attr, char *buf)
{
int usr = isl1208_i2c_get_usr(to_i2c_client(dev->parent));
if (usr < 0)
return usr;
return sprintf(buf, "0x%.4x\n", usr);
}
static ssize_t
isl1208_sysfs_store_usr(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int usr = -1;
if (buf[0] == '0' && (buf[1] == 'x' || buf[1] == 'X')) {
if (sscanf(buf, "%x", &usr) != 1)
return -EINVAL;
} else {
if (sscanf(buf, "%d", &usr) != 1)
return -EINVAL;
}
if (usr < 0 || usr > 0xffff)
return -EINVAL;
if (isl1208_i2c_set_usr(to_i2c_client(dev->parent), usr))
return -EIO;
return count;
}
static DEVICE_ATTR(usr, S_IRUGO | S_IWUSR, isl1208_sysfs_show_usr,
isl1208_sysfs_store_usr);
static struct attribute *isl1208_rtc_attrs[] = {
&dev_attr_atrim.attr,
&dev_attr_dtrim.attr,
&dev_attr_usr.attr,
NULL
};
static const struct attribute_group isl1208_rtc_sysfs_files = {
.attrs = isl1208_rtc_attrs,
};
static struct attribute *isl1219_rtc_attrs[] = {
&dev_attr_timestamp0.attr,
NULL
};
static const struct attribute_group isl1219_rtc_sysfs_files = {
.attrs = isl1219_rtc_attrs,
};
static int isl1208_nvmem_read(void *priv, unsigned int off, void *buf,
size_t count)
{
struct isl1208_state *isl1208 = priv;
struct i2c_client *client = to_i2c_client(isl1208->rtc->dev.parent);
int ret;
/* nvmem sanitizes offset/count for us, but count==0 is possible */
if (!count)
return count;
ret = isl1208_i2c_read_regs(client, ISL1208_REG_USR1 + off, buf,
count);
return ret == 0 ? count : ret;
}
static int isl1208_nvmem_write(void *priv, unsigned int off, void *buf,
size_t count)
{
struct isl1208_state *isl1208 = priv;
struct i2c_client *client = to_i2c_client(isl1208->rtc->dev.parent);
int ret;
/* nvmem sanitizes off/count for us, but count==0 is possible */
if (!count)
return count;
ret = isl1208_i2c_set_regs(client, ISL1208_REG_USR1 + off, buf,
count);
return ret == 0 ? count : ret;
}
static const struct nvmem_config isl1208_nvmem_config = {
.name = "isl1208_nvram",
.word_size = 1,
.stride = 1,
/* .size from chip specific config */
.reg_read = isl1208_nvmem_read,
.reg_write = isl1208_nvmem_write,
};
static int isl1208_setup_irq(struct i2c_client *client, int irq)
{
int rc = devm_request_threaded_irq(&client->dev, irq, NULL,
isl1208_rtc_interrupt,
IRQF_SHARED | IRQF_ONESHOT,
isl1208_driver.driver.name,
client);
if (!rc) {
device_init_wakeup(&client->dev, 1);
enable_irq_wake(irq);
} else {
dev_err(&client->dev,
"Unable to request irq %d, no alarm support\n",
irq);
}
return rc;
}
static int
isl1208_clk_present(struct i2c_client *client, const char *name)
{
struct clk *clk;
clk = devm_clk_get_optional(&client->dev, name);
if (IS_ERR(clk))
return PTR_ERR(clk);
return !!clk;
}
static int
isl1208_probe(struct i2c_client *client)
{
struct isl1208_state *isl1208;
int evdet_irq = -1;
int xtosb_val = 0;
int rc = 0;
int sr;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
if (isl1208_i2c_validate_client(client) < 0)
return -ENODEV;
/* Allocate driver state, point i2c client data to it */
isl1208 = devm_kzalloc(&client->dev, sizeof(*isl1208), GFP_KERNEL);
if (!isl1208)
return -ENOMEM;
i2c_set_clientdata(client, isl1208);
/* Determine which chip we have */
isl1208->config = i2c_get_match_data(client);
if (!isl1208->config)
return -ENODEV;
rc = isl1208_clk_present(client, "xin");
if (rc < 0)
return rc;
if (!rc) {
rc = isl1208_clk_present(client, "clkin");
if (rc < 0)
return rc;
if (rc)
xtosb_val = 1;
}
isl1208->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(isl1208->rtc))
return PTR_ERR(isl1208->rtc);
isl1208->rtc->ops = &isl1208_rtc_ops;
/* Setup nvmem configuration in driver state struct */
isl1208->nvmem_config = isl1208_nvmem_config;
isl1208->nvmem_config.size = isl1208->config->nvmem_length;
isl1208->nvmem_config.priv = isl1208;
sr = isl1208_i2c_get_sr(client);
if (sr < 0) {
dev_err(&client->dev, "reading status failed\n");
return sr;
}
if (isl1208->config->has_inverted_osc_bit)
xtosb_val = !xtosb_val;
rc = isl1208_set_xtoscb(client, sr, xtosb_val);
if (rc)
return rc;
if (sr & ISL1208_REG_SR_RTCF)
dev_warn(&client->dev, "rtc power failure detected, "
"please set clock.\n");
if (isl1208->config->has_tamper) {
struct device_node *np = client->dev.of_node;
u32 evienb;
rc = i2c_smbus_read_byte_data(client, ISL1219_REG_EV);
if (rc < 0) {
dev_err(&client->dev, "failed to read EV reg\n");
return rc;
}
rc |= ISL1219_REG_EV_EVEN;
if (!of_property_read_u32(np, "isil,ev-evienb", &evienb)) {
if (evienb)
rc |= ISL1219_REG_EV_EVIENB;
else
rc &= ~ISL1219_REG_EV_EVIENB;
}
rc = i2c_smbus_write_byte_data(client, ISL1219_REG_EV, rc);
if (rc < 0) {
dev_err(&client->dev, "could not enable tamper detection\n");
return rc;
}
evdet_irq = of_irq_get_byname(np, "evdet");
}
if (isl1208->config->has_timestamp) {
rc = rtc_add_group(isl1208->rtc, &isl1219_rtc_sysfs_files);
if (rc)
return rc;
}
rc = rtc_add_group(isl1208->rtc, &isl1208_rtc_sysfs_files);
if (rc)
return rc;
if (client->irq > 0) {
rc = isl1208_setup_irq(client, client->irq);
if (rc)
return rc;
} else {
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, isl1208->rtc->features);
}
if (evdet_irq > 0 && evdet_irq != client->irq)
rc = isl1208_setup_irq(client, evdet_irq);
if (rc)
return rc;
rc = devm_rtc_nvmem_register(isl1208->rtc, &isl1208->nvmem_config);
if (rc)
return rc;
return devm_rtc_register_device(isl1208->rtc);
}
static struct i2c_driver isl1208_driver = {
.driver = {
.name = "rtc-isl1208",
.of_match_table = of_match_ptr(isl1208_of_match),
},
.probe = isl1208_probe,
.id_table = isl1208_id,
};
module_i2c_driver(isl1208_driver);
MODULE_AUTHOR("Herbert Valerio Riedel <[email protected]>");
MODULE_DESCRIPTION("Intersil ISL1208 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-isl1208.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Real time clock driver for DA9055
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: Dajun Dajun Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/mfd/da9055/core.h>
#include <linux/mfd/da9055/reg.h>
#include <linux/mfd/da9055/pdata.h>
struct da9055_rtc {
struct rtc_device *rtc;
struct da9055 *da9055;
int alarm_enable;
};
static int da9055_rtc_enable_alarm(struct da9055_rtc *rtc, bool enable)
{
int ret;
if (enable) {
ret = da9055_reg_update(rtc->da9055, DA9055_REG_ALARM_Y,
DA9055_RTC_ALM_EN,
DA9055_RTC_ALM_EN);
if (ret != 0)
dev_err(rtc->da9055->dev, "Failed to enable ALM: %d\n",
ret);
rtc->alarm_enable = 1;
} else {
ret = da9055_reg_update(rtc->da9055, DA9055_REG_ALARM_Y,
DA9055_RTC_ALM_EN, 0);
if (ret != 0)
dev_err(rtc->da9055->dev,
"Failed to disable ALM: %d\n", ret);
rtc->alarm_enable = 0;
}
return ret;
}
static irqreturn_t da9055_rtc_alm_irq(int irq, void *data)
{
struct da9055_rtc *rtc = data;
da9055_rtc_enable_alarm(rtc, 0);
rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static int da9055_read_alarm(struct da9055 *da9055, struct rtc_time *rtc_tm)
{
int ret;
uint8_t v[5];
ret = da9055_group_read(da9055, DA9055_REG_ALARM_MI, 5, v);
if (ret != 0) {
dev_err(da9055->dev, "Failed to group read ALM: %d\n", ret);
return ret;
}
rtc_tm->tm_year = (v[4] & DA9055_RTC_ALM_YEAR) + 100;
rtc_tm->tm_mon = (v[3] & DA9055_RTC_ALM_MONTH) - 1;
rtc_tm->tm_mday = v[2] & DA9055_RTC_ALM_DAY;
rtc_tm->tm_hour = v[1] & DA9055_RTC_ALM_HOUR;
rtc_tm->tm_min = v[0] & DA9055_RTC_ALM_MIN;
rtc_tm->tm_sec = 0;
return rtc_valid_tm(rtc_tm);
}
static int da9055_set_alarm(struct da9055 *da9055, struct rtc_time *rtc_tm)
{
int ret;
uint8_t v[2];
rtc_tm->tm_year -= 100;
rtc_tm->tm_mon += 1;
ret = da9055_reg_update(da9055, DA9055_REG_ALARM_MI,
DA9055_RTC_ALM_MIN, rtc_tm->tm_min);
if (ret != 0) {
dev_err(da9055->dev, "Failed to write ALRM MIN: %d\n", ret);
return ret;
}
v[0] = rtc_tm->tm_hour;
v[1] = rtc_tm->tm_mday;
ret = da9055_group_write(da9055, DA9055_REG_ALARM_H, 2, v);
if (ret < 0)
return ret;
ret = da9055_reg_update(da9055, DA9055_REG_ALARM_MO,
DA9055_RTC_ALM_MONTH, rtc_tm->tm_mon);
if (ret < 0)
dev_err(da9055->dev, "Failed to write ALM Month:%d\n", ret);
ret = da9055_reg_update(da9055, DA9055_REG_ALARM_Y,
DA9055_RTC_ALM_YEAR, rtc_tm->tm_year);
if (ret < 0)
dev_err(da9055->dev, "Failed to write ALM Year:%d\n", ret);
return ret;
}
static int da9055_rtc_get_alarm_status(struct da9055 *da9055)
{
int ret;
ret = da9055_reg_read(da9055, DA9055_REG_ALARM_Y);
if (ret < 0) {
dev_err(da9055->dev, "Failed to read ALM: %d\n", ret);
return ret;
}
ret &= DA9055_RTC_ALM_EN;
return (ret > 0) ? 1 : 0;
}
static int da9055_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
{
struct da9055_rtc *rtc = dev_get_drvdata(dev);
uint8_t v[6];
int ret;
ret = da9055_reg_read(rtc->da9055, DA9055_REG_COUNT_S);
if (ret < 0)
return ret;
/*
* Registers are only valid when RTC_READ
* status bit is asserted
*/
if (!(ret & DA9055_RTC_READ))
return -EBUSY;
ret = da9055_group_read(rtc->da9055, DA9055_REG_COUNT_S, 6, v);
if (ret < 0) {
dev_err(rtc->da9055->dev, "Failed to read RTC time : %d\n",
ret);
return ret;
}
rtc_tm->tm_year = (v[5] & DA9055_RTC_YEAR) + 100;
rtc_tm->tm_mon = (v[4] & DA9055_RTC_MONTH) - 1;
rtc_tm->tm_mday = v[3] & DA9055_RTC_DAY;
rtc_tm->tm_hour = v[2] & DA9055_RTC_HOUR;
rtc_tm->tm_min = v[1] & DA9055_RTC_MIN;
rtc_tm->tm_sec = v[0] & DA9055_RTC_SEC;
return 0;
}
static int da9055_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct da9055_rtc *rtc;
uint8_t v[6];
rtc = dev_get_drvdata(dev);
v[0] = tm->tm_sec;
v[1] = tm->tm_min;
v[2] = tm->tm_hour;
v[3] = tm->tm_mday;
v[4] = tm->tm_mon + 1;
v[5] = tm->tm_year - 100;
return da9055_group_write(rtc->da9055, DA9055_REG_COUNT_S, 6, v);
}
static int da9055_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
int ret;
struct rtc_time *tm = &alrm->time;
struct da9055_rtc *rtc = dev_get_drvdata(dev);
ret = da9055_read_alarm(rtc->da9055, tm);
if (ret)
return ret;
alrm->enabled = da9055_rtc_get_alarm_status(rtc->da9055);
return 0;
}
static int da9055_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
int ret;
struct rtc_time *tm = &alrm->time;
struct da9055_rtc *rtc = dev_get_drvdata(dev);
ret = da9055_rtc_enable_alarm(rtc, 0);
if (ret < 0)
return ret;
ret = da9055_set_alarm(rtc->da9055, tm);
if (ret)
return ret;
ret = da9055_rtc_enable_alarm(rtc, 1);
return ret;
}
static int da9055_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct da9055_rtc *rtc = dev_get_drvdata(dev);
return da9055_rtc_enable_alarm(rtc, enabled);
}
static const struct rtc_class_ops da9055_rtc_ops = {
.read_time = da9055_rtc_read_time,
.set_time = da9055_rtc_set_time,
.read_alarm = da9055_rtc_read_alarm,
.set_alarm = da9055_rtc_set_alarm,
.alarm_irq_enable = da9055_rtc_alarm_irq_enable,
};
static int da9055_rtc_device_init(struct da9055 *da9055,
struct da9055_pdata *pdata)
{
int ret;
/* Enable RTC and the internal Crystal */
ret = da9055_reg_update(da9055, DA9055_REG_CONTROL_B,
DA9055_RTC_EN, DA9055_RTC_EN);
if (ret < 0)
return ret;
ret = da9055_reg_update(da9055, DA9055_REG_EN_32K,
DA9055_CRYSTAL_EN, DA9055_CRYSTAL_EN);
if (ret < 0)
return ret;
/* Enable RTC in Power Down mode */
ret = da9055_reg_update(da9055, DA9055_REG_CONTROL_B,
DA9055_RTC_MODE_PD, DA9055_RTC_MODE_PD);
if (ret < 0)
return ret;
/* Enable RTC in Reset mode */
if (pdata && pdata->reset_enable) {
ret = da9055_reg_update(da9055, DA9055_REG_CONTROL_B,
DA9055_RTC_MODE_SD,
DA9055_RTC_MODE_SD <<
DA9055_RTC_MODE_SD_SHIFT);
if (ret < 0)
return ret;
}
/* Disable the RTC TICK ALM */
ret = da9055_reg_update(da9055, DA9055_REG_ALARM_MO,
DA9055_RTC_TICK_WAKE_MASK, 0);
if (ret < 0)
return ret;
return 0;
}
static int da9055_rtc_probe(struct platform_device *pdev)
{
struct da9055_rtc *rtc;
struct da9055_pdata *pdata = NULL;
int ret, alm_irq;
rtc = devm_kzalloc(&pdev->dev, sizeof(struct da9055_rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->da9055 = dev_get_drvdata(pdev->dev.parent);
pdata = dev_get_platdata(rtc->da9055->dev);
platform_set_drvdata(pdev, rtc);
ret = da9055_rtc_device_init(rtc->da9055, pdata);
if (ret < 0)
goto err_rtc;
ret = da9055_reg_read(rtc->da9055, DA9055_REG_ALARM_Y);
if (ret < 0)
goto err_rtc;
if (ret & DA9055_RTC_ALM_EN)
rtc->alarm_enable = 1;
device_init_wakeup(&pdev->dev, 1);
rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
&da9055_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rtc)) {
ret = PTR_ERR(rtc->rtc);
goto err_rtc;
}
alm_irq = platform_get_irq_byname(pdev, "ALM");
if (alm_irq < 0)
return alm_irq;
ret = devm_request_threaded_irq(&pdev->dev, alm_irq, NULL,
da9055_rtc_alm_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"ALM", rtc);
if (ret != 0)
dev_err(rtc->da9055->dev, "irq registration failed: %d\n", ret);
err_rtc:
return ret;
}
#ifdef CONFIG_PM
/* Turn off the alarm if it should not be a wake source. */
static int da9055_rtc_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct da9055_rtc *rtc = dev_get_drvdata(&pdev->dev);
int ret;
if (!device_may_wakeup(&pdev->dev)) {
/* Disable the ALM IRQ */
ret = da9055_rtc_enable_alarm(rtc, 0);
if (ret < 0)
dev_err(&pdev->dev, "Failed to disable RTC ALM\n");
}
return 0;
}
/* Enable the alarm if it should be enabled (in case it was disabled to
* prevent use as a wake source).
*/
static int da9055_rtc_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct da9055_rtc *rtc = dev_get_drvdata(&pdev->dev);
int ret;
if (!device_may_wakeup(&pdev->dev)) {
if (rtc->alarm_enable) {
ret = da9055_rtc_enable_alarm(rtc, 1);
if (ret < 0)
dev_err(&pdev->dev,
"Failed to restart RTC ALM\n");
}
}
return 0;
}
/* Unconditionally disable the alarm */
static int da9055_rtc_freeze(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct da9055_rtc *rtc = dev_get_drvdata(&pdev->dev);
int ret;
ret = da9055_rtc_enable_alarm(rtc, 0);
if (ret < 0)
dev_err(&pdev->dev, "Failed to freeze RTC ALMs\n");
return 0;
}
#else
#define da9055_rtc_suspend NULL
#define da9055_rtc_resume NULL
#define da9055_rtc_freeze NULL
#endif
static const struct dev_pm_ops da9055_rtc_pm_ops = {
.suspend = da9055_rtc_suspend,
.resume = da9055_rtc_resume,
.freeze = da9055_rtc_freeze,
.thaw = da9055_rtc_resume,
.restore = da9055_rtc_resume,
.poweroff = da9055_rtc_suspend,
};
static struct platform_driver da9055_rtc_driver = {
.probe = da9055_rtc_probe,
.driver = {
.name = "da9055-rtc",
.pm = &da9055_rtc_pm_ops,
},
};
module_platform_driver(da9055_rtc_driver);
MODULE_AUTHOR("David Dajun Chen <[email protected]>");
MODULE_DESCRIPTION("RTC driver for Dialog DA9055 PMIC");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9055-rtc");
| linux-master | drivers/rtc/rtc-da9055.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Ran Bi <[email protected]>
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#define MT2712_BBPU 0x0000
#define MT2712_BBPU_CLRPKY BIT(4)
#define MT2712_BBPU_RELOAD BIT(5)
#define MT2712_BBPU_CBUSY BIT(6)
#define MT2712_BBPU_KEY (0x43 << 8)
#define MT2712_IRQ_STA 0x0004
#define MT2712_IRQ_STA_AL BIT(0)
#define MT2712_IRQ_STA_TC BIT(1)
#define MT2712_IRQ_EN 0x0008
#define MT2712_IRQ_EN_AL BIT(0)
#define MT2712_IRQ_EN_TC BIT(1)
#define MT2712_IRQ_EN_ONESHOT BIT(2)
#define MT2712_CII_EN 0x000c
#define MT2712_AL_MASK 0x0010
#define MT2712_AL_MASK_DOW BIT(4)
#define MT2712_TC_SEC 0x0014
#define MT2712_TC_MIN 0x0018
#define MT2712_TC_HOU 0x001c
#define MT2712_TC_DOM 0x0020
#define MT2712_TC_DOW 0x0024
#define MT2712_TC_MTH 0x0028
#define MT2712_TC_YEA 0x002c
#define MT2712_AL_SEC 0x0030
#define MT2712_AL_MIN 0x0034
#define MT2712_AL_HOU 0x0038
#define MT2712_AL_DOM 0x003c
#define MT2712_AL_DOW 0x0040
#define MT2712_AL_MTH 0x0044
#define MT2712_AL_YEA 0x0048
#define MT2712_SEC_MASK 0x003f
#define MT2712_MIN_MASK 0x003f
#define MT2712_HOU_MASK 0x001f
#define MT2712_DOM_MASK 0x001f
#define MT2712_DOW_MASK 0x0007
#define MT2712_MTH_MASK 0x000f
#define MT2712_YEA_MASK 0x007f
#define MT2712_POWERKEY1 0x004c
#define MT2712_POWERKEY2 0x0050
#define MT2712_POWERKEY1_KEY 0xa357
#define MT2712_POWERKEY2_KEY 0x67d2
#define MT2712_CON0 0x005c
#define MT2712_CON1 0x0060
#define MT2712_PROT 0x0070
#define MT2712_PROT_UNLOCK1 0x9136
#define MT2712_PROT_UNLOCK2 0x586a
#define MT2712_WRTGR 0x0078
#define MT2712_RTC_TIMESTAMP_END_2127 4985971199LL
struct mt2712_rtc {
struct rtc_device *rtc;
void __iomem *base;
int irq;
u8 irq_wake_enabled;
u8 powerlost;
};
static inline u32 mt2712_readl(struct mt2712_rtc *mt2712_rtc, u32 reg)
{
return readl(mt2712_rtc->base + reg);
}
static inline void mt2712_writel(struct mt2712_rtc *mt2712_rtc,
u32 reg, u32 val)
{
writel(val, mt2712_rtc->base + reg);
}
static void mt2712_rtc_write_trigger(struct mt2712_rtc *mt2712_rtc)
{
unsigned long timeout = jiffies + HZ / 10;
mt2712_writel(mt2712_rtc, MT2712_WRTGR, 1);
while (1) {
if (!(mt2712_readl(mt2712_rtc, MT2712_BBPU)
& MT2712_BBPU_CBUSY))
break;
if (time_after(jiffies, timeout)) {
dev_err(&mt2712_rtc->rtc->dev,
"%s time out!\n", __func__);
break;
}
cpu_relax();
}
}
static void mt2712_rtc_writeif_unlock(struct mt2712_rtc *mt2712_rtc)
{
mt2712_writel(mt2712_rtc, MT2712_PROT, MT2712_PROT_UNLOCK1);
mt2712_rtc_write_trigger(mt2712_rtc);
mt2712_writel(mt2712_rtc, MT2712_PROT, MT2712_PROT_UNLOCK2);
mt2712_rtc_write_trigger(mt2712_rtc);
}
static irqreturn_t rtc_irq_handler_thread(int irq, void *data)
{
struct mt2712_rtc *mt2712_rtc = data;
u16 irqsta;
/* Clear interrupt */
irqsta = mt2712_readl(mt2712_rtc, MT2712_IRQ_STA);
if (irqsta & MT2712_IRQ_STA_AL) {
rtc_update_irq(mt2712_rtc->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static void __mt2712_rtc_read_time(struct mt2712_rtc *mt2712_rtc,
struct rtc_time *tm, int *sec)
{
tm->tm_sec = mt2712_readl(mt2712_rtc, MT2712_TC_SEC)
& MT2712_SEC_MASK;
tm->tm_min = mt2712_readl(mt2712_rtc, MT2712_TC_MIN)
& MT2712_MIN_MASK;
tm->tm_hour = mt2712_readl(mt2712_rtc, MT2712_TC_HOU)
& MT2712_HOU_MASK;
tm->tm_mday = mt2712_readl(mt2712_rtc, MT2712_TC_DOM)
& MT2712_DOM_MASK;
tm->tm_mon = (mt2712_readl(mt2712_rtc, MT2712_TC_MTH) - 1)
& MT2712_MTH_MASK;
tm->tm_year = (mt2712_readl(mt2712_rtc, MT2712_TC_YEA) + 100)
& MT2712_YEA_MASK;
*sec = mt2712_readl(mt2712_rtc, MT2712_TC_SEC) & MT2712_SEC_MASK;
}
static int mt2712_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
int sec;
if (mt2712_rtc->powerlost)
return -EINVAL;
do {
__mt2712_rtc_read_time(mt2712_rtc, tm, &sec);
} while (sec < tm->tm_sec); /* SEC has carried */
return 0;
}
static int mt2712_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
mt2712_writel(mt2712_rtc, MT2712_TC_SEC, tm->tm_sec & MT2712_SEC_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_MIN, tm->tm_min & MT2712_MIN_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_HOU, tm->tm_hour & MT2712_HOU_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_DOM, tm->tm_mday & MT2712_DOM_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_MTH,
(tm->tm_mon + 1) & MT2712_MTH_MASK);
mt2712_writel(mt2712_rtc, MT2712_TC_YEA,
(tm->tm_year - 100) & MT2712_YEA_MASK);
mt2712_rtc_write_trigger(mt2712_rtc);
if (mt2712_rtc->powerlost)
mt2712_rtc->powerlost = false;
return 0;
}
static int mt2712_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &alm->time;
u16 irqen;
irqen = mt2712_readl(mt2712_rtc, MT2712_IRQ_EN);
alm->enabled = !!(irqen & MT2712_IRQ_EN_AL);
tm->tm_sec = mt2712_readl(mt2712_rtc, MT2712_AL_SEC) & MT2712_SEC_MASK;
tm->tm_min = mt2712_readl(mt2712_rtc, MT2712_AL_MIN) & MT2712_MIN_MASK;
tm->tm_hour = mt2712_readl(mt2712_rtc, MT2712_AL_HOU) & MT2712_HOU_MASK;
tm->tm_mday = mt2712_readl(mt2712_rtc, MT2712_AL_DOM) & MT2712_DOM_MASK;
tm->tm_mon = (mt2712_readl(mt2712_rtc, MT2712_AL_MTH) - 1)
& MT2712_MTH_MASK;
tm->tm_year = (mt2712_readl(mt2712_rtc, MT2712_AL_YEA) + 100)
& MT2712_YEA_MASK;
return 0;
}
static int mt2712_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
u16 irqen;
irqen = mt2712_readl(mt2712_rtc, MT2712_IRQ_EN);
if (enabled)
irqen |= MT2712_IRQ_EN_AL;
else
irqen &= ~MT2712_IRQ_EN_AL;
mt2712_writel(mt2712_rtc, MT2712_IRQ_EN, irqen);
mt2712_rtc_write_trigger(mt2712_rtc);
return 0;
}
static int mt2712_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &alm->time;
dev_dbg(&mt2712_rtc->rtc->dev, "set al time: %ptR, alm en: %d\n",
tm, alm->enabled);
mt2712_writel(mt2712_rtc, MT2712_AL_SEC,
(mt2712_readl(mt2712_rtc, MT2712_AL_SEC)
& ~(MT2712_SEC_MASK)) | (tm->tm_sec & MT2712_SEC_MASK));
mt2712_writel(mt2712_rtc, MT2712_AL_MIN,
(mt2712_readl(mt2712_rtc, MT2712_AL_MIN)
& ~(MT2712_MIN_MASK)) | (tm->tm_min & MT2712_MIN_MASK));
mt2712_writel(mt2712_rtc, MT2712_AL_HOU,
(mt2712_readl(mt2712_rtc, MT2712_AL_HOU)
& ~(MT2712_HOU_MASK)) | (tm->tm_hour & MT2712_HOU_MASK));
mt2712_writel(mt2712_rtc, MT2712_AL_DOM,
(mt2712_readl(mt2712_rtc, MT2712_AL_DOM)
& ~(MT2712_DOM_MASK)) | (tm->tm_mday & MT2712_DOM_MASK));
mt2712_writel(mt2712_rtc, MT2712_AL_MTH,
(mt2712_readl(mt2712_rtc, MT2712_AL_MTH)
& ~(MT2712_MTH_MASK))
| ((tm->tm_mon + 1) & MT2712_MTH_MASK));
mt2712_writel(mt2712_rtc, MT2712_AL_YEA,
(mt2712_readl(mt2712_rtc, MT2712_AL_YEA)
& ~(MT2712_YEA_MASK))
| ((tm->tm_year - 100) & MT2712_YEA_MASK));
/* mask day of week */
mt2712_writel(mt2712_rtc, MT2712_AL_MASK, MT2712_AL_MASK_DOW);
mt2712_rtc_write_trigger(mt2712_rtc);
mt2712_rtc_alarm_irq_enable(dev, alm->enabled);
return 0;
}
/* Init RTC register */
static void mt2712_rtc_hw_init(struct mt2712_rtc *mt2712_rtc)
{
u32 p1, p2;
mt2712_writel(mt2712_rtc, MT2712_BBPU,
MT2712_BBPU_KEY | MT2712_BBPU_RELOAD);
mt2712_writel(mt2712_rtc, MT2712_CII_EN, 0);
mt2712_writel(mt2712_rtc, MT2712_AL_MASK, 0);
/* necessary before set MT2712_POWERKEY */
mt2712_writel(mt2712_rtc, MT2712_CON0, 0x4848);
mt2712_writel(mt2712_rtc, MT2712_CON1, 0x0048);
mt2712_rtc_write_trigger(mt2712_rtc);
p1 = mt2712_readl(mt2712_rtc, MT2712_POWERKEY1);
p2 = mt2712_readl(mt2712_rtc, MT2712_POWERKEY2);
if (p1 != MT2712_POWERKEY1_KEY || p2 != MT2712_POWERKEY2_KEY) {
mt2712_rtc->powerlost = true;
dev_dbg(&mt2712_rtc->rtc->dev,
"powerkey not set (lost power)\n");
} else {
mt2712_rtc->powerlost = false;
}
/* RTC need POWERKEY1/2 match, then goto normal work mode */
mt2712_writel(mt2712_rtc, MT2712_POWERKEY1, MT2712_POWERKEY1_KEY);
mt2712_writel(mt2712_rtc, MT2712_POWERKEY2, MT2712_POWERKEY2_KEY);
mt2712_rtc_write_trigger(mt2712_rtc);
mt2712_rtc_writeif_unlock(mt2712_rtc);
}
static const struct rtc_class_ops mt2712_rtc_ops = {
.read_time = mt2712_rtc_read_time,
.set_time = mt2712_rtc_set_time,
.read_alarm = mt2712_rtc_read_alarm,
.set_alarm = mt2712_rtc_set_alarm,
.alarm_irq_enable = mt2712_rtc_alarm_irq_enable,
};
static int mt2712_rtc_probe(struct platform_device *pdev)
{
struct mt2712_rtc *mt2712_rtc;
int ret;
mt2712_rtc = devm_kzalloc(&pdev->dev,
sizeof(struct mt2712_rtc), GFP_KERNEL);
if (!mt2712_rtc)
return -ENOMEM;
mt2712_rtc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mt2712_rtc->base))
return PTR_ERR(mt2712_rtc->base);
/* rtc hw init */
mt2712_rtc_hw_init(mt2712_rtc);
mt2712_rtc->irq = platform_get_irq(pdev, 0);
if (mt2712_rtc->irq < 0)
return mt2712_rtc->irq;
platform_set_drvdata(pdev, mt2712_rtc);
mt2712_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(mt2712_rtc->rtc))
return PTR_ERR(mt2712_rtc->rtc);
ret = devm_request_threaded_irq(&pdev->dev, mt2712_rtc->irq, NULL,
rtc_irq_handler_thread,
IRQF_ONESHOT | IRQF_TRIGGER_LOW,
dev_name(&mt2712_rtc->rtc->dev),
mt2712_rtc);
if (ret) {
dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
mt2712_rtc->irq, ret);
return ret;
}
device_init_wakeup(&pdev->dev, true);
mt2712_rtc->rtc->ops = &mt2712_rtc_ops;
mt2712_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
mt2712_rtc->rtc->range_max = MT2712_RTC_TIMESTAMP_END_2127;
return devm_rtc_register_device(mt2712_rtc->rtc);
}
#ifdef CONFIG_PM_SLEEP
static int mt2712_rtc_suspend(struct device *dev)
{
int wake_status = 0;
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev)) {
wake_status = enable_irq_wake(mt2712_rtc->irq);
if (!wake_status)
mt2712_rtc->irq_wake_enabled = true;
}
return 0;
}
static int mt2712_rtc_resume(struct device *dev)
{
int wake_status = 0;
struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev) && mt2712_rtc->irq_wake_enabled) {
wake_status = disable_irq_wake(mt2712_rtc->irq);
if (!wake_status)
mt2712_rtc->irq_wake_enabled = false;
}
return 0;
}
static SIMPLE_DEV_PM_OPS(mt2712_pm_ops, mt2712_rtc_suspend,
mt2712_rtc_resume);
#endif
static const struct of_device_id mt2712_rtc_of_match[] = {
{ .compatible = "mediatek,mt2712-rtc", },
{ },
};
MODULE_DEVICE_TABLE(of, mt2712_rtc_of_match);
static struct platform_driver mt2712_rtc_driver = {
.driver = {
.name = "mt2712-rtc",
.of_match_table = mt2712_rtc_of_match,
#ifdef CONFIG_PM_SLEEP
.pm = &mt2712_pm_ops,
#endif
},
.probe = mt2712_rtc_probe,
};
module_platform_driver(mt2712_rtc_driver);
MODULE_DESCRIPTION("MediaTek MT2712 SoC based RTC Driver");
MODULE_AUTHOR("Ran Bi <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-mt2712.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Driver for the Epson RTC module RX-6110 SA
*
* Copyright(C) 2015 Pengutronix, Steffen Trumtrar <[email protected]>
* Copyright(C) SEIKO EPSON CORPORATION 2013. All rights reserved.
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/of.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
/* RX-6110 Register definitions */
#define RX6110_REG_SEC 0x10
#define RX6110_REG_MIN 0x11
#define RX6110_REG_HOUR 0x12
#define RX6110_REG_WDAY 0x13
#define RX6110_REG_MDAY 0x14
#define RX6110_REG_MONTH 0x15
#define RX6110_REG_YEAR 0x16
#define RX6110_REG_RES1 0x17
#define RX6110_REG_ALMIN 0x18
#define RX6110_REG_ALHOUR 0x19
#define RX6110_REG_ALWDAY 0x1A
#define RX6110_REG_TCOUNT0 0x1B
#define RX6110_REG_TCOUNT1 0x1C
#define RX6110_REG_EXT 0x1D
#define RX6110_REG_FLAG 0x1E
#define RX6110_REG_CTRL 0x1F
#define RX6110_REG_USER0 0x20
#define RX6110_REG_USER1 0x21
#define RX6110_REG_USER2 0x22
#define RX6110_REG_USER3 0x23
#define RX6110_REG_USER4 0x24
#define RX6110_REG_USER5 0x25
#define RX6110_REG_USER6 0x26
#define RX6110_REG_USER7 0x27
#define RX6110_REG_USER8 0x28
#define RX6110_REG_USER9 0x29
#define RX6110_REG_USERA 0x2A
#define RX6110_REG_USERB 0x2B
#define RX6110_REG_USERC 0x2C
#define RX6110_REG_USERD 0x2D
#define RX6110_REG_USERE 0x2E
#define RX6110_REG_USERF 0x2F
#define RX6110_REG_RES2 0x30
#define RX6110_REG_RES3 0x31
#define RX6110_REG_IRQ 0x32
#define RX6110_BIT_ALARM_EN BIT(7)
/* Extension Register (1Dh) bit positions */
#define RX6110_BIT_EXT_TSEL0 BIT(0)
#define RX6110_BIT_EXT_TSEL1 BIT(1)
#define RX6110_BIT_EXT_TSEL2 BIT(2)
#define RX6110_BIT_EXT_WADA BIT(3)
#define RX6110_BIT_EXT_TE BIT(4)
#define RX6110_BIT_EXT_USEL BIT(5)
#define RX6110_BIT_EXT_FSEL0 BIT(6)
#define RX6110_BIT_EXT_FSEL1 BIT(7)
/* Flag Register (1Eh) bit positions */
#define RX6110_BIT_FLAG_VLF BIT(1)
#define RX6110_BIT_FLAG_AF BIT(3)
#define RX6110_BIT_FLAG_TF BIT(4)
#define RX6110_BIT_FLAG_UF BIT(5)
/* Control Register (1Fh) bit positions */
#define RX6110_BIT_CTRL_TBKE BIT(0)
#define RX6110_BIT_CTRL_TBKON BIT(1)
#define RX6110_BIT_CTRL_TSTP BIT(2)
#define RX6110_BIT_CTRL_AIE BIT(3)
#define RX6110_BIT_CTRL_TIE BIT(4)
#define RX6110_BIT_CTRL_UIE BIT(5)
#define RX6110_BIT_CTRL_STOP BIT(6)
#define RX6110_BIT_CTRL_TEST BIT(7)
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WDAY,
RTC_MDAY,
RTC_MONTH,
RTC_YEAR,
RTC_NR_TIME
};
#define RX6110_DRIVER_NAME "rx6110"
struct rx6110_data {
struct rtc_device *rtc;
struct regmap *regmap;
};
/**
* rx6110_rtc_tm_to_data - convert rtc_time to native time encoding
*
* @tm: holds date and time
* @data: holds the encoding in rx6110 native form
*/
static int rx6110_rtc_tm_to_data(struct rtc_time *tm, u8 *data)
{
pr_debug("%s: date %ptRr\n", __func__, tm);
/*
* The year in the RTC is a value between 0 and 99.
* Assume that this represents the current century
* and disregard all other values.
*/
if (tm->tm_year < 100 || tm->tm_year >= 200)
return -EINVAL;
data[RTC_SEC] = bin2bcd(tm->tm_sec);
data[RTC_MIN] = bin2bcd(tm->tm_min);
data[RTC_HOUR] = bin2bcd(tm->tm_hour);
data[RTC_WDAY] = BIT(bin2bcd(tm->tm_wday));
data[RTC_MDAY] = bin2bcd(tm->tm_mday);
data[RTC_MONTH] = bin2bcd(tm->tm_mon + 1);
data[RTC_YEAR] = bin2bcd(tm->tm_year % 100);
return 0;
}
/**
* rx6110_data_to_rtc_tm - convert native time encoding to rtc_time
*
* @data: holds the encoding in rx6110 native form
* @tm: holds date and time
*/
static int rx6110_data_to_rtc_tm(u8 *data, struct rtc_time *tm)
{
tm->tm_sec = bcd2bin(data[RTC_SEC] & 0x7f);
tm->tm_min = bcd2bin(data[RTC_MIN] & 0x7f);
/* only 24-hour clock */
tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f);
tm->tm_wday = ffs(data[RTC_WDAY] & 0x7f);
tm->tm_mday = bcd2bin(data[RTC_MDAY] & 0x3f);
tm->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1f) - 1;
tm->tm_year = bcd2bin(data[RTC_YEAR]) + 100;
pr_debug("%s: date %ptRr\n", __func__, tm);
/*
* The year in the RTC is a value between 0 and 99.
* Assume that this represents the current century
* and disregard all other values.
*/
if (tm->tm_year < 100 || tm->tm_year >= 200)
return -EINVAL;
return 0;
}
/**
* rx6110_set_time - set the current time in the rx6110 registers
*
* @dev: the rtc device in use
* @tm: holds date and time
*
* BUG: The HW assumes every year that is a multiple of 4 to be a leap
* year. Next time this is wrong is 2100, which will not be a leap year
*
* Note: If STOP is not set/cleared, the clock will start when the seconds
* register is written
*
*/
static int rx6110_set_time(struct device *dev, struct rtc_time *tm)
{
struct rx6110_data *rx6110 = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = rx6110_rtc_tm_to_data(tm, data);
if (ret < 0)
return ret;
/* set STOP bit before changing clock/calendar */
ret = regmap_update_bits(rx6110->regmap, RX6110_REG_CTRL,
RX6110_BIT_CTRL_STOP, RX6110_BIT_CTRL_STOP);
if (ret)
return ret;
ret = regmap_bulk_write(rx6110->regmap, RX6110_REG_SEC, data,
RTC_NR_TIME);
if (ret)
return ret;
/* The time in the RTC is valid. Be sure to have VLF cleared. */
ret = regmap_update_bits(rx6110->regmap, RX6110_REG_FLAG,
RX6110_BIT_FLAG_VLF, 0);
if (ret)
return ret;
/* clear STOP bit after changing clock/calendar */
ret = regmap_update_bits(rx6110->regmap, RX6110_REG_CTRL,
RX6110_BIT_CTRL_STOP, 0);
return ret;
}
/**
* rx6110_get_time - get the current time from the rx6110 registers
* @dev: the rtc device in use
* @tm: holds date and time
*/
static int rx6110_get_time(struct device *dev, struct rtc_time *tm)
{
struct rx6110_data *rx6110 = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int flags;
int ret;
ret = regmap_read(rx6110->regmap, RX6110_REG_FLAG, &flags);
if (ret)
return -EINVAL;
/* check for VLF Flag (set at power-on) */
if ((flags & RX6110_BIT_FLAG_VLF)) {
dev_warn(dev, "Voltage low, data is invalid.\n");
return -EINVAL;
}
/* read registers to date */
ret = regmap_bulk_read(rx6110->regmap, RX6110_REG_SEC, data,
RTC_NR_TIME);
if (ret)
return ret;
ret = rx6110_data_to_rtc_tm(data, tm);
if (ret)
return ret;
dev_dbg(dev, "%s: date %ptRr\n", __func__, tm);
return 0;
}
static const struct reg_sequence rx6110_default_regs[] = {
{ RX6110_REG_RES1, 0xB8 },
{ RX6110_REG_RES2, 0x00 },
{ RX6110_REG_RES3, 0x10 },
{ RX6110_REG_IRQ, 0x00 },
{ RX6110_REG_ALMIN, 0x00 },
{ RX6110_REG_ALHOUR, 0x00 },
{ RX6110_REG_ALWDAY, 0x00 },
};
/**
* rx6110_init - initialize the rx6110 registers
*
* @rx6110: pointer to the rx6110 struct in use
*
*/
static int rx6110_init(struct rx6110_data *rx6110)
{
struct rtc_device *rtc = rx6110->rtc;
int flags;
int ret;
ret = regmap_update_bits(rx6110->regmap, RX6110_REG_EXT,
RX6110_BIT_EXT_TE, 0);
if (ret)
return ret;
ret = regmap_register_patch(rx6110->regmap, rx6110_default_regs,
ARRAY_SIZE(rx6110_default_regs));
if (ret)
return ret;
ret = regmap_read(rx6110->regmap, RX6110_REG_FLAG, &flags);
if (ret)
return ret;
/* check for VLF Flag (set at power-on) */
if ((flags & RX6110_BIT_FLAG_VLF))
dev_warn(&rtc->dev, "Voltage low, data loss detected.\n");
/* check for Alarm Flag */
if (flags & RX6110_BIT_FLAG_AF)
dev_warn(&rtc->dev, "An alarm may have been missed.\n");
/* check for Periodic Timer Flag */
if (flags & RX6110_BIT_FLAG_TF)
dev_warn(&rtc->dev, "Periodic timer was detected\n");
/* check for Update Timer Flag */
if (flags & RX6110_BIT_FLAG_UF)
dev_warn(&rtc->dev, "Update timer was detected\n");
/* clear all flags BUT VLF */
ret = regmap_update_bits(rx6110->regmap, RX6110_REG_FLAG,
RX6110_BIT_FLAG_AF |
RX6110_BIT_FLAG_UF |
RX6110_BIT_FLAG_TF,
0);
return ret;
}
static const struct rtc_class_ops rx6110_rtc_ops = {
.read_time = rx6110_get_time,
.set_time = rx6110_set_time,
};
static int rx6110_probe(struct rx6110_data *rx6110, struct device *dev)
{
int err;
rx6110->rtc = devm_rtc_device_register(dev,
RX6110_DRIVER_NAME,
&rx6110_rtc_ops, THIS_MODULE);
if (IS_ERR(rx6110->rtc))
return PTR_ERR(rx6110->rtc);
err = rx6110_init(rx6110);
if (err)
return err;
rx6110->rtc->max_user_freq = 1;
return 0;
}
#if IS_ENABLED(CONFIG_SPI_MASTER)
static struct regmap_config regmap_spi_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RX6110_REG_IRQ,
.read_flag_mask = 0x80,
};
/**
* rx6110_spi_probe - initialize rtc driver
* @spi: pointer to spi device
*/
static int rx6110_spi_probe(struct spi_device *spi)
{
struct rx6110_data *rx6110;
if ((spi->bits_per_word && spi->bits_per_word != 8) ||
(spi->max_speed_hz > 2000000) ||
(spi->mode != (SPI_CS_HIGH | SPI_CPOL | SPI_CPHA))) {
dev_warn(&spi->dev, "SPI settings: bits_per_word: %d, max_speed_hz: %d, mode: %xh\n",
spi->bits_per_word, spi->max_speed_hz, spi->mode);
dev_warn(&spi->dev, "driving device in an unsupported mode");
}
rx6110 = devm_kzalloc(&spi->dev, sizeof(*rx6110), GFP_KERNEL);
if (!rx6110)
return -ENOMEM;
rx6110->regmap = devm_regmap_init_spi(spi, ®map_spi_config);
if (IS_ERR(rx6110->regmap)) {
dev_err(&spi->dev, "regmap init failed for rtc rx6110\n");
return PTR_ERR(rx6110->regmap);
}
spi_set_drvdata(spi, rx6110);
return rx6110_probe(rx6110, &spi->dev);
}
static const struct spi_device_id rx6110_spi_id[] = {
{ "rx6110", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, rx6110_spi_id);
static const __maybe_unused struct of_device_id rx6110_spi_of_match[] = {
{ .compatible = "epson,rx6110" },
{ },
};
MODULE_DEVICE_TABLE(of, rx6110_spi_of_match);
static struct spi_driver rx6110_spi_driver = {
.driver = {
.name = RX6110_DRIVER_NAME,
.of_match_table = of_match_ptr(rx6110_spi_of_match),
},
.probe = rx6110_spi_probe,
.id_table = rx6110_spi_id,
};
static int rx6110_spi_register(void)
{
return spi_register_driver(&rx6110_spi_driver);
}
static void rx6110_spi_unregister(void)
{
spi_unregister_driver(&rx6110_spi_driver);
}
#else
static int rx6110_spi_register(void)
{
return 0;
}
static void rx6110_spi_unregister(void)
{
}
#endif /* CONFIG_SPI_MASTER */
#if IS_ENABLED(CONFIG_I2C)
static struct regmap_config regmap_i2c_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = RX6110_REG_IRQ,
.read_flag_mask = 0x80,
};
static int rx6110_i2c_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
struct rx6110_data *rx6110;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_I2C_BLOCK)) {
dev_err(&adapter->dev,
"doesn't support required functionality\n");
return -EIO;
}
rx6110 = devm_kzalloc(&client->dev, sizeof(*rx6110), GFP_KERNEL);
if (!rx6110)
return -ENOMEM;
rx6110->regmap = devm_regmap_init_i2c(client, ®map_i2c_config);
if (IS_ERR(rx6110->regmap)) {
dev_err(&client->dev, "regmap init failed for rtc rx6110\n");
return PTR_ERR(rx6110->regmap);
}
i2c_set_clientdata(client, rx6110);
return rx6110_probe(rx6110, &client->dev);
}
static const struct acpi_device_id rx6110_i2c_acpi_match[] = {
{ "SECC6110" },
{ }
};
MODULE_DEVICE_TABLE(acpi, rx6110_i2c_acpi_match);
static const struct i2c_device_id rx6110_i2c_id[] = {
{ "rx6110", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rx6110_i2c_id);
static struct i2c_driver rx6110_i2c_driver = {
.driver = {
.name = RX6110_DRIVER_NAME,
.acpi_match_table = rx6110_i2c_acpi_match,
},
.probe = rx6110_i2c_probe,
.id_table = rx6110_i2c_id,
};
static int rx6110_i2c_register(void)
{
return i2c_add_driver(&rx6110_i2c_driver);
}
static void rx6110_i2c_unregister(void)
{
i2c_del_driver(&rx6110_i2c_driver);
}
#else
static int rx6110_i2c_register(void)
{
return 0;
}
static void rx6110_i2c_unregister(void)
{
}
#endif /* CONFIG_I2C */
static int __init rx6110_module_init(void)
{
int ret;
ret = rx6110_spi_register();
if (ret)
return ret;
ret = rx6110_i2c_register();
if (ret)
rx6110_spi_unregister();
return ret;
}
module_init(rx6110_module_init);
static void __exit rx6110_module_exit(void)
{
rx6110_spi_unregister();
rx6110_i2c_unregister();
}
module_exit(rx6110_module_exit);
MODULE_AUTHOR("Val Krutov <[email protected]>");
MODULE_DESCRIPTION("RX-6110 SA RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-rx6110.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Real Time Clock (RTC) Driver for sd3078
* Copyright (C) 2018 Zoro Li
*/
#include <linux/bcd.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#define SD3078_REG_SC 0x00
#define SD3078_REG_MN 0x01
#define SD3078_REG_HR 0x02
#define SD3078_REG_DW 0x03
#define SD3078_REG_DM 0x04
#define SD3078_REG_MO 0x05
#define SD3078_REG_YR 0x06
#define SD3078_REG_CTRL1 0x0f
#define SD3078_REG_CTRL2 0x10
#define SD3078_REG_CTRL3 0x11
#define KEY_WRITE1 0x80
#define KEY_WRITE2 0x04
#define KEY_WRITE3 0x80
#define NUM_TIME_REGS (SD3078_REG_YR - SD3078_REG_SC + 1)
/*
* The sd3078 has write protection
* and we can choose whether or not to use it.
* Write protection is turned off by default.
*/
#define WRITE_PROTECT_EN 0
struct sd3078 {
struct rtc_device *rtc;
struct regmap *regmap;
};
/*
* In order to prevent arbitrary modification of the time register,
* when modification of the register,
* the "write" bit needs to be written in a certain order.
* 1. set WRITE1 bit
* 2. set WRITE2 bit
* 3. set WRITE3 bit
*/
static void sd3078_enable_reg_write(struct sd3078 *sd3078)
{
regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL2,
KEY_WRITE1, KEY_WRITE1);
regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
KEY_WRITE2, KEY_WRITE2);
regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
KEY_WRITE3, KEY_WRITE3);
}
#if WRITE_PROTECT_EN
/*
* In order to prevent arbitrary modification of the time register,
* we should disable the write function.
* when disable write,
* the "write" bit needs to be clear in a certain order.
* 1. clear WRITE2 bit
* 2. clear WRITE3 bit
* 3. clear WRITE1 bit
*/
static void sd3078_disable_reg_write(struct sd3078 *sd3078)
{
regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
KEY_WRITE2, 0);
regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL1,
KEY_WRITE3, 0);
regmap_update_bits(sd3078->regmap, SD3078_REG_CTRL2,
KEY_WRITE1, 0);
}
#endif
static int sd3078_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
unsigned char hour;
unsigned char rtc_data[NUM_TIME_REGS] = {0};
struct i2c_client *client = to_i2c_client(dev);
struct sd3078 *sd3078 = i2c_get_clientdata(client);
int ret;
ret = regmap_bulk_read(sd3078->regmap, SD3078_REG_SC, rtc_data,
NUM_TIME_REGS);
if (ret < 0) {
dev_err(dev, "reading from RTC failed with err:%d\n", ret);
return ret;
}
tm->tm_sec = bcd2bin(rtc_data[SD3078_REG_SC] & 0x7F);
tm->tm_min = bcd2bin(rtc_data[SD3078_REG_MN] & 0x7F);
/*
* The sd3078 supports 12/24 hour mode.
* When getting time,
* we need to convert the 12 hour mode to the 24 hour mode.
*/
hour = rtc_data[SD3078_REG_HR];
if (hour & 0x80) /* 24H MODE */
tm->tm_hour = bcd2bin(rtc_data[SD3078_REG_HR] & 0x3F);
else if (hour & 0x20) /* 12H MODE PM */
tm->tm_hour = bcd2bin(rtc_data[SD3078_REG_HR] & 0x1F) + 12;
else /* 12H MODE AM */
tm->tm_hour = bcd2bin(rtc_data[SD3078_REG_HR] & 0x1F);
tm->tm_mday = bcd2bin(rtc_data[SD3078_REG_DM] & 0x3F);
tm->tm_wday = rtc_data[SD3078_REG_DW] & 0x07;
tm->tm_mon = bcd2bin(rtc_data[SD3078_REG_MO] & 0x1F) - 1;
tm->tm_year = bcd2bin(rtc_data[SD3078_REG_YR]) + 100;
return 0;
}
static int sd3078_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
unsigned char rtc_data[NUM_TIME_REGS];
struct i2c_client *client = to_i2c_client(dev);
struct sd3078 *sd3078 = i2c_get_clientdata(client);
int ret;
rtc_data[SD3078_REG_SC] = bin2bcd(tm->tm_sec);
rtc_data[SD3078_REG_MN] = bin2bcd(tm->tm_min);
rtc_data[SD3078_REG_HR] = bin2bcd(tm->tm_hour) | 0x80;
rtc_data[SD3078_REG_DM] = bin2bcd(tm->tm_mday);
rtc_data[SD3078_REG_DW] = tm->tm_wday & 0x07;
rtc_data[SD3078_REG_MO] = bin2bcd(tm->tm_mon) + 1;
rtc_data[SD3078_REG_YR] = bin2bcd(tm->tm_year - 100);
#if WRITE_PROTECT_EN
sd3078_enable_reg_write(sd3078);
#endif
ret = regmap_bulk_write(sd3078->regmap, SD3078_REG_SC, rtc_data,
NUM_TIME_REGS);
if (ret < 0) {
dev_err(dev, "writing to RTC failed with err:%d\n", ret);
return ret;
}
#if WRITE_PROTECT_EN
sd3078_disable_reg_write(sd3078);
#endif
return 0;
}
static const struct rtc_class_ops sd3078_rtc_ops = {
.read_time = sd3078_rtc_read_time,
.set_time = sd3078_rtc_set_time,
};
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x11,
};
static int sd3078_probe(struct i2c_client *client)
{
int ret;
struct sd3078 *sd3078;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
sd3078 = devm_kzalloc(&client->dev, sizeof(*sd3078), GFP_KERNEL);
if (!sd3078)
return -ENOMEM;
sd3078->regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(sd3078->regmap)) {
dev_err(&client->dev, "regmap allocation failed\n");
return PTR_ERR(sd3078->regmap);
}
i2c_set_clientdata(client, sd3078);
sd3078->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(sd3078->rtc))
return PTR_ERR(sd3078->rtc);
sd3078->rtc->ops = &sd3078_rtc_ops;
sd3078->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
sd3078->rtc->range_max = RTC_TIMESTAMP_END_2099;
ret = devm_rtc_register_device(sd3078->rtc);
if (ret)
return ret;
sd3078_enable_reg_write(sd3078);
return 0;
}
static const struct i2c_device_id sd3078_id[] = {
{"sd3078", 0},
{ }
};
MODULE_DEVICE_TABLE(i2c, sd3078_id);
static const __maybe_unused struct of_device_id rtc_dt_match[] = {
{ .compatible = "whwave,sd3078" },
{},
};
MODULE_DEVICE_TABLE(of, rtc_dt_match);
static struct i2c_driver sd3078_driver = {
.driver = {
.name = "sd3078",
.of_match_table = of_match_ptr(rtc_dt_match),
},
.probe = sd3078_probe,
.id_table = sd3078_id,
};
module_i2c_driver(sd3078_driver);
MODULE_AUTHOR("Dianlong Li <[email protected]>");
MODULE_DESCRIPTION("SD3078 RTC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-sd3078.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RTC subsystem, interface functions
*
* Copyright (C) 2005 Tower Technologies
* Author: Alessandro Zummo <[email protected]>
*
* based on arch/arm/common/rtctime.c
*/
#include <linux/rtc.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/log2.h>
#include <linux/workqueue.h>
#define CREATE_TRACE_POINTS
#include <trace/events/rtc.h>
static int rtc_timer_enqueue(struct rtc_device *rtc, struct rtc_timer *timer);
static void rtc_timer_remove(struct rtc_device *rtc, struct rtc_timer *timer);
static void rtc_add_offset(struct rtc_device *rtc, struct rtc_time *tm)
{
time64_t secs;
if (!rtc->offset_secs)
return;
secs = rtc_tm_to_time64(tm);
/*
* Since the reading time values from RTC device are always in the RTC
* original valid range, but we need to skip the overlapped region
* between expanded range and original range, which is no need to add
* the offset.
*/
if ((rtc->start_secs > rtc->range_min && secs >= rtc->start_secs) ||
(rtc->start_secs < rtc->range_min &&
secs <= (rtc->start_secs + rtc->range_max - rtc->range_min)))
return;
rtc_time64_to_tm(secs + rtc->offset_secs, tm);
}
static void rtc_subtract_offset(struct rtc_device *rtc, struct rtc_time *tm)
{
time64_t secs;
if (!rtc->offset_secs)
return;
secs = rtc_tm_to_time64(tm);
/*
* If the setting time values are in the valid range of RTC hardware
* device, then no need to subtract the offset when setting time to RTC
* device. Otherwise we need to subtract the offset to make the time
* values are valid for RTC hardware device.
*/
if (secs >= rtc->range_min && secs <= rtc->range_max)
return;
rtc_time64_to_tm(secs - rtc->offset_secs, tm);
}
static int rtc_valid_range(struct rtc_device *rtc, struct rtc_time *tm)
{
if (rtc->range_min != rtc->range_max) {
time64_t time = rtc_tm_to_time64(tm);
time64_t range_min = rtc->set_start_time ? rtc->start_secs :
rtc->range_min;
timeu64_t range_max = rtc->set_start_time ?
(rtc->start_secs + rtc->range_max - rtc->range_min) :
rtc->range_max;
if (time < range_min || time > range_max)
return -ERANGE;
}
return 0;
}
static int __rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm)
{
int err;
if (!rtc->ops) {
err = -ENODEV;
} else if (!rtc->ops->read_time) {
err = -EINVAL;
} else {
memset(tm, 0, sizeof(struct rtc_time));
err = rtc->ops->read_time(rtc->dev.parent, tm);
if (err < 0) {
dev_dbg(&rtc->dev, "read_time: fail to read: %d\n",
err);
return err;
}
rtc_add_offset(rtc, tm);
err = rtc_valid_tm(tm);
if (err < 0)
dev_dbg(&rtc->dev, "read_time: rtc_time isn't valid\n");
}
return err;
}
int rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm)
{
int err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
err = __rtc_read_time(rtc, tm);
mutex_unlock(&rtc->ops_lock);
trace_rtc_read_time(rtc_tm_to_time64(tm), err);
return err;
}
EXPORT_SYMBOL_GPL(rtc_read_time);
int rtc_set_time(struct rtc_device *rtc, struct rtc_time *tm)
{
int err, uie;
err = rtc_valid_tm(tm);
if (err != 0)
return err;
err = rtc_valid_range(rtc, tm);
if (err)
return err;
rtc_subtract_offset(rtc, tm);
#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
uie = rtc->uie_rtctimer.enabled || rtc->uie_irq_active;
#else
uie = rtc->uie_rtctimer.enabled;
#endif
if (uie) {
err = rtc_update_irq_enable(rtc, 0);
if (err)
return err;
}
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
if (!rtc->ops)
err = -ENODEV;
else if (rtc->ops->set_time)
err = rtc->ops->set_time(rtc->dev.parent, tm);
else
err = -EINVAL;
pm_stay_awake(rtc->dev.parent);
mutex_unlock(&rtc->ops_lock);
/* A timer might have just expired */
schedule_work(&rtc->irqwork);
if (uie) {
err = rtc_update_irq_enable(rtc, 1);
if (err)
return err;
}
trace_rtc_set_time(rtc_tm_to_time64(tm), err);
return err;
}
EXPORT_SYMBOL_GPL(rtc_set_time);
static int rtc_read_alarm_internal(struct rtc_device *rtc,
struct rtc_wkalrm *alarm)
{
int err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
if (!rtc->ops) {
err = -ENODEV;
} else if (!test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->read_alarm) {
err = -EINVAL;
} else {
alarm->enabled = 0;
alarm->pending = 0;
alarm->time.tm_sec = -1;
alarm->time.tm_min = -1;
alarm->time.tm_hour = -1;
alarm->time.tm_mday = -1;
alarm->time.tm_mon = -1;
alarm->time.tm_year = -1;
alarm->time.tm_wday = -1;
alarm->time.tm_yday = -1;
alarm->time.tm_isdst = -1;
err = rtc->ops->read_alarm(rtc->dev.parent, alarm);
}
mutex_unlock(&rtc->ops_lock);
trace_rtc_read_alarm(rtc_tm_to_time64(&alarm->time), err);
return err;
}
int __rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
{
int err;
struct rtc_time before, now;
int first_time = 1;
time64_t t_now, t_alm;
enum { none, day, month, year } missing = none;
unsigned int days;
/* The lower level RTC driver may return -1 in some fields,
* creating invalid alarm->time values, for reasons like:
*
* - The hardware may not be capable of filling them in;
* many alarms match only on time-of-day fields, not
* day/month/year calendar data.
*
* - Some hardware uses illegal values as "wildcard" match
* values, which non-Linux firmware (like a BIOS) may try
* to set up as e.g. "alarm 15 minutes after each hour".
* Linux uses only oneshot alarms.
*
* When we see that here, we deal with it by using values from
* a current RTC timestamp for any missing (-1) values. The
* RTC driver prevents "periodic alarm" modes.
*
* But this can be racey, because some fields of the RTC timestamp
* may have wrapped in the interval since we read the RTC alarm,
* which would lead to us inserting inconsistent values in place
* of the -1 fields.
*
* Reading the alarm and timestamp in the reverse sequence
* would have the same race condition, and not solve the issue.
*
* So, we must first read the RTC timestamp,
* then read the RTC alarm value,
* and then read a second RTC timestamp.
*
* If any fields of the second timestamp have changed
* when compared with the first timestamp, then we know
* our timestamp may be inconsistent with that used by
* the low-level rtc_read_alarm_internal() function.
*
* So, when the two timestamps disagree, we just loop and do
* the process again to get a fully consistent set of values.
*
* This could all instead be done in the lower level driver,
* but since more than one lower level RTC implementation needs it,
* then it's probably best to do it here instead of there..
*/
/* Get the "before" timestamp */
err = rtc_read_time(rtc, &before);
if (err < 0)
return err;
do {
if (!first_time)
memcpy(&before, &now, sizeof(struct rtc_time));
first_time = 0;
/* get the RTC alarm values, which may be incomplete */
err = rtc_read_alarm_internal(rtc, alarm);
if (err)
return err;
/* full-function RTCs won't have such missing fields */
if (rtc_valid_tm(&alarm->time) == 0) {
rtc_add_offset(rtc, &alarm->time);
return 0;
}
/* get the "after" timestamp, to detect wrapped fields */
err = rtc_read_time(rtc, &now);
if (err < 0)
return err;
/* note that tm_sec is a "don't care" value here: */
} while (before.tm_min != now.tm_min ||
before.tm_hour != now.tm_hour ||
before.tm_mon != now.tm_mon ||
before.tm_year != now.tm_year);
/* Fill in the missing alarm fields using the timestamp; we
* know there's at least one since alarm->time is invalid.
*/
if (alarm->time.tm_sec == -1)
alarm->time.tm_sec = now.tm_sec;
if (alarm->time.tm_min == -1)
alarm->time.tm_min = now.tm_min;
if (alarm->time.tm_hour == -1)
alarm->time.tm_hour = now.tm_hour;
/* For simplicity, only support date rollover for now */
if (alarm->time.tm_mday < 1 || alarm->time.tm_mday > 31) {
alarm->time.tm_mday = now.tm_mday;
missing = day;
}
if ((unsigned int)alarm->time.tm_mon >= 12) {
alarm->time.tm_mon = now.tm_mon;
if (missing == none)
missing = month;
}
if (alarm->time.tm_year == -1) {
alarm->time.tm_year = now.tm_year;
if (missing == none)
missing = year;
}
/* Can't proceed if alarm is still invalid after replacing
* missing fields.
*/
err = rtc_valid_tm(&alarm->time);
if (err)
goto done;
/* with luck, no rollover is needed */
t_now = rtc_tm_to_time64(&now);
t_alm = rtc_tm_to_time64(&alarm->time);
if (t_now < t_alm)
goto done;
switch (missing) {
/* 24 hour rollover ... if it's now 10am Monday, an alarm that
* that will trigger at 5am will do so at 5am Tuesday, which
* could also be in the next month or year. This is a common
* case, especially for PCs.
*/
case day:
dev_dbg(&rtc->dev, "alarm rollover: %s\n", "day");
t_alm += 24 * 60 * 60;
rtc_time64_to_tm(t_alm, &alarm->time);
break;
/* Month rollover ... if it's the 31th, an alarm on the 3rd will
* be next month. An alarm matching on the 30th, 29th, or 28th
* may end up in the month after that! Many newer PCs support
* this type of alarm.
*/
case month:
dev_dbg(&rtc->dev, "alarm rollover: %s\n", "month");
do {
if (alarm->time.tm_mon < 11) {
alarm->time.tm_mon++;
} else {
alarm->time.tm_mon = 0;
alarm->time.tm_year++;
}
days = rtc_month_days(alarm->time.tm_mon,
alarm->time.tm_year);
} while (days < alarm->time.tm_mday);
break;
/* Year rollover ... easy except for leap years! */
case year:
dev_dbg(&rtc->dev, "alarm rollover: %s\n", "year");
do {
alarm->time.tm_year++;
} while (!is_leap_year(alarm->time.tm_year + 1900) &&
rtc_valid_tm(&alarm->time) != 0);
break;
default:
dev_warn(&rtc->dev, "alarm rollover not handled\n");
}
err = rtc_valid_tm(&alarm->time);
done:
if (err && alarm->enabled)
dev_warn(&rtc->dev, "invalid alarm value: %ptR\n",
&alarm->time);
return err;
}
int rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
{
int err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
if (!rtc->ops) {
err = -ENODEV;
} else if (!test_bit(RTC_FEATURE_ALARM, rtc->features)) {
err = -EINVAL;
} else {
memset(alarm, 0, sizeof(struct rtc_wkalrm));
alarm->enabled = rtc->aie_timer.enabled;
alarm->time = rtc_ktime_to_tm(rtc->aie_timer.node.expires);
}
mutex_unlock(&rtc->ops_lock);
trace_rtc_read_alarm(rtc_tm_to_time64(&alarm->time), err);
return err;
}
EXPORT_SYMBOL_GPL(rtc_read_alarm);
static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
{
struct rtc_time tm;
time64_t now, scheduled;
int err;
err = rtc_valid_tm(&alarm->time);
if (err)
return err;
scheduled = rtc_tm_to_time64(&alarm->time);
/* Make sure we're not setting alarms in the past */
err = __rtc_read_time(rtc, &tm);
if (err)
return err;
now = rtc_tm_to_time64(&tm);
if (scheduled <= now)
return -ETIME;
/*
* XXX - We just checked to make sure the alarm time is not
* in the past, but there is still a race window where if
* the is alarm set for the next second and the second ticks
* over right here, before we set the alarm.
*/
rtc_subtract_offset(rtc, &alarm->time);
if (!rtc->ops)
err = -ENODEV;
else if (!test_bit(RTC_FEATURE_ALARM, rtc->features))
err = -EINVAL;
else
err = rtc->ops->set_alarm(rtc->dev.parent, alarm);
trace_rtc_set_alarm(rtc_tm_to_time64(&alarm->time), err);
return err;
}
int rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
{
ktime_t alarm_time;
int err;
if (!rtc->ops)
return -ENODEV;
else if (!test_bit(RTC_FEATURE_ALARM, rtc->features))
return -EINVAL;
err = rtc_valid_tm(&alarm->time);
if (err != 0)
return err;
err = rtc_valid_range(rtc, &alarm->time);
if (err)
return err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
if (rtc->aie_timer.enabled)
rtc_timer_remove(rtc, &rtc->aie_timer);
alarm_time = rtc_tm_to_ktime(alarm->time);
/*
* Round down so we never miss a deadline, checking for past deadline is
* done in __rtc_set_alarm
*/
if (test_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->features))
alarm_time = ktime_sub_ns(alarm_time, (u64)alarm->time.tm_sec * NSEC_PER_SEC);
rtc->aie_timer.node.expires = alarm_time;
rtc->aie_timer.period = 0;
if (alarm->enabled)
err = rtc_timer_enqueue(rtc, &rtc->aie_timer);
mutex_unlock(&rtc->ops_lock);
return err;
}
EXPORT_SYMBOL_GPL(rtc_set_alarm);
/* Called once per device from rtc_device_register */
int rtc_initialize_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
{
int err;
struct rtc_time now;
err = rtc_valid_tm(&alarm->time);
if (err != 0)
return err;
err = rtc_read_time(rtc, &now);
if (err)
return err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
rtc->aie_timer.node.expires = rtc_tm_to_ktime(alarm->time);
rtc->aie_timer.period = 0;
/* Alarm has to be enabled & in the future for us to enqueue it */
if (alarm->enabled && (rtc_tm_to_ktime(now) <
rtc->aie_timer.node.expires)) {
rtc->aie_timer.enabled = 1;
timerqueue_add(&rtc->timerqueue, &rtc->aie_timer.node);
trace_rtc_timer_enqueue(&rtc->aie_timer);
}
mutex_unlock(&rtc->ops_lock);
return err;
}
EXPORT_SYMBOL_GPL(rtc_initialize_alarm);
int rtc_alarm_irq_enable(struct rtc_device *rtc, unsigned int enabled)
{
int err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
if (rtc->aie_timer.enabled != enabled) {
if (enabled)
err = rtc_timer_enqueue(rtc, &rtc->aie_timer);
else
rtc_timer_remove(rtc, &rtc->aie_timer);
}
if (err)
/* nothing */;
else if (!rtc->ops)
err = -ENODEV;
else if (!test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->alarm_irq_enable)
err = -EINVAL;
else
err = rtc->ops->alarm_irq_enable(rtc->dev.parent, enabled);
mutex_unlock(&rtc->ops_lock);
trace_rtc_alarm_irq_enable(enabled, err);
return err;
}
EXPORT_SYMBOL_GPL(rtc_alarm_irq_enable);
int rtc_update_irq_enable(struct rtc_device *rtc, unsigned int enabled)
{
int err;
err = mutex_lock_interruptible(&rtc->ops_lock);
if (err)
return err;
#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
if (enabled == 0 && rtc->uie_irq_active) {
mutex_unlock(&rtc->ops_lock);
return rtc_dev_update_irq_enable_emul(rtc, 0);
}
#endif
/* make sure we're changing state */
if (rtc->uie_rtctimer.enabled == enabled)
goto out;
if (!test_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->features) ||
!test_bit(RTC_FEATURE_ALARM, rtc->features)) {
mutex_unlock(&rtc->ops_lock);
#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
return rtc_dev_update_irq_enable_emul(rtc, enabled);
#else
return -EINVAL;
#endif
}
if (enabled) {
struct rtc_time tm;
ktime_t now, onesec;
err = __rtc_read_time(rtc, &tm);
if (err)
goto out;
onesec = ktime_set(1, 0);
now = rtc_tm_to_ktime(tm);
rtc->uie_rtctimer.node.expires = ktime_add(now, onesec);
rtc->uie_rtctimer.period = ktime_set(1, 0);
err = rtc_timer_enqueue(rtc, &rtc->uie_rtctimer);
} else {
rtc_timer_remove(rtc, &rtc->uie_rtctimer);
}
out:
mutex_unlock(&rtc->ops_lock);
return err;
}
EXPORT_SYMBOL_GPL(rtc_update_irq_enable);
/**
* rtc_handle_legacy_irq - AIE, UIE and PIE event hook
* @rtc: pointer to the rtc device
* @num: number of occurence of the event
* @mode: type of the event, RTC_AF, RTC_UF of RTC_PF
*
* This function is called when an AIE, UIE or PIE mode interrupt
* has occurred (or been emulated).
*
*/
void rtc_handle_legacy_irq(struct rtc_device *rtc, int num, int mode)
{
unsigned long flags;
/* mark one irq of the appropriate mode */
spin_lock_irqsave(&rtc->irq_lock, flags);
rtc->irq_data = (rtc->irq_data + (num << 8)) | (RTC_IRQF | mode);
spin_unlock_irqrestore(&rtc->irq_lock, flags);
wake_up_interruptible(&rtc->irq_queue);
kill_fasync(&rtc->async_queue, SIGIO, POLL_IN);
}
/**
* rtc_aie_update_irq - AIE mode rtctimer hook
* @rtc: pointer to the rtc_device
*
* This functions is called when the aie_timer expires.
*/
void rtc_aie_update_irq(struct rtc_device *rtc)
{
rtc_handle_legacy_irq(rtc, 1, RTC_AF);
}
/**
* rtc_uie_update_irq - UIE mode rtctimer hook
* @rtc: pointer to the rtc_device
*
* This functions is called when the uie_timer expires.
*/
void rtc_uie_update_irq(struct rtc_device *rtc)
{
rtc_handle_legacy_irq(rtc, 1, RTC_UF);
}
/**
* rtc_pie_update_irq - PIE mode hrtimer hook
* @timer: pointer to the pie mode hrtimer
*
* This function is used to emulate PIE mode interrupts
* using an hrtimer. This function is called when the periodic
* hrtimer expires.
*/
enum hrtimer_restart rtc_pie_update_irq(struct hrtimer *timer)
{
struct rtc_device *rtc;
ktime_t period;
u64 count;
rtc = container_of(timer, struct rtc_device, pie_timer);
period = NSEC_PER_SEC / rtc->irq_freq;
count = hrtimer_forward_now(timer, period);
rtc_handle_legacy_irq(rtc, count, RTC_PF);
return HRTIMER_RESTART;
}
/**
* rtc_update_irq - Triggered when a RTC interrupt occurs.
* @rtc: the rtc device
* @num: how many irqs are being reported (usually one)
* @events: mask of RTC_IRQF with one or more of RTC_PF, RTC_AF, RTC_UF
* Context: any
*/
void rtc_update_irq(struct rtc_device *rtc,
unsigned long num, unsigned long events)
{
if (IS_ERR_OR_NULL(rtc))
return;
pm_stay_awake(rtc->dev.parent);
schedule_work(&rtc->irqwork);
}
EXPORT_SYMBOL_GPL(rtc_update_irq);
struct rtc_device *rtc_class_open(const char *name)
{
struct device *dev;
struct rtc_device *rtc = NULL;
dev = class_find_device_by_name(rtc_class, name);
if (dev)
rtc = to_rtc_device(dev);
if (rtc) {
if (!try_module_get(rtc->owner)) {
put_device(dev);
rtc = NULL;
}
}
return rtc;
}
EXPORT_SYMBOL_GPL(rtc_class_open);
void rtc_class_close(struct rtc_device *rtc)
{
module_put(rtc->owner);
put_device(&rtc->dev);
}
EXPORT_SYMBOL_GPL(rtc_class_close);
static int rtc_update_hrtimer(struct rtc_device *rtc, int enabled)
{
/*
* We always cancel the timer here first, because otherwise
* we could run into BUG_ON(timer->state != HRTIMER_STATE_CALLBACK);
* when we manage to start the timer before the callback
* returns HRTIMER_RESTART.
*
* We cannot use hrtimer_cancel() here as a running callback
* could be blocked on rtc->irq_task_lock and hrtimer_cancel()
* would spin forever.
*/
if (hrtimer_try_to_cancel(&rtc->pie_timer) < 0)
return -1;
if (enabled) {
ktime_t period = NSEC_PER_SEC / rtc->irq_freq;
hrtimer_start(&rtc->pie_timer, period, HRTIMER_MODE_REL);
}
return 0;
}
/**
* rtc_irq_set_state - enable/disable 2^N Hz periodic IRQs
* @rtc: the rtc device
* @enabled: true to enable periodic IRQs
* Context: any
*
* Note that rtc_irq_set_freq() should previously have been used to
* specify the desired frequency of periodic IRQ.
*/
int rtc_irq_set_state(struct rtc_device *rtc, int enabled)
{
int err = 0;
while (rtc_update_hrtimer(rtc, enabled) < 0)
cpu_relax();
rtc->pie_enabled = enabled;
trace_rtc_irq_set_state(enabled, err);
return err;
}
/**
* rtc_irq_set_freq - set 2^N Hz periodic IRQ frequency for IRQ
* @rtc: the rtc device
* @freq: positive frequency
* Context: any
*
* Note that rtc_irq_set_state() is used to enable or disable the
* periodic IRQs.
*/
int rtc_irq_set_freq(struct rtc_device *rtc, int freq)
{
int err = 0;
if (freq <= 0 || freq > RTC_MAX_FREQ)
return -EINVAL;
rtc->irq_freq = freq;
while (rtc->pie_enabled && rtc_update_hrtimer(rtc, 1) < 0)
cpu_relax();
trace_rtc_irq_set_freq(freq, err);
return err;
}
/**
* rtc_timer_enqueue - Adds a rtc_timer to the rtc_device timerqueue
* @rtc: rtc device
* @timer: timer being added.
*
* Enqueues a timer onto the rtc devices timerqueue and sets
* the next alarm event appropriately.
*
* Sets the enabled bit on the added timer.
*
* Must hold ops_lock for proper serialization of timerqueue
*/
static int rtc_timer_enqueue(struct rtc_device *rtc, struct rtc_timer *timer)
{
struct timerqueue_node *next = timerqueue_getnext(&rtc->timerqueue);
struct rtc_time tm;
ktime_t now;
int err;
err = __rtc_read_time(rtc, &tm);
if (err)
return err;
timer->enabled = 1;
now = rtc_tm_to_ktime(tm);
/* Skip over expired timers */
while (next) {
if (next->expires >= now)
break;
next = timerqueue_iterate_next(next);
}
timerqueue_add(&rtc->timerqueue, &timer->node);
trace_rtc_timer_enqueue(timer);
if (!next || ktime_before(timer->node.expires, next->expires)) {
struct rtc_wkalrm alarm;
alarm.time = rtc_ktime_to_tm(timer->node.expires);
alarm.enabled = 1;
err = __rtc_set_alarm(rtc, &alarm);
if (err == -ETIME) {
pm_stay_awake(rtc->dev.parent);
schedule_work(&rtc->irqwork);
} else if (err) {
timerqueue_del(&rtc->timerqueue, &timer->node);
trace_rtc_timer_dequeue(timer);
timer->enabled = 0;
return err;
}
}
return 0;
}
static void rtc_alarm_disable(struct rtc_device *rtc)
{
if (!rtc->ops || !test_bit(RTC_FEATURE_ALARM, rtc->features) || !rtc->ops->alarm_irq_enable)
return;
rtc->ops->alarm_irq_enable(rtc->dev.parent, false);
trace_rtc_alarm_irq_enable(0, 0);
}
/**
* rtc_timer_remove - Removes a rtc_timer from the rtc_device timerqueue
* @rtc: rtc device
* @timer: timer being removed.
*
* Removes a timer onto the rtc devices timerqueue and sets
* the next alarm event appropriately.
*
* Clears the enabled bit on the removed timer.
*
* Must hold ops_lock for proper serialization of timerqueue
*/
static void rtc_timer_remove(struct rtc_device *rtc, struct rtc_timer *timer)
{
struct timerqueue_node *next = timerqueue_getnext(&rtc->timerqueue);
timerqueue_del(&rtc->timerqueue, &timer->node);
trace_rtc_timer_dequeue(timer);
timer->enabled = 0;
if (next == &timer->node) {
struct rtc_wkalrm alarm;
int err;
next = timerqueue_getnext(&rtc->timerqueue);
if (!next) {
rtc_alarm_disable(rtc);
return;
}
alarm.time = rtc_ktime_to_tm(next->expires);
alarm.enabled = 1;
err = __rtc_set_alarm(rtc, &alarm);
if (err == -ETIME) {
pm_stay_awake(rtc->dev.parent);
schedule_work(&rtc->irqwork);
}
}
}
/**
* rtc_timer_do_work - Expires rtc timers
* @work: work item
*
* Expires rtc timers. Reprograms next alarm event if needed.
* Called via worktask.
*
* Serializes access to timerqueue via ops_lock mutex
*/
void rtc_timer_do_work(struct work_struct *work)
{
struct rtc_timer *timer;
struct timerqueue_node *next;
ktime_t now;
struct rtc_time tm;
struct rtc_device *rtc =
container_of(work, struct rtc_device, irqwork);
mutex_lock(&rtc->ops_lock);
again:
__rtc_read_time(rtc, &tm);
now = rtc_tm_to_ktime(tm);
while ((next = timerqueue_getnext(&rtc->timerqueue))) {
if (next->expires > now)
break;
/* expire timer */
timer = container_of(next, struct rtc_timer, node);
timerqueue_del(&rtc->timerqueue, &timer->node);
trace_rtc_timer_dequeue(timer);
timer->enabled = 0;
if (timer->func)
timer->func(timer->rtc);
trace_rtc_timer_fired(timer);
/* Re-add/fwd periodic timers */
if (ktime_to_ns(timer->period)) {
timer->node.expires = ktime_add(timer->node.expires,
timer->period);
timer->enabled = 1;
timerqueue_add(&rtc->timerqueue, &timer->node);
trace_rtc_timer_enqueue(timer);
}
}
/* Set next alarm */
if (next) {
struct rtc_wkalrm alarm;
int err;
int retry = 3;
alarm.time = rtc_ktime_to_tm(next->expires);
alarm.enabled = 1;
reprogram:
err = __rtc_set_alarm(rtc, &alarm);
if (err == -ETIME) {
goto again;
} else if (err) {
if (retry-- > 0)
goto reprogram;
timer = container_of(next, struct rtc_timer, node);
timerqueue_del(&rtc->timerqueue, &timer->node);
trace_rtc_timer_dequeue(timer);
timer->enabled = 0;
dev_err(&rtc->dev, "__rtc_set_alarm: err=%d\n", err);
goto again;
}
} else {
rtc_alarm_disable(rtc);
}
pm_relax(rtc->dev.parent);
mutex_unlock(&rtc->ops_lock);
}
/* rtc_timer_init - Initializes an rtc_timer
* @timer: timer to be intiialized
* @f: function pointer to be called when timer fires
* @rtc: pointer to the rtc_device
*
* Kernel interface to initializing an rtc_timer.
*/
void rtc_timer_init(struct rtc_timer *timer, void (*f)(struct rtc_device *r),
struct rtc_device *rtc)
{
timerqueue_init(&timer->node);
timer->enabled = 0;
timer->func = f;
timer->rtc = rtc;
}
/* rtc_timer_start - Sets an rtc_timer to fire in the future
* @ rtc: rtc device to be used
* @ timer: timer being set
* @ expires: time at which to expire the timer
* @ period: period that the timer will recur
*
* Kernel interface to set an rtc_timer
*/
int rtc_timer_start(struct rtc_device *rtc, struct rtc_timer *timer,
ktime_t expires, ktime_t period)
{
int ret = 0;
mutex_lock(&rtc->ops_lock);
if (timer->enabled)
rtc_timer_remove(rtc, timer);
timer->node.expires = expires;
timer->period = period;
ret = rtc_timer_enqueue(rtc, timer);
mutex_unlock(&rtc->ops_lock);
return ret;
}
/* rtc_timer_cancel - Stops an rtc_timer
* @ rtc: rtc device to be used
* @ timer: timer being set
*
* Kernel interface to cancel an rtc_timer
*/
void rtc_timer_cancel(struct rtc_device *rtc, struct rtc_timer *timer)
{
mutex_lock(&rtc->ops_lock);
if (timer->enabled)
rtc_timer_remove(rtc, timer);
mutex_unlock(&rtc->ops_lock);
}
/**
* rtc_read_offset - Read the amount of rtc offset in parts per billion
* @rtc: rtc device to be used
* @offset: the offset in parts per billion
*
* see below for details.
*
* Kernel interface to read rtc clock offset
* Returns 0 on success, or a negative number on error.
* If read_offset() is not implemented for the rtc, return -EINVAL
*/
int rtc_read_offset(struct rtc_device *rtc, long *offset)
{
int ret;
if (!rtc->ops)
return -ENODEV;
if (!rtc->ops->read_offset)
return -EINVAL;
mutex_lock(&rtc->ops_lock);
ret = rtc->ops->read_offset(rtc->dev.parent, offset);
mutex_unlock(&rtc->ops_lock);
trace_rtc_read_offset(*offset, ret);
return ret;
}
/**
* rtc_set_offset - Adjusts the duration of the average second
* @rtc: rtc device to be used
* @offset: the offset in parts per billion
*
* Some rtc's allow an adjustment to the average duration of a second
* to compensate for differences in the actual clock rate due to temperature,
* the crystal, capacitor, etc.
*
* The adjustment applied is as follows:
* t = t0 * (1 + offset * 1e-9)
* where t0 is the measured length of 1 RTC second with offset = 0
*
* Kernel interface to adjust an rtc clock offset.
* Return 0 on success, or a negative number on error.
* If the rtc offset is not setable (or not implemented), return -EINVAL
*/
int rtc_set_offset(struct rtc_device *rtc, long offset)
{
int ret;
if (!rtc->ops)
return -ENODEV;
if (!rtc->ops->set_offset)
return -EINVAL;
mutex_lock(&rtc->ops_lock);
ret = rtc->ops->set_offset(rtc->dev.parent, offset);
mutex_unlock(&rtc->ops_lock);
trace_rtc_set_offset(offset, ret);
return ret;
}
| linux-master | drivers/rtc/interface.c |
// SPDX-License-Identifier: GPL-2.0+
//
// RTC driver for Maxim MAX77686 and MAX77802
//
// Copyright (C) 2012 Samsung Electronics Co.Ltd
//
// based on rtc-max8997.c
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/max77686-private.h>
#include <linux/irqdomain.h>
#include <linux/regmap.h>
#define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
#define MAX77620_I2C_ADDR_RTC 0x68
#define MAX77714_I2C_ADDR_RTC 0x48
#define MAX77686_INVALID_I2C_ADDR (-1)
/* Define non existing register */
#define MAX77686_INVALID_REG (-1)
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK BIT(BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK BIT(MODEL24_SHIFT)
/* RTC Update Register1 */
#define RTC_UDR_SHIFT 0
#define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
#define RTC_RBUDR_SHIFT 4
#define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
#define REG_RTC_NONE 0xdeadbeef
/*
* MAX77802 has separate register (RTCAE1) for alarm enable instead
* using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
* as in done in MAX77686.
*/
#define MAX77802_ALARM_ENABLE_VALUE 0x77
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_MONTH,
RTC_YEAR,
RTC_MONTHDAY,
RTC_NR_TIME
};
/**
* struct max77686_rtc_driver_data - model-specific configuration
* @delay: Minimum usecs needed for a RTC update
* @mask: Mask used to read RTC registers value
* @map: Registers offset to I2C addresses map
* @alarm_enable_reg: Has a separate alarm enable register?
* @rtc_i2c_addr: I2C address for RTC block
* @rtc_irq_from_platform: RTC interrupt via platform resource
* @alarm_pending_status_reg: Pending alarm status register
* @rtc_irq_chip: RTC IRQ CHIP for regmap
* @regmap_config: regmap configuration for the chip
*/
struct max77686_rtc_driver_data {
unsigned long delay;
u8 mask;
const unsigned int *map;
bool alarm_enable_reg;
int rtc_i2c_addr;
bool rtc_irq_from_platform;
int alarm_pending_status_reg;
const struct regmap_irq_chip *rtc_irq_chip;
const struct regmap_config *regmap_config;
};
struct max77686_rtc_info {
struct device *dev;
struct i2c_client *rtc;
struct rtc_device *rtc_dev;
struct mutex lock;
struct regmap *regmap;
struct regmap *rtc_regmap;
const struct max77686_rtc_driver_data *drv_data;
struct regmap_irq_chip_data *rtc_irq_data;
int rtc_irq;
int virq;
};
enum MAX77686_RTC_OP {
MAX77686_RTC_WRITE,
MAX77686_RTC_READ,
};
/* These are not registers but just offsets that are mapped to addresses */
enum max77686_rtc_reg_offset {
REG_RTC_CONTROLM = 0,
REG_RTC_CONTROL,
REG_RTC_UPDATE0,
REG_WTSR_SMPL_CNTL,
REG_RTC_SEC,
REG_RTC_MIN,
REG_RTC_HOUR,
REG_RTC_WEEKDAY,
REG_RTC_MONTH,
REG_RTC_YEAR,
REG_RTC_MONTHDAY,
REG_ALARM1_SEC,
REG_ALARM1_MIN,
REG_ALARM1_HOUR,
REG_ALARM1_WEEKDAY,
REG_ALARM1_MONTH,
REG_ALARM1_YEAR,
REG_ALARM1_DATE,
REG_ALARM2_SEC,
REG_ALARM2_MIN,
REG_ALARM2_HOUR,
REG_ALARM2_WEEKDAY,
REG_ALARM2_MONTH,
REG_ALARM2_YEAR,
REG_ALARM2_DATE,
REG_RTC_AE1,
REG_RTC_END,
};
/* Maps RTC registers offset to the MAX77686 register addresses */
static const unsigned int max77686_map[REG_RTC_END] = {
[REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
[REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
[REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
[REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
[REG_RTC_SEC] = MAX77686_RTC_SEC,
[REG_RTC_MIN] = MAX77686_RTC_MIN,
[REG_RTC_HOUR] = MAX77686_RTC_HOUR,
[REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
[REG_RTC_MONTH] = MAX77686_RTC_MONTH,
[REG_RTC_YEAR] = MAX77686_RTC_YEAR,
[REG_RTC_MONTHDAY] = MAX77686_RTC_MONTHDAY,
[REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
[REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
[REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
[REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
[REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
[REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
[REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
[REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
[REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
[REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
[REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
[REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
[REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
[REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
[REG_RTC_AE1] = REG_RTC_NONE,
};
static const struct regmap_irq max77686_rtc_irqs[] = {
/* RTC interrupts */
REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
};
static const struct regmap_irq_chip max77686_rtc_irq_chip = {
.name = "max77686-rtc",
.status_base = MAX77686_RTC_INT,
.mask_base = MAX77686_RTC_INTM,
.num_regs = 1,
.irqs = max77686_rtc_irqs,
.num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
};
static const struct regmap_config max77686_rtc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static const struct max77686_rtc_driver_data max77686_drv_data = {
.delay = 16000,
.mask = 0x7f,
.map = max77686_map,
.alarm_enable_reg = false,
.rtc_irq_from_platform = false,
.alarm_pending_status_reg = MAX77686_REG_STATUS2,
.rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
.rtc_irq_chip = &max77686_rtc_irq_chip,
.regmap_config = &max77686_rtc_regmap_config,
};
static const struct regmap_irq_chip max77714_rtc_irq_chip = {
.name = "max77714-rtc",
.status_base = MAX77686_RTC_INT,
.mask_base = MAX77686_RTC_INTM,
.num_regs = 1,
.irqs = max77686_rtc_irqs,
.num_irqs = ARRAY_SIZE(max77686_rtc_irqs) - 1, /* no WTSR on 77714 */
};
static const struct max77686_rtc_driver_data max77714_drv_data = {
.delay = 16000,
.mask = 0x7f,
.map = max77686_map,
.alarm_enable_reg = false,
.rtc_irq_from_platform = false,
/* On MAX77714 RTCA1 is BIT 1 of RTCINT (0x00). Not supported by this driver. */
.alarm_pending_status_reg = MAX77686_INVALID_REG,
.rtc_i2c_addr = MAX77714_I2C_ADDR_RTC,
.rtc_irq_chip = &max77714_rtc_irq_chip,
.regmap_config = &max77686_rtc_regmap_config,
};
static const struct regmap_config max77620_rtc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.use_single_write = true,
};
static const struct max77686_rtc_driver_data max77620_drv_data = {
.delay = 16000,
.mask = 0x7f,
.map = max77686_map,
.alarm_enable_reg = false,
.rtc_irq_from_platform = true,
.alarm_pending_status_reg = MAX77686_INVALID_REG,
.rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
.rtc_irq_chip = &max77686_rtc_irq_chip,
.regmap_config = &max77620_rtc_regmap_config,
};
static const unsigned int max77802_map[REG_RTC_END] = {
[REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
[REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
[REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
[REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
[REG_RTC_SEC] = MAX77802_RTC_SEC,
[REG_RTC_MIN] = MAX77802_RTC_MIN,
[REG_RTC_HOUR] = MAX77802_RTC_HOUR,
[REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
[REG_RTC_MONTH] = MAX77802_RTC_MONTH,
[REG_RTC_YEAR] = MAX77802_RTC_YEAR,
[REG_RTC_MONTHDAY] = MAX77802_RTC_MONTHDAY,
[REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
[REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
[REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
[REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
[REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
[REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
[REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
[REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
[REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
[REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
[REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
[REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
[REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
[REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
[REG_RTC_AE1] = MAX77802_RTC_AE1,
};
static const struct regmap_irq_chip max77802_rtc_irq_chip = {
.name = "max77802-rtc",
.status_base = MAX77802_RTC_INT,
.mask_base = MAX77802_RTC_INTM,
.num_regs = 1,
.irqs = max77686_rtc_irqs, /* same masks as 77686 */
.num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
};
static const struct max77686_rtc_driver_data max77802_drv_data = {
.delay = 200,
.mask = 0xff,
.map = max77802_map,
.alarm_enable_reg = true,
.rtc_irq_from_platform = false,
.alarm_pending_status_reg = MAX77686_REG_STATUS2,
.rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
.rtc_irq_chip = &max77802_rtc_irq_chip,
};
static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
struct max77686_rtc_info *info)
{
u8 mask = info->drv_data->mask;
tm->tm_sec = data[RTC_SEC] & mask;
tm->tm_min = data[RTC_MIN] & mask;
tm->tm_hour = data[RTC_HOUR] & 0x1f;
/* Only a single bit is set in data[], so fls() would be equivalent */
tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
tm->tm_mday = data[RTC_MONTHDAY] & 0x1f;
tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
tm->tm_year = data[RTC_YEAR] & mask;
tm->tm_yday = 0;
tm->tm_isdst = 0;
/*
* MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
* year values are just 0..99 so add 100 to support up to 2099.
*/
if (!info->drv_data->alarm_enable_reg)
tm->tm_year += 100;
}
static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
struct max77686_rtc_info *info)
{
data[RTC_SEC] = tm->tm_sec;
data[RTC_MIN] = tm->tm_min;
data[RTC_HOUR] = tm->tm_hour;
data[RTC_WEEKDAY] = 1 << tm->tm_wday;
data[RTC_MONTHDAY] = tm->tm_mday;
data[RTC_MONTH] = tm->tm_mon + 1;
if (info->drv_data->alarm_enable_reg) {
data[RTC_YEAR] = tm->tm_year;
return 0;
}
data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
if (tm->tm_year < 100) {
dev_err(info->dev, "RTC cannot handle the year %d.\n",
1900 + tm->tm_year);
return -EINVAL;
}
return 0;
}
static int max77686_rtc_update(struct max77686_rtc_info *info,
enum MAX77686_RTC_OP op)
{
int ret;
unsigned int data;
unsigned long delay = info->drv_data->delay;
if (op == MAX77686_RTC_WRITE)
data = 1 << RTC_UDR_SHIFT;
else
data = 1 << RTC_RBUDR_SHIFT;
ret = regmap_update_bits(info->rtc_regmap,
info->drv_data->map[REG_RTC_UPDATE0],
data, data);
if (ret < 0)
dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
ret, data);
else {
/* Minimum delay required before RTC update. */
usleep_range(delay, delay * 2);
}
return ret;
}
static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
mutex_lock(&info->lock);
ret = max77686_rtc_update(info, MAX77686_RTC_READ);
if (ret < 0)
goto out;
ret = regmap_bulk_read(info->rtc_regmap,
info->drv_data->map[REG_RTC_SEC],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
goto out;
}
max77686_rtc_data_to_tm(data, tm, info);
out:
mutex_unlock(&info->lock);
return ret;
}
static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = max77686_rtc_tm_to_data(tm, data, info);
if (ret < 0)
return ret;
mutex_lock(&info->lock);
ret = regmap_bulk_write(info->rtc_regmap,
info->drv_data->map[REG_RTC_SEC],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
out:
mutex_unlock(&info->lock);
return ret;
}
static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
unsigned int val;
const unsigned int *map = info->drv_data->map;
int i, ret;
mutex_lock(&info->lock);
ret = max77686_rtc_update(info, MAX77686_RTC_READ);
if (ret < 0)
goto out;
ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
goto out;
}
max77686_rtc_data_to_tm(data, &alrm->time, info);
alrm->enabled = 0;
if (info->drv_data->alarm_enable_reg) {
if (map[REG_RTC_AE1] == REG_RTC_NONE) {
ret = -EINVAL;
dev_err(info->dev,
"alarm enable register not set(%d)\n", ret);
goto out;
}
ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
if (ret < 0) {
dev_err(info->dev,
"fail to read alarm enable(%d)\n", ret);
goto out;
}
if (val)
alrm->enabled = 1;
} else {
for (i = 0; i < ARRAY_SIZE(data); i++) {
if (data[i] & ALARM_ENABLE_MASK) {
alrm->enabled = 1;
break;
}
}
}
alrm->pending = 0;
if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
goto out;
ret = regmap_read(info->regmap,
info->drv_data->alarm_pending_status_reg, &val);
if (ret < 0) {
dev_err(info->dev,
"Fail to read alarm pending status reg(%d)\n", ret);
goto out;
}
if (val & (1 << 4)) /* RTCA1 */
alrm->pending = 1;
out:
mutex_unlock(&info->lock);
return ret;
}
static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
{
u8 data[RTC_NR_TIME];
int ret, i;
struct rtc_time tm;
const unsigned int *map = info->drv_data->map;
if (!mutex_is_locked(&info->lock))
dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
ret = max77686_rtc_update(info, MAX77686_RTC_READ);
if (ret < 0)
goto out;
if (info->drv_data->alarm_enable_reg) {
if (map[REG_RTC_AE1] == REG_RTC_NONE) {
ret = -EINVAL;
dev_err(info->dev,
"alarm enable register not set(%d)\n", ret);
goto out;
}
ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
} else {
ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
goto out;
}
max77686_rtc_data_to_tm(data, &tm, info);
for (i = 0; i < ARRAY_SIZE(data); i++)
data[i] &= ~ALARM_ENABLE_MASK;
ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
data, ARRAY_SIZE(data));
}
if (ret < 0) {
dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
out:
return ret;
}
static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
{
u8 data[RTC_NR_TIME];
int ret;
struct rtc_time tm;
const unsigned int *map = info->drv_data->map;
if (!mutex_is_locked(&info->lock))
dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
ret = max77686_rtc_update(info, MAX77686_RTC_READ);
if (ret < 0)
goto out;
if (info->drv_data->alarm_enable_reg) {
ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
MAX77802_ALARM_ENABLE_VALUE);
} else {
ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
goto out;
}
max77686_rtc_data_to_tm(data, &tm, info);
data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
if (data[RTC_MONTH] & 0xf)
data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
if (data[RTC_YEAR] & info->drv_data->mask)
data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
if (data[RTC_MONTHDAY] & 0x1f)
data[RTC_MONTHDAY] |= (1 << ALARM_ENABLE_SHIFT);
ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
data, ARRAY_SIZE(data));
}
if (ret < 0) {
dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
out:
return ret;
}
static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
if (ret < 0)
return ret;
mutex_lock(&info->lock);
ret = max77686_rtc_stop_alarm(info);
if (ret < 0)
goto out;
ret = regmap_bulk_write(info->rtc_regmap,
info->drv_data->map[REG_ALARM1_SEC],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
goto out;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
if (ret < 0)
goto out;
if (alrm->enabled)
ret = max77686_rtc_start_alarm(info);
out:
mutex_unlock(&info->lock);
return ret;
}
static int max77686_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
int ret;
mutex_lock(&info->lock);
if (enabled)
ret = max77686_rtc_start_alarm(info);
else
ret = max77686_rtc_stop_alarm(info);
mutex_unlock(&info->lock);
return ret;
}
static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
{
struct max77686_rtc_info *info = data;
dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static const struct rtc_class_ops max77686_rtc_ops = {
.read_time = max77686_rtc_read_time,
.set_time = max77686_rtc_set_time,
.read_alarm = max77686_rtc_read_alarm,
.set_alarm = max77686_rtc_set_alarm,
.alarm_irq_enable = max77686_rtc_alarm_irq_enable,
};
static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
{
u8 data[2];
int ret;
/* Set RTC control register : Binary mode, 24hour mdoe */
data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
ret = regmap_bulk_write(info->rtc_regmap,
info->drv_data->map[REG_RTC_CONTROLM],
data, ARRAY_SIZE(data));
if (ret < 0) {
dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
return ret;
}
ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
return ret;
}
static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
{
struct device *parent = info->dev->parent;
struct i2c_client *parent_i2c = to_i2c_client(parent);
int ret;
if (info->drv_data->rtc_irq_from_platform) {
struct platform_device *pdev = to_platform_device(info->dev);
info->rtc_irq = platform_get_irq(pdev, 0);
if (info->rtc_irq < 0)
return info->rtc_irq;
} else {
info->rtc_irq = parent_i2c->irq;
}
info->regmap = dev_get_regmap(parent, NULL);
if (!info->regmap) {
dev_err(info->dev, "Failed to get rtc regmap\n");
return -ENODEV;
}
if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
info->rtc_regmap = info->regmap;
goto add_rtc_irq;
}
info->rtc = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter,
info->drv_data->rtc_i2c_addr);
if (IS_ERR(info->rtc)) {
dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
return PTR_ERR(info->rtc);
}
info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
info->drv_data->regmap_config);
if (IS_ERR(info->rtc_regmap)) {
ret = PTR_ERR(info->rtc_regmap);
dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
return ret;
}
add_rtc_irq:
ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
IRQF_ONESHOT | IRQF_SHARED,
0, info->drv_data->rtc_irq_chip,
&info->rtc_irq_data);
if (ret < 0) {
dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
return ret;
}
return 0;
}
static int max77686_rtc_probe(struct platform_device *pdev)
{
struct max77686_rtc_info *info;
const struct platform_device_id *id = platform_get_device_id(pdev);
int ret;
info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
GFP_KERNEL);
if (!info)
return -ENOMEM;
mutex_init(&info->lock);
info->dev = &pdev->dev;
info->drv_data = (const struct max77686_rtc_driver_data *)
id->driver_data;
ret = max77686_init_rtc_regmap(info);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, info);
ret = max77686_rtc_init_reg(info);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
goto err_rtc;
}
device_init_wakeup(&pdev->dev, 1);
info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
&max77686_rtc_ops, THIS_MODULE);
if (IS_ERR(info->rtc_dev)) {
ret = PTR_ERR(info->rtc_dev);
dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
if (ret == 0)
ret = -EINVAL;
goto err_rtc;
}
info->virq = regmap_irq_get_virq(info->rtc_irq_data,
MAX77686_RTCIRQ_RTCA1);
if (info->virq <= 0) {
ret = -ENXIO;
goto err_rtc;
}
ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
"rtc-alarm1", info);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
info->virq, ret);
goto err_rtc;
}
return 0;
err_rtc:
regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
return ret;
}
static void max77686_rtc_remove(struct platform_device *pdev)
{
struct max77686_rtc_info *info = platform_get_drvdata(pdev);
free_irq(info->virq, info);
regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
}
#ifdef CONFIG_PM_SLEEP
static int max77686_rtc_suspend(struct device *dev)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
int ret = 0;
if (device_may_wakeup(dev)) {
struct max77686_rtc_info *info = dev_get_drvdata(dev);
ret = enable_irq_wake(info->virq);
}
/*
* If the main IRQ (not virtual) is the parent IRQ, then it must be
* disabled during suspend because if it happens while suspended it
* will be handled before resuming I2C.
*
* Since Main IRQ is shared, all its users should disable it to be sure
* it won't fire while one of them is still suspended.
*/
if (!info->drv_data->rtc_irq_from_platform)
disable_irq(info->rtc_irq);
return ret;
}
static int max77686_rtc_resume(struct device *dev)
{
struct max77686_rtc_info *info = dev_get_drvdata(dev);
if (!info->drv_data->rtc_irq_from_platform)
enable_irq(info->rtc_irq);
if (device_may_wakeup(dev)) {
struct max77686_rtc_info *info = dev_get_drvdata(dev);
return disable_irq_wake(info->virq);
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
max77686_rtc_suspend, max77686_rtc_resume);
static const struct platform_device_id rtc_id[] = {
{ "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
{ "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
{ "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
{ "max77714-rtc", .driver_data = (kernel_ulong_t)&max77714_drv_data, },
{},
};
MODULE_DEVICE_TABLE(platform, rtc_id);
static struct platform_driver max77686_rtc_driver = {
.driver = {
.name = "max77686-rtc",
.pm = &max77686_rtc_pm_ops,
},
.probe = max77686_rtc_probe,
.remove_new = max77686_rtc_remove,
.id_table = rtc_id,
};
module_platform_driver(max77686_rtc_driver);
MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
MODULE_AUTHOR("Chiwoong Byun <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-max77686.c |
// SPDX-License-Identifier: GPL-2.0
/*
* rtc and date/time utility functions
*
* Copyright (C) 2005-06 Tower Technologies
* Author: Alessandro Zummo <[email protected]>
*
* based on arch/arm/common/rtctime.c and other bits
*
* Author: Cassio Neri <[email protected]> (rtc_time64_to_tm)
*/
#include <linux/export.h>
#include <linux/rtc.h>
static const unsigned char rtc_days_in_month[] = {
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
static const unsigned short rtc_ydays[2][13] = {
/* Normal years */
{ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 },
/* Leap years */
{ 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335, 366 }
};
/*
* The number of days in the month.
*/
int rtc_month_days(unsigned int month, unsigned int year)
{
return rtc_days_in_month[month] + (is_leap_year(year) && month == 1);
}
EXPORT_SYMBOL(rtc_month_days);
/*
* The number of days since January 1. (0 to 365)
*/
int rtc_year_days(unsigned int day, unsigned int month, unsigned int year)
{
return rtc_ydays[is_leap_year(year)][month] + day - 1;
}
EXPORT_SYMBOL(rtc_year_days);
/**
* rtc_time64_to_tm - converts time64_t to rtc_time.
*
* @time: The number of seconds since 01-01-1970 00:00:00.
* (Must be positive.)
* @tm: Pointer to the struct rtc_time.
*/
void rtc_time64_to_tm(time64_t time, struct rtc_time *tm)
{
unsigned int secs;
int days;
u64 u64tmp;
u32 u32tmp, udays, century, day_of_century, year_of_century, year,
day_of_year, month, day;
bool is_Jan_or_Feb, is_leap_year;
/* time must be positive */
days = div_s64_rem(time, 86400, &secs);
/* day of the week, 1970-01-01 was a Thursday */
tm->tm_wday = (days + 4) % 7;
/*
* The following algorithm is, basically, Proposition 6.3 of Neri
* and Schneider [1]. In a few words: it works on the computational
* (fictitious) calendar where the year starts in March, month = 2
* (*), and finishes in February, month = 13. This calendar is
* mathematically convenient because the day of the year does not
* depend on whether the year is leap or not. For instance:
*
* March 1st 0-th day of the year;
* ...
* April 1st 31-st day of the year;
* ...
* January 1st 306-th day of the year; (Important!)
* ...
* February 28th 364-th day of the year;
* February 29th 365-th day of the year (if it exists).
*
* After having worked out the date in the computational calendar
* (using just arithmetics) it's easy to convert it to the
* corresponding date in the Gregorian calendar.
*
* [1] "Euclidean Affine Functions and Applications to Calendar
* Algorithms". https://arxiv.org/abs/2102.06959
*
* (*) The numbering of months follows rtc_time more closely and
* thus, is slightly different from [1].
*/
udays = ((u32) days) + 719468;
u32tmp = 4 * udays + 3;
century = u32tmp / 146097;
day_of_century = u32tmp % 146097 / 4;
u32tmp = 4 * day_of_century + 3;
u64tmp = 2939745ULL * u32tmp;
year_of_century = upper_32_bits(u64tmp);
day_of_year = lower_32_bits(u64tmp) / 2939745 / 4;
year = 100 * century + year_of_century;
is_leap_year = year_of_century != 0 ?
year_of_century % 4 == 0 : century % 4 == 0;
u32tmp = 2141 * day_of_year + 132377;
month = u32tmp >> 16;
day = ((u16) u32tmp) / 2141;
/*
* Recall that January 01 is the 306-th day of the year in the
* computational (not Gregorian) calendar.
*/
is_Jan_or_Feb = day_of_year >= 306;
/* Converts to the Gregorian calendar. */
year = year + is_Jan_or_Feb;
month = is_Jan_or_Feb ? month - 12 : month;
day = day + 1;
day_of_year = is_Jan_or_Feb ?
day_of_year - 306 : day_of_year + 31 + 28 + is_leap_year;
/* Converts to rtc_time's format. */
tm->tm_year = (int) (year - 1900);
tm->tm_mon = (int) month;
tm->tm_mday = (int) day;
tm->tm_yday = (int) day_of_year + 1;
tm->tm_hour = secs / 3600;
secs -= tm->tm_hour * 3600;
tm->tm_min = secs / 60;
tm->tm_sec = secs - tm->tm_min * 60;
tm->tm_isdst = 0;
}
EXPORT_SYMBOL(rtc_time64_to_tm);
/*
* Does the rtc_time represent a valid date/time?
*/
int rtc_valid_tm(struct rtc_time *tm)
{
if (tm->tm_year < 70 ||
tm->tm_year > (INT_MAX - 1900) ||
((unsigned int)tm->tm_mon) >= 12 ||
tm->tm_mday < 1 ||
tm->tm_mday > rtc_month_days(tm->tm_mon,
((unsigned int)tm->tm_year + 1900)) ||
((unsigned int)tm->tm_hour) >= 24 ||
((unsigned int)tm->tm_min) >= 60 ||
((unsigned int)tm->tm_sec) >= 60)
return -EINVAL;
return 0;
}
EXPORT_SYMBOL(rtc_valid_tm);
/*
* rtc_tm_to_time64 - Converts rtc_time to time64_t.
* Convert Gregorian date to seconds since 01-01-1970 00:00:00.
*/
time64_t rtc_tm_to_time64(struct rtc_time *tm)
{
return mktime64(((unsigned int)tm->tm_year + 1900), tm->tm_mon + 1,
tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec);
}
EXPORT_SYMBOL(rtc_tm_to_time64);
/*
* Convert rtc_time to ktime
*/
ktime_t rtc_tm_to_ktime(struct rtc_time tm)
{
return ktime_set(rtc_tm_to_time64(&tm), 0);
}
EXPORT_SYMBOL_GPL(rtc_tm_to_ktime);
/*
* Convert ktime to rtc_time
*/
struct rtc_time rtc_ktime_to_tm(ktime_t kt)
{
struct timespec64 ts;
struct rtc_time ret;
ts = ktime_to_timespec64(kt);
/* Round up any ns */
if (ts.tv_nsec)
ts.tv_sec++;
rtc_time64_to_tm(ts.tv_sec, &ret);
return ret;
}
EXPORT_SYMBOL_GPL(rtc_ktime_to_tm);
| linux-master | drivers/rtc/lib.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RTC class driver for "CMOS RTC": PCs, ACPI, etc
*
* Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c)
* Copyright (C) 2006 David Brownell (convert to new framework)
*/
/*
* The original "cmos clock" chip was an MC146818 chip, now obsolete.
* That defined the register interface now provided by all PCs, some
* non-PC systems, and incorporated into ACPI. Modern PC chipsets
* integrate an MC146818 clone in their southbridge, and boards use
* that instead of discrete clones like the DS12887 or M48T86. There
* are also clones that connect using the LPC bus.
*
* That register API is also used directly by various other drivers
* (notably for integrated NVRAM), infrastructure (x86 has code to
* bypass the RTC framework, directly reading the RTC during boot
* and updating minutes/seconds for systems using NTP synch) and
* utilities (like userspace 'hwclock', if no /dev node exists).
*
* So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with
* interrupts disabled, holding the global rtc_lock, to exclude those
* other drivers and utilities on correctly configured systems.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/log2.h>
#include <linux/pm.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#ifdef CONFIG_X86
#include <asm/i8259.h>
#include <asm/processor.h>
#include <linux/dmi.h>
#endif
/* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */
#include <linux/mc146818rtc.h>
#ifdef CONFIG_ACPI
/*
* Use ACPI SCI to replace HPET interrupt for RTC Alarm event
*
* If cleared, ACPI SCI is only used to wake up the system from suspend
*
* If set, ACPI SCI is used to handle UIE/AIE and system wakeup
*/
static bool use_acpi_alarm;
module_param(use_acpi_alarm, bool, 0444);
static inline int cmos_use_acpi_alarm(void)
{
return use_acpi_alarm;
}
#else /* !CONFIG_ACPI */
static inline int cmos_use_acpi_alarm(void)
{
return 0;
}
#endif
struct cmos_rtc {
struct rtc_device *rtc;
struct device *dev;
int irq;
struct resource *iomem;
time64_t alarm_expires;
void (*wake_on)(struct device *);
void (*wake_off)(struct device *);
u8 enabled_wake;
u8 suspend_ctrl;
/* newer hardware extends the original register set */
u8 day_alrm;
u8 mon_alrm;
u8 century;
struct rtc_wkalrm saved_wkalrm;
};
/* both platform and pnp busses use negative numbers for invalid irqs */
#define is_valid_irq(n) ((n) > 0)
static const char driver_name[] = "rtc_cmos";
/* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear;
* always mask it against the irq enable bits in RTC_CONTROL. Bit values
* are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both.
*/
#define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF)
static inline int is_intr(u8 rtc_intr)
{
if (!(rtc_intr & RTC_IRQF))
return 0;
return rtc_intr & RTC_IRQMASK;
}
/*----------------------------------------------------------------*/
/* Much modern x86 hardware has HPETs (10+ MHz timers) which, because
* many BIOS programmers don't set up "sane mode" IRQ routing, are mostly
* used in a broken "legacy replacement" mode. The breakage includes
* HPET #1 hijacking the IRQ for this RTC, and being unavailable for
* other (better) use.
*
* When that broken mode is in use, platform glue provides a partial
* emulation of hardware RTC IRQ facilities using HPET #1. We don't
* want to use HPET for anything except those IRQs though...
*/
#ifdef CONFIG_HPET_EMULATE_RTC
#include <asm/hpet.h>
#else
static inline int is_hpet_enabled(void)
{
return 0;
}
static inline int hpet_mask_rtc_irq_bit(unsigned long mask)
{
return 0;
}
static inline int hpet_set_rtc_irq_bit(unsigned long mask)
{
return 0;
}
static inline int
hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
{
return 0;
}
static inline int hpet_set_periodic_freq(unsigned long freq)
{
return 0;
}
static inline int hpet_rtc_dropped_irq(void)
{
return 0;
}
static inline int hpet_rtc_timer_init(void)
{
return 0;
}
extern irq_handler_t hpet_rtc_interrupt;
static inline int hpet_register_irq_handler(irq_handler_t handler)
{
return 0;
}
static inline int hpet_unregister_irq_handler(irq_handler_t handler)
{
return 0;
}
#endif
/* Don't use HPET for RTC Alarm event if ACPI Fixed event is used */
static inline int use_hpet_alarm(void)
{
return is_hpet_enabled() && !cmos_use_acpi_alarm();
}
/*----------------------------------------------------------------*/
#ifdef RTC_PORT
/* Most newer x86 systems have two register banks, the first used
* for RTC and NVRAM and the second only for NVRAM. Caller must
* own rtc_lock ... and we won't worry about access during NMI.
*/
#define can_bank2 true
static inline unsigned char cmos_read_bank2(unsigned char addr)
{
outb(addr, RTC_PORT(2));
return inb(RTC_PORT(3));
}
static inline void cmos_write_bank2(unsigned char val, unsigned char addr)
{
outb(addr, RTC_PORT(2));
outb(val, RTC_PORT(3));
}
#else
#define can_bank2 false
static inline unsigned char cmos_read_bank2(unsigned char addr)
{
return 0;
}
static inline void cmos_write_bank2(unsigned char val, unsigned char addr)
{
}
#endif
/*----------------------------------------------------------------*/
static int cmos_read_time(struct device *dev, struct rtc_time *t)
{
int ret;
/*
* If pm_trace abused the RTC for storage, set the timespec to 0,
* which tells the caller that this RTC value is unusable.
*/
if (!pm_trace_rtc_valid())
return -EIO;
ret = mc146818_get_time(t);
if (ret < 0) {
dev_err_ratelimited(dev, "unable to read current time\n");
return ret;
}
return 0;
}
static int cmos_set_time(struct device *dev, struct rtc_time *t)
{
/* NOTE: this ignores the issue whereby updating the seconds
* takes effect exactly 500ms after we write the register.
* (Also queueing and other delays before we get this far.)
*/
return mc146818_set_time(t);
}
struct cmos_read_alarm_callback_param {
struct cmos_rtc *cmos;
struct rtc_time *time;
unsigned char rtc_control;
};
static void cmos_read_alarm_callback(unsigned char __always_unused seconds,
void *param_in)
{
struct cmos_read_alarm_callback_param *p =
(struct cmos_read_alarm_callback_param *)param_in;
struct rtc_time *time = p->time;
time->tm_sec = CMOS_READ(RTC_SECONDS_ALARM);
time->tm_min = CMOS_READ(RTC_MINUTES_ALARM);
time->tm_hour = CMOS_READ(RTC_HOURS_ALARM);
if (p->cmos->day_alrm) {
/* ignore upper bits on readback per ACPI spec */
time->tm_mday = CMOS_READ(p->cmos->day_alrm) & 0x3f;
if (!time->tm_mday)
time->tm_mday = -1;
if (p->cmos->mon_alrm) {
time->tm_mon = CMOS_READ(p->cmos->mon_alrm);
if (!time->tm_mon)
time->tm_mon = -1;
}
}
p->rtc_control = CMOS_READ(RTC_CONTROL);
}
static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
struct cmos_read_alarm_callback_param p = {
.cmos = cmos,
.time = &t->time,
};
/* This not only a rtc_op, but also called directly */
if (!is_valid_irq(cmos->irq))
return -EIO;
/* Basic alarms only support hour, minute, and seconds fields.
* Some also support day and month, for alarms up to a year in
* the future.
*/
/* Some Intel chipsets disconnect the alarm registers when the clock
* update is in progress - during this time reads return bogus values
* and writes may fail silently. See for example "7th Generation Intel®
* Processor Family I/O for U/Y Platforms [...] Datasheet", section
* 27.7.1
*
* Use the mc146818_avoid_UIP() function to avoid this.
*/
if (!mc146818_avoid_UIP(cmos_read_alarm_callback, &p))
return -EIO;
if (!(p.rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
if (((unsigned)t->time.tm_sec) < 0x60)
t->time.tm_sec = bcd2bin(t->time.tm_sec);
else
t->time.tm_sec = -1;
if (((unsigned)t->time.tm_min) < 0x60)
t->time.tm_min = bcd2bin(t->time.tm_min);
else
t->time.tm_min = -1;
if (((unsigned)t->time.tm_hour) < 0x24)
t->time.tm_hour = bcd2bin(t->time.tm_hour);
else
t->time.tm_hour = -1;
if (cmos->day_alrm) {
if (((unsigned)t->time.tm_mday) <= 0x31)
t->time.tm_mday = bcd2bin(t->time.tm_mday);
else
t->time.tm_mday = -1;
if (cmos->mon_alrm) {
if (((unsigned)t->time.tm_mon) <= 0x12)
t->time.tm_mon = bcd2bin(t->time.tm_mon)-1;
else
t->time.tm_mon = -1;
}
}
}
t->enabled = !!(p.rtc_control & RTC_AIE);
t->pending = 0;
return 0;
}
static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control)
{
unsigned char rtc_intr;
/* NOTE after changing RTC_xIE bits we always read INTR_FLAGS;
* allegedly some older rtcs need that to handle irqs properly
*/
rtc_intr = CMOS_READ(RTC_INTR_FLAGS);
if (use_hpet_alarm())
return;
rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
if (is_intr(rtc_intr))
rtc_update_irq(cmos->rtc, 1, rtc_intr);
}
static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask)
{
unsigned char rtc_control;
/* flush any pending IRQ status, notably for update irqs,
* before we enable new IRQs
*/
rtc_control = CMOS_READ(RTC_CONTROL);
cmos_checkintr(cmos, rtc_control);
rtc_control |= mask;
CMOS_WRITE(rtc_control, RTC_CONTROL);
if (use_hpet_alarm())
hpet_set_rtc_irq_bit(mask);
if ((mask & RTC_AIE) && cmos_use_acpi_alarm()) {
if (cmos->wake_on)
cmos->wake_on(cmos->dev);
}
cmos_checkintr(cmos, rtc_control);
}
static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask)
{
unsigned char rtc_control;
rtc_control = CMOS_READ(RTC_CONTROL);
rtc_control &= ~mask;
CMOS_WRITE(rtc_control, RTC_CONTROL);
if (use_hpet_alarm())
hpet_mask_rtc_irq_bit(mask);
if ((mask & RTC_AIE) && cmos_use_acpi_alarm()) {
if (cmos->wake_off)
cmos->wake_off(cmos->dev);
}
cmos_checkintr(cmos, rtc_control);
}
static int cmos_validate_alarm(struct device *dev, struct rtc_wkalrm *t)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
struct rtc_time now;
cmos_read_time(dev, &now);
if (!cmos->day_alrm) {
time64_t t_max_date;
time64_t t_alrm;
t_max_date = rtc_tm_to_time64(&now);
t_max_date += 24 * 60 * 60 - 1;
t_alrm = rtc_tm_to_time64(&t->time);
if (t_alrm > t_max_date) {
dev_err(dev,
"Alarms can be up to one day in the future\n");
return -EINVAL;
}
} else if (!cmos->mon_alrm) {
struct rtc_time max_date = now;
time64_t t_max_date;
time64_t t_alrm;
int max_mday;
if (max_date.tm_mon == 11) {
max_date.tm_mon = 0;
max_date.tm_year += 1;
} else {
max_date.tm_mon += 1;
}
max_mday = rtc_month_days(max_date.tm_mon, max_date.tm_year);
if (max_date.tm_mday > max_mday)
max_date.tm_mday = max_mday;
t_max_date = rtc_tm_to_time64(&max_date);
t_max_date -= 1;
t_alrm = rtc_tm_to_time64(&t->time);
if (t_alrm > t_max_date) {
dev_err(dev,
"Alarms can be up to one month in the future\n");
return -EINVAL;
}
} else {
struct rtc_time max_date = now;
time64_t t_max_date;
time64_t t_alrm;
int max_mday;
max_date.tm_year += 1;
max_mday = rtc_month_days(max_date.tm_mon, max_date.tm_year);
if (max_date.tm_mday > max_mday)
max_date.tm_mday = max_mday;
t_max_date = rtc_tm_to_time64(&max_date);
t_max_date -= 1;
t_alrm = rtc_tm_to_time64(&t->time);
if (t_alrm > t_max_date) {
dev_err(dev,
"Alarms can be up to one year in the future\n");
return -EINVAL;
}
}
return 0;
}
struct cmos_set_alarm_callback_param {
struct cmos_rtc *cmos;
unsigned char mon, mday, hrs, min, sec;
struct rtc_wkalrm *t;
};
/* Note: this function may be executed by mc146818_avoid_UIP() more then
* once
*/
static void cmos_set_alarm_callback(unsigned char __always_unused seconds,
void *param_in)
{
struct cmos_set_alarm_callback_param *p =
(struct cmos_set_alarm_callback_param *)param_in;
/* next rtc irq must not be from previous alarm setting */
cmos_irq_disable(p->cmos, RTC_AIE);
/* update alarm */
CMOS_WRITE(p->hrs, RTC_HOURS_ALARM);
CMOS_WRITE(p->min, RTC_MINUTES_ALARM);
CMOS_WRITE(p->sec, RTC_SECONDS_ALARM);
/* the system may support an "enhanced" alarm */
if (p->cmos->day_alrm) {
CMOS_WRITE(p->mday, p->cmos->day_alrm);
if (p->cmos->mon_alrm)
CMOS_WRITE(p->mon, p->cmos->mon_alrm);
}
if (use_hpet_alarm()) {
/*
* FIXME the HPET alarm glue currently ignores day_alrm
* and mon_alrm ...
*/
hpet_set_alarm_time(p->t->time.tm_hour, p->t->time.tm_min,
p->t->time.tm_sec);
}
if (p->t->enabled)
cmos_irq_enable(p->cmos, RTC_AIE);
}
static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
struct cmos_set_alarm_callback_param p = {
.cmos = cmos,
.t = t
};
unsigned char rtc_control;
int ret;
/* This not only a rtc_op, but also called directly */
if (!is_valid_irq(cmos->irq))
return -EIO;
ret = cmos_validate_alarm(dev, t);
if (ret < 0)
return ret;
p.mon = t->time.tm_mon + 1;
p.mday = t->time.tm_mday;
p.hrs = t->time.tm_hour;
p.min = t->time.tm_min;
p.sec = t->time.tm_sec;
spin_lock_irq(&rtc_lock);
rtc_control = CMOS_READ(RTC_CONTROL);
spin_unlock_irq(&rtc_lock);
if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
/* Writing 0xff means "don't care" or "match all". */
p.mon = (p.mon <= 12) ? bin2bcd(p.mon) : 0xff;
p.mday = (p.mday >= 1 && p.mday <= 31) ? bin2bcd(p.mday) : 0xff;
p.hrs = (p.hrs < 24) ? bin2bcd(p.hrs) : 0xff;
p.min = (p.min < 60) ? bin2bcd(p.min) : 0xff;
p.sec = (p.sec < 60) ? bin2bcd(p.sec) : 0xff;
}
/*
* Some Intel chipsets disconnect the alarm registers when the clock
* update is in progress - during this time writes fail silently.
*
* Use mc146818_avoid_UIP() to avoid this.
*/
if (!mc146818_avoid_UIP(cmos_set_alarm_callback, &p))
return -EIO;
cmos->alarm_expires = rtc_tm_to_time64(&t->time);
return 0;
}
static int cmos_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
if (enabled)
cmos_irq_enable(cmos, RTC_AIE);
else
cmos_irq_disable(cmos, RTC_AIE);
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
#if IS_ENABLED(CONFIG_RTC_INTF_PROC)
static int cmos_procfs(struct device *dev, struct seq_file *seq)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
unsigned char rtc_control, valid;
spin_lock_irq(&rtc_lock);
rtc_control = CMOS_READ(RTC_CONTROL);
valid = CMOS_READ(RTC_VALID);
spin_unlock_irq(&rtc_lock);
/* NOTE: at least ICH6 reports battery status using a different
* (non-RTC) bit; and SQWE is ignored on many current systems.
*/
seq_printf(seq,
"periodic_IRQ\t: %s\n"
"update_IRQ\t: %s\n"
"HPET_emulated\t: %s\n"
// "square_wave\t: %s\n"
"BCD\t\t: %s\n"
"DST_enable\t: %s\n"
"periodic_freq\t: %d\n"
"batt_status\t: %s\n",
(rtc_control & RTC_PIE) ? "yes" : "no",
(rtc_control & RTC_UIE) ? "yes" : "no",
use_hpet_alarm() ? "yes" : "no",
// (rtc_control & RTC_SQWE) ? "yes" : "no",
(rtc_control & RTC_DM_BINARY) ? "no" : "yes",
(rtc_control & RTC_DST_EN) ? "yes" : "no",
cmos->rtc->irq_freq,
(valid & RTC_VRT) ? "okay" : "dead");
return 0;
}
#else
#define cmos_procfs NULL
#endif
static const struct rtc_class_ops cmos_rtc_ops = {
.read_time = cmos_read_time,
.set_time = cmos_set_time,
.read_alarm = cmos_read_alarm,
.set_alarm = cmos_set_alarm,
.proc = cmos_procfs,
.alarm_irq_enable = cmos_alarm_irq_enable,
};
/*----------------------------------------------------------------*/
/*
* All these chips have at least 64 bytes of address space, shared by
* RTC registers and NVRAM. Most of those bytes of NVRAM are used
* by boot firmware. Modern chips have 128 or 256 bytes.
*/
#define NVRAM_OFFSET (RTC_REG_D + 1)
static int cmos_nvram_read(void *priv, unsigned int off, void *val,
size_t count)
{
unsigned char *buf = val;
int retval;
off += NVRAM_OFFSET;
spin_lock_irq(&rtc_lock);
for (retval = 0; count; count--, off++, retval++) {
if (off < 128)
*buf++ = CMOS_READ(off);
else if (can_bank2)
*buf++ = cmos_read_bank2(off);
else
break;
}
spin_unlock_irq(&rtc_lock);
return retval;
}
static int cmos_nvram_write(void *priv, unsigned int off, void *val,
size_t count)
{
struct cmos_rtc *cmos = priv;
unsigned char *buf = val;
int retval;
/* NOTE: on at least PCs and Ataris, the boot firmware uses a
* checksum on part of the NVRAM data. That's currently ignored
* here. If userspace is smart enough to know what fields of
* NVRAM to update, updating checksums is also part of its job.
*/
off += NVRAM_OFFSET;
spin_lock_irq(&rtc_lock);
for (retval = 0; count; count--, off++, retval++) {
/* don't trash RTC registers */
if (off == cmos->day_alrm
|| off == cmos->mon_alrm
|| off == cmos->century)
buf++;
else if (off < 128)
CMOS_WRITE(*buf++, off);
else if (can_bank2)
cmos_write_bank2(*buf++, off);
else
break;
}
spin_unlock_irq(&rtc_lock);
return retval;
}
/*----------------------------------------------------------------*/
static struct cmos_rtc cmos_rtc;
static irqreturn_t cmos_interrupt(int irq, void *p)
{
u8 irqstat;
u8 rtc_control;
spin_lock(&rtc_lock);
/* When the HPET interrupt handler calls us, the interrupt
* status is passed as arg1 instead of the irq number. But
* always clear irq status, even when HPET is in the way.
*
* Note that HPET and RTC are almost certainly out of phase,
* giving different IRQ status ...
*/
irqstat = CMOS_READ(RTC_INTR_FLAGS);
rtc_control = CMOS_READ(RTC_CONTROL);
if (use_hpet_alarm())
irqstat = (unsigned long)irq & 0xF0;
/* If we were suspended, RTC_CONTROL may not be accurate since the
* bios may have cleared it.
*/
if (!cmos_rtc.suspend_ctrl)
irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF;
else
irqstat &= (cmos_rtc.suspend_ctrl & RTC_IRQMASK) | RTC_IRQF;
/* All Linux RTC alarms should be treated as if they were oneshot.
* Similar code may be needed in system wakeup paths, in case the
* alarm woke the system.
*/
if (irqstat & RTC_AIE) {
cmos_rtc.suspend_ctrl &= ~RTC_AIE;
rtc_control &= ~RTC_AIE;
CMOS_WRITE(rtc_control, RTC_CONTROL);
if (use_hpet_alarm())
hpet_mask_rtc_irq_bit(RTC_AIE);
CMOS_READ(RTC_INTR_FLAGS);
}
spin_unlock(&rtc_lock);
if (is_intr(irqstat)) {
rtc_update_irq(p, 1, irqstat);
return IRQ_HANDLED;
} else
return IRQ_NONE;
}
#ifdef CONFIG_ACPI
#include <linux/acpi.h>
static u32 rtc_handler(void *context)
{
struct device *dev = context;
struct cmos_rtc *cmos = dev_get_drvdata(dev);
unsigned char rtc_control = 0;
unsigned char rtc_intr;
unsigned long flags;
/*
* Always update rtc irq when ACPI is used as RTC Alarm.
* Or else, ACPI SCI is enabled during suspend/resume only,
* update rtc irq in that case.
*/
if (cmos_use_acpi_alarm())
cmos_interrupt(0, (void *)cmos->rtc);
else {
/* Fix me: can we use cmos_interrupt() here as well? */
spin_lock_irqsave(&rtc_lock, flags);
if (cmos_rtc.suspend_ctrl)
rtc_control = CMOS_READ(RTC_CONTROL);
if (rtc_control & RTC_AIE) {
cmos_rtc.suspend_ctrl &= ~RTC_AIE;
CMOS_WRITE(rtc_control, RTC_CONTROL);
rtc_intr = CMOS_READ(RTC_INTR_FLAGS);
rtc_update_irq(cmos->rtc, 1, rtc_intr);
}
spin_unlock_irqrestore(&rtc_lock, flags);
}
pm_wakeup_hard_event(dev);
acpi_clear_event(ACPI_EVENT_RTC);
acpi_disable_event(ACPI_EVENT_RTC, 0);
return ACPI_INTERRUPT_HANDLED;
}
static void acpi_rtc_event_setup(struct device *dev)
{
if (acpi_disabled)
return;
acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, dev);
/*
* After the RTC handler is installed, the Fixed_RTC event should
* be disabled. Only when the RTC alarm is set will it be enabled.
*/
acpi_clear_event(ACPI_EVENT_RTC);
acpi_disable_event(ACPI_EVENT_RTC, 0);
}
static void acpi_rtc_event_cleanup(void)
{
if (acpi_disabled)
return;
acpi_remove_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler);
}
static void rtc_wake_on(struct device *dev)
{
acpi_clear_event(ACPI_EVENT_RTC);
acpi_enable_event(ACPI_EVENT_RTC, 0);
}
static void rtc_wake_off(struct device *dev)
{
acpi_disable_event(ACPI_EVENT_RTC, 0);
}
#ifdef CONFIG_X86
/* Enable use_acpi_alarm mode for Intel platforms no earlier than 2015 */
static void use_acpi_alarm_quirks(void)
{
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return;
if (!is_hpet_enabled())
return;
if (dmi_get_bios_year() < 2015)
return;
use_acpi_alarm = true;
}
#else
static inline void use_acpi_alarm_quirks(void) { }
#endif
static void acpi_cmos_wake_setup(struct device *dev)
{
if (acpi_disabled)
return;
use_acpi_alarm_quirks();
cmos_rtc.wake_on = rtc_wake_on;
cmos_rtc.wake_off = rtc_wake_off;
/* ACPI tables bug workaround. */
if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) {
dev_dbg(dev, "bogus FADT month_alarm (%d)\n",
acpi_gbl_FADT.month_alarm);
acpi_gbl_FADT.month_alarm = 0;
}
cmos_rtc.day_alrm = acpi_gbl_FADT.day_alarm;
cmos_rtc.mon_alrm = acpi_gbl_FADT.month_alarm;
cmos_rtc.century = acpi_gbl_FADT.century;
if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE)
dev_info(dev, "RTC can wake from S4\n");
/* RTC always wakes from S1/S2/S3, and often S4/STD */
device_init_wakeup(dev, 1);
}
static void cmos_check_acpi_rtc_status(struct device *dev,
unsigned char *rtc_control)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
acpi_event_status rtc_status;
acpi_status status;
if (acpi_gbl_FADT.flags & ACPI_FADT_FIXED_RTC)
return;
status = acpi_get_event_status(ACPI_EVENT_RTC, &rtc_status);
if (ACPI_FAILURE(status)) {
dev_err(dev, "Could not get RTC status\n");
} else if (rtc_status & ACPI_EVENT_FLAG_SET) {
unsigned char mask;
*rtc_control &= ~RTC_AIE;
CMOS_WRITE(*rtc_control, RTC_CONTROL);
mask = CMOS_READ(RTC_INTR_FLAGS);
rtc_update_irq(cmos->rtc, 1, mask);
}
}
#else /* !CONFIG_ACPI */
static inline void acpi_rtc_event_setup(struct device *dev)
{
}
static inline void acpi_rtc_event_cleanup(void)
{
}
static inline void acpi_cmos_wake_setup(struct device *dev)
{
}
static inline void cmos_check_acpi_rtc_status(struct device *dev,
unsigned char *rtc_control)
{
}
#endif /* CONFIG_ACPI */
#ifdef CONFIG_PNP
#define INITSECTION
#else
#define INITSECTION __init
#endif
#define SECS_PER_DAY (24 * 60 * 60)
#define SECS_PER_MONTH (28 * SECS_PER_DAY)
#define SECS_PER_YEAR (365 * SECS_PER_DAY)
static int INITSECTION
cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
{
struct cmos_rtc_board_info *info = dev_get_platdata(dev);
int retval = 0;
unsigned char rtc_control;
unsigned address_space;
u32 flags = 0;
struct nvmem_config nvmem_cfg = {
.name = "cmos_nvram",
.word_size = 1,
.stride = 1,
.reg_read = cmos_nvram_read,
.reg_write = cmos_nvram_write,
.priv = &cmos_rtc,
};
/* there can be only one ... */
if (cmos_rtc.dev)
return -EBUSY;
if (!ports)
return -ENODEV;
/* Claim I/O ports ASAP, minimizing conflict with legacy driver.
*
* REVISIT non-x86 systems may instead use memory space resources
* (needing ioremap etc), not i/o space resources like this ...
*/
if (RTC_IOMAPPED)
ports = request_region(ports->start, resource_size(ports),
driver_name);
else
ports = request_mem_region(ports->start, resource_size(ports),
driver_name);
if (!ports) {
dev_dbg(dev, "i/o registers already in use\n");
return -EBUSY;
}
cmos_rtc.irq = rtc_irq;
cmos_rtc.iomem = ports;
/* Heuristic to deduce NVRAM size ... do what the legacy NVRAM
* driver did, but don't reject unknown configs. Old hardware
* won't address 128 bytes. Newer chips have multiple banks,
* though they may not be listed in one I/O resource.
*/
#if defined(CONFIG_ATARI)
address_space = 64;
#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \
|| defined(__sparc__) || defined(__mips__) \
|| defined(__powerpc__)
address_space = 128;
#else
#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes.
address_space = 128;
#endif
if (can_bank2 && ports->end > (ports->start + 1))
address_space = 256;
/* For ACPI systems extension info comes from the FADT. On others,
* board specific setup provides it as appropriate. Systems where
* the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and
* some almost-clones) can provide hooks to make that behave.
*
* Note that ACPI doesn't preclude putting these registers into
* "extended" areas of the chip, including some that we won't yet
* expect CMOS_READ and friends to handle.
*/
if (info) {
if (info->flags)
flags = info->flags;
if (info->address_space)
address_space = info->address_space;
cmos_rtc.day_alrm = info->rtc_day_alarm;
cmos_rtc.mon_alrm = info->rtc_mon_alarm;
cmos_rtc.century = info->rtc_century;
if (info->wake_on && info->wake_off) {
cmos_rtc.wake_on = info->wake_on;
cmos_rtc.wake_off = info->wake_off;
}
} else {
acpi_cmos_wake_setup(dev);
}
if (cmos_rtc.day_alrm >= 128)
cmos_rtc.day_alrm = 0;
if (cmos_rtc.mon_alrm >= 128)
cmos_rtc.mon_alrm = 0;
if (cmos_rtc.century >= 128)
cmos_rtc.century = 0;
cmos_rtc.dev = dev;
dev_set_drvdata(dev, &cmos_rtc);
cmos_rtc.rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(cmos_rtc.rtc)) {
retval = PTR_ERR(cmos_rtc.rtc);
goto cleanup0;
}
if (cmos_rtc.mon_alrm)
cmos_rtc.rtc->alarm_offset_max = SECS_PER_YEAR - 1;
else if (cmos_rtc.day_alrm)
cmos_rtc.rtc->alarm_offset_max = SECS_PER_MONTH - 1;
else
cmos_rtc.rtc->alarm_offset_max = SECS_PER_DAY - 1;
rename_region(ports, dev_name(&cmos_rtc.rtc->dev));
if (!mc146818_does_rtc_work()) {
dev_warn(dev, "broken or not accessible\n");
retval = -ENXIO;
goto cleanup1;
}
spin_lock_irq(&rtc_lock);
if (!(flags & CMOS_RTC_FLAGS_NOFREQ)) {
/* force periodic irq to CMOS reset default of 1024Hz;
*
* REVISIT it's been reported that at least one x86_64 ALI
* mobo doesn't use 32KHz here ... for portability we might
* need to do something about other clock frequencies.
*/
cmos_rtc.rtc->irq_freq = 1024;
if (use_hpet_alarm())
hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq);
CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT);
}
/* disable irqs */
if (is_valid_irq(rtc_irq))
cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE);
rtc_control = CMOS_READ(RTC_CONTROL);
spin_unlock_irq(&rtc_lock);
if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) {
dev_warn(dev, "only 24-hr supported\n");
retval = -ENXIO;
goto cleanup1;
}
if (use_hpet_alarm())
hpet_rtc_timer_init();
if (is_valid_irq(rtc_irq)) {
irq_handler_t rtc_cmos_int_handler;
if (use_hpet_alarm()) {
rtc_cmos_int_handler = hpet_rtc_interrupt;
retval = hpet_register_irq_handler(cmos_interrupt);
if (retval) {
hpet_mask_rtc_irq_bit(RTC_IRQMASK);
dev_warn(dev, "hpet_register_irq_handler "
" failed in rtc_init().");
goto cleanup1;
}
} else
rtc_cmos_int_handler = cmos_interrupt;
retval = request_irq(rtc_irq, rtc_cmos_int_handler,
0, dev_name(&cmos_rtc.rtc->dev),
cmos_rtc.rtc);
if (retval < 0) {
dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq);
goto cleanup1;
}
} else {
clear_bit(RTC_FEATURE_ALARM, cmos_rtc.rtc->features);
}
cmos_rtc.rtc->ops = &cmos_rtc_ops;
retval = devm_rtc_register_device(cmos_rtc.rtc);
if (retval)
goto cleanup2;
/* Set the sync offset for the periodic 11min update correct */
cmos_rtc.rtc->set_offset_nsec = NSEC_PER_SEC / 2;
/* export at least the first block of NVRAM */
nvmem_cfg.size = address_space - NVRAM_OFFSET;
devm_rtc_nvmem_register(cmos_rtc.rtc, &nvmem_cfg);
/*
* Everything has gone well so far, so by default register a handler for
* the ACPI RTC fixed event.
*/
if (!info)
acpi_rtc_event_setup(dev);
dev_info(dev, "%s%s, %d bytes nvram%s\n",
!is_valid_irq(rtc_irq) ? "no alarms" :
cmos_rtc.mon_alrm ? "alarms up to one year" :
cmos_rtc.day_alrm ? "alarms up to one month" :
"alarms up to one day",
cmos_rtc.century ? ", y3k" : "",
nvmem_cfg.size,
use_hpet_alarm() ? ", hpet irqs" : "");
return 0;
cleanup2:
if (is_valid_irq(rtc_irq))
free_irq(rtc_irq, cmos_rtc.rtc);
cleanup1:
cmos_rtc.dev = NULL;
cleanup0:
if (RTC_IOMAPPED)
release_region(ports->start, resource_size(ports));
else
release_mem_region(ports->start, resource_size(ports));
return retval;
}
static void cmos_do_shutdown(int rtc_irq)
{
spin_lock_irq(&rtc_lock);
if (is_valid_irq(rtc_irq))
cmos_irq_disable(&cmos_rtc, RTC_IRQMASK);
spin_unlock_irq(&rtc_lock);
}
static void cmos_do_remove(struct device *dev)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
struct resource *ports;
cmos_do_shutdown(cmos->irq);
if (is_valid_irq(cmos->irq)) {
free_irq(cmos->irq, cmos->rtc);
if (use_hpet_alarm())
hpet_unregister_irq_handler(cmos_interrupt);
}
if (!dev_get_platdata(dev))
acpi_rtc_event_cleanup();
cmos->rtc = NULL;
ports = cmos->iomem;
if (RTC_IOMAPPED)
release_region(ports->start, resource_size(ports));
else
release_mem_region(ports->start, resource_size(ports));
cmos->iomem = NULL;
cmos->dev = NULL;
}
static int cmos_aie_poweroff(struct device *dev)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
struct rtc_time now;
time64_t t_now;
int retval = 0;
unsigned char rtc_control;
if (!cmos->alarm_expires)
return -EINVAL;
spin_lock_irq(&rtc_lock);
rtc_control = CMOS_READ(RTC_CONTROL);
spin_unlock_irq(&rtc_lock);
/* We only care about the situation where AIE is disabled. */
if (rtc_control & RTC_AIE)
return -EBUSY;
cmos_read_time(dev, &now);
t_now = rtc_tm_to_time64(&now);
/*
* When enabling "RTC wake-up" in BIOS setup, the machine reboots
* automatically right after shutdown on some buggy boxes.
* This automatic rebooting issue won't happen when the alarm
* time is larger than now+1 seconds.
*
* If the alarm time is equal to now+1 seconds, the issue can be
* prevented by cancelling the alarm.
*/
if (cmos->alarm_expires == t_now + 1) {
struct rtc_wkalrm alarm;
/* Cancel the AIE timer by configuring the past time. */
rtc_time64_to_tm(t_now - 1, &alarm.time);
alarm.enabled = 0;
retval = cmos_set_alarm(dev, &alarm);
} else if (cmos->alarm_expires > t_now + 1) {
retval = -EBUSY;
}
return retval;
}
static int cmos_suspend(struct device *dev)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
unsigned char tmp;
/* only the alarm might be a wakeup event source */
spin_lock_irq(&rtc_lock);
cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL);
if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) {
unsigned char mask;
if (device_may_wakeup(dev))
mask = RTC_IRQMASK & ~RTC_AIE;
else
mask = RTC_IRQMASK;
tmp &= ~mask;
CMOS_WRITE(tmp, RTC_CONTROL);
if (use_hpet_alarm())
hpet_mask_rtc_irq_bit(mask);
cmos_checkintr(cmos, tmp);
}
spin_unlock_irq(&rtc_lock);
if ((tmp & RTC_AIE) && !cmos_use_acpi_alarm()) {
cmos->enabled_wake = 1;
if (cmos->wake_on)
cmos->wake_on(dev);
else
enable_irq_wake(cmos->irq);
}
memset(&cmos->saved_wkalrm, 0, sizeof(struct rtc_wkalrm));
cmos_read_alarm(dev, &cmos->saved_wkalrm);
dev_dbg(dev, "suspend%s, ctrl %02x\n",
(tmp & RTC_AIE) ? ", alarm may wake" : "",
tmp);
return 0;
}
/* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even
* after a detour through G3 "mechanical off", although the ACPI spec
* says wakeup should only work from G1/S4 "hibernate". To most users,
* distinctions between S4 and S5 are pointless. So when the hardware
* allows, don't draw that distinction.
*/
static inline int cmos_poweroff(struct device *dev)
{
if (!IS_ENABLED(CONFIG_PM))
return -ENOSYS;
return cmos_suspend(dev);
}
static void cmos_check_wkalrm(struct device *dev)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
struct rtc_wkalrm current_alarm;
time64_t t_now;
time64_t t_current_expires;
time64_t t_saved_expires;
struct rtc_time now;
/* Check if we have RTC Alarm armed */
if (!(cmos->suspend_ctrl & RTC_AIE))
return;
cmos_read_time(dev, &now);
t_now = rtc_tm_to_time64(&now);
/*
* ACPI RTC wake event is cleared after resume from STR,
* ACK the rtc irq here
*/
if (t_now >= cmos->alarm_expires && cmos_use_acpi_alarm()) {
local_irq_disable();
cmos_interrupt(0, (void *)cmos->rtc);
local_irq_enable();
return;
}
memset(¤t_alarm, 0, sizeof(struct rtc_wkalrm));
cmos_read_alarm(dev, ¤t_alarm);
t_current_expires = rtc_tm_to_time64(¤t_alarm.time);
t_saved_expires = rtc_tm_to_time64(&cmos->saved_wkalrm.time);
if (t_current_expires != t_saved_expires ||
cmos->saved_wkalrm.enabled != current_alarm.enabled) {
cmos_set_alarm(dev, &cmos->saved_wkalrm);
}
}
static int __maybe_unused cmos_resume(struct device *dev)
{
struct cmos_rtc *cmos = dev_get_drvdata(dev);
unsigned char tmp;
if (cmos->enabled_wake && !cmos_use_acpi_alarm()) {
if (cmos->wake_off)
cmos->wake_off(dev);
else
disable_irq_wake(cmos->irq);
cmos->enabled_wake = 0;
}
/* The BIOS might have changed the alarm, restore it */
cmos_check_wkalrm(dev);
spin_lock_irq(&rtc_lock);
tmp = cmos->suspend_ctrl;
cmos->suspend_ctrl = 0;
/* re-enable any irqs previously active */
if (tmp & RTC_IRQMASK) {
unsigned char mask;
if (device_may_wakeup(dev) && use_hpet_alarm())
hpet_rtc_timer_init();
do {
CMOS_WRITE(tmp, RTC_CONTROL);
if (use_hpet_alarm())
hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK);
mask = CMOS_READ(RTC_INTR_FLAGS);
mask &= (tmp & RTC_IRQMASK) | RTC_IRQF;
if (!use_hpet_alarm() || !is_intr(mask))
break;
/* force one-shot behavior if HPET blocked
* the wake alarm's irq
*/
rtc_update_irq(cmos->rtc, 1, mask);
tmp &= ~RTC_AIE;
hpet_mask_rtc_irq_bit(RTC_AIE);
} while (mask & RTC_AIE);
if (tmp & RTC_AIE)
cmos_check_acpi_rtc_status(dev, &tmp);
}
spin_unlock_irq(&rtc_lock);
dev_dbg(dev, "resume, ctrl %02x\n", tmp);
return 0;
}
static SIMPLE_DEV_PM_OPS(cmos_pm_ops, cmos_suspend, cmos_resume);
/*----------------------------------------------------------------*/
/* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus.
* ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs
* probably list them in similar PNPBIOS tables; so PNP is more common.
*
* We don't use legacy "poke at the hardware" probing. Ancient PCs that
* predate even PNPBIOS should set up platform_bus devices.
*/
#ifdef CONFIG_PNP
#include <linux/pnp.h>
static int cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id)
{
int irq;
if (pnp_port_start(pnp, 0) == 0x70 && !pnp_irq_valid(pnp, 0)) {
irq = 0;
#ifdef CONFIG_X86
/* Some machines contain a PNP entry for the RTC, but
* don't define the IRQ. It should always be safe to
* hardcode it on systems with a legacy PIC.
*/
if (nr_legacy_irqs())
irq = RTC_IRQ;
#endif
} else {
irq = pnp_irq(pnp, 0);
}
return cmos_do_probe(&pnp->dev, pnp_get_resource(pnp, IORESOURCE_IO, 0), irq);
}
static void cmos_pnp_remove(struct pnp_dev *pnp)
{
cmos_do_remove(&pnp->dev);
}
static void cmos_pnp_shutdown(struct pnp_dev *pnp)
{
struct device *dev = &pnp->dev;
struct cmos_rtc *cmos = dev_get_drvdata(dev);
if (system_state == SYSTEM_POWER_OFF) {
int retval = cmos_poweroff(dev);
if (cmos_aie_poweroff(dev) < 0 && !retval)
return;
}
cmos_do_shutdown(cmos->irq);
}
static const struct pnp_device_id rtc_ids[] = {
{ .id = "PNP0b00", },
{ .id = "PNP0b01", },
{ .id = "PNP0b02", },
{ },
};
MODULE_DEVICE_TABLE(pnp, rtc_ids);
static struct pnp_driver cmos_pnp_driver = {
.name = driver_name,
.id_table = rtc_ids,
.probe = cmos_pnp_probe,
.remove = cmos_pnp_remove,
.shutdown = cmos_pnp_shutdown,
/* flag ensures resume() gets called, and stops syslog spam */
.flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
.driver = {
.pm = &cmos_pm_ops,
},
};
#endif /* CONFIG_PNP */
#ifdef CONFIG_OF
static const struct of_device_id of_cmos_match[] = {
{
.compatible = "motorola,mc146818",
},
{ },
};
MODULE_DEVICE_TABLE(of, of_cmos_match);
static __init void cmos_of_init(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const __be32 *val;
if (!node)
return;
val = of_get_property(node, "ctrl-reg", NULL);
if (val)
CMOS_WRITE(be32_to_cpup(val), RTC_CONTROL);
val = of_get_property(node, "freq-reg", NULL);
if (val)
CMOS_WRITE(be32_to_cpup(val), RTC_FREQ_SELECT);
}
#else
static inline void cmos_of_init(struct platform_device *pdev) {}
#endif
/*----------------------------------------------------------------*/
/* Platform setup should have set up an RTC device, when PNP is
* unavailable ... this could happen even on (older) PCs.
*/
static int __init cmos_platform_probe(struct platform_device *pdev)
{
struct resource *resource;
int irq;
cmos_of_init(pdev);
if (RTC_IOMAPPED)
resource = platform_get_resource(pdev, IORESOURCE_IO, 0);
else
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
irq = -1;
return cmos_do_probe(&pdev->dev, resource, irq);
}
static void cmos_platform_remove(struct platform_device *pdev)
{
cmos_do_remove(&pdev->dev);
}
static void cmos_platform_shutdown(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cmos_rtc *cmos = dev_get_drvdata(dev);
if (system_state == SYSTEM_POWER_OFF) {
int retval = cmos_poweroff(dev);
if (cmos_aie_poweroff(dev) < 0 && !retval)
return;
}
cmos_do_shutdown(cmos->irq);
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:rtc_cmos");
static struct platform_driver cmos_platform_driver = {
.remove_new = cmos_platform_remove,
.shutdown = cmos_platform_shutdown,
.driver = {
.name = driver_name,
.pm = &cmos_pm_ops,
.of_match_table = of_match_ptr(of_cmos_match),
}
};
#ifdef CONFIG_PNP
static bool pnp_driver_registered;
#endif
static bool platform_driver_registered;
static int __init cmos_init(void)
{
int retval = 0;
#ifdef CONFIG_PNP
retval = pnp_register_driver(&cmos_pnp_driver);
if (retval == 0)
pnp_driver_registered = true;
#endif
if (!cmos_rtc.dev) {
retval = platform_driver_probe(&cmos_platform_driver,
cmos_platform_probe);
if (retval == 0)
platform_driver_registered = true;
}
if (retval == 0)
return 0;
#ifdef CONFIG_PNP
if (pnp_driver_registered)
pnp_unregister_driver(&cmos_pnp_driver);
#endif
return retval;
}
module_init(cmos_init);
static void __exit cmos_exit(void)
{
#ifdef CONFIG_PNP
if (pnp_driver_registered)
pnp_unregister_driver(&cmos_pnp_driver);
#endif
if (platform_driver_registered)
platform_driver_unregister(&cmos_platform_driver);
}
module_exit(cmos_exit);
MODULE_AUTHOR("David Brownell");
MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-cmos.c |
// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2012 Sven Schnelle <[email protected]>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/rtc.h>
#include <linux/types.h>
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <linux/io.h>
#define DS2404_STATUS_REG 0x200
#define DS2404_CONTROL_REG 0x201
#define DS2404_RTC_REG 0x202
#define DS2404_WRITE_SCRATCHPAD_CMD 0x0f
#define DS2404_READ_SCRATCHPAD_CMD 0xaa
#define DS2404_COPY_SCRATCHPAD_CMD 0x55
#define DS2404_READ_MEMORY_CMD 0xf0
#define DS2404_RST 0
#define DS2404_CLK 1
#define DS2404_DQ 2
struct ds2404 {
struct device *dev;
struct gpio_desc *rst_gpiod;
struct gpio_desc *clk_gpiod;
struct gpio_desc *dq_gpiod;
struct rtc_device *rtc;
};
static int ds2404_gpio_map(struct ds2404 *chip, struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
/* This will de-assert RESET, declare this GPIO as GPIOD_ACTIVE_LOW */
chip->rst_gpiod = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW);
if (IS_ERR(chip->rst_gpiod))
return PTR_ERR(chip->rst_gpiod);
chip->clk_gpiod = devm_gpiod_get(dev, "clk", GPIOD_OUT_HIGH);
if (IS_ERR(chip->clk_gpiod))
return PTR_ERR(chip->clk_gpiod);
chip->dq_gpiod = devm_gpiod_get(dev, "dq", GPIOD_ASIS);
if (IS_ERR(chip->dq_gpiod))
return PTR_ERR(chip->dq_gpiod);
return 0;
}
static void ds2404_reset(struct ds2404 *chip)
{
gpiod_set_value(chip->rst_gpiod, 1);
udelay(1000);
gpiod_set_value(chip->rst_gpiod, 0);
gpiod_set_value(chip->clk_gpiod, 0);
gpiod_direction_output(chip->dq_gpiod, 0);
udelay(10);
}
static void ds2404_write_byte(struct ds2404 *chip, u8 byte)
{
int i;
gpiod_direction_output(chip->dq_gpiod, 1);
for (i = 0; i < 8; i++) {
gpiod_set_value(chip->dq_gpiod, byte & (1 << i));
udelay(10);
gpiod_set_value(chip->clk_gpiod, 1);
udelay(10);
gpiod_set_value(chip->clk_gpiod, 0);
udelay(10);
}
}
static u8 ds2404_read_byte(struct ds2404 *chip)
{
int i;
u8 ret = 0;
gpiod_direction_input(chip->dq_gpiod);
for (i = 0; i < 8; i++) {
gpiod_set_value(chip->clk_gpiod, 0);
udelay(10);
if (gpiod_get_value(chip->dq_gpiod))
ret |= 1 << i;
gpiod_set_value(chip->clk_gpiod, 1);
udelay(10);
}
return ret;
}
static void ds2404_read_memory(struct ds2404 *chip, u16 offset,
int length, u8 *out)
{
ds2404_reset(chip);
ds2404_write_byte(chip, DS2404_READ_MEMORY_CMD);
ds2404_write_byte(chip, offset & 0xff);
ds2404_write_byte(chip, (offset >> 8) & 0xff);
while (length--)
*out++ = ds2404_read_byte(chip);
}
static void ds2404_write_memory(struct ds2404 *chip, u16 offset,
int length, u8 *out)
{
int i;
u8 ta01, ta02, es;
ds2404_reset(chip);
ds2404_write_byte(chip, DS2404_WRITE_SCRATCHPAD_CMD);
ds2404_write_byte(chip, offset & 0xff);
ds2404_write_byte(chip, (offset >> 8) & 0xff);
for (i = 0; i < length; i++)
ds2404_write_byte(chip, out[i]);
ds2404_reset(chip);
ds2404_write_byte(chip, DS2404_READ_SCRATCHPAD_CMD);
ta01 = ds2404_read_byte(chip);
ta02 = ds2404_read_byte(chip);
es = ds2404_read_byte(chip);
for (i = 0; i < length; i++) {
if (out[i] != ds2404_read_byte(chip)) {
dev_err(chip->dev, "read invalid data\n");
return;
}
}
ds2404_reset(chip);
ds2404_write_byte(chip, DS2404_COPY_SCRATCHPAD_CMD);
ds2404_write_byte(chip, ta01);
ds2404_write_byte(chip, ta02);
ds2404_write_byte(chip, es);
while (gpiod_get_value(chip->dq_gpiod))
;
}
static void ds2404_enable_osc(struct ds2404 *chip)
{
u8 in[1] = { 0x10 }; /* enable oscillator */
ds2404_write_memory(chip, 0x201, 1, in);
}
static int ds2404_read_time(struct device *dev, struct rtc_time *dt)
{
struct ds2404 *chip = dev_get_drvdata(dev);
unsigned long time = 0;
__le32 hw_time = 0;
ds2404_read_memory(chip, 0x203, 4, (u8 *)&hw_time);
time = le32_to_cpu(hw_time);
rtc_time64_to_tm(time, dt);
return 0;
}
static int ds2404_set_time(struct device *dev, struct rtc_time *dt)
{
struct ds2404 *chip = dev_get_drvdata(dev);
u32 time = cpu_to_le32(rtc_tm_to_time64(dt));
ds2404_write_memory(chip, 0x203, 4, (u8 *)&time);
return 0;
}
static const struct rtc_class_ops ds2404_rtc_ops = {
.read_time = ds2404_read_time,
.set_time = ds2404_set_time,
};
static int rtc_probe(struct platform_device *pdev)
{
struct ds2404 *chip;
int retval = -EBUSY;
chip = devm_kzalloc(&pdev->dev, sizeof(struct ds2404), GFP_KERNEL);
if (!chip)
return -ENOMEM;
chip->dev = &pdev->dev;
chip->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(chip->rtc))
return PTR_ERR(chip->rtc);
retval = ds2404_gpio_map(chip, pdev);
if (retval)
return retval;
platform_set_drvdata(pdev, chip);
chip->rtc->ops = &ds2404_rtc_ops;
chip->rtc->range_max = U32_MAX;
retval = devm_rtc_register_device(chip->rtc);
if (retval)
return retval;
ds2404_enable_osc(chip);
return 0;
}
static struct platform_driver rtc_device_driver = {
.probe = rtc_probe,
.driver = {
.name = "ds2404",
},
};
module_platform_driver(rtc_device_driver);
MODULE_DESCRIPTION("DS2404 RTC");
MODULE_AUTHOR("Sven Schnelle");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ds2404");
| linux-master | drivers/rtc/rtc-ds2404.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* An RTC driver for the NVIDIA Tegra 200 series internal RTC.
*
* Copyright (c) 2010-2019, NVIDIA Corporation.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/rtc.h>
#include <linux/slab.h>
/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
#define TEGRA_RTC_REG_BUSY 0x004
#define TEGRA_RTC_REG_SECONDS 0x008
/* When msec is read, the seconds are buffered into shadow seconds. */
#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
#define TEGRA_RTC_REG_INTR_MASK 0x028
/* write 1 bits to clear status bits */
#define TEGRA_RTC_REG_INTR_STATUS 0x02c
/* bits in INTR_MASK */
#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
/* bits in INTR_STATUS */
#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
struct tegra_rtc_info {
struct platform_device *pdev;
struct rtc_device *rtc;
void __iomem *base; /* NULL if not initialized */
struct clk *clk;
int irq; /* alarm and periodic IRQ */
spinlock_t lock;
};
/*
* RTC hardware is busy when it is updating its values over AHB once every
* eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
* write. CPU is always free to read.
*/
static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
{
return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
}
/*
* Wait for hardware to be ready for writing. This function tries to maximize
* the amount of time before the next update. It does this by waiting for the
* RTC to become busy with its periodic update, then returning once the RTC
* first becomes not busy.
*
* This periodic update (where the seconds and milliseconds are copied to the
* AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
* function allows us to make some assumptions without introducing a race,
* because 250 us is plenty of time to read/write a value.
*/
static int tegra_rtc_wait_while_busy(struct device *dev)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
int retries = 500; /* ~490 us is the worst case, ~250 us is best */
/*
* First wait for the RTC to become busy. This is when it posts its
* updated seconds+msec registers to AHB side.
*/
while (tegra_rtc_check_busy(info)) {
if (!retries--)
goto retry_failed;
udelay(1);
}
/* now we have about 250 us to manipulate registers */
return 0;
retry_failed:
dev_err(dev, "write failed: retry count exceeded\n");
return -ETIMEDOUT;
}
static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
unsigned long flags;
u32 sec;
/*
* RTC hardware copies seconds to shadow seconds when a read of
* milliseconds occurs. use a lock to keep other threads out.
*/
spin_lock_irqsave(&info->lock, flags);
readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
spin_unlock_irqrestore(&info->lock, flags);
rtc_time64_to_tm(sec, tm);
dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
return 0;
}
static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
u32 sec;
int ret;
/* convert tm to seconds */
sec = rtc_tm_to_time64(tm);
dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
/* seconds only written if wait succeeded */
ret = tegra_rtc_wait_while_busy(dev);
if (!ret)
writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
dev_vdbg(dev, "time read back as %d\n",
readl(info->base + TEGRA_RTC_REG_SECONDS));
return ret;
}
static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
u32 sec, value;
sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
if (sec == 0) {
/* alarm is disabled */
alarm->enabled = 0;
} else {
/* alarm is enabled */
alarm->enabled = 1;
rtc_time64_to_tm(sec, &alarm->time);
}
value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
return 0;
}
static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
unsigned long flags;
u32 status;
tegra_rtc_wait_while_busy(dev);
spin_lock_irqsave(&info->lock, flags);
/* read the original value, and OR in the flag */
status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
if (enabled)
status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
else
status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
spin_unlock_irqrestore(&info->lock, flags);
return 0;
}
static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
u32 sec;
if (alarm->enabled)
sec = rtc_tm_to_time64(&alarm->time);
else
sec = 0;
tegra_rtc_wait_while_busy(dev);
writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
dev_vdbg(dev, "alarm read back as %d\n",
readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
/* if successfully written and alarm is enabled ... */
if (sec) {
tegra_rtc_alarm_irq_enable(dev, 1);
dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
} else {
/* disable alarm if 0 or write error */
dev_vdbg(dev, "alarm disabled\n");
tegra_rtc_alarm_irq_enable(dev, 0);
}
return 0;
}
static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
{
if (!dev || !dev->driver)
return 0;
seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
return 0;
}
static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
{
struct device *dev = data;
struct tegra_rtc_info *info = dev_get_drvdata(dev);
unsigned long events = 0;
u32 status;
status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
if (status) {
/* clear the interrupt masks and status on any IRQ */
tegra_rtc_wait_while_busy(dev);
spin_lock(&info->lock);
writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
spin_unlock(&info->lock);
}
/* check if alarm */
if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
events |= RTC_IRQF | RTC_AF;
/* check if periodic */
if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
events |= RTC_IRQF | RTC_PF;
rtc_update_irq(info->rtc, 1, events);
return IRQ_HANDLED;
}
static const struct rtc_class_ops tegra_rtc_ops = {
.read_time = tegra_rtc_read_time,
.set_time = tegra_rtc_set_time,
.read_alarm = tegra_rtc_read_alarm,
.set_alarm = tegra_rtc_set_alarm,
.proc = tegra_rtc_proc,
.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
};
static const struct of_device_id tegra_rtc_dt_match[] = {
{ .compatible = "nvidia,tegra20-rtc", },
{}
};
MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
static int tegra_rtc_probe(struct platform_device *pdev)
{
struct tegra_rtc_info *info;
int ret;
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->base))
return PTR_ERR(info->base);
ret = platform_get_irq(pdev, 0);
if (ret <= 0)
return ret;
info->irq = ret;
info->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(info->rtc))
return PTR_ERR(info->rtc);
info->rtc->ops = &tegra_rtc_ops;
info->rtc->range_max = U32_MAX;
info->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(info->clk))
return PTR_ERR(info->clk);
ret = clk_prepare_enable(info->clk);
if (ret < 0)
return ret;
/* set context info */
info->pdev = pdev;
spin_lock_init(&info->lock);
platform_set_drvdata(pdev, info);
/* clear out the hardware */
writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
device_init_wakeup(&pdev->dev, 1);
ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
goto disable_clk;
}
ret = devm_rtc_register_device(info->rtc);
if (ret)
goto disable_clk;
dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
return 0;
disable_clk:
clk_disable_unprepare(info->clk);
return ret;
}
static void tegra_rtc_remove(struct platform_device *pdev)
{
struct tegra_rtc_info *info = platform_get_drvdata(pdev);
clk_disable_unprepare(info->clk);
}
#ifdef CONFIG_PM_SLEEP
static int tegra_rtc_suspend(struct device *dev)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
tegra_rtc_wait_while_busy(dev);
/* only use ALARM0 as a wake source */
writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
info->base + TEGRA_RTC_REG_INTR_MASK);
dev_vdbg(dev, "alarm sec = %d\n",
readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
device_may_wakeup(dev), info->irq);
/* leave the alarms on as a wake source */
if (device_may_wakeup(dev))
enable_irq_wake(info->irq);
return 0;
}
static int tegra_rtc_resume(struct device *dev)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
device_may_wakeup(dev));
/* alarms were left on as a wake source, turn them off */
if (device_may_wakeup(dev))
disable_irq_wake(info->irq);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
static void tegra_rtc_shutdown(struct platform_device *pdev)
{
dev_vdbg(&pdev->dev, "disabling interrupts\n");
tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
}
static struct platform_driver tegra_rtc_driver = {
.probe = tegra_rtc_probe,
.remove_new = tegra_rtc_remove,
.shutdown = tegra_rtc_shutdown,
.driver = {
.name = "tegra_rtc",
.of_match_table = tegra_rtc_dt_match,
.pm = &tegra_rtc_pm_ops,
},
};
module_platform_driver(tegra_rtc_driver);
MODULE_AUTHOR("Jon Mayo <[email protected]>");
MODULE_DESCRIPTION("driver for Tegra internal RTC");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-tegra.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* EPSON TOYOCOM RTC-7301SF/DG Driver
*
* Copyright (c) 2016 Akinobu Mita <[email protected]>
*
* Based on rtc-rp5c01.c
*
* Datasheet: http://www5.epsondevice.com/en/products/parallel/rtc7301sf.html
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#define DRV_NAME "rtc-r7301"
#define RTC7301_1_SEC 0x0 /* Bank 0 and Band 1 */
#define RTC7301_10_SEC 0x1 /* Bank 0 and Band 1 */
#define RTC7301_AE BIT(3)
#define RTC7301_1_MIN 0x2 /* Bank 0 and Band 1 */
#define RTC7301_10_MIN 0x3 /* Bank 0 and Band 1 */
#define RTC7301_1_HOUR 0x4 /* Bank 0 and Band 1 */
#define RTC7301_10_HOUR 0x5 /* Bank 0 and Band 1 */
#define RTC7301_DAY_OF_WEEK 0x6 /* Bank 0 and Band 1 */
#define RTC7301_1_DAY 0x7 /* Bank 0 and Band 1 */
#define RTC7301_10_DAY 0x8 /* Bank 0 and Band 1 */
#define RTC7301_1_MONTH 0x9 /* Bank 0 */
#define RTC7301_10_MONTH 0xa /* Bank 0 */
#define RTC7301_1_YEAR 0xb /* Bank 0 */
#define RTC7301_10_YEAR 0xc /* Bank 0 */
#define RTC7301_100_YEAR 0xd /* Bank 0 */
#define RTC7301_1000_YEAR 0xe /* Bank 0 */
#define RTC7301_ALARM_CONTROL 0xe /* Bank 1 */
#define RTC7301_ALARM_CONTROL_AIE BIT(0)
#define RTC7301_ALARM_CONTROL_AF BIT(1)
#define RTC7301_TIMER_CONTROL 0xe /* Bank 2 */
#define RTC7301_TIMER_CONTROL_TIE BIT(0)
#define RTC7301_TIMER_CONTROL_TF BIT(1)
#define RTC7301_CONTROL 0xf /* All banks */
#define RTC7301_CONTROL_BUSY BIT(0)
#define RTC7301_CONTROL_STOP BIT(1)
#define RTC7301_CONTROL_BANK_SEL_0 BIT(2)
#define RTC7301_CONTROL_BANK_SEL_1 BIT(3)
struct rtc7301_priv {
struct regmap *regmap;
int irq;
spinlock_t lock;
u8 bank;
};
static const struct regmap_config rtc7301_regmap_config = {
.reg_bits = 32,
.val_bits = 8,
.reg_stride = 4,
};
static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg)
{
int reg_stride = regmap_get_reg_stride(priv->regmap);
unsigned int val;
regmap_read(priv->regmap, reg_stride * reg, &val);
return val & 0xf;
}
static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg)
{
int reg_stride = regmap_get_reg_stride(priv->regmap);
regmap_write(priv->regmap, reg_stride * reg, val);
}
static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg,
u8 mask, u8 val)
{
int reg_stride = regmap_get_reg_stride(priv->regmap);
regmap_update_bits(priv->regmap, reg_stride * reg, mask, val);
}
static int rtc7301_wait_while_busy(struct rtc7301_priv *priv)
{
int retries = 100;
while (retries-- > 0) {
u8 val;
val = rtc7301_read(priv, RTC7301_CONTROL);
if (!(val & RTC7301_CONTROL_BUSY))
return 0;
udelay(300);
}
return -ETIMEDOUT;
}
static void rtc7301_stop(struct rtc7301_priv *priv)
{
rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP,
RTC7301_CONTROL_STOP);
}
static void rtc7301_start(struct rtc7301_priv *priv)
{
rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP, 0);
}
static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)
{
u8 val = 0;
if (bank == priv->bank)
return;
if (bank & BIT(0))
val |= RTC7301_CONTROL_BANK_SEL_0;
if (bank & BIT(1))
val |= RTC7301_CONTROL_BANK_SEL_1;
rtc7301_update_bits(priv, RTC7301_CONTROL,
RTC7301_CONTROL_BANK_SEL_0 |
RTC7301_CONTROL_BANK_SEL_1, val);
priv->bank = bank;
}
static void rtc7301_get_time(struct rtc7301_priv *priv, struct rtc_time *tm,
bool alarm)
{
int year;
tm->tm_sec = rtc7301_read(priv, RTC7301_1_SEC);
tm->tm_sec += (rtc7301_read(priv, RTC7301_10_SEC) & ~RTC7301_AE) * 10;
tm->tm_min = rtc7301_read(priv, RTC7301_1_MIN);
tm->tm_min += (rtc7301_read(priv, RTC7301_10_MIN) & ~RTC7301_AE) * 10;
tm->tm_hour = rtc7301_read(priv, RTC7301_1_HOUR);
tm->tm_hour += (rtc7301_read(priv, RTC7301_10_HOUR) & ~RTC7301_AE) * 10;
tm->tm_mday = rtc7301_read(priv, RTC7301_1_DAY);
tm->tm_mday += (rtc7301_read(priv, RTC7301_10_DAY) & ~RTC7301_AE) * 10;
if (alarm) {
tm->tm_wday = -1;
tm->tm_mon = -1;
tm->tm_year = -1;
tm->tm_yday = -1;
tm->tm_isdst = -1;
return;
}
tm->tm_wday = (rtc7301_read(priv, RTC7301_DAY_OF_WEEK) & ~RTC7301_AE);
tm->tm_mon = rtc7301_read(priv, RTC7301_10_MONTH) * 10 +
rtc7301_read(priv, RTC7301_1_MONTH) - 1;
year = rtc7301_read(priv, RTC7301_1000_YEAR) * 1000 +
rtc7301_read(priv, RTC7301_100_YEAR) * 100 +
rtc7301_read(priv, RTC7301_10_YEAR) * 10 +
rtc7301_read(priv, RTC7301_1_YEAR);
tm->tm_year = year - 1900;
}
static void rtc7301_write_time(struct rtc7301_priv *priv, struct rtc_time *tm,
bool alarm)
{
int year;
rtc7301_write(priv, tm->tm_sec % 10, RTC7301_1_SEC);
rtc7301_write(priv, tm->tm_sec / 10, RTC7301_10_SEC);
rtc7301_write(priv, tm->tm_min % 10, RTC7301_1_MIN);
rtc7301_write(priv, tm->tm_min / 10, RTC7301_10_MIN);
rtc7301_write(priv, tm->tm_hour % 10, RTC7301_1_HOUR);
rtc7301_write(priv, tm->tm_hour / 10, RTC7301_10_HOUR);
rtc7301_write(priv, tm->tm_mday % 10, RTC7301_1_DAY);
rtc7301_write(priv, tm->tm_mday / 10, RTC7301_10_DAY);
/* Don't care for alarm register */
rtc7301_write(priv, alarm ? RTC7301_AE : tm->tm_wday,
RTC7301_DAY_OF_WEEK);
if (alarm)
return;
rtc7301_write(priv, (tm->tm_mon + 1) % 10, RTC7301_1_MONTH);
rtc7301_write(priv, (tm->tm_mon + 1) / 10, RTC7301_10_MONTH);
year = tm->tm_year + 1900;
rtc7301_write(priv, year % 10, RTC7301_1_YEAR);
rtc7301_write(priv, (year / 10) % 10, RTC7301_10_YEAR);
rtc7301_write(priv, (year / 100) % 10, RTC7301_100_YEAR);
rtc7301_write(priv, year / 1000, RTC7301_1000_YEAR);
}
static void rtc7301_alarm_irq(struct rtc7301_priv *priv, unsigned int enabled)
{
rtc7301_update_bits(priv, RTC7301_ALARM_CONTROL,
RTC7301_ALARM_CONTROL_AF |
RTC7301_ALARM_CONTROL_AIE,
enabled ? RTC7301_ALARM_CONTROL_AIE : 0);
}
static int rtc7301_read_time(struct device *dev, struct rtc_time *tm)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
unsigned long flags;
int err;
spin_lock_irqsave(&priv->lock, flags);
rtc7301_select_bank(priv, 0);
err = rtc7301_wait_while_busy(priv);
if (!err)
rtc7301_get_time(priv, tm, false);
spin_unlock_irqrestore(&priv->lock, flags);
return err;
}
static int rtc7301_set_time(struct device *dev, struct rtc_time *tm)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rtc7301_stop(priv);
udelay(300);
rtc7301_select_bank(priv, 0);
rtc7301_write_time(priv, tm, false);
rtc7301_start(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static int rtc7301_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
unsigned long flags;
u8 alrm_ctrl;
if (priv->irq <= 0)
return -EINVAL;
spin_lock_irqsave(&priv->lock, flags);
rtc7301_select_bank(priv, 1);
rtc7301_get_time(priv, &alarm->time, true);
alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
alarm->enabled = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AIE);
alarm->pending = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AF);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static int rtc7301_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
unsigned long flags;
if (priv->irq <= 0)
return -EINVAL;
spin_lock_irqsave(&priv->lock, flags);
rtc7301_select_bank(priv, 1);
rtc7301_write_time(priv, &alarm->time, true);
rtc7301_alarm_irq(priv, alarm->enabled);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static int rtc7301_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
unsigned long flags;
if (priv->irq <= 0)
return -EINVAL;
spin_lock_irqsave(&priv->lock, flags);
rtc7301_select_bank(priv, 1);
rtc7301_alarm_irq(priv, enabled);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
static const struct rtc_class_ops rtc7301_rtc_ops = {
.read_time = rtc7301_read_time,
.set_time = rtc7301_set_time,
.read_alarm = rtc7301_read_alarm,
.set_alarm = rtc7301_set_alarm,
.alarm_irq_enable = rtc7301_alarm_irq_enable,
};
static irqreturn_t rtc7301_irq_handler(int irq, void *dev_id)
{
struct rtc_device *rtc = dev_id;
struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent);
irqreturn_t ret = IRQ_NONE;
u8 alrm_ctrl;
spin_lock(&priv->lock);
rtc7301_select_bank(priv, 1);
alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
if (alrm_ctrl & RTC7301_ALARM_CONTROL_AF) {
ret = IRQ_HANDLED;
rtc7301_alarm_irq(priv, false);
rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
}
spin_unlock(&priv->lock);
return ret;
}
static void rtc7301_init(struct rtc7301_priv *priv)
{
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rtc7301_select_bank(priv, 2);
rtc7301_write(priv, 0, RTC7301_TIMER_CONTROL);
spin_unlock_irqrestore(&priv->lock, flags);
}
static int __init rtc7301_rtc_probe(struct platform_device *dev)
{
void __iomem *regs;
struct rtc7301_priv *priv;
struct rtc_device *rtc;
int ret;
priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
regs = devm_platform_ioremap_resource(dev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
priv->regmap = devm_regmap_init_mmio(&dev->dev, regs,
&rtc7301_regmap_config);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
priv->irq = platform_get_irq(dev, 0);
spin_lock_init(&priv->lock);
priv->bank = -1;
rtc7301_init(priv);
platform_set_drvdata(dev, priv);
rtc = devm_rtc_device_register(&dev->dev, DRV_NAME, &rtc7301_rtc_ops,
THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
if (priv->irq > 0) {
ret = devm_request_irq(&dev->dev, priv->irq,
rtc7301_irq_handler, IRQF_SHARED,
dev_name(&dev->dev), rtc);
if (ret) {
priv->irq = 0;
dev_err(&dev->dev, "unable to request IRQ\n");
} else {
device_set_wakeup_capable(&dev->dev, true);
}
}
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int rtc7301_suspend(struct device *dev)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(priv->irq);
return 0;
}
static int rtc7301_resume(struct device *dev)
{
struct rtc7301_priv *priv = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(priv->irq);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(rtc7301_pm_ops, rtc7301_suspend, rtc7301_resume);
static const struct of_device_id rtc7301_dt_match[] = {
{ .compatible = "epson,rtc7301sf" },
{ .compatible = "epson,rtc7301dg" },
{}
};
MODULE_DEVICE_TABLE(of, rtc7301_dt_match);
static struct platform_driver rtc7301_rtc_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = rtc7301_dt_match,
.pm = &rtc7301_pm_ops,
},
};
module_platform_driver_probe(rtc7301_rtc_driver, rtc7301_rtc_probe);
MODULE_AUTHOR("Akinobu Mita <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("EPSON TOYOCOM RTC-7301SF/DG Driver");
MODULE_ALIAS("platform:rtc-r7301");
| linux-master | drivers/rtc/rtc-r7301.c |
// SPDX-License-Identifier: GPL-2.0-only
/* drivers/rtc/rtc-s3c.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright (c) 2004,2006 Simtec Electronics
* Ben Dooks, <[email protected]>
* http://armlinux.simtec.co.uk/
*
* S3C2410/S3C2440/S3C24XX Internal RTC Driver
*/
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/clk.h>
#include <linux/log2.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <asm/irq.h>
#include "rtc-s3c.h"
struct s3c_rtc {
struct device *dev;
struct rtc_device *rtc;
void __iomem *base;
struct clk *rtc_clk;
struct clk *rtc_src_clk;
bool alarm_enabled;
const struct s3c_rtc_data *data;
int irq_alarm;
spinlock_t alarm_lock;
bool wake_en;
};
struct s3c_rtc_data {
bool needs_src_clk;
void (*irq_handler) (struct s3c_rtc *info, int mask);
void (*enable) (struct s3c_rtc *info);
void (*disable) (struct s3c_rtc *info);
};
static int s3c_rtc_enable_clk(struct s3c_rtc *info)
{
int ret;
ret = clk_enable(info->rtc_clk);
if (ret)
return ret;
if (info->data->needs_src_clk) {
ret = clk_enable(info->rtc_src_clk);
if (ret) {
clk_disable(info->rtc_clk);
return ret;
}
}
return 0;
}
static void s3c_rtc_disable_clk(struct s3c_rtc *info)
{
if (info->data->needs_src_clk)
clk_disable(info->rtc_src_clk);
clk_disable(info->rtc_clk);
}
/* IRQ Handler */
static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
{
struct s3c_rtc *info = (struct s3c_rtc *)id;
if (info->data->irq_handler)
info->data->irq_handler(info, S3C2410_INTP_ALM);
return IRQ_HANDLED;
}
/* Update control registers */
static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
unsigned long flags;
unsigned int tmp;
int ret;
dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled);
ret = s3c_rtc_enable_clk(info);
if (ret)
return ret;
tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
if (enabled)
tmp |= S3C2410_RTCALM_ALMEN;
writeb(tmp, info->base + S3C2410_RTCALM);
spin_lock_irqsave(&info->alarm_lock, flags);
if (info->alarm_enabled && !enabled)
s3c_rtc_disable_clk(info);
else if (!info->alarm_enabled && enabled)
ret = s3c_rtc_enable_clk(info);
info->alarm_enabled = enabled;
spin_unlock_irqrestore(&info->alarm_lock, flags);
s3c_rtc_disable_clk(info);
return ret;
}
/* Read time from RTC and convert it from BCD */
static int s3c_rtc_read_time(struct s3c_rtc *info, struct rtc_time *tm)
{
unsigned int have_retried = 0;
int ret;
ret = s3c_rtc_enable_clk(info);
if (ret)
return ret;
retry_get_time:
tm->tm_min = readb(info->base + S3C2410_RTCMIN);
tm->tm_hour = readb(info->base + S3C2410_RTCHOUR);
tm->tm_mday = readb(info->base + S3C2410_RTCDATE);
tm->tm_mon = readb(info->base + S3C2410_RTCMON);
tm->tm_year = readb(info->base + S3C2410_RTCYEAR);
tm->tm_sec = readb(info->base + S3C2410_RTCSEC);
/*
* The only way to work out whether the system was mid-update
* when we read it is to check the second counter, and if it
* is zero, then we re-try the entire read
*/
if (tm->tm_sec == 0 && !have_retried) {
have_retried = 1;
goto retry_get_time;
}
s3c_rtc_disable_clk(info);
tm->tm_sec = bcd2bin(tm->tm_sec);
tm->tm_min = bcd2bin(tm->tm_min);
tm->tm_hour = bcd2bin(tm->tm_hour);
tm->tm_mday = bcd2bin(tm->tm_mday);
tm->tm_mon = bcd2bin(tm->tm_mon);
tm->tm_year = bcd2bin(tm->tm_year);
return 0;
}
/* Convert time to BCD and write it to RTC */
static int s3c_rtc_write_time(struct s3c_rtc *info, const struct rtc_time *tm)
{
int ret;
ret = s3c_rtc_enable_clk(info);
if (ret)
return ret;
writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC);
writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN);
writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR);
writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE);
writeb(bin2bcd(tm->tm_mon), info->base + S3C2410_RTCMON);
writeb(bin2bcd(tm->tm_year), info->base + S3C2410_RTCYEAR);
s3c_rtc_disable_clk(info);
return 0;
}
static int s3c_rtc_gettime(struct device *dev, struct rtc_time *tm)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
int ret;
ret = s3c_rtc_read_time(info, tm);
if (ret)
return ret;
/* Convert internal representation to actual date/time */
tm->tm_year += 100;
tm->tm_mon -= 1;
dev_dbg(dev, "read time %ptR\n", tm);
return 0;
}
static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
struct rtc_time rtc_tm = *tm;
dev_dbg(dev, "set time %ptR\n", tm);
/*
* Convert actual date/time to internal representation.
* We get around Y2K by simply not supporting it.
*/
rtc_tm.tm_year -= 100;
rtc_tm.tm_mon += 1;
return s3c_rtc_write_time(info, &rtc_tm);
}
static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
struct rtc_time *alm_tm = &alrm->time;
unsigned int alm_en;
int ret;
ret = s3c_rtc_enable_clk(info);
if (ret)
return ret;
alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC);
alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN);
alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR);
alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON);
alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE);
alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR);
alm_en = readb(info->base + S3C2410_RTCALM);
s3c_rtc_disable_clk(info);
alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
dev_dbg(dev, "read alarm %d, %ptR\n", alm_en, alm_tm);
/* decode the alarm enable field */
if (alm_en & S3C2410_RTCALM_SECEN)
alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
if (alm_en & S3C2410_RTCALM_MINEN)
alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
if (alm_en & S3C2410_RTCALM_HOUREN)
alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
if (alm_en & S3C2410_RTCALM_DAYEN)
alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
if (alm_en & S3C2410_RTCALM_MONEN) {
alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
alm_tm->tm_mon -= 1;
}
if (alm_en & S3C2410_RTCALM_YEAREN)
alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
return 0;
}
static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
unsigned int alrm_en;
int ret;
dev_dbg(dev, "s3c_rtc_setalarm: %d, %ptR\n", alrm->enabled, tm);
ret = s3c_rtc_enable_clk(info);
if (ret)
return ret;
alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
writeb(0x00, info->base + S3C2410_RTCALM);
if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
alrm_en |= S3C2410_RTCALM_SECEN;
writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC);
}
if (tm->tm_min < 60 && tm->tm_min >= 0) {
alrm_en |= S3C2410_RTCALM_MINEN;
writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN);
}
if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
alrm_en |= S3C2410_RTCALM_HOUREN;
writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR);
}
if (tm->tm_mon < 12 && tm->tm_mon >= 0) {
alrm_en |= S3C2410_RTCALM_MONEN;
writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_ALMMON);
}
if (tm->tm_mday <= 31 && tm->tm_mday >= 1) {
alrm_en |= S3C2410_RTCALM_DAYEN;
writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_ALMDATE);
}
dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
writeb(alrm_en, info->base + S3C2410_RTCALM);
s3c_rtc_setaie(dev, alrm->enabled);
s3c_rtc_disable_clk(info);
return 0;
}
static const struct rtc_class_ops s3c_rtcops = {
.read_time = s3c_rtc_gettime,
.set_time = s3c_rtc_settime,
.read_alarm = s3c_rtc_getalarm,
.set_alarm = s3c_rtc_setalarm,
.alarm_irq_enable = s3c_rtc_setaie,
};
static void s3c24xx_rtc_enable(struct s3c_rtc *info)
{
unsigned int con, tmp;
con = readw(info->base + S3C2410_RTCCON);
/* re-enable the device, and check it is ok */
if ((con & S3C2410_RTCCON_RTCEN) == 0) {
dev_info(info->dev, "rtc disabled, re-enabling\n");
tmp = readw(info->base + S3C2410_RTCCON);
writew(tmp | S3C2410_RTCCON_RTCEN, info->base + S3C2410_RTCCON);
}
if (con & S3C2410_RTCCON_CNTSEL) {
dev_info(info->dev, "removing RTCCON_CNTSEL\n");
tmp = readw(info->base + S3C2410_RTCCON);
writew(tmp & ~S3C2410_RTCCON_CNTSEL,
info->base + S3C2410_RTCCON);
}
if (con & S3C2410_RTCCON_CLKRST) {
dev_info(info->dev, "removing RTCCON_CLKRST\n");
tmp = readw(info->base + S3C2410_RTCCON);
writew(tmp & ~S3C2410_RTCCON_CLKRST,
info->base + S3C2410_RTCCON);
}
}
static void s3c24xx_rtc_disable(struct s3c_rtc *info)
{
unsigned int con;
con = readw(info->base + S3C2410_RTCCON);
con &= ~S3C2410_RTCCON_RTCEN;
writew(con, info->base + S3C2410_RTCCON);
con = readb(info->base + S3C2410_TICNT);
con &= ~S3C2410_TICNT_ENABLE;
writeb(con, info->base + S3C2410_TICNT);
}
static void s3c6410_rtc_disable(struct s3c_rtc *info)
{
unsigned int con;
con = readw(info->base + S3C2410_RTCCON);
con &= ~S3C64XX_RTCCON_TICEN;
con &= ~S3C2410_RTCCON_RTCEN;
writew(con, info->base + S3C2410_RTCCON);
}
static void s3c_rtc_remove(struct platform_device *pdev)
{
struct s3c_rtc *info = platform_get_drvdata(pdev);
s3c_rtc_setaie(info->dev, 0);
if (info->data->needs_src_clk)
clk_unprepare(info->rtc_src_clk);
clk_unprepare(info->rtc_clk);
}
static int s3c_rtc_probe(struct platform_device *pdev)
{
struct s3c_rtc *info = NULL;
int ret;
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->dev = &pdev->dev;
info->data = of_device_get_match_data(&pdev->dev);
if (!info->data) {
dev_err(&pdev->dev, "failed getting s3c_rtc_data\n");
return -EINVAL;
}
spin_lock_init(&info->alarm_lock);
platform_set_drvdata(pdev, info);
info->irq_alarm = platform_get_irq(pdev, 0);
if (info->irq_alarm < 0)
return info->irq_alarm;
dev_dbg(&pdev->dev, "s3c2410_rtc: alarm irq %d\n", info->irq_alarm);
/* get the memory region */
info->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->base))
return PTR_ERR(info->base);
info->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
if (IS_ERR(info->rtc_clk))
return dev_err_probe(&pdev->dev, PTR_ERR(info->rtc_clk),
"failed to find rtc clock\n");
ret = clk_prepare_enable(info->rtc_clk);
if (ret)
return ret;
if (info->data->needs_src_clk) {
info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src");
if (IS_ERR(info->rtc_src_clk)) {
ret = dev_err_probe(&pdev->dev, PTR_ERR(info->rtc_src_clk),
"failed to find rtc source clock\n");
goto err_src_clk;
}
ret = clk_prepare_enable(info->rtc_src_clk);
if (ret)
goto err_src_clk;
}
/* disable RTC enable bits potentially set by the bootloader */
if (info->data->disable)
info->data->disable(info);
/* check to see if everything is setup correctly */
if (info->data->enable)
info->data->enable(info);
dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
readw(info->base + S3C2410_RTCCON));
device_init_wakeup(&pdev->dev, 1);
info->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(info->rtc)) {
ret = PTR_ERR(info->rtc);
goto err_nortc;
}
info->rtc->ops = &s3c_rtcops;
info->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
info->rtc->range_max = RTC_TIMESTAMP_END_2099;
ret = devm_rtc_register_device(info->rtc);
if (ret)
goto err_nortc;
ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq,
0, "s3c2410-rtc alarm", info);
if (ret) {
dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret);
goto err_nortc;
}
s3c_rtc_disable_clk(info);
return 0;
err_nortc:
if (info->data->disable)
info->data->disable(info);
if (info->data->needs_src_clk)
clk_disable_unprepare(info->rtc_src_clk);
err_src_clk:
clk_disable_unprepare(info->rtc_clk);
return ret;
}
#ifdef CONFIG_PM_SLEEP
static int s3c_rtc_suspend(struct device *dev)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
int ret;
ret = s3c_rtc_enable_clk(info);
if (ret)
return ret;
if (info->data->disable)
info->data->disable(info);
if (device_may_wakeup(dev) && !info->wake_en) {
if (enable_irq_wake(info->irq_alarm) == 0)
info->wake_en = true;
else
dev_err(dev, "enable_irq_wake failed\n");
}
return 0;
}
static int s3c_rtc_resume(struct device *dev)
{
struct s3c_rtc *info = dev_get_drvdata(dev);
if (info->data->enable)
info->data->enable(info);
s3c_rtc_disable_clk(info);
if (device_may_wakeup(dev) && info->wake_en) {
disable_irq_wake(info->irq_alarm);
info->wake_en = false;
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask)
{
rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
}
static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask)
{
rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
writeb(mask, info->base + S3C2410_INTP);
}
static struct s3c_rtc_data const s3c2410_rtc_data = {
.irq_handler = s3c24xx_rtc_irq,
.enable = s3c24xx_rtc_enable,
.disable = s3c24xx_rtc_disable,
};
static struct s3c_rtc_data const s3c2416_rtc_data = {
.irq_handler = s3c24xx_rtc_irq,
.enable = s3c24xx_rtc_enable,
.disable = s3c24xx_rtc_disable,
};
static struct s3c_rtc_data const s3c2443_rtc_data = {
.irq_handler = s3c24xx_rtc_irq,
.enable = s3c24xx_rtc_enable,
.disable = s3c24xx_rtc_disable,
};
static struct s3c_rtc_data const s3c6410_rtc_data = {
.needs_src_clk = true,
.irq_handler = s3c6410_rtc_irq,
.enable = s3c24xx_rtc_enable,
.disable = s3c6410_rtc_disable,
};
static const __maybe_unused struct of_device_id s3c_rtc_dt_match[] = {
{
.compatible = "samsung,s3c2410-rtc",
.data = &s3c2410_rtc_data,
}, {
.compatible = "samsung,s3c2416-rtc",
.data = &s3c2416_rtc_data,
}, {
.compatible = "samsung,s3c2443-rtc",
.data = &s3c2443_rtc_data,
}, {
.compatible = "samsung,s3c6410-rtc",
.data = &s3c6410_rtc_data,
}, {
.compatible = "samsung,exynos3250-rtc",
.data = &s3c6410_rtc_data,
},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
static struct platform_driver s3c_rtc_driver = {
.probe = s3c_rtc_probe,
.remove_new = s3c_rtc_remove,
.driver = {
.name = "s3c-rtc",
.pm = &s3c_rtc_pm_ops,
.of_match_table = of_match_ptr(s3c_rtc_dt_match),
},
};
module_platform_driver(s3c_rtc_driver);
MODULE_DESCRIPTION("Samsung S3C RTC Driver");
MODULE_AUTHOR("Ben Dooks <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:s3c2410-rtc");
| linux-master | drivers/rtc/rtc-s3c.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RTC subsystem, sysfs interface
*
* Copyright (C) 2005 Tower Technologies
* Author: Alessandro Zummo <[email protected]>
*/
#include <linux/kstrtox.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include "rtc-core.h"
/* device attributes */
/*
* NOTE: RTC times displayed in sysfs use the RTC's timezone. That's
* ideally UTC. However, PCs that also boot to MS-Windows normally use
* the local time and change to match daylight savings time. That affects
* attributes including date, time, since_epoch, and wakealarm.
*/
static ssize_t
name_show(struct device *dev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%s %s\n", dev_driver_string(dev->parent),
dev_name(dev->parent));
}
static DEVICE_ATTR_RO(name);
static ssize_t
date_show(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t retval;
struct rtc_time tm;
retval = rtc_read_time(to_rtc_device(dev), &tm);
if (retval)
return retval;
return sprintf(buf, "%ptRd\n", &tm);
}
static DEVICE_ATTR_RO(date);
static ssize_t
time_show(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t retval;
struct rtc_time tm;
retval = rtc_read_time(to_rtc_device(dev), &tm);
if (retval)
return retval;
return sprintf(buf, "%ptRt\n", &tm);
}
static DEVICE_ATTR_RO(time);
static ssize_t
since_epoch_show(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t retval;
struct rtc_time tm;
retval = rtc_read_time(to_rtc_device(dev), &tm);
if (retval == 0) {
time64_t time;
time = rtc_tm_to_time64(&tm);
retval = sprintf(buf, "%lld\n", time);
}
return retval;
}
static DEVICE_ATTR_RO(since_epoch);
static ssize_t
max_user_freq_show(struct device *dev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", to_rtc_device(dev)->max_user_freq);
}
static ssize_t
max_user_freq_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t n)
{
struct rtc_device *rtc = to_rtc_device(dev);
unsigned long val;
int err;
err = kstrtoul(buf, 0, &val);
if (err)
return err;
if (val >= 4096 || val == 0)
return -EINVAL;
rtc->max_user_freq = (int)val;
return n;
}
static DEVICE_ATTR_RW(max_user_freq);
/**
* hctosys_show - indicate if the given RTC set the system time
* @dev: The device that the attribute belongs to.
* @attr: The attribute being read.
* @buf: The result buffer.
*
* buf is "1" if the system clock was set by this RTC at the last
* boot or resume event.
*/
static ssize_t
hctosys_show(struct device *dev, struct device_attribute *attr, char *buf)
{
#ifdef CONFIG_RTC_HCTOSYS_DEVICE
if (rtc_hctosys_ret == 0 &&
strcmp(dev_name(&to_rtc_device(dev)->dev),
CONFIG_RTC_HCTOSYS_DEVICE) == 0)
return sprintf(buf, "1\n");
#endif
return sprintf(buf, "0\n");
}
static DEVICE_ATTR_RO(hctosys);
static ssize_t
wakealarm_show(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t retval;
time64_t alarm;
struct rtc_wkalrm alm;
/* Don't show disabled alarms. For uniformity, RTC alarms are
* conceptually one-shot, even though some common RTCs (on PCs)
* don't actually work that way.
*
* NOTE: RTC implementations where the alarm doesn't match an
* exact YYYY-MM-DD HH:MM[:SS] date *must* disable their RTC
* alarms after they trigger, to ensure one-shot semantics.
*/
retval = rtc_read_alarm(to_rtc_device(dev), &alm);
if (retval == 0 && alm.enabled) {
alarm = rtc_tm_to_time64(&alm.time);
retval = sprintf(buf, "%lld\n", alarm);
}
return retval;
}
static ssize_t
wakealarm_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t n)
{
ssize_t retval;
time64_t now, alarm;
time64_t push = 0;
struct rtc_wkalrm alm;
struct rtc_device *rtc = to_rtc_device(dev);
const char *buf_ptr;
int adjust = 0;
/* Only request alarms that trigger in the future. Disable them
* by writing another time, e.g. 0 meaning Jan 1 1970 UTC.
*/
retval = rtc_read_time(rtc, &alm.time);
if (retval < 0)
return retval;
now = rtc_tm_to_time64(&alm.time);
buf_ptr = buf;
if (*buf_ptr == '+') {
buf_ptr++;
if (*buf_ptr == '=') {
buf_ptr++;
push = 1;
} else {
adjust = 1;
}
}
retval = kstrtos64(buf_ptr, 0, &alarm);
if (retval)
return retval;
if (adjust)
alarm += now;
if (alarm > now || push) {
/* Avoid accidentally clobbering active alarms; we can't
* entirely prevent that here, without even the minimal
* locking from the /dev/rtcN api.
*/
retval = rtc_read_alarm(rtc, &alm);
if (retval < 0)
return retval;
if (alm.enabled) {
if (push) {
push = rtc_tm_to_time64(&alm.time);
alarm += push;
} else
return -EBUSY;
} else if (push)
return -EINVAL;
alm.enabled = 1;
} else {
alm.enabled = 0;
/* Provide a valid future alarm time. Linux isn't EFI,
* this time won't be ignored when disabling the alarm.
*/
alarm = now + 300;
}
rtc_time64_to_tm(alarm, &alm.time);
retval = rtc_set_alarm(rtc, &alm);
return (retval < 0) ? retval : n;
}
static DEVICE_ATTR_RW(wakealarm);
static ssize_t
offset_show(struct device *dev, struct device_attribute *attr, char *buf)
{
ssize_t retval;
long offset;
retval = rtc_read_offset(to_rtc_device(dev), &offset);
if (retval == 0)
retval = sprintf(buf, "%ld\n", offset);
return retval;
}
static ssize_t
offset_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t n)
{
ssize_t retval;
long offset;
retval = kstrtol(buf, 10, &offset);
if (retval == 0)
retval = rtc_set_offset(to_rtc_device(dev), offset);
return (retval < 0) ? retval : n;
}
static DEVICE_ATTR_RW(offset);
static ssize_t
range_show(struct device *dev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "[%lld,%llu]\n", to_rtc_device(dev)->range_min,
to_rtc_device(dev)->range_max);
}
static DEVICE_ATTR_RO(range);
static struct attribute *rtc_attrs[] = {
&dev_attr_name.attr,
&dev_attr_date.attr,
&dev_attr_time.attr,
&dev_attr_since_epoch.attr,
&dev_attr_max_user_freq.attr,
&dev_attr_hctosys.attr,
&dev_attr_wakealarm.attr,
&dev_attr_offset.attr,
&dev_attr_range.attr,
NULL,
};
/* The reason to trigger an alarm with no process watching it (via sysfs)
* is its side effect: waking from a system state like suspend-to-RAM or
* suspend-to-disk. So: no attribute unless that side effect is possible.
* (Userspace may disable that mechanism later.)
*/
static bool rtc_does_wakealarm(struct rtc_device *rtc)
{
if (!device_can_wakeup(rtc->dev.parent))
return false;
return !!test_bit(RTC_FEATURE_ALARM, rtc->features);
}
static umode_t rtc_attr_is_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct device *dev = kobj_to_dev(kobj);
struct rtc_device *rtc = to_rtc_device(dev);
umode_t mode = attr->mode;
if (attr == &dev_attr_wakealarm.attr) {
if (!rtc_does_wakealarm(rtc))
mode = 0;
} else if (attr == &dev_attr_offset.attr) {
if (!rtc->ops->set_offset)
mode = 0;
} else if (attr == &dev_attr_range.attr) {
if (!(rtc->range_max - rtc->range_min))
mode = 0;
}
return mode;
}
static struct attribute_group rtc_attr_group = {
.is_visible = rtc_attr_is_visible,
.attrs = rtc_attrs,
};
static const struct attribute_group *rtc_attr_groups[] = {
&rtc_attr_group,
NULL
};
const struct attribute_group **rtc_get_dev_attribute_groups(void)
{
return rtc_attr_groups;
}
int rtc_add_groups(struct rtc_device *rtc, const struct attribute_group **grps)
{
size_t old_cnt = 0, add_cnt = 0, new_cnt;
const struct attribute_group **groups, **old;
if (!grps)
return -EINVAL;
groups = rtc->dev.groups;
if (groups)
for (; *groups; groups++)
old_cnt++;
for (groups = grps; *groups; groups++)
add_cnt++;
new_cnt = old_cnt + add_cnt + 1;
groups = devm_kcalloc(&rtc->dev, new_cnt, sizeof(*groups), GFP_KERNEL);
if (!groups)
return -ENOMEM;
memcpy(groups, rtc->dev.groups, old_cnt * sizeof(*groups));
memcpy(groups + old_cnt, grps, add_cnt * sizeof(*groups));
groups[old_cnt + add_cnt] = NULL;
old = rtc->dev.groups;
rtc->dev.groups = groups;
if (old && old != rtc_attr_groups)
devm_kfree(&rtc->dev, old);
return 0;
}
EXPORT_SYMBOL(rtc_add_groups);
int rtc_add_group(struct rtc_device *rtc, const struct attribute_group *grp)
{
const struct attribute_group *groups[] = { grp, NULL };
return rtc_add_groups(rtc, groups);
}
EXPORT_SYMBOL(rtc_add_group);
| linux-master | drivers/rtc/sysfs.c |
// SPDX-License-Identifier: GPL-2.0+
//
// RTC driver for Maxim MAX8997
//
// Copyright (C) 2013 Samsung Electronics Co.Ltd
//
// based on rtc-max8998.c
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/max8997-private.h>
#include <linux/irqdomain.h>
/* Module parameter for WTSR function control */
static int wtsr_en = 1;
module_param(wtsr_en, int, 0444);
MODULE_PARM_DESC(wtsr_en, "Watchdog Timeout & Software Reset (default=on)");
/* Module parameter for SMPL function control */
static int smpl_en = 1;
module_param(smpl_en, int, 0444);
MODULE_PARM_DESC(smpl_en, "Sudden Momentary Power Loss (default=on)");
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK (1 << MODEL24_SHIFT)
/* RTC Update Register1 */
#define RTC_UDR_SHIFT 0
#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
/* WTSR and SMPL Register */
#define WTSRT_SHIFT 0
#define SMPLT_SHIFT 2
#define WTSR_EN_SHIFT 6
#define SMPL_EN_SHIFT 7
#define WTSRT_MASK (3 << WTSRT_SHIFT)
#define SMPLT_MASK (3 << SMPLT_SHIFT)
#define WTSR_EN_MASK (1 << WTSR_EN_SHIFT)
#define SMPL_EN_MASK (1 << SMPL_EN_SHIFT)
/* RTC Hour register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_MONTH,
RTC_YEAR,
RTC_DATE,
RTC_NR_TIME
};
struct max8997_rtc_info {
struct device *dev;
struct max8997_dev *max8997;
struct i2c_client *rtc;
struct rtc_device *rtc_dev;
struct mutex lock;
int virq;
int rtc_24hr_mode;
};
static void max8997_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
int rtc_24hr_mode)
{
tm->tm_sec = data[RTC_SEC] & 0x7f;
tm->tm_min = data[RTC_MIN] & 0x7f;
if (rtc_24hr_mode)
tm->tm_hour = data[RTC_HOUR] & 0x1f;
else {
tm->tm_hour = data[RTC_HOUR] & 0x0f;
if (data[RTC_HOUR] & HOUR_PM_MASK)
tm->tm_hour += 12;
}
tm->tm_wday = fls(data[RTC_WEEKDAY] & 0x7f) - 1;
tm->tm_mday = data[RTC_DATE] & 0x1f;
tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
tm->tm_year = (data[RTC_YEAR] & 0x7f) + 100;
tm->tm_yday = 0;
tm->tm_isdst = 0;
}
static int max8997_rtc_tm_to_data(struct rtc_time *tm, u8 *data)
{
data[RTC_SEC] = tm->tm_sec;
data[RTC_MIN] = tm->tm_min;
data[RTC_HOUR] = tm->tm_hour;
data[RTC_WEEKDAY] = 1 << tm->tm_wday;
data[RTC_DATE] = tm->tm_mday;
data[RTC_MONTH] = tm->tm_mon + 1;
data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
if (tm->tm_year < 100) {
pr_warn("RTC cannot handle the year %d. Assume it's 2000.\n",
1900 + tm->tm_year);
return -EINVAL;
}
return 0;
}
static inline int max8997_rtc_set_update_reg(struct max8997_rtc_info *info)
{
int ret;
ret = max8997_write_reg(info->rtc, MAX8997_RTC_UPDATE1,
RTC_UDR_MASK);
if (ret < 0)
dev_err(info->dev, "%s: fail to write update reg(%d)\n",
__func__, ret);
else {
/* Minimum 16ms delay required before RTC update.
* Otherwise, we may read and update based on out-of-date
* value */
msleep(20);
}
return ret;
}
static int max8997_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct max8997_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
mutex_lock(&info->lock);
ret = max8997_bulk_read(info->rtc, MAX8997_RTC_SEC, RTC_NR_TIME, data);
mutex_unlock(&info->lock);
if (ret < 0) {
dev_err(info->dev, "%s: fail to read time reg(%d)\n", __func__,
ret);
return ret;
}
max8997_rtc_data_to_tm(data, tm, info->rtc_24hr_mode);
return 0;
}
static int max8997_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct max8997_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = max8997_rtc_tm_to_data(tm, data);
if (ret < 0)
return ret;
mutex_lock(&info->lock);
ret = max8997_bulk_write(info->rtc, MAX8997_RTC_SEC, RTC_NR_TIME, data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write time reg(%d)\n", __func__,
ret);
goto out;
}
ret = max8997_rtc_set_update_reg(info);
out:
mutex_unlock(&info->lock);
return ret;
}
static int max8997_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max8997_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
u8 val;
int i, ret;
mutex_lock(&info->lock);
ret = max8997_bulk_read(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
data);
if (ret < 0) {
dev_err(info->dev, "%s:%d fail to read alarm reg(%d)\n",
__func__, __LINE__, ret);
goto out;
}
max8997_rtc_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
alrm->enabled = 0;
for (i = 0; i < RTC_NR_TIME; i++) {
if (data[i] & ALARM_ENABLE_MASK) {
alrm->enabled = 1;
break;
}
}
alrm->pending = 0;
ret = max8997_read_reg(info->max8997->i2c, MAX8997_REG_STATUS1, &val);
if (ret < 0) {
dev_err(info->dev, "%s:%d fail to read status1 reg(%d)\n",
__func__, __LINE__, ret);
goto out;
}
if (val & (1 << 4)) /* RTCA1 */
alrm->pending = 1;
out:
mutex_unlock(&info->lock);
return ret;
}
static int max8997_rtc_stop_alarm(struct max8997_rtc_info *info)
{
u8 data[RTC_NR_TIME];
int ret, i;
if (!mutex_is_locked(&info->lock))
dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
ret = max8997_bulk_read(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
__func__, ret);
goto out;
}
for (i = 0; i < RTC_NR_TIME; i++)
data[i] &= ~ALARM_ENABLE_MASK;
ret = max8997_bulk_write(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
__func__, ret);
goto out;
}
ret = max8997_rtc_set_update_reg(info);
out:
return ret;
}
static int max8997_rtc_start_alarm(struct max8997_rtc_info *info)
{
u8 data[RTC_NR_TIME];
int ret;
if (!mutex_is_locked(&info->lock))
dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
ret = max8997_bulk_read(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
__func__, ret);
goto out;
}
data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
if (data[RTC_MONTH] & 0xf)
data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
if (data[RTC_YEAR] & 0x7f)
data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
if (data[RTC_DATE] & 0x1f)
data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
ret = max8997_bulk_write(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
__func__, ret);
goto out;
}
ret = max8997_rtc_set_update_reg(info);
out:
return ret;
}
static int max8997_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max8997_rtc_info *info = dev_get_drvdata(dev);
u8 data[RTC_NR_TIME];
int ret;
ret = max8997_rtc_tm_to_data(&alrm->time, data);
if (ret < 0)
return ret;
dev_info(info->dev, "%s: %d-%02d-%02d %02d:%02d:%02d\n", __func__,
data[RTC_YEAR] + 2000, data[RTC_MONTH], data[RTC_DATE],
data[RTC_HOUR], data[RTC_MIN], data[RTC_SEC]);
mutex_lock(&info->lock);
ret = max8997_rtc_stop_alarm(info);
if (ret < 0)
goto out;
ret = max8997_bulk_write(info->rtc, MAX8997_RTC_ALARM1_SEC, RTC_NR_TIME,
data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
__func__, ret);
goto out;
}
ret = max8997_rtc_set_update_reg(info);
if (ret < 0)
goto out;
if (alrm->enabled)
ret = max8997_rtc_start_alarm(info);
out:
mutex_unlock(&info->lock);
return ret;
}
static int max8997_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct max8997_rtc_info *info = dev_get_drvdata(dev);
int ret;
mutex_lock(&info->lock);
if (enabled)
ret = max8997_rtc_start_alarm(info);
else
ret = max8997_rtc_stop_alarm(info);
mutex_unlock(&info->lock);
return ret;
}
static irqreturn_t max8997_rtc_alarm_irq(int irq, void *data)
{
struct max8997_rtc_info *info = data;
dev_info(info->dev, "%s:irq(%d)\n", __func__, irq);
rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static const struct rtc_class_ops max8997_rtc_ops = {
.read_time = max8997_rtc_read_time,
.set_time = max8997_rtc_set_time,
.read_alarm = max8997_rtc_read_alarm,
.set_alarm = max8997_rtc_set_alarm,
.alarm_irq_enable = max8997_rtc_alarm_irq_enable,
};
static void max8997_rtc_enable_wtsr(struct max8997_rtc_info *info, bool enable)
{
int ret;
u8 val, mask;
if (!wtsr_en)
return;
if (enable)
val = (1 << WTSR_EN_SHIFT) | (3 << WTSRT_SHIFT);
else
val = 0;
mask = WTSR_EN_MASK | WTSRT_MASK;
dev_info(info->dev, "%s: %s WTSR\n", __func__,
enable ? "enable" : "disable");
ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask);
if (ret < 0) {
dev_err(info->dev, "%s: fail to update WTSR reg(%d)\n",
__func__, ret);
return;
}
max8997_rtc_set_update_reg(info);
}
static void max8997_rtc_enable_smpl(struct max8997_rtc_info *info, bool enable)
{
int ret;
u8 val, mask;
if (!smpl_en)
return;
if (enable)
val = (1 << SMPL_EN_SHIFT) | (0 << SMPLT_SHIFT);
else
val = 0;
mask = SMPL_EN_MASK | SMPLT_MASK;
dev_info(info->dev, "%s: %s SMPL\n", __func__,
enable ? "enable" : "disable");
ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask);
if (ret < 0) {
dev_err(info->dev, "%s: fail to update SMPL reg(%d)\n",
__func__, ret);
return;
}
max8997_rtc_set_update_reg(info);
val = 0;
max8997_read_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, &val);
pr_info("WTSR_SMPL(0x%02x)\n", val);
}
static int max8997_rtc_init_reg(struct max8997_rtc_info *info)
{
u8 data[2];
int ret;
/* Set RTC control register : Binary mode, 24hour mdoe */
data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
info->rtc_24hr_mode = 1;
ret = max8997_bulk_write(info->rtc, MAX8997_RTC_CTRLMASK, 2, data);
if (ret < 0) {
dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
__func__, ret);
return ret;
}
ret = max8997_rtc_set_update_reg(info);
return ret;
}
static int max8997_rtc_probe(struct platform_device *pdev)
{
struct max8997_dev *max8997 = dev_get_drvdata(pdev->dev.parent);
struct max8997_rtc_info *info;
int ret, virq;
info = devm_kzalloc(&pdev->dev, sizeof(struct max8997_rtc_info),
GFP_KERNEL);
if (!info)
return -ENOMEM;
mutex_init(&info->lock);
info->dev = &pdev->dev;
info->max8997 = max8997;
info->rtc = max8997->rtc;
platform_set_drvdata(pdev, info);
ret = max8997_rtc_init_reg(info);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
return ret;
}
max8997_rtc_enable_wtsr(info, true);
max8997_rtc_enable_smpl(info, true);
device_init_wakeup(&pdev->dev, 1);
info->rtc_dev = devm_rtc_device_register(&pdev->dev, "max8997-rtc",
&max8997_rtc_ops, THIS_MODULE);
if (IS_ERR(info->rtc_dev)) {
ret = PTR_ERR(info->rtc_dev);
dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
return ret;
}
virq = irq_create_mapping(max8997->irq_domain, MAX8997_PMICIRQ_RTCA1);
if (!virq) {
dev_err(&pdev->dev, "Failed to create mapping alarm IRQ\n");
ret = -ENXIO;
goto err_out;
}
info->virq = virq;
ret = devm_request_threaded_irq(&pdev->dev, virq, NULL,
max8997_rtc_alarm_irq, 0,
"rtc-alarm0", info);
if (ret < 0)
dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
info->virq, ret);
err_out:
return ret;
}
static void max8997_rtc_shutdown(struct platform_device *pdev)
{
struct max8997_rtc_info *info = platform_get_drvdata(pdev);
max8997_rtc_enable_wtsr(info, false);
max8997_rtc_enable_smpl(info, false);
}
static const struct platform_device_id rtc_id[] = {
{ "max8997-rtc", 0 },
{},
};
MODULE_DEVICE_TABLE(platform, rtc_id);
static struct platform_driver max8997_rtc_driver = {
.driver = {
.name = "max8997-rtc",
},
.probe = max8997_rtc_probe,
.shutdown = max8997_rtc_shutdown,
.id_table = rtc_id,
};
module_platform_driver(max8997_rtc_driver);
MODULE_DESCRIPTION("Maxim MAX8997 RTC driver");
MODULE_AUTHOR("<[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-max8997.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* TI OMAP Real Time Clock interface for Linux
*
* Copyright (C) 2003 MontaVista Software, Inc.
* Author: George G. Davis <[email protected]> or <[email protected]>
*
* Copyright (C) 2006 David Brownell (new RTC framework)
* Copyright (C) 2014 Johan Hovold <[email protected]>
*/
#include <linux/bcd.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/rtc.h>
#include <linux/rtc/rtc-omap.h>
/*
* The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
* with century-range alarm matching, driven by the 32kHz clock.
*
* The main user-visible ways it differs from PC RTCs are by omitting
* "don't care" alarm fields and sub-second periodic IRQs, and having
* an autoadjust mechanism to calibrate to the true oscillator rate.
*
* Board-specific wiring options include using split power mode with
* RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
* and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
* low power modes) for OMAP1 boards (OMAP-L138 has this built into
* the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
*/
/* RTC registers */
#define OMAP_RTC_SECONDS_REG 0x00
#define OMAP_RTC_MINUTES_REG 0x04
#define OMAP_RTC_HOURS_REG 0x08
#define OMAP_RTC_DAYS_REG 0x0C
#define OMAP_RTC_MONTHS_REG 0x10
#define OMAP_RTC_YEARS_REG 0x14
#define OMAP_RTC_WEEKS_REG 0x18
#define OMAP_RTC_ALARM_SECONDS_REG 0x20
#define OMAP_RTC_ALARM_MINUTES_REG 0x24
#define OMAP_RTC_ALARM_HOURS_REG 0x28
#define OMAP_RTC_ALARM_DAYS_REG 0x2c
#define OMAP_RTC_ALARM_MONTHS_REG 0x30
#define OMAP_RTC_ALARM_YEARS_REG 0x34
#define OMAP_RTC_CTRL_REG 0x40
#define OMAP_RTC_STATUS_REG 0x44
#define OMAP_RTC_INTERRUPTS_REG 0x48
#define OMAP_RTC_COMP_LSB_REG 0x4c
#define OMAP_RTC_COMP_MSB_REG 0x50
#define OMAP_RTC_OSC_REG 0x54
#define OMAP_RTC_SCRATCH0_REG 0x60
#define OMAP_RTC_SCRATCH1_REG 0x64
#define OMAP_RTC_SCRATCH2_REG 0x68
#define OMAP_RTC_KICK0_REG 0x6c
#define OMAP_RTC_KICK1_REG 0x70
#define OMAP_RTC_IRQWAKEEN 0x7c
#define OMAP_RTC_ALARM2_SECONDS_REG 0x80
#define OMAP_RTC_ALARM2_MINUTES_REG 0x84
#define OMAP_RTC_ALARM2_HOURS_REG 0x88
#define OMAP_RTC_ALARM2_DAYS_REG 0x8c
#define OMAP_RTC_ALARM2_MONTHS_REG 0x90
#define OMAP_RTC_ALARM2_YEARS_REG 0x94
#define OMAP_RTC_PMIC_REG 0x98
/* OMAP_RTC_CTRL_REG bit fields: */
#define OMAP_RTC_CTRL_SPLIT BIT(7)
#define OMAP_RTC_CTRL_DISABLE BIT(6)
#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
#define OMAP_RTC_CTRL_TEST BIT(4)
#define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
#define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
#define OMAP_RTC_CTRL_ROUND_30S BIT(1)
#define OMAP_RTC_CTRL_STOP BIT(0)
/* OMAP_RTC_STATUS_REG bit fields: */
#define OMAP_RTC_STATUS_POWER_UP BIT(7)
#define OMAP_RTC_STATUS_ALARM2 BIT(7)
#define OMAP_RTC_STATUS_ALARM BIT(6)
#define OMAP_RTC_STATUS_1D_EVENT BIT(5)
#define OMAP_RTC_STATUS_1H_EVENT BIT(4)
#define OMAP_RTC_STATUS_1M_EVENT BIT(3)
#define OMAP_RTC_STATUS_1S_EVENT BIT(2)
#define OMAP_RTC_STATUS_RUN BIT(1)
#define OMAP_RTC_STATUS_BUSY BIT(0)
/* OMAP_RTC_INTERRUPTS_REG bit fields: */
#define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4)
#define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
#define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
/* OMAP_RTC_OSC_REG bit fields: */
#define OMAP_RTC_OSC_32KCLK_EN BIT(6)
#define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
/* OMAP_RTC_IRQWAKEEN bit fields: */
#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
/* OMAP_RTC_PMIC bit fields: */
#define OMAP_RTC_PMIC_POWER_EN_EN BIT(16)
#define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x)
#define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x)
/* OMAP_RTC_KICKER values */
#define KICK0_VALUE 0x83e70b13
#define KICK1_VALUE 0x95a4f1e0
struct omap_rtc;
struct omap_rtc_device_type {
bool has_32kclk_en;
bool has_irqwakeen;
bool has_pmic_mode;
bool has_power_up_reset;
void (*lock)(struct omap_rtc *rtc);
void (*unlock)(struct omap_rtc *rtc);
};
struct omap_rtc {
struct rtc_device *rtc;
void __iomem *base;
struct clk *clk;
int irq_alarm;
int irq_timer;
u8 interrupts_reg;
bool is_pmic_controller;
bool has_ext_clk;
bool is_suspending;
const struct omap_rtc_device_type *type;
struct pinctrl_dev *pctldev;
};
static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
{
return readb(rtc->base + reg);
}
static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
{
return readl(rtc->base + reg);
}
static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
{
writeb(val, rtc->base + reg);
}
static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
{
writel(val, rtc->base + reg);
}
static void am3352_rtc_unlock(struct omap_rtc *rtc)
{
rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
}
static void am3352_rtc_lock(struct omap_rtc *rtc)
{
rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
}
static void default_rtc_unlock(struct omap_rtc *rtc)
{
}
static void default_rtc_lock(struct omap_rtc *rtc)
{
}
/*
* We rely on the rtc framework to handle locking (rtc->ops_lock),
* so the only other requirement is that register accesses which
* require BUSY to be clear are made with IRQs locally disabled
*/
static void rtc_wait_not_busy(struct omap_rtc *rtc)
{
int count;
u8 status;
/* BUSY may stay active for 1/32768 second (~30 usec) */
for (count = 0; count < 50; count++) {
status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
if (!(status & OMAP_RTC_STATUS_BUSY))
break;
udelay(1);
}
/* now we have ~15 usec to read/write various registers */
}
static irqreturn_t rtc_irq(int irq, void *dev_id)
{
struct omap_rtc *rtc = dev_id;
unsigned long events = 0;
u8 irq_data;
irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
/* alarm irq? */
if (irq_data & OMAP_RTC_STATUS_ALARM) {
rtc->type->unlock(rtc);
rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
rtc->type->lock(rtc);
events |= RTC_IRQF | RTC_AF;
}
/* 1/sec periodic/update irq? */
if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
events |= RTC_IRQF | RTC_UF;
rtc_update_irq(rtc->rtc, 1, events);
return IRQ_HANDLED;
}
static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
u8 reg, irqwake_reg = 0;
local_irq_disable();
rtc_wait_not_busy(rtc);
reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
if (rtc->type->has_irqwakeen)
irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
if (enabled) {
reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
} else {
reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
}
rtc_wait_not_busy(rtc);
rtc->type->unlock(rtc);
rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
if (rtc->type->has_irqwakeen)
rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
rtc->type->lock(rtc);
local_irq_enable();
return 0;
}
/* this hardware doesn't support "don't care" alarm fields */
static void tm2bcd(struct rtc_time *tm)
{
tm->tm_sec = bin2bcd(tm->tm_sec);
tm->tm_min = bin2bcd(tm->tm_min);
tm->tm_hour = bin2bcd(tm->tm_hour);
tm->tm_mday = bin2bcd(tm->tm_mday);
tm->tm_mon = bin2bcd(tm->tm_mon + 1);
tm->tm_year = bin2bcd(tm->tm_year - 100);
}
static void bcd2tm(struct rtc_time *tm)
{
tm->tm_sec = bcd2bin(tm->tm_sec);
tm->tm_min = bcd2bin(tm->tm_min);
tm->tm_hour = bcd2bin(tm->tm_hour);
tm->tm_mday = bcd2bin(tm->tm_mday);
tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
/* epoch == 1900 */
tm->tm_year = bcd2bin(tm->tm_year) + 100;
}
static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
{
tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
}
static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
/* we don't report wday/yday/isdst ... */
local_irq_disable();
rtc_wait_not_busy(rtc);
omap_rtc_read_time_raw(rtc, tm);
local_irq_enable();
bcd2tm(tm);
return 0;
}
static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
tm2bcd(tm);
local_irq_disable();
rtc_wait_not_busy(rtc);
rtc->type->unlock(rtc);
rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
rtc->type->lock(rtc);
local_irq_enable();
return 0;
}
static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
u8 interrupts;
local_irq_disable();
rtc_wait_not_busy(rtc);
alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
local_irq_enable();
bcd2tm(&alm->time);
interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
return 0;
}
static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
u8 reg, irqwake_reg = 0;
tm2bcd(&alm->time);
local_irq_disable();
rtc_wait_not_busy(rtc);
rtc->type->unlock(rtc);
rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
if (rtc->type->has_irqwakeen)
irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
if (alm->enabled) {
reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
} else {
reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
}
rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
if (rtc->type->has_irqwakeen)
rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
rtc->type->lock(rtc);
local_irq_enable();
return 0;
}
static struct omap_rtc *omap_rtc_power_off_rtc;
/**
* omap_rtc_power_off_program: Set the pmic power off sequence. The RTC
* generates pmic_pwr_enable control, which can be used to control an external
* PMIC.
*/
int omap_rtc_power_off_program(struct device *dev)
{
struct omap_rtc *rtc = omap_rtc_power_off_rtc;
struct rtc_time tm;
unsigned long now;
int seconds;
u32 val;
rtc->type->unlock(rtc);
/* enable pmic_power_en control */
val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
again:
/* Clear any existing ALARM2 event */
rtc_writel(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM2);
/* set alarm one second from now */
omap_rtc_read_time_raw(rtc, &tm);
seconds = tm.tm_sec;
bcd2tm(&tm);
now = rtc_tm_to_time64(&tm);
rtc_time64_to_tm(now + 1, &tm);
tm2bcd(&tm);
rtc_wait_not_busy(rtc);
rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
/*
* enable ALARM2 interrupt
*
* NOTE: this fails on AM3352 if rtc_write (writeb) is used
*/
val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
/* Retry in case roll over happened before alarm was armed. */
if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
if (!(val & OMAP_RTC_STATUS_ALARM2))
goto again;
}
rtc->type->lock(rtc);
return 0;
}
EXPORT_SYMBOL(omap_rtc_power_off_program);
/*
* omap_rtc_poweroff: RTC-controlled power off
*
* The RTC can be used to control an external PMIC via the pmic_power_en pin,
* which can be configured to transition to OFF on ALARM2 events.
*
* Notes:
* The one-second alarm offset is the shortest offset possible as the alarm
* registers must be set before the next timer update and the offset
* calculation is too heavy for everything to be done within a single access
* period (~15 us).
*
* Called with local interrupts disabled.
*/
static void omap_rtc_power_off(void)
{
struct rtc_device *rtc = omap_rtc_power_off_rtc->rtc;
u32 val;
omap_rtc_power_off_program(rtc->dev.parent);
/* Set PMIC power enable and EXT_WAKEUP in case PB power on is used */
omap_rtc_power_off_rtc->type->unlock(omap_rtc_power_off_rtc);
val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG);
val |= OMAP_RTC_PMIC_POWER_EN_EN | OMAP_RTC_PMIC_EXT_WKUP_POL(0) |
OMAP_RTC_PMIC_EXT_WKUP_EN(0);
rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val);
omap_rtc_power_off_rtc->type->lock(omap_rtc_power_off_rtc);
/*
* Wait for alarm to trigger (within one second) and external PMIC to
* power off the system. Add a 500 ms margin for external latencies
* (e.g. debounce circuits).
*/
mdelay(1500);
}
static const struct rtc_class_ops omap_rtc_ops = {
.read_time = omap_rtc_read_time,
.set_time = omap_rtc_set_time,
.read_alarm = omap_rtc_read_alarm,
.set_alarm = omap_rtc_set_alarm,
.alarm_irq_enable = omap_rtc_alarm_irq_enable,
};
static const struct omap_rtc_device_type omap_rtc_default_type = {
.has_power_up_reset = true,
.lock = default_rtc_lock,
.unlock = default_rtc_unlock,
};
static const struct omap_rtc_device_type omap_rtc_am3352_type = {
.has_32kclk_en = true,
.has_irqwakeen = true,
.has_pmic_mode = true,
.lock = am3352_rtc_lock,
.unlock = am3352_rtc_unlock,
};
static const struct omap_rtc_device_type omap_rtc_da830_type = {
.lock = am3352_rtc_lock,
.unlock = am3352_rtc_unlock,
};
static const struct platform_device_id omap_rtc_id_table[] = {
{
.name = "omap_rtc",
.driver_data = (kernel_ulong_t)&omap_rtc_default_type,
}, {
.name = "am3352-rtc",
.driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
}, {
.name = "da830-rtc",
.driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
static const struct of_device_id omap_rtc_of_match[] = {
{
.compatible = "ti,am3352-rtc",
.data = &omap_rtc_am3352_type,
}, {
.compatible = "ti,da830-rtc",
.data = &omap_rtc_da830_type,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
static const struct pinctrl_pin_desc rtc_pins_desc[] = {
PINCTRL_PIN(0, "ext_wakeup0"),
PINCTRL_PIN(1, "ext_wakeup1"),
PINCTRL_PIN(2, "ext_wakeup2"),
PINCTRL_PIN(3, "ext_wakeup3"),
};
static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
return 0;
}
static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
return NULL;
}
static const struct pinctrl_ops rtc_pinctrl_ops = {
.get_groups_count = rtc_pinctrl_get_groups_count,
.get_group_name = rtc_pinctrl_get_group_name,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinconf_generic_dt_free_map,
};
#define PIN_CONFIG_ACTIVE_HIGH (PIN_CONFIG_END + 1)
static const struct pinconf_generic_params rtc_params[] = {
{"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
};
#endif
static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
unsigned int param = pinconf_to_config_param(*config);
u32 val;
u16 arg = 0;
val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
return -EINVAL;
break;
case PIN_CONFIG_ACTIVE_HIGH:
if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
return -EINVAL;
break;
default:
return -ENOTSUPP;
}
*config = pinconf_to_config_packed(param, arg);
return 0;
}
static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
u32 val;
unsigned int param;
u32 param_val;
int i;
val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
/* active low by default */
val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_INPUT_ENABLE:
if (param_val)
val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
else
val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
break;
case PIN_CONFIG_ACTIVE_HIGH:
val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
break;
default:
dev_err(&rtc->rtc->dev, "Property %u not supported\n",
param);
return -ENOTSUPP;
}
}
rtc->type->unlock(rtc);
rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
rtc->type->lock(rtc);
return 0;
}
static const struct pinconf_ops rtc_pinconf_ops = {
.is_generic = true,
.pin_config_get = rtc_pinconf_get,
.pin_config_set = rtc_pinconf_set,
};
static struct pinctrl_desc rtc_pinctrl_desc = {
.pins = rtc_pins_desc,
.npins = ARRAY_SIZE(rtc_pins_desc),
.pctlops = &rtc_pinctrl_ops,
.confops = &rtc_pinconf_ops,
.custom_params = rtc_params,
.num_custom_params = ARRAY_SIZE(rtc_params),
#ifdef CONFIG_DEBUG_FS
.custom_conf_items = rtc_conf_items,
#endif
.owner = THIS_MODULE,
};
static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
size_t bytes)
{
struct omap_rtc *rtc = priv;
u32 *val = _val;
int i;
for (i = 0; i < bytes / 4; i++)
val[i] = rtc_readl(rtc,
OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
return 0;
}
static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
size_t bytes)
{
struct omap_rtc *rtc = priv;
u32 *val = _val;
int i;
rtc->type->unlock(rtc);
for (i = 0; i < bytes / 4; i++)
rtc_writel(rtc,
OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
rtc->type->lock(rtc);
return 0;
}
static struct nvmem_config omap_rtc_nvmem_config = {
.name = "omap_rtc_scratch",
.word_size = 4,
.stride = 4,
.size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
.reg_read = omap_rtc_scratch_read,
.reg_write = omap_rtc_scratch_write,
};
static int omap_rtc_probe(struct platform_device *pdev)
{
struct omap_rtc *rtc;
u8 reg, mask, new_ctrl;
const struct platform_device_id *id_entry;
const struct of_device_id *of_id;
int ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
if (of_id) {
rtc->type = of_id->data;
rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
of_device_is_system_power_controller(pdev->dev.of_node);
} else {
id_entry = platform_get_device_id(pdev);
rtc->type = (void *)id_entry->driver_data;
}
rtc->irq_timer = platform_get_irq(pdev, 0);
if (rtc->irq_timer < 0)
return rtc->irq_timer;
rtc->irq_alarm = platform_get_irq(pdev, 1);
if (rtc->irq_alarm < 0)
return rtc->irq_alarm;
rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
if (!IS_ERR(rtc->clk))
rtc->has_ext_clk = true;
else
rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
if (!IS_ERR(rtc->clk))
clk_prepare_enable(rtc->clk);
rtc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->base)) {
clk_disable_unprepare(rtc->clk);
return PTR_ERR(rtc->base);
}
platform_set_drvdata(pdev, rtc);
/* Enable the clock/module so that we can access the registers */
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
rtc->type->unlock(rtc);
/*
* disable interrupts
*
* NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
*/
rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
/* enable RTC functional clock */
if (rtc->type->has_32kclk_en) {
reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
rtc_write(rtc, OMAP_RTC_OSC_REG, reg | OMAP_RTC_OSC_32KCLK_EN);
}
/* clear old status */
reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
mask = OMAP_RTC_STATUS_ALARM;
if (rtc->type->has_pmic_mode)
mask |= OMAP_RTC_STATUS_ALARM2;
if (rtc->type->has_power_up_reset) {
mask |= OMAP_RTC_STATUS_POWER_UP;
if (reg & OMAP_RTC_STATUS_POWER_UP)
dev_info(&pdev->dev, "RTC power up reset detected\n");
}
if (reg & mask)
rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
if (reg & OMAP_RTC_CTRL_STOP)
dev_info(&pdev->dev, "already running\n");
/* force to 24 hour mode */
new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
new_ctrl |= OMAP_RTC_CTRL_STOP;
/*
* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
*
* - Device wake-up capability setting should come through chip
* init logic. OMAP1 boards should initialize the "wakeup capable"
* flag in the platform device if the board is wired right for
* being woken up by RTC alarm. For OMAP-L138, this capability
* is built into the SoC by the "Deep Sleep" capability.
*
* - Boards wired so RTC_ON_nOFF is used as the reset signal,
* rather than nPWRON_RESET, should forcibly enable split
* power mode. (Some chip errata report that RTC_CTRL_SPLIT
* is write-only, and always reads as zero...)
*/
if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
dev_info(&pdev->dev, "split power mode\n");
if (reg != new_ctrl)
rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
/*
* If we have the external clock then switch to it so we can keep
* ticking across suspend.
*/
if (rtc->has_ext_clk) {
reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
}
rtc->type->lock(rtc);
device_init_wakeup(&pdev->dev, true);
rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc)) {
ret = PTR_ERR(rtc->rtc);
goto err;
}
rtc->rtc->ops = &omap_rtc_ops;
rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
omap_rtc_nvmem_config.priv = rtc;
/* handle periodic and alarm irqs */
ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
dev_name(&rtc->rtc->dev), rtc);
if (ret)
goto err;
if (rtc->irq_timer != rtc->irq_alarm) {
ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
dev_name(&rtc->rtc->dev), rtc);
if (ret)
goto err;
}
/* Support ext_wakeup pinconf */
rtc_pinctrl_desc.name = dev_name(&pdev->dev);
rtc->pctldev = devm_pinctrl_register(&pdev->dev, &rtc_pinctrl_desc, rtc);
if (IS_ERR(rtc->pctldev)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
ret = PTR_ERR(rtc->pctldev);
goto err;
}
ret = devm_rtc_register_device(rtc->rtc);
if (ret)
goto err;
devm_rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
if (rtc->is_pmic_controller) {
if (!pm_power_off) {
omap_rtc_power_off_rtc = rtc;
pm_power_off = omap_rtc_power_off;
}
}
return 0;
err:
clk_disable_unprepare(rtc->clk);
device_init_wakeup(&pdev->dev, false);
rtc->type->lock(rtc);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return ret;
}
static void omap_rtc_remove(struct platform_device *pdev)
{
struct omap_rtc *rtc = platform_get_drvdata(pdev);
u8 reg;
if (pm_power_off == omap_rtc_power_off &&
omap_rtc_power_off_rtc == rtc) {
pm_power_off = NULL;
omap_rtc_power_off_rtc = NULL;
}
device_init_wakeup(&pdev->dev, 0);
if (!IS_ERR(rtc->clk))
clk_disable_unprepare(rtc->clk);
rtc->type->unlock(rtc);
/* leave rtc running, but disable irqs */
rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
if (rtc->has_ext_clk) {
reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
}
rtc->type->lock(rtc);
/* Disable the clock/module */
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
}
static int __maybe_unused omap_rtc_suspend(struct device *dev)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
rtc->type->unlock(rtc);
/*
* FIXME: the RTC alarm is not currently acting as a wakeup event
* source on some platforms, and in fact this enable() call is just
* saving a flag that's never used...
*/
if (device_may_wakeup(dev))
enable_irq_wake(rtc->irq_alarm);
else
rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
rtc->type->lock(rtc);
rtc->is_suspending = true;
return 0;
}
static int __maybe_unused omap_rtc_resume(struct device *dev)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
rtc->type->unlock(rtc);
if (device_may_wakeup(dev))
disable_irq_wake(rtc->irq_alarm);
else
rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
rtc->type->lock(rtc);
rtc->is_suspending = false;
return 0;
}
static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
{
struct omap_rtc *rtc = dev_get_drvdata(dev);
if (rtc->is_suspending && !rtc->has_ext_clk)
return -EBUSY;
return 0;
}
static const struct dev_pm_ops omap_rtc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
};
static void omap_rtc_shutdown(struct platform_device *pdev)
{
struct omap_rtc *rtc = platform_get_drvdata(pdev);
u8 mask;
/*
* Keep the ALARM interrupt enabled to allow the system to power up on
* alarm events.
*/
rtc->type->unlock(rtc);
mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
rtc->type->lock(rtc);
}
static struct platform_driver omap_rtc_driver = {
.probe = omap_rtc_probe,
.remove_new = omap_rtc_remove,
.shutdown = omap_rtc_shutdown,
.driver = {
.name = "omap_rtc",
.pm = &omap_rtc_pm_ops,
.of_match_table = omap_rtc_of_match,
},
.id_table = omap_rtc_id_table,
};
module_platform_driver(omap_rtc_driver);
MODULE_AUTHOR("George G. Davis (and others)");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-omap.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
* I2C RTC / Alarm chip
*
* Copyright (C) 2014, Arnaud EBALARD <[email protected]>
*
* Detailed datasheet of the chip is available here:
*
* https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
*
* This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
*
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/interrupt.h>
#define DRV_NAME "rtc-ab-b5ze-s3"
/* Control section */
#define ABB5ZES3_REG_CTRL1 0x00 /* Control 1 register */
#define ABB5ZES3_REG_CTRL1_CIE BIT(0) /* Pulse interrupt enable */
#define ABB5ZES3_REG_CTRL1_AIE BIT(1) /* Alarm interrupt enable */
#define ABB5ZES3_REG_CTRL1_SIE BIT(2) /* Second interrupt enable */
#define ABB5ZES3_REG_CTRL1_PM BIT(3) /* 24h/12h mode */
#define ABB5ZES3_REG_CTRL1_SR BIT(4) /* Software reset */
#define ABB5ZES3_REG_CTRL1_STOP BIT(5) /* RTC circuit enable */
#define ABB5ZES3_REG_CTRL1_CAP BIT(7)
#define ABB5ZES3_REG_CTRL2 0x01 /* Control 2 register */
#define ABB5ZES3_REG_CTRL2_CTBIE BIT(0) /* Countdown timer B int. enable */
#define ABB5ZES3_REG_CTRL2_CTAIE BIT(1) /* Countdown timer A int. enable */
#define ABB5ZES3_REG_CTRL2_WTAIE BIT(2) /* Watchdog timer A int. enable */
#define ABB5ZES3_REG_CTRL2_AF BIT(3) /* Alarm interrupt status */
#define ABB5ZES3_REG_CTRL2_SF BIT(4) /* Second interrupt status */
#define ABB5ZES3_REG_CTRL2_CTBF BIT(5) /* Countdown timer B int. status */
#define ABB5ZES3_REG_CTRL2_CTAF BIT(6) /* Countdown timer A int. status */
#define ABB5ZES3_REG_CTRL2_WTAF BIT(7) /* Watchdog timer A int. status */
#define ABB5ZES3_REG_CTRL3 0x02 /* Control 3 register */
#define ABB5ZES3_REG_CTRL3_PM2 BIT(7) /* Power Management bit 2 */
#define ABB5ZES3_REG_CTRL3_PM1 BIT(6) /* Power Management bit 1 */
#define ABB5ZES3_REG_CTRL3_PM0 BIT(5) /* Power Management bit 0 */
#define ABB5ZES3_REG_CTRL3_BSF BIT(3) /* Battery switchover int. status */
#define ABB5ZES3_REG_CTRL3_BLF BIT(2) /* Battery low int. status */
#define ABB5ZES3_REG_CTRL3_BSIE BIT(1) /* Battery switchover int. enable */
#define ABB5ZES3_REG_CTRL3_BLIE BIT(0) /* Battery low int. enable */
#define ABB5ZES3_CTRL_SEC_LEN 3
/* RTC section */
#define ABB5ZES3_REG_RTC_SC 0x03 /* RTC Seconds register */
#define ABB5ZES3_REG_RTC_SC_OSC BIT(7) /* Clock integrity status */
#define ABB5ZES3_REG_RTC_MN 0x04 /* RTC Minutes register */
#define ABB5ZES3_REG_RTC_HR 0x05 /* RTC Hours register */
#define ABB5ZES3_REG_RTC_HR_PM BIT(5) /* RTC Hours PM bit */
#define ABB5ZES3_REG_RTC_DT 0x06 /* RTC Date register */
#define ABB5ZES3_REG_RTC_DW 0x07 /* RTC Day of the week register */
#define ABB5ZES3_REG_RTC_MO 0x08 /* RTC Month register */
#define ABB5ZES3_REG_RTC_YR 0x09 /* RTC Year register */
#define ABB5ZES3_RTC_SEC_LEN 7
/* Alarm section (enable bits are all active low) */
#define ABB5ZES3_REG_ALRM_MN 0x0A /* Alarm - minute register */
#define ABB5ZES3_REG_ALRM_MN_AE BIT(7) /* Minute enable */
#define ABB5ZES3_REG_ALRM_HR 0x0B /* Alarm - hours register */
#define ABB5ZES3_REG_ALRM_HR_AE BIT(7) /* Hour enable */
#define ABB5ZES3_REG_ALRM_DT 0x0C /* Alarm - date register */
#define ABB5ZES3_REG_ALRM_DT_AE BIT(7) /* Date (day of the month) enable */
#define ABB5ZES3_REG_ALRM_DW 0x0D /* Alarm - day of the week reg. */
#define ABB5ZES3_REG_ALRM_DW_AE BIT(7) /* Day of the week enable */
#define ABB5ZES3_ALRM_SEC_LEN 4
/* Frequency offset section */
#define ABB5ZES3_REG_FREQ_OF 0x0E /* Frequency offset register */
#define ABB5ZES3_REG_FREQ_OF_MODE 0x0E /* Offset mode: 2 hours / minute */
/* CLOCKOUT section */
#define ABB5ZES3_REG_TIM_CLK 0x0F /* Timer & Clockout register */
#define ABB5ZES3_REG_TIM_CLK_TAM BIT(7) /* Permanent/pulsed timer A/int. 2 */
#define ABB5ZES3_REG_TIM_CLK_TBM BIT(6) /* Permanent/pulsed timer B */
#define ABB5ZES3_REG_TIM_CLK_COF2 BIT(5) /* Clkout Freq bit 2 */
#define ABB5ZES3_REG_TIM_CLK_COF1 BIT(4) /* Clkout Freq bit 1 */
#define ABB5ZES3_REG_TIM_CLK_COF0 BIT(3) /* Clkout Freq bit 0 */
#define ABB5ZES3_REG_TIM_CLK_TAC1 BIT(2) /* Timer A: - 01 : countdown */
#define ABB5ZES3_REG_TIM_CLK_TAC0 BIT(1) /* - 10 : timer */
#define ABB5ZES3_REG_TIM_CLK_TBC BIT(0) /* Timer B enable */
/* Timer A Section */
#define ABB5ZES3_REG_TIMA_CLK 0x10 /* Timer A clock register */
#define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2) /* Freq bit 2 */
#define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1) /* Freq bit 1 */
#define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0) /* Freq bit 0 */
#define ABB5ZES3_REG_TIMA 0x11 /* Timer A register */
#define ABB5ZES3_TIMA_SEC_LEN 2
/* Timer B Section */
#define ABB5ZES3_REG_TIMB_CLK 0x12 /* Timer B clock register */
#define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
#define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
#define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
#define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
#define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
#define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
#define ABB5ZES3_REG_TIMB 0x13 /* Timer B register */
#define ABB5ZES3_TIMB_SEC_LEN 2
#define ABB5ZES3_MEM_MAP_LEN 0x14
struct abb5zes3_rtc_data {
struct rtc_device *rtc;
struct regmap *regmap;
int irq;
bool battery_low;
bool timer_alarm; /* current alarm is via timer A */
};
/*
* Try and match register bits w/ fixed null values to see whether we
* are dealing with an ABB5ZES3.
*/
static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
{
u8 regs[ABB5ZES3_MEM_MAP_LEN];
static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
0x80, 0xc0, 0xc0, 0xf8,
0xe0, 0x00, 0x00, 0x40,
0x40, 0x78, 0x00, 0x00,
0xf8, 0x00, 0x88, 0x00 };
int ret, i;
ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
if (ret)
return ret;
for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
if (regs[i] & mask[i]) /* check if bits are cleared */
return -ENODEV;
}
return 0;
}
/* Clear alarm status bit. */
static int _abb5zes3_rtc_clear_alarm(struct device *dev)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
ABB5ZES3_REG_CTRL2_AF, 0);
if (ret)
dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
return ret;
}
/* Enable or disable alarm (i.e. alarm interrupt generation) */
static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
ABB5ZES3_REG_CTRL1_AIE,
enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
if (ret)
dev_err(dev, "%s: writing alarm INT failed (%d)\n",
__func__, ret);
return ret;
}
/* Enable or disable timer (watchdog timer A interrupt generation) */
static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
ABB5ZES3_REG_CTRL2_WTAIE,
enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
if (ret)
dev_err(dev, "%s: writing timer INT failed (%d)\n",
__func__, ret);
return ret;
}
/*
* Note: we only read, so regmap inner lock protection is sufficient, i.e.
* we do not need driver's main lock protection.
*/
static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
int ret = 0;
/*
* As we need to read CTRL1 register anyway to access 24/12h
* mode bit, we do a single bulk read of both control and RTC
* sections (they are consecutive). This also ease indexing
* of register values after bulk read.
*/
ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
sizeof(regs));
if (ret) {
dev_err(dev, "%s: reading RTC time failed (%d)\n",
__func__, ret);
return ret;
}
/* If clock integrity is not guaranteed, do not return a time value */
if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC)
return -ENODATA;
tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
tm->tm_hour += 12;
} else { /* 24hr mode */
tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
}
tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
tm->tm_mon = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
return ret;
}
static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
int ret;
regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
regs + ABB5ZES3_REG_RTC_SC,
ABB5ZES3_RTC_SEC_LEN);
return ret;
}
/*
* Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
* given number of seconds.
*/
static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
{
*taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
*timer_a = secs;
}
/*
* Return current number of seconds in Timer A. As we only use
* timer A with a 1Hz freq, this is what we expect to have.
*/
static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
{
if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
return -EINVAL;
*secs = timer_a;
return 0;
}
/*
* Read alarm currently configured via a watchdog timer using timer A. This
* is done by reading current RTC time and adding remaining timer time.
*/
static int _abb5zes3_rtc_read_timer(struct device *dev,
struct rtc_wkalrm *alarm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
unsigned long rtc_secs;
unsigned int reg;
u8 timer_secs;
int ret;
/*
* Instead of doing two separate calls, because they are consecutive,
* we grab both clockout register and Timer A section. The latter is
* used to decide if timer A is enabled (as a watchdog timer).
*/
ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
ABB5ZES3_TIMA_SEC_LEN + 1);
if (ret) {
dev_err(dev, "%s: reading Timer A section failed (%d)\n",
__func__, ret);
return ret;
}
/* get current time ... */
ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
if (ret)
return ret;
/* ... convert to seconds ... */
rtc_secs = rtc_tm_to_time64(&rtc_tm);
/* ... add remaining timer A time ... */
ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
if (ret)
return ret;
/* ... and convert back. */
rtc_time64_to_tm(rtc_secs + timer_secs, alarm_tm);
ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, ®);
if (ret) {
dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
__func__, ret);
return ret;
}
alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
return 0;
}
/* Read alarm currently configured via a RTC alarm registers. */
static int _abb5zes3_rtc_read_alarm(struct device *dev,
struct rtc_wkalrm *alarm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
unsigned long rtc_secs, alarm_secs;
u8 regs[ABB5ZES3_ALRM_SEC_LEN];
unsigned int reg;
int ret;
ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
ABB5ZES3_ALRM_SEC_LEN);
if (ret) {
dev_err(dev, "%s: reading alarm section failed (%d)\n",
__func__, ret);
return ret;
}
alarm_tm->tm_sec = 0;
alarm_tm->tm_min = bcd2bin(regs[0] & 0x7f);
alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
alarm_tm->tm_wday = -1;
/*
* The alarm section does not store year/month. We use the ones in rtc
* section as a basis and increment month and then year if needed to get
* alarm after current time.
*/
ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
if (ret)
return ret;
alarm_tm->tm_year = rtc_tm.tm_year;
alarm_tm->tm_mon = rtc_tm.tm_mon;
rtc_secs = rtc_tm_to_time64(&rtc_tm);
alarm_secs = rtc_tm_to_time64(alarm_tm);
if (alarm_secs < rtc_secs) {
if (alarm_tm->tm_mon == 11) {
alarm_tm->tm_mon = 0;
alarm_tm->tm_year += 1;
} else {
alarm_tm->tm_mon += 1;
}
}
ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, ®);
if (ret) {
dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
__func__, ret);
return ret;
}
alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
return 0;
}
/*
* As the Alarm mechanism supported by the chip is only accurate to the
* minute, we use the watchdog timer mechanism provided by timer A
* (up to 256 seconds w/ a second accuracy) for low alarm values (below
* 4 minutes). Otherwise, we use the common alarm mechanism provided
* by the chip. In order for that to work, we keep track of currently
* configured timer type via 'timer_alarm' flag in our private data
* structure.
*/
static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
int ret;
if (data->timer_alarm)
ret = _abb5zes3_rtc_read_timer(dev, alarm);
else
ret = _abb5zes3_rtc_read_alarm(dev, alarm);
return ret;
}
/*
* Set alarm using chip alarm mechanism. It is only accurate to the
* minute (not the second). The function expects alarm interrupt to
* be disabled.
*/
static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
struct rtc_time *alarm_tm = &alarm->time;
u8 regs[ABB5ZES3_ALRM_SEC_LEN];
struct rtc_time rtc_tm;
int ret, enable = 1;
if (!alarm->enabled) {
enable = 0;
} else {
unsigned long rtc_secs, alarm_secs;
/*
* Chip only support alarms up to one month in the future. Let's
* return an error if we get something after that limit.
* Comparison is done by incrementing rtc_tm month field by one
* and checking alarm value is still below.
*/
ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
if (ret)
return ret;
if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
rtc_tm.tm_mon = 0;
rtc_tm.tm_year += 1;
} else {
rtc_tm.tm_mon += 1;
}
rtc_secs = rtc_tm_to_time64(&rtc_tm);
alarm_secs = rtc_tm_to_time64(alarm_tm);
if (alarm_secs > rtc_secs) {
dev_err(dev, "%s: alarm maximum is one month in the future (%d)\n",
__func__, ret);
return -EINVAL;
}
}
/*
* Program all alarm registers but DW one. For each register, setting
* MSB to 0 enables associated alarm.
*/
regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
ABB5ZES3_ALRM_SEC_LEN);
if (ret < 0) {
dev_err(dev, "%s: writing ALARM section failed (%d)\n",
__func__, ret);
return ret;
}
/* Record currently configured alarm is not a timer */
data->timer_alarm = 0;
/* Enable or disable alarm interrupt generation */
return _abb5zes3_rtc_update_alarm(dev, enable);
}
/*
* Set alarm using timer watchdog (via timer A) mechanism. The function expects
* timer A interrupt to be disabled.
*/
static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
u8 secs)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABB5ZES3_TIMA_SEC_LEN];
u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
int ret = 0;
/* Program given number of seconds to Timer A registers */
sec_to_timer_a(secs, ®s[0], ®s[1]);
ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
ABB5ZES3_TIMA_SEC_LEN);
if (ret < 0) {
dev_err(dev, "%s: writing timer section failed\n", __func__);
return ret;
}
/* Configure Timer A as a watchdog timer */
ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
mask, ABB5ZES3_REG_TIM_CLK_TAC1);
if (ret)
dev_err(dev, "%s: failed to update timer\n", __func__);
/* Record currently configured alarm is a timer */
data->timer_alarm = 1;
/* Enable or disable timer interrupt generation */
return _abb5zes3_rtc_update_timer(dev, alarm->enabled);
}
/*
* The chip has an alarm which is only accurate to the minute. In order to
* handle alarms below that limit, we use the watchdog timer function of
* timer A. More precisely, the timer method is used for alarms below 240
* seconds.
*/
static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
struct rtc_time *alarm_tm = &alarm->time;
unsigned long rtc_secs, alarm_secs;
struct rtc_time rtc_tm;
int ret;
ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
if (ret)
return ret;
rtc_secs = rtc_tm_to_time64(&rtc_tm);
alarm_secs = rtc_tm_to_time64(alarm_tm);
/* Let's first disable both the alarm and the timer interrupts */
ret = _abb5zes3_rtc_update_alarm(dev, false);
if (ret < 0) {
dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
ret);
return ret;
}
ret = _abb5zes3_rtc_update_timer(dev, false);
if (ret < 0) {
dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
ret);
return ret;
}
data->timer_alarm = 0;
/*
* Let's now configure the alarm; if we are expected to ring in
* more than 240s, then we setup an alarm. Otherwise, a timer.
*/
if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
ret = _abb5zes3_rtc_set_timer(dev, alarm,
alarm_secs - rtc_secs);
else
ret = _abb5zes3_rtc_set_alarm(dev, alarm);
if (ret)
dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
ret);
return ret;
}
/* Enable or disable battery low irq generation */
static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
bool enable)
{
return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
ABB5ZES3_REG_CTRL3_BLIE,
enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
}
/*
* Check current RTC status and enable/disable what needs to be. Return 0 if
* everything went ok and a negative value upon error.
*/
static int abb5zes3_rtc_check_setup(struct device *dev)
{
struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
struct regmap *regmap = data->regmap;
unsigned int reg;
int ret;
u8 mask;
/*
* By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
* is disabled here to prevent polluting the interrupt line and
* uselessly triggering the IRQ handler we install for alarm and battery
* low events. Note: this is done before clearing int. status below
* in this function.
* We also disable all timers and set timer interrupt to permanent (not
* pulsed).
*/
mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
ABB5ZES3_REG_TIM_CLK_COF0 |
ABB5ZES3_REG_TIM_CLK_COF1 |
ABB5ZES3_REG_TIM_CLK_COF2);
if (ret < 0) {
dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
__func__, ret);
return ret;
}
/*
* Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
* individually by clearing/setting MSB of each associated register. So,
* we set all alarm enable bits to disable current alarm setting.
*/
mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
if (ret < 0) {
dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
__func__, ret);
return ret;
}
/* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
if (ret < 0) {
dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
__func__, ret);
return ret;
}
/*
* Set Control 2 register (timer int. disabled, alarm status cleared).
* WTAF is read-only and cleared automatically by reading the register.
*/
mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
ABB5ZES3_REG_CTRL2_CTAF);
ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
if (ret < 0) {
dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
__func__, ret);
return ret;
}
/*
* Enable battery low detection function and battery switchover function
* (standard mode). Disable associated interrupts. Clear battery
* switchover flag but not battery low flag. The latter is checked
* later below.
*/
mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 |
ABB5ZES3_REG_CTRL3_PM2 | ABB5ZES3_REG_CTRL3_BLIE |
ABB5ZES3_REG_CTRL3_BSIE | ABB5ZES3_REG_CTRL3_BSF);
ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
if (ret < 0) {
dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
__func__, ret);
return ret;
}
/* Check oscillator integrity flag */
ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, ®);
if (ret < 0) {
dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
__func__, ret);
return ret;
}
if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
dev_err(dev, "clock integrity not guaranteed. Osc. has stopped or has been interrupted.\n");
dev_err(dev, "change battery (if not already done) and then set time to reset osc. failure flag.\n");
}
/*
* Check battery low flag at startup: this allows reporting battery
* is low at startup when IRQ line is not connected. Note: we record
* current status to avoid reenabling this interrupt later in probe
* function if battery is low.
*/
ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, ®);
if (ret < 0) {
dev_err(dev, "%s: unable to read battery low flag (%d)\n",
__func__, ret);
return ret;
}
data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
if (data->battery_low) {
dev_err(dev, "RTC battery is low; please, consider changing it!\n");
ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
if (ret)
dev_err(dev, "%s: disabling battery low interrupt generation failed (%d)\n",
__func__, ret);
}
return ret;
}
static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
unsigned int enable)
{
struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
int ret = 0;
if (rtc_data->irq) {
if (rtc_data->timer_alarm)
ret = _abb5zes3_rtc_update_timer(dev, enable);
else
ret = _abb5zes3_rtc_update_alarm(dev, enable);
}
return ret;
}
static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
{
struct i2c_client *client = data;
struct device *dev = &client->dev;
struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
struct rtc_device *rtc = rtc_data->rtc;
u8 regs[ABB5ZES3_CTRL_SEC_LEN];
int ret, handled = IRQ_NONE;
ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
ABB5ZES3_CTRL_SEC_LEN);
if (ret) {
dev_err(dev, "%s: unable to read control section (%d)!\n",
__func__, ret);
return handled;
}
/*
* Check battery low detection flag and disable battery low interrupt
* generation if flag is set (interrupt can only be cleared when
* battery is replaced).
*/
if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
dev_err(dev, "RTC battery is low; please change it!\n");
_abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
handled = IRQ_HANDLED;
}
/* Check alarm flag */
if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
dev_dbg(dev, "RTC alarm!\n");
rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
/* Acknowledge and disable the alarm */
_abb5zes3_rtc_clear_alarm(dev);
_abb5zes3_rtc_update_alarm(dev, 0);
handled = IRQ_HANDLED;
}
/* Check watchdog Timer A flag */
if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
dev_dbg(dev, "RTC timer!\n");
rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
/*
* Acknowledge and disable the alarm. Note: WTAF
* flag had been cleared when reading CTRL2
*/
_abb5zes3_rtc_update_timer(dev, 0);
rtc_data->timer_alarm = 0;
handled = IRQ_HANDLED;
}
return handled;
}
static const struct rtc_class_ops rtc_ops = {
.read_time = _abb5zes3_rtc_read_time,
.set_time = abb5zes3_rtc_set_time,
.read_alarm = abb5zes3_rtc_read_alarm,
.set_alarm = abb5zes3_rtc_set_alarm,
.alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
};
static const struct regmap_config abb5zes3_rtc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
};
static int abb5zes3_probe(struct i2c_client *client)
{
struct abb5zes3_rtc_data *data = NULL;
struct device *dev = &client->dev;
struct regmap *regmap;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_I2C_BLOCK))
return -ENODEV;
regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(dev, "%s: regmap allocation failed: %d\n",
__func__, ret);
return ret;
}
ret = abb5zes3_i2c_validate_chip(regmap);
if (ret)
return ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->regmap = regmap;
dev_set_drvdata(dev, data);
ret = abb5zes3_rtc_check_setup(dev);
if (ret)
return ret;
data->rtc = devm_rtc_allocate_device(dev);
ret = PTR_ERR_OR_ZERO(data->rtc);
if (ret) {
dev_err(dev, "%s: unable to allocate RTC device (%d)\n",
__func__, ret);
return ret;
}
if (client->irq > 0) {
ret = devm_request_threaded_irq(dev, client->irq, NULL,
_abb5zes3_rtc_interrupt,
IRQF_SHARED | IRQF_ONESHOT,
DRV_NAME, client);
if (!ret) {
device_init_wakeup(dev, true);
data->irq = client->irq;
dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
client->irq);
} else {
dev_err(dev, "%s: irq %d unavailable (%d)\n",
__func__, client->irq, ret);
goto err;
}
}
data->rtc->ops = &rtc_ops;
data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
data->rtc->range_max = RTC_TIMESTAMP_END_2099;
/* Enable battery low detection interrupt if battery not already low */
if (!data->battery_low && data->irq) {
ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
if (ret) {
dev_err(dev, "%s: enabling battery low interrupt generation failed (%d)\n",
__func__, ret);
goto err;
}
}
ret = devm_rtc_register_device(data->rtc);
err:
if (ret && data->irq)
device_init_wakeup(dev, false);
return ret;
}
#ifdef CONFIG_PM_SLEEP
static int abb5zes3_rtc_suspend(struct device *dev)
{
struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
return enable_irq_wake(rtc_data->irq);
return 0;
}
static int abb5zes3_rtc_resume(struct device *dev)
{
struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
return disable_irq_wake(rtc_data->irq);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
abb5zes3_rtc_resume);
#ifdef CONFIG_OF
static const struct of_device_id abb5zes3_dt_match[] = {
{ .compatible = "abracon,abb5zes3" },
{ },
};
MODULE_DEVICE_TABLE(of, abb5zes3_dt_match);
#endif
static const struct i2c_device_id abb5zes3_id[] = {
{ "abb5zes3", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
static struct i2c_driver abb5zes3_driver = {
.driver = {
.name = DRV_NAME,
.pm = &abb5zes3_rtc_pm_ops,
.of_match_table = of_match_ptr(abb5zes3_dt_match),
},
.probe = abb5zes3_probe,
.id_table = abb5zes3_id,
};
module_i2c_driver(abb5zes3_driver);
MODULE_AUTHOR("Arnaud EBALARD <[email protected]>");
MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-ab-b5ze-s3.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RTC subsystem, base class
*
* Copyright (C) 2005 Tower Technologies
* Author: Alessandro Zummo <[email protected]>
*
* class skeleton from drivers/hwmon/hwmon.c
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/of.h>
#include <linux/rtc.h>
#include <linux/kdev_t.h>
#include <linux/idr.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include "rtc-core.h"
static DEFINE_IDA(rtc_ida);
struct class *rtc_class;
static void rtc_device_release(struct device *dev)
{
struct rtc_device *rtc = to_rtc_device(dev);
struct timerqueue_head *head = &rtc->timerqueue;
struct timerqueue_node *node;
mutex_lock(&rtc->ops_lock);
while ((node = timerqueue_getnext(head)))
timerqueue_del(head, node);
mutex_unlock(&rtc->ops_lock);
cancel_work_sync(&rtc->irqwork);
ida_free(&rtc_ida, rtc->id);
mutex_destroy(&rtc->ops_lock);
kfree(rtc);
}
#ifdef CONFIG_RTC_HCTOSYS_DEVICE
/* Result of the last RTC to system clock attempt. */
int rtc_hctosys_ret = -ENODEV;
/* IMPORTANT: the RTC only stores whole seconds. It is arbitrary
* whether it stores the most close value or the value with partial
* seconds truncated. However, it is important that we use it to store
* the truncated value. This is because otherwise it is necessary,
* in an rtc sync function, to read both xtime.tv_sec and
* xtime.tv_nsec. On some processors (i.e. ARM), an atomic read
* of >32bits is not possible. So storing the most close value would
* slow down the sync API. So here we have the truncated value and
* the best guess is to add 0.5s.
*/
static void rtc_hctosys(struct rtc_device *rtc)
{
int err;
struct rtc_time tm;
struct timespec64 tv64 = {
.tv_nsec = NSEC_PER_SEC >> 1,
};
err = rtc_read_time(rtc, &tm);
if (err) {
dev_err(rtc->dev.parent,
"hctosys: unable to read the hardware clock\n");
goto err_read;
}
tv64.tv_sec = rtc_tm_to_time64(&tm);
#if BITS_PER_LONG == 32
if (tv64.tv_sec > INT_MAX) {
err = -ERANGE;
goto err_read;
}
#endif
err = do_settimeofday64(&tv64);
dev_info(rtc->dev.parent, "setting system clock to %ptR UTC (%lld)\n",
&tm, (long long)tv64.tv_sec);
err_read:
rtc_hctosys_ret = err;
}
#endif
#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_RTC_HCTOSYS_DEVICE)
/*
* On suspend(), measure the delta between one RTC and the
* system's wall clock; restore it on resume().
*/
static struct timespec64 old_rtc, old_system, old_delta;
static int rtc_suspend(struct device *dev)
{
struct rtc_device *rtc = to_rtc_device(dev);
struct rtc_time tm;
struct timespec64 delta, delta_delta;
int err;
if (timekeeping_rtc_skipsuspend())
return 0;
if (strcmp(dev_name(&rtc->dev), CONFIG_RTC_HCTOSYS_DEVICE) != 0)
return 0;
/* snapshot the current RTC and system time at suspend*/
err = rtc_read_time(rtc, &tm);
if (err < 0) {
pr_debug("%s: fail to read rtc time\n", dev_name(&rtc->dev));
return 0;
}
ktime_get_real_ts64(&old_system);
old_rtc.tv_sec = rtc_tm_to_time64(&tm);
/*
* To avoid drift caused by repeated suspend/resumes,
* which each can add ~1 second drift error,
* try to compensate so the difference in system time
* and rtc time stays close to constant.
*/
delta = timespec64_sub(old_system, old_rtc);
delta_delta = timespec64_sub(delta, old_delta);
if (delta_delta.tv_sec < -2 || delta_delta.tv_sec >= 2) {
/*
* if delta_delta is too large, assume time correction
* has occurred and set old_delta to the current delta.
*/
old_delta = delta;
} else {
/* Otherwise try to adjust old_system to compensate */
old_system = timespec64_sub(old_system, delta_delta);
}
return 0;
}
static int rtc_resume(struct device *dev)
{
struct rtc_device *rtc = to_rtc_device(dev);
struct rtc_time tm;
struct timespec64 new_system, new_rtc;
struct timespec64 sleep_time;
int err;
if (timekeeping_rtc_skipresume())
return 0;
rtc_hctosys_ret = -ENODEV;
if (strcmp(dev_name(&rtc->dev), CONFIG_RTC_HCTOSYS_DEVICE) != 0)
return 0;
/* snapshot the current rtc and system time at resume */
ktime_get_real_ts64(&new_system);
err = rtc_read_time(rtc, &tm);
if (err < 0) {
pr_debug("%s: fail to read rtc time\n", dev_name(&rtc->dev));
return 0;
}
new_rtc.tv_sec = rtc_tm_to_time64(&tm);
new_rtc.tv_nsec = 0;
if (new_rtc.tv_sec < old_rtc.tv_sec) {
pr_debug("%s: time travel!\n", dev_name(&rtc->dev));
return 0;
}
/* calculate the RTC time delta (sleep time)*/
sleep_time = timespec64_sub(new_rtc, old_rtc);
/*
* Since these RTC suspend/resume handlers are not called
* at the very end of suspend or the start of resume,
* some run-time may pass on either sides of the sleep time
* so subtract kernel run-time between rtc_suspend to rtc_resume
* to keep things accurate.
*/
sleep_time = timespec64_sub(sleep_time,
timespec64_sub(new_system, old_system));
if (sleep_time.tv_sec >= 0)
timekeeping_inject_sleeptime64(&sleep_time);
rtc_hctosys_ret = 0;
return 0;
}
static SIMPLE_DEV_PM_OPS(rtc_class_dev_pm_ops, rtc_suspend, rtc_resume);
#define RTC_CLASS_DEV_PM_OPS (&rtc_class_dev_pm_ops)
#else
#define RTC_CLASS_DEV_PM_OPS NULL
#endif
/* Ensure the caller will set the id before releasing the device */
static struct rtc_device *rtc_allocate_device(void)
{
struct rtc_device *rtc;
rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return NULL;
device_initialize(&rtc->dev);
/*
* Drivers can revise this default after allocating the device.
* The default is what most RTCs do: Increment seconds exactly one
* second after the write happened. This adds a default transport
* time of 5ms which is at least halfways close to reality.
*/
rtc->set_offset_nsec = NSEC_PER_SEC + 5 * NSEC_PER_MSEC;
rtc->irq_freq = 1;
rtc->max_user_freq = 64;
rtc->dev.class = rtc_class;
rtc->dev.groups = rtc_get_dev_attribute_groups();
rtc->dev.release = rtc_device_release;
mutex_init(&rtc->ops_lock);
spin_lock_init(&rtc->irq_lock);
init_waitqueue_head(&rtc->irq_queue);
/* Init timerqueue */
timerqueue_init_head(&rtc->timerqueue);
INIT_WORK(&rtc->irqwork, rtc_timer_do_work);
/* Init aie timer */
rtc_timer_init(&rtc->aie_timer, rtc_aie_update_irq, rtc);
/* Init uie timer */
rtc_timer_init(&rtc->uie_rtctimer, rtc_uie_update_irq, rtc);
/* Init pie timer */
hrtimer_init(&rtc->pie_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
rtc->pie_timer.function = rtc_pie_update_irq;
rtc->pie_enabled = 0;
set_bit(RTC_FEATURE_ALARM, rtc->features);
set_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->features);
return rtc;
}
static int rtc_device_get_id(struct device *dev)
{
int of_id = -1, id = -1;
if (dev->of_node)
of_id = of_alias_get_id(dev->of_node, "rtc");
else if (dev->parent && dev->parent->of_node)
of_id = of_alias_get_id(dev->parent->of_node, "rtc");
if (of_id >= 0) {
id = ida_simple_get(&rtc_ida, of_id, of_id + 1, GFP_KERNEL);
if (id < 0)
dev_warn(dev, "/aliases ID %d not available\n", of_id);
}
if (id < 0)
id = ida_alloc(&rtc_ida, GFP_KERNEL);
return id;
}
static void rtc_device_get_offset(struct rtc_device *rtc)
{
time64_t range_secs;
u32 start_year;
int ret;
/*
* If RTC driver did not implement the range of RTC hardware device,
* then we can not expand the RTC range by adding or subtracting one
* offset.
*/
if (rtc->range_min == rtc->range_max)
return;
ret = device_property_read_u32(rtc->dev.parent, "start-year",
&start_year);
if (!ret) {
rtc->start_secs = mktime64(start_year, 1, 1, 0, 0, 0);
rtc->set_start_time = true;
}
/*
* If user did not implement the start time for RTC driver, then no
* need to expand the RTC range.
*/
if (!rtc->set_start_time)
return;
range_secs = rtc->range_max - rtc->range_min + 1;
/*
* If the start_secs is larger than the maximum seconds (rtc->range_max)
* supported by RTC hardware or the maximum seconds of new expanded
* range (start_secs + rtc->range_max - rtc->range_min) is less than
* rtc->range_min, which means the minimum seconds (rtc->range_min) of
* RTC hardware will be mapped to start_secs by adding one offset, so
* the offset seconds calculation formula should be:
* rtc->offset_secs = rtc->start_secs - rtc->range_min;
*
* If the start_secs is larger than the minimum seconds (rtc->range_min)
* supported by RTC hardware, then there is one region is overlapped
* between the original RTC hardware range and the new expanded range,
* and this overlapped region do not need to be mapped into the new
* expanded range due to it is valid for RTC device. So the minimum
* seconds of RTC hardware (rtc->range_min) should be mapped to
* rtc->range_max + 1, then the offset seconds formula should be:
* rtc->offset_secs = rtc->range_max - rtc->range_min + 1;
*
* If the start_secs is less than the minimum seconds (rtc->range_min),
* which is similar to case 2. So the start_secs should be mapped to
* start_secs + rtc->range_max - rtc->range_min + 1, then the
* offset seconds formula should be:
* rtc->offset_secs = -(rtc->range_max - rtc->range_min + 1);
*
* Otherwise the offset seconds should be 0.
*/
if (rtc->start_secs > rtc->range_max ||
rtc->start_secs + range_secs - 1 < rtc->range_min)
rtc->offset_secs = rtc->start_secs - rtc->range_min;
else if (rtc->start_secs > rtc->range_min)
rtc->offset_secs = range_secs;
else if (rtc->start_secs < rtc->range_min)
rtc->offset_secs = -range_secs;
else
rtc->offset_secs = 0;
}
static void devm_rtc_unregister_device(void *data)
{
struct rtc_device *rtc = data;
mutex_lock(&rtc->ops_lock);
/*
* Remove innards of this RTC, then disable it, before
* letting any rtc_class_open() users access it again
*/
rtc_proc_del_device(rtc);
if (!test_bit(RTC_NO_CDEV, &rtc->flags))
cdev_device_del(&rtc->char_dev, &rtc->dev);
rtc->ops = NULL;
mutex_unlock(&rtc->ops_lock);
}
static void devm_rtc_release_device(void *res)
{
struct rtc_device *rtc = res;
put_device(&rtc->dev);
}
struct rtc_device *devm_rtc_allocate_device(struct device *dev)
{
struct rtc_device *rtc;
int id, err;
id = rtc_device_get_id(dev);
if (id < 0)
return ERR_PTR(id);
rtc = rtc_allocate_device();
if (!rtc) {
ida_free(&rtc_ida, id);
return ERR_PTR(-ENOMEM);
}
rtc->id = id;
rtc->dev.parent = dev;
err = devm_add_action_or_reset(dev, devm_rtc_release_device, rtc);
if (err)
return ERR_PTR(err);
err = dev_set_name(&rtc->dev, "rtc%d", id);
if (err)
return ERR_PTR(err);
return rtc;
}
EXPORT_SYMBOL_GPL(devm_rtc_allocate_device);
int __devm_rtc_register_device(struct module *owner, struct rtc_device *rtc)
{
struct rtc_wkalrm alrm;
int err;
if (!rtc->ops) {
dev_dbg(&rtc->dev, "no ops set\n");
return -EINVAL;
}
if (!rtc->ops->set_alarm)
clear_bit(RTC_FEATURE_ALARM, rtc->features);
if (rtc->ops->set_offset)
set_bit(RTC_FEATURE_CORRECTION, rtc->features);
rtc->owner = owner;
rtc_device_get_offset(rtc);
/* Check to see if there is an ALARM already set in hw */
err = __rtc_read_alarm(rtc, &alrm);
if (!err && !rtc_valid_tm(&alrm.time))
rtc_initialize_alarm(rtc, &alrm);
rtc_dev_prepare(rtc);
err = cdev_device_add(&rtc->char_dev, &rtc->dev);
if (err) {
set_bit(RTC_NO_CDEV, &rtc->flags);
dev_warn(rtc->dev.parent, "failed to add char device %d:%d\n",
MAJOR(rtc->dev.devt), rtc->id);
} else {
dev_dbg(rtc->dev.parent, "char device (%d:%d)\n",
MAJOR(rtc->dev.devt), rtc->id);
}
rtc_proc_add_device(rtc);
dev_info(rtc->dev.parent, "registered as %s\n",
dev_name(&rtc->dev));
#ifdef CONFIG_RTC_HCTOSYS_DEVICE
if (!strcmp(dev_name(&rtc->dev), CONFIG_RTC_HCTOSYS_DEVICE))
rtc_hctosys(rtc);
#endif
return devm_add_action_or_reset(rtc->dev.parent,
devm_rtc_unregister_device, rtc);
}
EXPORT_SYMBOL_GPL(__devm_rtc_register_device);
/**
* devm_rtc_device_register - resource managed rtc_device_register()
* @dev: the device to register
* @name: the name of the device (unused)
* @ops: the rtc operations structure
* @owner: the module owner
*
* @return a struct rtc on success, or an ERR_PTR on error
*
* Managed rtc_device_register(). The rtc_device returned from this function
* are automatically freed on driver detach.
* This function is deprecated, use devm_rtc_allocate_device and
* rtc_register_device instead
*/
struct rtc_device *devm_rtc_device_register(struct device *dev,
const char *name,
const struct rtc_class_ops *ops,
struct module *owner)
{
struct rtc_device *rtc;
int err;
rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(rtc))
return rtc;
rtc->ops = ops;
err = __devm_rtc_register_device(owner, rtc);
if (err)
return ERR_PTR(err);
return rtc;
}
EXPORT_SYMBOL_GPL(devm_rtc_device_register);
static int __init rtc_init(void)
{
rtc_class = class_create("rtc");
if (IS_ERR(rtc_class)) {
pr_err("couldn't create class\n");
return PTR_ERR(rtc_class);
}
rtc_class->pm = RTC_CLASS_DEV_PM_OPS;
rtc_dev_init();
return 0;
}
subsys_initcall(rtc_init);
| linux-master | drivers/rtc/class.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An rtc driver for the Dallas DS1511
*
* Copyright (C) 2006 Atsushi Nemoto <[email protected]>
* Copyright (C) 2007 Andrew Sharp <[email protected]>
*
* Real time clock driver for the Dallas 1511 chip, which also
* contains a watchdog timer. There is a tiny amount of code that
* platform code could use to mess with the watchdog device a little
* bit, but not a full watchdog driver.
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>
enum ds1511reg {
DS1511_SEC = 0x0,
DS1511_MIN = 0x1,
DS1511_HOUR = 0x2,
DS1511_DOW = 0x3,
DS1511_DOM = 0x4,
DS1511_MONTH = 0x5,
DS1511_YEAR = 0x6,
DS1511_CENTURY = 0x7,
DS1511_AM1_SEC = 0x8,
DS1511_AM2_MIN = 0x9,
DS1511_AM3_HOUR = 0xa,
DS1511_AM4_DATE = 0xb,
DS1511_WD_MSEC = 0xc,
DS1511_WD_SEC = 0xd,
DS1511_CONTROL_A = 0xe,
DS1511_CONTROL_B = 0xf,
DS1511_RAMADDR_LSB = 0x10,
DS1511_RAMDATA = 0x13
};
#define DS1511_BLF1 0x80
#define DS1511_BLF2 0x40
#define DS1511_PRS 0x20
#define DS1511_PAB 0x10
#define DS1511_TDF 0x08
#define DS1511_KSF 0x04
#define DS1511_WDF 0x02
#define DS1511_IRQF 0x01
#define DS1511_TE 0x80
#define DS1511_CS 0x40
#define DS1511_BME 0x20
#define DS1511_TPE 0x10
#define DS1511_TIE 0x08
#define DS1511_KIE 0x04
#define DS1511_WDE 0x02
#define DS1511_WDS 0x01
#define DS1511_RAM_MAX 0x100
#define RTC_CMD DS1511_CONTROL_B
#define RTC_CMD1 DS1511_CONTROL_A
#define RTC_ALARM_SEC DS1511_AM1_SEC
#define RTC_ALARM_MIN DS1511_AM2_MIN
#define RTC_ALARM_HOUR DS1511_AM3_HOUR
#define RTC_ALARM_DATE DS1511_AM4_DATE
#define RTC_SEC DS1511_SEC
#define RTC_MIN DS1511_MIN
#define RTC_HOUR DS1511_HOUR
#define RTC_DOW DS1511_DOW
#define RTC_DOM DS1511_DOM
#define RTC_MON DS1511_MONTH
#define RTC_YEAR DS1511_YEAR
#define RTC_CENTURY DS1511_CENTURY
#define RTC_TIE DS1511_TIE
#define RTC_TE DS1511_TE
struct rtc_plat_data {
struct rtc_device *rtc;
void __iomem *ioaddr; /* virtual base address */
int irq;
unsigned int irqen;
int alrm_sec;
int alrm_min;
int alrm_hour;
int alrm_mday;
spinlock_t lock;
};
static DEFINE_SPINLOCK(ds1511_lock);
static __iomem char *ds1511_base;
static u32 reg_spacing = 1;
static noinline void
rtc_write(uint8_t val, uint32_t reg)
{
writeb(val, ds1511_base + (reg * reg_spacing));
}
static noinline uint8_t
rtc_read(enum ds1511reg reg)
{
return readb(ds1511_base + (reg * reg_spacing));
}
static inline void
rtc_disable_update(void)
{
rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD);
}
static void
rtc_enable_update(void)
{
rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD);
}
/*
* #define DS1511_WDOG_RESET_SUPPORT
*
* Uncomment this if you want to use these routines in
* some platform code.
*/
#ifdef DS1511_WDOG_RESET_SUPPORT
/*
* just enough code to set the watchdog timer so that it
* will reboot the system
*/
void
ds1511_wdog_set(unsigned long deciseconds)
{
/*
* the wdog timer can take 99.99 seconds
*/
deciseconds %= 10000;
/*
* set the wdog values in the wdog registers
*/
rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC);
rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC);
/*
* set wdog enable and wdog 'steering' bit to issue a reset
*/
rtc_write(rtc_read(RTC_CMD) | DS1511_WDE | DS1511_WDS, RTC_CMD);
}
void
ds1511_wdog_disable(void)
{
/*
* clear wdog enable and wdog 'steering' bits
*/
rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD);
/*
* clear the wdog counter
*/
rtc_write(0, DS1511_WD_MSEC);
rtc_write(0, DS1511_WD_SEC);
}
#endif
/*
* set the rtc chip's idea of the time.
* stupidly, some callers call with year unmolested;
* and some call with year = year - 1900. thanks.
*/
static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
{
u8 mon, day, dow, hrs, min, sec, yrs, cen;
unsigned long flags;
/*
* won't have to change this for a while
*/
if (rtc_tm->tm_year < 1900)
rtc_tm->tm_year += 1900;
if (rtc_tm->tm_year < 1970)
return -EINVAL;
yrs = rtc_tm->tm_year % 100;
cen = rtc_tm->tm_year / 100;
mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */
day = rtc_tm->tm_mday;
dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
hrs = rtc_tm->tm_hour;
min = rtc_tm->tm_min;
sec = rtc_tm->tm_sec;
if ((mon > 12) || (day == 0))
return -EINVAL;
if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year))
return -EINVAL;
if ((hrs >= 24) || (min >= 60) || (sec >= 60))
return -EINVAL;
/*
* each register is a different number of valid bits
*/
sec = bin2bcd(sec) & 0x7f;
min = bin2bcd(min) & 0x7f;
hrs = bin2bcd(hrs) & 0x3f;
day = bin2bcd(day) & 0x3f;
mon = bin2bcd(mon) & 0x1f;
yrs = bin2bcd(yrs) & 0xff;
cen = bin2bcd(cen) & 0xff;
spin_lock_irqsave(&ds1511_lock, flags);
rtc_disable_update();
rtc_write(cen, RTC_CENTURY);
rtc_write(yrs, RTC_YEAR);
rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON);
rtc_write(day, RTC_DOM);
rtc_write(hrs, RTC_HOUR);
rtc_write(min, RTC_MIN);
rtc_write(sec, RTC_SEC);
rtc_write(dow, RTC_DOW);
rtc_enable_update();
spin_unlock_irqrestore(&ds1511_lock, flags);
return 0;
}
static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
{
unsigned int century;
unsigned long flags;
spin_lock_irqsave(&ds1511_lock, flags);
rtc_disable_update();
rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f;
rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f;
rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f;
rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f;
rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7;
rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f;
rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f;
century = rtc_read(RTC_CENTURY);
rtc_enable_update();
spin_unlock_irqrestore(&ds1511_lock, flags);
rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
century = bcd2bin(century) * 100;
/*
* Account for differences between how the RTC uses the values
* and how they are defined in a struct rtc_time;
*/
century += rtc_tm->tm_year;
rtc_tm->tm_year = century - 1900;
rtc_tm->tm_mon--;
return 0;
}
/*
* write the alarm register settings
*
* we only have the use to interrupt every second, otherwise
* known as the update interrupt, or the interrupt if the whole
* date/hours/mins/secs matches. the ds1511 has many more
* permutations, but the kernel doesn't.
*/
static void
ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
{
unsigned long flags;
spin_lock_irqsave(&pdata->lock, flags);
rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_mday) & 0x3f,
RTC_ALARM_DATE);
rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_hour) & 0x3f,
RTC_ALARM_HOUR);
rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_min) & 0x7f,
RTC_ALARM_MIN);
rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_sec) & 0x7f,
RTC_ALARM_SEC);
rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD);
rtc_read(RTC_CMD1); /* clear interrupts */
spin_unlock_irqrestore(&pdata->lock, flags);
}
static int
ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
pdata->alrm_mday = alrm->time.tm_mday;
pdata->alrm_hour = alrm->time.tm_hour;
pdata->alrm_min = alrm->time.tm_min;
pdata->alrm_sec = alrm->time.tm_sec;
if (alrm->enabled)
pdata->irqen |= RTC_AF;
ds1511_rtc_update_alarm(pdata);
return 0;
}
static int
ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
return 0;
}
static irqreturn_t
ds1511_interrupt(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
unsigned long events = 0;
spin_lock(&pdata->lock);
/*
* read and clear interrupt
*/
if (rtc_read(RTC_CMD1) & DS1511_IRQF) {
events = RTC_IRQF;
if (rtc_read(RTC_ALARM_SEC) & 0x80)
events |= RTC_UF;
else
events |= RTC_AF;
rtc_update_irq(pdata->rtc, 1, events);
}
spin_unlock(&pdata->lock);
return events ? IRQ_HANDLED : IRQ_NONE;
}
static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
if (enabled)
pdata->irqen |= RTC_AF;
else
pdata->irqen &= ~RTC_AF;
ds1511_rtc_update_alarm(pdata);
return 0;
}
static const struct rtc_class_ops ds1511_rtc_ops = {
.read_time = ds1511_rtc_read_time,
.set_time = ds1511_rtc_set_time,
.read_alarm = ds1511_rtc_read_alarm,
.set_alarm = ds1511_rtc_set_alarm,
.alarm_irq_enable = ds1511_rtc_alarm_irq_enable,
};
static int ds1511_nvram_read(void *priv, unsigned int pos, void *buf,
size_t size)
{
int i;
rtc_write(pos, DS1511_RAMADDR_LSB);
for (i = 0; i < size; i++)
*(char *)buf++ = rtc_read(DS1511_RAMDATA);
return 0;
}
static int ds1511_nvram_write(void *priv, unsigned int pos, void *buf,
size_t size)
{
int i;
rtc_write(pos, DS1511_RAMADDR_LSB);
for (i = 0; i < size; i++)
rtc_write(*(char *)buf++, DS1511_RAMDATA);
return 0;
}
static int ds1511_rtc_probe(struct platform_device *pdev)
{
struct rtc_plat_data *pdata;
int ret = 0;
struct nvmem_config ds1511_nvmem_cfg = {
.name = "ds1511_nvram",
.word_size = 1,
.stride = 1,
.size = DS1511_RAM_MAX,
.reg_read = ds1511_nvram_read,
.reg_write = ds1511_nvram_write,
.priv = &pdev->dev,
};
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
ds1511_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ds1511_base))
return PTR_ERR(ds1511_base);
pdata->ioaddr = ds1511_base;
pdata->irq = platform_get_irq(pdev, 0);
/*
* turn on the clock and the crystal, etc.
*/
rtc_write(DS1511_BME, RTC_CMD);
rtc_write(0, RTC_CMD1);
/*
* clear the wdog counter
*/
rtc_write(0, DS1511_WD_MSEC);
rtc_write(0, DS1511_WD_SEC);
/*
* start the clock
*/
rtc_enable_update();
/*
* check for a dying bat-tree
*/
if (rtc_read(RTC_CMD1) & DS1511_BLF1)
dev_warn(&pdev->dev, "voltage-low detected.\n");
spin_lock_init(&pdata->lock);
platform_set_drvdata(pdev, pdata);
pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pdata->rtc))
return PTR_ERR(pdata->rtc);
pdata->rtc->ops = &ds1511_rtc_ops;
ret = devm_rtc_register_device(pdata->rtc);
if (ret)
return ret;
devm_rtc_nvmem_register(pdata->rtc, &ds1511_nvmem_cfg);
/*
* if the platform has an interrupt in mind for this device,
* then by all means, set it
*/
if (pdata->irq > 0) {
rtc_read(RTC_CMD1);
if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt,
IRQF_SHARED, pdev->name, pdev) < 0) {
dev_warn(&pdev->dev, "interrupt not available.\n");
pdata->irq = 0;
}
}
return 0;
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:ds1511");
static struct platform_driver ds1511_rtc_driver = {
.probe = ds1511_rtc_probe,
.driver = {
.name = "ds1511",
},
};
module_platform_driver(ds1511_rtc_driver);
MODULE_AUTHOR("Andrew Sharp <[email protected]>");
MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-ds1511.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RTC driver for the Micro Crystal RV3028
*
* Copyright (C) 2019 Micro Crystal SA
*
* Alexandre Belloni <[email protected]>
*
*/
#include <linux/clk-provider.h>
#include <linux/bcd.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#define RV3028_SEC 0x00
#define RV3028_MIN 0x01
#define RV3028_HOUR 0x02
#define RV3028_WDAY 0x03
#define RV3028_DAY 0x04
#define RV3028_MONTH 0x05
#define RV3028_YEAR 0x06
#define RV3028_ALARM_MIN 0x07
#define RV3028_ALARM_HOUR 0x08
#define RV3028_ALARM_DAY 0x09
#define RV3028_STATUS 0x0E
#define RV3028_CTRL1 0x0F
#define RV3028_CTRL2 0x10
#define RV3028_EVT_CTRL 0x13
#define RV3028_TS_COUNT 0x14
#define RV3028_TS_SEC 0x15
#define RV3028_RAM1 0x1F
#define RV3028_EEPROM_ADDR 0x25
#define RV3028_EEPROM_DATA 0x26
#define RV3028_EEPROM_CMD 0x27
#define RV3028_CLKOUT 0x35
#define RV3028_OFFSET 0x36
#define RV3028_BACKUP 0x37
#define RV3028_STATUS_PORF BIT(0)
#define RV3028_STATUS_EVF BIT(1)
#define RV3028_STATUS_AF BIT(2)
#define RV3028_STATUS_TF BIT(3)
#define RV3028_STATUS_UF BIT(4)
#define RV3028_STATUS_BSF BIT(5)
#define RV3028_STATUS_CLKF BIT(6)
#define RV3028_STATUS_EEBUSY BIT(7)
#define RV3028_CLKOUT_FD_MASK GENMASK(2, 0)
#define RV3028_CLKOUT_PORIE BIT(3)
#define RV3028_CLKOUT_CLKSY BIT(6)
#define RV3028_CLKOUT_CLKOE BIT(7)
#define RV3028_CTRL1_EERD BIT(3)
#define RV3028_CTRL1_WADA BIT(5)
#define RV3028_CTRL2_RESET BIT(0)
#define RV3028_CTRL2_12_24 BIT(1)
#define RV3028_CTRL2_EIE BIT(2)
#define RV3028_CTRL2_AIE BIT(3)
#define RV3028_CTRL2_TIE BIT(4)
#define RV3028_CTRL2_UIE BIT(5)
#define RV3028_CTRL2_TSE BIT(7)
#define RV3028_EVT_CTRL_TSR BIT(2)
#define RV3028_EEPROM_CMD_UPDATE 0x11
#define RV3028_EEPROM_CMD_WRITE 0x21
#define RV3028_EEPROM_CMD_READ 0x22
#define RV3028_EEBUSY_POLL 10000
#define RV3028_EEBUSY_TIMEOUT 100000
#define RV3028_BACKUP_TCE BIT(5)
#define RV3028_BACKUP_TCR_MASK GENMASK(1,0)
#define RV3028_BACKUP_BSM GENMASK(3,2)
#define RV3028_BACKUP_BSM_DSM 0x1
#define RV3028_BACKUP_BSM_LSM 0x3
#define OFFSET_STEP_PPT 953674
enum rv3028_type {
rv_3028,
};
struct rv3028_data {
struct regmap *regmap;
struct rtc_device *rtc;
enum rv3028_type type;
#ifdef CONFIG_COMMON_CLK
struct clk_hw clkout_hw;
#endif
};
static u16 rv3028_trickle_resistors[] = {3000, 5000, 9000, 15000};
static ssize_t timestamp0_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
regmap_update_bits(rv3028->regmap, RV3028_EVT_CTRL, RV3028_EVT_CTRL_TSR,
RV3028_EVT_CTRL_TSR);
return count;
};
static ssize_t timestamp0_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
struct rtc_time tm;
int ret, count;
u8 date[6];
ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
if (ret)
return ret;
if (!count)
return 0;
ret = regmap_bulk_read(rv3028->regmap, RV3028_TS_SEC, date,
sizeof(date));
if (ret)
return ret;
tm.tm_sec = bcd2bin(date[0]);
tm.tm_min = bcd2bin(date[1]);
tm.tm_hour = bcd2bin(date[2]);
tm.tm_mday = bcd2bin(date[3]);
tm.tm_mon = bcd2bin(date[4]) - 1;
tm.tm_year = bcd2bin(date[5]) + 100;
ret = rtc_valid_tm(&tm);
if (ret)
return ret;
return sprintf(buf, "%llu\n",
(unsigned long long)rtc_tm_to_time64(&tm));
};
static DEVICE_ATTR_RW(timestamp0);
static ssize_t timestamp0_count_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
int ret, count;
ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
if (ret)
return ret;
return sprintf(buf, "%u\n", count);
};
static DEVICE_ATTR_RO(timestamp0_count);
static struct attribute *rv3028_attrs[] = {
&dev_attr_timestamp0.attr,
&dev_attr_timestamp0_count.attr,
NULL
};
static const struct attribute_group rv3028_attr_group = {
.attrs = rv3028_attrs,
};
static int rv3028_exit_eerd(struct rv3028_data *rv3028, u32 eerd)
{
if (eerd)
return 0;
return regmap_update_bits(rv3028->regmap, RV3028_CTRL1, RV3028_CTRL1_EERD, 0);
}
static int rv3028_enter_eerd(struct rv3028_data *rv3028, u32 *eerd)
{
u32 ctrl1, status;
int ret;
ret = regmap_read(rv3028->regmap, RV3028_CTRL1, &ctrl1);
if (ret)
return ret;
*eerd = ctrl1 & RV3028_CTRL1_EERD;
if (*eerd)
return 0;
ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
RV3028_CTRL1_EERD, RV3028_CTRL1_EERD);
if (ret)
return ret;
ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
!(status & RV3028_STATUS_EEBUSY),
RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
if (ret) {
rv3028_exit_eerd(rv3028, *eerd);
return ret;
}
return 0;
}
static int rv3028_update_eeprom(struct rv3028_data *rv3028, u32 eerd)
{
u32 status;
int ret;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
if (ret)
goto exit_eerd;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, RV3028_EEPROM_CMD_UPDATE);
if (ret)
goto exit_eerd;
usleep_range(63000, RV3028_EEBUSY_TIMEOUT);
ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
!(status & RV3028_STATUS_EEBUSY),
RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
exit_eerd:
rv3028_exit_eerd(rv3028, eerd);
return ret;
}
static int rv3028_update_cfg(struct rv3028_data *rv3028, unsigned int reg,
unsigned int mask, unsigned int val)
{
u32 eerd;
int ret;
ret = rv3028_enter_eerd(rv3028, &eerd);
if (ret)
return ret;
ret = regmap_update_bits(rv3028->regmap, reg, mask, val);
if (ret) {
rv3028_exit_eerd(rv3028, eerd);
return ret;
}
return rv3028_update_eeprom(rv3028, eerd);
}
static irqreturn_t rv3028_handle_irq(int irq, void *dev_id)
{
struct rv3028_data *rv3028 = dev_id;
unsigned long events = 0;
u32 status = 0, ctrl = 0;
if (regmap_read(rv3028->regmap, RV3028_STATUS, &status) < 0 ||
status == 0) {
return IRQ_NONE;
}
status &= ~RV3028_STATUS_PORF;
if (status & RV3028_STATUS_TF) {
status |= RV3028_STATUS_TF;
ctrl |= RV3028_CTRL2_TIE;
events |= RTC_PF;
}
if (status & RV3028_STATUS_AF) {
status |= RV3028_STATUS_AF;
ctrl |= RV3028_CTRL2_AIE;
events |= RTC_AF;
}
if (status & RV3028_STATUS_UF) {
status |= RV3028_STATUS_UF;
ctrl |= RV3028_CTRL2_UIE;
events |= RTC_UF;
}
if (events) {
rtc_update_irq(rv3028->rtc, 1, events);
regmap_update_bits(rv3028->regmap, RV3028_STATUS, status, 0);
regmap_update_bits(rv3028->regmap, RV3028_CTRL2, ctrl, 0);
}
if (status & RV3028_STATUS_EVF) {
sysfs_notify(&rv3028->rtc->dev.kobj, NULL,
dev_attr_timestamp0.attr.name);
dev_warn(&rv3028->rtc->dev, "event detected");
}
return IRQ_HANDLED;
}
static int rv3028_get_time(struct device *dev, struct rtc_time *tm)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
u8 date[7];
int ret, status;
ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
if (ret < 0)
return ret;
if (status & RV3028_STATUS_PORF)
return -EINVAL;
ret = regmap_bulk_read(rv3028->regmap, RV3028_SEC, date, sizeof(date));
if (ret)
return ret;
tm->tm_sec = bcd2bin(date[RV3028_SEC] & 0x7f);
tm->tm_min = bcd2bin(date[RV3028_MIN] & 0x7f);
tm->tm_hour = bcd2bin(date[RV3028_HOUR] & 0x3f);
tm->tm_wday = date[RV3028_WDAY] & 0x7f;
tm->tm_mday = bcd2bin(date[RV3028_DAY] & 0x3f);
tm->tm_mon = bcd2bin(date[RV3028_MONTH] & 0x1f) - 1;
tm->tm_year = bcd2bin(date[RV3028_YEAR]) + 100;
return 0;
}
static int rv3028_set_time(struct device *dev, struct rtc_time *tm)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
u8 date[7];
int ret;
date[RV3028_SEC] = bin2bcd(tm->tm_sec);
date[RV3028_MIN] = bin2bcd(tm->tm_min);
date[RV3028_HOUR] = bin2bcd(tm->tm_hour);
date[RV3028_WDAY] = tm->tm_wday;
date[RV3028_DAY] = bin2bcd(tm->tm_mday);
date[RV3028_MONTH] = bin2bcd(tm->tm_mon + 1);
date[RV3028_YEAR] = bin2bcd(tm->tm_year - 100);
/*
* Writing to the Seconds register has the same effect as setting RESET
* bit to 1
*/
ret = regmap_bulk_write(rv3028->regmap, RV3028_SEC, date,
sizeof(date));
if (ret)
return ret;
ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
RV3028_STATUS_PORF, 0);
return ret;
}
static int rv3028_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
u8 alarmvals[3];
int status, ctrl, ret;
ret = regmap_bulk_read(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
sizeof(alarmvals));
if (ret)
return ret;
ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
if (ret < 0)
return ret;
ret = regmap_read(rv3028->regmap, RV3028_CTRL2, &ctrl);
if (ret < 0)
return ret;
alrm->time.tm_sec = 0;
alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f);
alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
alrm->enabled = !!(ctrl & RV3028_CTRL2_AIE);
alrm->pending = (status & RV3028_STATUS_AF) && alrm->enabled;
return 0;
}
static int rv3028_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
u8 alarmvals[3];
u8 ctrl = 0;
int ret;
/* The alarm has no seconds, round up to nearest minute */
if (alrm->time.tm_sec) {
time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
alarm_time += 60 - alrm->time.tm_sec;
rtc_time64_to_tm(alarm_time, &alrm->time);
}
ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
RV3028_CTRL2_AIE | RV3028_CTRL2_UIE, 0);
if (ret)
return ret;
alarmvals[0] = bin2bcd(alrm->time.tm_min);
alarmvals[1] = bin2bcd(alrm->time.tm_hour);
alarmvals[2] = bin2bcd(alrm->time.tm_mday);
ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
RV3028_STATUS_AF, 0);
if (ret)
return ret;
ret = regmap_bulk_write(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
sizeof(alarmvals));
if (ret)
return ret;
if (alrm->enabled) {
if (rv3028->rtc->uie_rtctimer.enabled)
ctrl |= RV3028_CTRL2_UIE;
if (rv3028->rtc->aie_timer.enabled)
ctrl |= RV3028_CTRL2_AIE;
}
ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
return ret;
}
static int rv3028_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
int ctrl = 0, ret;
if (enabled) {
if (rv3028->rtc->uie_rtctimer.enabled)
ctrl |= RV3028_CTRL2_UIE;
if (rv3028->rtc->aie_timer.enabled)
ctrl |= RV3028_CTRL2_AIE;
}
ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
RV3028_STATUS_AF | RV3028_STATUS_UF, 0);
if (ret)
return ret;
ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
if (ret)
return ret;
return 0;
}
static int rv3028_read_offset(struct device *dev, long *offset)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
int ret, value, steps;
ret = regmap_read(rv3028->regmap, RV3028_OFFSET, &value);
if (ret < 0)
return ret;
steps = sign_extend32(value << 1, 8);
ret = regmap_read(rv3028->regmap, RV3028_BACKUP, &value);
if (ret < 0)
return ret;
steps += value >> 7;
*offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
return 0;
}
static int rv3028_set_offset(struct device *dev, long offset)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
u32 eerd;
int ret;
offset = clamp(offset, -244141L, 243187L) * 1000;
offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
ret = rv3028_enter_eerd(rv3028, &eerd);
if (ret)
return ret;
ret = regmap_write(rv3028->regmap, RV3028_OFFSET, offset >> 1);
if (ret < 0)
goto exit_eerd;
ret = regmap_update_bits(rv3028->regmap, RV3028_BACKUP, BIT(7),
offset << 7);
if (ret < 0)
goto exit_eerd;
return rv3028_update_eeprom(rv3028, eerd);
exit_eerd:
rv3028_exit_eerd(rv3028, eerd);
return ret;
}
static int rv3028_param_get(struct device *dev, struct rtc_param *param)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
int ret;
u32 value;
switch(param->param) {
case RTC_PARAM_BACKUP_SWITCH_MODE:
ret = regmap_read(rv3028->regmap, RV3028_BACKUP, &value);
if (ret < 0)
return ret;
value = FIELD_GET(RV3028_BACKUP_BSM, value);
switch(value) {
case RV3028_BACKUP_BSM_DSM:
param->uvalue = RTC_BSM_DIRECT;
break;
case RV3028_BACKUP_BSM_LSM:
param->uvalue = RTC_BSM_LEVEL;
break;
default:
param->uvalue = RTC_BSM_DISABLED;
}
break;
default:
return -EINVAL;
}
return 0;
}
static int rv3028_param_set(struct device *dev, struct rtc_param *param)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
u8 mode;
switch(param->param) {
case RTC_PARAM_BACKUP_SWITCH_MODE:
switch (param->uvalue) {
case RTC_BSM_DISABLED:
mode = 0;
break;
case RTC_BSM_DIRECT:
mode = RV3028_BACKUP_BSM_DSM;
break;
case RTC_BSM_LEVEL:
mode = RV3028_BACKUP_BSM_LSM;
break;
default:
return -EINVAL;
}
return rv3028_update_cfg(rv3028, RV3028_BACKUP, RV3028_BACKUP_BSM,
FIELD_PREP(RV3028_BACKUP_BSM, mode));
default:
return -EINVAL;
}
return 0;
}
static int rv3028_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
struct rv3028_data *rv3028 = dev_get_drvdata(dev);
int status, ret = 0;
switch (cmd) {
case RTC_VL_READ:
ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
if (ret < 0)
return ret;
status = status & RV3028_STATUS_PORF ? RTC_VL_DATA_INVALID : 0;
return put_user(status, (unsigned int __user *)arg);
default:
return -ENOIOCTLCMD;
}
}
static int rv3028_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return regmap_bulk_write(priv, RV3028_RAM1 + offset, val, bytes);
}
static int rv3028_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return regmap_bulk_read(priv, RV3028_RAM1 + offset, val, bytes);
}
static int rv3028_eeprom_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct rv3028_data *rv3028 = priv;
u32 status, eerd;
int i, ret;
u8 *buf = val;
ret = rv3028_enter_eerd(rv3028, &eerd);
if (ret)
return ret;
for (i = 0; i < bytes; i++) {
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_ADDR, offset + i);
if (ret)
goto restore_eerd;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_DATA, buf[i]);
if (ret)
goto restore_eerd;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
if (ret)
goto restore_eerd;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD,
RV3028_EEPROM_CMD_WRITE);
if (ret)
goto restore_eerd;
usleep_range(RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
!(status & RV3028_STATUS_EEBUSY),
RV3028_EEBUSY_POLL,
RV3028_EEBUSY_TIMEOUT);
if (ret)
goto restore_eerd;
}
restore_eerd:
rv3028_exit_eerd(rv3028, eerd);
return ret;
}
static int rv3028_eeprom_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct rv3028_data *rv3028 = priv;
u32 status, eerd, data;
int i, ret;
u8 *buf = val;
ret = rv3028_enter_eerd(rv3028, &eerd);
if (ret)
return ret;
for (i = 0; i < bytes; i++) {
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_ADDR, offset + i);
if (ret)
goto restore_eerd;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
if (ret)
goto restore_eerd;
ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD,
RV3028_EEPROM_CMD_READ);
if (ret)
goto restore_eerd;
ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
!(status & RV3028_STATUS_EEBUSY),
RV3028_EEBUSY_POLL,
RV3028_EEBUSY_TIMEOUT);
if (ret)
goto restore_eerd;
ret = regmap_read(rv3028->regmap, RV3028_EEPROM_DATA, &data);
if (ret)
goto restore_eerd;
buf[i] = data;
}
restore_eerd:
rv3028_exit_eerd(rv3028, eerd);
return ret;
}
#ifdef CONFIG_COMMON_CLK
#define clkout_hw_to_rv3028(hw) container_of(hw, struct rv3028_data, clkout_hw)
static int clkout_rates[] = {
32768,
8192,
1024,
64,
32,
1,
};
static unsigned long rv3028_clkout_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
int clkout, ret;
struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout);
if (ret < 0)
return 0;
clkout &= RV3028_CLKOUT_FD_MASK;
return clkout_rates[clkout];
}
static long rv3028_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
int i;
for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
if (clkout_rates[i] <= rate)
return clkout_rates[i];
return 0;
}
static int rv3028_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
int i, ret;
u32 enabled;
struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &enabled);
if (ret < 0)
return ret;
ret = regmap_write(rv3028->regmap, RV3028_CLKOUT, 0x0);
if (ret < 0)
return ret;
enabled &= RV3028_CLKOUT_CLKOE;
for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
if (clkout_rates[i] == rate)
return rv3028_update_cfg(rv3028, RV3028_CLKOUT, 0xff,
RV3028_CLKOUT_CLKSY | enabled | i);
return -EINVAL;
}
static int rv3028_clkout_prepare(struct clk_hw *hw)
{
struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
return regmap_write(rv3028->regmap, RV3028_CLKOUT,
RV3028_CLKOUT_CLKSY | RV3028_CLKOUT_CLKOE);
}
static void rv3028_clkout_unprepare(struct clk_hw *hw)
{
struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
regmap_write(rv3028->regmap, RV3028_CLKOUT, 0x0);
regmap_update_bits(rv3028->regmap, RV3028_STATUS,
RV3028_STATUS_CLKF, 0);
}
static int rv3028_clkout_is_prepared(struct clk_hw *hw)
{
int clkout, ret;
struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout);
if (ret < 0)
return ret;
return !!(clkout & RV3028_CLKOUT_CLKOE);
}
static const struct clk_ops rv3028_clkout_ops = {
.prepare = rv3028_clkout_prepare,
.unprepare = rv3028_clkout_unprepare,
.is_prepared = rv3028_clkout_is_prepared,
.recalc_rate = rv3028_clkout_recalc_rate,
.round_rate = rv3028_clkout_round_rate,
.set_rate = rv3028_clkout_set_rate,
};
static int rv3028_clkout_register_clk(struct rv3028_data *rv3028,
struct i2c_client *client)
{
int ret;
struct clk *clk;
struct clk_init_data init;
struct device_node *node = client->dev.of_node;
ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
RV3028_STATUS_CLKF, 0);
if (ret < 0)
return ret;
init.name = "rv3028-clkout";
init.ops = &rv3028_clkout_ops;
init.flags = 0;
init.parent_names = NULL;
init.num_parents = 0;
rv3028->clkout_hw.init = &init;
/* optional override of the clockname */
of_property_read_string(node, "clock-output-names", &init.name);
/* register the clock */
clk = devm_clk_register(&client->dev, &rv3028->clkout_hw);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return 0;
}
#endif
static const struct rtc_class_ops rv3028_rtc_ops = {
.read_time = rv3028_get_time,
.set_time = rv3028_set_time,
.read_alarm = rv3028_get_alarm,
.set_alarm = rv3028_set_alarm,
.alarm_irq_enable = rv3028_alarm_irq_enable,
.read_offset = rv3028_read_offset,
.set_offset = rv3028_set_offset,
.ioctl = rv3028_ioctl,
.param_get = rv3028_param_get,
.param_set = rv3028_param_set,
};
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x37,
};
static u8 rv3028_set_trickle_charger(struct rv3028_data *rv3028,
struct i2c_client *client)
{
int ret, val_old, val;
u32 ohms, chargeable;
ret = regmap_read(rv3028->regmap, RV3028_BACKUP, &val_old);
if (ret < 0)
return ret;
/* mask out only trickle charger bits */
val_old = val_old & (RV3028_BACKUP_TCE | RV3028_BACKUP_TCR_MASK);
val = val_old;
/* setup trickle charger */
if (!device_property_read_u32(&client->dev, "trickle-resistor-ohms",
&ohms)) {
int i;
for (i = 0; i < ARRAY_SIZE(rv3028_trickle_resistors); i++)
if (ohms == rv3028_trickle_resistors[i])
break;
if (i < ARRAY_SIZE(rv3028_trickle_resistors)) {
/* enable trickle charger and its resistor */
val = RV3028_BACKUP_TCE | i;
} else {
dev_warn(&client->dev, "invalid trickle resistor value\n");
}
}
if (!device_property_read_u32(&client->dev, "aux-voltage-chargeable",
&chargeable)) {
switch (chargeable) {
case 0:
val &= ~RV3028_BACKUP_TCE;
break;
case 1:
val |= RV3028_BACKUP_TCE;
break;
default:
dev_warn(&client->dev,
"unsupported aux-voltage-chargeable value\n");
break;
}
}
/* only update EEPROM if changes are necessary */
if (val_old != val) {
ret = rv3028_update_cfg(rv3028, RV3028_BACKUP, RV3028_BACKUP_TCE |
RV3028_BACKUP_TCR_MASK, val);
if (ret)
return ret;
}
return ret;
}
static int rv3028_probe(struct i2c_client *client)
{
struct rv3028_data *rv3028;
int ret, status;
struct nvmem_config nvmem_cfg = {
.name = "rv3028_nvram",
.word_size = 1,
.stride = 1,
.size = 2,
.type = NVMEM_TYPE_BATTERY_BACKED,
.reg_read = rv3028_nvram_read,
.reg_write = rv3028_nvram_write,
};
struct nvmem_config eeprom_cfg = {
.name = "rv3028_eeprom",
.word_size = 1,
.stride = 1,
.size = 43,
.type = NVMEM_TYPE_EEPROM,
.reg_read = rv3028_eeprom_read,
.reg_write = rv3028_eeprom_write,
};
rv3028 = devm_kzalloc(&client->dev, sizeof(struct rv3028_data),
GFP_KERNEL);
if (!rv3028)
return -ENOMEM;
rv3028->regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(rv3028->regmap))
return PTR_ERR(rv3028->regmap);
i2c_set_clientdata(client, rv3028);
ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
if (ret < 0)
return ret;
if (status & RV3028_STATUS_AF)
dev_warn(&client->dev, "An alarm may have been missed.\n");
rv3028->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(rv3028->rtc))
return PTR_ERR(rv3028->rtc);
if (client->irq > 0) {
unsigned long flags;
/*
* If flags = 0, devm_request_threaded_irq() will use IRQ flags
* obtained from device tree.
*/
if (dev_fwnode(&client->dev))
flags = 0;
else
flags = IRQF_TRIGGER_LOW;
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, rv3028_handle_irq,
flags | IRQF_ONESHOT,
"rv3028", rv3028);
if (ret) {
dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
client->irq = 0;
}
}
if (!client->irq)
clear_bit(RTC_FEATURE_ALARM, rv3028->rtc->features);
ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
RV3028_CTRL1_WADA, RV3028_CTRL1_WADA);
if (ret)
return ret;
/* setup timestamping */
ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
RV3028_CTRL2_EIE | RV3028_CTRL2_TSE,
RV3028_CTRL2_EIE | RV3028_CTRL2_TSE);
if (ret)
return ret;
ret = rv3028_set_trickle_charger(rv3028, client);
if (ret)
return ret;
ret = rtc_add_group(rv3028->rtc, &rv3028_attr_group);
if (ret)
return ret;
set_bit(RTC_FEATURE_BACKUP_SWITCH_MODE, rv3028->rtc->features);
rv3028->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rv3028->rtc->range_max = RTC_TIMESTAMP_END_2099;
rv3028->rtc->ops = &rv3028_rtc_ops;
ret = devm_rtc_register_device(rv3028->rtc);
if (ret)
return ret;
nvmem_cfg.priv = rv3028->regmap;
devm_rtc_nvmem_register(rv3028->rtc, &nvmem_cfg);
eeprom_cfg.priv = rv3028;
devm_rtc_nvmem_register(rv3028->rtc, &eeprom_cfg);
rv3028->rtc->max_user_freq = 1;
#ifdef CONFIG_COMMON_CLK
rv3028_clkout_register_clk(rv3028, client);
#endif
return 0;
}
static const struct acpi_device_id rv3028_i2c_acpi_match[] = {
{ "MCRY3028" },
{ }
};
MODULE_DEVICE_TABLE(acpi, rv3028_i2c_acpi_match);
static const __maybe_unused struct of_device_id rv3028_of_match[] = {
{ .compatible = "microcrystal,rv3028", },
{ }
};
MODULE_DEVICE_TABLE(of, rv3028_of_match);
static const struct i2c_device_id rv3028_id_table[] = {
{ .name = "rv3028", },
{ }
};
MODULE_DEVICE_TABLE(i2c, rv3028_id_table);
static struct i2c_driver rv3028_driver = {
.driver = {
.name = "rtc-rv3028",
.acpi_match_table = rv3028_i2c_acpi_match,
.of_match_table = of_match_ptr(rv3028_of_match),
},
.id_table = rv3028_id_table,
.probe = rv3028_probe,
};
module_i2c_driver(rv3028_driver);
MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
MODULE_DESCRIPTION("Micro Crystal RV3028 RTC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-rv3028.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* SPI Driver for Microchip MCP795 RTC
*
* Copyright (C) Josef Gajdusek <[email protected]>
*
* based on other Linux RTC drivers
*
* Device datasheet:
* https://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/printk.h>
#include <linux/spi/spi.h>
#include <linux/rtc.h>
#include <linux/of.h>
#include <linux/bcd.h>
#include <linux/delay.h>
/* MCP795 Instructions, see datasheet table 3-1 */
#define MCP795_EEREAD 0x03
#define MCP795_EEWRITE 0x02
#define MCP795_EEWRDI 0x04
#define MCP795_EEWREN 0x06
#define MCP795_SRREAD 0x05
#define MCP795_SRWRITE 0x01
#define MCP795_READ 0x13
#define MCP795_WRITE 0x12
#define MCP795_UNLOCK 0x14
#define MCP795_IDWRITE 0x32
#define MCP795_IDREAD 0x33
#define MCP795_CLRWDT 0x44
#define MCP795_CLRRAM 0x54
/* MCP795 RTCC registers, see datasheet table 4-1 */
#define MCP795_REG_SECONDS 0x01
#define MCP795_REG_DAY 0x04
#define MCP795_REG_MONTH 0x06
#define MCP795_REG_CONTROL 0x08
#define MCP795_REG_ALM0_SECONDS 0x0C
#define MCP795_REG_ALM0_DAY 0x0F
#define MCP795_ST_BIT BIT(7)
#define MCP795_24_BIT BIT(6)
#define MCP795_LP_BIT BIT(5)
#define MCP795_EXTOSC_BIT BIT(3)
#define MCP795_OSCON_BIT BIT(5)
#define MCP795_ALM0_BIT BIT(4)
#define MCP795_ALM1_BIT BIT(5)
#define MCP795_ALM0IF_BIT BIT(3)
#define MCP795_ALM0C0_BIT BIT(4)
#define MCP795_ALM0C1_BIT BIT(5)
#define MCP795_ALM0C2_BIT BIT(6)
#define SEC_PER_DAY (24 * 60 * 60)
static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
{
struct spi_device *spi = to_spi_device(dev);
int ret;
u8 tx[2];
tx[0] = MCP795_READ;
tx[1] = addr;
ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
if (ret)
dev_err(dev, "Failed reading %d bytes from address %x.\n",
count, addr);
return ret;
}
static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
{
struct spi_device *spi = to_spi_device(dev);
int ret;
u8 tx[257];
tx[0] = MCP795_WRITE;
tx[1] = addr;
memcpy(&tx[2], data, count);
ret = spi_write(spi, tx, 2 + count);
if (ret)
dev_err(dev, "Failed to write %d bytes to address %x.\n",
count, addr);
return ret;
}
static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
{
int ret;
u8 tmp;
ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
if (ret)
return ret;
if ((tmp & mask) != state) {
tmp = (tmp & ~mask) | state;
ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
}
return ret;
}
static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
{
int retries = 5;
int ret;
u8 data;
ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
if (ret)
return ret;
ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
if (ret)
return ret;
*extosc = !!(data & MCP795_EXTOSC_BIT);
ret = mcp795_rtcc_set_bits(
dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
if (ret)
return ret;
/* wait for the OSCON bit to clear */
do {
usleep_range(700, 800);
ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
if (ret)
break;
if (!(data & MCP795_OSCON_BIT))
break;
} while (--retries);
return !retries ? -EIO : ret;
}
static int mcp795_start_oscillator(struct device *dev, bool *extosc)
{
if (extosc) {
u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
int ret;
ret = mcp795_rtcc_set_bits(
dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
if (ret)
return ret;
}
return mcp795_rtcc_set_bits(
dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
}
/* Enable or disable Alarm 0 in RTC */
static int mcp795_update_alarm(struct device *dev, bool enable)
{
int ret;
dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
if (enable) {
/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
MCP795_ALM0IF_BIT, 0);
if (ret)
return ret;
/* enable alarm 0 */
ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
MCP795_ALM0_BIT, MCP795_ALM0_BIT);
} else {
/* disable alarm 0 and alarm 1 */
ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
}
return ret;
}
static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
{
int ret;
u8 data[7];
bool extosc;
/* Stop RTC and store current value of EXTOSC bit */
ret = mcp795_stop_oscillator(dev, &extosc);
if (ret)
return ret;
/* Read first, so we can leave config bits untouched */
ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
if (ret)
return ret;
data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
data[2] = bin2bcd(tim->tm_hour);
data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
data[4] = bin2bcd(tim->tm_mday);
data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
if (tim->tm_year > 100)
tim->tm_year -= 100;
data[6] = bin2bcd(tim->tm_year);
/* Always write the date and month using a separate Write command.
* This is a workaround for a know silicon issue that some combinations
* of date and month values may result in the date being reset to 1.
*/
ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
if (ret)
return ret;
ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
if (ret)
return ret;
/* Start back RTC and restore previous value of EXTOSC bit.
* There is no need to clear EXTOSC bit when the previous value was 0
* because it was already cleared when stopping the RTC oscillator.
*/
ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
if (ret)
return ret;
dev_dbg(dev, "Set mcp795: %ptR\n", tim);
return 0;
}
static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
{
int ret;
u8 data[7];
ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
if (ret)
return ret;
tim->tm_sec = bcd2bin(data[0] & 0x7F);
tim->tm_min = bcd2bin(data[1] & 0x7F);
tim->tm_hour = bcd2bin(data[2] & 0x3F);
tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
tim->tm_mday = bcd2bin(data[4] & 0x3F);
tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
return 0;
}
static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct rtc_time now_tm;
time64_t now;
time64_t later;
u8 tmp[6];
int ret;
/* Read current time from RTC hardware */
ret = mcp795_read_time(dev, &now_tm);
if (ret)
return ret;
/* Get the number of seconds since 1970 */
now = rtc_tm_to_time64(&now_tm);
later = rtc_tm_to_time64(&alm->time);
if (later <= now)
return -EINVAL;
/* make sure alarm fires within the next one year */
if ((later - now) >=
(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
return -EDOM;
/* disable alarm */
ret = mcp795_update_alarm(dev, false);
if (ret)
return ret;
/* Read registers, so we can leave configuration bits untouched */
ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
if (ret)
return ret;
alm->time.tm_year = -1;
alm->time.tm_isdst = -1;
alm->time.tm_yday = -1;
tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
/* set alarm match: seconds, minutes, hour, day, date and month */
tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
if (ret)
return ret;
/* enable alarm if requested */
if (alm->enabled) {
ret = mcp795_update_alarm(dev, true);
if (ret)
return ret;
dev_dbg(dev, "Alarm IRQ armed\n");
}
dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
&alm->time, alm->time.tm_wday, &alm->time);
return 0;
}
static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
u8 data[6];
int ret;
ret = mcp795_rtcc_read(
dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
if (ret)
return ret;
alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
alm->time.tm_min = bcd2bin(data[1] & 0x7F);
alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
alm->time.tm_year = -1;
alm->time.tm_isdst = -1;
alm->time.tm_yday = -1;
dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
&alm->time, alm->time.tm_wday, &alm->time);
return 0;
}
static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
return mcp795_update_alarm(dev, !!enabled);
}
static irqreturn_t mcp795_irq(int irq, void *data)
{
struct spi_device *spi = data;
struct rtc_device *rtc = spi_get_drvdata(spi);
int ret;
rtc_lock(rtc);
/* Disable alarm.
* There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
* because it is done every time when alarm is enabled.
*/
ret = mcp795_update_alarm(&spi->dev, false);
if (ret)
dev_err(&spi->dev,
"Failed to disable alarm in IRQ (ret=%d)\n", ret);
rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
rtc_unlock(rtc);
return IRQ_HANDLED;
}
static const struct rtc_class_ops mcp795_rtc_ops = {
.read_time = mcp795_read_time,
.set_time = mcp795_set_time,
.read_alarm = mcp795_read_alarm,
.set_alarm = mcp795_set_alarm,
.alarm_irq_enable = mcp795_alarm_irq_enable
};
static int mcp795_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
int ret;
spi->mode = SPI_MODE_0;
spi->bits_per_word = 8;
ret = spi_setup(spi);
if (ret) {
dev_err(&spi->dev, "Unable to setup SPI\n");
return ret;
}
/* Start the oscillator but don't set the value of EXTOSC bit */
mcp795_start_oscillator(&spi->dev, NULL);
/* Clear the 12 hour mode flag*/
mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
&mcp795_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
spi_set_drvdata(spi, rtc);
if (spi->irq > 0) {
dev_dbg(&spi->dev, "Alarm support enabled\n");
/* Clear any pending alarm (ALM0IF bit) before requesting
* the interrupt.
*/
mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
MCP795_ALM0IF_BIT, 0);
ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
dev_name(&rtc->dev), spi);
if (ret)
dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
spi->irq, ret);
else
device_init_wakeup(&spi->dev, true);
}
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id mcp795_of_match[] = {
{ .compatible = "maxim,mcp795" },
{ }
};
MODULE_DEVICE_TABLE(of, mcp795_of_match);
#endif
static const struct spi_device_id mcp795_spi_ids[] = {
{ .name = "mcp795" },
{ }
};
MODULE_DEVICE_TABLE(spi, mcp795_spi_ids);
static struct spi_driver mcp795_driver = {
.driver = {
.name = "rtc-mcp795",
.of_match_table = of_match_ptr(mcp795_of_match),
},
.probe = mcp795_probe,
.id_table = mcp795_spi_ids,
};
module_spi_driver(mcp795_driver);
MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
MODULE_AUTHOR("Josef Gajdusek <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:mcp795");
| linux-master | drivers/rtc/rtc-mcp795.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
*
* Copyright (C) 2015 Xilinx, Inc.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
/* RTC Registers */
#define RTC_SET_TM_WR 0x00
#define RTC_SET_TM_RD 0x04
#define RTC_CALIB_WR 0x08
#define RTC_CALIB_RD 0x0C
#define RTC_CUR_TM 0x10
#define RTC_CUR_TICK 0x14
#define RTC_ALRM 0x18
#define RTC_INT_STS 0x20
#define RTC_INT_MASK 0x24
#define RTC_INT_EN 0x28
#define RTC_INT_DIS 0x2C
#define RTC_CTRL 0x40
#define RTC_FR_EN BIT(20)
#define RTC_FR_DATSHIFT 16
#define RTC_TICK_MASK 0xFFFF
#define RTC_INT_SEC BIT(0)
#define RTC_INT_ALRM BIT(1)
#define RTC_OSC_EN BIT(24)
#define RTC_BATT_EN BIT(31)
#define RTC_CALIB_DEF 0x7FFF
#define RTC_CALIB_MASK 0x1FFFFF
#define RTC_ALRM_MASK BIT(1)
#define RTC_MSEC 1000
#define RTC_FR_MASK 0xF0000
#define RTC_FR_MAX_TICKS 16
#define RTC_PPB 1000000000LL
#define RTC_MIN_OFFSET -32768000
#define RTC_MAX_OFFSET 32767000
struct xlnx_rtc_dev {
struct rtc_device *rtc;
void __iomem *reg_base;
int alarm_irq;
int sec_irq;
struct clk *rtc_clk;
unsigned int freq;
};
static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
unsigned long new_time;
/*
* The value written will be updated after 1 sec into the
* seconds read register, so we need to program time +1 sec
* to get the correct time on read.
*/
new_time = rtc_tm_to_time64(tm) + 1;
writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
/*
* Clear the rtc interrupt status register after setting the
* time. During a read_time function, the code should read the
* RTC_INT_STATUS register and if bit 0 is still 0, it means
* that one second has not elapsed yet since RTC was set and
* the current time should be read from SET_TIME_READ register;
* otherwise, CURRENT_TIME register is read to report the time
*/
writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
return 0;
}
static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
u32 status;
unsigned long read_time;
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
status = readl(xrtcdev->reg_base + RTC_INT_STS);
if (status & RTC_INT_SEC) {
/*
* RTC has updated the CURRENT_TIME with the time written into
* SET_TIME_WRITE register.
*/
read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
} else {
/*
* Time written in SET_TIME_WRITE has not yet updated into
* the seconds read register, so read the time from the
* SET_TIME_WRITE instead of CURRENT_TIME register.
* Since we add +1 sec while writing, we need to -1 sec while
* reading.
*/
read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
}
rtc_time64_to_tm(read_time, tm);
return 0;
}
static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
return 0;
}
static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
unsigned int status;
ulong timeout;
timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
if (enabled) {
while (1) {
status = readl(xrtcdev->reg_base + RTC_INT_STS);
if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
break;
if (time_after_eq(jiffies, timeout)) {
dev_err(dev, "Time out occur, while clearing alarm status bit\n");
return -ETIMEDOUT;
}
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
}
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
} else {
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
}
return 0;
}
static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
unsigned long alarm_time;
alarm_time = rtc_tm_to_time64(&alrm->time);
writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
return 0;
}
static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
{
u32 rtc_ctrl;
/* Enable RTC switch to battery when VCC_PSAUX is not available */
rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
rtc_ctrl |= RTC_BATT_EN;
writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
}
static int xlnx_rtc_read_offset(struct device *dev, long *offset)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
unsigned long long rtc_ppb = RTC_PPB;
unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
unsigned int calibval;
long offset_val;
calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
/* Offset with seconds ticks */
offset_val = calibval & RTC_TICK_MASK;
offset_val = offset_val - RTC_CALIB_DEF;
offset_val = offset_val * tick_mult;
/* Offset with fractional ticks */
if (calibval & RTC_FR_EN)
offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT)
* (tick_mult / RTC_FR_MAX_TICKS);
*offset = offset_val;
return 0;
}
static int xlnx_rtc_set_offset(struct device *dev, long offset)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
unsigned long long rtc_ppb = RTC_PPB;
unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq);
unsigned char fract_tick = 0;
unsigned int calibval;
short int max_tick;
int fract_offset;
if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET)
return -ERANGE;
/* Number ticks for given offset */
max_tick = div_s64_rem(offset, tick_mult, &fract_offset);
/* Number fractional ticks for given offset */
if (fract_offset) {
if (fract_offset < 0) {
fract_offset = fract_offset + tick_mult;
max_tick--;
}
if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) {
for (fract_tick = 1; fract_tick < 16; fract_tick++) {
if (fract_offset <=
(fract_tick *
(tick_mult / RTC_FR_MAX_TICKS)))
break;
}
}
}
/* Zynqmp RTC uses second and fractional tick
* counters for compensation
*/
calibval = max_tick + RTC_CALIB_DEF;
if (fract_tick)
calibval |= RTC_FR_EN;
calibval |= (fract_tick << RTC_FR_DATSHIFT);
writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
return 0;
}
static const struct rtc_class_ops xlnx_rtc_ops = {
.set_time = xlnx_rtc_set_time,
.read_time = xlnx_rtc_read_time,
.read_alarm = xlnx_rtc_read_alarm,
.set_alarm = xlnx_rtc_set_alarm,
.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
.read_offset = xlnx_rtc_read_offset,
.set_offset = xlnx_rtc_set_offset,
};
static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
{
struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
unsigned int status;
status = readl(xrtcdev->reg_base + RTC_INT_STS);
/* Check if interrupt asserted */
if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
return IRQ_NONE;
/* Disable RTC_INT_ALRM interrupt only */
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
if (status & RTC_INT_ALRM)
rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static int xlnx_rtc_probe(struct platform_device *pdev)
{
struct xlnx_rtc_dev *xrtcdev;
int ret;
xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
if (!xrtcdev)
return -ENOMEM;
platform_set_drvdata(pdev, xrtcdev);
xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(xrtcdev->rtc))
return PTR_ERR(xrtcdev->rtc);
xrtcdev->rtc->ops = &xlnx_rtc_ops;
xrtcdev->rtc->range_max = U32_MAX;
xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xrtcdev->reg_base))
return PTR_ERR(xrtcdev->reg_base);
xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
if (xrtcdev->alarm_irq < 0)
return xrtcdev->alarm_irq;
ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
xlnx_rtc_interrupt, 0,
dev_name(&pdev->dev), xrtcdev);
if (ret) {
dev_err(&pdev->dev, "request irq failed\n");
return ret;
}
xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
if (xrtcdev->sec_irq < 0)
return xrtcdev->sec_irq;
ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
xlnx_rtc_interrupt, 0,
dev_name(&pdev->dev), xrtcdev);
if (ret) {
dev_err(&pdev->dev, "request irq failed\n");
return ret;
}
/* Getting the rtc_clk info */
xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk");
if (IS_ERR(xrtcdev->rtc_clk)) {
if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER)
dev_warn(&pdev->dev, "Device clock not found.\n");
}
xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk);
if (!xrtcdev->freq) {
ret = of_property_read_u32(pdev->dev.of_node, "calibration",
&xrtcdev->freq);
if (ret)
xrtcdev->freq = RTC_CALIB_DEF;
}
ret = readl(xrtcdev->reg_base + RTC_CALIB_RD);
if (!ret)
writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
xlnx_init_rtc(xrtcdev);
device_init_wakeup(&pdev->dev, 1);
return devm_rtc_register_device(xrtcdev->rtc);
}
static void xlnx_rtc_remove(struct platform_device *pdev)
{
xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
device_init_wakeup(&pdev->dev, 0);
}
static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(xrtcdev->alarm_irq);
else
xlnx_rtc_alarm_irq_enable(dev, 0);
return 0;
}
static int __maybe_unused xlnx_rtc_resume(struct device *dev)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(xrtcdev->alarm_irq);
else
xlnx_rtc_alarm_irq_enable(dev, 1);
return 0;
}
static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
static const struct of_device_id xlnx_rtc_of_match[] = {
{.compatible = "xlnx,zynqmp-rtc" },
{ }
};
MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
static struct platform_driver xlnx_rtc_driver = {
.probe = xlnx_rtc_probe,
.remove_new = xlnx_rtc_remove,
.driver = {
.name = KBUILD_MODNAME,
.pm = &xlnx_rtc_pm_ops,
.of_match_table = xlnx_rtc_of_match,
},
};
module_platform_driver(xlnx_rtc_driver);
MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
MODULE_AUTHOR("Xilinx Inc.");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-zynqmp.c |
/* rtc-starfire.c: Starfire platform RTC driver.
*
* Author: David S. Miller
* License: GPL
*
* Copyright (C) 2008 David S. Miller <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <asm/oplib.h>
static u32 starfire_get_time(void)
{
static char obp_gettod[32];
static u32 unix_tod;
sprintf(obp_gettod, "h# %08x unix-gettod",
(unsigned int) (long) &unix_tod);
prom_feval(obp_gettod);
return unix_tod;
}
static int starfire_read_time(struct device *dev, struct rtc_time *tm)
{
rtc_time64_to_tm(starfire_get_time(), tm);
return 0;
}
static const struct rtc_class_ops starfire_rtc_ops = {
.read_time = starfire_read_time,
};
static int __init starfire_rtc_probe(struct platform_device *pdev)
{
struct rtc_device *rtc;
rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &starfire_rtc_ops;
rtc->range_max = U32_MAX;
platform_set_drvdata(pdev, rtc);
return devm_rtc_register_device(rtc);
}
static struct platform_driver starfire_rtc_driver = {
.driver = {
.name = "rtc-starfire",
},
};
builtin_platform_driver_probe(starfire_rtc_driver, starfire_rtc_probe);
| linux-master | drivers/rtc/rtc-starfire.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2017
* Author: Amelie Delaunay <[email protected]>
*/
#include <linux/bcd.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#define DRIVER_NAME "stm32_rtc"
/* STM32_RTC_TR bit fields */
#define STM32_RTC_TR_SEC_SHIFT 0
#define STM32_RTC_TR_SEC GENMASK(6, 0)
#define STM32_RTC_TR_MIN_SHIFT 8
#define STM32_RTC_TR_MIN GENMASK(14, 8)
#define STM32_RTC_TR_HOUR_SHIFT 16
#define STM32_RTC_TR_HOUR GENMASK(21, 16)
/* STM32_RTC_DR bit fields */
#define STM32_RTC_DR_DATE_SHIFT 0
#define STM32_RTC_DR_DATE GENMASK(5, 0)
#define STM32_RTC_DR_MONTH_SHIFT 8
#define STM32_RTC_DR_MONTH GENMASK(12, 8)
#define STM32_RTC_DR_WDAY_SHIFT 13
#define STM32_RTC_DR_WDAY GENMASK(15, 13)
#define STM32_RTC_DR_YEAR_SHIFT 16
#define STM32_RTC_DR_YEAR GENMASK(23, 16)
/* STM32_RTC_CR bit fields */
#define STM32_RTC_CR_FMT BIT(6)
#define STM32_RTC_CR_ALRAE BIT(8)
#define STM32_RTC_CR_ALRAIE BIT(12)
/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
#define STM32_RTC_ISR_ALRAWF BIT(0)
#define STM32_RTC_ISR_INITS BIT(4)
#define STM32_RTC_ISR_RSF BIT(5)
#define STM32_RTC_ISR_INITF BIT(6)
#define STM32_RTC_ISR_INIT BIT(7)
#define STM32_RTC_ISR_ALRAF BIT(8)
/* STM32_RTC_PRER bit fields */
#define STM32_RTC_PRER_PRED_S_SHIFT 0
#define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
#define STM32_RTC_PRER_PRED_A_SHIFT 16
#define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
/* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
#define STM32_RTC_ALRMXR_SEC_SHIFT 0
#define STM32_RTC_ALRMXR_SEC GENMASK(6, 0)
#define STM32_RTC_ALRMXR_SEC_MASK BIT(7)
#define STM32_RTC_ALRMXR_MIN_SHIFT 8
#define STM32_RTC_ALRMXR_MIN GENMASK(14, 8)
#define STM32_RTC_ALRMXR_MIN_MASK BIT(15)
#define STM32_RTC_ALRMXR_HOUR_SHIFT 16
#define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16)
#define STM32_RTC_ALRMXR_PM BIT(22)
#define STM32_RTC_ALRMXR_HOUR_MASK BIT(23)
#define STM32_RTC_ALRMXR_DATE_SHIFT 24
#define STM32_RTC_ALRMXR_DATE GENMASK(29, 24)
#define STM32_RTC_ALRMXR_WDSEL BIT(30)
#define STM32_RTC_ALRMXR_WDAY_SHIFT 24
#define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24)
#define STM32_RTC_ALRMXR_DATE_MASK BIT(31)
/* STM32_RTC_SR/_SCR bit fields */
#define STM32_RTC_SR_ALRA BIT(0)
/* STM32_RTC_VERR bit fields */
#define STM32_RTC_VERR_MINREV_SHIFT 0
#define STM32_RTC_VERR_MINREV GENMASK(3, 0)
#define STM32_RTC_VERR_MAJREV_SHIFT 4
#define STM32_RTC_VERR_MAJREV GENMASK(7, 4)
/* STM32_RTC_WPR key constants */
#define RTC_WPR_1ST_KEY 0xCA
#define RTC_WPR_2ND_KEY 0x53
#define RTC_WPR_WRONG_KEY 0xFF
/* Max STM32 RTC register offset is 0x3FC */
#define UNDEF_REG 0xFFFF
/* STM32 RTC driver time helpers */
#define SEC_PER_DAY (24 * 60 * 60)
struct stm32_rtc;
struct stm32_rtc_registers {
u16 tr;
u16 dr;
u16 cr;
u16 isr;
u16 prer;
u16 alrmar;
u16 wpr;
u16 sr;
u16 scr;
u16 verr;
};
struct stm32_rtc_events {
u32 alra;
};
struct stm32_rtc_data {
const struct stm32_rtc_registers regs;
const struct stm32_rtc_events events;
void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
bool has_pclk;
bool need_dbp;
bool need_accuracy;
};
struct stm32_rtc {
struct rtc_device *rtc_dev;
void __iomem *base;
struct regmap *dbp;
unsigned int dbp_reg;
unsigned int dbp_mask;
struct clk *pclk;
struct clk *rtc_ck;
const struct stm32_rtc_data *data;
int irq_alarm;
};
static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
}
static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
}
static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int isr = readl_relaxed(rtc->base + regs->isr);
if (!(isr & STM32_RTC_ISR_INITF)) {
isr |= STM32_RTC_ISR_INIT;
writel_relaxed(isr, rtc->base + regs->isr);
/*
* It takes around 2 rtc_ck clock cycles to enter in
* initialization phase mode (and have INITF flag set). As
* slowest rtc_ck frequency may be 32kHz and highest should be
* 1MHz, we poll every 10 us with a timeout of 100ms.
*/
return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr,
(isr & STM32_RTC_ISR_INITF),
10, 100000);
}
return 0;
}
static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int isr = readl_relaxed(rtc->base + regs->isr);
isr &= ~STM32_RTC_ISR_INIT;
writel_relaxed(isr, rtc->base + regs->isr);
}
static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int isr = readl_relaxed(rtc->base + regs->isr);
isr &= ~STM32_RTC_ISR_RSF;
writel_relaxed(isr, rtc->base + regs->isr);
/*
* Wait for RSF to be set to ensure the calendar registers are
* synchronised, it takes around 2 rtc_ck clock cycles
*/
return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
isr,
(isr & STM32_RTC_ISR_RSF),
10, 100000);
}
static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
unsigned int flags)
{
rtc->data->clear_events(rtc, flags);
}
static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
{
struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
const struct stm32_rtc_registers *regs = &rtc->data->regs;
const struct stm32_rtc_events *evts = &rtc->data->events;
unsigned int status, cr;
rtc_lock(rtc->rtc_dev);
status = readl_relaxed(rtc->base + regs->sr);
cr = readl_relaxed(rtc->base + regs->cr);
if ((status & evts->alra) &&
(cr & STM32_RTC_CR_ALRAIE)) {
/* Alarm A flag - Alarm interrupt */
dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
/* Pass event to the kernel */
rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
/* Clear event flags, otherwise new events won't be received */
stm32_rtc_clear_event_flags(rtc, evts->alra);
}
rtc_unlock(rtc->rtc_dev);
return IRQ_HANDLED;
}
/* Convert rtc_time structure from bin to bcd format */
static void tm2bcd(struct rtc_time *tm)
{
tm->tm_sec = bin2bcd(tm->tm_sec);
tm->tm_min = bin2bcd(tm->tm_min);
tm->tm_hour = bin2bcd(tm->tm_hour);
tm->tm_mday = bin2bcd(tm->tm_mday);
tm->tm_mon = bin2bcd(tm->tm_mon + 1);
tm->tm_year = bin2bcd(tm->tm_year - 100);
/*
* Number of days since Sunday
* - on kernel side, 0=Sunday...6=Saturday
* - on rtc side, 0=invalid,1=Monday...7=Sunday
*/
tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
}
/* Convert rtc_time structure from bcd to bin format */
static void bcd2tm(struct rtc_time *tm)
{
tm->tm_sec = bcd2bin(tm->tm_sec);
tm->tm_min = bcd2bin(tm->tm_min);
tm->tm_hour = bcd2bin(tm->tm_hour);
tm->tm_mday = bcd2bin(tm->tm_mday);
tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
tm->tm_year = bcd2bin(tm->tm_year) + 100;
/*
* Number of days since Sunday
* - on kernel side, 0=Sunday...6=Saturday
* - on rtc side, 0=invalid,1=Monday...7=Sunday
*/
tm->tm_wday %= 7;
}
static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int tr, dr;
/* Time and Date in BCD format */
tr = readl_relaxed(rtc->base + regs->tr);
dr = readl_relaxed(rtc->base + regs->dr);
tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
/* We don't report tm_yday and tm_isdst */
bcd2tm(tm);
return 0;
}
static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int tr, dr;
int ret = 0;
tm2bcd(tm);
/* Time in BCD format */
tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
/* Date in BCD format */
dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
stm32_rtc_wpr_unlock(rtc);
ret = stm32_rtc_enter_init_mode(rtc);
if (ret) {
dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
goto end;
}
writel_relaxed(tr, rtc->base + regs->tr);
writel_relaxed(dr, rtc->base + regs->dr);
stm32_rtc_exit_init_mode(rtc);
ret = stm32_rtc_wait_sync(rtc);
end:
stm32_rtc_wpr_lock(rtc);
return ret;
}
static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
const struct stm32_rtc_registers *regs = &rtc->data->regs;
const struct stm32_rtc_events *evts = &rtc->data->events;
struct rtc_time *tm = &alrm->time;
unsigned int alrmar, cr, status;
alrmar = readl_relaxed(rtc->base + regs->alrmar);
cr = readl_relaxed(rtc->base + regs->cr);
status = readl_relaxed(rtc->base + regs->sr);
if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
/*
* Date/day doesn't matter in Alarm comparison so alarm
* triggers every day
*/
tm->tm_mday = -1;
tm->tm_wday = -1;
} else {
if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
/* Alarm is set to a day of week */
tm->tm_mday = -1;
tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
STM32_RTC_ALRMXR_WDAY_SHIFT;
tm->tm_wday %= 7;
} else {
/* Alarm is set to a day of month */
tm->tm_wday = -1;
tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
STM32_RTC_ALRMXR_DATE_SHIFT;
}
}
if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
/* Hours don't matter in Alarm comparison */
tm->tm_hour = -1;
} else {
tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
STM32_RTC_ALRMXR_HOUR_SHIFT;
if (alrmar & STM32_RTC_ALRMXR_PM)
tm->tm_hour += 12;
}
if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
/* Minutes don't matter in Alarm comparison */
tm->tm_min = -1;
} else {
tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
STM32_RTC_ALRMXR_MIN_SHIFT;
}
if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
/* Seconds don't matter in Alarm comparison */
tm->tm_sec = -1;
} else {
tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
STM32_RTC_ALRMXR_SEC_SHIFT;
}
bcd2tm(tm);
alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
alrm->pending = (status & evts->alra) ? 1 : 0;
return 0;
}
static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
const struct stm32_rtc_registers *regs = &rtc->data->regs;
const struct stm32_rtc_events *evts = &rtc->data->events;
unsigned int cr;
cr = readl_relaxed(rtc->base + regs->cr);
stm32_rtc_wpr_unlock(rtc);
/* We expose Alarm A to the kernel */
if (enabled)
cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
else
cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
writel_relaxed(cr, rtc->base + regs->cr);
/* Clear event flags, otherwise new events won't be received */
stm32_rtc_clear_event_flags(rtc, evts->alra);
stm32_rtc_wpr_lock(rtc);
return 0;
}
static int stm32_rtc_valid_alrm(struct device *dev, struct rtc_time *tm)
{
static struct rtc_time now;
time64_t max_alarm_time64;
int max_day_forward;
int next_month;
int next_year;
/*
* Assuming current date is M-D-Y H:M:S.
* RTC alarm can't be set on a specific month and year.
* So the valid alarm range is:
* M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
*/
stm32_rtc_read_time(dev, &now);
/*
* Find the next month and the year of the next month.
* Note: tm_mon and next_month are from 0 to 11
*/
next_month = now.tm_mon + 1;
if (next_month == 12) {
next_month = 0;
next_year = now.tm_year + 1;
} else {
next_year = now.tm_year;
}
/* Find the maximum limit of alarm in days. */
max_day_forward = rtc_month_days(now.tm_mon, now.tm_year)
- now.tm_mday
+ min(rtc_month_days(next_month, next_year), now.tm_mday);
/* Convert to timestamp and compare the alarm time and its upper limit */
max_alarm_time64 = rtc_tm_to_time64(&now) + max_day_forward * SEC_PER_DAY;
return rtc_tm_to_time64(tm) <= max_alarm_time64 ? 0 : -EINVAL;
}
static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
const struct stm32_rtc_registers *regs = &rtc->data->regs;
struct rtc_time *tm = &alrm->time;
unsigned int cr, isr, alrmar;
int ret = 0;
/*
* RTC alarm can't be set on a specific date, unless this date is
* up to the same day of month next month.
*/
if (stm32_rtc_valid_alrm(dev, tm) < 0) {
dev_err(dev, "Alarm can be set only on upcoming month.\n");
return -EINVAL;
}
tm2bcd(tm);
alrmar = 0;
/* tm_year and tm_mon are not used because not supported by RTC */
alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
STM32_RTC_ALRMXR_DATE;
/* 24-hour format */
alrmar &= ~STM32_RTC_ALRMXR_PM;
alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
STM32_RTC_ALRMXR_HOUR;
alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
STM32_RTC_ALRMXR_MIN;
alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
STM32_RTC_ALRMXR_SEC;
stm32_rtc_wpr_unlock(rtc);
/* Disable Alarm */
cr = readl_relaxed(rtc->base + regs->cr);
cr &= ~STM32_RTC_CR_ALRAE;
writel_relaxed(cr, rtc->base + regs->cr);
/*
* Poll Alarm write flag to be sure that Alarm update is allowed: it
* takes around 2 rtc_ck clock cycles
*/
ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
isr,
(isr & STM32_RTC_ISR_ALRAWF),
10, 100000);
if (ret) {
dev_err(dev, "Alarm update not allowed\n");
goto end;
}
/* Write to Alarm register */
writel_relaxed(alrmar, rtc->base + regs->alrmar);
stm32_rtc_alarm_irq_enable(dev, alrm->enabled);
end:
stm32_rtc_wpr_lock(rtc);
return ret;
}
static const struct rtc_class_ops stm32_rtc_ops = {
.read_time = stm32_rtc_read_time,
.set_time = stm32_rtc_set_time,
.read_alarm = stm32_rtc_read_alarm,
.set_alarm = stm32_rtc_set_alarm,
.alarm_irq_enable = stm32_rtc_alarm_irq_enable,
};
static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
unsigned int flags)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
/* Flags are cleared by writing 0 in RTC_ISR */
writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
rtc->base + regs->isr);
}
static const struct stm32_rtc_data stm32_rtc_data = {
.has_pclk = false,
.need_dbp = true,
.need_accuracy = false,
.regs = {
.tr = 0x00,
.dr = 0x04,
.cr = 0x08,
.isr = 0x0C,
.prer = 0x10,
.alrmar = 0x1C,
.wpr = 0x24,
.sr = 0x0C, /* set to ISR offset to ease alarm management */
.scr = UNDEF_REG,
.verr = UNDEF_REG,
},
.events = {
.alra = STM32_RTC_ISR_ALRAF,
},
.clear_events = stm32_rtc_clear_events,
};
static const struct stm32_rtc_data stm32h7_rtc_data = {
.has_pclk = true,
.need_dbp = true,
.need_accuracy = false,
.regs = {
.tr = 0x00,
.dr = 0x04,
.cr = 0x08,
.isr = 0x0C,
.prer = 0x10,
.alrmar = 0x1C,
.wpr = 0x24,
.sr = 0x0C, /* set to ISR offset to ease alarm management */
.scr = UNDEF_REG,
.verr = UNDEF_REG,
},
.events = {
.alra = STM32_RTC_ISR_ALRAF,
},
.clear_events = stm32_rtc_clear_events,
};
static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
unsigned int flags)
{
struct stm32_rtc_registers regs = rtc->data->regs;
/* Flags are cleared by writing 1 in RTC_SCR */
writel_relaxed(flags, rtc->base + regs.scr);
}
static const struct stm32_rtc_data stm32mp1_data = {
.has_pclk = true,
.need_dbp = false,
.need_accuracy = true,
.regs = {
.tr = 0x00,
.dr = 0x04,
.cr = 0x18,
.isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
.prer = 0x10,
.alrmar = 0x40,
.wpr = 0x24,
.sr = 0x50,
.scr = 0x5C,
.verr = 0x3F4,
},
.events = {
.alra = STM32_RTC_SR_ALRA,
},
.clear_events = stm32mp1_rtc_clear_events,
};
static const struct of_device_id stm32_rtc_of_match[] = {
{ .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
{ .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
{ .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
{}
};
MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
static int stm32_rtc_init(struct platform_device *pdev,
struct stm32_rtc *rtc)
{
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
unsigned int rate;
int ret;
rate = clk_get_rate(rtc->rtc_ck);
/* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
if (rate > (pred_a_max + 1) * (pred_s_max + 1)) {
dev_err(&pdev->dev, "rtc_ck rate is too high: %dHz\n", rate);
return -EINVAL;
}
if (rtc->data->need_accuracy) {
for (pred_a = 0; pred_a <= pred_a_max; pred_a++) {
pred_s = (rate / (pred_a + 1)) - 1;
if (pred_s <= pred_s_max && ((pred_s + 1) * (pred_a + 1)) == rate)
break;
}
} else {
for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
pred_s = (rate / (pred_a + 1)) - 1;
if (((pred_s + 1) * (pred_a + 1)) == rate)
break;
}
}
/*
* Can't find a 1Hz, so give priority to RTC power consumption
* by choosing the higher possible value for prediv_a
*/
if (pred_s > pred_s_max || pred_a > pred_a_max) {
pred_a = pred_a_max;
pred_s = (rate / (pred_a + 1)) - 1;
dev_warn(&pdev->dev, "rtc_ck is %s\n",
(rate < ((pred_a + 1) * (pred_s + 1))) ?
"fast" : "slow");
}
cr = readl_relaxed(rtc->base + regs->cr);
prer = readl_relaxed(rtc->base + regs->prer);
prer &= STM32_RTC_PRER_PRED_S | STM32_RTC_PRER_PRED_A;
pred_s = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) &
STM32_RTC_PRER_PRED_S;
pred_a = (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) &
STM32_RTC_PRER_PRED_A;
/* quit if there is nothing to initialize */
if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a))
return 0;
stm32_rtc_wpr_unlock(rtc);
ret = stm32_rtc_enter_init_mode(rtc);
if (ret) {
dev_err(&pdev->dev,
"Can't enter in init mode. Prescaler config failed.\n");
goto end;
}
writel_relaxed(pred_s, rtc->base + regs->prer);
writel_relaxed(pred_a | pred_s, rtc->base + regs->prer);
/* Force 24h time format */
cr &= ~STM32_RTC_CR_FMT;
writel_relaxed(cr, rtc->base + regs->cr);
stm32_rtc_exit_init_mode(rtc);
ret = stm32_rtc_wait_sync(rtc);
end:
stm32_rtc_wpr_lock(rtc);
return ret;
}
static int stm32_rtc_probe(struct platform_device *pdev)
{
struct stm32_rtc *rtc;
const struct stm32_rtc_registers *regs;
int ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->base))
return PTR_ERR(rtc->base);
rtc->data = (struct stm32_rtc_data *)
of_device_get_match_data(&pdev->dev);
regs = &rtc->data->regs;
if (rtc->data->need_dbp) {
rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"st,syscfg");
if (IS_ERR(rtc->dbp)) {
dev_err(&pdev->dev, "no st,syscfg\n");
return PTR_ERR(rtc->dbp);
}
ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
1, &rtc->dbp_reg);
if (ret) {
dev_err(&pdev->dev, "can't read DBP register offset\n");
return ret;
}
ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
2, &rtc->dbp_mask);
if (ret) {
dev_err(&pdev->dev, "can't read DBP register mask\n");
return ret;
}
}
if (!rtc->data->has_pclk) {
rtc->pclk = NULL;
rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
} else {
rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(rtc->pclk))
return dev_err_probe(&pdev->dev, PTR_ERR(rtc->pclk), "no pclk clock");
rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
}
if (IS_ERR(rtc->rtc_ck))
return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_ck), "no rtc_ck clock");
if (rtc->data->has_pclk) {
ret = clk_prepare_enable(rtc->pclk);
if (ret)
return ret;
}
ret = clk_prepare_enable(rtc->rtc_ck);
if (ret)
goto err_no_rtc_ck;
if (rtc->data->need_dbp)
regmap_update_bits(rtc->dbp, rtc->dbp_reg,
rtc->dbp_mask, rtc->dbp_mask);
/*
* After a system reset, RTC_ISR.INITS flag can be read to check if
* the calendar has been initialized or not. INITS flag is reset by a
* power-on reset (no vbat, no power-supply). It is not reset if
* rtc_ck parent clock has changed (so RTC prescalers need to be
* changed). That's why we cannot rely on this flag to know if RTC
* init has to be done.
*/
ret = stm32_rtc_init(pdev, rtc);
if (ret)
goto err;
rtc->irq_alarm = platform_get_irq(pdev, 0);
if (rtc->irq_alarm <= 0) {
ret = rtc->irq_alarm;
goto err;
}
ret = device_init_wakeup(&pdev->dev, true);
if (ret)
goto err;
ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm);
if (ret)
goto err;
platform_set_drvdata(pdev, rtc);
rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
&stm32_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rtc_dev)) {
ret = PTR_ERR(rtc->rtc_dev);
dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
ret);
goto err;
}
/* Handle RTC alarm interrupts */
ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
stm32_rtc_alarm_irq, IRQF_ONESHOT,
pdev->name, rtc);
if (ret) {
dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
rtc->irq_alarm);
goto err;
}
/*
* If INITS flag is reset (calendar year field set to 0x00), calendar
* must be initialized
*/
if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
dev_warn(&pdev->dev, "Date/Time must be initialized\n");
if (regs->verr != UNDEF_REG) {
u32 ver = readl_relaxed(rtc->base + regs->verr);
dev_info(&pdev->dev, "registered rev:%d.%d\n",
(ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
(ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
}
return 0;
err:
clk_disable_unprepare(rtc->rtc_ck);
err_no_rtc_ck:
if (rtc->data->has_pclk)
clk_disable_unprepare(rtc->pclk);
if (rtc->data->need_dbp)
regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
return ret;
}
static void stm32_rtc_remove(struct platform_device *pdev)
{
struct stm32_rtc *rtc = platform_get_drvdata(pdev);
const struct stm32_rtc_registers *regs = &rtc->data->regs;
unsigned int cr;
/* Disable interrupts */
stm32_rtc_wpr_unlock(rtc);
cr = readl_relaxed(rtc->base + regs->cr);
cr &= ~STM32_RTC_CR_ALRAIE;
writel_relaxed(cr, rtc->base + regs->cr);
stm32_rtc_wpr_lock(rtc);
clk_disable_unprepare(rtc->rtc_ck);
if (rtc->data->has_pclk)
clk_disable_unprepare(rtc->pclk);
/* Enable backup domain write protection if needed */
if (rtc->data->need_dbp)
regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
}
static int stm32_rtc_suspend(struct device *dev)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
if (rtc->data->has_pclk)
clk_disable_unprepare(rtc->pclk);
return 0;
}
static int stm32_rtc_resume(struct device *dev)
{
struct stm32_rtc *rtc = dev_get_drvdata(dev);
int ret = 0;
if (rtc->data->has_pclk) {
ret = clk_prepare_enable(rtc->pclk);
if (ret)
return ret;
}
ret = stm32_rtc_wait_sync(rtc);
if (ret < 0) {
if (rtc->data->has_pclk)
clk_disable_unprepare(rtc->pclk);
return ret;
}
return ret;
}
static const struct dev_pm_ops stm32_rtc_pm_ops = {
NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_rtc_suspend, stm32_rtc_resume)
};
static struct platform_driver stm32_rtc_driver = {
.probe = stm32_rtc_probe,
.remove_new = stm32_rtc_remove,
.driver = {
.name = DRIVER_NAME,
.pm = &stm32_rtc_pm_ops,
.of_match_table = stm32_rtc_of_match,
},
};
module_platform_driver(stm32_rtc_driver);
MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_AUTHOR("Amelie Delaunay <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-stm32.c |
// SPDX-License-Identifier: GPL-2.0-or-later
//
// Copyright (C) 2018 ROHM Semiconductors
//
// RTC driver for ROHM BD71828 and BD71815 PMIC
#include <linux/bcd.h>
#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
/*
* On BD71828 and BD71815 the ALM0 MASK is 14 bytes after the ALM0
* block start
*/
#define BD718XX_ALM_EN_OFFSET 14
/*
* We read regs RTC_SEC => RTC_YEAR
* this struct is ordered according to chip registers.
* Keep it u8 only (or packed) to avoid padding issues.
*/
struct bd70528_rtc_day {
u8 sec;
u8 min;
u8 hour;
} __packed;
struct bd70528_rtc_data {
struct bd70528_rtc_day time;
u8 week;
u8 day;
u8 month;
u8 year;
} __packed;
struct bd71828_rtc_alm {
struct bd70528_rtc_data alm0;
struct bd70528_rtc_data alm1;
u8 alm_mask;
u8 alm1_mask;
} __packed;
struct bd70528_rtc {
struct rohm_regmap_dev *parent;
struct regmap *regmap;
struct device *dev;
u8 reg_time_start;
u8 bd718xx_alm_block_start;
};
static inline void tmday2rtc(struct rtc_time *t, struct bd70528_rtc_day *d)
{
d->sec &= ~BD70528_MASK_RTC_SEC;
d->min &= ~BD70528_MASK_RTC_MINUTE;
d->hour &= ~BD70528_MASK_RTC_HOUR;
d->sec |= bin2bcd(t->tm_sec);
d->min |= bin2bcd(t->tm_min);
d->hour |= bin2bcd(t->tm_hour);
}
static inline void tm2rtc(struct rtc_time *t, struct bd70528_rtc_data *r)
{
r->day &= ~BD70528_MASK_RTC_DAY;
r->week &= ~BD70528_MASK_RTC_WEEK;
r->month &= ~BD70528_MASK_RTC_MONTH;
/*
* PM and 24H bits are not used by Wake - thus we clear them
* here and not in tmday2rtc() which is also used by wake.
*/
r->time.hour &= ~(BD70528_MASK_RTC_HOUR_PM | BD70528_MASK_RTC_HOUR_24H);
tmday2rtc(t, &r->time);
/*
* We do always set time in 24H mode.
*/
r->time.hour |= BD70528_MASK_RTC_HOUR_24H;
r->day |= bin2bcd(t->tm_mday);
r->week |= bin2bcd(t->tm_wday);
r->month |= bin2bcd(t->tm_mon + 1);
r->year = bin2bcd(t->tm_year - 100);
}
static inline void rtc2tm(struct bd70528_rtc_data *r, struct rtc_time *t)
{
t->tm_sec = bcd2bin(r->time.sec & BD70528_MASK_RTC_SEC);
t->tm_min = bcd2bin(r->time.min & BD70528_MASK_RTC_MINUTE);
t->tm_hour = bcd2bin(r->time.hour & BD70528_MASK_RTC_HOUR);
/*
* If RTC is in 12H mode, then bit BD70528_MASK_RTC_HOUR_PM
* is not BCD value but tells whether it is AM or PM
*/
if (!(r->time.hour & BD70528_MASK_RTC_HOUR_24H)) {
t->tm_hour %= 12;
if (r->time.hour & BD70528_MASK_RTC_HOUR_PM)
t->tm_hour += 12;
}
t->tm_mday = bcd2bin(r->day & BD70528_MASK_RTC_DAY);
t->tm_mon = bcd2bin(r->month & BD70528_MASK_RTC_MONTH) - 1;
t->tm_year = 100 + bcd2bin(r->year & BD70528_MASK_RTC_YEAR);
t->tm_wday = bcd2bin(r->week & BD70528_MASK_RTC_WEEK);
}
static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a)
{
int ret;
struct bd71828_rtc_alm alm;
struct bd70528_rtc *r = dev_get_drvdata(dev);
ret = regmap_bulk_read(r->regmap, r->bd718xx_alm_block_start, &alm,
sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
return ret;
}
tm2rtc(&a->time, &alm.alm0);
if (!a->enabled)
alm.alm_mask &= ~BD70528_MASK_ALM_EN;
else
alm.alm_mask |= BD70528_MASK_ALM_EN;
ret = regmap_bulk_write(r->regmap, r->bd718xx_alm_block_start, &alm,
sizeof(alm));
if (ret)
dev_err(dev, "Failed to set alarm time\n");
return ret;
}
static int bd71828_read_alarm(struct device *dev, struct rtc_wkalrm *a)
{
int ret;
struct bd71828_rtc_alm alm;
struct bd70528_rtc *r = dev_get_drvdata(dev);
ret = regmap_bulk_read(r->regmap, r->bd718xx_alm_block_start, &alm,
sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
return ret;
}
rtc2tm(&alm.alm0, &a->time);
a->time.tm_mday = -1;
a->time.tm_mon = -1;
a->time.tm_year = -1;
a->enabled = !!(alm.alm_mask & BD70528_MASK_ALM_EN);
a->pending = 0;
return 0;
}
static int bd71828_set_time(struct device *dev, struct rtc_time *t)
{
int ret;
struct bd70528_rtc_data rtc_data;
struct bd70528_rtc *r = dev_get_drvdata(dev);
ret = regmap_bulk_read(r->regmap, r->reg_time_start, &rtc_data,
sizeof(rtc_data));
if (ret) {
dev_err(dev, "Failed to read RTC time registers\n");
return ret;
}
tm2rtc(t, &rtc_data);
ret = regmap_bulk_write(r->regmap, r->reg_time_start, &rtc_data,
sizeof(rtc_data));
if (ret)
dev_err(dev, "Failed to set RTC time\n");
return ret;
}
static int bd70528_get_time(struct device *dev, struct rtc_time *t)
{
struct bd70528_rtc *r = dev_get_drvdata(dev);
struct bd70528_rtc_data rtc_data;
int ret;
/* read the RTC date and time registers all at once */
ret = regmap_bulk_read(r->regmap, r->reg_time_start, &rtc_data,
sizeof(rtc_data));
if (ret) {
dev_err(dev, "Failed to read RTC time (err %d)\n", ret);
return ret;
}
rtc2tm(&rtc_data, t);
return 0;
}
static int bd71828_alm_enable(struct device *dev, unsigned int enabled)
{
int ret;
struct bd70528_rtc *r = dev_get_drvdata(dev);
unsigned int enableval = BD70528_MASK_ALM_EN;
if (!enabled)
enableval = 0;
ret = regmap_update_bits(r->regmap, r->bd718xx_alm_block_start +
BD718XX_ALM_EN_OFFSET, BD70528_MASK_ALM_EN,
enableval);
if (ret)
dev_err(dev, "Failed to change alarm state\n");
return ret;
}
static const struct rtc_class_ops bd71828_rtc_ops = {
.read_time = bd70528_get_time,
.set_time = bd71828_set_time,
.read_alarm = bd71828_read_alarm,
.set_alarm = bd71828_set_alarm,
.alarm_irq_enable = bd71828_alm_enable,
};
static irqreturn_t alm_hndlr(int irq, void *data)
{
struct rtc_device *rtc = data;
rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF | RTC_PF);
return IRQ_HANDLED;
}
static int bd70528_probe(struct platform_device *pdev)
{
struct bd70528_rtc *bd_rtc;
const struct rtc_class_ops *rtc_ops;
const char *irq_name;
int ret;
struct rtc_device *rtc;
int irq;
unsigned int hr;
u8 hour_reg;
enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;
bd_rtc = devm_kzalloc(&pdev->dev, sizeof(*bd_rtc), GFP_KERNEL);
if (!bd_rtc)
return -ENOMEM;
bd_rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!bd_rtc->regmap) {
dev_err(&pdev->dev, "No regmap\n");
return -EINVAL;
}
bd_rtc->dev = &pdev->dev;
rtc_ops = &bd71828_rtc_ops;
switch (chip) {
case ROHM_CHIP_TYPE_BD71815:
irq_name = "bd71815-rtc-alm-0";
bd_rtc->reg_time_start = BD71815_REG_RTC_START;
/*
* See also BD718XX_ALM_EN_OFFSET:
* This works for BD71828 and BD71815 as they have same offset
* between ALM0 start and ALM0_MASK. If new ICs are to be
* added this requires proper check as ALM0_MASK is not located
* at the end of ALM0 block - but after all ALM blocks so if
* amount of ALMs differ the offset to enable/disable is likely
* to be incorrect and enable/disable must be given as own
* reg address here.
*/
bd_rtc->bd718xx_alm_block_start = BD71815_REG_RTC_ALM_START;
hour_reg = BD71815_REG_HOUR;
break;
case ROHM_CHIP_TYPE_BD71828:
irq_name = "bd71828-rtc-alm-0";
bd_rtc->reg_time_start = BD71828_REG_RTC_START;
bd_rtc->bd718xx_alm_block_start = BD71828_REG_RTC_ALM_START;
hour_reg = BD71828_REG_RTC_HOUR;
break;
default:
dev_err(&pdev->dev, "Unknown chip\n");
return -ENOENT;
}
irq = platform_get_irq_byname(pdev, irq_name);
if (irq < 0)
return irq;
platform_set_drvdata(pdev, bd_rtc);
ret = regmap_read(bd_rtc->regmap, hour_reg, &hr);
if (ret) {
dev_err(&pdev->dev, "Failed to reag RTC clock\n");
return ret;
}
if (!(hr & BD70528_MASK_RTC_HOUR_24H)) {
struct rtc_time t;
ret = rtc_ops->read_time(&pdev->dev, &t);
if (!ret)
ret = rtc_ops->set_time(&pdev->dev, &t);
if (ret) {
dev_err(&pdev->dev,
"Setting 24H clock for RTC failed\n");
return ret;
}
}
device_set_wakeup_capable(&pdev->dev, true);
device_wakeup_enable(&pdev->dev);
rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc)) {
dev_err(&pdev->dev, "RTC device creation failed\n");
return PTR_ERR(rtc);
}
rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc->range_max = RTC_TIMESTAMP_END_2099;
rtc->ops = rtc_ops;
/* Request alarm IRQ prior to registerig the RTC */
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, &alm_hndlr,
IRQF_ONESHOT, "bd70528-rtc", rtc);
if (ret)
return ret;
return devm_rtc_register_device(rtc);
}
static const struct platform_device_id bd718x7_rtc_id[] = {
{ "bd71828-rtc", ROHM_CHIP_TYPE_BD71828 },
{ "bd71815-rtc", ROHM_CHIP_TYPE_BD71815 },
{ },
};
MODULE_DEVICE_TABLE(platform, bd718x7_rtc_id);
static struct platform_driver bd70528_rtc = {
.driver = {
.name = "bd70528-rtc"
},
.probe = bd70528_probe,
.id_table = bd718x7_rtc_id,
};
module_platform_driver(bd70528_rtc);
MODULE_AUTHOR("Matti Vaittinen <[email protected]>");
MODULE_DESCRIPTION("ROHM BD71828 and BD71815 PMIC RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd70528-rtc");
| linux-master | drivers/rtc/rtc-bd70528.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
*
* Copyright (C) 2008 David Brownell
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <linux/spi/ds1305.h>
#include <linux/module.h>
/*
* Registers ... mask DS1305_WRITE into register address to write,
* otherwise you're reading it. All non-bitmask values are BCD.
*/
#define DS1305_WRITE 0x80
/* RTC date/time ... the main special cases are that we:
* - Need fancy "hours" encoding in 12hour mode
* - Don't rely on the "day-of-week" field (or tm_wday)
* - Are a 21st-century clock (2000 <= year < 2100)
*/
#define DS1305_RTC_LEN 7 /* bytes for RTC regs */
#define DS1305_SEC 0x00 /* register addresses */
#define DS1305_MIN 0x01
#define DS1305_HOUR 0x02
# define DS1305_HR_12 0x40 /* set == 12 hr mode */
# define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
#define DS1305_WDAY 0x03
#define DS1305_MDAY 0x04
#define DS1305_MON 0x05
#define DS1305_YEAR 0x06
/* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
* DS1305_ALM_DISABLE disables a match field (some combos are bad).
*
* NOTE that since we don't use WDAY, we limit ourselves to alarms
* only one day into the future (vs potentially up to a week).
*
* NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
* don't currently support them. We'd either need to do it only when
* no alarm is pending (not the standard model), or to use the second
* alarm (implying that this is a DS1305 not DS1306, *and* that either
* it's wired up a second IRQ we know, or that INTCN is set)
*/
#define DS1305_ALM_LEN 4 /* bytes for ALM regs */
#define DS1305_ALM_DISABLE 0x80
#define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
#define DS1305_ALM1(r) (0x0b + (r))
/* three control registers */
#define DS1305_CONTROL_LEN 3 /* bytes of control regs */
#define DS1305_CONTROL 0x0f /* register addresses */
# define DS1305_nEOSC 0x80 /* low enables oscillator */
# define DS1305_WP 0x40 /* write protect */
# define DS1305_INTCN 0x04 /* clear == only int0 used */
# define DS1306_1HZ 0x04 /* enable 1Hz output */
# define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
# define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
#define DS1305_STATUS 0x10
/* status has just AEIx bits, mirrored as IRQFx */
#define DS1305_TRICKLE 0x11
/* trickle bits are defined in <linux/spi/ds1305.h> */
/* a bunch of NVRAM */
#define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
#define DS1305_NVRAM 0x20 /* register addresses */
struct ds1305 {
struct spi_device *spi;
struct rtc_device *rtc;
struct work_struct work;
unsigned long flags;
#define FLAG_EXITING 0
bool hr12;
u8 ctrl[DS1305_CONTROL_LEN];
};
/*----------------------------------------------------------------------*/
/*
* Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
* software (like a bootloader) which may require it.
*/
static unsigned bcd2hour(u8 bcd)
{
if (bcd & DS1305_HR_12) {
unsigned hour = 0;
bcd &= ~DS1305_HR_12;
if (bcd & DS1305_HR_PM) {
hour = 12;
bcd &= ~DS1305_HR_PM;
}
hour += bcd2bin(bcd);
return hour - 1;
}
return bcd2bin(bcd);
}
static u8 hour2bcd(bool hr12, int hour)
{
if (hr12) {
hour++;
if (hour <= 12)
return DS1305_HR_12 | bin2bcd(hour);
hour -= 12;
return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
}
return bin2bcd(hour);
}
/*----------------------------------------------------------------------*/
/*
* Interface to RTC framework
*/
static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct ds1305 *ds1305 = dev_get_drvdata(dev);
u8 buf[2];
long err = -EINVAL;
buf[0] = DS1305_WRITE | DS1305_CONTROL;
buf[1] = ds1305->ctrl[0];
if (enabled) {
if (ds1305->ctrl[0] & DS1305_AEI0)
goto done;
buf[1] |= DS1305_AEI0;
} else {
if (!(buf[1] & DS1305_AEI0))
goto done;
buf[1] &= ~DS1305_AEI0;
}
err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
if (err >= 0)
ds1305->ctrl[0] = buf[1];
done:
return err;
}
/*
* Get/set of date and time is pretty normal.
*/
static int ds1305_get_time(struct device *dev, struct rtc_time *time)
{
struct ds1305 *ds1305 = dev_get_drvdata(dev);
u8 addr = DS1305_SEC;
u8 buf[DS1305_RTC_LEN];
int status;
/* Use write-then-read to get all the date/time registers
* since dma from stack is nonportable
*/
status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
buf, sizeof(buf));
if (status < 0)
return status;
dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
/* Decode the registers */
time->tm_sec = bcd2bin(buf[DS1305_SEC]);
time->tm_min = bcd2bin(buf[DS1305_MIN]);
time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
time->tm_wday = buf[DS1305_WDAY] - 1;
time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
dev_vdbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"read", time->tm_sec, time->tm_min,
time->tm_hour, time->tm_mday,
time->tm_mon, time->tm_year, time->tm_wday);
return 0;
}
static int ds1305_set_time(struct device *dev, struct rtc_time *time)
{
struct ds1305 *ds1305 = dev_get_drvdata(dev);
u8 buf[1 + DS1305_RTC_LEN];
u8 *bp = buf;
dev_vdbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"write", time->tm_sec, time->tm_min,
time->tm_hour, time->tm_mday,
time->tm_mon, time->tm_year, time->tm_wday);
/* Write registers starting at the first time/date address. */
*bp++ = DS1305_WRITE | DS1305_SEC;
*bp++ = bin2bcd(time->tm_sec);
*bp++ = bin2bcd(time->tm_min);
*bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
*bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
*bp++ = bin2bcd(time->tm_mday);
*bp++ = bin2bcd(time->tm_mon + 1);
*bp++ = bin2bcd(time->tm_year - 100);
dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
/* use write-then-read since dma from stack is nonportable */
return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
NULL, 0);
}
/*
* Get/set of alarm is a bit funky:
*
* - First there's the inherent raciness of getting the (partitioned)
* status of an alarm that could trigger while we're reading parts
* of that status.
*
* - Second there's its limited range (we could increase it a bit by
* relying on WDAY), which means it will easily roll over.
*
* - Third there's the choice of two alarms and alarm signals.
* Here we use ALM0 and expect that nINT0 (open drain) is used;
* that's the only real option for DS1306 runtime alarms, and is
* natural on DS1305.
*
* - Fourth, there's also ALM1, and a second interrupt signal:
* + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
* + On DS1306 ALM1 only uses INT1 (an active high pulse)
* and it won't work when VCC1 is active.
*
* So to be most general, we should probably set both alarms to the
* same value, letting ALM1 be the wakeup event source on DS1306
* and handling several wiring options on DS1305.
*
* - Fifth, we support the polled mode (as well as possible; why not?)
* even when no interrupt line is wired to an IRQ.
*/
/*
* Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
*/
static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct ds1305 *ds1305 = dev_get_drvdata(dev);
struct spi_device *spi = ds1305->spi;
u8 addr;
int status;
u8 buf[DS1305_ALM_LEN];
/* Refresh control register cache BEFORE reading ALM0 registers,
* since reading alarm registers acks any pending IRQ. That
* makes returning "pending" status a bit of a lie, but that bit
* of EFI status is at best fragile anyway (given IRQ handlers).
*/
addr = DS1305_CONTROL;
status = spi_write_then_read(spi, &addr, sizeof(addr),
ds1305->ctrl, sizeof(ds1305->ctrl));
if (status < 0)
return status;
alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
/* get and check ALM0 registers */
addr = DS1305_ALM0(DS1305_SEC);
status = spi_write_then_read(spi, &addr, sizeof(addr),
buf, sizeof(buf));
if (status < 0)
return status;
dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
"alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
buf[DS1305_HOUR], buf[DS1305_WDAY]);
if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
|| (DS1305_ALM_DISABLE & buf[DS1305_MIN])
|| (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
return -EIO;
/* Stuff these values into alm->time and let RTC framework code
* fill in the rest ... and also handle rollover to tomorrow when
* that's needed.
*/
alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
return 0;
}
/*
* Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
*/
static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct ds1305 *ds1305 = dev_get_drvdata(dev);
struct spi_device *spi = ds1305->spi;
unsigned long now, later;
struct rtc_time tm;
int status;
u8 buf[1 + DS1305_ALM_LEN];
/* convert desired alarm to time_t */
later = rtc_tm_to_time64(&alm->time);
/* Read current time as time_t */
status = ds1305_get_time(dev, &tm);
if (status < 0)
return status;
now = rtc_tm_to_time64(&tm);
/* make sure alarm fires within the next 24 hours */
if (later <= now)
return -EINVAL;
if ((later - now) > ds1305->rtc->alarm_offset_max)
return -ERANGE;
/* disable alarm if needed */
if (ds1305->ctrl[0] & DS1305_AEI0) {
ds1305->ctrl[0] &= ~DS1305_AEI0;
buf[0] = DS1305_WRITE | DS1305_CONTROL;
buf[1] = ds1305->ctrl[0];
status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
if (status < 0)
return status;
}
/* write alarm */
buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
"alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
if (status < 0)
return status;
/* enable alarm if requested */
if (alm->enabled) {
ds1305->ctrl[0] |= DS1305_AEI0;
buf[0] = DS1305_WRITE | DS1305_CONTROL;
buf[1] = ds1305->ctrl[0];
status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
}
return status;
}
#ifdef CONFIG_PROC_FS
static int ds1305_proc(struct device *dev, struct seq_file *seq)
{
struct ds1305 *ds1305 = dev_get_drvdata(dev);
char *diodes = "no";
char *resistors = "";
/* ctrl[2] is treated as read-only; no locking needed */
if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
switch (ds1305->ctrl[2] & 0x0c) {
case DS1305_TRICKLE_DS2:
diodes = "2 diodes, ";
break;
case DS1305_TRICKLE_DS1:
diodes = "1 diode, ";
break;
default:
goto done;
}
switch (ds1305->ctrl[2] & 0x03) {
case DS1305_TRICKLE_2K:
resistors = "2k Ohm";
break;
case DS1305_TRICKLE_4K:
resistors = "4k Ohm";
break;
case DS1305_TRICKLE_8K:
resistors = "8k Ohm";
break;
default:
diodes = "no";
break;
}
}
done:
seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
return 0;
}
#else
#define ds1305_proc NULL
#endif
static const struct rtc_class_ops ds1305_ops = {
.read_time = ds1305_get_time,
.set_time = ds1305_set_time,
.read_alarm = ds1305_get_alarm,
.set_alarm = ds1305_set_alarm,
.proc = ds1305_proc,
.alarm_irq_enable = ds1305_alarm_irq_enable,
};
static void ds1305_work(struct work_struct *work)
{
struct ds1305 *ds1305 = container_of(work, struct ds1305, work);
struct spi_device *spi = ds1305->spi;
u8 buf[3];
int status;
/* lock to protect ds1305->ctrl */
rtc_lock(ds1305->rtc);
/* Disable the IRQ, and clear its status ... for now, we "know"
* that if more than one alarm is active, they're in sync.
* Note that reading ALM data registers also clears IRQ status.
*/
ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
ds1305->ctrl[1] = 0;
buf[0] = DS1305_WRITE | DS1305_CONTROL;
buf[1] = ds1305->ctrl[0];
buf[2] = 0;
status = spi_write_then_read(spi, buf, sizeof(buf),
NULL, 0);
if (status < 0)
dev_dbg(&spi->dev, "clear irq --> %d\n", status);
rtc_unlock(ds1305->rtc);
if (!test_bit(FLAG_EXITING, &ds1305->flags))
enable_irq(spi->irq);
rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
}
/*
* This "real" IRQ handler hands off to a workqueue mostly to allow
* mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
* I/O requests in IRQ context (to clear the IRQ status).
*/
static irqreturn_t ds1305_irq(int irq, void *p)
{
struct ds1305 *ds1305 = p;
disable_irq(irq);
schedule_work(&ds1305->work);
return IRQ_HANDLED;
}
/*----------------------------------------------------------------------*/
/*
* Interface for NVRAM
*/
static void msg_init(struct spi_message *m, struct spi_transfer *x,
u8 *addr, size_t count, char *tx, char *rx)
{
spi_message_init(m);
memset(x, 0, 2 * sizeof(*x));
x->tx_buf = addr;
x->len = 1;
spi_message_add_tail(x, m);
x++;
x->tx_buf = tx;
x->rx_buf = rx;
x->len = count;
spi_message_add_tail(x, m);
}
static int ds1305_nvram_read(void *priv, unsigned int off, void *buf,
size_t count)
{
struct ds1305 *ds1305 = priv;
struct spi_device *spi = ds1305->spi;
u8 addr;
struct spi_message m;
struct spi_transfer x[2];
addr = DS1305_NVRAM + off;
msg_init(&m, x, &addr, count, NULL, buf);
return spi_sync(spi, &m);
}
static int ds1305_nvram_write(void *priv, unsigned int off, void *buf,
size_t count)
{
struct ds1305 *ds1305 = priv;
struct spi_device *spi = ds1305->spi;
u8 addr;
struct spi_message m;
struct spi_transfer x[2];
addr = (DS1305_WRITE | DS1305_NVRAM) + off;
msg_init(&m, x, &addr, count, buf, NULL);
return spi_sync(spi, &m);
}
/*----------------------------------------------------------------------*/
/*
* Interface to SPI stack
*/
static int ds1305_probe(struct spi_device *spi)
{
struct ds1305 *ds1305;
int status;
u8 addr, value;
struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev);
bool write_ctrl = false;
struct nvmem_config ds1305_nvmem_cfg = {
.name = "ds1305_nvram",
.word_size = 1,
.stride = 1,
.size = DS1305_NVRAM_LEN,
.reg_read = ds1305_nvram_read,
.reg_write = ds1305_nvram_write,
};
/* Sanity check board setup data. This may be hooked up
* in 3wire mode, but we don't care. Note that unless
* there's an inverter in place, this needs SPI_CS_HIGH!
*/
if ((spi->bits_per_word && spi->bits_per_word != 8)
|| (spi->max_speed_hz > 2000000)
|| !(spi->mode & SPI_CPHA))
return -EINVAL;
/* set up driver data */
ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
if (!ds1305)
return -ENOMEM;
ds1305->spi = spi;
spi_set_drvdata(spi, ds1305);
/* read and cache control registers */
addr = DS1305_CONTROL;
status = spi_write_then_read(spi, &addr, sizeof(addr),
ds1305->ctrl, sizeof(ds1305->ctrl));
if (status < 0) {
dev_dbg(&spi->dev, "can't %s, %d\n",
"read", status);
return status;
}
dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
/* Sanity check register values ... partially compensating for the
* fact that SPI has no device handshake. A pullup on MISO would
* make these tests fail; but not all systems will have one. If
* some register is neither 0x00 nor 0xff, a chip is likely there.
*/
if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
dev_dbg(&spi->dev, "RTC chip is not present\n");
return -ENODEV;
}
if (ds1305->ctrl[2] == 0)
dev_dbg(&spi->dev, "chip may not be present\n");
/* enable writes if needed ... if we were paranoid it would
* make sense to enable them only when absolutely necessary.
*/
if (ds1305->ctrl[0] & DS1305_WP) {
u8 buf[2];
ds1305->ctrl[0] &= ~DS1305_WP;
buf[0] = DS1305_WRITE | DS1305_CONTROL;
buf[1] = ds1305->ctrl[0];
status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
dev_dbg(&spi->dev, "clear WP --> %d\n", status);
if (status < 0)
return status;
}
/* on DS1305, maybe start oscillator; like most low power
* oscillators, it may take a second to stabilize
*/
if (ds1305->ctrl[0] & DS1305_nEOSC) {
ds1305->ctrl[0] &= ~DS1305_nEOSC;
write_ctrl = true;
dev_warn(&spi->dev, "SET TIME!\n");
}
/* ack any pending IRQs */
if (ds1305->ctrl[1]) {
ds1305->ctrl[1] = 0;
write_ctrl = true;
}
/* this may need one-time (re)init */
if (pdata) {
/* maybe enable trickle charge */
if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
| pdata->trickle;
write_ctrl = true;
}
/* on DS1306, configure 1 Hz signal */
if (pdata->is_ds1306) {
if (pdata->en_1hz) {
if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
ds1305->ctrl[0] |= DS1306_1HZ;
write_ctrl = true;
}
} else {
if (ds1305->ctrl[0] & DS1306_1HZ) {
ds1305->ctrl[0] &= ~DS1306_1HZ;
write_ctrl = true;
}
}
}
}
if (write_ctrl) {
u8 buf[4];
buf[0] = DS1305_WRITE | DS1305_CONTROL;
buf[1] = ds1305->ctrl[0];
buf[2] = ds1305->ctrl[1];
buf[3] = ds1305->ctrl[2];
status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
if (status < 0) {
dev_dbg(&spi->dev, "can't %s, %d\n",
"write", status);
return status;
}
dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
}
/* see if non-Linux software set up AM/PM mode */
addr = DS1305_HOUR;
status = spi_write_then_read(spi, &addr, sizeof(addr),
&value, sizeof(value));
if (status < 0) {
dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
return status;
}
ds1305->hr12 = (DS1305_HR_12 & value) != 0;
if (ds1305->hr12)
dev_dbg(&spi->dev, "AM/PM\n");
/* register RTC ... from here on, ds1305->ctrl needs locking */
ds1305->rtc = devm_rtc_allocate_device(&spi->dev);
if (IS_ERR(ds1305->rtc))
return PTR_ERR(ds1305->rtc);
ds1305->rtc->ops = &ds1305_ops;
ds1305->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
ds1305->rtc->range_max = RTC_TIMESTAMP_END_2099;
ds1305->rtc->alarm_offset_max = 24 * 60 * 60;
ds1305_nvmem_cfg.priv = ds1305;
status = devm_rtc_register_device(ds1305->rtc);
if (status)
return status;
devm_rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg);
/* Maybe set up alarm IRQ; be ready to handle it triggering right
* away. NOTE that we don't share this. The signal is active low,
* and we can't ack it before a SPI message delay. We temporarily
* disable the IRQ until it's acked, which lets us work with more
* IRQ trigger modes (not all IRQ controllers can do falling edge).
*/
if (spi->irq) {
INIT_WORK(&ds1305->work, ds1305_work);
status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
0, dev_name(&ds1305->rtc->dev), ds1305);
if (status < 0) {
dev_err(&spi->dev, "request_irq %d --> %d\n",
spi->irq, status);
} else {
device_set_wakeup_capable(&spi->dev, 1);
}
}
return 0;
}
static void ds1305_remove(struct spi_device *spi)
{
struct ds1305 *ds1305 = spi_get_drvdata(spi);
/* carefully shut down irq and workqueue, if present */
if (spi->irq) {
set_bit(FLAG_EXITING, &ds1305->flags);
devm_free_irq(&spi->dev, spi->irq, ds1305);
cancel_work_sync(&ds1305->work);
}
}
static struct spi_driver ds1305_driver = {
.driver.name = "rtc-ds1305",
.probe = ds1305_probe,
.remove = ds1305_remove,
/* REVISIT add suspend/resume */
};
module_spi_driver(ds1305_driver);
MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rtc-ds1305");
| linux-master | drivers/rtc/rtc-ds1305.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rtc-ds1390.c -- driver for the Dallas/Maxim DS1390/93/94 SPI RTC
*
* Copyright (C) 2008 Mercury IMC Ltd
* Written by Mark Jackson <[email protected]>
*
* NOTE: Currently this driver only supports the bare minimum for read
* and write the RTC. The extra features provided by the chip family
* (alarms, trickle charger, different control registers) are unavailable.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#include <linux/of.h>
#define DS1390_REG_100THS 0x00
#define DS1390_REG_SECONDS 0x01
#define DS1390_REG_MINUTES 0x02
#define DS1390_REG_HOURS 0x03
#define DS1390_REG_DAY 0x04
#define DS1390_REG_DATE 0x05
#define DS1390_REG_MONTH_CENT 0x06
#define DS1390_REG_YEAR 0x07
#define DS1390_REG_ALARM_100THS 0x08
#define DS1390_REG_ALARM_SECONDS 0x09
#define DS1390_REG_ALARM_MINUTES 0x0A
#define DS1390_REG_ALARM_HOURS 0x0B
#define DS1390_REG_ALARM_DAY_DATE 0x0C
#define DS1390_REG_CONTROL 0x0D
#define DS1390_REG_STATUS 0x0E
#define DS1390_REG_TRICKLE 0x0F
#define DS1390_TRICKLE_CHARGER_ENABLE 0xA0
#define DS1390_TRICKLE_CHARGER_250_OHM 0x01
#define DS1390_TRICKLE_CHARGER_2K_OHM 0x02
#define DS1390_TRICKLE_CHARGER_4K_OHM 0x03
#define DS1390_TRICKLE_CHARGER_NO_DIODE 0x04
#define DS1390_TRICKLE_CHARGER_DIODE 0x08
struct ds1390 {
struct rtc_device *rtc;
u8 txrx_buf[9]; /* cmd + 8 registers */
};
static void ds1390_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* MSB must be '1' to write */
buf[0] = address | 0x80;
buf[1] = data;
spi_write(spi, buf, 2);
}
static int ds1390_get_reg(struct device *dev, unsigned char address,
unsigned char *data)
{
struct spi_device *spi = to_spi_device(dev);
struct ds1390 *chip = dev_get_drvdata(dev);
int status;
if (!data)
return -EINVAL;
/* Clear MSB to indicate read */
chip->txrx_buf[0] = address & 0x7f;
/* do the i/o */
status = spi_write_then_read(spi, chip->txrx_buf, 1, chip->txrx_buf, 1);
if (status != 0)
return status;
*data = chip->txrx_buf[0];
return 0;
}
static void ds1390_trickle_of_init(struct spi_device *spi)
{
u32 ohms = 0;
u8 value;
if (of_property_read_u32(spi->dev.of_node, "trickle-resistor-ohms",
&ohms))
goto out;
/* Enable charger */
value = DS1390_TRICKLE_CHARGER_ENABLE;
if (of_property_read_bool(spi->dev.of_node, "trickle-diode-disable"))
value |= DS1390_TRICKLE_CHARGER_NO_DIODE;
else
value |= DS1390_TRICKLE_CHARGER_DIODE;
/* Resistor select */
switch (ohms) {
case 250:
value |= DS1390_TRICKLE_CHARGER_250_OHM;
break;
case 2000:
value |= DS1390_TRICKLE_CHARGER_2K_OHM;
break;
case 4000:
value |= DS1390_TRICKLE_CHARGER_4K_OHM;
break;
default:
dev_warn(&spi->dev,
"Unsupported ohm value %02ux in dt\n", ohms);
return;
}
ds1390_set_reg(&spi->dev, DS1390_REG_TRICKLE, value);
out:
return;
}
static int ds1390_read_time(struct device *dev, struct rtc_time *dt)
{
struct spi_device *spi = to_spi_device(dev);
struct ds1390 *chip = dev_get_drvdata(dev);
int status;
/* build the message */
chip->txrx_buf[0] = DS1390_REG_SECONDS;
/* do the i/o */
status = spi_write_then_read(spi, chip->txrx_buf, 1, chip->txrx_buf, 8);
if (status != 0)
return status;
/* The chip sends data in this order:
* Seconds, Minutes, Hours, Day, Date, Month / Century, Year */
dt->tm_sec = bcd2bin(chip->txrx_buf[0]);
dt->tm_min = bcd2bin(chip->txrx_buf[1]);
dt->tm_hour = bcd2bin(chip->txrx_buf[2]);
dt->tm_wday = bcd2bin(chip->txrx_buf[3]);
dt->tm_mday = bcd2bin(chip->txrx_buf[4]);
/* mask off century bit */
dt->tm_mon = bcd2bin(chip->txrx_buf[5] & 0x7f) - 1;
/* adjust for century bit */
dt->tm_year = bcd2bin(chip->txrx_buf[6]) + ((chip->txrx_buf[5] & 0x80) ? 100 : 0);
return 0;
}
static int ds1390_set_time(struct device *dev, struct rtc_time *dt)
{
struct spi_device *spi = to_spi_device(dev);
struct ds1390 *chip = dev_get_drvdata(dev);
/* build the message */
chip->txrx_buf[0] = DS1390_REG_SECONDS | 0x80;
chip->txrx_buf[1] = bin2bcd(dt->tm_sec);
chip->txrx_buf[2] = bin2bcd(dt->tm_min);
chip->txrx_buf[3] = bin2bcd(dt->tm_hour);
chip->txrx_buf[4] = bin2bcd(dt->tm_wday);
chip->txrx_buf[5] = bin2bcd(dt->tm_mday);
chip->txrx_buf[6] = bin2bcd(dt->tm_mon + 1) |
((dt->tm_year > 99) ? 0x80 : 0x00);
chip->txrx_buf[7] = bin2bcd(dt->tm_year % 100);
/* do the i/o */
return spi_write_then_read(spi, chip->txrx_buf, 8, NULL, 0);
}
static const struct rtc_class_ops ds1390_rtc_ops = {
.read_time = ds1390_read_time,
.set_time = ds1390_set_time,
};
static int ds1390_probe(struct spi_device *spi)
{
unsigned char tmp;
struct ds1390 *chip;
int res;
spi->mode = SPI_MODE_3;
spi->bits_per_word = 8;
spi_setup(spi);
chip = devm_kzalloc(&spi->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
spi_set_drvdata(spi, chip);
res = ds1390_get_reg(&spi->dev, DS1390_REG_SECONDS, &tmp);
if (res != 0) {
dev_err(&spi->dev, "unable to read device\n");
return res;
}
if (spi->dev.of_node)
ds1390_trickle_of_init(spi);
chip->rtc = devm_rtc_device_register(&spi->dev, "ds1390",
&ds1390_rtc_ops, THIS_MODULE);
if (IS_ERR(chip->rtc)) {
dev_err(&spi->dev, "unable to register device\n");
res = PTR_ERR(chip->rtc);
}
return res;
}
static const struct of_device_id ds1390_of_match[] __maybe_unused = {
{ .compatible = "dallas,ds1390" },
{}
};
MODULE_DEVICE_TABLE(of, ds1390_of_match);
static const struct spi_device_id ds1390_spi_ids[] = {
{ .name = "ds1390" },
{}
};
MODULE_DEVICE_TABLE(spi, ds1390_spi_ids);
static struct spi_driver ds1390_driver = {
.driver = {
.name = "rtc-ds1390",
.of_match_table = of_match_ptr(ds1390_of_match),
},
.probe = ds1390_probe,
.id_table = ds1390_spi_ids,
};
module_spi_driver(ds1390_driver);
MODULE_DESCRIPTION("Dallas/Maxim DS1390/93/94 SPI RTC driver");
MODULE_AUTHOR("Mark Jackson <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rtc-ds1390");
| linux-master | drivers/rtc/rtc-ds1390.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An rtc driver for the Dallas DS1742
*
* Copyright (C) 2006 Atsushi Nemoto <[email protected]>
*
* Copyright (C) 2006 Torsten Ertbjerg Rasmussen <[email protected]>
* - nvram size determined from resource
* - this ds1742 driver now supports ds1743.
*/
#include <linux/bcd.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/rtc.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>
#define RTC_SIZE 8
#define RTC_CONTROL 0
#define RTC_CENTURY 0
#define RTC_SECONDS 1
#define RTC_MINUTES 2
#define RTC_HOURS 3
#define RTC_DAY 4
#define RTC_DATE 5
#define RTC_MONTH 6
#define RTC_YEAR 7
#define RTC_CENTURY_MASK 0x3f
#define RTC_SECONDS_MASK 0x7f
#define RTC_DAY_MASK 0x07
/* Bits in the Control/Century register */
#define RTC_WRITE 0x80
#define RTC_READ 0x40
/* Bits in the Seconds register */
#define RTC_STOP 0x80
/* Bits in the Day register */
#define RTC_BATT_FLAG 0x80
struct rtc_plat_data {
void __iomem *ioaddr_nvram;
void __iomem *ioaddr_rtc;
unsigned long last_jiffies;
};
static int ds1742_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr_rtc;
u8 century;
century = bin2bcd((tm->tm_year + 1900) / 100);
writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR);
writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH);
writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY);
writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE);
writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS);
writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES);
writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS);
/* RTC_CENTURY and RTC_CONTROL share same register */
writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr + RTC_CENTURY);
writeb(century & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
return 0;
}
static int ds1742_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr_rtc;
unsigned int year, month, day, hour, minute, second, week;
unsigned int century;
/* give enough time to update RTC in case of continuous read */
if (pdata->last_jiffies == jiffies)
msleep(1);
pdata->last_jiffies = jiffies;
writeb(RTC_READ, ioaddr + RTC_CONTROL);
second = readb(ioaddr + RTC_SECONDS) & RTC_SECONDS_MASK;
minute = readb(ioaddr + RTC_MINUTES);
hour = readb(ioaddr + RTC_HOURS);
day = readb(ioaddr + RTC_DATE);
week = readb(ioaddr + RTC_DAY) & RTC_DAY_MASK;
month = readb(ioaddr + RTC_MONTH);
year = readb(ioaddr + RTC_YEAR);
century = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
writeb(0, ioaddr + RTC_CONTROL);
tm->tm_sec = bcd2bin(second);
tm->tm_min = bcd2bin(minute);
tm->tm_hour = bcd2bin(hour);
tm->tm_mday = bcd2bin(day);
tm->tm_wday = bcd2bin(week);
tm->tm_mon = bcd2bin(month) - 1;
/* year is 1900 + tm->tm_year */
tm->tm_year = bcd2bin(year) + bcd2bin(century) * 100 - 1900;
return 0;
}
static const struct rtc_class_ops ds1742_rtc_ops = {
.read_time = ds1742_rtc_read_time,
.set_time = ds1742_rtc_set_time,
};
static int ds1742_nvram_read(void *priv, unsigned int pos, void *val,
size_t bytes)
{
struct rtc_plat_data *pdata = priv;
void __iomem *ioaddr = pdata->ioaddr_nvram;
u8 *buf = val;
for (; bytes; bytes--)
*buf++ = readb(ioaddr + pos++);
return 0;
}
static int ds1742_nvram_write(void *priv, unsigned int pos, void *val,
size_t bytes)
{
struct rtc_plat_data *pdata = priv;
void __iomem *ioaddr = pdata->ioaddr_nvram;
u8 *buf = val;
for (; bytes; bytes--)
writeb(*buf++, ioaddr + pos++);
return 0;
}
static int ds1742_rtc_probe(struct platform_device *pdev)
{
struct rtc_device *rtc;
struct resource *res;
unsigned int cen, sec;
struct rtc_plat_data *pdata;
void __iomem *ioaddr;
int ret = 0;
struct nvmem_config nvmem_cfg = {
.name = "ds1742_nvram",
.reg_read = ds1742_nvram_read,
.reg_write = ds1742_nvram_write,
};
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
ioaddr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(ioaddr))
return PTR_ERR(ioaddr);
pdata->ioaddr_nvram = ioaddr;
pdata->ioaddr_rtc = ioaddr + resource_size(res) - RTC_SIZE;
nvmem_cfg.size = resource_size(res) - RTC_SIZE;
nvmem_cfg.priv = pdata;
/* turn RTC on if it was not on */
ioaddr = pdata->ioaddr_rtc;
sec = readb(ioaddr + RTC_SECONDS);
if (sec & RTC_STOP) {
sec &= RTC_SECONDS_MASK;
cen = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
writeb(sec, ioaddr + RTC_SECONDS);
writeb(cen & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
}
if (!(readb(ioaddr + RTC_DAY) & RTC_BATT_FLAG))
dev_warn(&pdev->dev, "voltage-low detected.\n");
pdata->last_jiffies = jiffies;
platform_set_drvdata(pdev, pdata);
rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &ds1742_rtc_ops;
ret = devm_rtc_register_device(rtc);
if (ret)
return ret;
devm_rtc_nvmem_register(rtc, &nvmem_cfg);
return 0;
}
static const struct of_device_id __maybe_unused ds1742_rtc_of_match[] = {
{ .compatible = "maxim,ds1742", },
{ }
};
MODULE_DEVICE_TABLE(of, ds1742_rtc_of_match);
static struct platform_driver ds1742_rtc_driver = {
.probe = ds1742_rtc_probe,
.driver = {
.name = "rtc-ds1742",
.of_match_table = of_match_ptr(ds1742_rtc_of_match),
},
};
module_platform_driver(ds1742_rtc_driver);
MODULE_AUTHOR("Atsushi Nemoto <[email protected]>");
MODULE_DESCRIPTION("Dallas DS1742 RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-ds1742");
| linux-master | drivers/rtc/rtc-ds1742.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Real time clock driver for DA9052
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: Dajun Dajun Chen <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/mfd/da9052/da9052.h>
#include <linux/mfd/da9052/reg.h>
#define rtc_err(rtc, fmt, ...) \
dev_err(rtc->da9052->dev, "%s: " fmt, __func__, ##__VA_ARGS__)
#define DA9052_GET_TIME_RETRIES 5
struct da9052_rtc {
struct rtc_device *rtc;
struct da9052 *da9052;
};
static int da9052_rtc_enable_alarm(struct da9052_rtc *rtc, bool enable)
{
int ret;
if (enable) {
ret = da9052_reg_update(rtc->da9052, DA9052_ALARM_Y_REG,
DA9052_ALARM_Y_ALARM_ON|DA9052_ALARM_Y_TICK_ON,
DA9052_ALARM_Y_ALARM_ON);
if (ret != 0)
rtc_err(rtc, "Failed to enable ALM: %d\n", ret);
} else {
ret = da9052_reg_update(rtc->da9052, DA9052_ALARM_Y_REG,
DA9052_ALARM_Y_ALARM_ON|DA9052_ALARM_Y_TICK_ON, 0);
if (ret != 0)
rtc_err(rtc, "Write error: %d\n", ret);
}
return ret;
}
static irqreturn_t da9052_rtc_irq(int irq, void *data)
{
struct da9052_rtc *rtc = data;
rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static int da9052_read_alarm(struct da9052_rtc *rtc, struct rtc_time *rtc_tm)
{
int ret;
uint8_t v[2][5];
int idx = 1;
int timeout = DA9052_GET_TIME_RETRIES;
ret = da9052_group_read(rtc->da9052, DA9052_ALARM_MI_REG, 5, &v[0][0]);
if (ret) {
rtc_err(rtc, "Failed to group read ALM: %d\n", ret);
return ret;
}
do {
ret = da9052_group_read(rtc->da9052,
DA9052_ALARM_MI_REG, 5, &v[idx][0]);
if (ret) {
rtc_err(rtc, "Failed to group read ALM: %d\n", ret);
return ret;
}
if (memcmp(&v[0][0], &v[1][0], 5) == 0) {
rtc_tm->tm_year = (v[0][4] & DA9052_RTC_YEAR) + 100;
rtc_tm->tm_mon = (v[0][3] & DA9052_RTC_MONTH) - 1;
rtc_tm->tm_mday = v[0][2] & DA9052_RTC_DAY;
rtc_tm->tm_hour = v[0][1] & DA9052_RTC_HOUR;
rtc_tm->tm_min = v[0][0] & DA9052_RTC_MIN;
rtc_tm->tm_sec = 0;
ret = rtc_valid_tm(rtc_tm);
return ret;
}
idx = (1-idx);
msleep(20);
} while (timeout--);
rtc_err(rtc, "Timed out reading alarm time\n");
return -EIO;
}
static int da9052_set_alarm(struct da9052_rtc *rtc, struct rtc_time *rtc_tm)
{
struct da9052 *da9052 = rtc->da9052;
unsigned long alm_time;
int ret;
uint8_t v[3];
alm_time = rtc_tm_to_time64(rtc_tm);
if (rtc_tm->tm_sec > 0) {
alm_time += 60 - rtc_tm->tm_sec;
rtc_time64_to_tm(alm_time, rtc_tm);
}
BUG_ON(rtc_tm->tm_sec); /* it will cause repeated irqs if not zero */
rtc_tm->tm_year -= 100;
rtc_tm->tm_mon += 1;
ret = da9052_reg_update(da9052, DA9052_ALARM_MI_REG,
DA9052_RTC_MIN, rtc_tm->tm_min);
if (ret != 0) {
rtc_err(rtc, "Failed to write ALRM MIN: %d\n", ret);
return ret;
}
v[0] = rtc_tm->tm_hour;
v[1] = rtc_tm->tm_mday;
v[2] = rtc_tm->tm_mon;
ret = da9052_group_write(da9052, DA9052_ALARM_H_REG, 3, v);
if (ret < 0)
return ret;
ret = da9052_reg_update(da9052, DA9052_ALARM_Y_REG,
DA9052_RTC_YEAR, rtc_tm->tm_year);
if (ret != 0)
rtc_err(rtc, "Failed to write ALRM YEAR: %d\n", ret);
return ret;
}
static int da9052_rtc_get_alarm_status(struct da9052_rtc *rtc)
{
int ret;
ret = da9052_reg_read(rtc->da9052, DA9052_ALARM_Y_REG);
if (ret < 0) {
rtc_err(rtc, "Failed to read ALM: %d\n", ret);
return ret;
}
return !!(ret&DA9052_ALARM_Y_ALARM_ON);
}
static int da9052_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
{
struct da9052_rtc *rtc = dev_get_drvdata(dev);
int ret;
uint8_t v[2][6];
int idx = 1;
int timeout = DA9052_GET_TIME_RETRIES;
ret = da9052_group_read(rtc->da9052, DA9052_COUNT_S_REG, 6, &v[0][0]);
if (ret) {
rtc_err(rtc, "Failed to read RTC time : %d\n", ret);
return ret;
}
do {
ret = da9052_group_read(rtc->da9052,
DA9052_COUNT_S_REG, 6, &v[idx][0]);
if (ret) {
rtc_err(rtc, "Failed to read RTC time : %d\n", ret);
return ret;
}
if (memcmp(&v[0][0], &v[1][0], 6) == 0) {
rtc_tm->tm_year = (v[0][5] & DA9052_RTC_YEAR) + 100;
rtc_tm->tm_mon = (v[0][4] & DA9052_RTC_MONTH) - 1;
rtc_tm->tm_mday = v[0][3] & DA9052_RTC_DAY;
rtc_tm->tm_hour = v[0][2] & DA9052_RTC_HOUR;
rtc_tm->tm_min = v[0][1] & DA9052_RTC_MIN;
rtc_tm->tm_sec = v[0][0] & DA9052_RTC_SEC;
return 0;
}
idx = (1-idx);
msleep(20);
} while (timeout--);
rtc_err(rtc, "Timed out reading time\n");
return -EIO;
}
static int da9052_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct da9052_rtc *rtc;
uint8_t v[6];
int ret;
/* DA9052 only has 6 bits for year - to represent 2000-2063 */
if ((tm->tm_year < 100) || (tm->tm_year > 163))
return -EINVAL;
rtc = dev_get_drvdata(dev);
v[0] = tm->tm_sec;
v[1] = tm->tm_min;
v[2] = tm->tm_hour;
v[3] = tm->tm_mday;
v[4] = tm->tm_mon + 1;
v[5] = tm->tm_year - 100;
ret = da9052_group_write(rtc->da9052, DA9052_COUNT_S_REG, 6, v);
if (ret < 0)
rtc_err(rtc, "failed to set RTC time: %d\n", ret);
return ret;
}
static int da9052_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
int ret;
struct rtc_time *tm = &alrm->time;
struct da9052_rtc *rtc = dev_get_drvdata(dev);
ret = da9052_read_alarm(rtc, tm);
if (ret < 0) {
rtc_err(rtc, "failed to read RTC alarm: %d\n", ret);
return ret;
}
alrm->enabled = da9052_rtc_get_alarm_status(rtc);
return 0;
}
static int da9052_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
int ret;
struct rtc_time *tm = &alrm->time;
struct da9052_rtc *rtc = dev_get_drvdata(dev);
/* DA9052 only has 6 bits for year - to represent 2000-2063 */
if ((tm->tm_year < 100) || (tm->tm_year > 163))
return -EINVAL;
ret = da9052_rtc_enable_alarm(rtc, 0);
if (ret < 0)
return ret;
ret = da9052_set_alarm(rtc, tm);
if (ret < 0)
return ret;
ret = da9052_rtc_enable_alarm(rtc, 1);
return ret;
}
static int da9052_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct da9052_rtc *rtc = dev_get_drvdata(dev);
return da9052_rtc_enable_alarm(rtc, enabled);
}
static const struct rtc_class_ops da9052_rtc_ops = {
.read_time = da9052_rtc_read_time,
.set_time = da9052_rtc_set_time,
.read_alarm = da9052_rtc_read_alarm,
.set_alarm = da9052_rtc_set_alarm,
.alarm_irq_enable = da9052_rtc_alarm_irq_enable,
};
static int da9052_rtc_probe(struct platform_device *pdev)
{
struct da9052_rtc *rtc;
int ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(struct da9052_rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->da9052 = dev_get_drvdata(pdev->dev.parent);
platform_set_drvdata(pdev, rtc);
ret = da9052_reg_write(rtc->da9052, DA9052_BBAT_CONT_REG, 0xFE);
if (ret < 0) {
rtc_err(rtc,
"Failed to setup RTC battery charging: %d\n", ret);
return ret;
}
ret = da9052_reg_update(rtc->da9052, DA9052_ALARM_Y_REG,
DA9052_ALARM_Y_TICK_ON, 0);
if (ret != 0)
rtc_err(rtc, "Failed to disable TICKS: %d\n", ret);
device_init_wakeup(&pdev->dev, true);
rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc))
return PTR_ERR(rtc->rtc);
rtc->rtc->ops = &da9052_rtc_ops;
rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc->rtc->range_max = RTC_TIMESTAMP_END_2063;
ret = devm_rtc_register_device(rtc->rtc);
if (ret)
return ret;
ret = da9052_request_irq(rtc->da9052, DA9052_IRQ_ALARM, "ALM",
da9052_rtc_irq, rtc);
if (ret != 0) {
rtc_err(rtc, "irq registration failed: %d\n", ret);
return ret;
}
return 0;
}
static struct platform_driver da9052_rtc_driver = {
.probe = da9052_rtc_probe,
.driver = {
.name = "da9052-rtc",
},
};
module_platform_driver(da9052_rtc_driver);
MODULE_AUTHOR("Anthony Olech <[email protected]>");
MODULE_DESCRIPTION("RTC driver for Dialog DA9052 PMIC");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da9052-rtc");
| linux-master | drivers/rtc/rtc-da9052.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP.
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/arm-smccc.h>
#include <linux/firmware/imx/sci.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#define IMX_SC_TIMER_FUNC_GET_RTC_SEC1970 9
#define IMX_SC_TIMER_FUNC_SET_RTC_ALARM 8
#define IMX_SC_TIMER_FUNC_SET_RTC_TIME 6
#define IMX_SIP_SRTC 0xC2000002
#define IMX_SIP_SRTC_SET_TIME 0x0
#define SC_IRQ_GROUP_RTC 2
#define SC_IRQ_RTC 1
static struct imx_sc_ipc *rtc_ipc_handle;
static struct rtc_device *imx_sc_rtc;
struct imx_sc_msg_timer_get_rtc_time {
struct imx_sc_rpc_msg hdr;
u32 time;
} __packed;
struct imx_sc_msg_timer_rtc_set_alarm {
struct imx_sc_rpc_msg hdr;
u16 year;
u8 mon;
u8 day;
u8 hour;
u8 min;
u8 sec;
} __packed __aligned(4);
static int imx_sc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct imx_sc_msg_timer_get_rtc_time msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_TIMER;
hdr->func = IMX_SC_TIMER_FUNC_GET_RTC_SEC1970;
hdr->size = 1;
ret = imx_scu_call_rpc(rtc_ipc_handle, &msg, true);
if (ret) {
dev_err(dev, "read rtc time failed, ret %d\n", ret);
return ret;
}
rtc_time64_to_tm(msg.time, tm);
return 0;
}
static int imx_sc_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct arm_smccc_res res;
/* pack 2 time parameters into 1 register, 16 bits for each */
arm_smccc_smc(IMX_SIP_SRTC, IMX_SIP_SRTC_SET_TIME,
((tm->tm_year + 1900) << 16) | (tm->tm_mon + 1),
(tm->tm_mday << 16) | tm->tm_hour,
(tm->tm_min << 16) | tm->tm_sec,
0, 0, 0, &res);
return res.a0;
}
static int imx_sc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
return imx_scu_irq_group_enable(SC_IRQ_GROUP_RTC, SC_IRQ_RTC, enable);
}
static int imx_sc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct imx_sc_msg_timer_rtc_set_alarm msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
struct rtc_time *alrm_tm = &alrm->time;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_TIMER;
hdr->func = IMX_SC_TIMER_FUNC_SET_RTC_ALARM;
hdr->size = 3;
msg.year = alrm_tm->tm_year + 1900;
msg.mon = alrm_tm->tm_mon + 1;
msg.day = alrm_tm->tm_mday;
msg.hour = alrm_tm->tm_hour;
msg.min = alrm_tm->tm_min;
msg.sec = alrm_tm->tm_sec;
ret = imx_scu_call_rpc(rtc_ipc_handle, &msg, true);
if (ret) {
dev_err(dev, "set rtc alarm failed, ret %d\n", ret);
return ret;
}
ret = imx_sc_rtc_alarm_irq_enable(dev, alrm->enabled);
if (ret) {
dev_err(dev, "enable rtc alarm failed, ret %d\n", ret);
return ret;
}
return 0;
}
static const struct rtc_class_ops imx_sc_rtc_ops = {
.read_time = imx_sc_rtc_read_time,
.set_time = imx_sc_rtc_set_time,
.set_alarm = imx_sc_rtc_set_alarm,
.alarm_irq_enable = imx_sc_rtc_alarm_irq_enable,
};
static int imx_sc_rtc_alarm_notify(struct notifier_block *nb,
unsigned long event, void *group)
{
/* ignore non-rtc irq */
if (!((event & SC_IRQ_RTC) && (*(u8 *)group == SC_IRQ_GROUP_RTC)))
return 0;
rtc_update_irq(imx_sc_rtc, 1, RTC_IRQF | RTC_AF);
return 0;
}
static struct notifier_block imx_sc_rtc_alarm_sc_notifier = {
.notifier_call = imx_sc_rtc_alarm_notify,
};
static int imx_sc_rtc_probe(struct platform_device *pdev)
{
int ret;
ret = imx_scu_get_handle(&rtc_ipc_handle);
if (ret)
return ret;
device_init_wakeup(&pdev->dev, true);
imx_sc_rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(imx_sc_rtc))
return PTR_ERR(imx_sc_rtc);
imx_sc_rtc->ops = &imx_sc_rtc_ops;
imx_sc_rtc->range_min = 0;
imx_sc_rtc->range_max = U32_MAX;
ret = devm_rtc_register_device(imx_sc_rtc);
if (ret)
return ret;
imx_scu_irq_register_notifier(&imx_sc_rtc_alarm_sc_notifier);
return 0;
}
static const struct of_device_id imx_sc_dt_ids[] = {
{ .compatible = "fsl,imx8qxp-sc-rtc", },
{}
};
MODULE_DEVICE_TABLE(of, imx_sc_dt_ids);
static struct platform_driver imx_sc_rtc_driver = {
.driver = {
.name = "imx-sc-rtc",
.of_match_table = imx_sc_dt_ids,
},
.probe = imx_sc_rtc_probe,
};
module_platform_driver(imx_sc_rtc_driver);
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX System Controller RTC Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-imx-sc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An rtc/i2c driver for the EM Microelectronic EM3027
* Copyright 2011 CompuLab, Ltd.
*
* Author: Mike Rapoport <[email protected]>
*
* Based on rtc-ds1672.c by Alessandro Zummo <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/module.h>
#include <linux/of.h>
/* Registers */
#define EM3027_REG_ON_OFF_CTRL 0x00
#define EM3027_REG_IRQ_CTRL 0x01
#define EM3027_REG_IRQ_FLAGS 0x02
#define EM3027_REG_STATUS 0x03
#define EM3027_REG_RST_CTRL 0x04
#define EM3027_REG_WATCH_SEC 0x08
#define EM3027_REG_WATCH_MIN 0x09
#define EM3027_REG_WATCH_HOUR 0x0a
#define EM3027_REG_WATCH_DATE 0x0b
#define EM3027_REG_WATCH_DAY 0x0c
#define EM3027_REG_WATCH_MON 0x0d
#define EM3027_REG_WATCH_YEAR 0x0e
#define EM3027_REG_ALARM_SEC 0x10
#define EM3027_REG_ALARM_MIN 0x11
#define EM3027_REG_ALARM_HOUR 0x12
#define EM3027_REG_ALARM_DATE 0x13
#define EM3027_REG_ALARM_DAY 0x14
#define EM3027_REG_ALARM_MON 0x15
#define EM3027_REG_ALARM_YEAR 0x16
static struct i2c_driver em3027_driver;
static int em3027_get_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char addr = EM3027_REG_WATCH_SEC;
unsigned char buf[7];
struct i2c_msg msgs[] = {
{/* setup read addr */
.addr = client->addr,
.len = 1,
.buf = &addr
},
{/* read time/date */
.addr = client->addr,
.flags = I2C_M_RD,
.len = 7,
.buf = buf
},
};
/* read time/date registers */
if ((i2c_transfer(client->adapter, &msgs[0], 2)) != 2) {
dev_err(&client->dev, "%s: read error\n", __func__);
return -EIO;
}
tm->tm_sec = bcd2bin(buf[0]);
tm->tm_min = bcd2bin(buf[1]);
tm->tm_hour = bcd2bin(buf[2]);
tm->tm_mday = bcd2bin(buf[3]);
tm->tm_wday = bcd2bin(buf[4]);
tm->tm_mon = bcd2bin(buf[5]) - 1;
tm->tm_year = bcd2bin(buf[6]) + 100;
return 0;
}
static int em3027_set_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char buf[8];
struct i2c_msg msg = {
.addr = client->addr,
.len = 8,
.buf = buf, /* write time/date */
};
buf[0] = EM3027_REG_WATCH_SEC;
buf[1] = bin2bcd(tm->tm_sec);
buf[2] = bin2bcd(tm->tm_min);
buf[3] = bin2bcd(tm->tm_hour);
buf[4] = bin2bcd(tm->tm_mday);
buf[5] = bin2bcd(tm->tm_wday);
buf[6] = bin2bcd(tm->tm_mon + 1);
buf[7] = bin2bcd(tm->tm_year % 100);
/* write time/date registers */
if ((i2c_transfer(client->adapter, &msg, 1)) != 1) {
dev_err(&client->dev, "%s: write error\n", __func__);
return -EIO;
}
return 0;
}
static const struct rtc_class_ops em3027_rtc_ops = {
.read_time = em3027_get_time,
.set_time = em3027_set_time,
};
static int em3027_probe(struct i2c_client *client)
{
struct rtc_device *rtc;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
rtc = devm_rtc_device_register(&client->dev, em3027_driver.driver.name,
&em3027_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
i2c_set_clientdata(client, rtc);
return 0;
}
static const struct i2c_device_id em3027_id[] = {
{ "em3027", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, em3027_id);
#ifdef CONFIG_OF
static const struct of_device_id em3027_of_match[] = {
{ .compatible = "emmicro,em3027", },
{}
};
MODULE_DEVICE_TABLE(of, em3027_of_match);
#endif
static struct i2c_driver em3027_driver = {
.driver = {
.name = "rtc-em3027",
.of_match_table = of_match_ptr(em3027_of_match),
},
.probe = em3027_probe,
.id_table = em3027_id,
};
module_i2c_driver(em3027_driver);
MODULE_AUTHOR("Mike Rapoport <[email protected]>");
MODULE_DESCRIPTION("EM Microelectronic EM3027 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-em3027.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RTC client/driver for the Maxim/Dallas DS3232/DS3234 Real-Time Clock
*
* Copyright (C) 2009-2011 Freescale Semiconductor.
* Author: Jack Lan <[email protected]>
* Copyright (C) 2008 MIMOMax Wireless Ltd.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include <linux/hwmon.h>
#define DS3232_REG_SECONDS 0x00
#define DS3232_REG_MINUTES 0x01
#define DS3232_REG_HOURS 0x02
#define DS3232_REG_AMPM 0x02
#define DS3232_REG_DAY 0x03
#define DS3232_REG_DATE 0x04
#define DS3232_REG_MONTH 0x05
#define DS3232_REG_CENTURY 0x05
#define DS3232_REG_YEAR 0x06
#define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
#define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
#define DS3232_REG_CR 0x0E /* Control register */
# define DS3232_REG_CR_nEOSC 0x80
# define DS3232_REG_CR_INTCN 0x04
# define DS3232_REG_CR_A2IE 0x02
# define DS3232_REG_CR_A1IE 0x01
#define DS3232_REG_SR 0x0F /* control/status register */
# define DS3232_REG_SR_OSF 0x80
# define DS3232_REG_SR_BSY 0x04
# define DS3232_REG_SR_A2F 0x02
# define DS3232_REG_SR_A1F 0x01
#define DS3232_REG_TEMPERATURE 0x11
#define DS3232_REG_SRAM_START 0x14
#define DS3232_REG_SRAM_END 0xFF
#define DS3232_REG_SRAM_SIZE 236
struct ds3232 {
struct device *dev;
struct regmap *regmap;
int irq;
struct rtc_device *rtc;
bool suspended;
};
static int ds3232_check_rtc_status(struct device *dev)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int ret = 0;
int control, stat;
ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
if (ret)
return ret;
if (stat & DS3232_REG_SR_OSF)
dev_warn(dev,
"oscillator discontinuity flagged, "
"time unreliable\n");
stat &= ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
if (ret)
return ret;
/* If the alarm is pending, clear it before requesting
* the interrupt, so an interrupt event isn't reported
* before everything is initialized.
*/
ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
if (ret)
return ret;
control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
control |= DS3232_REG_CR_INTCN;
return regmap_write(ds3232->regmap, DS3232_REG_CR, control);
}
static int ds3232_read_time(struct device *dev, struct rtc_time *time)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int ret;
u8 buf[7];
unsigned int year, month, day, hour, minute, second;
unsigned int week, twelve_hr, am_pm;
unsigned int century, add_century = 0;
ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_SECONDS, buf, 7);
if (ret)
return ret;
second = buf[0];
minute = buf[1];
hour = buf[2];
week = buf[3];
day = buf[4];
month = buf[5];
year = buf[6];
/* Extract additional information for AM/PM and century */
twelve_hr = hour & 0x40;
am_pm = hour & 0x20;
century = month & 0x80;
/* Write to rtc_time structure */
time->tm_sec = bcd2bin(second);
time->tm_min = bcd2bin(minute);
if (twelve_hr) {
/* Convert to 24 hr */
if (am_pm)
time->tm_hour = bcd2bin(hour & 0x1F) + 12;
else
time->tm_hour = bcd2bin(hour & 0x1F);
} else {
time->tm_hour = bcd2bin(hour);
}
/* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
time->tm_wday = bcd2bin(week) - 1;
time->tm_mday = bcd2bin(day);
/* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
time->tm_mon = bcd2bin(month & 0x7F) - 1;
if (century)
add_century = 100;
time->tm_year = bcd2bin(year) + add_century;
return 0;
}
static int ds3232_set_time(struct device *dev, struct rtc_time *time)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
u8 buf[7];
/* Extract time from rtc_time and load into ds3232*/
buf[0] = bin2bcd(time->tm_sec);
buf[1] = bin2bcd(time->tm_min);
buf[2] = bin2bcd(time->tm_hour);
/* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
buf[3] = bin2bcd(time->tm_wday + 1);
buf[4] = bin2bcd(time->tm_mday); /* Date */
/* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
buf[5] = bin2bcd(time->tm_mon + 1);
if (time->tm_year >= 100) {
buf[5] |= 0x80;
buf[6] = bin2bcd(time->tm_year - 100);
} else {
buf[6] = bin2bcd(time->tm_year);
}
return regmap_bulk_write(ds3232->regmap, DS3232_REG_SECONDS, buf, 7);
}
/*
* DS3232 has two alarm, we only use alarm1
* According to linux specification, only support one-shot alarm
* no periodic alarm mode
*/
static int ds3232_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int control, stat;
int ret;
u8 buf[4];
ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
if (ret)
goto out;
ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
if (ret)
goto out;
ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
if (ret)
goto out;
alarm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
alarm->time.tm_min = bcd2bin(buf[1] & 0x7F);
alarm->time.tm_hour = bcd2bin(buf[2] & 0x7F);
alarm->time.tm_mday = bcd2bin(buf[3] & 0x7F);
alarm->enabled = !!(control & DS3232_REG_CR_A1IE);
alarm->pending = !!(stat & DS3232_REG_SR_A1F);
ret = 0;
out:
return ret;
}
/*
* linux rtc-module does not support wday alarm
* and only 24h time mode supported indeed
*/
static int ds3232_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int control, stat;
int ret;
u8 buf[4];
if (ds3232->irq <= 0)
return -EINVAL;
buf[0] = bin2bcd(alarm->time.tm_sec);
buf[1] = bin2bcd(alarm->time.tm_min);
buf[2] = bin2bcd(alarm->time.tm_hour);
buf[3] = bin2bcd(alarm->time.tm_mday);
/* clear alarm interrupt enable bit */
ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
if (ret)
goto out;
control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
if (ret)
goto out;
/* clear any pending alarm flag */
ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
if (ret)
goto out;
stat &= ~(DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
if (ret)
goto out;
ret = regmap_bulk_write(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
if (ret)
goto out;
if (alarm->enabled) {
control |= DS3232_REG_CR_A1IE;
ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
}
out:
return ret;
}
static int ds3232_update_alarm(struct device *dev, unsigned int enabled)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int control;
int ret;
ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
if (ret)
return ret;
if (enabled)
/* enable alarm1 interrupt */
control |= DS3232_REG_CR_A1IE;
else
/* disable alarm1 interrupt */
control &= ~(DS3232_REG_CR_A1IE);
ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
return ret;
}
/*
* Temperature sensor support for ds3232/ds3234 devices.
* A user-initiated temperature conversion is not started by this function,
* so the temperature is updated once every 64 seconds.
*/
static int ds3232_hwmon_read_temp(struct device *dev, long int *mC)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
u8 temp_buf[2];
s16 temp;
int ret;
ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_TEMPERATURE, temp_buf,
sizeof(temp_buf));
if (ret < 0)
return ret;
/*
* Temperature is represented as a 10-bit code with a resolution of
* 0.25 degree celsius and encoded in two's complement format.
*/
temp = (temp_buf[0] << 8) | temp_buf[1];
temp >>= 6;
*mC = temp * 250;
return 0;
}
static umode_t ds3232_hwmon_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type != hwmon_temp)
return 0;
switch (attr) {
case hwmon_temp_input:
return 0444;
default:
return 0;
}
}
static int ds3232_hwmon_read(struct device *dev,
enum hwmon_sensor_types type,
u32 attr, int channel, long *temp)
{
int err;
switch (attr) {
case hwmon_temp_input:
err = ds3232_hwmon_read_temp(dev, temp);
break;
default:
err = -EOPNOTSUPP;
break;
}
return err;
}
static u32 ds3232_hwmon_chip_config[] = {
HWMON_C_REGISTER_TZ,
0
};
static const struct hwmon_channel_info ds3232_hwmon_chip = {
.type = hwmon_chip,
.config = ds3232_hwmon_chip_config,
};
static u32 ds3232_hwmon_temp_config[] = {
HWMON_T_INPUT,
0
};
static const struct hwmon_channel_info ds3232_hwmon_temp = {
.type = hwmon_temp,
.config = ds3232_hwmon_temp_config,
};
static const struct hwmon_channel_info * const ds3232_hwmon_info[] = {
&ds3232_hwmon_chip,
&ds3232_hwmon_temp,
NULL
};
static const struct hwmon_ops ds3232_hwmon_hwmon_ops = {
.is_visible = ds3232_hwmon_is_visible,
.read = ds3232_hwmon_read,
};
static const struct hwmon_chip_info ds3232_hwmon_chip_info = {
.ops = &ds3232_hwmon_hwmon_ops,
.info = ds3232_hwmon_info,
};
static void ds3232_hwmon_register(struct device *dev, const char *name)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
struct device *hwmon_dev;
if (!IS_ENABLED(CONFIG_RTC_DRV_DS3232_HWMON))
return;
hwmon_dev = devm_hwmon_device_register_with_info(dev, name, ds3232,
&ds3232_hwmon_chip_info,
NULL);
if (IS_ERR(hwmon_dev)) {
dev_err(dev, "unable to register hwmon device %ld\n",
PTR_ERR(hwmon_dev));
}
}
static int ds3232_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
if (ds3232->irq <= 0)
return -EINVAL;
return ds3232_update_alarm(dev, enabled);
}
static irqreturn_t ds3232_irq(int irq, void *dev_id)
{
struct device *dev = dev_id;
struct ds3232 *ds3232 = dev_get_drvdata(dev);
int ret;
int stat, control;
rtc_lock(ds3232->rtc);
ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
if (ret)
goto unlock;
if (stat & DS3232_REG_SR_A1F) {
ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
if (ret) {
dev_warn(ds3232->dev,
"Read Control Register error %d\n", ret);
} else {
/* disable alarm1 interrupt */
control &= ~(DS3232_REG_CR_A1IE);
ret = regmap_write(ds3232->regmap, DS3232_REG_CR,
control);
if (ret) {
dev_warn(ds3232->dev,
"Write Control Register error %d\n",
ret);
goto unlock;
}
/* clear the alarm pend flag */
stat &= ~DS3232_REG_SR_A1F;
ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
if (ret) {
dev_warn(ds3232->dev,
"Write Status Register error %d\n",
ret);
goto unlock;
}
rtc_update_irq(ds3232->rtc, 1, RTC_AF | RTC_IRQF);
}
}
unlock:
rtc_unlock(ds3232->rtc);
return IRQ_HANDLED;
}
static const struct rtc_class_ops ds3232_rtc_ops = {
.read_time = ds3232_read_time,
.set_time = ds3232_set_time,
.read_alarm = ds3232_read_alarm,
.set_alarm = ds3232_set_alarm,
.alarm_irq_enable = ds3232_alarm_irq_enable,
};
static int ds3232_nvmem_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct regmap *ds3232_regmap = (struct regmap *)priv;
return regmap_bulk_read(ds3232_regmap, DS3232_REG_SRAM_START + offset,
val, bytes);
}
static int ds3232_nvmem_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct regmap *ds3232_regmap = (struct regmap *)priv;
return regmap_bulk_write(ds3232_regmap, DS3232_REG_SRAM_START + offset,
val, bytes);
}
static int ds3232_probe(struct device *dev, struct regmap *regmap, int irq,
const char *name)
{
struct ds3232 *ds3232;
int ret;
struct nvmem_config nvmem_cfg = {
.name = "ds3232_sram",
.stride = 1,
.size = DS3232_REG_SRAM_SIZE,
.word_size = 1,
.reg_read = ds3232_nvmem_read,
.reg_write = ds3232_nvmem_write,
.priv = regmap,
.type = NVMEM_TYPE_BATTERY_BACKED
};
ds3232 = devm_kzalloc(dev, sizeof(*ds3232), GFP_KERNEL);
if (!ds3232)
return -ENOMEM;
ds3232->regmap = regmap;
ds3232->irq = irq;
ds3232->dev = dev;
dev_set_drvdata(dev, ds3232);
ret = ds3232_check_rtc_status(dev);
if (ret)
return ret;
if (ds3232->irq > 0)
device_init_wakeup(dev, 1);
ds3232_hwmon_register(dev, name);
ds3232->rtc = devm_rtc_device_register(dev, name, &ds3232_rtc_ops,
THIS_MODULE);
if (IS_ERR(ds3232->rtc))
return PTR_ERR(ds3232->rtc);
ret = devm_rtc_nvmem_register(ds3232->rtc, &nvmem_cfg);
if(ret)
return ret;
if (ds3232->irq > 0) {
ret = devm_request_threaded_irq(dev, ds3232->irq, NULL,
ds3232_irq,
IRQF_SHARED | IRQF_ONESHOT,
name, dev);
if (ret) {
device_set_wakeup_capable(dev, 0);
ds3232->irq = 0;
dev_err(dev, "unable to request IRQ\n");
}
}
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int ds3232_suspend(struct device *dev)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
if (device_may_wakeup(dev)) {
if (enable_irq_wake(ds3232->irq))
dev_warn_once(dev, "Cannot set wakeup source\n");
}
return 0;
}
static int ds3232_resume(struct device *dev)
{
struct ds3232 *ds3232 = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(ds3232->irq);
return 0;
}
#endif
static const struct dev_pm_ops ds3232_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(ds3232_suspend, ds3232_resume)
};
#if IS_ENABLED(CONFIG_I2C)
static int ds3232_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
static const struct regmap_config config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = DS3232_REG_SRAM_END,
};
regmap = devm_regmap_init_i2c(client, &config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
__func__, PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return ds3232_probe(&client->dev, regmap, client->irq, client->name);
}
static const struct i2c_device_id ds3232_id[] = {
{ "ds3232", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ds3232_id);
static const __maybe_unused struct of_device_id ds3232_of_match[] = {
{ .compatible = "dallas,ds3232" },
{ }
};
MODULE_DEVICE_TABLE(of, ds3232_of_match);
static struct i2c_driver ds3232_driver = {
.driver = {
.name = "rtc-ds3232",
.of_match_table = of_match_ptr(ds3232_of_match),
.pm = &ds3232_pm_ops,
},
.probe = ds3232_i2c_probe,
.id_table = ds3232_id,
};
static int ds3232_register_driver(void)
{
return i2c_add_driver(&ds3232_driver);
}
static void ds3232_unregister_driver(void)
{
i2c_del_driver(&ds3232_driver);
}
#else
static int ds3232_register_driver(void)
{
return 0;
}
static void ds3232_unregister_driver(void)
{
}
#endif
#if IS_ENABLED(CONFIG_SPI_MASTER)
static int ds3234_probe(struct spi_device *spi)
{
int res;
unsigned int tmp;
static const struct regmap_config config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = DS3232_REG_SRAM_END,
.write_flag_mask = 0x80,
};
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
__func__, PTR_ERR(regmap));
return PTR_ERR(regmap);
}
spi->mode = SPI_MODE_3;
spi->bits_per_word = 8;
spi_setup(spi);
res = regmap_read(regmap, DS3232_REG_SECONDS, &tmp);
if (res)
return res;
/* Control settings
*
* CONTROL_REG
* BIT 7 6 5 4 3 2 1 0
* EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE
*
* 0 0 0 1 1 1 0 0
*
* CONTROL_STAT_REG
* BIT 7 6 5 4 3 2 1 0
* OSF BB32kHz CRATE1 CRATE0 EN32kHz BSY A2F A1F
*
* 1 0 0 0 1 0 0 0
*/
res = regmap_read(regmap, DS3232_REG_CR, &tmp);
if (res)
return res;
res = regmap_write(regmap, DS3232_REG_CR, tmp & 0x1c);
if (res)
return res;
res = regmap_read(regmap, DS3232_REG_SR, &tmp);
if (res)
return res;
res = regmap_write(regmap, DS3232_REG_SR, tmp & 0x88);
if (res)
return res;
/* Print our settings */
res = regmap_read(regmap, DS3232_REG_CR, &tmp);
if (res)
return res;
dev_info(&spi->dev, "Control Reg: 0x%02x\n", tmp);
res = regmap_read(regmap, DS3232_REG_SR, &tmp);
if (res)
return res;
dev_info(&spi->dev, "Ctrl/Stat Reg: 0x%02x\n", tmp);
return ds3232_probe(&spi->dev, regmap, spi->irq, "ds3234");
}
static struct spi_driver ds3234_driver = {
.driver = {
.name = "ds3234",
},
.probe = ds3234_probe,
};
static int ds3234_register_driver(void)
{
return spi_register_driver(&ds3234_driver);
}
static void ds3234_unregister_driver(void)
{
spi_unregister_driver(&ds3234_driver);
}
#else
static int ds3234_register_driver(void)
{
return 0;
}
static void ds3234_unregister_driver(void)
{
}
#endif
static int __init ds323x_init(void)
{
int ret;
ret = ds3232_register_driver();
if (ret) {
pr_err("Failed to register ds3232 driver: %d\n", ret);
return ret;
}
ret = ds3234_register_driver();
if (ret) {
pr_err("Failed to register ds3234 driver: %d\n", ret);
ds3232_unregister_driver();
}
return ret;
}
module_init(ds323x_init)
static void __exit ds323x_exit(void)
{
ds3234_unregister_driver();
ds3232_unregister_driver();
}
module_exit(ds323x_exit)
MODULE_AUTHOR("Srikanth Srinivasan <[email protected]>");
MODULE_AUTHOR("Dennis Aberilla <[email protected]>");
MODULE_DESCRIPTION("Maxim/Dallas DS3232/DS3234 RTC Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:ds3234");
| linux-master | drivers/rtc/rtc-ds3232.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* RTC driver for NXP LPC178x/18xx/43xx Real-Time Clock (RTC)
*
* Copyright (C) 2011 NXP Semiconductors
* Copyright (C) 2015 Joachim Eastwood <[email protected]>
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
/* LPC24xx RTC register offsets and bits */
#define LPC24XX_ILR 0x00
#define LPC24XX_RTCCIF BIT(0)
#define LPC24XX_RTCALF BIT(1)
#define LPC24XX_CTC 0x04
#define LPC24XX_CCR 0x08
#define LPC24XX_CLKEN BIT(0)
#define LPC178X_CCALEN BIT(4)
#define LPC24XX_CIIR 0x0c
#define LPC24XX_AMR 0x10
#define LPC24XX_ALARM_DISABLE 0xff
#define LPC24XX_CTIME0 0x14
#define LPC24XX_CTIME1 0x18
#define LPC24XX_CTIME2 0x1c
#define LPC24XX_SEC 0x20
#define LPC24XX_MIN 0x24
#define LPC24XX_HOUR 0x28
#define LPC24XX_DOM 0x2c
#define LPC24XX_DOW 0x30
#define LPC24XX_DOY 0x34
#define LPC24XX_MONTH 0x38
#define LPC24XX_YEAR 0x3c
#define LPC24XX_ALSEC 0x60
#define LPC24XX_ALMIN 0x64
#define LPC24XX_ALHOUR 0x68
#define LPC24XX_ALDOM 0x6c
#define LPC24XX_ALDOW 0x70
#define LPC24XX_ALDOY 0x74
#define LPC24XX_ALMON 0x78
#define LPC24XX_ALYEAR 0x7c
/* Macros to read fields in consolidated time (CT) registers */
#define CT0_SECS(x) (((x) >> 0) & 0x3f)
#define CT0_MINS(x) (((x) >> 8) & 0x3f)
#define CT0_HOURS(x) (((x) >> 16) & 0x1f)
#define CT0_DOW(x) (((x) >> 24) & 0x07)
#define CT1_DOM(x) (((x) >> 0) & 0x1f)
#define CT1_MONTH(x) (((x) >> 8) & 0x0f)
#define CT1_YEAR(x) (((x) >> 16) & 0xfff)
#define CT2_DOY(x) (((x) >> 0) & 0xfff)
#define rtc_readl(dev, reg) readl((dev)->rtc_base + (reg))
#define rtc_writel(dev, reg, val) writel((val), (dev)->rtc_base + (reg))
struct lpc24xx_rtc {
void __iomem *rtc_base;
struct rtc_device *rtc;
struct clk *clk_rtc;
struct clk *clk_reg;
};
static int lpc24xx_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
/* Disable RTC during update */
rtc_writel(rtc, LPC24XX_CCR, LPC178X_CCALEN);
rtc_writel(rtc, LPC24XX_SEC, tm->tm_sec);
rtc_writel(rtc, LPC24XX_MIN, tm->tm_min);
rtc_writel(rtc, LPC24XX_HOUR, tm->tm_hour);
rtc_writel(rtc, LPC24XX_DOW, tm->tm_wday);
rtc_writel(rtc, LPC24XX_DOM, tm->tm_mday);
rtc_writel(rtc, LPC24XX_DOY, tm->tm_yday);
rtc_writel(rtc, LPC24XX_MONTH, tm->tm_mon);
rtc_writel(rtc, LPC24XX_YEAR, tm->tm_year);
rtc_writel(rtc, LPC24XX_CCR, LPC24XX_CLKEN | LPC178X_CCALEN);
return 0;
}
static int lpc24xx_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
u32 ct0, ct1, ct2;
ct0 = rtc_readl(rtc, LPC24XX_CTIME0);
ct1 = rtc_readl(rtc, LPC24XX_CTIME1);
ct2 = rtc_readl(rtc, LPC24XX_CTIME2);
tm->tm_sec = CT0_SECS(ct0);
tm->tm_min = CT0_MINS(ct0);
tm->tm_hour = CT0_HOURS(ct0);
tm->tm_wday = CT0_DOW(ct0);
tm->tm_mon = CT1_MONTH(ct1);
tm->tm_mday = CT1_DOM(ct1);
tm->tm_year = CT1_YEAR(ct1);
tm->tm_yday = CT2_DOY(ct2);
return 0;
}
static int lpc24xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &wkalrm->time;
tm->tm_sec = rtc_readl(rtc, LPC24XX_ALSEC);
tm->tm_min = rtc_readl(rtc, LPC24XX_ALMIN);
tm->tm_hour = rtc_readl(rtc, LPC24XX_ALHOUR);
tm->tm_mday = rtc_readl(rtc, LPC24XX_ALDOM);
tm->tm_wday = rtc_readl(rtc, LPC24XX_ALDOW);
tm->tm_yday = rtc_readl(rtc, LPC24XX_ALDOY);
tm->tm_mon = rtc_readl(rtc, LPC24XX_ALMON);
tm->tm_year = rtc_readl(rtc, LPC24XX_ALYEAR);
wkalrm->enabled = rtc_readl(rtc, LPC24XX_AMR) == 0;
wkalrm->pending = !!(rtc_readl(rtc, LPC24XX_ILR) & LPC24XX_RTCCIF);
return rtc_valid_tm(&wkalrm->time);
}
static int lpc24xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &wkalrm->time;
/* Disable alarm irq during update */
rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
rtc_writel(rtc, LPC24XX_ALSEC, tm->tm_sec);
rtc_writel(rtc, LPC24XX_ALMIN, tm->tm_min);
rtc_writel(rtc, LPC24XX_ALHOUR, tm->tm_hour);
rtc_writel(rtc, LPC24XX_ALDOM, tm->tm_mday);
rtc_writel(rtc, LPC24XX_ALDOW, tm->tm_wday);
rtc_writel(rtc, LPC24XX_ALDOY, tm->tm_yday);
rtc_writel(rtc, LPC24XX_ALMON, tm->tm_mon);
rtc_writel(rtc, LPC24XX_ALYEAR, tm->tm_year);
if (wkalrm->enabled)
rtc_writel(rtc, LPC24XX_AMR, 0);
return 0;
}
static int lpc24xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
if (enable)
rtc_writel(rtc, LPC24XX_AMR, 0);
else
rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
return 0;
}
static irqreturn_t lpc24xx_rtc_interrupt(int irq, void *data)
{
unsigned long events = RTC_IRQF;
struct lpc24xx_rtc *rtc = data;
u32 rtc_iir;
/* Check interrupt cause */
rtc_iir = rtc_readl(rtc, LPC24XX_ILR);
if (rtc_iir & LPC24XX_RTCALF) {
events |= RTC_AF;
rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
}
/* Clear interrupt status and report event */
rtc_writel(rtc, LPC24XX_ILR, rtc_iir);
rtc_update_irq(rtc->rtc, 1, events);
return IRQ_HANDLED;
}
static const struct rtc_class_ops lpc24xx_rtc_ops = {
.read_time = lpc24xx_rtc_read_time,
.set_time = lpc24xx_rtc_set_time,
.read_alarm = lpc24xx_rtc_read_alarm,
.set_alarm = lpc24xx_rtc_set_alarm,
.alarm_irq_enable = lpc24xx_rtc_alarm_irq_enable,
};
static int lpc24xx_rtc_probe(struct platform_device *pdev)
{
struct lpc24xx_rtc *rtc;
int irq, ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->rtc_base))
return PTR_ERR(rtc->rtc_base);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
rtc->clk_rtc = devm_clk_get(&pdev->dev, "rtc");
if (IS_ERR(rtc->clk_rtc)) {
dev_err(&pdev->dev, "error getting rtc clock\n");
return PTR_ERR(rtc->clk_rtc);
}
rtc->clk_reg = devm_clk_get(&pdev->dev, "reg");
if (IS_ERR(rtc->clk_reg)) {
dev_err(&pdev->dev, "error getting reg clock\n");
return PTR_ERR(rtc->clk_reg);
}
ret = clk_prepare_enable(rtc->clk_rtc);
if (ret) {
dev_err(&pdev->dev, "unable to enable rtc clock\n");
return ret;
}
ret = clk_prepare_enable(rtc->clk_reg);
if (ret) {
dev_err(&pdev->dev, "unable to enable reg clock\n");
goto disable_rtc_clk;
}
platform_set_drvdata(pdev, rtc);
/* Clear any pending interrupts */
rtc_writel(rtc, LPC24XX_ILR, LPC24XX_RTCCIF | LPC24XX_RTCALF);
/* Enable RTC count */
rtc_writel(rtc, LPC24XX_CCR, LPC24XX_CLKEN | LPC178X_CCALEN);
ret = devm_request_irq(&pdev->dev, irq, lpc24xx_rtc_interrupt, 0,
pdev->name, rtc);
if (ret < 0) {
dev_warn(&pdev->dev, "can't request interrupt\n");
goto disable_clks;
}
rtc->rtc = devm_rtc_device_register(&pdev->dev, "lpc24xx-rtc",
&lpc24xx_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rtc)) {
dev_err(&pdev->dev, "can't register rtc device\n");
ret = PTR_ERR(rtc->rtc);
goto disable_clks;
}
return 0;
disable_clks:
clk_disable_unprepare(rtc->clk_reg);
disable_rtc_clk:
clk_disable_unprepare(rtc->clk_rtc);
return ret;
}
static void lpc24xx_rtc_remove(struct platform_device *pdev)
{
struct lpc24xx_rtc *rtc = platform_get_drvdata(pdev);
/* Ensure all interrupt sources are masked */
rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
rtc_writel(rtc, LPC24XX_CIIR, 0);
rtc_writel(rtc, LPC24XX_CCR, LPC178X_CCALEN);
clk_disable_unprepare(rtc->clk_rtc);
clk_disable_unprepare(rtc->clk_reg);
}
static const struct of_device_id lpc24xx_rtc_match[] = {
{ .compatible = "nxp,lpc1788-rtc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpc24xx_rtc_match);
static struct platform_driver lpc24xx_rtc_driver = {
.probe = lpc24xx_rtc_probe,
.remove_new = lpc24xx_rtc_remove,
.driver = {
.name = "lpc24xx-rtc",
.of_match_table = lpc24xx_rtc_match,
},
};
module_platform_driver(lpc24xx_rtc_driver);
MODULE_AUTHOR("Kevin Wells <[email protected]>");
MODULE_DESCRIPTION("RTC driver for the LPC178x/18xx/408x/43xx SoCs");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-lpc24xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Dallas DS1216 RTC driver
*
* Copyright (c) 2007 Thomas Bogendoerfer
*
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/bcd.h>
#include <linux/slab.h>
struct ds1216_regs {
u8 tsec;
u8 sec;
u8 min;
u8 hour;
u8 wday;
u8 mday;
u8 month;
u8 year;
};
#define DS1216_HOUR_1224 (1 << 7)
#define DS1216_HOUR_AMPM (1 << 5)
struct ds1216_priv {
struct rtc_device *rtc;
void __iomem *ioaddr;
};
static const u8 magic[] = {
0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
};
/*
* Read the 64 bit we'd like to have - It a series
* of 64 bits showing up in the LSB of the base register.
*
*/
static void ds1216_read(u8 __iomem *ioaddr, u8 *buf)
{
unsigned char c;
int i, j;
for (i = 0; i < 8; i++) {
c = 0;
for (j = 0; j < 8; j++)
c |= (readb(ioaddr) & 0x1) << j;
buf[i] = c;
}
}
static void ds1216_write(u8 __iomem *ioaddr, const u8 *buf)
{
unsigned char c;
int i, j;
for (i = 0; i < 8; i++) {
c = buf[i];
for (j = 0; j < 8; j++) {
writeb(c, ioaddr);
c = c >> 1;
}
}
}
static void ds1216_switch_ds_to_clock(u8 __iomem *ioaddr)
{
/* Reset magic pointer */
readb(ioaddr);
/* Write 64 bit magic to DS1216 */
ds1216_write(ioaddr, magic);
}
static int ds1216_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct ds1216_priv *priv = dev_get_drvdata(dev);
struct ds1216_regs regs;
ds1216_switch_ds_to_clock(priv->ioaddr);
ds1216_read(priv->ioaddr, (u8 *)®s);
tm->tm_sec = bcd2bin(regs.sec);
tm->tm_min = bcd2bin(regs.min);
if (regs.hour & DS1216_HOUR_1224) {
/* AM/PM mode */
tm->tm_hour = bcd2bin(regs.hour & 0x1f);
if (regs.hour & DS1216_HOUR_AMPM)
tm->tm_hour += 12;
} else
tm->tm_hour = bcd2bin(regs.hour & 0x3f);
tm->tm_wday = (regs.wday & 7) - 1;
tm->tm_mday = bcd2bin(regs.mday & 0x3f);
tm->tm_mon = bcd2bin(regs.month & 0x1f);
tm->tm_year = bcd2bin(regs.year);
if (tm->tm_year < 70)
tm->tm_year += 100;
return 0;
}
static int ds1216_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct ds1216_priv *priv = dev_get_drvdata(dev);
struct ds1216_regs regs;
ds1216_switch_ds_to_clock(priv->ioaddr);
ds1216_read(priv->ioaddr, (u8 *)®s);
regs.tsec = 0; /* clear 0.1 and 0.01 seconds */
regs.sec = bin2bcd(tm->tm_sec);
regs.min = bin2bcd(tm->tm_min);
regs.hour &= DS1216_HOUR_1224;
if (regs.hour && tm->tm_hour > 12) {
regs.hour |= DS1216_HOUR_AMPM;
tm->tm_hour -= 12;
}
regs.hour |= bin2bcd(tm->tm_hour);
regs.wday &= ~7;
regs.wday |= tm->tm_wday;
regs.mday = bin2bcd(tm->tm_mday);
regs.month = bin2bcd(tm->tm_mon);
regs.year = bin2bcd(tm->tm_year % 100);
ds1216_switch_ds_to_clock(priv->ioaddr);
ds1216_write(priv->ioaddr, (u8 *)®s);
return 0;
}
static const struct rtc_class_ops ds1216_rtc_ops = {
.read_time = ds1216_rtc_read_time,
.set_time = ds1216_rtc_set_time,
};
static int __init ds1216_rtc_probe(struct platform_device *pdev)
{
struct ds1216_priv *priv;
u8 dummy[8];
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->ioaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->ioaddr))
return PTR_ERR(priv->ioaddr);
priv->rtc = devm_rtc_device_register(&pdev->dev, "ds1216",
&ds1216_rtc_ops, THIS_MODULE);
if (IS_ERR(priv->rtc))
return PTR_ERR(priv->rtc);
/* dummy read to get clock into a known state */
ds1216_read(priv->ioaddr, dummy);
return 0;
}
static struct platform_driver ds1216_rtc_platform_driver = {
.driver = {
.name = "rtc-ds1216",
},
};
module_platform_driver_probe(ds1216_rtc_platform_driver, ds1216_rtc_probe);
MODULE_AUTHOR("Thomas Bogendoerfer <[email protected]>");
MODULE_DESCRIPTION("DS1216 RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-ds1216");
| linux-master | drivers/rtc/rtc-ds1216.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Real Time Clock driver for Conexant Digicolor
*
* Copyright (C) 2015 Paradox Innovation Ltd.
*
* Author: Baruch Siach <[email protected]>
*/
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/of.h>
#define DC_RTC_CONTROL 0x0
#define DC_RTC_TIME 0x8
#define DC_RTC_REFERENCE 0xc
#define DC_RTC_ALARM 0x10
#define DC_RTC_INTFLAG_CLEAR 0x14
#define DC_RTC_INTENABLE 0x16
#define DC_RTC_CMD_MASK 0xf
#define DC_RTC_GO_BUSY BIT(7)
#define CMD_NOP 0
#define CMD_RESET 1
#define CMD_WRITE 3
#define CMD_READ 4
#define CMD_DELAY_US (10*1000)
#define CMD_TIMEOUT_US (500*CMD_DELAY_US)
struct dc_rtc {
struct rtc_device *rtc_dev;
void __iomem *regs;
};
static int dc_rtc_cmds(struct dc_rtc *rtc, const u8 *cmds, int len)
{
u8 val;
int i, ret;
for (i = 0; i < len; i++) {
writeb_relaxed((cmds[i] & DC_RTC_CMD_MASK) | DC_RTC_GO_BUSY,
rtc->regs + DC_RTC_CONTROL);
ret = readb_relaxed_poll_timeout(
rtc->regs + DC_RTC_CONTROL, val,
!(val & DC_RTC_GO_BUSY), CMD_DELAY_US, CMD_TIMEOUT_US);
if (ret < 0)
return ret;
}
return 0;
}
static int dc_rtc_read(struct dc_rtc *rtc, unsigned long *val)
{
static const u8 read_cmds[] = {CMD_READ, CMD_NOP};
u32 reference, time1, time2;
int ret;
ret = dc_rtc_cmds(rtc, read_cmds, ARRAY_SIZE(read_cmds));
if (ret < 0)
return ret;
reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE);
time1 = readl_relaxed(rtc->regs + DC_RTC_TIME);
/* Read twice to ensure consistency */
while (1) {
time2 = readl_relaxed(rtc->regs + DC_RTC_TIME);
if (time1 == time2)
break;
time1 = time2;
}
*val = reference + time1;
return 0;
}
static int dc_rtc_write(struct dc_rtc *rtc, u32 val)
{
static const u8 write_cmds[] = {CMD_WRITE, CMD_NOP, CMD_RESET, CMD_NOP};
writel_relaxed(val, rtc->regs + DC_RTC_REFERENCE);
return dc_rtc_cmds(rtc, write_cmds, ARRAY_SIZE(write_cmds));
}
static int dc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct dc_rtc *rtc = dev_get_drvdata(dev);
unsigned long now;
int ret;
ret = dc_rtc_read(rtc, &now);
if (ret < 0)
return ret;
rtc_time64_to_tm(now, tm);
return 0;
}
static int dc_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct dc_rtc *rtc = dev_get_drvdata(dev);
return dc_rtc_write(rtc, rtc_tm_to_time64(tm));
}
static int dc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct dc_rtc *rtc = dev_get_drvdata(dev);
u32 alarm_reg, reference;
unsigned long now;
int ret;
alarm_reg = readl_relaxed(rtc->regs + DC_RTC_ALARM);
reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE);
rtc_time64_to_tm(reference + alarm_reg, &alarm->time);
ret = dc_rtc_read(rtc, &now);
if (ret < 0)
return ret;
alarm->pending = alarm_reg + reference > now;
alarm->enabled = readl_relaxed(rtc->regs + DC_RTC_INTENABLE);
return 0;
}
static int dc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct dc_rtc *rtc = dev_get_drvdata(dev);
time64_t alarm_time;
u32 reference;
alarm_time = rtc_tm_to_time64(&alarm->time);
reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE);
writel_relaxed(alarm_time - reference, rtc->regs + DC_RTC_ALARM);
writeb_relaxed(!!alarm->enabled, rtc->regs + DC_RTC_INTENABLE);
return 0;
}
static int dc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct dc_rtc *rtc = dev_get_drvdata(dev);
writeb_relaxed(!!enabled, rtc->regs + DC_RTC_INTENABLE);
return 0;
}
static const struct rtc_class_ops dc_rtc_ops = {
.read_time = dc_rtc_read_time,
.set_time = dc_rtc_set_time,
.read_alarm = dc_rtc_read_alarm,
.set_alarm = dc_rtc_set_alarm,
.alarm_irq_enable = dc_rtc_alarm_irq_enable,
};
static irqreturn_t dc_rtc_irq(int irq, void *dev_id)
{
struct dc_rtc *rtc = dev_id;
writeb_relaxed(1, rtc->regs + DC_RTC_INTFLAG_CLEAR);
rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
return IRQ_HANDLED;
}
static int __init dc_rtc_probe(struct platform_device *pdev)
{
struct dc_rtc *rtc;
int irq, ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->regs))
return PTR_ERR(rtc->regs);
rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc_dev))
return PTR_ERR(rtc->rtc_dev);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(&pdev->dev, irq, dc_rtc_irq, 0, pdev->name, rtc);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, rtc);
rtc->rtc_dev->ops = &dc_rtc_ops;
rtc->rtc_dev->range_max = U32_MAX;
return devm_rtc_register_device(rtc->rtc_dev);
}
static const __maybe_unused struct of_device_id dc_dt_ids[] = {
{ .compatible = "cnxt,cx92755-rtc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dc_dt_ids);
static struct platform_driver dc_rtc_driver = {
.driver = {
.name = "digicolor_rtc",
.of_match_table = of_match_ptr(dc_dt_ids),
},
};
module_platform_driver_probe(dc_rtc_driver, dc_rtc_probe);
MODULE_AUTHOR("Baruch Siach <[email protected]>");
MODULE_DESCRIPTION("Conexant Digicolor Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-digicolor.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 BayLibre, SAS
* Author: Neil Armstrong <[email protected]>
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/time64.h>
struct meson_vrtc_data {
void __iomem *io_alarm;
struct rtc_device *rtc;
unsigned long alarm_time;
bool enabled;
};
static int meson_vrtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct timespec64 time;
dev_dbg(dev, "%s\n", __func__);
ktime_get_real_ts64(&time);
rtc_time64_to_tm(time.tv_sec, tm);
return 0;
}
static void meson_vrtc_set_wakeup_time(struct meson_vrtc_data *vrtc,
unsigned long time)
{
writel_relaxed(time, vrtc->io_alarm);
}
static int meson_vrtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct meson_vrtc_data *vrtc = dev_get_drvdata(dev);
dev_dbg(dev, "%s: alarm->enabled=%d\n", __func__, alarm->enabled);
if (alarm->enabled)
vrtc->alarm_time = rtc_tm_to_time64(&alarm->time);
else
vrtc->alarm_time = 0;
return 0;
}
static int meson_vrtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct meson_vrtc_data *vrtc = dev_get_drvdata(dev);
vrtc->enabled = enabled;
return 0;
}
static const struct rtc_class_ops meson_vrtc_ops = {
.read_time = meson_vrtc_read_time,
.set_alarm = meson_vrtc_set_alarm,
.alarm_irq_enable = meson_vrtc_alarm_irq_enable,
};
static int meson_vrtc_probe(struct platform_device *pdev)
{
struct meson_vrtc_data *vrtc;
vrtc = devm_kzalloc(&pdev->dev, sizeof(*vrtc), GFP_KERNEL);
if (!vrtc)
return -ENOMEM;
vrtc->io_alarm = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(vrtc->io_alarm))
return PTR_ERR(vrtc->io_alarm);
device_init_wakeup(&pdev->dev, 1);
platform_set_drvdata(pdev, vrtc);
vrtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(vrtc->rtc))
return PTR_ERR(vrtc->rtc);
vrtc->rtc->ops = &meson_vrtc_ops;
return devm_rtc_register_device(vrtc->rtc);
}
static int __maybe_unused meson_vrtc_suspend(struct device *dev)
{
struct meson_vrtc_data *vrtc = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
if (vrtc->alarm_time) {
unsigned long local_time;
long alarm_secs;
struct timespec64 time;
ktime_get_real_ts64(&time);
local_time = time.tv_sec;
dev_dbg(dev, "alarm_time = %lus, local_time=%lus\n",
vrtc->alarm_time, local_time);
alarm_secs = vrtc->alarm_time - local_time;
if (alarm_secs > 0) {
meson_vrtc_set_wakeup_time(vrtc, alarm_secs);
dev_dbg(dev, "system will wakeup in %lds.\n",
alarm_secs);
} else {
dev_err(dev, "alarm time already passed: %lds.\n",
alarm_secs);
}
}
return 0;
}
static int __maybe_unused meson_vrtc_resume(struct device *dev)
{
struct meson_vrtc_data *vrtc = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
vrtc->alarm_time = 0;
meson_vrtc_set_wakeup_time(vrtc, 0);
return 0;
}
static SIMPLE_DEV_PM_OPS(meson_vrtc_pm_ops,
meson_vrtc_suspend, meson_vrtc_resume);
static const struct of_device_id meson_vrtc_dt_match[] = {
{ .compatible = "amlogic,meson-vrtc"},
{},
};
MODULE_DEVICE_TABLE(of, meson_vrtc_dt_match);
static struct platform_driver meson_vrtc_driver = {
.probe = meson_vrtc_probe,
.driver = {
.name = "meson-vrtc",
.of_match_table = meson_vrtc_dt_match,
.pm = &meson_vrtc_pm_ops,
},
};
module_platform_driver(meson_vrtc_driver);
MODULE_DESCRIPTION("Amlogic Virtual Wakeup RTC Timer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-meson-vrtc.c |
// SPDX-License-Identifier: GPL-2.0-only
/* rtc-bq4802.c: TI BQ4802 RTC driver.
*
* Copyright (C) 2008 David S. Miller <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/slab.h>
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_DESCRIPTION("TI BQ4802 RTC driver");
MODULE_LICENSE("GPL");
struct bq4802 {
void __iomem *regs;
unsigned long ioport;
struct rtc_device *rtc;
spinlock_t lock;
struct resource *r;
u8 (*read)(struct bq4802 *, int);
void (*write)(struct bq4802 *, int, u8);
};
static u8 bq4802_read_io(struct bq4802 *p, int off)
{
return inb(p->ioport + off);
}
static void bq4802_write_io(struct bq4802 *p, int off, u8 val)
{
outb(val, p->ioport + off);
}
static u8 bq4802_read_mem(struct bq4802 *p, int off)
{
return readb(p->regs + off);
}
static void bq4802_write_mem(struct bq4802 *p, int off, u8 val)
{
writeb(val, p->regs + off);
}
static int bq4802_read_time(struct device *dev, struct rtc_time *tm)
{
struct bq4802 *p = dev_get_drvdata(dev);
unsigned long flags;
unsigned int century;
u8 val;
spin_lock_irqsave(&p->lock, flags);
val = p->read(p, 0x0e);
p->write(p, 0xe, val | 0x08);
tm->tm_sec = p->read(p, 0x00);
tm->tm_min = p->read(p, 0x02);
tm->tm_hour = p->read(p, 0x04);
tm->tm_mday = p->read(p, 0x06);
tm->tm_mon = p->read(p, 0x09);
tm->tm_year = p->read(p, 0x0a);
tm->tm_wday = p->read(p, 0x08);
century = p->read(p, 0x0f);
p->write(p, 0x0e, val);
spin_unlock_irqrestore(&p->lock, flags);
tm->tm_sec = bcd2bin(tm->tm_sec);
tm->tm_min = bcd2bin(tm->tm_min);
tm->tm_hour = bcd2bin(tm->tm_hour);
tm->tm_mday = bcd2bin(tm->tm_mday);
tm->tm_mon = bcd2bin(tm->tm_mon);
tm->tm_year = bcd2bin(tm->tm_year);
tm->tm_wday = bcd2bin(tm->tm_wday);
century = bcd2bin(century);
tm->tm_year += (century * 100);
tm->tm_year -= 1900;
tm->tm_mon--;
return 0;
}
static int bq4802_set_time(struct device *dev, struct rtc_time *tm)
{
struct bq4802 *p = dev_get_drvdata(dev);
u8 sec, min, hrs, day, mon, yrs, century, val;
unsigned long flags;
unsigned int year;
year = tm->tm_year + 1900;
century = year / 100;
yrs = year % 100;
mon = tm->tm_mon + 1; /* tm_mon starts at zero */
day = tm->tm_mday;
hrs = tm->tm_hour;
min = tm->tm_min;
sec = tm->tm_sec;
sec = bin2bcd(sec);
min = bin2bcd(min);
hrs = bin2bcd(hrs);
day = bin2bcd(day);
mon = bin2bcd(mon);
yrs = bin2bcd(yrs);
century = bin2bcd(century);
spin_lock_irqsave(&p->lock, flags);
val = p->read(p, 0x0e);
p->write(p, 0x0e, val | 0x08);
p->write(p, 0x00, sec);
p->write(p, 0x02, min);
p->write(p, 0x04, hrs);
p->write(p, 0x06, day);
p->write(p, 0x09, mon);
p->write(p, 0x0a, yrs);
p->write(p, 0x0f, century);
p->write(p, 0x0e, val);
spin_unlock_irqrestore(&p->lock, flags);
return 0;
}
static const struct rtc_class_ops bq4802_ops = {
.read_time = bq4802_read_time,
.set_time = bq4802_set_time,
};
static int bq4802_probe(struct platform_device *pdev)
{
struct bq4802 *p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
int err = -ENOMEM;
if (!p)
goto out;
spin_lock_init(&p->lock);
p->r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!p->r) {
p->r = platform_get_resource(pdev, IORESOURCE_IO, 0);
err = -EINVAL;
if (!p->r)
goto out;
}
if (p->r->flags & IORESOURCE_IO) {
p->ioport = p->r->start;
p->read = bq4802_read_io;
p->write = bq4802_write_io;
} else if (p->r->flags & IORESOURCE_MEM) {
p->regs = devm_ioremap(&pdev->dev, p->r->start,
resource_size(p->r));
if (!p->regs){
err = -ENOMEM;
goto out;
}
p->read = bq4802_read_mem;
p->write = bq4802_write_mem;
} else {
err = -EINVAL;
goto out;
}
platform_set_drvdata(pdev, p);
p->rtc = devm_rtc_device_register(&pdev->dev, "bq4802",
&bq4802_ops, THIS_MODULE);
if (IS_ERR(p->rtc)) {
err = PTR_ERR(p->rtc);
goto out;
}
err = 0;
out:
return err;
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:rtc-bq4802");
static struct platform_driver bq4802_driver = {
.driver = {
.name = "rtc-bq4802",
},
.probe = bq4802_probe,
};
module_platform_driver(bq4802_driver);
| linux-master | drivers/rtc/rtc-bq4802.c |
// SPDX-License-Identifier: LGPL-2.1+
#include <kunit/test.h>
#include <linux/rtc.h>
/*
* Advance a date by one day.
*/
static void advance_date(int *year, int *month, int *mday, int *yday)
{
if (*mday != rtc_month_days(*month - 1, *year)) {
++*mday;
++*yday;
return;
}
*mday = 1;
if (*month != 12) {
++*month;
++*yday;
return;
}
*month = 1;
*yday = 1;
++*year;
}
/*
* Checks every day in a 160000 years interval starting on 1970-01-01
* against the expected result.
*/
static void rtc_time64_to_tm_test_date_range(struct kunit *test)
{
/*
* 160000 years = (160000 / 400) * 400 years
* = (160000 / 400) * 146097 days
* = (160000 / 400) * 146097 * 86400 seconds
*/
time64_t total_secs = ((time64_t) 160000) / 400 * 146097 * 86400;
int year = 1970;
int month = 1;
int mday = 1;
int yday = 1;
struct rtc_time result;
time64_t secs;
s64 days;
for (secs = 0; secs <= total_secs; secs += 86400) {
rtc_time64_to_tm(secs, &result);
days = div_s64(secs, 86400);
#define FAIL_MSG "%d/%02d/%02d (%2d) : %ld", \
year, month, mday, yday, days
KUNIT_ASSERT_EQ_MSG(test, year - 1900, result.tm_year, FAIL_MSG);
KUNIT_ASSERT_EQ_MSG(test, month - 1, result.tm_mon, FAIL_MSG);
KUNIT_ASSERT_EQ_MSG(test, mday, result.tm_mday, FAIL_MSG);
KUNIT_ASSERT_EQ_MSG(test, yday, result.tm_yday, FAIL_MSG);
advance_date(&year, &month, &mday, &yday);
}
}
static struct kunit_case rtc_lib_test_cases[] = {
KUNIT_CASE(rtc_time64_to_tm_test_date_range),
{}
};
static struct kunit_suite rtc_lib_test_suite = {
.name = "rtc_lib_test_cases",
.test_cases = rtc_lib_test_cases,
};
kunit_test_suite(rtc_lib_test_suite);
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/lib_test.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010 NXP Semiconductors
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
/*
* Clock and Power control register offsets
*/
#define LPC32XX_RTC_UCOUNT 0x00
#define LPC32XX_RTC_DCOUNT 0x04
#define LPC32XX_RTC_MATCH0 0x08
#define LPC32XX_RTC_MATCH1 0x0C
#define LPC32XX_RTC_CTRL 0x10
#define LPC32XX_RTC_INTSTAT 0x14
#define LPC32XX_RTC_KEY 0x18
#define LPC32XX_RTC_SRAM 0x80
#define LPC32XX_RTC_CTRL_MATCH0 (1 << 0)
#define LPC32XX_RTC_CTRL_MATCH1 (1 << 1)
#define LPC32XX_RTC_CTRL_ONSW_MATCH0 (1 << 2)
#define LPC32XX_RTC_CTRL_ONSW_MATCH1 (1 << 3)
#define LPC32XX_RTC_CTRL_SW_RESET (1 << 4)
#define LPC32XX_RTC_CTRL_CNTR_DIS (1 << 6)
#define LPC32XX_RTC_CTRL_ONSW_FORCE_HI (1 << 7)
#define LPC32XX_RTC_INTSTAT_MATCH0 (1 << 0)
#define LPC32XX_RTC_INTSTAT_MATCH1 (1 << 1)
#define LPC32XX_RTC_INTSTAT_ONSW (1 << 2)
#define LPC32XX_RTC_KEY_ONSW_LOADVAL 0xB5C13F27
#define rtc_readl(dev, reg) \
__raw_readl((dev)->rtc_base + (reg))
#define rtc_writel(dev, reg, val) \
__raw_writel((val), (dev)->rtc_base + (reg))
struct lpc32xx_rtc {
void __iomem *rtc_base;
int irq;
unsigned char alarm_enabled;
struct rtc_device *rtc;
spinlock_t lock;
};
static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
unsigned long elapsed_sec;
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
rtc_time64_to_tm(elapsed_sec, time);
return 0;
}
static int lpc32xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
u32 secs = rtc_tm_to_time64(time);
u32 tmp;
spin_lock_irq(&rtc->lock);
/* RTC must be disabled during count update */
tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
spin_unlock_irq(&rtc->lock);
return 0;
}
static int lpc32xx_rtc_read_alarm(struct device *dev,
struct rtc_wkalrm *wkalrm)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
rtc_time64_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
wkalrm->enabled = rtc->alarm_enabled;
wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
LPC32XX_RTC_INTSTAT_MATCH0);
return rtc_valid_tm(&wkalrm->time);
}
static int lpc32xx_rtc_set_alarm(struct device *dev,
struct rtc_wkalrm *wkalrm)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
unsigned long alarmsecs;
u32 tmp;
alarmsecs = rtc_tm_to_time64(&wkalrm->time);
spin_lock_irq(&rtc->lock);
/* Disable alarm during update */
tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
rtc->alarm_enabled = wkalrm->enabled;
if (wkalrm->enabled) {
rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
LPC32XX_RTC_INTSTAT_MATCH0);
rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
LPC32XX_RTC_CTRL_MATCH0);
}
spin_unlock_irq(&rtc->lock);
return 0;
}
static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
u32 tmp;
spin_lock_irq(&rtc->lock);
tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
if (enabled) {
rtc->alarm_enabled = 1;
tmp |= LPC32XX_RTC_CTRL_MATCH0;
} else {
rtc->alarm_enabled = 0;
tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
}
rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
spin_unlock_irq(&rtc->lock);
return 0;
}
static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
{
struct lpc32xx_rtc *rtc = dev;
spin_lock(&rtc->lock);
/* Disable alarm interrupt */
rtc_writel(rtc, LPC32XX_RTC_CTRL,
rtc_readl(rtc, LPC32XX_RTC_CTRL) &
~LPC32XX_RTC_CTRL_MATCH0);
rtc->alarm_enabled = 0;
/*
* Write a large value to the match value so the RTC won't
* keep firing the match status
*/
rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
spin_unlock(&rtc->lock);
rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static const struct rtc_class_ops lpc32xx_rtc_ops = {
.read_time = lpc32xx_rtc_read_time,
.set_time = lpc32xx_rtc_set_time,
.read_alarm = lpc32xx_rtc_read_alarm,
.set_alarm = lpc32xx_rtc_set_alarm,
.alarm_irq_enable = lpc32xx_rtc_alarm_irq_enable,
};
static int lpc32xx_rtc_probe(struct platform_device *pdev)
{
struct lpc32xx_rtc *rtc;
int err;
u32 tmp;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (unlikely(!rtc))
return -ENOMEM;
rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->rtc_base))
return PTR_ERR(rtc->rtc_base);
spin_lock_init(&rtc->lock);
/*
* The RTC is on a separate power domain and can keep it's state
* across a chip power cycle. If the RTC has never been previously
* setup, then set it up now for the first time.
*/
tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
LPC32XX_RTC_CTRL_CNTR_DIS |
LPC32XX_RTC_CTRL_MATCH0 |
LPC32XX_RTC_CTRL_MATCH1 |
LPC32XX_RTC_CTRL_ONSW_MATCH0 |
LPC32XX_RTC_CTRL_ONSW_MATCH1 |
LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
/* Clear latched interrupt states */
rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
LPC32XX_RTC_INTSTAT_MATCH0 |
LPC32XX_RTC_INTSTAT_MATCH1 |
LPC32XX_RTC_INTSTAT_ONSW);
/* Write key value to RTC so it won't reload on reset */
rtc_writel(rtc, LPC32XX_RTC_KEY,
LPC32XX_RTC_KEY_ONSW_LOADVAL);
} else {
rtc_writel(rtc, LPC32XX_RTC_CTRL,
tmp & ~LPC32XX_RTC_CTRL_MATCH0);
}
platform_set_drvdata(pdev, rtc);
rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc))
return PTR_ERR(rtc->rtc);
rtc->rtc->ops = &lpc32xx_rtc_ops;
rtc->rtc->range_max = U32_MAX;
err = devm_rtc_register_device(rtc->rtc);
if (err)
return err;
/*
* IRQ is enabled after device registration in case alarm IRQ
* is pending upon suspend exit.
*/
rtc->irq = platform_get_irq(pdev, 0);
if (rtc->irq < 0) {
dev_warn(&pdev->dev, "Can't get interrupt resource\n");
} else {
if (devm_request_irq(&pdev->dev, rtc->irq,
lpc32xx_rtc_alarm_interrupt,
0, pdev->name, rtc) < 0) {
dev_warn(&pdev->dev, "Can't request interrupt.\n");
rtc->irq = -1;
} else {
device_init_wakeup(&pdev->dev, 1);
}
}
return 0;
}
#ifdef CONFIG_PM
static int lpc32xx_rtc_suspend(struct device *dev)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
if (rtc->irq >= 0) {
if (device_may_wakeup(dev))
enable_irq_wake(rtc->irq);
else
disable_irq_wake(rtc->irq);
}
return 0;
}
static int lpc32xx_rtc_resume(struct device *dev)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
if (rtc->irq >= 0 && device_may_wakeup(dev))
disable_irq_wake(rtc->irq);
return 0;
}
/* Unconditionally disable the alarm */
static int lpc32xx_rtc_freeze(struct device *dev)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
spin_lock_irq(&rtc->lock);
rtc_writel(rtc, LPC32XX_RTC_CTRL,
rtc_readl(rtc, LPC32XX_RTC_CTRL) &
~LPC32XX_RTC_CTRL_MATCH0);
spin_unlock_irq(&rtc->lock);
return 0;
}
static int lpc32xx_rtc_thaw(struct device *dev)
{
struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
if (rtc->alarm_enabled) {
spin_lock_irq(&rtc->lock);
rtc_writel(rtc, LPC32XX_RTC_CTRL,
rtc_readl(rtc, LPC32XX_RTC_CTRL) |
LPC32XX_RTC_CTRL_MATCH0);
spin_unlock_irq(&rtc->lock);
}
return 0;
}
static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
.suspend = lpc32xx_rtc_suspend,
.resume = lpc32xx_rtc_resume,
.freeze = lpc32xx_rtc_freeze,
.thaw = lpc32xx_rtc_thaw,
.restore = lpc32xx_rtc_resume
};
#define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
#else
#define LPC32XX_RTC_PM_OPS NULL
#endif
#ifdef CONFIG_OF
static const struct of_device_id lpc32xx_rtc_match[] = {
{ .compatible = "nxp,lpc3220-rtc" },
{ }
};
MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
#endif
static struct platform_driver lpc32xx_rtc_driver = {
.probe = lpc32xx_rtc_probe,
.driver = {
.name = "rtc-lpc32xx",
.pm = LPC32XX_RTC_PM_OPS,
.of_match_table = of_match_ptr(lpc32xx_rtc_match),
},
};
module_platform_driver(lpc32xx_rtc_driver);
MODULE_AUTHOR("Kevin Wells <[email protected]");
MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-lpc32xx");
| linux-master | drivers/rtc/rtc-lpc32xx.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TI LP8788 MFD - rtc driver
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <[email protected]>
*/
#include <linux/err.h>
#include <linux/irqdomain.h>
#include <linux/mfd/lp8788.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/slab.h>
/* register address */
#define LP8788_INTEN_3 0x05
#define LP8788_RTC_UNLOCK 0x64
#define LP8788_RTC_SEC 0x70
#define LP8788_ALM1_SEC 0x77
#define LP8788_ALM1_EN 0x7D
#define LP8788_ALM2_SEC 0x7E
#define LP8788_ALM2_EN 0x84
/* mask/shift bits */
#define LP8788_INT_RTC_ALM1_M BIT(1) /* Addr 05h */
#define LP8788_INT_RTC_ALM1_S 1
#define LP8788_INT_RTC_ALM2_M BIT(2) /* Addr 05h */
#define LP8788_INT_RTC_ALM2_S 2
#define LP8788_ALM_EN_M BIT(7) /* Addr 7Dh or 84h */
#define LP8788_ALM_EN_S 7
#define DEFAULT_ALARM_SEL LP8788_ALARM_1
#define LP8788_MONTH_OFFSET 1
#define LP8788_BASE_YEAR 2000
#define MAX_WDAY_BITS 7
#define LP8788_WDAY_SET 1
#define RTC_UNLOCK 0x1
#define RTC_LATCH 0x2
#define ALARM_IRQ_FLAG (RTC_IRQF | RTC_AF)
enum lp8788_time {
LPTIME_SEC,
LPTIME_MIN,
LPTIME_HOUR,
LPTIME_MDAY,
LPTIME_MON,
LPTIME_YEAR,
LPTIME_WDAY,
LPTIME_MAX,
};
struct lp8788_rtc {
struct lp8788 *lp;
struct rtc_device *rdev;
enum lp8788_alarm_sel alarm;
int irq;
};
static const u8 addr_alarm_sec[LP8788_ALARM_MAX] = {
LP8788_ALM1_SEC,
LP8788_ALM2_SEC,
};
static const u8 addr_alarm_en[LP8788_ALARM_MAX] = {
LP8788_ALM1_EN,
LP8788_ALM2_EN,
};
static const u8 mask_alarm_en[LP8788_ALARM_MAX] = {
LP8788_INT_RTC_ALM1_M,
LP8788_INT_RTC_ALM2_M,
};
static const u8 shift_alarm_en[LP8788_ALARM_MAX] = {
LP8788_INT_RTC_ALM1_S,
LP8788_INT_RTC_ALM2_S,
};
static int _to_tm_wday(u8 lp8788_wday)
{
int i;
if (lp8788_wday == 0)
return 0;
/* lookup defined weekday from read register value */
for (i = 0; i < MAX_WDAY_BITS; i++) {
if ((lp8788_wday >> i) == LP8788_WDAY_SET)
break;
}
return i + 1;
}
static inline int _to_lp8788_wday(int tm_wday)
{
return LP8788_WDAY_SET << (tm_wday - 1);
}
static void lp8788_rtc_unlock(struct lp8788 *lp)
{
lp8788_write_byte(lp, LP8788_RTC_UNLOCK, RTC_UNLOCK);
lp8788_write_byte(lp, LP8788_RTC_UNLOCK, RTC_LATCH);
}
static int lp8788_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct lp8788_rtc *rtc = dev_get_drvdata(dev);
struct lp8788 *lp = rtc->lp;
u8 data[LPTIME_MAX];
int ret;
lp8788_rtc_unlock(lp);
ret = lp8788_read_multi_bytes(lp, LP8788_RTC_SEC, data, LPTIME_MAX);
if (ret)
return ret;
tm->tm_sec = data[LPTIME_SEC];
tm->tm_min = data[LPTIME_MIN];
tm->tm_hour = data[LPTIME_HOUR];
tm->tm_mday = data[LPTIME_MDAY];
tm->tm_mon = data[LPTIME_MON] - LP8788_MONTH_OFFSET;
tm->tm_year = data[LPTIME_YEAR] + LP8788_BASE_YEAR - 1900;
tm->tm_wday = _to_tm_wday(data[LPTIME_WDAY]);
return 0;
}
static int lp8788_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct lp8788_rtc *rtc = dev_get_drvdata(dev);
struct lp8788 *lp = rtc->lp;
u8 data[LPTIME_MAX - 1];
int ret, i, year;
year = tm->tm_year + 1900 - LP8788_BASE_YEAR;
if (year < 0) {
dev_err(lp->dev, "invalid year: %d\n", year);
return -EINVAL;
}
/* because rtc weekday is a readonly register, do not update */
data[LPTIME_SEC] = tm->tm_sec;
data[LPTIME_MIN] = tm->tm_min;
data[LPTIME_HOUR] = tm->tm_hour;
data[LPTIME_MDAY] = tm->tm_mday;
data[LPTIME_MON] = tm->tm_mon + LP8788_MONTH_OFFSET;
data[LPTIME_YEAR] = year;
for (i = 0; i < ARRAY_SIZE(data); i++) {
ret = lp8788_write_byte(lp, LP8788_RTC_SEC + i, data[i]);
if (ret)
return ret;
}
return 0;
}
static int lp8788_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct lp8788_rtc *rtc = dev_get_drvdata(dev);
struct lp8788 *lp = rtc->lp;
struct rtc_time *tm = &alarm->time;
u8 addr, data[LPTIME_MAX];
int ret;
addr = addr_alarm_sec[rtc->alarm];
ret = lp8788_read_multi_bytes(lp, addr, data, LPTIME_MAX);
if (ret)
return ret;
tm->tm_sec = data[LPTIME_SEC];
tm->tm_min = data[LPTIME_MIN];
tm->tm_hour = data[LPTIME_HOUR];
tm->tm_mday = data[LPTIME_MDAY];
tm->tm_mon = data[LPTIME_MON] - LP8788_MONTH_OFFSET;
tm->tm_year = data[LPTIME_YEAR] + LP8788_BASE_YEAR - 1900;
tm->tm_wday = _to_tm_wday(data[LPTIME_WDAY]);
alarm->enabled = data[LPTIME_WDAY] & LP8788_ALM_EN_M;
return 0;
}
static int lp8788_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct lp8788_rtc *rtc = dev_get_drvdata(dev);
struct lp8788 *lp = rtc->lp;
struct rtc_time *tm = &alarm->time;
u8 addr, data[LPTIME_MAX];
int ret, i, year;
year = tm->tm_year + 1900 - LP8788_BASE_YEAR;
if (year < 0) {
dev_err(lp->dev, "invalid year: %d\n", year);
return -EINVAL;
}
data[LPTIME_SEC] = tm->tm_sec;
data[LPTIME_MIN] = tm->tm_min;
data[LPTIME_HOUR] = tm->tm_hour;
data[LPTIME_MDAY] = tm->tm_mday;
data[LPTIME_MON] = tm->tm_mon + LP8788_MONTH_OFFSET;
data[LPTIME_YEAR] = year;
data[LPTIME_WDAY] = _to_lp8788_wday(tm->tm_wday);
for (i = 0; i < ARRAY_SIZE(data); i++) {
addr = addr_alarm_sec[rtc->alarm] + i;
ret = lp8788_write_byte(lp, addr, data[i]);
if (ret)
return ret;
}
alarm->enabled = 1;
addr = addr_alarm_en[rtc->alarm];
return lp8788_update_bits(lp, addr, LP8788_ALM_EN_M,
alarm->enabled << LP8788_ALM_EN_S);
}
static int lp8788_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct lp8788_rtc *rtc = dev_get_drvdata(dev);
struct lp8788 *lp = rtc->lp;
u8 mask, shift;
if (!rtc->irq)
return -EIO;
mask = mask_alarm_en[rtc->alarm];
shift = shift_alarm_en[rtc->alarm];
return lp8788_update_bits(lp, LP8788_INTEN_3, mask, enable << shift);
}
static const struct rtc_class_ops lp8788_rtc_ops = {
.read_time = lp8788_rtc_read_time,
.set_time = lp8788_rtc_set_time,
.read_alarm = lp8788_read_alarm,
.set_alarm = lp8788_set_alarm,
.alarm_irq_enable = lp8788_alarm_irq_enable,
};
static irqreturn_t lp8788_alarm_irq_handler(int irq, void *ptr)
{
struct lp8788_rtc *rtc = ptr;
rtc_update_irq(rtc->rdev, 1, ALARM_IRQ_FLAG);
return IRQ_HANDLED;
}
static int lp8788_alarm_irq_register(struct platform_device *pdev,
struct lp8788_rtc *rtc)
{
struct resource *r;
struct lp8788 *lp = rtc->lp;
struct irq_domain *irqdm = lp->irqdm;
int irq;
rtc->irq = 0;
/* even the alarm IRQ number is not specified, rtc time should work */
r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, LP8788_ALM_IRQ);
if (!r)
return 0;
if (rtc->alarm == LP8788_ALARM_1)
irq = r->start;
else
irq = r->end;
rtc->irq = irq_create_mapping(irqdm, irq);
return devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
lp8788_alarm_irq_handler,
0, LP8788_ALM_IRQ, rtc);
}
static int lp8788_rtc_probe(struct platform_device *pdev)
{
struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
struct lp8788_rtc *rtc;
struct device *dev = &pdev->dev;
rtc = devm_kzalloc(dev, sizeof(struct lp8788_rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->lp = lp;
rtc->alarm = lp->pdata ? lp->pdata->alarm_sel : DEFAULT_ALARM_SEL;
platform_set_drvdata(pdev, rtc);
device_init_wakeup(dev, 1);
rtc->rdev = devm_rtc_device_register(dev, "lp8788_rtc",
&lp8788_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rdev)) {
dev_err(dev, "can not register rtc device\n");
return PTR_ERR(rtc->rdev);
}
if (lp8788_alarm_irq_register(pdev, rtc))
dev_warn(lp->dev, "no rtc irq handler\n");
return 0;
}
static struct platform_driver lp8788_rtc_driver = {
.probe = lp8788_rtc_probe,
.driver = {
.name = LP8788_DEV_RTC,
},
};
module_platform_driver(lp8788_rtc_driver);
MODULE_DESCRIPTION("Texas Instruments LP8788 RTC Driver");
MODULE_AUTHOR("Milo Kim");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lp8788-rtc");
| linux-master | drivers/rtc/rtc-lp8788.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/rtc/rtc-vt8500.c
*
* Copyright (C) 2010 Alexey Charkov <[email protected]>
*
* Based on rtc-pxa.c
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
/*
* Register definitions
*/
#define VT8500_RTC_TS 0x00 /* Time set */
#define VT8500_RTC_DS 0x04 /* Date set */
#define VT8500_RTC_AS 0x08 /* Alarm set */
#define VT8500_RTC_CR 0x0c /* Control */
#define VT8500_RTC_TR 0x10 /* Time read */
#define VT8500_RTC_DR 0x14 /* Date read */
#define VT8500_RTC_WS 0x18 /* Write status */
#define VT8500_RTC_CL 0x20 /* Calibration */
#define VT8500_RTC_IS 0x24 /* Interrupt status */
#define VT8500_RTC_ST 0x28 /* Status */
#define INVALID_TIME_BIT (1 << 31)
#define DATE_CENTURY_S 19
#define DATE_YEAR_S 11
#define DATE_YEAR_MASK (0xff << DATE_YEAR_S)
#define DATE_MONTH_S 6
#define DATE_MONTH_MASK (0x1f << DATE_MONTH_S)
#define DATE_DAY_MASK 0x3f
#define TIME_DOW_S 20
#define TIME_DOW_MASK (0x07 << TIME_DOW_S)
#define TIME_HOUR_S 14
#define TIME_HOUR_MASK (0x3f << TIME_HOUR_S)
#define TIME_MIN_S 7
#define TIME_MIN_MASK (0x7f << TIME_MIN_S)
#define TIME_SEC_MASK 0x7f
#define ALARM_DAY_S 20
#define ALARM_DAY_MASK (0x3f << ALARM_DAY_S)
#define ALARM_DAY_BIT (1 << 29)
#define ALARM_HOUR_BIT (1 << 28)
#define ALARM_MIN_BIT (1 << 27)
#define ALARM_SEC_BIT (1 << 26)
#define ALARM_ENABLE_MASK (ALARM_DAY_BIT \
| ALARM_HOUR_BIT \
| ALARM_MIN_BIT \
| ALARM_SEC_BIT)
#define VT8500_RTC_CR_ENABLE (1 << 0) /* Enable RTC */
#define VT8500_RTC_CR_12H (1 << 1) /* 12h time format */
#define VT8500_RTC_CR_SM_ENABLE (1 << 2) /* Enable periodic irqs */
#define VT8500_RTC_CR_SM_SEC (1 << 3) /* 0: 1Hz/60, 1: 1Hz */
#define VT8500_RTC_CR_CALIB (1 << 4) /* Enable calibration */
#define VT8500_RTC_IS_ALARM (1 << 0) /* Alarm interrupt status */
struct vt8500_rtc {
void __iomem *regbase;
int irq_alarm;
struct rtc_device *rtc;
spinlock_t lock; /* Protects this structure */
};
static irqreturn_t vt8500_rtc_irq(int irq, void *dev_id)
{
struct vt8500_rtc *vt8500_rtc = dev_id;
u32 isr;
unsigned long events = 0;
spin_lock(&vt8500_rtc->lock);
/* clear interrupt sources */
isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS);
writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS);
spin_unlock(&vt8500_rtc->lock);
if (isr & VT8500_RTC_IS_ALARM)
events |= RTC_AF | RTC_IRQF;
rtc_update_irq(vt8500_rtc->rtc, 1, events);
return IRQ_HANDLED;
}
static int vt8500_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
u32 date, time;
date = readl(vt8500_rtc->regbase + VT8500_RTC_DR);
time = readl(vt8500_rtc->regbase + VT8500_RTC_TR);
tm->tm_sec = bcd2bin(time & TIME_SEC_MASK);
tm->tm_min = bcd2bin((time & TIME_MIN_MASK) >> TIME_MIN_S);
tm->tm_hour = bcd2bin((time & TIME_HOUR_MASK) >> TIME_HOUR_S);
tm->tm_mday = bcd2bin(date & DATE_DAY_MASK);
tm->tm_mon = bcd2bin((date & DATE_MONTH_MASK) >> DATE_MONTH_S) - 1;
tm->tm_year = bcd2bin((date & DATE_YEAR_MASK) >> DATE_YEAR_S)
+ ((date >> DATE_CENTURY_S) & 1 ? 200 : 100);
tm->tm_wday = (time & TIME_DOW_MASK) >> TIME_DOW_S;
return 0;
}
static int vt8500_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
writel((bin2bcd(tm->tm_year % 100) << DATE_YEAR_S)
| (bin2bcd(tm->tm_mon + 1) << DATE_MONTH_S)
| (bin2bcd(tm->tm_mday))
| ((tm->tm_year >= 200) << DATE_CENTURY_S),
vt8500_rtc->regbase + VT8500_RTC_DS);
writel((bin2bcd(tm->tm_wday) << TIME_DOW_S)
| (bin2bcd(tm->tm_hour) << TIME_HOUR_S)
| (bin2bcd(tm->tm_min) << TIME_MIN_S)
| (bin2bcd(tm->tm_sec)),
vt8500_rtc->regbase + VT8500_RTC_TS);
return 0;
}
static int vt8500_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
u32 isr, alarm;
alarm = readl(vt8500_rtc->regbase + VT8500_RTC_AS);
isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS);
alrm->time.tm_mday = bcd2bin((alarm & ALARM_DAY_MASK) >> ALARM_DAY_S);
alrm->time.tm_hour = bcd2bin((alarm & TIME_HOUR_MASK) >> TIME_HOUR_S);
alrm->time.tm_min = bcd2bin((alarm & TIME_MIN_MASK) >> TIME_MIN_S);
alrm->time.tm_sec = bcd2bin((alarm & TIME_SEC_MASK));
alrm->enabled = (alarm & ALARM_ENABLE_MASK) ? 1 : 0;
alrm->pending = (isr & VT8500_RTC_IS_ALARM) ? 1 : 0;
return rtc_valid_tm(&alrm->time);
}
static int vt8500_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
writel((alrm->enabled ? ALARM_ENABLE_MASK : 0)
| (bin2bcd(alrm->time.tm_mday) << ALARM_DAY_S)
| (bin2bcd(alrm->time.tm_hour) << TIME_HOUR_S)
| (bin2bcd(alrm->time.tm_min) << TIME_MIN_S)
| (bin2bcd(alrm->time.tm_sec)),
vt8500_rtc->regbase + VT8500_RTC_AS);
return 0;
}
static int vt8500_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct vt8500_rtc *vt8500_rtc = dev_get_drvdata(dev);
unsigned long tmp = readl(vt8500_rtc->regbase + VT8500_RTC_AS);
if (enabled)
tmp |= ALARM_ENABLE_MASK;
else
tmp &= ~ALARM_ENABLE_MASK;
writel(tmp, vt8500_rtc->regbase + VT8500_RTC_AS);
return 0;
}
static const struct rtc_class_ops vt8500_rtc_ops = {
.read_time = vt8500_rtc_read_time,
.set_time = vt8500_rtc_set_time,
.read_alarm = vt8500_rtc_read_alarm,
.set_alarm = vt8500_rtc_set_alarm,
.alarm_irq_enable = vt8500_alarm_irq_enable,
};
static int vt8500_rtc_probe(struct platform_device *pdev)
{
struct vt8500_rtc *vt8500_rtc;
int ret;
vt8500_rtc = devm_kzalloc(&pdev->dev,
sizeof(struct vt8500_rtc), GFP_KERNEL);
if (!vt8500_rtc)
return -ENOMEM;
spin_lock_init(&vt8500_rtc->lock);
platform_set_drvdata(pdev, vt8500_rtc);
vt8500_rtc->irq_alarm = platform_get_irq(pdev, 0);
if (vt8500_rtc->irq_alarm < 0)
return vt8500_rtc->irq_alarm;
vt8500_rtc->regbase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(vt8500_rtc->regbase))
return PTR_ERR(vt8500_rtc->regbase);
/* Enable RTC and set it to 24-hour mode */
writel(VT8500_RTC_CR_ENABLE,
vt8500_rtc->regbase + VT8500_RTC_CR);
vt8500_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(vt8500_rtc->rtc))
return PTR_ERR(vt8500_rtc->rtc);
vt8500_rtc->rtc->ops = &vt8500_rtc_ops;
vt8500_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
vt8500_rtc->rtc->range_max = RTC_TIMESTAMP_END_2199;
ret = devm_request_irq(&pdev->dev, vt8500_rtc->irq_alarm,
vt8500_rtc_irq, 0, "rtc alarm", vt8500_rtc);
if (ret < 0) {
dev_err(&pdev->dev, "can't get irq %i, err %d\n",
vt8500_rtc->irq_alarm, ret);
return ret;
}
return devm_rtc_register_device(vt8500_rtc->rtc);
}
static void vt8500_rtc_remove(struct platform_device *pdev)
{
struct vt8500_rtc *vt8500_rtc = platform_get_drvdata(pdev);
/* Disable alarm matching */
writel(0, vt8500_rtc->regbase + VT8500_RTC_IS);
}
static const struct of_device_id wmt_dt_ids[] = {
{ .compatible = "via,vt8500-rtc", },
{}
};
MODULE_DEVICE_TABLE(of, wmt_dt_ids);
static struct platform_driver vt8500_rtc_driver = {
.probe = vt8500_rtc_probe,
.remove_new = vt8500_rtc_remove,
.driver = {
.name = "vt8500-rtc",
.of_match_table = wmt_dt_ids,
},
};
module_platform_driver(vt8500_rtc_driver);
MODULE_AUTHOR("Alexey Charkov <[email protected]>");
MODULE_DESCRIPTION("VIA VT8500 SoC Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:vt8500-rtc");
| linux-master | drivers/rtc/rtc-vt8500.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Virupax Sadashivpetimath <[email protected]>
*
* RTC clock driver for the RTC part of the AB8500 Power management chip.
* Based on RTC clock driver for the AB3100 Analog Baseband Chip by
* Linus Walleij <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/pm_wakeirq.h>
#define AB8500_RTC_SOFF_STAT_REG 0x00
#define AB8500_RTC_CC_CONF_REG 0x01
#define AB8500_RTC_READ_REQ_REG 0x02
#define AB8500_RTC_WATCH_TSECMID_REG 0x03
#define AB8500_RTC_WATCH_TSECHI_REG 0x04
#define AB8500_RTC_WATCH_TMIN_LOW_REG 0x05
#define AB8500_RTC_WATCH_TMIN_MID_REG 0x06
#define AB8500_RTC_WATCH_TMIN_HI_REG 0x07
#define AB8500_RTC_ALRM_MIN_LOW_REG 0x08
#define AB8500_RTC_ALRM_MIN_MID_REG 0x09
#define AB8500_RTC_ALRM_MIN_HI_REG 0x0A
#define AB8500_RTC_STAT_REG 0x0B
#define AB8500_RTC_BKUP_CHG_REG 0x0C
#define AB8500_RTC_FORCE_BKUP_REG 0x0D
#define AB8500_RTC_CALIB_REG 0x0E
#define AB8500_RTC_SWITCH_STAT_REG 0x0F
/* RtcReadRequest bits */
#define RTC_READ_REQUEST 0x01
#define RTC_WRITE_REQUEST 0x02
/* RtcCtrl bits */
#define RTC_ALARM_ENA 0x04
#define RTC_STATUS_DATA 0x01
#define COUNTS_PER_SEC (0xF000 / 60)
static const u8 ab8500_rtc_time_regs[] = {
AB8500_RTC_WATCH_TMIN_HI_REG, AB8500_RTC_WATCH_TMIN_MID_REG,
AB8500_RTC_WATCH_TMIN_LOW_REG, AB8500_RTC_WATCH_TSECHI_REG,
AB8500_RTC_WATCH_TSECMID_REG
};
static const u8 ab8500_rtc_alarm_regs[] = {
AB8500_RTC_ALRM_MIN_HI_REG, AB8500_RTC_ALRM_MIN_MID_REG,
AB8500_RTC_ALRM_MIN_LOW_REG
};
static int ab8500_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
unsigned long timeout = jiffies + HZ;
int retval, i;
unsigned long mins, secs;
unsigned char buf[ARRAY_SIZE(ab8500_rtc_time_regs)];
u8 value;
/* Request a data read */
retval = abx500_set_register_interruptible(dev,
AB8500_RTC, AB8500_RTC_READ_REQ_REG, RTC_READ_REQUEST);
if (retval < 0)
return retval;
/* Wait for some cycles after enabling the rtc read in ab8500 */
while (time_before(jiffies, timeout)) {
retval = abx500_get_register_interruptible(dev,
AB8500_RTC, AB8500_RTC_READ_REQ_REG, &value);
if (retval < 0)
return retval;
if (!(value & RTC_READ_REQUEST))
break;
usleep_range(1000, 5000);
}
/* Read the Watchtime registers */
for (i = 0; i < ARRAY_SIZE(ab8500_rtc_time_regs); i++) {
retval = abx500_get_register_interruptible(dev,
AB8500_RTC, ab8500_rtc_time_regs[i], &value);
if (retval < 0)
return retval;
buf[i] = value;
}
mins = (buf[0] << 16) | (buf[1] << 8) | buf[2];
secs = (buf[3] << 8) | buf[4];
secs = secs / COUNTS_PER_SEC;
secs = secs + (mins * 60);
rtc_time64_to_tm(secs, tm);
return 0;
}
static int ab8500_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
int retval, i;
unsigned char buf[ARRAY_SIZE(ab8500_rtc_time_regs)];
unsigned long no_secs, no_mins, secs = 0;
secs = rtc_tm_to_time64(tm);
no_mins = secs / 60;
no_secs = secs % 60;
/* Make the seconds count as per the RTC resolution */
no_secs = no_secs * COUNTS_PER_SEC;
buf[4] = no_secs & 0xFF;
buf[3] = (no_secs >> 8) & 0xFF;
buf[2] = no_mins & 0xFF;
buf[1] = (no_mins >> 8) & 0xFF;
buf[0] = (no_mins >> 16) & 0xFF;
for (i = 0; i < ARRAY_SIZE(ab8500_rtc_time_regs); i++) {
retval = abx500_set_register_interruptible(dev, AB8500_RTC,
ab8500_rtc_time_regs[i], buf[i]);
if (retval < 0)
return retval;
}
/* Request a data write */
return abx500_set_register_interruptible(dev, AB8500_RTC,
AB8500_RTC_READ_REQ_REG, RTC_WRITE_REQUEST);
}
static int ab8500_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
int retval, i;
u8 rtc_ctrl, value;
unsigned char buf[ARRAY_SIZE(ab8500_rtc_alarm_regs)];
unsigned long secs, mins;
/* Check if the alarm is enabled or not */
retval = abx500_get_register_interruptible(dev, AB8500_RTC,
AB8500_RTC_STAT_REG, &rtc_ctrl);
if (retval < 0)
return retval;
if (rtc_ctrl & RTC_ALARM_ENA)
alarm->enabled = 1;
else
alarm->enabled = 0;
alarm->pending = 0;
for (i = 0; i < ARRAY_SIZE(ab8500_rtc_alarm_regs); i++) {
retval = abx500_get_register_interruptible(dev, AB8500_RTC,
ab8500_rtc_alarm_regs[i], &value);
if (retval < 0)
return retval;
buf[i] = value;
}
mins = (buf[0] << 16) | (buf[1] << 8) | (buf[2]);
secs = mins * 60;
rtc_time64_to_tm(secs, &alarm->time);
return 0;
}
static int ab8500_rtc_irq_enable(struct device *dev, unsigned int enabled)
{
return abx500_mask_and_set_register_interruptible(dev, AB8500_RTC,
AB8500_RTC_STAT_REG, RTC_ALARM_ENA,
enabled ? RTC_ALARM_ENA : 0);
}
static int ab8500_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
int retval, i;
unsigned char buf[ARRAY_SIZE(ab8500_rtc_alarm_regs)];
unsigned long mins;
mins = (unsigned long)rtc_tm_to_time64(&alarm->time) / 60;
buf[2] = mins & 0xFF;
buf[1] = (mins >> 8) & 0xFF;
buf[0] = (mins >> 16) & 0xFF;
/* Set the alarm time */
for (i = 0; i < ARRAY_SIZE(ab8500_rtc_alarm_regs); i++) {
retval = abx500_set_register_interruptible(dev, AB8500_RTC,
ab8500_rtc_alarm_regs[i], buf[i]);
if (retval < 0)
return retval;
}
return ab8500_rtc_irq_enable(dev, alarm->enabled);
}
static int ab8500_rtc_set_calibration(struct device *dev, int calibration)
{
int retval;
u8 rtccal = 0;
/*
* Check that the calibration value (which is in units of 0.5
* parts-per-million) is in the AB8500's range for RtcCalibration
* register. -128 (0x80) is not permitted because the AB8500 uses
* a sign-bit rather than two's complement, so 0x80 is just another
* representation of zero.
*/
if ((calibration < -127) || (calibration > 127)) {
dev_err(dev, "RtcCalibration value outside permitted range\n");
return -EINVAL;
}
/*
* The AB8500 uses sign (in bit7) and magnitude (in bits0-7)
* so need to convert to this sort of representation before writing
* into RtcCalibration register...
*/
if (calibration >= 0)
rtccal = 0x7F & calibration;
else
rtccal = ~(calibration - 1) | 0x80;
retval = abx500_set_register_interruptible(dev, AB8500_RTC,
AB8500_RTC_CALIB_REG, rtccal);
return retval;
}
static int ab8500_rtc_get_calibration(struct device *dev, int *calibration)
{
int retval;
u8 rtccal = 0;
retval = abx500_get_register_interruptible(dev, AB8500_RTC,
AB8500_RTC_CALIB_REG, &rtccal);
if (retval >= 0) {
/*
* The AB8500 uses sign (in bit7) and magnitude (in bits0-7)
* so need to convert value from RtcCalibration register into
* a two's complement signed value...
*/
if (rtccal & 0x80)
*calibration = 0 - (rtccal & 0x7F);
else
*calibration = 0x7F & rtccal;
}
return retval;
}
static ssize_t ab8500_sysfs_store_rtc_calibration(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int retval;
int calibration = 0;
if (sscanf(buf, " %i ", &calibration) != 1) {
dev_err(dev, "Failed to store RTC calibration attribute\n");
return -EINVAL;
}
retval = ab8500_rtc_set_calibration(dev, calibration);
return retval ? retval : count;
}
static ssize_t ab8500_sysfs_show_rtc_calibration(struct device *dev,
struct device_attribute *attr, char *buf)
{
int retval = 0;
int calibration = 0;
retval = ab8500_rtc_get_calibration(dev, &calibration);
if (retval < 0) {
dev_err(dev, "Failed to read RTC calibration attribute\n");
sprintf(buf, "0\n");
return retval;
}
return sprintf(buf, "%d\n", calibration);
}
static DEVICE_ATTR(rtc_calibration, S_IRUGO | S_IWUSR,
ab8500_sysfs_show_rtc_calibration,
ab8500_sysfs_store_rtc_calibration);
static struct attribute *ab8500_rtc_attrs[] = {
&dev_attr_rtc_calibration.attr,
NULL
};
static const struct attribute_group ab8500_rtc_sysfs_files = {
.attrs = ab8500_rtc_attrs,
};
static irqreturn_t rtc_alarm_handler(int irq, void *data)
{
struct rtc_device *rtc = data;
unsigned long events = RTC_IRQF | RTC_AF;
dev_dbg(&rtc->dev, "%s\n", __func__);
rtc_update_irq(rtc, 1, events);
return IRQ_HANDLED;
}
static const struct rtc_class_ops ab8500_rtc_ops = {
.read_time = ab8500_rtc_read_time,
.set_time = ab8500_rtc_set_time,
.read_alarm = ab8500_rtc_read_alarm,
.set_alarm = ab8500_rtc_set_alarm,
.alarm_irq_enable = ab8500_rtc_irq_enable,
};
static const struct platform_device_id ab85xx_rtc_ids[] = {
{ "ab8500-rtc", (kernel_ulong_t)&ab8500_rtc_ops, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, ab85xx_rtc_ids);
static int ab8500_rtc_probe(struct platform_device *pdev)
{
const struct platform_device_id *platid = platform_get_device_id(pdev);
int err;
struct rtc_device *rtc;
u8 rtc_ctrl;
int irq;
irq = platform_get_irq_byname(pdev, "ALARM");
if (irq < 0)
return irq;
/* For RTC supply test */
err = abx500_mask_and_set_register_interruptible(&pdev->dev, AB8500_RTC,
AB8500_RTC_STAT_REG, RTC_STATUS_DATA, RTC_STATUS_DATA);
if (err < 0)
return err;
/* Wait for reset by the PorRtc */
usleep_range(1000, 5000);
err = abx500_get_register_interruptible(&pdev->dev, AB8500_RTC,
AB8500_RTC_STAT_REG, &rtc_ctrl);
if (err < 0)
return err;
/* Check if the RTC Supply fails */
if (!(rtc_ctrl & RTC_STATUS_DATA)) {
dev_err(&pdev->dev, "RTC supply failure\n");
return -ENODEV;
}
device_init_wakeup(&pdev->dev, true);
rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = (struct rtc_class_ops *)platid->driver_data;
err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
rtc_alarm_handler, IRQF_ONESHOT,
"ab8500-rtc", rtc);
if (err < 0)
return err;
dev_pm_set_wake_irq(&pdev->dev, irq);
platform_set_drvdata(pdev, rtc);
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->features);
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->features);
rtc->range_max = (1ULL << 24) * 60 - 1; // 24-bit minutes + 59 secs
rtc->start_secs = RTC_TIMESTAMP_BEGIN_2000;
rtc->set_start_time = true;
err = rtc_add_group(rtc, &ab8500_rtc_sysfs_files);
if (err)
return err;
return devm_rtc_register_device(rtc);
}
static void ab8500_rtc_remove(struct platform_device *pdev)
{
dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
}
static struct platform_driver ab8500_rtc_driver = {
.driver = {
.name = "ab8500-rtc",
},
.probe = ab8500_rtc_probe,
.remove_new = ab8500_rtc_remove,
.id_table = ab85xx_rtc_ids,
};
module_platform_driver(ab8500_rtc_driver);
MODULE_AUTHOR("Virupax Sadashivpetimath <[email protected]>");
MODULE_DESCRIPTION("AB8500 RTC Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-ab8500.c |
// SPDX-License-Identifier: GPL-2.0
/*
* A driver for the RTC embedded in the Cirrus Logic EP93XX processors
* Copyright (c) 2006 Tower Technologies
*
* Author: Alessandro Zummo <[email protected]>
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gfp.h>
#define EP93XX_RTC_DATA 0x000
#define EP93XX_RTC_MATCH 0x004
#define EP93XX_RTC_STATUS 0x008
#define EP93XX_RTC_STATUS_INTR BIT(0)
#define EP93XX_RTC_LOAD 0x00C
#define EP93XX_RTC_CONTROL 0x010
#define EP93XX_RTC_CONTROL_MIE BIT(0)
#define EP93XX_RTC_SWCOMP 0x108
#define EP93XX_RTC_SWCOMP_DEL_MASK 0x001f0000
#define EP93XX_RTC_SWCOMP_DEL_SHIFT 16
#define EP93XX_RTC_SWCOMP_INT_MASK 0x0000ffff
#define EP93XX_RTC_SWCOMP_INT_SHIFT 0
struct ep93xx_rtc {
void __iomem *mmio_base;
struct rtc_device *rtc;
};
static int ep93xx_rtc_get_swcomp(struct device *dev, unsigned short *preload,
unsigned short *delete)
{
struct ep93xx_rtc *ep93xx_rtc = dev_get_drvdata(dev);
unsigned long comp;
comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP);
if (preload)
*preload = (comp & EP93XX_RTC_SWCOMP_INT_MASK)
>> EP93XX_RTC_SWCOMP_INT_SHIFT;
if (delete)
*delete = (comp & EP93XX_RTC_SWCOMP_DEL_MASK)
>> EP93XX_RTC_SWCOMP_DEL_SHIFT;
return 0;
}
static int ep93xx_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct ep93xx_rtc *ep93xx_rtc = dev_get_drvdata(dev);
unsigned long time;
time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA);
rtc_time64_to_tm(time, tm);
return 0;
}
static int ep93xx_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct ep93xx_rtc *ep93xx_rtc = dev_get_drvdata(dev);
unsigned long secs = rtc_tm_to_time64(tm);
writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD);
return 0;
}
static int ep93xx_rtc_proc(struct device *dev, struct seq_file *seq)
{
unsigned short preload, delete;
ep93xx_rtc_get_swcomp(dev, &preload, &delete);
seq_printf(seq, "preload\t\t: %d\n", preload);
seq_printf(seq, "delete\t\t: %d\n", delete);
return 0;
}
static const struct rtc_class_ops ep93xx_rtc_ops = {
.read_time = ep93xx_rtc_read_time,
.set_time = ep93xx_rtc_set_time,
.proc = ep93xx_rtc_proc,
};
static ssize_t comp_preload_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
unsigned short preload;
ep93xx_rtc_get_swcomp(dev->parent, &preload, NULL);
return sprintf(buf, "%d\n", preload);
}
static DEVICE_ATTR_RO(comp_preload);
static ssize_t comp_delete_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
unsigned short delete;
ep93xx_rtc_get_swcomp(dev->parent, NULL, &delete);
return sprintf(buf, "%d\n", delete);
}
static DEVICE_ATTR_RO(comp_delete);
static struct attribute *ep93xx_rtc_attrs[] = {
&dev_attr_comp_preload.attr,
&dev_attr_comp_delete.attr,
NULL
};
static const struct attribute_group ep93xx_rtc_sysfs_files = {
.attrs = ep93xx_rtc_attrs,
};
static int ep93xx_rtc_probe(struct platform_device *pdev)
{
struct ep93xx_rtc *ep93xx_rtc;
int err;
ep93xx_rtc = devm_kzalloc(&pdev->dev, sizeof(*ep93xx_rtc), GFP_KERNEL);
if (!ep93xx_rtc)
return -ENOMEM;
ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ep93xx_rtc->mmio_base))
return PTR_ERR(ep93xx_rtc->mmio_base);
platform_set_drvdata(pdev, ep93xx_rtc);
ep93xx_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(ep93xx_rtc->rtc))
return PTR_ERR(ep93xx_rtc->rtc);
ep93xx_rtc->rtc->ops = &ep93xx_rtc_ops;
ep93xx_rtc->rtc->range_max = U32_MAX;
err = rtc_add_group(ep93xx_rtc->rtc, &ep93xx_rtc_sysfs_files);
if (err)
return err;
return devm_rtc_register_device(ep93xx_rtc->rtc);
}
static struct platform_driver ep93xx_rtc_driver = {
.driver = {
.name = "ep93xx-rtc",
},
.probe = ep93xx_rtc_probe,
};
module_platform_driver(ep93xx_rtc_driver);
MODULE_AUTHOR("Alessandro Zummo <[email protected]>");
MODULE_DESCRIPTION("EP93XX RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ep93xx-rtc");
| linux-master | drivers/rtc/rtc-ep93xx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for MediaTek SoC based RTC
*
* Copyright (C) 2017 Sean Wang <[email protected]>
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#define MTK_RTC_DEV KBUILD_MODNAME
#define MTK_RTC_PWRCHK1 0x4
#define RTC_PWRCHK1_MAGIC 0xc6
#define MTK_RTC_PWRCHK2 0x8
#define RTC_PWRCHK2_MAGIC 0x9a
#define MTK_RTC_KEY 0xc
#define RTC_KEY_MAGIC 0x59
#define MTK_RTC_PROT1 0x10
#define RTC_PROT1_MAGIC 0xa3
#define MTK_RTC_PROT2 0x14
#define RTC_PROT2_MAGIC 0x57
#define MTK_RTC_PROT3 0x18
#define RTC_PROT3_MAGIC 0x67
#define MTK_RTC_PROT4 0x1c
#define RTC_PROT4_MAGIC 0xd2
#define MTK_RTC_CTL 0x20
#define RTC_RC_STOP BIT(0)
#define MTK_RTC_DEBNCE 0x2c
#define RTC_DEBNCE_MASK GENMASK(2, 0)
#define MTK_RTC_INT 0x30
#define RTC_INT_AL_STA BIT(4)
/*
* Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
* day of month, day of week, hour, minute and second.
*/
#define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
#define MTK_RTC_AL_CTL 0x7c
#define RTC_AL_EN BIT(0)
#define RTC_AL_ALL GENMASK(7, 0)
/*
* The offset is used in the translation for the year between in struct
* rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
*/
#define MTK_RTC_TM_YR_OFFSET 100
/*
* The lowest value for the valid tm_year. RTC hardware would take incorrectly
* tm_year 100 as not a leap year and thus it is also required being excluded
* from the valid options.
*/
#define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1)
/*
* The most year the RTC can hold is 99 and the next to 99 in year register
* would be wraparound to 0, for MT7622.
*/
#define MTK_RTC_HW_YR_LIMIT 99
/* The highest value for the valid tm_year */
#define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
/* Simple macro helps to check whether the hardware supports the tm_year */
#define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \
(_y) <= MTK_RTC_TM_YR_H)
/* Types of the function the RTC provides are time counter and alarm. */
enum {
MTK_TC,
MTK_AL,
};
/* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
enum {
MTK_YEA,
MTK_MON,
MTK_DOM,
MTK_DOW,
MTK_HOU,
MTK_MIN,
MTK_SEC
};
struct mtk_rtc {
struct rtc_device *rtc;
void __iomem *base;
int irq;
struct clk *clk;
};
static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
{
writel_relaxed(val, rtc->base + reg);
}
static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
{
return readl_relaxed(rtc->base + reg);
}
static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
{
u32 val;
val = mtk_r32(rtc, reg);
val &= ~mask;
val |= set;
mtk_w32(rtc, reg, val);
}
static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
{
mtk_rmw(rtc, reg, 0, val);
}
static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
{
mtk_rmw(rtc, reg, val, 0);
}
static void mtk_rtc_hw_init(struct mtk_rtc *hw)
{
/* The setup of the init sequence is for allowing RTC got to work */
mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
}
static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
int time_alarm)
{
u32 year, mon, mday, wday, hour, min, sec;
/*
* Read again until the field of the second is not changed which
* ensures all fields in the consistent state. Note that MTK_SEC must
* be read first. In this way, it guarantees the others remain not
* changed when the results for two MTK_SEC consecutive reads are same.
*/
do {
sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
} while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
tm->tm_sec = sec;
tm->tm_min = min;
tm->tm_hour = hour;
tm->tm_wday = wday;
tm->tm_mday = mday;
tm->tm_mon = mon - 1;
/* Rebase to the absolute year which userspace queries */
tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
}
static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
int time_alarm)
{
u32 year;
/* Rebase to the relative year which RTC hardware requires */
year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
}
static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
{
struct mtk_rtc *hw = (struct mtk_rtc *)id;
u32 irq_sta;
irq_sta = mtk_r32(hw, MTK_RTC_INT);
if (irq_sta & RTC_INT_AL_STA) {
/* Stop alarm also implicitly disables the alarm interrupt */
mtk_w32(hw, MTK_RTC_AL_CTL, 0);
rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
/* Ack alarm interrupt status */
mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
{
struct mtk_rtc *hw = dev_get_drvdata(dev);
mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
return 0;
}
static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct mtk_rtc *hw = dev_get_drvdata(dev);
if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
return -EINVAL;
/* Stop time counter before setting a new one*/
mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
/* Restart the time counter */
mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
return 0;
}
static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
struct mtk_rtc *hw = dev_get_drvdata(dev);
struct rtc_time *alrm_tm = &wkalrm->time;
mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
return 0;
}
static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
struct mtk_rtc *hw = dev_get_drvdata(dev);
struct rtc_time *alrm_tm = &wkalrm->time;
if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
return -EINVAL;
/*
* Stop the alarm also implicitly including disables interrupt before
* setting a new one.
*/
mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
/*
* Avoid contention between mtk_rtc_setalarm and IRQ handler so that
* disabling the interrupt and awaiting for pending IRQ handler to
* complete.
*/
synchronize_irq(hw->irq);
mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
/* Restart the alarm with the new setup */
mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
return 0;
}
static const struct rtc_class_ops mtk_rtc_ops = {
.read_time = mtk_rtc_gettime,
.set_time = mtk_rtc_settime,
.read_alarm = mtk_rtc_getalarm,
.set_alarm = mtk_rtc_setalarm,
};
static const struct of_device_id mtk_rtc_match[] = {
{ .compatible = "mediatek,mt7622-rtc" },
{ .compatible = "mediatek,soc-rtc" },
{},
};
MODULE_DEVICE_TABLE(of, mtk_rtc_match);
static int mtk_rtc_probe(struct platform_device *pdev)
{
struct mtk_rtc *hw;
int ret;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
if (!hw)
return -ENOMEM;
platform_set_drvdata(pdev, hw);
hw->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hw->base))
return PTR_ERR(hw->base);
hw->clk = devm_clk_get(&pdev->dev, "rtc");
if (IS_ERR(hw->clk)) {
dev_err(&pdev->dev, "No clock\n");
return PTR_ERR(hw->clk);
}
ret = clk_prepare_enable(hw->clk);
if (ret)
return ret;
hw->irq = platform_get_irq(pdev, 0);
if (hw->irq < 0) {
ret = hw->irq;
goto err;
}
ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
0, dev_name(&pdev->dev), hw);
if (ret) {
dev_err(&pdev->dev, "Can't request IRQ\n");
goto err;
}
mtk_rtc_hw_init(hw);
device_init_wakeup(&pdev->dev, true);
hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
&mtk_rtc_ops, THIS_MODULE);
if (IS_ERR(hw->rtc)) {
ret = PTR_ERR(hw->rtc);
dev_err(&pdev->dev, "Unable to register device\n");
goto err;
}
return 0;
err:
clk_disable_unprepare(hw->clk);
return ret;
}
static void mtk_rtc_remove(struct platform_device *pdev)
{
struct mtk_rtc *hw = platform_get_drvdata(pdev);
clk_disable_unprepare(hw->clk);
}
#ifdef CONFIG_PM_SLEEP
static int mtk_rtc_suspend(struct device *dev)
{
struct mtk_rtc *hw = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(hw->irq);
return 0;
}
static int mtk_rtc_resume(struct device *dev)
{
struct mtk_rtc *hw = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(hw->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
#define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
#else /* CONFIG_PM */
#define MTK_RTC_PM_OPS NULL
#endif /* CONFIG_PM */
static struct platform_driver mtk_rtc_driver = {
.probe = mtk_rtc_probe,
.remove_new = mtk_rtc_remove,
.driver = {
.name = MTK_RTC_DEV,
.of_match_table = mtk_rtc_match,
.pm = MTK_RTC_PM_OPS,
},
};
module_platform_driver(mtk_rtc_driver);
MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
MODULE_AUTHOR("Sean Wang <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-mt7622.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* rtc-st-lpc.c - ST's LPC RTC, powered by the Low Power Timer
*
* Copyright (C) 2014 STMicroelectronics Limited
*
* Author: David Paris <[email protected]> for STMicroelectronics
* Lee Jones <[email protected]> for STMicroelectronics
*
* Based on the original driver written by Stuart Menefy.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <dt-bindings/mfd/st-lpc.h>
/* Low Power Timer */
#define LPC_LPT_LSB_OFF 0x400
#define LPC_LPT_MSB_OFF 0x404
#define LPC_LPT_START_OFF 0x408
/* Low Power Alarm */
#define LPC_LPA_LSB_OFF 0x410
#define LPC_LPA_MSB_OFF 0x414
#define LPC_LPA_START_OFF 0x418
/* LPC as WDT */
#define LPC_WDT_OFF 0x510
#define LPC_WDT_FLAG_OFF 0x514
struct st_rtc {
struct rtc_device *rtc_dev;
struct rtc_wkalrm alarm;
struct clk *clk;
unsigned long clkrate;
void __iomem *ioaddr;
bool irq_enabled:1;
spinlock_t lock;
short irq;
};
static void st_rtc_set_hw_alarm(struct st_rtc *rtc,
unsigned long msb, unsigned long lsb)
{
unsigned long flags;
spin_lock_irqsave(&rtc->lock, flags);
writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF);
writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF);
writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF);
writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
spin_unlock_irqrestore(&rtc->lock, flags);
}
static irqreturn_t st_rtc_handler(int this_irq, void *data)
{
struct st_rtc *rtc = (struct st_rtc *)data;
rtc_update_irq(rtc->rtc_dev, 1, RTC_AF);
return IRQ_HANDLED;
}
static int st_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
unsigned long lpt_lsb, lpt_msb;
unsigned long long lpt;
unsigned long flags;
spin_lock_irqsave(&rtc->lock, flags);
do {
lpt_msb = readl_relaxed(rtc->ioaddr + LPC_LPT_MSB_OFF);
lpt_lsb = readl_relaxed(rtc->ioaddr + LPC_LPT_LSB_OFF);
} while (readl_relaxed(rtc->ioaddr + LPC_LPT_MSB_OFF) != lpt_msb);
spin_unlock_irqrestore(&rtc->lock, flags);
lpt = ((unsigned long long)lpt_msb << 32) | lpt_lsb;
do_div(lpt, rtc->clkrate);
rtc_time64_to_tm(lpt, tm);
return 0;
}
static int st_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
unsigned long long lpt, secs;
unsigned long flags;
secs = rtc_tm_to_time64(tm);
lpt = (unsigned long long)secs * rtc->clkrate;
spin_lock_irqsave(&rtc->lock, flags);
writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF);
writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF);
writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF);
spin_unlock_irqrestore(&rtc->lock, flags);
return 0;
}
static int st_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&rtc->lock, flags);
memcpy(wkalrm, &rtc->alarm, sizeof(struct rtc_wkalrm));
spin_unlock_irqrestore(&rtc->lock, flags);
return 0;
}
static int st_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
if (enabled && !rtc->irq_enabled) {
enable_irq(rtc->irq);
rtc->irq_enabled = true;
} else if (!enabled && rtc->irq_enabled) {
disable_irq(rtc->irq);
rtc->irq_enabled = false;
}
return 0;
}
static int st_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
struct rtc_time now;
unsigned long long now_secs;
unsigned long long alarm_secs;
unsigned long long lpa;
st_rtc_read_time(dev, &now);
now_secs = rtc_tm_to_time64(&now);
alarm_secs = rtc_tm_to_time64(&t->time);
memcpy(&rtc->alarm, t, sizeof(struct rtc_wkalrm));
/* Now many secs to fire */
alarm_secs -= now_secs;
lpa = (unsigned long long)alarm_secs * rtc->clkrate;
st_rtc_set_hw_alarm(rtc, lpa >> 32, lpa);
st_rtc_alarm_irq_enable(dev, t->enabled);
return 0;
}
static const struct rtc_class_ops st_rtc_ops = {
.read_time = st_rtc_read_time,
.set_time = st_rtc_set_time,
.read_alarm = st_rtc_read_alarm,
.set_alarm = st_rtc_set_alarm,
.alarm_irq_enable = st_rtc_alarm_irq_enable,
};
static int st_rtc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct st_rtc *rtc;
uint32_t mode;
int ret = 0;
ret = of_property_read_u32(np, "st,lpc-mode", &mode);
if (ret) {
dev_err(&pdev->dev, "An LPC mode must be provided\n");
return -EINVAL;
}
/* LPC can either run as a Clocksource or in RTC or WDT mode */
if (mode != ST_LPC_MODE_RTC)
return -ENODEV;
rtc = devm_kzalloc(&pdev->dev, sizeof(struct st_rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc_dev))
return PTR_ERR(rtc->rtc_dev);
spin_lock_init(&rtc->lock);
rtc->ioaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->ioaddr))
return PTR_ERR(rtc->ioaddr);
rtc->irq = irq_of_parse_and_map(np, 0);
if (!rtc->irq) {
dev_err(&pdev->dev, "IRQ missing or invalid\n");
return -EINVAL;
}
ret = devm_request_irq(&pdev->dev, rtc->irq, st_rtc_handler, 0,
pdev->name, rtc);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq %i\n", rtc->irq);
return ret;
}
enable_irq_wake(rtc->irq);
disable_irq(rtc->irq);
rtc->clk = devm_clk_get_enabled(&pdev->dev, NULL);
if (IS_ERR(rtc->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk),
"Unable to request clock\n");
rtc->clkrate = clk_get_rate(rtc->clk);
if (!rtc->clkrate) {
dev_err(&pdev->dev, "Unable to fetch clock rate\n");
return -EINVAL;
}
device_set_wakeup_capable(&pdev->dev, 1);
platform_set_drvdata(pdev, rtc);
rtc->rtc_dev->ops = &st_rtc_ops;
rtc->rtc_dev->range_max = U64_MAX;
do_div(rtc->rtc_dev->range_max, rtc->clkrate);
ret = devm_rtc_register_device(rtc->rtc_dev);
if (ret)
return ret;
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int st_rtc_suspend(struct device *dev)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
return 0;
writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF);
writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
return 0;
}
static int st_rtc_resume(struct device *dev)
{
struct st_rtc *rtc = dev_get_drvdata(dev);
rtc_alarm_irq_enable(rtc->rtc_dev, 0);
/*
* clean 'rtc->alarm' to allow a new
* .set_alarm to the upper RTC layer
*/
memset(&rtc->alarm, 0, sizeof(struct rtc_wkalrm));
writel_relaxed(0, rtc->ioaddr + LPC_LPA_MSB_OFF);
writel_relaxed(0, rtc->ioaddr + LPC_LPA_LSB_OFF);
writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF);
writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF);
writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(st_rtc_pm_ops, st_rtc_suspend, st_rtc_resume);
static const struct of_device_id st_rtc_match[] = {
{ .compatible = "st,stih407-lpc" },
{}
};
MODULE_DEVICE_TABLE(of, st_rtc_match);
static struct platform_driver st_rtc_platform_driver = {
.driver = {
.name = "st-lpc-rtc",
.pm = &st_rtc_pm_ops,
.of_match_table = st_rtc_match,
},
.probe = st_rtc_probe,
};
module_platform_driver(st_rtc_platform_driver);
MODULE_DESCRIPTION("STMicroelectronics LPC RTC driver");
MODULE_AUTHOR("David Paris <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-st-lpc.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Real time clock device driver for DA9063
* Copyright (C) 2013-2015 Dialog Semiconductor Ltd.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/mfd/da9062/registers.h>
#include <linux/mfd/da9063/registers.h>
#include <linux/mfd/da9063/core.h>
#define YEARS_TO_DA9063(year) ((year) - 100)
#define MONTHS_TO_DA9063(month) ((month) + 1)
#define YEARS_FROM_DA9063(year) ((year) + 100)
#define MONTHS_FROM_DA9063(month) ((month) - 1)
enum {
RTC_SEC = 0,
RTC_MIN = 1,
RTC_HOUR = 2,
RTC_DAY = 3,
RTC_MONTH = 4,
RTC_YEAR = 5,
RTC_DATA_LEN
};
struct da9063_compatible_rtc_regmap {
/* REGS */
int rtc_enable_reg;
int rtc_enable_32k_crystal_reg;
int rtc_alarm_secs_reg;
int rtc_alarm_year_reg;
int rtc_count_secs_reg;
int rtc_count_year_reg;
int rtc_event_reg;
/* MASKS */
int rtc_enable_mask;
int rtc_crystal_mask;
int rtc_event_alarm_mask;
int rtc_alarm_on_mask;
int rtc_alarm_status_mask;
int rtc_tick_on_mask;
int rtc_ready_to_read_mask;
int rtc_count_sec_mask;
int rtc_count_min_mask;
int rtc_count_hour_mask;
int rtc_count_day_mask;
int rtc_count_month_mask;
int rtc_count_year_mask;
/* ALARM CONFIG */
int rtc_data_start;
int rtc_alarm_len;
};
struct da9063_compatible_rtc {
struct rtc_device *rtc_dev;
struct rtc_time alarm_time;
struct regmap *regmap;
const struct da9063_compatible_rtc_regmap *config;
bool rtc_sync;
};
static const struct da9063_compatible_rtc_regmap da9063_ad_regs = {
/* REGS */
.rtc_enable_reg = DA9063_REG_CONTROL_E,
.rtc_alarm_secs_reg = DA9063_AD_REG_ALARM_MI,
.rtc_alarm_year_reg = DA9063_AD_REG_ALARM_Y,
.rtc_count_secs_reg = DA9063_REG_COUNT_S,
.rtc_count_year_reg = DA9063_REG_COUNT_Y,
.rtc_event_reg = DA9063_REG_EVENT_A,
/* MASKS */
.rtc_enable_mask = DA9063_RTC_EN,
.rtc_crystal_mask = DA9063_CRYSTAL,
.rtc_enable_32k_crystal_reg = DA9063_REG_EN_32K,
.rtc_event_alarm_mask = DA9063_E_ALARM,
.rtc_alarm_on_mask = DA9063_ALARM_ON,
.rtc_alarm_status_mask = DA9063_ALARM_STATUS_ALARM |
DA9063_ALARM_STATUS_TICK,
.rtc_tick_on_mask = DA9063_TICK_ON,
.rtc_ready_to_read_mask = DA9063_RTC_READ,
.rtc_count_sec_mask = DA9063_COUNT_SEC_MASK,
.rtc_count_min_mask = DA9063_COUNT_MIN_MASK,
.rtc_count_hour_mask = DA9063_COUNT_HOUR_MASK,
.rtc_count_day_mask = DA9063_COUNT_DAY_MASK,
.rtc_count_month_mask = DA9063_COUNT_MONTH_MASK,
.rtc_count_year_mask = DA9063_COUNT_YEAR_MASK,
/* ALARM CONFIG */
.rtc_data_start = RTC_MIN,
.rtc_alarm_len = RTC_DATA_LEN - 1,
};
static const struct da9063_compatible_rtc_regmap da9063_bb_regs = {
/* REGS */
.rtc_enable_reg = DA9063_REG_CONTROL_E,
.rtc_alarm_secs_reg = DA9063_BB_REG_ALARM_S,
.rtc_alarm_year_reg = DA9063_BB_REG_ALARM_Y,
.rtc_count_secs_reg = DA9063_REG_COUNT_S,
.rtc_count_year_reg = DA9063_REG_COUNT_Y,
.rtc_event_reg = DA9063_REG_EVENT_A,
/* MASKS */
.rtc_enable_mask = DA9063_RTC_EN,
.rtc_crystal_mask = DA9063_CRYSTAL,
.rtc_enable_32k_crystal_reg = DA9063_REG_EN_32K,
.rtc_event_alarm_mask = DA9063_E_ALARM,
.rtc_alarm_on_mask = DA9063_ALARM_ON,
.rtc_alarm_status_mask = DA9063_ALARM_STATUS_ALARM |
DA9063_ALARM_STATUS_TICK,
.rtc_tick_on_mask = DA9063_TICK_ON,
.rtc_ready_to_read_mask = DA9063_RTC_READ,
.rtc_count_sec_mask = DA9063_COUNT_SEC_MASK,
.rtc_count_min_mask = DA9063_COUNT_MIN_MASK,
.rtc_count_hour_mask = DA9063_COUNT_HOUR_MASK,
.rtc_count_day_mask = DA9063_COUNT_DAY_MASK,
.rtc_count_month_mask = DA9063_COUNT_MONTH_MASK,
.rtc_count_year_mask = DA9063_COUNT_YEAR_MASK,
/* ALARM CONFIG */
.rtc_data_start = RTC_SEC,
.rtc_alarm_len = RTC_DATA_LEN,
};
static const struct da9063_compatible_rtc_regmap da9062_aa_regs = {
/* REGS */
.rtc_enable_reg = DA9062AA_CONTROL_E,
.rtc_alarm_secs_reg = DA9062AA_ALARM_S,
.rtc_alarm_year_reg = DA9062AA_ALARM_Y,
.rtc_count_secs_reg = DA9062AA_COUNT_S,
.rtc_count_year_reg = DA9062AA_COUNT_Y,
.rtc_event_reg = DA9062AA_EVENT_A,
/* MASKS */
.rtc_enable_mask = DA9062AA_RTC_EN_MASK,
.rtc_crystal_mask = DA9062AA_CRYSTAL_MASK,
.rtc_enable_32k_crystal_reg = DA9062AA_EN_32K,
.rtc_event_alarm_mask = DA9062AA_M_ALARM_MASK,
.rtc_alarm_on_mask = DA9062AA_ALARM_ON_MASK,
.rtc_alarm_status_mask = (0x02 << 6),
.rtc_tick_on_mask = DA9062AA_TICK_ON_MASK,
.rtc_ready_to_read_mask = DA9062AA_RTC_READ_MASK,
.rtc_count_sec_mask = DA9062AA_COUNT_SEC_MASK,
.rtc_count_min_mask = DA9062AA_COUNT_MIN_MASK,
.rtc_count_hour_mask = DA9062AA_COUNT_HOUR_MASK,
.rtc_count_day_mask = DA9062AA_COUNT_DAY_MASK,
.rtc_count_month_mask = DA9062AA_COUNT_MONTH_MASK,
.rtc_count_year_mask = DA9062AA_COUNT_YEAR_MASK,
/* ALARM CONFIG */
.rtc_data_start = RTC_SEC,
.rtc_alarm_len = RTC_DATA_LEN,
};
static const struct of_device_id da9063_compatible_reg_id_table[] = {
{ .compatible = "dlg,da9063-rtc", .data = &da9063_bb_regs },
{ .compatible = "dlg,da9062-rtc", .data = &da9062_aa_regs },
{ },
};
MODULE_DEVICE_TABLE(of, da9063_compatible_reg_id_table);
static void da9063_data_to_tm(u8 *data, struct rtc_time *tm,
struct da9063_compatible_rtc *rtc)
{
const struct da9063_compatible_rtc_regmap *config = rtc->config;
tm->tm_sec = data[RTC_SEC] & config->rtc_count_sec_mask;
tm->tm_min = data[RTC_MIN] & config->rtc_count_min_mask;
tm->tm_hour = data[RTC_HOUR] & config->rtc_count_hour_mask;
tm->tm_mday = data[RTC_DAY] & config->rtc_count_day_mask;
tm->tm_mon = MONTHS_FROM_DA9063(data[RTC_MONTH] &
config->rtc_count_month_mask);
tm->tm_year = YEARS_FROM_DA9063(data[RTC_YEAR] &
config->rtc_count_year_mask);
}
static void da9063_tm_to_data(struct rtc_time *tm, u8 *data,
struct da9063_compatible_rtc *rtc)
{
const struct da9063_compatible_rtc_regmap *config = rtc->config;
data[RTC_SEC] = tm->tm_sec & config->rtc_count_sec_mask;
data[RTC_MIN] = tm->tm_min & config->rtc_count_min_mask;
data[RTC_HOUR] = tm->tm_hour & config->rtc_count_hour_mask;
data[RTC_DAY] = tm->tm_mday & config->rtc_count_day_mask;
data[RTC_MONTH] = MONTHS_TO_DA9063(tm->tm_mon) &
config->rtc_count_month_mask;
data[RTC_YEAR] = YEARS_TO_DA9063(tm->tm_year) &
config->rtc_count_year_mask;
}
static int da9063_rtc_stop_alarm(struct device *dev)
{
struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
const struct da9063_compatible_rtc_regmap *config = rtc->config;
return regmap_update_bits(rtc->regmap,
config->rtc_alarm_year_reg,
config->rtc_alarm_on_mask,
0);
}
static int da9063_rtc_start_alarm(struct device *dev)
{
struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
const struct da9063_compatible_rtc_regmap *config = rtc->config;
return regmap_update_bits(rtc->regmap,
config->rtc_alarm_year_reg,
config->rtc_alarm_on_mask,
config->rtc_alarm_on_mask);
}
static int da9063_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
const struct da9063_compatible_rtc_regmap *config = rtc->config;
unsigned long tm_secs;
unsigned long al_secs;
u8 data[RTC_DATA_LEN];
int ret;
ret = regmap_bulk_read(rtc->regmap,
config->rtc_count_secs_reg,
data, RTC_DATA_LEN);
if (ret < 0) {
dev_err(dev, "Failed to read RTC time data: %d\n", ret);
return ret;
}
if (!(data[RTC_SEC] & config->rtc_ready_to_read_mask)) {
dev_dbg(dev, "RTC not yet ready to be read by the host\n");
return -EINVAL;
}
da9063_data_to_tm(data, tm, rtc);
tm_secs = rtc_tm_to_time64(tm);
al_secs = rtc_tm_to_time64(&rtc->alarm_time);
/* handle the rtc synchronisation delay */
if (rtc->rtc_sync && al_secs - tm_secs == 1)
memcpy(tm, &rtc->alarm_time, sizeof(struct rtc_time));
else
rtc->rtc_sync = false;
return 0;
}
static int da9063_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
const struct da9063_compatible_rtc_regmap *config = rtc->config;
u8 data[RTC_DATA_LEN];
int ret;
da9063_tm_to_data(tm, data, rtc);
ret = regmap_bulk_write(rtc->regmap,
config->rtc_count_secs_reg,
data, RTC_DATA_LEN);
if (ret < 0)
dev_err(dev, "Failed to set RTC time data: %d\n", ret);
return ret;
}
static int da9063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
const struct da9063_compatible_rtc_regmap *config = rtc->config;
u8 data[RTC_DATA_LEN];
int ret;
unsigned int val;
data[RTC_SEC] = 0;
ret = regmap_bulk_read(rtc->regmap,
config->rtc_alarm_secs_reg,
&data[config->rtc_data_start],
config->rtc_alarm_len);
if (ret < 0)
return ret;
da9063_data_to_tm(data, &alrm->time, rtc);
alrm->enabled = !!(data[RTC_YEAR] & config->rtc_alarm_on_mask);
ret = regmap_read(rtc->regmap,
config->rtc_event_reg,
&val);
if (ret < 0)
return ret;
if (val & config->rtc_event_alarm_mask)
alrm->pending = 1;
else
alrm->pending = 0;
return 0;
}
static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
const struct da9063_compatible_rtc_regmap *config = rtc->config;
u8 data[RTC_DATA_LEN];
int ret;
da9063_tm_to_data(&alrm->time, data, rtc);
ret = da9063_rtc_stop_alarm(dev);
if (ret < 0) {
dev_err(dev, "Failed to stop alarm: %d\n", ret);
return ret;
}
ret = regmap_bulk_write(rtc->regmap,
config->rtc_alarm_secs_reg,
&data[config->rtc_data_start],
config->rtc_alarm_len);
if (ret < 0) {
dev_err(dev, "Failed to write alarm: %d\n", ret);
return ret;
}
da9063_data_to_tm(data, &rtc->alarm_time, rtc);
if (alrm->enabled) {
ret = da9063_rtc_start_alarm(dev);
if (ret < 0) {
dev_err(dev, "Failed to start alarm: %d\n", ret);
return ret;
}
}
return ret;
}
static int da9063_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
if (enabled)
return da9063_rtc_start_alarm(dev);
else
return da9063_rtc_stop_alarm(dev);
}
static irqreturn_t da9063_alarm_event(int irq, void *data)
{
struct da9063_compatible_rtc *rtc = data;
const struct da9063_compatible_rtc_regmap *config = rtc->config;
regmap_update_bits(rtc->regmap,
config->rtc_alarm_year_reg,
config->rtc_alarm_on_mask,
0);
rtc->rtc_sync = true;
rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static const struct rtc_class_ops da9063_rtc_ops = {
.read_time = da9063_rtc_read_time,
.set_time = da9063_rtc_set_time,
.read_alarm = da9063_rtc_read_alarm,
.set_alarm = da9063_rtc_set_alarm,
.alarm_irq_enable = da9063_rtc_alarm_irq_enable,
};
static int da9063_rtc_probe(struct platform_device *pdev)
{
struct da9063_compatible_rtc *rtc;
const struct da9063_compatible_rtc_regmap *config;
const struct of_device_id *match;
int irq_alarm;
u8 data[RTC_DATA_LEN];
int ret;
if (!pdev->dev.of_node)
return -ENXIO;
match = of_match_node(da9063_compatible_reg_id_table,
pdev->dev.of_node);
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->config = match->data;
if (of_device_is_compatible(pdev->dev.of_node, "dlg,da9063-rtc")) {
struct da9063 *chip = dev_get_drvdata(pdev->dev.parent);
if (chip->variant_code == PMIC_DA9063_AD)
rtc->config = &da9063_ad_regs;
}
rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!rtc->regmap) {
dev_warn(&pdev->dev, "Parent regmap unavailable.\n");
return -ENXIO;
}
config = rtc->config;
ret = regmap_update_bits(rtc->regmap,
config->rtc_enable_reg,
config->rtc_enable_mask,
config->rtc_enable_mask);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to enable RTC\n");
return ret;
}
ret = regmap_update_bits(rtc->regmap,
config->rtc_enable_32k_crystal_reg,
config->rtc_crystal_mask,
config->rtc_crystal_mask);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to run 32kHz oscillator\n");
return ret;
}
ret = regmap_update_bits(rtc->regmap,
config->rtc_alarm_secs_reg,
config->rtc_alarm_status_mask,
0);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to access RTC alarm register\n");
return ret;
}
ret = regmap_update_bits(rtc->regmap,
config->rtc_alarm_secs_reg,
DA9063_ALARM_STATUS_ALARM,
DA9063_ALARM_STATUS_ALARM);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to access RTC alarm register\n");
return ret;
}
ret = regmap_update_bits(rtc->regmap,
config->rtc_alarm_year_reg,
config->rtc_tick_on_mask,
0);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to disable TICKs\n");
return ret;
}
data[RTC_SEC] = 0;
ret = regmap_bulk_read(rtc->regmap,
config->rtc_alarm_secs_reg,
&data[config->rtc_data_start],
config->rtc_alarm_len);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n",
ret);
return ret;
}
platform_set_drvdata(pdev, rtc);
rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc_dev))
return PTR_ERR(rtc->rtc_dev);
rtc->rtc_dev->ops = &da9063_rtc_ops;
rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_2063;
da9063_data_to_tm(data, &rtc->alarm_time, rtc);
rtc->rtc_sync = false;
if (config->rtc_data_start != RTC_SEC) {
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtc_dev->features);
/*
* TODO: some models have alarms on a minute boundary but still
* support real hardware interrupts.
*/
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtc_dev->features);
}
irq_alarm = platform_get_irq_byname(pdev, "ALARM");
if (irq_alarm < 0)
return irq_alarm;
ret = devm_request_threaded_irq(&pdev->dev, irq_alarm, NULL,
da9063_alarm_event,
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
"ALARM", rtc);
if (ret)
dev_err(&pdev->dev, "Failed to request ALARM IRQ %d: %d\n",
irq_alarm, ret);
ret = dev_pm_set_wake_irq(&pdev->dev, irq_alarm);
if (ret)
dev_warn(&pdev->dev,
"Failed to set IRQ %d as a wake IRQ: %d\n",
irq_alarm, ret);
device_init_wakeup(&pdev->dev, true);
return devm_rtc_register_device(rtc->rtc_dev);
}
static struct platform_driver da9063_rtc_driver = {
.probe = da9063_rtc_probe,
.driver = {
.name = DA9063_DRVNAME_RTC,
.of_match_table = da9063_compatible_reg_id_table,
},
};
module_platform_driver(da9063_rtc_driver);
MODULE_AUTHOR("S Twiss <[email protected]>");
MODULE_DESCRIPTION("Real time clock device driver for Dialog DA9063");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DA9063_DRVNAME_RTC);
| linux-master | drivers/rtc/rtc-da9063.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* drivers/rtc/rtc-rc5t619.c
*
* Real time clock driver for RICOH RC5T619 power management chip.
*
* Copyright (C) 2019 Andreas Kemnade
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mfd/rn5t618.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/irqdomain.h>
struct rc5t619_rtc {
int irq;
struct rtc_device *rtc;
struct rn5t618 *rn5t618;
};
#define CTRL1_ALARM_ENABLED 0x40
#define CTRL1_24HR 0x20
#define CTRL1_PERIODIC_MASK 0xf
#define CTRL2_PON 0x10
#define CTRL2_ALARM_STATUS 0x80
#define CTRL2_CTFG 0x4
#define CTRL2_CTC 0x1
#define MONTH_CENTFLAG 0x80
#define HOUR_PMFLAG 0x20
#define MDAY_DAL_EXT 0x80
static uint8_t rtc5t619_12hour_bcd2bin(uint8_t hour)
{
if (hour & HOUR_PMFLAG) {
hour = bcd2bin(hour & ~HOUR_PMFLAG);
return hour == 12 ? 12 : 12 + hour;
}
hour = bcd2bin(hour);
return hour == 12 ? 0 : hour;
}
static uint8_t rtc5t619_12hour_bin2bcd(uint8_t hour)
{
if (!hour)
return 0x12;
if (hour < 12)
return bin2bcd(hour);
if (hour == 12)
return 0x12 | HOUR_PMFLAG;
return bin2bcd(hour - 12) | HOUR_PMFLAG;
}
static int rc5t619_rtc_periodic_disable(struct device *dev)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
int err;
/* disable function */
err = regmap_update_bits(rtc->rn5t618->regmap,
RN5T618_RTC_CTRL1, CTRL1_PERIODIC_MASK, 0);
if (err < 0)
return err;
/* clear alarm flag and CTFG */
err = regmap_update_bits(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2,
CTRL2_ALARM_STATUS | CTRL2_CTFG | CTRL2_CTC,
0);
if (err < 0)
return err;
return 0;
}
/* things to be done once after power on */
static int rc5t619_rtc_pon_setup(struct device *dev)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
int err;
unsigned int reg_data;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, ®_data);
if (err < 0)
return err;
/* clear VDET PON */
reg_data &= ~(CTRL2_PON | CTRL2_CTC | 0x4a); /* 0101-1011 */
reg_data |= 0x20; /* 0010-0000 */
err = regmap_write(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, reg_data);
if (err < 0)
return err;
/* clearing RTC Adjust register */
err = regmap_write(rtc->rn5t618->regmap, RN5T618_RTC_ADJUST, 0);
if (err)
return err;
return regmap_update_bits(rtc->rn5t618->regmap,
RN5T618_RTC_CTRL1,
CTRL1_24HR, CTRL1_24HR);
}
static int rc5t619_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
u8 buff[7];
int err;
int cent_flag;
unsigned int ctrl1;
unsigned int ctrl2;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, &ctrl2);
if (err < 0)
return err;
if (ctrl2 & CTRL2_PON)
return -EINVAL;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL1, &ctrl1);
if (err < 0)
return err;
err = regmap_bulk_read(rtc->rn5t618->regmap, RN5T618_RTC_SECONDS,
buff, sizeof(buff));
if (err < 0)
return err;
if (buff[5] & MONTH_CENTFLAG)
cent_flag = 1;
else
cent_flag = 0;
tm->tm_sec = bcd2bin(buff[0]);
tm->tm_min = bcd2bin(buff[1]);
if (ctrl1 & CTRL1_24HR)
tm->tm_hour = bcd2bin(buff[2]);
else
tm->tm_hour = rtc5t619_12hour_bcd2bin(buff[2]);
tm->tm_wday = bcd2bin(buff[3]);
tm->tm_mday = bcd2bin(buff[4]);
tm->tm_mon = bcd2bin(buff[5] & 0x1f) - 1; /* back to system 0-11 */
tm->tm_year = bcd2bin(buff[6]) + 100 * cent_flag;
return 0;
}
static int rc5t619_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
u8 buff[7];
int err;
int cent_flag;
unsigned int ctrl1;
unsigned int ctrl2;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, &ctrl2);
if (err < 0)
return err;
if (ctrl2 & CTRL2_PON)
rc5t619_rtc_pon_setup(dev);
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL1, &ctrl1);
if (err < 0)
return err;
if (tm->tm_year >= 100)
cent_flag = 1;
else
cent_flag = 0;
buff[0] = bin2bcd(tm->tm_sec);
buff[1] = bin2bcd(tm->tm_min);
if (ctrl1 & CTRL1_24HR)
buff[2] = bin2bcd(tm->tm_hour);
else
buff[2] = rtc5t619_12hour_bin2bcd(tm->tm_hour);
buff[3] = bin2bcd(tm->tm_wday);
buff[4] = bin2bcd(tm->tm_mday);
buff[5] = bin2bcd(tm->tm_mon + 1); /* system set 0-11 */
buff[6] = bin2bcd(tm->tm_year - cent_flag * 100);
if (cent_flag)
buff[5] |= MONTH_CENTFLAG;
err = regmap_bulk_write(rtc->rn5t618->regmap, RN5T618_RTC_SECONDS,
buff, sizeof(buff));
if (err < 0) {
dev_err(dev, "failed to program new time: %d\n", err);
return err;
}
return 0;
}
/* 0-disable, 1-enable */
static int rc5t619_rtc_alarm_enable(struct device *dev, unsigned int enabled)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
return regmap_update_bits(rtc->rn5t618->regmap,
RN5T618_RTC_CTRL1,
CTRL1_ALARM_ENABLED,
enabled ? CTRL1_ALARM_ENABLED : 0);
}
static int rc5t619_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
u8 buff[6];
unsigned int buff_cent;
int err;
int cent_flag;
unsigned int ctrl1;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL1, &ctrl1);
if (err)
return err;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_MONTH, &buff_cent);
if (err < 0) {
dev_err(dev, "failed to read time: %d\n", err);
return err;
}
if (buff_cent & MONTH_CENTFLAG)
cent_flag = 1;
else
cent_flag = 0;
err = regmap_bulk_read(rtc->rn5t618->regmap, RN5T618_RTC_ALARM_Y_SEC,
buff, sizeof(buff));
if (err)
return err;
buff[3] = buff[3] & 0x3f;
alrm->time.tm_sec = bcd2bin(buff[0]);
alrm->time.tm_min = bcd2bin(buff[1]);
if (ctrl1 & CTRL1_24HR)
alrm->time.tm_hour = bcd2bin(buff[2]);
else
alrm->time.tm_hour = rtc5t619_12hour_bcd2bin(buff[2]);
alrm->time.tm_mday = bcd2bin(buff[3]);
alrm->time.tm_mon = bcd2bin(buff[4]) - 1;
alrm->time.tm_year = bcd2bin(buff[5]) + 100 * cent_flag;
alrm->enabled = !!(ctrl1 & CTRL1_ALARM_ENABLED);
dev_dbg(dev, "read alarm: %ptR\n", &alrm->time);
return 0;
}
static int rc5t619_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
u8 buff[6];
int err;
int cent_flag;
unsigned int ctrl1;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL1, &ctrl1);
if (err)
return err;
err = rc5t619_rtc_alarm_enable(dev, 0);
if (err < 0)
return err;
if (rtc->irq == -1)
return -EINVAL;
if (alrm->enabled == 0)
return 0;
if (alrm->time.tm_year >= 100)
cent_flag = 1;
else
cent_flag = 0;
alrm->time.tm_mon += 1;
buff[0] = bin2bcd(alrm->time.tm_sec);
buff[1] = bin2bcd(alrm->time.tm_min);
if (ctrl1 & CTRL1_24HR)
buff[2] = bin2bcd(alrm->time.tm_hour);
else
buff[2] = rtc5t619_12hour_bin2bcd(alrm->time.tm_hour);
buff[3] = bin2bcd(alrm->time.tm_mday);
buff[4] = bin2bcd(alrm->time.tm_mon);
buff[5] = bin2bcd(alrm->time.tm_year - 100 * cent_flag);
buff[3] |= MDAY_DAL_EXT;
err = regmap_bulk_write(rtc->rn5t618->regmap, RN5T618_RTC_ALARM_Y_SEC,
buff, sizeof(buff));
if (err < 0)
return err;
return rc5t619_rtc_alarm_enable(dev, alrm->enabled);
}
static const struct rtc_class_ops rc5t619_rtc_ops = {
.read_time = rc5t619_rtc_read_time,
.set_time = rc5t619_rtc_set_time,
.set_alarm = rc5t619_rtc_set_alarm,
.read_alarm = rc5t619_rtc_read_alarm,
.alarm_irq_enable = rc5t619_rtc_alarm_enable,
};
static int rc5t619_rtc_alarm_flag_clr(struct device *dev)
{
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
/* clear alarm-D status bits.*/
return regmap_update_bits(rtc->rn5t618->regmap,
RN5T618_RTC_CTRL2,
CTRL2_ALARM_STATUS | CTRL2_CTC, 0);
}
static irqreturn_t rc5t619_rtc_irq(int irq, void *data)
{
struct device *dev = data;
struct rc5t619_rtc *rtc = dev_get_drvdata(dev);
rc5t619_rtc_alarm_flag_clr(dev);
rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static int rc5t619_rtc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct rn5t618 *rn5t618 = dev_get_drvdata(pdev->dev.parent);
struct rc5t619_rtc *rtc;
unsigned int ctrl2;
int err;
rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->rn5t618 = rn5t618;
dev_set_drvdata(dev, rtc);
rtc->irq = -1;
if (rn5t618->irq_data)
rtc->irq = regmap_irq_get_virq(rn5t618->irq_data,
RN5T618_IRQ_RTC);
if (rtc->irq < 0)
rtc->irq = -1;
err = regmap_read(rtc->rn5t618->regmap, RN5T618_RTC_CTRL2, &ctrl2);
if (err < 0)
return err;
/* disable rtc periodic function */
err = rc5t619_rtc_periodic_disable(&pdev->dev);
if (err)
return err;
if (ctrl2 & CTRL2_PON) {
err = rc5t619_rtc_alarm_flag_clr(&pdev->dev);
if (err)
return err;
}
rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtc)) {
err = PTR_ERR(rtc->rtc);
dev_err(dev, "RTC device register: err %d\n", err);
return err;
}
rtc->rtc->ops = &rc5t619_rtc_ops;
rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
/* set interrupt and enable it */
if (rtc->irq != -1) {
err = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
rc5t619_rtc_irq,
IRQF_ONESHOT,
"rtc-rc5t619",
&pdev->dev);
if (err < 0) {
dev_err(&pdev->dev, "request IRQ:%d fail\n", rtc->irq);
rtc->irq = -1;
err = rc5t619_rtc_alarm_enable(&pdev->dev, 0);
if (err)
return err;
} else {
/* enable wake */
device_init_wakeup(&pdev->dev, 1);
enable_irq_wake(rtc->irq);
}
} else {
/* system don't want to using alarm interrupt, so close it */
err = rc5t619_rtc_alarm_enable(&pdev->dev, 0);
if (err)
return err;
dev_warn(&pdev->dev, "rc5t619 interrupt is disabled\n");
}
return devm_rtc_register_device(rtc->rtc);
}
static struct platform_driver rc5t619_rtc_driver = {
.driver = {
.name = "rc5t619-rtc",
},
.probe = rc5t619_rtc_probe,
};
module_platform_driver(rc5t619_rtc_driver);
MODULE_ALIAS("platform:rc5t619-rtc");
MODULE_DESCRIPTION("RICOH RC5T619 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-rc5t619.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Freescale STMP37XX/STMP378X Real Time Clock driver
*
* Copyright (c) 2007 Sigmatel, Inc.
* Peter Hartley, <[email protected]>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
* Copyright 2011 Wolfram Sang, Pengutronix e.K.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>
#define STMP3XXX_RTC_CTRL 0x0
#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
#define STMP3XXX_RTC_STAT 0x10
#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
#define STMP3XXX_RTC_SECONDS 0x30
#define STMP3XXX_RTC_ALARM 0x40
#define STMP3XXX_RTC_WATCHDOG 0x50
#define STMP3XXX_RTC_PERSISTENT0 0x60
#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
#define STMP3XXX_RTC_PERSISTENT1 0x70
/* missing bitmask in headers */
#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
struct stmp3xxx_rtc_data {
struct rtc_device *rtc;
void __iomem *io;
int irq_alarm;
};
#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
/**
* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
* @dev: the parent device of the watchdog (= the RTC)
* @timeout: the desired value for the timeout register of the watchdog.
* 0 disables the watchdog
*
* The watchdog needs one register and two bits which are in the RTC domain.
* To handle the resource conflict, the RTC driver will create another
* platform_device for the watchdog driver as a child of the RTC device.
* The watchdog driver is passed the below accessor function via platform_data
* to configure the watchdog. Locking is not needed because accessing SET/CLR
* registers is atomic.
*/
static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
if (timeout) {
writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
} else {
writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
}
}
static struct stmp3xxx_wdt_pdata wdt_pdata = {
.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
};
static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
int rc = -1;
struct platform_device *wdt_pdev =
platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
if (wdt_pdev) {
wdt_pdev->dev.parent = &rtc_pdev->dev;
wdt_pdev->dev.platform_data = &wdt_pdata;
rc = platform_device_add(wdt_pdev);
if (rc)
platform_device_put(wdt_pdev);
}
if (rc)
dev_err(&rtc_pdev->dev,
"failed to register stmp3xxx_rtc_wdt\n");
}
#else
static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
}
#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
{
int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
/*
* The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
* states:
* | The order in which registers are updated is
* | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
* | (This list is in bitfield order, from LSB to MSB, as they would
* | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
* | register. For example, the Seconds register corresponds to
* | STALE_REGS or NEW_REGS containing 0x80.)
*/
do {
if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
return 0;
udelay(1);
} while (--timeout > 0);
return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
}
/* Time read/write */
static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
int ret;
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
ret = stmp3xxx_wait_time(rtc_data);
if (ret)
return ret;
rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
return 0;
}
static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
return stmp3xxx_wait_time(rtc_data);
}
/* interrupt(s) handler */
static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
if (enabled) {
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
STMP_OFFSET_REG_SET);
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
} else {
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
STMP_OFFSET_REG_CLR);
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
}
return 0;
}
static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
return 0;
}
static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
stmp3xxx_alarm_irq_enable(dev, alm->enabled);
return 0;
}
static const struct rtc_class_ops stmp3xxx_rtc_ops = {
.alarm_irq_enable =
stmp3xxx_alarm_irq_enable,
.read_time = stmp3xxx_rtc_gettime,
.set_time = stmp3xxx_rtc_settime,
.read_alarm = stmp3xxx_rtc_read_alarm,
.set_alarm = stmp3xxx_rtc_set_alarm,
};
static void stmp3xxx_rtc_remove(struct platform_device *pdev)
{
struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
if (!rtc_data)
return;
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
}
static int stmp3xxx_rtc_probe(struct platform_device *pdev)
{
struct stmp3xxx_rtc_data *rtc_data;
struct resource *r;
u32 rtc_stat;
u32 pers0_set, pers0_clr;
u32 crystalfreq = 0;
int err;
rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
if (!rtc_data)
return -ENOMEM;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "failed to get resource\n");
return -ENXIO;
}
rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
if (!rtc_data->io) {
dev_err(&pdev->dev, "ioremap failed\n");
return -EIO;
}
rtc_data->irq_alarm = platform_get_irq(pdev, 0);
rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
dev_err(&pdev->dev, "no device onboard\n");
return -ENODEV;
}
platform_set_drvdata(pdev, rtc_data);
/*
* Resetting the rtc stops the watchdog timer that is potentially
* running. So (assuming it is running on purpose) don't reset if the
* watchdog is enabled.
*/
if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
STMP3XXX_RTC_CTRL_WATCHDOGEN) {
dev_info(&pdev->dev,
"Watchdog is running, skip resetting rtc\n");
} else {
err = stmp_reset_block(rtc_data->io);
if (err) {
dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
err);
return err;
}
}
/*
* Obviously the rtc needs a clock input to be able to run.
* This clock can be provided by an external 32k crystal. If that one is
* missing XTAL must not be disabled in suspend which consumes a
* lot of power. Normally the presence and exact frequency (supported
* are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
* proves these fuses are not blown correctly on all machines, so the
* frequency can be overridden in the device tree.
*/
if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
crystalfreq = 32000;
else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
crystalfreq = 32768;
of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
&crystalfreq);
switch (crystalfreq) {
case 32000:
/* keep 32kHz crystal running in low-power mode */
pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
break;
case 32768:
/* keep 32.768kHz crystal running in low-power mode */
pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
break;
default:
dev_warn(&pdev->dev,
"invalid crystal-freq specified in device-tree. Assuming no crystal\n");
fallthrough;
case 0:
/* keep XTAL on in low-power mode */
pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
}
writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
STMP_OFFSET_REG_SET);
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc_data->rtc))
return PTR_ERR(rtc_data->rtc);
err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
if (err) {
dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
rtc_data->irq_alarm);
return err;
}
rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
rtc_data->rtc->range_max = U32_MAX;
err = devm_rtc_register_device(rtc_data->rtc);
if (err)
return err;
stmp3xxx_wdt_register(pdev);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int stmp3xxx_rtc_suspend(struct device *dev)
{
return 0;
}
static int stmp3xxx_rtc_resume(struct device *dev)
{
struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
stmp_reset_block(rtc_data->io);
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
stmp3xxx_rtc_resume);
static const struct of_device_id rtc_dt_ids[] = {
{ .compatible = "fsl,stmp3xxx-rtc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtc_dt_ids);
static struct platform_driver stmp3xxx_rtcdrv = {
.probe = stmp3xxx_rtc_probe,
.remove_new = stmp3xxx_rtc_remove,
.driver = {
.name = "stmp3xxx-rtc",
.pm = &stmp3xxx_rtc_pm_ops,
.of_match_table = rtc_dt_ids,
},
};
module_platform_driver(stmp3xxx_rtcdrv);
MODULE_DESCRIPTION("STMP3xxx RTC Driver");
MODULE_AUTHOR("dmitry pervushin <[email protected]> and "
"Wolfram Sang <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-stmp3xxx.c |
// SPDX-License-Identifier: GPL-2.0
/*
* A driver for the I2C members of the Abracon AB x8xx RTC family,
* and compatible: AB 1805 and AB 0805
*
* Copyright 2014-2015 Macq S.A.
*
* Author: Philippe De Muyter <[email protected]>
* Author: Alexandre Belloni <[email protected]>
*
*/
#include <linux/bcd.h>
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/kstrtox.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/rtc.h>
#include <linux/watchdog.h>
#define ABX8XX_REG_HTH 0x00
#define ABX8XX_REG_SC 0x01
#define ABX8XX_REG_MN 0x02
#define ABX8XX_REG_HR 0x03
#define ABX8XX_REG_DA 0x04
#define ABX8XX_REG_MO 0x05
#define ABX8XX_REG_YR 0x06
#define ABX8XX_REG_WD 0x07
#define ABX8XX_REG_AHTH 0x08
#define ABX8XX_REG_ASC 0x09
#define ABX8XX_REG_AMN 0x0a
#define ABX8XX_REG_AHR 0x0b
#define ABX8XX_REG_ADA 0x0c
#define ABX8XX_REG_AMO 0x0d
#define ABX8XX_REG_AWD 0x0e
#define ABX8XX_REG_STATUS 0x0f
#define ABX8XX_STATUS_AF BIT(2)
#define ABX8XX_STATUS_BLF BIT(4)
#define ABX8XX_STATUS_WDT BIT(6)
#define ABX8XX_REG_CTRL1 0x10
#define ABX8XX_CTRL_WRITE BIT(0)
#define ABX8XX_CTRL_ARST BIT(2)
#define ABX8XX_CTRL_12_24 BIT(6)
#define ABX8XX_REG_CTRL2 0x11
#define ABX8XX_CTRL2_RSVD BIT(5)
#define ABX8XX_REG_IRQ 0x12
#define ABX8XX_IRQ_AIE BIT(2)
#define ABX8XX_IRQ_IM_1_4 (0x3 << 5)
#define ABX8XX_REG_CD_TIMER_CTL 0x18
#define ABX8XX_REG_OSC 0x1c
#define ABX8XX_OSC_FOS BIT(3)
#define ABX8XX_OSC_BOS BIT(4)
#define ABX8XX_OSC_ACAL_512 BIT(5)
#define ABX8XX_OSC_ACAL_1024 BIT(6)
#define ABX8XX_OSC_OSEL BIT(7)
#define ABX8XX_REG_OSS 0x1d
#define ABX8XX_OSS_OF BIT(1)
#define ABX8XX_OSS_OMODE BIT(4)
#define ABX8XX_REG_WDT 0x1b
#define ABX8XX_WDT_WDS BIT(7)
#define ABX8XX_WDT_BMB_MASK 0x7c
#define ABX8XX_WDT_BMB_SHIFT 2
#define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
#define ABX8XX_WDT_WRB_MASK 0x03
#define ABX8XX_WDT_WRB_1HZ 0x02
#define ABX8XX_REG_CFG_KEY 0x1f
#define ABX8XX_CFG_KEY_OSC 0xa1
#define ABX8XX_CFG_KEY_MISC 0x9d
#define ABX8XX_REG_ID0 0x28
#define ABX8XX_REG_OUT_CTRL 0x30
#define ABX8XX_OUT_CTRL_EXDS BIT(4)
#define ABX8XX_REG_TRICKLE 0x20
#define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0
#define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
#define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
#define ABX8XX_REG_EXTRAM 0x3f
#define ABX8XX_EXTRAM_XADS GENMASK(1, 0)
#define ABX8XX_SRAM_BASE 0x40
#define ABX8XX_SRAM_WIN_SIZE 0x40
#define ABX8XX_RAM_SIZE 256
#define NVMEM_ADDR_LOWER GENMASK(5, 0)
#define NVMEM_ADDR_UPPER GENMASK(7, 6)
static u8 trickle_resistors[] = {0, 3, 6, 11};
enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};
struct abx80x_cap {
u16 pn;
bool has_tc;
bool has_wdog;
};
static struct abx80x_cap abx80x_caps[] = {
[AB0801] = {.pn = 0x0801},
[AB0803] = {.pn = 0x0803},
[AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
[AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
[AB1801] = {.pn = 0x1801},
[AB1803] = {.pn = 0x1803},
[AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
[AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
[RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
[ABX80X] = {.pn = 0}
};
struct abx80x_priv {
struct rtc_device *rtc;
struct i2c_client *client;
struct watchdog_device wdog;
};
static int abx80x_write_config_key(struct i2c_client *client, u8 key)
{
if (i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY, key) < 0) {
dev_err(&client->dev, "Unable to write configuration key\n");
return -EIO;
}
return 0;
}
static int abx80x_is_rc_mode(struct i2c_client *client)
{
int flags = 0;
flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
if (flags < 0) {
dev_err(&client->dev,
"Failed to read autocalibration attribute\n");
return flags;
}
return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
}
static int abx80x_enable_trickle_charger(struct i2c_client *client,
u8 trickle_cfg)
{
int err;
/*
* Write the configuration key register to enable access to the Trickle
* register
*/
if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_MISC) < 0)
return -EIO;
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_TRICKLE,
ABX8XX_TRICKLE_CHARGE_ENABLE |
trickle_cfg);
if (err < 0) {
dev_err(&client->dev, "Unable to write trickle register\n");
return -EIO;
}
return 0;
}
static int abx80x_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char buf[8];
int err, flags, rc_mode = 0;
/* Read the Oscillator Failure only in XT mode */
rc_mode = abx80x_is_rc_mode(client);
if (rc_mode < 0)
return rc_mode;
if (!rc_mode) {
flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
if (flags < 0)
return flags;
if (flags & ABX8XX_OSS_OF) {
dev_err(dev, "Oscillator failure, data is invalid.\n");
return -EINVAL;
}
}
err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_HTH,
sizeof(buf), buf);
if (err < 0) {
dev_err(&client->dev, "Unable to read date\n");
return -EIO;
}
tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F) - 1;
tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 100;
return 0;
}
static int abx80x_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char buf[8];
int err, flags;
if (tm->tm_year < 100)
return -EINVAL;
buf[ABX8XX_REG_HTH] = 0;
buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon + 1);
buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 100);
buf[ABX8XX_REG_WD] = tm->tm_wday;
err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_HTH,
sizeof(buf), buf);
if (err < 0) {
dev_err(&client->dev, "Unable to write to date registers\n");
return -EIO;
}
/* Clear the OF bit of Oscillator Status Register */
flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
if (flags < 0)
return flags;
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSS,
flags & ~ABX8XX_OSS_OF);
if (err < 0) {
dev_err(&client->dev, "Unable to write oscillator status register\n");
return err;
}
return 0;
}
static irqreturn_t abx80x_handle_irq(int irq, void *dev_id)
{
struct i2c_client *client = dev_id;
struct abx80x_priv *priv = i2c_get_clientdata(client);
struct rtc_device *rtc = priv->rtc;
int status;
status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
if (status < 0)
return IRQ_NONE;
if (status & ABX8XX_STATUS_AF)
rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
/*
* It is unclear if we'll get an interrupt before the external
* reset kicks in.
*/
if (status & ABX8XX_STATUS_WDT)
dev_alert(&client->dev, "watchdog timeout interrupt.\n");
i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
return IRQ_HANDLED;
}
static int abx80x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char buf[7];
int irq_mask, err;
if (client->irq <= 0)
return -EINVAL;
err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ASC,
sizeof(buf), buf);
if (err)
return err;
irq_mask = i2c_smbus_read_byte_data(client, ABX8XX_REG_IRQ);
if (irq_mask < 0)
return irq_mask;
t->time.tm_sec = bcd2bin(buf[0] & 0x7F);
t->time.tm_min = bcd2bin(buf[1] & 0x7F);
t->time.tm_hour = bcd2bin(buf[2] & 0x3F);
t->time.tm_mday = bcd2bin(buf[3] & 0x3F);
t->time.tm_mon = bcd2bin(buf[4] & 0x1F) - 1;
t->time.tm_wday = buf[5] & 0x7;
t->enabled = !!(irq_mask & ABX8XX_IRQ_AIE);
t->pending = (buf[6] & ABX8XX_STATUS_AF) && t->enabled;
return err;
}
static int abx80x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
{
struct i2c_client *client = to_i2c_client(dev);
u8 alarm[6];
int err;
if (client->irq <= 0)
return -EINVAL;
alarm[0] = 0x0;
alarm[1] = bin2bcd(t->time.tm_sec);
alarm[2] = bin2bcd(t->time.tm_min);
alarm[3] = bin2bcd(t->time.tm_hour);
alarm[4] = bin2bcd(t->time.tm_mday);
alarm[5] = bin2bcd(t->time.tm_mon + 1);
err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_AHTH,
sizeof(alarm), alarm);
if (err < 0) {
dev_err(&client->dev, "Unable to write alarm registers\n");
return -EIO;
}
if (t->enabled) {
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
(ABX8XX_IRQ_IM_1_4 |
ABX8XX_IRQ_AIE));
if (err)
return err;
}
return 0;
}
static int abx80x_rtc_set_autocalibration(struct device *dev,
int autocalibration)
{
struct i2c_client *client = to_i2c_client(dev);
int retval, flags = 0;
if ((autocalibration != 0) && (autocalibration != 1024) &&
(autocalibration != 512)) {
dev_err(dev, "autocalibration value outside permitted range\n");
return -EINVAL;
}
flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
if (flags < 0)
return flags;
if (autocalibration == 0) {
flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024);
} else if (autocalibration == 1024) {
/* 1024 autocalibration is 0x10 */
flags |= ABX8XX_OSC_ACAL_1024;
flags &= ~(ABX8XX_OSC_ACAL_512);
} else {
/* 512 autocalibration is 0x11 */
flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512);
}
/* Unlock write access to Oscillator Control Register */
if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_OSC) < 0)
return -EIO;
retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
return retval;
}
static int abx80x_rtc_get_autocalibration(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
int flags = 0, autocalibration;
flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
if (flags < 0)
return flags;
if (flags & ABX8XX_OSC_ACAL_512)
autocalibration = 512;
else if (flags & ABX8XX_OSC_ACAL_1024)
autocalibration = 1024;
else
autocalibration = 0;
return autocalibration;
}
static ssize_t autocalibration_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int retval;
unsigned long autocalibration = 0;
retval = kstrtoul(buf, 10, &autocalibration);
if (retval < 0) {
dev_err(dev, "Failed to store RTC autocalibration attribute\n");
return -EINVAL;
}
retval = abx80x_rtc_set_autocalibration(dev->parent, autocalibration);
return retval ? retval : count;
}
static ssize_t autocalibration_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int autocalibration = 0;
autocalibration = abx80x_rtc_get_autocalibration(dev->parent);
if (autocalibration < 0) {
dev_err(dev, "Failed to read RTC autocalibration\n");
sprintf(buf, "0\n");
return autocalibration;
}
return sprintf(buf, "%d\n", autocalibration);
}
static DEVICE_ATTR_RW(autocalibration);
static ssize_t oscillator_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct i2c_client *client = to_i2c_client(dev->parent);
int retval, flags, rc_mode = 0;
if (strncmp(buf, "rc", 2) == 0) {
rc_mode = 1;
} else if (strncmp(buf, "xtal", 4) == 0) {
rc_mode = 0;
} else {
dev_err(dev, "Oscillator selection value outside permitted ones\n");
return -EINVAL;
}
flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
if (flags < 0)
return flags;
if (rc_mode == 0)
flags &= ~(ABX8XX_OSC_OSEL);
else
flags |= (ABX8XX_OSC_OSEL);
/* Unlock write access on Oscillator Control register */
if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_OSC) < 0)
return -EIO;
retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
if (retval < 0) {
dev_err(dev, "Failed to write Oscillator Control register\n");
return retval;
}
return retval ? retval : count;
}
static ssize_t oscillator_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int rc_mode = 0;
struct i2c_client *client = to_i2c_client(dev->parent);
rc_mode = abx80x_is_rc_mode(client);
if (rc_mode < 0) {
dev_err(dev, "Failed to read RTC oscillator selection\n");
sprintf(buf, "\n");
return rc_mode;
}
if (rc_mode)
return sprintf(buf, "rc\n");
else
return sprintf(buf, "xtal\n");
}
static DEVICE_ATTR_RW(oscillator);
static struct attribute *rtc_calib_attrs[] = {
&dev_attr_autocalibration.attr,
&dev_attr_oscillator.attr,
NULL,
};
static const struct attribute_group rtc_calib_attr_group = {
.attrs = rtc_calib_attrs,
};
static int abx80x_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct i2c_client *client = to_i2c_client(dev);
int err;
if (enabled)
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
(ABX8XX_IRQ_IM_1_4 |
ABX8XX_IRQ_AIE));
else
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
ABX8XX_IRQ_IM_1_4);
return err;
}
static int abx80x_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
struct i2c_client *client = to_i2c_client(dev);
int status, tmp;
switch (cmd) {
case RTC_VL_READ:
status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
if (status < 0)
return status;
tmp = status & ABX8XX_STATUS_BLF ? RTC_VL_BACKUP_LOW : 0;
return put_user(tmp, (unsigned int __user *)arg);
case RTC_VL_CLR:
status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
if (status < 0)
return status;
status &= ~ABX8XX_STATUS_BLF;
tmp = i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
if (tmp < 0)
return tmp;
return 0;
default:
return -ENOIOCTLCMD;
}
}
static const struct rtc_class_ops abx80x_rtc_ops = {
.read_time = abx80x_rtc_read_time,
.set_time = abx80x_rtc_set_time,
.read_alarm = abx80x_read_alarm,
.set_alarm = abx80x_set_alarm,
.alarm_irq_enable = abx80x_alarm_irq_enable,
.ioctl = abx80x_ioctl,
};
static int abx80x_dt_trickle_cfg(struct i2c_client *client)
{
struct device_node *np = client->dev.of_node;
const char *diode;
int trickle_cfg = 0;
int i, ret;
u32 tmp;
ret = of_property_read_string(np, "abracon,tc-diode", &diode);
if (ret)
return ret;
if (!strcmp(diode, "standard")) {
trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE;
} else if (!strcmp(diode, "schottky")) {
trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
} else {
dev_dbg(&client->dev, "Invalid tc-diode value: %s\n", diode);
return -EINVAL;
}
ret = of_property_read_u32(np, "abracon,tc-resistor", &tmp);
if (ret)
return ret;
for (i = 0; i < sizeof(trickle_resistors); i++)
if (trickle_resistors[i] == tmp)
break;
if (i == sizeof(trickle_resistors)) {
dev_dbg(&client->dev, "Invalid tc-resistor value: %u\n", tmp);
return -EINVAL;
}
return (trickle_cfg | i);
}
#ifdef CONFIG_WATCHDOG
static inline u8 timeout_bits(unsigned int timeout)
{
return ((timeout << ABX8XX_WDT_BMB_SHIFT) & ABX8XX_WDT_BMB_MASK) |
ABX8XX_WDT_WRB_1HZ;
}
static int __abx80x_wdog_set_timeout(struct watchdog_device *wdog,
unsigned int timeout)
{
struct abx80x_priv *priv = watchdog_get_drvdata(wdog);
u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout);
/*
* Writing any timeout to the WDT register resets the watchdog timer.
* Writing 0 disables it.
*/
return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val);
}
static int abx80x_wdog_set_timeout(struct watchdog_device *wdog,
unsigned int new_timeout)
{
int err = 0;
if (watchdog_hw_running(wdog))
err = __abx80x_wdog_set_timeout(wdog, new_timeout);
if (err == 0)
wdog->timeout = new_timeout;
return err;
}
static int abx80x_wdog_ping(struct watchdog_device *wdog)
{
return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
}
static int abx80x_wdog_start(struct watchdog_device *wdog)
{
return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
}
static int abx80x_wdog_stop(struct watchdog_device *wdog)
{
return __abx80x_wdog_set_timeout(wdog, 0);
}
static const struct watchdog_info abx80x_wdog_info = {
.identity = "abx80x watchdog",
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};
static const struct watchdog_ops abx80x_wdog_ops = {
.owner = THIS_MODULE,
.start = abx80x_wdog_start,
.stop = abx80x_wdog_stop,
.ping = abx80x_wdog_ping,
.set_timeout = abx80x_wdog_set_timeout,
};
static int abx80x_setup_watchdog(struct abx80x_priv *priv)
{
priv->wdog.parent = &priv->client->dev;
priv->wdog.ops = &abx80x_wdog_ops;
priv->wdog.info = &abx80x_wdog_info;
priv->wdog.min_timeout = 1;
priv->wdog.max_timeout = ABX8XX_WDT_MAX_TIME;
priv->wdog.timeout = ABX8XX_WDT_MAX_TIME;
watchdog_set_drvdata(&priv->wdog, priv);
return devm_watchdog_register_device(&priv->client->dev, &priv->wdog);
}
#else
static int abx80x_setup_watchdog(struct abx80x_priv *priv)
{
return 0;
}
#endif
static int abx80x_nvmem_xfer(struct abx80x_priv *priv, unsigned int offset,
void *val, size_t bytes, bool write)
{
int ret;
while (bytes) {
u8 extram, reg, len, lower, upper;
lower = FIELD_GET(NVMEM_ADDR_LOWER, offset);
upper = FIELD_GET(NVMEM_ADDR_UPPER, offset);
extram = FIELD_PREP(ABX8XX_EXTRAM_XADS, upper);
reg = ABX8XX_SRAM_BASE + lower;
len = min(lower + bytes, (size_t)ABX8XX_SRAM_WIN_SIZE) - lower;
len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
ret = i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_EXTRAM,
extram);
if (ret)
return ret;
if (write)
ret = i2c_smbus_write_i2c_block_data(priv->client, reg,
len, val);
else
ret = i2c_smbus_read_i2c_block_data(priv->client, reg,
len, val);
if (ret)
return ret;
offset += len;
val += len;
bytes -= len;
}
return 0;
}
static int abx80x_nvmem_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return abx80x_nvmem_xfer(priv, offset, val, bytes, false);
}
static int abx80x_nvmem_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return abx80x_nvmem_xfer(priv, offset, val, bytes, true);
}
static int abx80x_setup_nvmem(struct abx80x_priv *priv)
{
struct nvmem_config config = {
.type = NVMEM_TYPE_BATTERY_BACKED,
.reg_read = abx80x_nvmem_read,
.reg_write = abx80x_nvmem_write,
.size = ABX8XX_RAM_SIZE,
.priv = priv,
};
return devm_rtc_nvmem_register(priv->rtc, &config);
}
static const struct i2c_device_id abx80x_id[] = {
{ "abx80x", ABX80X },
{ "ab0801", AB0801 },
{ "ab0803", AB0803 },
{ "ab0804", AB0804 },
{ "ab0805", AB0805 },
{ "ab1801", AB1801 },
{ "ab1803", AB1803 },
{ "ab1804", AB1804 },
{ "ab1805", AB1805 },
{ "rv1805", RV1805 },
{ }
};
MODULE_DEVICE_TABLE(i2c, abx80x_id);
static int abx80x_probe(struct i2c_client *client)
{
struct device_node *np = client->dev.of_node;
struct abx80x_priv *priv;
int i, data, err, trickle_cfg = -EINVAL;
char buf[7];
const struct i2c_device_id *id = i2c_match_id(abx80x_id, client);
unsigned int part = id->driver_data;
unsigned int partnumber;
unsigned int majrev, minrev;
unsigned int lot;
unsigned int wafer;
unsigned int uid;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ID0,
sizeof(buf), buf);
if (err < 0) {
dev_err(&client->dev, "Unable to read partnumber\n");
return -EIO;
}
partnumber = (buf[0] << 8) | buf[1];
majrev = buf[2] >> 3;
minrev = buf[2] & 0x7;
lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3];
uid = ((buf[4] & 0x7f) << 8) | buf[5];
wafer = (buf[6] & 0x7c) >> 2;
dev_info(&client->dev, "model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
partnumber, majrev, minrev, lot, wafer, uid);
data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL1);
if (data < 0) {
dev_err(&client->dev, "Unable to read control register\n");
return -EIO;
}
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL1,
((data & ~(ABX8XX_CTRL_12_24 |
ABX8XX_CTRL_ARST)) |
ABX8XX_CTRL_WRITE));
if (err < 0) {
dev_err(&client->dev, "Unable to write control register\n");
return -EIO;
}
/* Configure RV1805 specifics */
if (part == RV1805) {
/*
* Avoid accidentally entering test mode. This can happen
* on the RV1805 in case the reserved bit 5 in control2
* register is set. RV-1805-C3 datasheet indicates that
* the bit should be cleared in section 11h - Control2.
*/
data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL2);
if (data < 0) {
dev_err(&client->dev,
"Unable to read control2 register\n");
return -EIO;
}
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL2,
data & ~ABX8XX_CTRL2_RSVD);
if (err < 0) {
dev_err(&client->dev,
"Unable to write control2 register\n");
return -EIO;
}
/*
* Avoid extra power leakage. The RV1805 uses smaller
* 10pin package and the EXTI input is not present.
* Disable it to avoid leakage.
*/
data = i2c_smbus_read_byte_data(client, ABX8XX_REG_OUT_CTRL);
if (data < 0) {
dev_err(&client->dev,
"Unable to read output control register\n");
return -EIO;
}
/*
* Write the configuration key register to enable access to
* the config2 register
*/
if (abx80x_write_config_key(client, ABX8XX_CFG_KEY_MISC) < 0)
return -EIO;
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OUT_CTRL,
data | ABX8XX_OUT_CTRL_EXDS);
if (err < 0) {
dev_err(&client->dev,
"Unable to write output control register\n");
return -EIO;
}
}
/* part autodetection */
if (part == ABX80X) {
for (i = 0; abx80x_caps[i].pn; i++)
if (partnumber == abx80x_caps[i].pn)
break;
if (abx80x_caps[i].pn == 0) {
dev_err(&client->dev, "Unknown part: %04x\n",
partnumber);
return -EINVAL;
}
part = i;
}
if (partnumber != abx80x_caps[part].pn) {
dev_err(&client->dev, "partnumber mismatch %04x != %04x\n",
partnumber, abx80x_caps[part].pn);
return -EINVAL;
}
if (np && abx80x_caps[part].has_tc)
trickle_cfg = abx80x_dt_trickle_cfg(client);
if (trickle_cfg > 0) {
dev_info(&client->dev, "Enabling trickle charger: %02x\n",
trickle_cfg);
abx80x_enable_trickle_charger(client, trickle_cfg);
}
err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CD_TIMER_CTL,
BIT(2));
if (err)
return err;
priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
if (priv == NULL)
return -ENOMEM;
priv->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(priv->rtc))
return PTR_ERR(priv->rtc);
priv->rtc->ops = &abx80x_rtc_ops;
priv->client = client;
i2c_set_clientdata(client, priv);
if (abx80x_caps[part].has_wdog) {
err = abx80x_setup_watchdog(priv);
if (err)
return err;
}
err = abx80x_setup_nvmem(priv);
if (err)
return err;
if (client->irq > 0) {
dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
abx80x_handle_irq,
IRQF_SHARED | IRQF_ONESHOT,
"abx8xx",
client);
if (err) {
dev_err(&client->dev, "unable to request IRQ, alarms disabled\n");
client->irq = 0;
}
}
err = rtc_add_group(priv->rtc, &rtc_calib_attr_group);
if (err) {
dev_err(&client->dev, "Failed to create sysfs group: %d\n",
err);
return err;
}
return devm_rtc_register_device(priv->rtc);
}
#ifdef CONFIG_OF
static const struct of_device_id abx80x_of_match[] = {
{
.compatible = "abracon,abx80x",
.data = (void *)ABX80X
},
{
.compatible = "abracon,ab0801",
.data = (void *)AB0801
},
{
.compatible = "abracon,ab0803",
.data = (void *)AB0803
},
{
.compatible = "abracon,ab0804",
.data = (void *)AB0804
},
{
.compatible = "abracon,ab0805",
.data = (void *)AB0805
},
{
.compatible = "abracon,ab1801",
.data = (void *)AB1801
},
{
.compatible = "abracon,ab1803",
.data = (void *)AB1803
},
{
.compatible = "abracon,ab1804",
.data = (void *)AB1804
},
{
.compatible = "abracon,ab1805",
.data = (void *)AB1805
},
{
.compatible = "microcrystal,rv1805",
.data = (void *)RV1805
},
{ }
};
MODULE_DEVICE_TABLE(of, abx80x_of_match);
#endif
static struct i2c_driver abx80x_driver = {
.driver = {
.name = "rtc-abx80x",
.of_match_table = of_match_ptr(abx80x_of_match),
},
.probe = abx80x_probe,
.id_table = abx80x_id,
};
module_i2c_driver(abx80x_driver);
MODULE_AUTHOR("Philippe De Muyter <[email protected]>");
MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
MODULE_DESCRIPTION("Abracon ABX80X RTC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-abx80x.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 Microchip.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/tee_drv.h>
#define RTC_INFO_VERSION 0x1
#define TA_CMD_RTC_GET_INFO 0x0
#define TA_CMD_RTC_GET_TIME 0x1
#define TA_CMD_RTC_SET_TIME 0x2
#define TA_CMD_RTC_GET_OFFSET 0x3
#define TA_CMD_RTC_SET_OFFSET 0x4
#define TA_RTC_FEATURE_CORRECTION BIT(0)
struct optee_rtc_time {
u32 tm_sec;
u32 tm_min;
u32 tm_hour;
u32 tm_mday;
u32 tm_mon;
u32 tm_year;
u32 tm_wday;
};
struct optee_rtc_info {
u64 version;
u64 features;
struct optee_rtc_time range_min;
struct optee_rtc_time range_max;
};
/**
* struct optee_rtc - OP-TEE RTC private data
* @dev: OP-TEE based RTC device.
* @ctx: OP-TEE context handler.
* @session_id: RTC TA session identifier.
* @shm: Memory pool shared with RTC device.
* @features: Bitfield of RTC features
*/
struct optee_rtc {
struct device *dev;
struct tee_context *ctx;
u32 session_id;
struct tee_shm *shm;
u64 features;
};
static int optee_rtc_readtime(struct device *dev, struct rtc_time *tm)
{
struct optee_rtc *priv = dev_get_drvdata(dev);
struct tee_ioctl_invoke_arg inv_arg = {0};
struct optee_rtc_time *optee_tm;
struct tee_param param[4] = {0};
int ret;
inv_arg.func = TA_CMD_RTC_GET_TIME;
inv_arg.session = priv->session_id;
inv_arg.num_params = 4;
/* Fill invoke cmd params */
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
param[0].u.memref.shm = priv->shm;
param[0].u.memref.size = sizeof(struct optee_rtc_time);
ret = tee_client_invoke_func(priv->ctx, &inv_arg, param);
if (ret < 0 || inv_arg.ret != 0)
return ret ? ret : -EPROTO;
optee_tm = tee_shm_get_va(priv->shm, 0);
if (IS_ERR(optee_tm))
return PTR_ERR(optee_tm);
if (param[0].u.memref.size != sizeof(*optee_tm))
return -EPROTO;
tm->tm_sec = optee_tm->tm_sec;
tm->tm_min = optee_tm->tm_min;
tm->tm_hour = optee_tm->tm_hour;
tm->tm_mday = optee_tm->tm_mday;
tm->tm_mon = optee_tm->tm_mon;
tm->tm_year = optee_tm->tm_year - 1900;
tm->tm_wday = optee_tm->tm_wday;
tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
return 0;
}
static int optee_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct optee_rtc *priv = dev_get_drvdata(dev);
struct tee_ioctl_invoke_arg inv_arg = {0};
struct tee_param param[4] = {0};
struct optee_rtc_time optee_tm;
void *rtc_data;
int ret;
optee_tm.tm_sec = tm->tm_sec;
optee_tm.tm_min = tm->tm_min;
optee_tm.tm_hour = tm->tm_hour;
optee_tm.tm_mday = tm->tm_mday;
optee_tm.tm_mon = tm->tm_mon;
optee_tm.tm_year = tm->tm_year + 1900;
optee_tm.tm_wday = tm->tm_wday;
inv_arg.func = TA_CMD_RTC_SET_TIME;
inv_arg.session = priv->session_id;
inv_arg.num_params = 4;
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT;
param[0].u.memref.shm = priv->shm;
param[0].u.memref.size = sizeof(struct optee_rtc_time);
rtc_data = tee_shm_get_va(priv->shm, 0);
if (IS_ERR(rtc_data))
return PTR_ERR(rtc_data);
memcpy(rtc_data, &optee_tm, sizeof(struct optee_rtc_time));
ret = tee_client_invoke_func(priv->ctx, &inv_arg, param);
if (ret < 0 || inv_arg.ret != 0)
return ret ? ret : -EPROTO;
return 0;
}
static int optee_rtc_readoffset(struct device *dev, long *offset)
{
struct optee_rtc *priv = dev_get_drvdata(dev);
struct tee_ioctl_invoke_arg inv_arg = {0};
struct tee_param param[4] = {0};
int ret;
if (!(priv->features & TA_RTC_FEATURE_CORRECTION))
return -EOPNOTSUPP;
inv_arg.func = TA_CMD_RTC_GET_OFFSET;
inv_arg.session = priv->session_id;
inv_arg.num_params = 4;
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT;
ret = tee_client_invoke_func(priv->ctx, &inv_arg, param);
if (ret < 0 || inv_arg.ret != 0)
return ret ? ret : -EPROTO;
*offset = param[0].u.value.a;
return 0;
}
static int optee_rtc_setoffset(struct device *dev, long offset)
{
struct optee_rtc *priv = dev_get_drvdata(dev);
struct tee_ioctl_invoke_arg inv_arg = {0};
struct tee_param param[4] = {0};
int ret;
if (!(priv->features & TA_RTC_FEATURE_CORRECTION))
return -EOPNOTSUPP;
inv_arg.func = TA_CMD_RTC_SET_OFFSET;
inv_arg.session = priv->session_id;
inv_arg.num_params = 4;
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT;
param[0].u.value.a = offset;
ret = tee_client_invoke_func(priv->ctx, &inv_arg, param);
if (ret < 0 || inv_arg.ret != 0)
return ret ? ret : -EPROTO;
return 0;
}
static const struct rtc_class_ops optee_rtc_ops = {
.read_time = optee_rtc_readtime,
.set_time = optee_rtc_settime,
.set_offset = optee_rtc_setoffset,
.read_offset = optee_rtc_readoffset,
};
static int optee_rtc_read_info(struct device *dev, struct rtc_device *rtc,
u64 *features)
{
struct optee_rtc *priv = dev_get_drvdata(dev);
struct tee_ioctl_invoke_arg inv_arg = {0};
struct tee_param param[4] = {0};
struct optee_rtc_info *info;
struct optee_rtc_time *tm;
int ret;
inv_arg.func = TA_CMD_RTC_GET_INFO;
inv_arg.session = priv->session_id;
inv_arg.num_params = 4;
param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
param[0].u.memref.shm = priv->shm;
param[0].u.memref.size = sizeof(*info);
ret = tee_client_invoke_func(priv->ctx, &inv_arg, param);
if (ret < 0 || inv_arg.ret != 0)
return ret ? ret : -EPROTO;
info = tee_shm_get_va(priv->shm, 0);
if (IS_ERR(info))
return PTR_ERR(info);
if (param[0].u.memref.size != sizeof(*info))
return -EPROTO;
if (info->version != RTC_INFO_VERSION)
return -EPROTO;
*features = info->features;
tm = &info->range_min;
rtc->range_min = mktime64(tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min,
tm->tm_sec);
tm = &info->range_max;
rtc->range_max = mktime64(tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min,
tm->tm_sec);
return 0;
}
static int optee_ctx_match(struct tee_ioctl_version_data *ver, const void *data)
{
if (ver->impl_id == TEE_IMPL_ID_OPTEE)
return 1;
else
return 0;
}
static int optee_rtc_probe(struct device *dev)
{
struct tee_client_device *rtc_device = to_tee_client_device(dev);
struct tee_ioctl_open_session_arg sess_arg;
struct optee_rtc *priv;
struct rtc_device *rtc;
struct tee_shm *shm;
int ret, err;
memset(&sess_arg, 0, sizeof(sess_arg));
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
/* Open context with TEE driver */
priv->ctx = tee_client_open_context(NULL, optee_ctx_match, NULL, NULL);
if (IS_ERR(priv->ctx))
return -ENODEV;
/* Open session with rtc Trusted App */
export_uuid(sess_arg.uuid, &rtc_device->id.uuid);
sess_arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL;
ret = tee_client_open_session(priv->ctx, &sess_arg, NULL);
if (ret < 0 || sess_arg.ret != 0) {
dev_err(dev, "tee_client_open_session failed, err: %x\n", sess_arg.ret);
err = -EINVAL;
goto out_ctx;
}
priv->session_id = sess_arg.session;
shm = tee_shm_alloc_kernel_buf(priv->ctx, sizeof(struct optee_rtc_info));
if (IS_ERR(shm)) {
dev_err(priv->dev, "tee_shm_alloc_kernel_buf failed\n");
err = PTR_ERR(shm);
goto out_sess;
}
priv->shm = shm;
priv->dev = dev;
dev_set_drvdata(dev, priv);
rtc->ops = &optee_rtc_ops;
err = optee_rtc_read_info(dev, rtc, &priv->features);
if (err) {
dev_err(dev, "Failed to get RTC features from OP-TEE\n");
goto out_shm;
}
err = devm_rtc_register_device(rtc);
if (err)
goto out_shm;
/*
* We must clear this bit after registering because rtc_register_device
* will set it if it sees that .set_offset is provided.
*/
if (!(priv->features & TA_RTC_FEATURE_CORRECTION))
clear_bit(RTC_FEATURE_CORRECTION, rtc->features);
return 0;
out_shm:
tee_shm_free(priv->shm);
out_sess:
tee_client_close_session(priv->ctx, priv->session_id);
out_ctx:
tee_client_close_context(priv->ctx);
return err;
}
static int optee_rtc_remove(struct device *dev)
{
struct optee_rtc *priv = dev_get_drvdata(dev);
tee_client_close_session(priv->ctx, priv->session_id);
tee_client_close_context(priv->ctx);
return 0;
}
static const struct tee_client_device_id optee_rtc_id_table[] = {
{UUID_INIT(0xf389f8c8, 0x845f, 0x496c,
0x8b, 0xbe, 0xd6, 0x4b, 0xd2, 0x4c, 0x92, 0xfd)},
{}
};
MODULE_DEVICE_TABLE(tee, optee_rtc_id_table);
static struct tee_client_driver optee_rtc_driver = {
.id_table = optee_rtc_id_table,
.driver = {
.name = "optee_rtc",
.bus = &tee_bus_type,
.probe = optee_rtc_probe,
.remove = optee_rtc_remove,
},
};
static int __init optee_rtc_mod_init(void)
{
return driver_register(&optee_rtc_driver.driver);
}
static void __exit optee_rtc_mod_exit(void)
{
driver_unregister(&optee_rtc_driver.driver);
}
module_init(optee_rtc_mod_init);
module_exit(optee_rtc_mod_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Clément Léger <[email protected]>");
MODULE_DESCRIPTION("OP-TEE based RTC driver");
| linux-master | drivers/rtc/rtc-optee.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Texas Instruments K3 RTC driver
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/sys_soc.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
/* Registers */
#define REG_K3RTC_S_CNT_LSW 0x08
#define REG_K3RTC_S_CNT_MSW 0x0c
#define REG_K3RTC_COMP 0x10
#define REG_K3RTC_ON_OFF_S_CNT_LSW 0x20
#define REG_K3RTC_ON_OFF_S_CNT_MSW 0x24
#define REG_K3RTC_SCRATCH0 0x30
#define REG_K3RTC_SCRATCH7 0x4c
#define REG_K3RTC_GENERAL_CTL 0x50
#define REG_K3RTC_IRQSTATUS_RAW_SYS 0x54
#define REG_K3RTC_IRQSTATUS_SYS 0x58
#define REG_K3RTC_IRQENABLE_SET_SYS 0x5c
#define REG_K3RTC_IRQENABLE_CLR_SYS 0x60
#define REG_K3RTC_SYNCPEND 0x68
#define REG_K3RTC_KICK0 0x70
#define REG_K3RTC_KICK1 0x74
/* Freeze when lsw is read and unfreeze when msw is read */
#define K3RTC_CNT_FMODE_S_CNT_VALUE (0x2 << 24)
/* Magic values for lock/unlock */
#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13
#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0
/* Multiplier for ppb conversions */
#define K3RTC_PPB_MULT (1000000000LL)
/* Min and max values supported with 'offset' interface (swapped sign) */
#define K3RTC_MIN_OFFSET (-277761)
#define K3RTC_MAX_OFFSET (277778)
static const struct regmap_config ti_k3_rtc_regmap_config = {
.name = "peripheral-registers",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = REG_K3RTC_KICK1,
};
enum ti_k3_rtc_fields {
K3RTC_KICK0,
K3RTC_KICK1,
K3RTC_S_CNT_LSW,
K3RTC_S_CNT_MSW,
K3RTC_O32K_OSC_DEP_EN,
K3RTC_UNLOCK,
K3RTC_CNT_FMODE,
K3RTC_PEND,
K3RTC_RELOAD_FROM_BBD,
K3RTC_COMP,
K3RTC_ALM_S_CNT_LSW,
K3RTC_ALM_S_CNT_MSW,
K3RTC_IRQ_STATUS_RAW,
K3RTC_IRQ_STATUS,
K3RTC_IRQ_ENABLE_SET,
K3RTC_IRQ_ENABLE_CLR,
K3RTC_IRQ_STATUS_ALT,
K3RTC_IRQ_ENABLE_CLR_ALT,
K3_RTC_MAX_FIELDS
};
static const struct reg_field ti_rtc_reg_fields[] = {
[K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31),
[K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31),
[K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31),
[K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15),
[K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21),
[K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23),
[K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25),
[K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1),
[K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31),
[K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31),
/* We use on to off as alarm trigger */
[K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31),
[K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15),
[K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0),
[K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0),
[K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0),
[K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0),
/* Off to on is alternate */
[K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1),
[K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1),
};
/**
* struct ti_k3_rtc - Private data for ti-k3-rtc
* @irq: IRQ
* @sync_timeout_us: data sync timeout period in uSec
* @rate_32k: 32k clock rate in Hz
* @rtc_dev: rtc device
* @regmap: rtc mmio regmap
* @r_fields: rtc register fields
*/
struct ti_k3_rtc {
unsigned int irq;
u32 sync_timeout_us;
unsigned long rate_32k;
struct rtc_device *rtc_dev;
struct regmap *regmap;
struct regmap_field *r_fields[K3_RTC_MAX_FIELDS];
};
static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f)
{
int ret;
int val;
ret = regmap_field_read(priv->r_fields[f], &val);
/*
* We shouldn't be seeing regmap fail on us for mmio reads
* This is possible if clock context fails, but that isn't the case for us
*/
if (WARN_ON_ONCE(ret))
return ret;
return val;
}
static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val)
{
regmap_field_write(priv->r_fields[f], val);
}
/**
* k3rtc_fence - Ensure a register sync took place between the two domains
* @priv: pointer to priv data
*
* Return: 0 if the sync took place, else returns -ETIMEDOUT
*/
static int k3rtc_fence(struct ti_k3_rtc *priv)
{
int ret;
ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret,
!ret, 2, priv->sync_timeout_us);
return ret;
}
static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv)
{
int ret;
ret = k3rtc_field_read(priv, K3RTC_UNLOCK);
if (ret < 0)
return ret;
return (ret) ? 0 : 1;
}
static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv)
{
int ret;
ret = k3rtc_check_unlocked(priv);
if (!ret)
return ret;
k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE);
k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE);
/* Skip fence since we are going to check the unlock bit as fence */
ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret,
ret, 2, priv->sync_timeout_us);
return ret;
}
/*
* This is the list of SoCs affected by TI's i2327 errata causing the RTC
* state-machine to break if not unlocked fast enough during boot. These
* SoCs must have the bootloader unlock this device very early in the
* boot-flow before we (Linux) can use this device.
*/
static const struct soc_device_attribute has_erratum_i2327[] = {
{ .family = "AM62X", .revision = "SR1.0" },
{ /* sentinel */ }
};
static int k3rtc_configure(struct device *dev)
{
int ret;
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
/*
* HWBUG: The compare state machine is broken if the RTC module
* is NOT unlocked in under one second of boot - which is pretty long
* time from the perspective of Linux driver (module load, u-boot
* shell all can take much longer than this.
*
* In such occurrence, it is assumed that the RTC module is unusable
*/
if (soc_device_match(has_erratum_i2327)) {
ret = k3rtc_check_unlocked(priv);
/* If there is an error OR if we are locked, return error */
if (ret) {
dev_err(dev,
HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n");
return -EFAULT;
}
} else {
/* May need to explicitly unlock first time */
ret = k3rtc_unlock_rtc(priv);
if (ret) {
dev_err(dev, "Failed to unlock(%d)!\n", ret);
return ret;
}
}
/* Enable Shadow register sync on 32k clock boundary */
k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1);
/*
* Wait at least clock sync time before proceeding further programming.
* This ensures that the 32k based sync is active.
*/
usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5);
/* We need to ensure fence here to make sure sync here */
ret = k3rtc_fence(priv);
if (ret) {
dev_err(dev,
"Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret);
return ret;
}
/*
* FMODE setting: Reading lower seconds will freeze value on higher
* seconds. This also implies that we must *ALWAYS* read lower seconds
* prior to reading higher seconds
*/
k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE);
/* Clear any spurious IRQ sources if any */
k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1);
k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1);
/* Disable all IRQs */
k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1);
k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1);
/* And.. Let us Sync the writes in */
return k3rtc_fence(priv);
}
static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
u32 seconds_lo, seconds_hi;
seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW);
seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW);
rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm);
return 0;
}
static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
time64_t seconds;
seconds = rtc_tm_to_time64(tm);
/*
* Read operation on LSW will freeze the RTC, so to update
* the time, we cannot use field operations. Just write since the
* reserved bits are ignored.
*/
regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds);
regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32);
return k3rtc_fence(priv);
}
static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
u32 reg;
u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR;
reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
if ((enabled && reg) || (!enabled && !reg))
return 0;
k3rtc_field_write(priv, offset, 0x1);
/*
* Ensure the write sync is through - NOTE: it should be OK to have
* ISR to fire as we are checking sync (which should be done in a 32k
* cycle or so).
*/
return k3rtc_fence(priv);
}
static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
u32 seconds_lo, seconds_hi;
seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW);
seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW);
rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time);
alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
return 0;
}
static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
time64_t seconds;
int ret;
seconds = rtc_tm_to_time64(&alarm->time);
k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds);
k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32));
/* Make sure the alarm time is synced in */
ret = k3rtc_fence(priv);
if (ret) {
dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret);
return ret;
}
/* Alarm IRQ enable will do a sync */
return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled);
}
static int ti_k3_rtc_read_offset(struct device *dev, long *offset)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
u32 ticks_per_hr = priv->rate_32k * 3600;
int comp;
s64 tmp;
comp = k3rtc_field_read(priv, K3RTC_COMP);
/* Convert from RTC calibration register format to ppb format */
tmp = comp * (s64)K3RTC_PPB_MULT;
if (tmp < 0)
tmp -= ticks_per_hr / 2LL;
else
tmp += ticks_per_hr / 2LL;
tmp = div_s64(tmp, ticks_per_hr);
/* Offset value operates in negative way, so swap sign */
*offset = (long)-tmp;
return 0;
}
static int ti_k3_rtc_set_offset(struct device *dev, long offset)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
u32 ticks_per_hr = priv->rate_32k * 3600;
int comp;
s64 tmp;
/* Make sure offset value is within supported range */
if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET)
return -ERANGE;
/* Convert from ppb format to RTC calibration register format */
tmp = offset * (s64)ticks_per_hr;
if (tmp < 0)
tmp -= K3RTC_PPB_MULT / 2LL;
else
tmp += K3RTC_PPB_MULT / 2LL;
tmp = div_s64(tmp, K3RTC_PPB_MULT);
/* Offset value operates in negative way, so swap sign */
comp = (int)-tmp;
k3rtc_field_write(priv, K3RTC_COMP, comp);
return k3rtc_fence(priv);
}
static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id)
{
struct device *dev = dev_id;
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
u32 reg;
int ret;
/*
* IRQ assertion can be very fast, however, the IRQ Status clear
* de-assert depends on 32k clock edge in the 32k domain
* If we clear the status prior to the first 32k clock edge,
* the status bit is cleared, but the IRQ stays re-asserted.
*
* To prevent this condition, we need to wait for clock sync time.
* We can either do that by polling the 32k observability signal for
* a toggle OR we could just sleep and let the processor do other
* stuff.
*/
usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2);
/* Lets make sure that this is a valid interrupt */
reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS);
if (!reg) {
u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW);
dev_err(dev,
HW_ERR
"Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw);
return IRQ_NONE;
}
/*
* Write 1 to clear status reg
* We cannot use a field operation here due to a potential race between
* 32k domain and vbus domain.
*/
regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1);
/* Sync the write in */
ret = k3rtc_fence(priv);
if (ret) {
dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret);
return IRQ_NONE;
}
/*
* Force the 32k status to be reloaded back in to ensure status is
* reflected back correctly.
*/
k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1);
/* Ensure the write sync is through */
ret = k3rtc_fence(priv);
if (ret) {
dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret);
return IRQ_NONE;
}
/* Now we ensure that the status bit is cleared */
ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS],
ret, !ret, 2, priv->sync_timeout_us);
if (ret) {
dev_err(dev, "Time out waiting for status clear\n");
return IRQ_NONE;
}
/* Notify RTC core on event */
rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static const struct rtc_class_ops ti_k3_rtc_ops = {
.read_time = ti_k3_rtc_read_time,
.set_time = ti_k3_rtc_set_time,
.read_alarm = ti_k3_rtc_read_alarm,
.set_alarm = ti_k3_rtc_set_alarm,
.read_offset = ti_k3_rtc_read_offset,
.set_offset = ti_k3_rtc_set_offset,
.alarm_irq_enable = ti_k3_rtc_alarm_irq_enable,
};
static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset,
void *val, size_t bytes)
{
struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
}
static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset,
void *val, size_t bytes)
{
struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
int ret;
ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
if (ret)
return ret;
return k3rtc_fence(priv);
}
static struct nvmem_config ti_k3_rtc_nvmem_config = {
.name = "ti_k3_rtc_scratch",
.word_size = 4,
.stride = 4,
.size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4,
.reg_read = ti_k3_rtc_scratch_read,
.reg_write = ti_k3_rtc_scratch_write,
};
static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv)
{
struct clk *clk;
clk = devm_clk_get_enabled(dev, "osc32k");
if (IS_ERR(clk))
return PTR_ERR(clk);
priv->rate_32k = clk_get_rate(clk);
/* Make sure we are exact 32k clock. Else, try to compensate delay */
if (priv->rate_32k != 32768)
dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n",
priv->rate_32k);
/*
* Sync timeout should be two 32k clk sync cycles = ~61uS. We double
* it to comprehend intermediate bus segment and cpu frequency
* deltas
*/
priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4);
return 0;
}
static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv)
{
struct clk *clk;
/* Note: VBUS isn't a context clock, it is needed for hardware operation */
clk = devm_clk_get_enabled(dev, "vbus");
if (IS_ERR(clk))
return PTR_ERR(clk);
return 0;
}
static int ti_k3_rtc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct ti_k3_rtc *priv;
void __iomem *rtc_base;
int ret;
priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL);
if (!priv)
return -ENOMEM;
rtc_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc_base))
return PTR_ERR(rtc_base);
priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields,
ti_rtc_reg_fields, K3_RTC_MAX_FIELDS);
if (ret)
return ret;
ret = k3rtc_get_32kclk(dev, priv);
if (ret)
return ret;
ret = k3rtc_get_vbusclk(dev, priv);
if (ret)
return ret;
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return ret;
priv->irq = (unsigned int)ret;
priv->rtc_dev = devm_rtc_allocate_device(dev);
if (IS_ERR(priv->rtc_dev))
return PTR_ERR(priv->rtc_dev);
priv->rtc_dev->ops = &ti_k3_rtc_ops;
priv->rtc_dev->range_max = (1ULL << 48) - 1; /* 48Bit seconds */
ti_k3_rtc_nvmem_config.priv = priv;
ret = devm_request_threaded_irq(dev, priv->irq, NULL,
ti_k3_rtc_interrupt,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
dev_name(dev), dev);
if (ret) {
dev_err(dev, "Could not request IRQ: %d\n", ret);
return ret;
}
platform_set_drvdata(pdev, priv);
ret = k3rtc_configure(dev);
if (ret)
return ret;
if (device_property_present(dev, "wakeup-source"))
device_init_wakeup(dev, true);
else
device_set_wakeup_capable(dev, true);
ret = devm_rtc_register_device(priv->rtc_dev);
if (ret)
return ret;
return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config);
}
static const struct of_device_id ti_k3_rtc_of_match_table[] = {
{.compatible = "ti,am62-rtc" },
{}
};
MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table);
static int __maybe_unused ti_k3_rtc_suspend(struct device *dev)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
return enable_irq_wake(priv->irq);
return 0;
}
static int __maybe_unused ti_k3_rtc_resume(struct device *dev)
{
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(priv->irq);
return 0;
}
static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume);
static struct platform_driver ti_k3_rtc_driver = {
.probe = ti_k3_rtc_probe,
.driver = {
.name = "rtc-ti-k3",
.of_match_table = ti_k3_rtc_of_match_table,
.pm = &ti_k3_rtc_pm_ops,
},
};
module_platform_driver(ti_k3_rtc_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("TI K3 RTC driver");
MODULE_AUTHOR("Nishanth Menon");
| linux-master | drivers/rtc/rtc-ti-k3.c |
// SPDX-License-Identifier: GPL-2.0
/*
* drivers/rtc/rtc-pcf85363.c
*
* Driver for NXP PCF85363 real-time clock.
*
* Copyright (C) 2017 Eric Nelson
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/regmap.h>
/*
* Date/Time registers
*/
#define DT_100THS 0x00
#define DT_SECS 0x01
#define DT_MINUTES 0x02
#define DT_HOURS 0x03
#define DT_DAYS 0x04
#define DT_WEEKDAYS 0x05
#define DT_MONTHS 0x06
#define DT_YEARS 0x07
/*
* Alarm registers
*/
#define DT_SECOND_ALM1 0x08
#define DT_MINUTE_ALM1 0x09
#define DT_HOUR_ALM1 0x0a
#define DT_DAY_ALM1 0x0b
#define DT_MONTH_ALM1 0x0c
#define DT_MINUTE_ALM2 0x0d
#define DT_HOUR_ALM2 0x0e
#define DT_WEEKDAY_ALM2 0x0f
#define DT_ALARM_EN 0x10
/*
* Time stamp registers
*/
#define DT_TIMESTAMP1 0x11
#define DT_TIMESTAMP2 0x17
#define DT_TIMESTAMP3 0x1d
#define DT_TS_MODE 0x23
/*
* control registers
*/
#define CTRL_OFFSET 0x24
#define CTRL_OSCILLATOR 0x25
#define CTRL_BATTERY 0x26
#define CTRL_PIN_IO 0x27
#define CTRL_FUNCTION 0x28
#define CTRL_INTA_EN 0x29
#define CTRL_INTB_EN 0x2a
#define CTRL_FLAGS 0x2b
#define CTRL_RAMBYTE 0x2c
#define CTRL_WDOG 0x2d
#define CTRL_STOP_EN 0x2e
#define CTRL_RESETS 0x2f
#define CTRL_RAM 0x40
#define ALRM_SEC_A1E BIT(0)
#define ALRM_MIN_A1E BIT(1)
#define ALRM_HR_A1E BIT(2)
#define ALRM_DAY_A1E BIT(3)
#define ALRM_MON_A1E BIT(4)
#define ALRM_MIN_A2E BIT(5)
#define ALRM_HR_A2E BIT(6)
#define ALRM_DAY_A2E BIT(7)
#define INT_WDIE BIT(0)
#define INT_BSIE BIT(1)
#define INT_TSRIE BIT(2)
#define INT_A2IE BIT(3)
#define INT_A1IE BIT(4)
#define INT_OIE BIT(5)
#define INT_PIE BIT(6)
#define INT_ILP BIT(7)
#define FLAGS_TSR1F BIT(0)
#define FLAGS_TSR2F BIT(1)
#define FLAGS_TSR3F BIT(2)
#define FLAGS_BSF BIT(3)
#define FLAGS_WDF BIT(4)
#define FLAGS_A1F BIT(5)
#define FLAGS_A2F BIT(6)
#define FLAGS_PIF BIT(7)
#define PIN_IO_INTAPM GENMASK(1, 0)
#define PIN_IO_INTA_CLK 0
#define PIN_IO_INTA_BAT 1
#define PIN_IO_INTA_OUT 2
#define PIN_IO_INTA_HIZ 3
#define OSC_CAP_SEL GENMASK(1, 0)
#define OSC_CAP_6000 0x01
#define OSC_CAP_12500 0x02
#define STOP_EN_STOP BIT(0)
#define RESET_CPR 0xa4
#define NVRAM_SIZE 0x40
struct pcf85363 {
struct rtc_device *rtc;
struct regmap *regmap;
};
struct pcf85x63_config {
struct regmap_config regmap;
unsigned int num_nvram;
};
static int pcf85363_load_capacitance(struct pcf85363 *pcf85363, struct device_node *node)
{
u32 load = 7000;
u8 value = 0;
of_property_read_u32(node, "quartz-load-femtofarads", &load);
switch (load) {
default:
dev_warn(&pcf85363->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
load);
fallthrough;
case 7000:
break;
case 6000:
value = OSC_CAP_6000;
break;
case 12500:
value = OSC_CAP_12500;
break;
}
return regmap_update_bits(pcf85363->regmap, CTRL_OSCILLATOR,
OSC_CAP_SEL, value);
}
static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
unsigned char buf[DT_YEARS + 1];
int ret, len = sizeof(buf);
/* read the RTC date and time registers all at once */
ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len);
if (ret) {
dev_err(dev, "%s: error %d\n", __func__, ret);
return ret;
}
tm->tm_year = bcd2bin(buf[DT_YEARS]);
/* adjust for 1900 base of rtc_time */
tm->tm_year += 100;
tm->tm_wday = buf[DT_WEEKDAYS] & 7;
buf[DT_SECS] &= 0x7F;
tm->tm_sec = bcd2bin(buf[DT_SECS]);
buf[DT_MINUTES] &= 0x7F;
tm->tm_min = bcd2bin(buf[DT_MINUTES]);
tm->tm_hour = bcd2bin(buf[DT_HOURS]);
tm->tm_mday = bcd2bin(buf[DT_DAYS]);
tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1;
return 0;
}
static int pcf85363_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
unsigned char tmp[11];
unsigned char *buf = &tmp[2];
int ret;
tmp[0] = STOP_EN_STOP;
tmp[1] = RESET_CPR;
buf[DT_100THS] = 0;
buf[DT_SECS] = bin2bcd(tm->tm_sec);
buf[DT_MINUTES] = bin2bcd(tm->tm_min);
buf[DT_HOURS] = bin2bcd(tm->tm_hour);
buf[DT_DAYS] = bin2bcd(tm->tm_mday);
buf[DT_WEEKDAYS] = tm->tm_wday;
buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1);
buf[DT_YEARS] = bin2bcd(tm->tm_year % 100);
ret = regmap_bulk_write(pcf85363->regmap, CTRL_STOP_EN,
tmp, 2);
if (ret)
return ret;
ret = regmap_bulk_write(pcf85363->regmap, DT_100THS,
buf, sizeof(tmp) - 2);
if (ret)
return ret;
return regmap_write(pcf85363->regmap, CTRL_STOP_EN, 0);
}
static int pcf85363_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
unsigned int val;
int ret;
ret = regmap_bulk_read(pcf85363->regmap, DT_SECOND_ALM1, buf,
sizeof(buf));
if (ret)
return ret;
alrm->time.tm_sec = bcd2bin(buf[0]);
alrm->time.tm_min = bcd2bin(buf[1]);
alrm->time.tm_hour = bcd2bin(buf[2]);
alrm->time.tm_mday = bcd2bin(buf[3]);
alrm->time.tm_mon = bcd2bin(buf[4]) - 1;
ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val);
if (ret)
return ret;
alrm->enabled = !!(val & INT_A1IE);
return 0;
}
static int _pcf85363_rtc_alarm_irq_enable(struct pcf85363 *pcf85363, unsigned
int enabled)
{
unsigned int alarm_flags = ALRM_SEC_A1E | ALRM_MIN_A1E | ALRM_HR_A1E |
ALRM_DAY_A1E | ALRM_MON_A1E;
int ret;
ret = regmap_update_bits(pcf85363->regmap, DT_ALARM_EN, alarm_flags,
enabled ? alarm_flags : 0);
if (ret)
return ret;
ret = regmap_update_bits(pcf85363->regmap, CTRL_INTA_EN,
INT_A1IE, enabled ? INT_A1IE : 0);
if (ret || enabled)
return ret;
/* clear current flags */
return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
}
static int pcf85363_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
return _pcf85363_rtc_alarm_irq_enable(pcf85363, enabled);
}
static int pcf85363_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
int ret;
buf[0] = bin2bcd(alrm->time.tm_sec);
buf[1] = bin2bcd(alrm->time.tm_min);
buf[2] = bin2bcd(alrm->time.tm_hour);
buf[3] = bin2bcd(alrm->time.tm_mday);
buf[4] = bin2bcd(alrm->time.tm_mon + 1);
/*
* Disable the alarm interrupt before changing the value to avoid
* spurious interrupts
*/
ret = _pcf85363_rtc_alarm_irq_enable(pcf85363, 0);
if (ret)
return ret;
ret = regmap_bulk_write(pcf85363->regmap, DT_SECOND_ALM1, buf,
sizeof(buf));
if (ret)
return ret;
return _pcf85363_rtc_alarm_irq_enable(pcf85363, alrm->enabled);
}
static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
{
struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
unsigned int flags;
int err;
err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
if (err)
return IRQ_NONE;
if (flags & FLAGS_A1F) {
rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF | RTC_AF);
regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static const struct rtc_class_ops rtc_ops = {
.read_time = pcf85363_rtc_read_time,
.set_time = pcf85363_rtc_set_time,
.read_alarm = pcf85363_rtc_read_alarm,
.set_alarm = pcf85363_rtc_set_alarm,
.alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
};
static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct pcf85363 *pcf85363 = priv;
return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset,
val, bytes);
}
static int pcf85363_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct pcf85363 *pcf85363 = priv;
return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset,
val, bytes);
}
static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct pcf85363 *pcf85363 = priv;
unsigned int tmp_val;
int ret;
ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, &tmp_val);
(*(unsigned char *) val) = (unsigned char) tmp_val;
return ret;
}
static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct pcf85363 *pcf85363 = priv;
unsigned char tmp_val;
tmp_val = *((unsigned char *)val);
return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
(unsigned int)tmp_val);
}
static const struct pcf85x63_config pcf_85263_config = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x2f,
},
.num_nvram = 1
};
static const struct pcf85x63_config pcf_85363_config = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x7f,
},
.num_nvram = 2
};
static int pcf85363_probe(struct i2c_client *client)
{
struct pcf85363 *pcf85363;
const struct pcf85x63_config *config = &pcf_85363_config;
const void *data = of_device_get_match_data(&client->dev);
static struct nvmem_config nvmem_cfg[] = {
{
.name = "pcf85x63-",
.word_size = 1,
.stride = 1,
.size = 1,
.reg_read = pcf85x63_nvram_read,
.reg_write = pcf85x63_nvram_write,
}, {
.name = "pcf85363-",
.word_size = 1,
.stride = 1,
.size = NVRAM_SIZE,
.reg_read = pcf85363_nvram_read,
.reg_write = pcf85363_nvram_write,
},
};
int ret, i, err;
bool wakeup_source;
if (data)
config = data;
pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
GFP_KERNEL);
if (!pcf85363)
return -ENOMEM;
pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
if (IS_ERR(pcf85363->regmap)) {
dev_err(&client->dev, "regmap allocation failed\n");
return PTR_ERR(pcf85363->regmap);
}
i2c_set_clientdata(client, pcf85363);
pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(pcf85363->rtc))
return PTR_ERR(pcf85363->rtc);
err = pcf85363_load_capacitance(pcf85363, client->dev.of_node);
if (err < 0)
dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
err);
pcf85363->rtc->ops = &rtc_ops;
pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;
wakeup_source = device_property_read_bool(&client->dev,
"wakeup-source");
if (client->irq > 0 || wakeup_source) {
regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
PIN_IO_INTA_OUT, PIN_IO_INTAPM);
}
if (client->irq > 0) {
unsigned long irqflags = IRQF_TRIGGER_LOW;
if (dev_fwnode(&client->dev))
irqflags = 0;
ret = devm_request_threaded_irq(&client->dev, client->irq,
NULL, pcf85363_rtc_handle_irq,
irqflags | IRQF_ONESHOT,
"pcf85363", client);
if (ret) {
dev_warn(&client->dev,
"unable to request IRQ, alarms disabled\n");
client->irq = 0;
}
}
if (client->irq > 0 || wakeup_source) {
device_init_wakeup(&client->dev, true);
set_bit(RTC_FEATURE_ALARM, pcf85363->rtc->features);
} else {
clear_bit(RTC_FEATURE_ALARM, pcf85363->rtc->features);
}
ret = devm_rtc_register_device(pcf85363->rtc);
for (i = 0; i < config->num_nvram; i++) {
nvmem_cfg[i].priv = pcf85363;
devm_rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
}
return ret;
}
static const __maybe_unused struct of_device_id dev_ids[] = {
{ .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
{ .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dev_ids);
static struct i2c_driver pcf85363_driver = {
.driver = {
.name = "pcf85363",
.of_match_table = of_match_ptr(dev_ids),
},
.probe = pcf85363_probe,
};
module_i2c_driver(pcf85363_driver);
MODULE_AUTHOR("Eric Nelson");
MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pcf85363.c |
// SPDX-License-Identifier: GPL-2.0
/*
* An RTC test device/driver
* Copyright (C) 2005 Tower Technologies
* Author: Alessandro Zummo <[email protected]>
*/
#include <linux/module.h>
#include <linux/err.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#define MAX_RTC_TEST 3
struct rtc_test_data {
struct rtc_device *rtc;
time64_t offset;
struct timer_list alarm;
bool alarm_en;
};
static struct platform_device *pdev[MAX_RTC_TEST];
static int test_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_test_data *rtd = dev_get_drvdata(dev);
time64_t alarm;
alarm = (rtd->alarm.expires - jiffies) / HZ;
alarm += ktime_get_real_seconds() + rtd->offset;
rtc_time64_to_tm(alarm, &alrm->time);
alrm->enabled = rtd->alarm_en;
return 0;
}
static int test_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_test_data *rtd = dev_get_drvdata(dev);
ktime_t timeout;
u64 expires;
timeout = rtc_tm_to_time64(&alrm->time) - ktime_get_real_seconds();
timeout -= rtd->offset;
del_timer(&rtd->alarm);
expires = jiffies + timeout * HZ;
if (expires > U32_MAX)
expires = U32_MAX;
rtd->alarm.expires = expires;
if (alrm->enabled)
add_timer(&rtd->alarm);
rtd->alarm_en = alrm->enabled;
return 0;
}
static int test_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_test_data *rtd = dev_get_drvdata(dev);
rtc_time64_to_tm(ktime_get_real_seconds() + rtd->offset, tm);
return 0;
}
static int test_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_test_data *rtd = dev_get_drvdata(dev);
rtd->offset = rtc_tm_to_time64(tm) - ktime_get_real_seconds();
return 0;
}
static int test_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct rtc_test_data *rtd = dev_get_drvdata(dev);
rtd->alarm_en = enable;
if (enable)
add_timer(&rtd->alarm);
else
del_timer(&rtd->alarm);
return 0;
}
static const struct rtc_class_ops test_rtc_ops_noalm = {
.read_time = test_rtc_read_time,
.set_time = test_rtc_set_time,
.alarm_irq_enable = test_rtc_alarm_irq_enable,
};
static const struct rtc_class_ops test_rtc_ops = {
.read_time = test_rtc_read_time,
.set_time = test_rtc_set_time,
.read_alarm = test_rtc_read_alarm,
.set_alarm = test_rtc_set_alarm,
.alarm_irq_enable = test_rtc_alarm_irq_enable,
};
static void test_rtc_alarm_handler(struct timer_list *t)
{
struct rtc_test_data *rtd = from_timer(rtd, t, alarm);
rtc_update_irq(rtd->rtc, 1, RTC_AF | RTC_IRQF);
}
static int test_probe(struct platform_device *plat_dev)
{
struct rtc_test_data *rtd;
rtd = devm_kzalloc(&plat_dev->dev, sizeof(*rtd), GFP_KERNEL);
if (!rtd)
return -ENOMEM;
platform_set_drvdata(plat_dev, rtd);
rtd->rtc = devm_rtc_allocate_device(&plat_dev->dev);
if (IS_ERR(rtd->rtc))
return PTR_ERR(rtd->rtc);
switch (plat_dev->id) {
case 0:
rtd->rtc->ops = &test_rtc_ops_noalm;
break;
default:
rtd->rtc->ops = &test_rtc_ops;
device_init_wakeup(&plat_dev->dev, 1);
}
timer_setup(&rtd->alarm, test_rtc_alarm_handler, 0);
rtd->alarm.expires = 0;
return devm_rtc_register_device(rtd->rtc);
}
static struct platform_driver test_driver = {
.probe = test_probe,
.driver = {
.name = "rtc-test",
},
};
static int __init test_init(void)
{
int i, err;
err = platform_driver_register(&test_driver);
if (err)
return err;
err = -ENOMEM;
for (i = 0; i < MAX_RTC_TEST; i++) {
pdev[i] = platform_device_alloc("rtc-test", i);
if (!pdev[i])
goto exit_free_mem;
}
for (i = 0; i < MAX_RTC_TEST; i++) {
err = platform_device_add(pdev[i]);
if (err)
goto exit_device_del;
}
return 0;
exit_device_del:
for (; i > 0; i--)
platform_device_del(pdev[i - 1]);
exit_free_mem:
for (i = 0; i < MAX_RTC_TEST; i++)
platform_device_put(pdev[i]);
platform_driver_unregister(&test_driver);
return err;
}
static void __exit test_exit(void)
{
int i;
for (i = 0; i < MAX_RTC_TEST; i++)
platform_device_unregister(pdev[i]);
platform_driver_unregister(&test_driver);
}
MODULE_AUTHOR("Alessandro Zummo <[email protected]>");
MODULE_DESCRIPTION("RTC test driver/device");
MODULE_LICENSE("GPL v2");
module_init(test_init);
module_exit(test_exit);
| linux-master | drivers/rtc/rtc-test.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright © 2014-2017 Broadcom
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqreturn.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_wakeup.h>
#include <linux/reboot.h>
#include <linux/rtc.h>
#include <linux/stat.h>
#include <linux/suspend.h>
struct brcmstb_waketmr {
struct rtc_device *rtc;
struct device *dev;
void __iomem *base;
unsigned int wake_irq;
unsigned int alarm_irq;
struct notifier_block reboot_notifier;
struct clk *clk;
u32 rate;
unsigned long rtc_alarm;
bool alarm_en;
};
#define BRCMSTB_WKTMR_EVENT 0x00
#define WKTMR_ALARM_EVENT BIT(0)
#define BRCMSTB_WKTMR_COUNTER 0x04
#define BRCMSTB_WKTMR_ALARM 0x08
#define BRCMSTB_WKTMR_PRESCALER 0x0C
#define BRCMSTB_WKTMR_PRESCALER_VAL 0x10
#define BRCMSTB_WKTMR_DEFAULT_FREQ 27000000
static inline bool brcmstb_waketmr_is_pending(struct brcmstb_waketmr *timer)
{
u32 reg;
reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT);
return !!(reg & WKTMR_ALARM_EVENT);
}
static inline void brcmstb_waketmr_clear_alarm(struct brcmstb_waketmr *timer)
{
u32 reg;
if (timer->alarm_en && timer->alarm_irq)
disable_irq(timer->alarm_irq);
timer->alarm_en = false;
reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER);
writel_relaxed(reg - 1, timer->base + BRCMSTB_WKTMR_ALARM);
writel_relaxed(WKTMR_ALARM_EVENT, timer->base + BRCMSTB_WKTMR_EVENT);
(void)readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT);
}
static void brcmstb_waketmr_set_alarm(struct brcmstb_waketmr *timer,
unsigned int secs)
{
unsigned int now;
brcmstb_waketmr_clear_alarm(timer);
/* Make sure we are actually counting in seconds */
writel_relaxed(timer->rate, timer->base + BRCMSTB_WKTMR_PRESCALER);
writel_relaxed(secs, timer->base + BRCMSTB_WKTMR_ALARM);
now = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER);
while ((int)(secs - now) <= 0 &&
!brcmstb_waketmr_is_pending(timer)) {
secs = now + 1;
writel_relaxed(secs, timer->base + BRCMSTB_WKTMR_ALARM);
now = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER);
}
}
static irqreturn_t brcmstb_waketmr_irq(int irq, void *data)
{
struct brcmstb_waketmr *timer = data;
if (!timer->alarm_irq)
pm_wakeup_event(timer->dev, 0);
return IRQ_HANDLED;
}
static irqreturn_t brcmstb_alarm_irq(int irq, void *data)
{
struct brcmstb_waketmr *timer = data;
/* Ignore spurious interrupts */
if (!brcmstb_waketmr_is_pending(timer))
return IRQ_HANDLED;
if (timer->alarm_en) {
if (!device_may_wakeup(timer->dev))
writel_relaxed(WKTMR_ALARM_EVENT,
timer->base + BRCMSTB_WKTMR_EVENT);
rtc_update_irq(timer->rtc, 1, RTC_IRQF | RTC_AF);
}
return IRQ_HANDLED;
}
struct wktmr_time {
u32 sec;
u32 pre;
};
static void wktmr_read(struct brcmstb_waketmr *timer,
struct wktmr_time *t)
{
u32 tmp;
do {
t->sec = readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER);
tmp = readl_relaxed(timer->base + BRCMSTB_WKTMR_PRESCALER_VAL);
} while (tmp >= timer->rate);
t->pre = timer->rate - tmp;
}
static int brcmstb_waketmr_prepare_suspend(struct brcmstb_waketmr *timer)
{
struct device *dev = timer->dev;
int ret;
if (device_may_wakeup(dev)) {
ret = enable_irq_wake(timer->wake_irq);
if (ret) {
dev_err(dev, "failed to enable wake-up interrupt\n");
return ret;
}
if (timer->alarm_en && timer->alarm_irq) {
ret = enable_irq_wake(timer->alarm_irq);
if (ret) {
dev_err(dev, "failed to enable rtc interrupt\n");
disable_irq_wake(timer->wake_irq);
return ret;
}
}
}
return 0;
}
/* If enabled as a wakeup-source, arm the timer when powering off */
static int brcmstb_waketmr_reboot(struct notifier_block *nb,
unsigned long action, void *data)
{
struct brcmstb_waketmr *timer;
timer = container_of(nb, struct brcmstb_waketmr, reboot_notifier);
/* Set timer for cold boot */
if (action == SYS_POWER_OFF)
brcmstb_waketmr_prepare_suspend(timer);
return NOTIFY_DONE;
}
static int brcmstb_waketmr_gettime(struct device *dev,
struct rtc_time *tm)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
struct wktmr_time now;
wktmr_read(timer, &now);
rtc_time64_to_tm(now.sec, tm);
return 0;
}
static int brcmstb_waketmr_settime(struct device *dev,
struct rtc_time *tm)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
time64_t sec;
sec = rtc_tm_to_time64(tm);
writel_relaxed(sec, timer->base + BRCMSTB_WKTMR_COUNTER);
return 0;
}
static int brcmstb_waketmr_getalarm(struct device *dev,
struct rtc_wkalrm *alarm)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
alarm->enabled = timer->alarm_en;
rtc_time64_to_tm(timer->rtc_alarm, &alarm->time);
alarm->pending = brcmstb_waketmr_is_pending(timer);
return 0;
}
static int brcmstb_waketmr_alarm_enable(struct device *dev,
unsigned int enabled)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
if (enabled && !timer->alarm_en) {
if ((int)(readl_relaxed(timer->base + BRCMSTB_WKTMR_COUNTER) -
readl_relaxed(timer->base + BRCMSTB_WKTMR_ALARM)) >= 0 &&
!brcmstb_waketmr_is_pending(timer))
return -EINVAL;
timer->alarm_en = true;
if (timer->alarm_irq)
enable_irq(timer->alarm_irq);
} else if (!enabled && timer->alarm_en) {
if (timer->alarm_irq)
disable_irq(timer->alarm_irq);
timer->alarm_en = false;
}
return 0;
}
static int brcmstb_waketmr_setalarm(struct device *dev,
struct rtc_wkalrm *alarm)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
timer->rtc_alarm = rtc_tm_to_time64(&alarm->time);
brcmstb_waketmr_set_alarm(timer, timer->rtc_alarm);
return brcmstb_waketmr_alarm_enable(dev, alarm->enabled);
}
static const struct rtc_class_ops brcmstb_waketmr_ops = {
.read_time = brcmstb_waketmr_gettime,
.set_time = brcmstb_waketmr_settime,
.read_alarm = brcmstb_waketmr_getalarm,
.set_alarm = brcmstb_waketmr_setalarm,
.alarm_irq_enable = brcmstb_waketmr_alarm_enable,
};
static int brcmstb_waketmr_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct brcmstb_waketmr *timer;
int ret;
timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
if (!timer)
return -ENOMEM;
platform_set_drvdata(pdev, timer);
timer->dev = dev;
timer->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(timer->base))
return PTR_ERR(timer->base);
timer->rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(timer->rtc))
return PTR_ERR(timer->rtc);
/*
* Set wakeup capability before requesting wakeup interrupt, so we can
* process boot-time "wakeups" (e.g., from S5 soft-off)
*/
device_init_wakeup(dev, true);
ret = platform_get_irq(pdev, 0);
if (ret < 0)
return -ENODEV;
timer->wake_irq = (unsigned int)ret;
timer->clk = devm_clk_get(dev, NULL);
if (!IS_ERR(timer->clk)) {
ret = clk_prepare_enable(timer->clk);
if (ret)
return ret;
timer->rate = clk_get_rate(timer->clk);
if (!timer->rate)
timer->rate = BRCMSTB_WKTMR_DEFAULT_FREQ;
} else {
timer->rate = BRCMSTB_WKTMR_DEFAULT_FREQ;
timer->clk = NULL;
}
ret = devm_request_irq(dev, timer->wake_irq, brcmstb_waketmr_irq, 0,
"brcmstb-waketimer", timer);
if (ret < 0)
goto err_clk;
brcmstb_waketmr_clear_alarm(timer);
/* Attempt to initialize non-wake irq */
ret = platform_get_irq(pdev, 1);
if (ret > 0) {
timer->alarm_irq = (unsigned int)ret;
ret = devm_request_irq(dev, timer->alarm_irq, brcmstb_alarm_irq,
IRQF_NO_AUTOEN, "brcmstb-waketimer-rtc",
timer);
if (ret < 0)
timer->alarm_irq = 0;
}
timer->reboot_notifier.notifier_call = brcmstb_waketmr_reboot;
register_reboot_notifier(&timer->reboot_notifier);
timer->rtc->ops = &brcmstb_waketmr_ops;
timer->rtc->range_max = U32_MAX;
ret = devm_rtc_register_device(timer->rtc);
if (ret)
goto err_notifier;
return 0;
err_notifier:
unregister_reboot_notifier(&timer->reboot_notifier);
err_clk:
clk_disable_unprepare(timer->clk);
return ret;
}
static void brcmstb_waketmr_remove(struct platform_device *pdev)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(&pdev->dev);
unregister_reboot_notifier(&timer->reboot_notifier);
clk_disable_unprepare(timer->clk);
}
#ifdef CONFIG_PM_SLEEP
static int brcmstb_waketmr_suspend(struct device *dev)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
return brcmstb_waketmr_prepare_suspend(timer);
}
static int brcmstb_waketmr_resume(struct device *dev)
{
struct brcmstb_waketmr *timer = dev_get_drvdata(dev);
int ret;
if (!device_may_wakeup(dev))
return 0;
ret = disable_irq_wake(timer->wake_irq);
if (timer->alarm_en && timer->alarm_irq)
disable_irq_wake(timer->alarm_irq);
brcmstb_waketmr_clear_alarm(timer);
return ret;
}
#endif /* CONFIG_PM_SLEEP */
static SIMPLE_DEV_PM_OPS(brcmstb_waketmr_pm_ops,
brcmstb_waketmr_suspend, brcmstb_waketmr_resume);
static const __maybe_unused struct of_device_id brcmstb_waketmr_of_match[] = {
{ .compatible = "brcm,brcmstb-waketimer" },
{ /* sentinel */ },
};
static struct platform_driver brcmstb_waketmr_driver = {
.probe = brcmstb_waketmr_probe,
.remove_new = brcmstb_waketmr_remove,
.driver = {
.name = "brcmstb-waketimer",
.pm = &brcmstb_waketmr_pm_ops,
.of_match_table = of_match_ptr(brcmstb_waketmr_of_match),
}
};
module_platform_driver(brcmstb_waketmr_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Brian Norris");
MODULE_AUTHOR("Markus Mayer");
MODULE_AUTHOR("Doug Berger");
MODULE_DESCRIPTION("Wake-up timer driver for STB chips");
| linux-master | drivers/rtc/rtc-brcmstb-waketimer.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Dallas DS1302 RTC Support
*
* Copyright (C) 2002 David McCullough
* Copyright (C) 2003 - 2007 Paul Mundt
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#define RTC_CMD_READ 0x81 /* Read command */
#define RTC_CMD_WRITE 0x80 /* Write command */
#define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
#define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
#define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
#define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
#define RTC_CLCK_BURST 0x1F /* Address of clock burst */
#define RTC_CLCK_LEN 0x08 /* Size of clock burst */
#define RTC_ADDR_CTRL 0x07 /* Address of control register */
#define RTC_ADDR_YEAR 0x06 /* Address of year register */
#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
#define RTC_ADDR_MON 0x04 /* Address of month register */
#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
#define RTC_ADDR_MIN 0x01 /* Address of minute register */
#define RTC_ADDR_SEC 0x00 /* Address of second register */
static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
{
struct spi_device *spi = dev_get_drvdata(dev);
u8 buf[1 + RTC_CLCK_LEN];
u8 *bp;
int status;
/* Enable writing */
bp = buf;
*bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
*bp++ = RTC_CMD_WRITE_ENABLE;
status = spi_write_then_read(spi, buf, 2,
NULL, 0);
if (status)
return status;
/* Write registers starting at the first time/date address. */
bp = buf;
*bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
*bp++ = bin2bcd(time->tm_sec);
*bp++ = bin2bcd(time->tm_min);
*bp++ = bin2bcd(time->tm_hour);
*bp++ = bin2bcd(time->tm_mday);
*bp++ = bin2bcd(time->tm_mon + 1);
*bp++ = time->tm_wday + 1;
*bp++ = bin2bcd(time->tm_year % 100);
*bp++ = RTC_CMD_WRITE_DISABLE;
/* use write-then-read since dma from stack is nonportable */
return spi_write_then_read(spi, buf, sizeof(buf),
NULL, 0);
}
static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
{
struct spi_device *spi = dev_get_drvdata(dev);
u8 addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
u8 buf[RTC_CLCK_LEN - 1];
int status;
/* Use write-then-read to get all the date/time registers
* since dma from stack is nonportable
*/
status = spi_write_then_read(spi, &addr, sizeof(addr),
buf, sizeof(buf));
if (status < 0)
return status;
/* Decode the registers */
time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
time->tm_wday = buf[RTC_ADDR_DAY] - 1;
time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
return 0;
}
static const struct rtc_class_ops ds1302_rtc_ops = {
.read_time = ds1302_rtc_get_time,
.set_time = ds1302_rtc_set_time,
};
static int ds1302_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
u8 addr;
u8 buf[4];
u8 *bp;
int status;
/* Sanity check board setup data. This may be hooked up
* in 3wire mode, but we don't care. Note that unless
* there's an inverter in place, this needs SPI_CS_HIGH!
*/
if (spi->bits_per_word && (spi->bits_per_word != 8)) {
dev_err(&spi->dev, "bad word length\n");
return -EINVAL;
} else if (spi->max_speed_hz > 2000000) {
dev_err(&spi->dev, "speed is too high\n");
return -EINVAL;
} else if (spi->mode & SPI_CPHA) {
dev_err(&spi->dev, "bad mode\n");
return -EINVAL;
}
addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
if (status < 0) {
dev_err(&spi->dev, "control register read error %d\n",
status);
return status;
}
if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
if (status < 0) {
dev_err(&spi->dev, "control register read error %d\n",
status);
return status;
}
if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
dev_err(&spi->dev, "junk in control register\n");
return -ENODEV;
}
}
if (buf[0] == 0) {
bp = buf;
*bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
*bp++ = RTC_CMD_WRITE_DISABLE;
status = spi_write_then_read(spi, buf, 2, NULL, 0);
if (status < 0) {
dev_err(&spi->dev, "control register write error %d\n",
status);
return status;
}
addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
if (status < 0) {
dev_err(&spi->dev,
"error %d reading control register\n",
status);
return status;
}
if (buf[0] != RTC_CMD_WRITE_DISABLE) {
dev_err(&spi->dev, "failed to detect chip\n");
return -ENODEV;
}
}
spi_set_drvdata(spi, spi);
rtc = devm_rtc_device_register(&spi->dev, "ds1302",
&ds1302_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc)) {
status = PTR_ERR(rtc);
dev_err(&spi->dev, "error %d registering rtc\n", status);
return status;
}
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id ds1302_dt_ids[] = {
{ .compatible = "maxim,ds1302", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
#endif
static const struct spi_device_id ds1302_spi_ids[] = {
{ .name = "ds1302", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, ds1302_spi_ids);
static struct spi_driver ds1302_driver = {
.driver.name = "rtc-ds1302",
.driver.of_match_table = of_match_ptr(ds1302_dt_ids),
.probe = ds1302_probe,
.id_table = ds1302_spi_ids,
};
module_spi_driver(ds1302_driver);
MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
MODULE_AUTHOR("Paul Mundt, David McCullough");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-ds1302.c |
// SPDX-License-Identifier: GPL-2.0
/* rtc-sun4v.c: Hypervisor based RTC for SUN4V systems.
*
* Author: David S. Miller
*
* Copyright (C) 2008 David S. Miller <[email protected]>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <asm/hypervisor.h>
static unsigned long hypervisor_get_time(void)
{
unsigned long ret, time;
int retries = 10000;
retry:
ret = sun4v_tod_get(&time);
if (ret == HV_EOK)
return time;
if (ret == HV_EWOULDBLOCK) {
if (--retries > 0) {
udelay(100);
goto retry;
}
pr_warn("tod_get() timed out.\n");
return 0;
}
pr_warn("tod_get() not supported.\n");
return 0;
}
static int sun4v_read_time(struct device *dev, struct rtc_time *tm)
{
rtc_time64_to_tm(hypervisor_get_time(), tm);
return 0;
}
static int hypervisor_set_time(unsigned long secs)
{
unsigned long ret;
int retries = 10000;
retry:
ret = sun4v_tod_set(secs);
if (ret == HV_EOK)
return 0;
if (ret == HV_EWOULDBLOCK) {
if (--retries > 0) {
udelay(100);
goto retry;
}
pr_warn("tod_set() timed out.\n");
return -EAGAIN;
}
pr_warn("tod_set() not supported.\n");
return -EOPNOTSUPP;
}
static int sun4v_set_time(struct device *dev, struct rtc_time *tm)
{
return hypervisor_set_time(rtc_tm_to_time64(tm));
}
static const struct rtc_class_ops sun4v_rtc_ops = {
.read_time = sun4v_read_time,
.set_time = sun4v_set_time,
};
static int __init sun4v_rtc_probe(struct platform_device *pdev)
{
struct rtc_device *rtc;
rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &sun4v_rtc_ops;
rtc->range_max = U64_MAX;
platform_set_drvdata(pdev, rtc);
return devm_rtc_register_device(rtc);
}
static struct platform_driver sun4v_rtc_driver = {
.driver = {
.name = "rtc-sun4v",
},
};
builtin_platform_driver_probe(sun4v_rtc_driver, sun4v_rtc_probe);
| linux-master | drivers/rtc/rtc-sun4v.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Micro Crystal RV-3029 / RV-3049 rtc class driver
*
* Author: Gregory Hermant <[email protected]>
* Michael Buesch <[email protected]>
*
* based on previously existing rtc class drivers
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/kstrtox.h>
#include <linux/regmap.h>
/* Register map */
/* control section */
#define RV3029_ONOFF_CTRL 0x00
#define RV3029_ONOFF_CTRL_WE BIT(0)
#define RV3029_ONOFF_CTRL_TE BIT(1)
#define RV3029_ONOFF_CTRL_TAR BIT(2)
#define RV3029_ONOFF_CTRL_EERE BIT(3)
#define RV3029_ONOFF_CTRL_SRON BIT(4)
#define RV3029_ONOFF_CTRL_TD0 BIT(5)
#define RV3029_ONOFF_CTRL_TD1 BIT(6)
#define RV3029_ONOFF_CTRL_CLKINT BIT(7)
#define RV3029_IRQ_CTRL 0x01
#define RV3029_IRQ_CTRL_AIE BIT(0)
#define RV3029_IRQ_CTRL_TIE BIT(1)
#define RV3029_IRQ_CTRL_V1IE BIT(2)
#define RV3029_IRQ_CTRL_V2IE BIT(3)
#define RV3029_IRQ_CTRL_SRIE BIT(4)
#define RV3029_IRQ_FLAGS 0x02
#define RV3029_IRQ_FLAGS_AF BIT(0)
#define RV3029_IRQ_FLAGS_TF BIT(1)
#define RV3029_IRQ_FLAGS_V1IF BIT(2)
#define RV3029_IRQ_FLAGS_V2IF BIT(3)
#define RV3029_IRQ_FLAGS_SRF BIT(4)
#define RV3029_STATUS 0x03
#define RV3029_STATUS_VLOW1 BIT(2)
#define RV3029_STATUS_VLOW2 BIT(3)
#define RV3029_STATUS_SR BIT(4)
#define RV3029_STATUS_PON BIT(5)
#define RV3029_STATUS_EEBUSY BIT(7)
#define RV3029_RST_CTRL 0x04
#define RV3029_RST_CTRL_SYSR BIT(4)
#define RV3029_CONTROL_SECTION_LEN 0x05
/* watch section */
#define RV3029_W_SEC 0x08
#define RV3029_W_MINUTES 0x09
#define RV3029_W_HOURS 0x0A
#define RV3029_REG_HR_12_24 BIT(6) /* 24h/12h mode */
#define RV3029_REG_HR_PM BIT(5) /* PM/AM bit in 12h mode */
#define RV3029_W_DATE 0x0B
#define RV3029_W_DAYS 0x0C
#define RV3029_W_MONTHS 0x0D
#define RV3029_W_YEARS 0x0E
#define RV3029_WATCH_SECTION_LEN 0x07
/* alarm section */
#define RV3029_A_SC 0x10
#define RV3029_A_MN 0x11
#define RV3029_A_HR 0x12
#define RV3029_A_DT 0x13
#define RV3029_A_DW 0x14
#define RV3029_A_MO 0x15
#define RV3029_A_YR 0x16
#define RV3029_A_AE_X BIT(7)
#define RV3029_ALARM_SECTION_LEN 0x07
/* timer section */
#define RV3029_TIMER_LOW 0x18
#define RV3029_TIMER_HIGH 0x19
/* temperature section */
#define RV3029_TEMP_PAGE 0x20
/* eeprom data section */
#define RV3029_E2P_EEDATA1 0x28
#define RV3029_E2P_EEDATA2 0x29
#define RV3029_E2PDATA_SECTION_LEN 0x02
/* eeprom control section */
#define RV3029_CONTROL_E2P_EECTRL 0x30
#define RV3029_EECTRL_THP BIT(0) /* temp scan interval */
#define RV3029_EECTRL_THE BIT(1) /* thermometer enable */
#define RV3029_EECTRL_FD0 BIT(2) /* CLKOUT */
#define RV3029_EECTRL_FD1 BIT(3) /* CLKOUT */
#define RV3029_TRICKLE_1K BIT(4) /* 1.5K resistance */
#define RV3029_TRICKLE_5K BIT(5) /* 5K resistance */
#define RV3029_TRICKLE_20K BIT(6) /* 20K resistance */
#define RV3029_TRICKLE_80K BIT(7) /* 80K resistance */
#define RV3029_TRICKLE_MASK (RV3029_TRICKLE_1K |\
RV3029_TRICKLE_5K |\
RV3029_TRICKLE_20K |\
RV3029_TRICKLE_80K)
#define RV3029_TRICKLE_SHIFT 4
#define RV3029_CONTROL_E2P_XOFFS 0x31 /* XTAL offset */
#define RV3029_CONTROL_E2P_XOFFS_SIGN BIT(7) /* Sign: 1->pos, 0->neg */
#define RV3029_CONTROL_E2P_QCOEF 0x32 /* XTAL temp drift coef */
#define RV3029_CONTROL_E2P_TURNOVER 0x33 /* XTAL turnover temp (in *C) */
#define RV3029_CONTROL_E2P_TOV_MASK 0x3F /* XTAL turnover temp mask */
/* user ram section */
#define RV3029_RAM_PAGE 0x38
#define RV3029_RAM_SECTION_LEN 8
struct rv3029_data {
struct device *dev;
struct rtc_device *rtc;
struct regmap *regmap;
int irq;
};
static int rv3029_eeprom_busywait(struct rv3029_data *rv3029)
{
unsigned int sr;
int i, ret;
for (i = 100; i > 0; i--) {
ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
if (ret < 0)
break;
if (!(sr & RV3029_STATUS_EEBUSY))
break;
usleep_range(1000, 10000);
}
if (i <= 0) {
dev_err(rv3029->dev, "EEPROM busy wait timeout.\n");
return -ETIMEDOUT;
}
return ret;
}
static int rv3029_eeprom_exit(struct rv3029_data *rv3029)
{
/* Re-enable eeprom refresh */
return regmap_update_bits(rv3029->regmap, RV3029_ONOFF_CTRL,
RV3029_ONOFF_CTRL_EERE,
RV3029_ONOFF_CTRL_EERE);
}
static int rv3029_eeprom_enter(struct rv3029_data *rv3029)
{
unsigned int sr;
int ret;
/* Check whether we are in the allowed voltage range. */
ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
if (ret < 0)
return ret;
if (sr & RV3029_STATUS_VLOW2)
return -ENODEV;
if (sr & RV3029_STATUS_VLOW1) {
/* We clear the bits and retry once just in case
* we had a brown out in early startup.
*/
ret = regmap_update_bits(rv3029->regmap, RV3029_STATUS,
RV3029_STATUS_VLOW1, 0);
if (ret < 0)
return ret;
usleep_range(1000, 10000);
ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
if (ret < 0)
return ret;
if (sr & RV3029_STATUS_VLOW1) {
dev_err(rv3029->dev,
"Supply voltage is too low to safely access the EEPROM.\n");
return -ENODEV;
}
}
/* Disable eeprom refresh. */
ret = regmap_update_bits(rv3029->regmap, RV3029_ONOFF_CTRL,
RV3029_ONOFF_CTRL_EERE, 0);
if (ret < 0)
return ret;
/* Wait for any previous eeprom accesses to finish. */
ret = rv3029_eeprom_busywait(rv3029);
if (ret < 0)
rv3029_eeprom_exit(rv3029);
return ret;
}
static int rv3029_eeprom_read(struct rv3029_data *rv3029, u8 reg,
u8 buf[], size_t len)
{
int ret, err;
err = rv3029_eeprom_enter(rv3029);
if (err < 0)
return err;
ret = regmap_bulk_read(rv3029->regmap, reg, buf, len);
err = rv3029_eeprom_exit(rv3029);
if (err < 0)
return err;
return ret;
}
static int rv3029_eeprom_write(struct rv3029_data *rv3029, u8 reg,
u8 const buf[], size_t len)
{
unsigned int tmp;
int ret, err;
size_t i;
err = rv3029_eeprom_enter(rv3029);
if (err < 0)
return err;
for (i = 0; i < len; i++, reg++) {
ret = regmap_read(rv3029->regmap, reg, &tmp);
if (ret < 0)
break;
if (tmp != buf[i]) {
tmp = buf[i];
ret = regmap_write(rv3029->regmap, reg, tmp);
if (ret < 0)
break;
}
ret = rv3029_eeprom_busywait(rv3029);
if (ret < 0)
break;
}
err = rv3029_eeprom_exit(rv3029);
if (err < 0)
return err;
return ret;
}
static int rv3029_eeprom_update_bits(struct rv3029_data *rv3029,
u8 reg, u8 mask, u8 set)
{
u8 buf;
int ret;
ret = rv3029_eeprom_read(rv3029, reg, &buf, 1);
if (ret < 0)
return ret;
buf &= ~mask;
buf |= set & mask;
ret = rv3029_eeprom_write(rv3029, reg, &buf, 1);
if (ret < 0)
return ret;
return 0;
}
static irqreturn_t rv3029_handle_irq(int irq, void *dev_id)
{
struct device *dev = dev_id;
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
unsigned int flags, controls;
unsigned long events = 0;
int ret;
rtc_lock(rv3029->rtc);
ret = regmap_read(rv3029->regmap, RV3029_IRQ_CTRL, &controls);
if (ret) {
dev_warn(dev, "Read IRQ Control Register error %d\n", ret);
rtc_unlock(rv3029->rtc);
return IRQ_NONE;
}
ret = regmap_read(rv3029->regmap, RV3029_IRQ_FLAGS, &flags);
if (ret) {
dev_warn(dev, "Read IRQ Flags Register error %d\n", ret);
rtc_unlock(rv3029->rtc);
return IRQ_NONE;
}
if (flags & RV3029_IRQ_FLAGS_AF) {
flags &= ~RV3029_IRQ_FLAGS_AF;
controls &= ~RV3029_IRQ_CTRL_AIE;
events |= RTC_AF;
}
if (events) {
rtc_update_irq(rv3029->rtc, 1, events);
regmap_write(rv3029->regmap, RV3029_IRQ_FLAGS, flags);
regmap_write(rv3029->regmap, RV3029_IRQ_CTRL, controls);
}
rtc_unlock(rv3029->rtc);
return IRQ_HANDLED;
}
static int rv3029_read_time(struct device *dev, struct rtc_time *tm)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
unsigned int sr;
int ret;
u8 regs[RV3029_WATCH_SECTION_LEN] = { 0, };
ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
if (ret < 0)
return ret;
if (sr & (RV3029_STATUS_VLOW2 | RV3029_STATUS_PON))
return -EINVAL;
ret = regmap_bulk_read(rv3029->regmap, RV3029_W_SEC, regs,
RV3029_WATCH_SECTION_LEN);
if (ret < 0)
return ret;
tm->tm_sec = bcd2bin(regs[RV3029_W_SEC - RV3029_W_SEC]);
tm->tm_min = bcd2bin(regs[RV3029_W_MINUTES - RV3029_W_SEC]);
/* HR field has a more complex interpretation */
{
const u8 _hr = regs[RV3029_W_HOURS - RV3029_W_SEC];
if (_hr & RV3029_REG_HR_12_24) {
/* 12h format */
tm->tm_hour = bcd2bin(_hr & 0x1f);
if (_hr & RV3029_REG_HR_PM) /* PM flag set */
tm->tm_hour += 12;
} else /* 24h format */
tm->tm_hour = bcd2bin(_hr & 0x3f);
}
tm->tm_mday = bcd2bin(regs[RV3029_W_DATE - RV3029_W_SEC]);
tm->tm_mon = bcd2bin(regs[RV3029_W_MONTHS - RV3029_W_SEC]) - 1;
tm->tm_year = bcd2bin(regs[RV3029_W_YEARS - RV3029_W_SEC]) + 100;
tm->tm_wday = bcd2bin(regs[RV3029_W_DAYS - RV3029_W_SEC]) - 1;
return 0;
}
static int rv3029_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
struct rtc_time *const tm = &alarm->time;
unsigned int controls, flags;
int ret;
u8 regs[8];
ret = regmap_bulk_read(rv3029->regmap, RV3029_A_SC, regs,
RV3029_ALARM_SECTION_LEN);
if (ret < 0)
return ret;
ret = regmap_read(rv3029->regmap, RV3029_IRQ_CTRL, &controls);
if (ret)
return ret;
ret = regmap_read(rv3029->regmap, RV3029_IRQ_FLAGS, &flags);
if (ret < 0)
return ret;
tm->tm_sec = bcd2bin(regs[RV3029_A_SC - RV3029_A_SC] & 0x7f);
tm->tm_min = bcd2bin(regs[RV3029_A_MN - RV3029_A_SC] & 0x7f);
tm->tm_hour = bcd2bin(regs[RV3029_A_HR - RV3029_A_SC] & 0x3f);
tm->tm_mday = bcd2bin(regs[RV3029_A_DT - RV3029_A_SC] & 0x3f);
tm->tm_mon = bcd2bin(regs[RV3029_A_MO - RV3029_A_SC] & 0x1f) - 1;
tm->tm_year = bcd2bin(regs[RV3029_A_YR - RV3029_A_SC] & 0x7f) + 100;
tm->tm_wday = bcd2bin(regs[RV3029_A_DW - RV3029_A_SC] & 0x07) - 1;
alarm->enabled = !!(controls & RV3029_IRQ_CTRL_AIE);
alarm->pending = (flags & RV3029_IRQ_FLAGS_AF) && alarm->enabled;
return 0;
}
static int rv3029_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
return regmap_update_bits(rv3029->regmap, RV3029_IRQ_CTRL,
RV3029_IRQ_CTRL_AIE,
enable ? RV3029_IRQ_CTRL_AIE : 0);
}
static int rv3029_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
struct rtc_time *const tm = &alarm->time;
int ret;
u8 regs[8];
/* Activate all the alarms with AE_x bit */
regs[RV3029_A_SC - RV3029_A_SC] = bin2bcd(tm->tm_sec) | RV3029_A_AE_X;
regs[RV3029_A_MN - RV3029_A_SC] = bin2bcd(tm->tm_min) | RV3029_A_AE_X;
regs[RV3029_A_HR - RV3029_A_SC] = (bin2bcd(tm->tm_hour) & 0x3f)
| RV3029_A_AE_X;
regs[RV3029_A_DT - RV3029_A_SC] = (bin2bcd(tm->tm_mday) & 0x3f)
| RV3029_A_AE_X;
regs[RV3029_A_MO - RV3029_A_SC] = (bin2bcd(tm->tm_mon + 1) & 0x1f)
| RV3029_A_AE_X;
regs[RV3029_A_DW - RV3029_A_SC] = (bin2bcd(tm->tm_wday + 1) & 0x7)
| RV3029_A_AE_X;
regs[RV3029_A_YR - RV3029_A_SC] = (bin2bcd(tm->tm_year - 100))
| RV3029_A_AE_X;
/* Write the alarm */
ret = regmap_bulk_write(rv3029->regmap, RV3029_A_SC, regs,
RV3029_ALARM_SECTION_LEN);
if (ret < 0)
return ret;
return rv3029_alarm_irq_enable(dev, alarm->enabled);
}
static int rv3029_set_time(struct device *dev, struct rtc_time *tm)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
u8 regs[8];
int ret;
regs[RV3029_W_SEC - RV3029_W_SEC] = bin2bcd(tm->tm_sec);
regs[RV3029_W_MINUTES - RV3029_W_SEC] = bin2bcd(tm->tm_min);
regs[RV3029_W_HOURS - RV3029_W_SEC] = bin2bcd(tm->tm_hour);
regs[RV3029_W_DATE - RV3029_W_SEC] = bin2bcd(tm->tm_mday);
regs[RV3029_W_MONTHS - RV3029_W_SEC] = bin2bcd(tm->tm_mon + 1);
regs[RV3029_W_DAYS - RV3029_W_SEC] = bin2bcd(tm->tm_wday + 1) & 0x7;
regs[RV3029_W_YEARS - RV3029_W_SEC] = bin2bcd(tm->tm_year - 100);
ret = regmap_bulk_write(rv3029->regmap, RV3029_W_SEC, regs,
RV3029_WATCH_SECTION_LEN);
if (ret < 0)
return ret;
/* clear PON and VLOW2 bits */
return regmap_update_bits(rv3029->regmap, RV3029_STATUS,
RV3029_STATUS_PON | RV3029_STATUS_VLOW2, 0);
}
static int rv3029_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
unsigned long vl = 0;
int sr, ret = 0;
switch (cmd) {
case RTC_VL_READ:
ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
if (ret < 0)
return ret;
if (sr & RV3029_STATUS_VLOW1)
vl = RTC_VL_ACCURACY_LOW;
if (sr & (RV3029_STATUS_VLOW2 | RV3029_STATUS_PON))
vl |= RTC_VL_DATA_INVALID;
return put_user(vl, (unsigned int __user *)arg);
case RTC_VL_CLR:
return regmap_update_bits(rv3029->regmap, RV3029_STATUS,
RV3029_STATUS_VLOW1, 0);
default:
return -ENOIOCTLCMD;
}
}
static int rv3029_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return regmap_bulk_write(priv, RV3029_RAM_PAGE + offset, val, bytes);
}
static int rv3029_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return regmap_bulk_read(priv, RV3029_RAM_PAGE + offset, val, bytes);
}
static const struct rv3029_trickle_tab_elem {
u32 r; /* resistance in ohms */
u8 conf; /* trickle config bits */
} rv3029_trickle_tab[] = {
{
.r = 1076,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K |
RV3029_TRICKLE_20K | RV3029_TRICKLE_80K,
}, {
.r = 1091,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K |
RV3029_TRICKLE_20K,
}, {
.r = 1137,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K |
RV3029_TRICKLE_80K,
}, {
.r = 1154,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K,
}, {
.r = 1371,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_20K |
RV3029_TRICKLE_80K,
}, {
.r = 1395,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_20K,
}, {
.r = 1472,
.conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_80K,
}, {
.r = 1500,
.conf = RV3029_TRICKLE_1K,
}, {
.r = 3810,
.conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_20K |
RV3029_TRICKLE_80K,
}, {
.r = 4000,
.conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_20K,
}, {
.r = 4706,
.conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_80K,
}, {
.r = 5000,
.conf = RV3029_TRICKLE_5K,
}, {
.r = 16000,
.conf = RV3029_TRICKLE_20K | RV3029_TRICKLE_80K,
}, {
.r = 20000,
.conf = RV3029_TRICKLE_20K,
}, {
.r = 80000,
.conf = RV3029_TRICKLE_80K,
},
};
static void rv3029_trickle_config(struct device *dev)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
struct device_node *of_node = dev->of_node;
const struct rv3029_trickle_tab_elem *elem;
int i, err;
u32 ohms;
u8 trickle_set_bits;
if (!of_node)
return;
/* Configure the trickle charger. */
err = of_property_read_u32(of_node, "trickle-resistor-ohms", &ohms);
if (err) {
/* Disable trickle charger. */
trickle_set_bits = 0;
} else {
/* Enable trickle charger. */
for (i = 0; i < ARRAY_SIZE(rv3029_trickle_tab); i++) {
elem = &rv3029_trickle_tab[i];
if (elem->r >= ohms)
break;
}
trickle_set_bits = elem->conf;
dev_info(dev,
"Trickle charger enabled at %d ohms resistance.\n",
elem->r);
}
err = rv3029_eeprom_update_bits(rv3029, RV3029_CONTROL_E2P_EECTRL,
RV3029_TRICKLE_MASK,
trickle_set_bits);
if (err < 0)
dev_err(dev, "Failed to update trickle charger config\n");
}
#ifdef CONFIG_RTC_DRV_RV3029_HWMON
static int rv3029_read_temp(struct rv3029_data *rv3029, int *temp_mC)
{
unsigned int temp;
int ret;
ret = regmap_read(rv3029->regmap, RV3029_TEMP_PAGE, &temp);
if (ret < 0)
return ret;
*temp_mC = ((int)temp - 60) * 1000;
return 0;
}
static ssize_t rv3029_hwmon_show_temp(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
int ret, temp_mC;
ret = rv3029_read_temp(rv3029, &temp_mC);
if (ret < 0)
return ret;
return sprintf(buf, "%d\n", temp_mC);
}
static ssize_t rv3029_hwmon_set_update_interval(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t count)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
unsigned int th_set_bits = 0;
unsigned long interval_ms;
int ret;
ret = kstrtoul(buf, 10, &interval_ms);
if (ret < 0)
return ret;
if (interval_ms != 0) {
th_set_bits |= RV3029_EECTRL_THE;
if (interval_ms >= 16000)
th_set_bits |= RV3029_EECTRL_THP;
}
ret = rv3029_eeprom_update_bits(rv3029, RV3029_CONTROL_E2P_EECTRL,
RV3029_EECTRL_THE | RV3029_EECTRL_THP,
th_set_bits);
if (ret < 0)
return ret;
return count;
}
static ssize_t rv3029_hwmon_show_update_interval(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
int ret, interval_ms;
u8 eectrl;
ret = rv3029_eeprom_read(rv3029, RV3029_CONTROL_E2P_EECTRL,
&eectrl, 1);
if (ret < 0)
return ret;
if (eectrl & RV3029_EECTRL_THE) {
if (eectrl & RV3029_EECTRL_THP)
interval_ms = 16000;
else
interval_ms = 1000;
} else {
interval_ms = 0;
}
return sprintf(buf, "%d\n", interval_ms);
}
static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, rv3029_hwmon_show_temp,
NULL, 0);
static SENSOR_DEVICE_ATTR(update_interval, S_IWUSR | S_IRUGO,
rv3029_hwmon_show_update_interval,
rv3029_hwmon_set_update_interval, 0);
static struct attribute *rv3029_hwmon_attrs[] = {
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_update_interval.dev_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(rv3029_hwmon);
static void rv3029_hwmon_register(struct device *dev, const char *name)
{
struct rv3029_data *rv3029 = dev_get_drvdata(dev);
struct device *hwmon_dev;
hwmon_dev = devm_hwmon_device_register_with_groups(dev, name, rv3029,
rv3029_hwmon_groups);
if (IS_ERR(hwmon_dev)) {
dev_warn(dev, "unable to register hwmon device %ld\n",
PTR_ERR(hwmon_dev));
}
}
#else /* CONFIG_RTC_DRV_RV3029_HWMON */
static void rv3029_hwmon_register(struct device *dev, const char *name)
{
}
#endif /* CONFIG_RTC_DRV_RV3029_HWMON */
static const struct rtc_class_ops rv3029_rtc_ops = {
.read_time = rv3029_read_time,
.set_time = rv3029_set_time,
.ioctl = rv3029_ioctl,
.read_alarm = rv3029_read_alarm,
.set_alarm = rv3029_set_alarm,
.alarm_irq_enable = rv3029_alarm_irq_enable,
};
static int rv3029_probe(struct device *dev, struct regmap *regmap, int irq,
const char *name)
{
struct rv3029_data *rv3029;
struct nvmem_config nvmem_cfg = {
.name = "rv3029_nvram",
.word_size = 1,
.stride = 1,
.size = RV3029_RAM_SECTION_LEN,
.type = NVMEM_TYPE_BATTERY_BACKED,
.reg_read = rv3029_nvram_read,
.reg_write = rv3029_nvram_write,
};
int rc = 0;
rv3029 = devm_kzalloc(dev, sizeof(*rv3029), GFP_KERNEL);
if (!rv3029)
return -ENOMEM;
rv3029->regmap = regmap;
rv3029->irq = irq;
rv3029->dev = dev;
dev_set_drvdata(dev, rv3029);
rv3029_trickle_config(dev);
rv3029_hwmon_register(dev, name);
rv3029->rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(rv3029->rtc))
return PTR_ERR(rv3029->rtc);
if (rv3029->irq > 0) {
unsigned long irqflags = IRQF_TRIGGER_LOW;
if (dev_fwnode(dev))
irqflags = 0;
rc = devm_request_threaded_irq(dev, rv3029->irq,
NULL, rv3029_handle_irq,
irqflags | IRQF_ONESHOT,
"rv3029", dev);
if (rc) {
dev_warn(dev, "unable to request IRQ, alarms disabled\n");
rv3029->irq = 0;
}
}
if (!rv3029->irq)
clear_bit(RTC_FEATURE_ALARM, rv3029->rtc->features);
rv3029->rtc->ops = &rv3029_rtc_ops;
rv3029->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rv3029->rtc->range_max = RTC_TIMESTAMP_END_2079;
rc = devm_rtc_register_device(rv3029->rtc);
if (rc)
return rc;
nvmem_cfg.priv = rv3029->regmap;
devm_rtc_nvmem_register(rv3029->rtc, &nvmem_cfg);
return 0;
}
static const struct regmap_range rv3029_holes_range[] = {
regmap_reg_range(0x05, 0x07),
regmap_reg_range(0x0f, 0x0f),
regmap_reg_range(0x17, 0x17),
regmap_reg_range(0x1a, 0x1f),
regmap_reg_range(0x21, 0x27),
regmap_reg_range(0x34, 0x37),
};
static const struct regmap_access_table rv3029_regs = {
.no_ranges = rv3029_holes_range,
.n_no_ranges = ARRAY_SIZE(rv3029_holes_range),
};
static const struct regmap_config config = {
.reg_bits = 8,
.val_bits = 8,
.rd_table = &rv3029_regs,
.wr_table = &rv3029_regs,
.max_register = 0x3f,
};
#if IS_ENABLED(CONFIG_I2C)
static int rv3029_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK |
I2C_FUNC_SMBUS_BYTE)) {
dev_err(&client->dev, "Adapter does not support SMBUS_I2C_BLOCK or SMBUS_I2C_BYTE\n");
return -ENODEV;
}
regmap = devm_regmap_init_i2c(client, &config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rv3029_probe(&client->dev, regmap, client->irq, client->name);
}
static const struct i2c_device_id rv3029_id[] = {
{ "rv3029", 0 },
{ "rv3029c2", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rv3029_id);
static const __maybe_unused struct of_device_id rv3029_of_match[] = {
{ .compatible = "microcrystal,rv3029" },
{ }
};
MODULE_DEVICE_TABLE(of, rv3029_of_match);
static struct i2c_driver rv3029_driver = {
.driver = {
.name = "rv3029",
.of_match_table = of_match_ptr(rv3029_of_match),
},
.probe = rv3029_i2c_probe,
.id_table = rv3029_id,
};
static int __init rv3029_register_driver(void)
{
return i2c_add_driver(&rv3029_driver);
}
static void rv3029_unregister_driver(void)
{
i2c_del_driver(&rv3029_driver);
}
#else
static int __init rv3029_register_driver(void)
{
return 0;
}
static void rv3029_unregister_driver(void)
{
}
#endif
#if IS_ENABLED(CONFIG_SPI_MASTER)
static int rv3049_probe(struct spi_device *spi)
{
struct regmap *regmap;
regmap = devm_regmap_init_spi(spi, &config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rv3029_probe(&spi->dev, regmap, spi->irq, "rv3049");
}
static struct spi_driver rv3049_driver = {
.driver = {
.name = "rv3049",
},
.probe = rv3049_probe,
};
static int __init rv3049_register_driver(void)
{
return spi_register_driver(&rv3049_driver);
}
static void __exit rv3049_unregister_driver(void)
{
spi_unregister_driver(&rv3049_driver);
}
#else
static int __init rv3049_register_driver(void)
{
return 0;
}
static void __exit rv3049_unregister_driver(void)
{
}
#endif
static int __init rv30x9_init(void)
{
int ret;
ret = rv3029_register_driver();
if (ret)
return ret;
ret = rv3049_register_driver();
if (ret)
rv3029_unregister_driver();
return ret;
}
module_init(rv30x9_init)
static void __exit rv30x9_exit(void)
{
rv3049_unregister_driver();
rv3029_unregister_driver();
}
module_exit(rv30x9_exit)
MODULE_AUTHOR("Gregory Hermant <[email protected]>");
MODULE_AUTHOR("Michael Buesch <[email protected]>");
MODULE_DESCRIPTION("Micro Crystal RV3029/RV3049 RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rv3049");
| linux-master | drivers/rtc/rtc-rv3029c2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* PS3 RTC Driver
*
* Copyright 2009 Sony Corporation
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <asm/lv1call.h>
#include <asm/ps3.h>
static u64 read_rtc(void)
{
int result;
u64 rtc_val;
u64 tb_val;
result = lv1_get_rtc(&rtc_val, &tb_val);
BUG_ON(result);
return rtc_val;
}
static int ps3_get_time(struct device *dev, struct rtc_time *tm)
{
rtc_time64_to_tm(read_rtc() + ps3_os_area_get_rtc_diff(), tm);
return 0;
}
static int ps3_set_time(struct device *dev, struct rtc_time *tm)
{
ps3_os_area_set_rtc_diff(rtc_tm_to_time64(tm) - read_rtc());
return 0;
}
static const struct rtc_class_ops ps3_rtc_ops = {
.read_time = ps3_get_time,
.set_time = ps3_set_time,
};
static int __init ps3_rtc_probe(struct platform_device *dev)
{
struct rtc_device *rtc;
rtc = devm_rtc_allocate_device(&dev->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &ps3_rtc_ops;
rtc->range_max = U64_MAX;
platform_set_drvdata(dev, rtc);
return devm_rtc_register_device(rtc);
}
static struct platform_driver ps3_rtc_driver = {
.driver = {
.name = "rtc-ps3",
},
};
module_platform_driver_probe(ps3_rtc_driver, ps3_rtc_probe);
MODULE_AUTHOR("Sony Corporation");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ps3 RTC driver");
MODULE_ALIAS("platform:rtc-ps3");
| linux-master | drivers/rtc/rtc-ps3.c |
// SPDX-License-Identifier: GPL-2.0
// RTC driver for ChromeOS Embedded Controller.
//
// Copyright (C) 2017 Google, Inc.
// Author: Stephen Barber <[email protected]>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#define DRV_NAME "cros-ec-rtc"
#define SECS_PER_DAY (24 * 60 * 60)
/**
* struct cros_ec_rtc - Driver data for EC RTC
*
* @cros_ec: Pointer to EC device
* @rtc: Pointer to RTC device
* @notifier: Notifier info for responding to EC events
* @saved_alarm: Alarm to restore when interrupts are reenabled
*/
struct cros_ec_rtc {
struct cros_ec_device *cros_ec;
struct rtc_device *rtc;
struct notifier_block notifier;
u32 saved_alarm;
};
static int cros_ec_rtc_get(struct cros_ec_device *cros_ec, u32 command,
u32 *response)
{
int ret;
struct {
struct cros_ec_command msg;
struct ec_response_rtc data;
} __packed msg;
memset(&msg, 0, sizeof(msg));
msg.msg.command = command;
msg.msg.insize = sizeof(msg.data);
ret = cros_ec_cmd_xfer_status(cros_ec, &msg.msg);
if (ret < 0)
return ret;
*response = msg.data.time;
return 0;
}
static int cros_ec_rtc_set(struct cros_ec_device *cros_ec, u32 command,
u32 param)
{
int ret;
struct {
struct cros_ec_command msg;
struct ec_response_rtc data;
} __packed msg;
memset(&msg, 0, sizeof(msg));
msg.msg.command = command;
msg.msg.outsize = sizeof(msg.data);
msg.data.time = param;
ret = cros_ec_cmd_xfer_status(cros_ec, &msg.msg);
if (ret < 0)
return ret;
return 0;
}
/* Read the current time from the EC. */
static int cros_ec_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(dev);
struct cros_ec_device *cros_ec = cros_ec_rtc->cros_ec;
int ret;
u32 time;
ret = cros_ec_rtc_get(cros_ec, EC_CMD_RTC_GET_VALUE, &time);
if (ret) {
dev_err(dev, "error getting time: %d\n", ret);
return ret;
}
rtc_time64_to_tm(time, tm);
return 0;
}
/* Set the current EC time. */
static int cros_ec_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(dev);
struct cros_ec_device *cros_ec = cros_ec_rtc->cros_ec;
int ret;
time64_t time = rtc_tm_to_time64(tm);
ret = cros_ec_rtc_set(cros_ec, EC_CMD_RTC_SET_VALUE, (u32)time);
if (ret < 0) {
dev_err(dev, "error setting time: %d\n", ret);
return ret;
}
return 0;
}
/* Read alarm time from RTC. */
static int cros_ec_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(dev);
struct cros_ec_device *cros_ec = cros_ec_rtc->cros_ec;
int ret;
u32 current_time, alarm_offset;
/*
* The EC host command for getting the alarm is relative (i.e. 5
* seconds from now) whereas rtc_wkalrm is absolute. Get the current
* RTC time first so we can calculate the relative time.
*/
ret = cros_ec_rtc_get(cros_ec, EC_CMD_RTC_GET_VALUE, ¤t_time);
if (ret < 0) {
dev_err(dev, "error getting time: %d\n", ret);
return ret;
}
ret = cros_ec_rtc_get(cros_ec, EC_CMD_RTC_GET_ALARM, &alarm_offset);
if (ret < 0) {
dev_err(dev, "error getting alarm: %d\n", ret);
return ret;
}
rtc_time64_to_tm(current_time + alarm_offset, &alrm->time);
return 0;
}
/* Set the EC's RTC alarm. */
static int cros_ec_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(dev);
struct cros_ec_device *cros_ec = cros_ec_rtc->cros_ec;
int ret;
time64_t alarm_time;
u32 current_time, alarm_offset;
/*
* The EC host command for setting the alarm is relative
* (i.e. 5 seconds from now) whereas rtc_wkalrm is absolute.
* Get the current RTC time first so we can calculate the
* relative time.
*/
ret = cros_ec_rtc_get(cros_ec, EC_CMD_RTC_GET_VALUE, ¤t_time);
if (ret < 0) {
dev_err(dev, "error getting time: %d\n", ret);
return ret;
}
alarm_time = rtc_tm_to_time64(&alrm->time);
if (alarm_time < 0 || alarm_time > U32_MAX)
return -EINVAL;
if (!alrm->enabled) {
/*
* If the alarm is being disabled, send an alarm
* clear command.
*/
alarm_offset = EC_RTC_ALARM_CLEAR;
cros_ec_rtc->saved_alarm = (u32)alarm_time;
} else {
/* Don't set an alarm in the past. */
if ((u32)alarm_time <= current_time)
return -ETIME;
alarm_offset = (u32)alarm_time - current_time;
}
ret = cros_ec_rtc_set(cros_ec, EC_CMD_RTC_SET_ALARM, alarm_offset);
if (ret < 0) {
dev_err(dev, "error setting alarm in %u seconds: %d\n",
alarm_offset, ret);
/*
* The EC code returns -EINVAL if the alarm time is too
* far in the future. Convert it to the expected error code.
*/
if (ret == -EINVAL)
ret = -ERANGE;
return ret;
}
return 0;
}
static int cros_ec_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(dev);
struct cros_ec_device *cros_ec = cros_ec_rtc->cros_ec;
int ret;
u32 current_time, alarm_offset, alarm_value;
ret = cros_ec_rtc_get(cros_ec, EC_CMD_RTC_GET_VALUE, ¤t_time);
if (ret < 0) {
dev_err(dev, "error getting time: %d\n", ret);
return ret;
}
if (enabled) {
/* Restore saved alarm if it's still in the future. */
if (cros_ec_rtc->saved_alarm < current_time)
alarm_offset = EC_RTC_ALARM_CLEAR;
else
alarm_offset = cros_ec_rtc->saved_alarm - current_time;
ret = cros_ec_rtc_set(cros_ec, EC_CMD_RTC_SET_ALARM,
alarm_offset);
if (ret < 0) {
dev_err(dev, "error restoring alarm: %d\n", ret);
return ret;
}
} else {
/* Disable alarm, saving the old alarm value. */
ret = cros_ec_rtc_get(cros_ec, EC_CMD_RTC_GET_ALARM,
&alarm_offset);
if (ret < 0) {
dev_err(dev, "error saving alarm: %d\n", ret);
return ret;
}
alarm_value = current_time + alarm_offset;
/*
* If the current EC alarm is already past, we don't want
* to set an alarm when we go through the alarm irq enable
* path.
*/
if (alarm_value < current_time)
cros_ec_rtc->saved_alarm = EC_RTC_ALARM_CLEAR;
else
cros_ec_rtc->saved_alarm = alarm_value;
alarm_offset = EC_RTC_ALARM_CLEAR;
ret = cros_ec_rtc_set(cros_ec, EC_CMD_RTC_SET_ALARM,
alarm_offset);
if (ret < 0) {
dev_err(dev, "error disabling alarm: %d\n", ret);
return ret;
}
}
return 0;
}
static int cros_ec_rtc_event(struct notifier_block *nb,
unsigned long queued_during_suspend,
void *_notify)
{
struct cros_ec_rtc *cros_ec_rtc;
struct rtc_device *rtc;
struct cros_ec_device *cros_ec;
u32 host_event;
cros_ec_rtc = container_of(nb, struct cros_ec_rtc, notifier);
rtc = cros_ec_rtc->rtc;
cros_ec = cros_ec_rtc->cros_ec;
host_event = cros_ec_get_host_event(cros_ec);
if (host_event & EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)) {
rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
return NOTIFY_OK;
} else {
return NOTIFY_DONE;
}
}
static const struct rtc_class_ops cros_ec_rtc_ops = {
.read_time = cros_ec_rtc_read_time,
.set_time = cros_ec_rtc_set_time,
.read_alarm = cros_ec_rtc_read_alarm,
.set_alarm = cros_ec_rtc_set_alarm,
.alarm_irq_enable = cros_ec_rtc_alarm_irq_enable,
};
#ifdef CONFIG_PM_SLEEP
static int cros_ec_rtc_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(&pdev->dev);
if (device_may_wakeup(dev))
return enable_irq_wake(cros_ec_rtc->cros_ec->irq);
return 0;
}
static int cros_ec_rtc_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct cros_ec_rtc *cros_ec_rtc = dev_get_drvdata(&pdev->dev);
if (device_may_wakeup(dev))
return disable_irq_wake(cros_ec_rtc->cros_ec->irq);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(cros_ec_rtc_pm_ops, cros_ec_rtc_suspend,
cros_ec_rtc_resume);
static int cros_ec_rtc_probe(struct platform_device *pdev)
{
struct cros_ec_dev *ec_dev = dev_get_drvdata(pdev->dev.parent);
struct cros_ec_device *cros_ec = ec_dev->ec_dev;
struct cros_ec_rtc *cros_ec_rtc;
struct rtc_time tm;
int ret;
cros_ec_rtc = devm_kzalloc(&pdev->dev, sizeof(*cros_ec_rtc),
GFP_KERNEL);
if (!cros_ec_rtc)
return -ENOMEM;
platform_set_drvdata(pdev, cros_ec_rtc);
cros_ec_rtc->cros_ec = cros_ec;
/* Get initial time */
ret = cros_ec_rtc_read_time(&pdev->dev, &tm);
if (ret) {
dev_err(&pdev->dev, "failed to read RTC time\n");
return ret;
}
ret = device_init_wakeup(&pdev->dev, 1);
if (ret) {
dev_err(&pdev->dev, "failed to initialize wakeup\n");
return ret;
}
cros_ec_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(cros_ec_rtc->rtc))
return PTR_ERR(cros_ec_rtc->rtc);
cros_ec_rtc->rtc->ops = &cros_ec_rtc_ops;
cros_ec_rtc->rtc->range_max = U32_MAX;
/*
* The RTC on some older Chromebooks can only handle alarms less than
* 24 hours in the future. The only way to find out is to try to set an
* alarm further in the future. If that fails, assume that the RTC
* connected to the EC can only handle less than 24 hours of alarm
* window.
*/
ret = cros_ec_rtc_set(cros_ec, EC_CMD_RTC_SET_ALARM, SECS_PER_DAY * 2);
if (ret == -EINVAL)
cros_ec_rtc->rtc->alarm_offset_max = SECS_PER_DAY - 1;
(void)cros_ec_rtc_set(cros_ec, EC_CMD_RTC_SET_ALARM,
EC_RTC_ALARM_CLEAR);
ret = devm_rtc_register_device(cros_ec_rtc->rtc);
if (ret)
return ret;
/* Get RTC events from the EC. */
cros_ec_rtc->notifier.notifier_call = cros_ec_rtc_event;
ret = blocking_notifier_chain_register(&cros_ec->event_notifier,
&cros_ec_rtc->notifier);
if (ret) {
dev_err(&pdev->dev, "failed to register notifier\n");
return ret;
}
return 0;
}
static void cros_ec_rtc_remove(struct platform_device *pdev)
{
struct cros_ec_rtc *cros_ec_rtc = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
int ret;
ret = blocking_notifier_chain_unregister(
&cros_ec_rtc->cros_ec->event_notifier,
&cros_ec_rtc->notifier);
if (ret)
dev_err(dev, "failed to unregister notifier\n");
}
static struct platform_driver cros_ec_rtc_driver = {
.probe = cros_ec_rtc_probe,
.remove_new = cros_ec_rtc_remove,
.driver = {
.name = DRV_NAME,
.pm = &cros_ec_rtc_pm_ops,
},
};
module_platform_driver(cros_ec_rtc_driver);
MODULE_DESCRIPTION("RTC driver for Chrome OS ECs");
MODULE_AUTHOR("Stephen Barber <[email protected]>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
| linux-master | drivers/rtc/rtc-cros-ec.c |
// SPDX-License-Identifier: GPL-2.0
/*
* An I2C driver for the PCF85063 RTC
* Copyright 2014 Rose Technology
*
* Author: Søren Andersen <[email protected]>
* Maintainers: http://www.nslu2-linux.org/
*
* Copyright (C) 2019 Micro Crystal AG
* Author: Alexandre Belloni <[email protected]>
*/
#include <linux/clk-provider.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
/*
* Information for this driver was pulled from the following datasheets.
*
* https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
* https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
*
* PCF85063A -- Rev. 7 — 30 March 2018
* PCF85063TP -- Rev. 4 — 6 May 2015
*
* https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
* RV8263 -- Rev. 1.0 — January 2019
*/
#define PCF85063_REG_CTRL1 0x00 /* status */
#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
#define PCF85063_REG_CTRL1_STOP BIT(5)
#define PCF85063_REG_CTRL1_EXT_TEST BIT(7)
#define PCF85063_REG_CTRL2 0x01
#define PCF85063_CTRL2_AF BIT(6)
#define PCF85063_CTRL2_AIE BIT(7)
#define PCF85063_REG_OFFSET 0x02
#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
#define PCF85063_OFFSET_MODE BIT(7)
#define PCF85063_OFFSET_STEP0 4340
#define PCF85063_OFFSET_STEP1 4069
#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
#define PCF85063_REG_CLKO_F_32768HZ 0x00
#define PCF85063_REG_CLKO_F_OFF 0x07
#define PCF85063_REG_RAM 0x03
#define PCF85063_REG_SC 0x04 /* datetime */
#define PCF85063_REG_SC_OS 0x80
#define PCF85063_REG_ALM_S 0x0b
#define PCF85063_AEN BIT(7)
struct pcf85063_config {
struct regmap_config regmap;
unsigned has_alarms:1;
unsigned force_cap_7000:1;
};
struct pcf85063 {
struct rtc_device *rtc;
struct regmap *regmap;
#ifdef CONFIG_COMMON_CLK
struct clk_hw clkout_hw;
#endif
};
static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
int rc;
u8 regs[7];
/*
* while reading, the time/date registers are blocked and not updated
* anymore until the access is finished. To not lose a second
* event, the access must be finished within one second. So, read all
* time/date registers in one turn.
*/
rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
sizeof(regs));
if (rc)
return rc;
/* if the clock has lost its power it makes no sense to use its time */
if (regs[0] & PCF85063_REG_SC_OS) {
dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
return -EINVAL;
}
tm->tm_sec = bcd2bin(regs[0] & 0x7F);
tm->tm_min = bcd2bin(regs[1] & 0x7F);
tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
tm->tm_mday = bcd2bin(regs[3] & 0x3F);
tm->tm_wday = regs[4] & 0x07;
tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
tm->tm_year = bcd2bin(regs[6]);
tm->tm_year += 100;
return 0;
}
static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
int rc;
u8 regs[7];
/*
* to accurately set the time, reset the divider chain and keep it in
* reset state until all time/date registers are written
*/
rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
PCF85063_REG_CTRL1_EXT_TEST |
PCF85063_REG_CTRL1_STOP,
PCF85063_REG_CTRL1_STOP);
if (rc)
return rc;
/* hours, minutes and seconds */
regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
regs[1] = bin2bcd(tm->tm_min);
regs[2] = bin2bcd(tm->tm_hour);
/* Day of month, 1 - 31 */
regs[3] = bin2bcd(tm->tm_mday);
/* Day, 0 - 6 */
regs[4] = tm->tm_wday & 0x07;
/* month, 1 - 12 */
regs[5] = bin2bcd(tm->tm_mon + 1);
/* year and century */
regs[6] = bin2bcd(tm->tm_year - 100);
/* write all registers at once */
rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
regs, sizeof(regs));
if (rc)
return rc;
/*
* Write the control register as a separate action since the size of
* the register space is different between the PCF85063TP and
* PCF85063A devices. The rollover point can not be used.
*/
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
PCF85063_REG_CTRL1_STOP, 0);
}
static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
u8 buf[4];
unsigned int val;
int ret;
ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
buf, sizeof(buf));
if (ret)
return ret;
alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
if (ret)
return ret;
alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
return 0;
}
static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
u8 buf[5];
int ret;
buf[0] = bin2bcd(alrm->time.tm_sec);
buf[1] = bin2bcd(alrm->time.tm_min);
buf[2] = bin2bcd(alrm->time.tm_hour);
buf[3] = bin2bcd(alrm->time.tm_mday);
buf[4] = PCF85063_AEN; /* Do not match on week day */
ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
if (ret)
return ret;
ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
buf, sizeof(buf));
if (ret)
return ret;
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
}
static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_CTRL2_AIE,
enabled ? PCF85063_CTRL2_AIE : 0);
}
static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
{
struct pcf85063 *pcf85063 = dev_id;
unsigned int val;
int err;
err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
if (err)
return IRQ_NONE;
if (val & PCF85063_CTRL2_AF) {
rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
0);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int pcf85063_read_offset(struct device *dev, long *offset)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
long val;
u32 reg;
int ret;
ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, ®);
if (ret < 0)
return ret;
val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
PCF85063_OFFSET_SIGN_BIT);
if (reg & PCF85063_OFFSET_MODE)
*offset = val * PCF85063_OFFSET_STEP1;
else
*offset = val * PCF85063_OFFSET_STEP0;
return 0;
}
static int pcf85063_set_offset(struct device *dev, long offset)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
s8 mode0, mode1, reg;
unsigned int error0, error1;
if (offset > PCF85063_OFFSET_STEP0 * 63)
return -ERANGE;
if (offset < PCF85063_OFFSET_STEP0 * -64)
return -ERANGE;
mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
if (mode1 > 63 || mode1 < -64 || error0 < error1)
reg = mode0 & ~PCF85063_OFFSET_MODE;
else
reg = mode1 | PCF85063_OFFSET_MODE;
return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
}
static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
unsigned long arg)
{
struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
int status, ret = 0;
switch (cmd) {
case RTC_VL_READ:
ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
if (ret < 0)
return ret;
status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
return put_user(status, (unsigned int __user *)arg);
default:
return -ENOIOCTLCMD;
}
}
static const struct rtc_class_ops pcf85063_rtc_ops = {
.read_time = pcf85063_rtc_read_time,
.set_time = pcf85063_rtc_set_time,
.read_offset = pcf85063_read_offset,
.set_offset = pcf85063_set_offset,
.read_alarm = pcf85063_rtc_read_alarm,
.set_alarm = pcf85063_rtc_set_alarm,
.alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
.ioctl = pcf85063_ioctl,
};
static int pcf85063_nvmem_read(void *priv, unsigned int offset,
void *val, size_t bytes)
{
return regmap_read(priv, PCF85063_REG_RAM, val);
}
static int pcf85063_nvmem_write(void *priv, unsigned int offset,
void *val, size_t bytes)
{
return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
}
static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
const struct device_node *np,
unsigned int force_cap)
{
u32 load = 7000;
u8 reg = 0;
if (force_cap)
load = force_cap;
else
of_property_read_u32(np, "quartz-load-femtofarads", &load);
switch (load) {
default:
dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
load);
fallthrough;
case 7000:
break;
case 12500:
reg = PCF85063_REG_CTRL1_CAP_SEL;
break;
}
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
PCF85063_REG_CTRL1_CAP_SEL, reg);
}
#ifdef CONFIG_COMMON_CLK
/*
* Handling of the clkout
*/
#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
static int clkout_rates[] = {
32768,
16384,
8192,
4096,
2048,
1024,
1,
0
};
static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
unsigned int buf;
int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
if (ret < 0)
return 0;
buf &= PCF85063_REG_CLKO_F_MASK;
return clkout_rates[buf];
}
static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
int i;
for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
if (clkout_rates[i] <= rate)
return clkout_rates[i];
return 0;
}
static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
int i;
for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
if (clkout_rates[i] == rate)
return regmap_update_bits(pcf85063->regmap,
PCF85063_REG_CTRL2,
PCF85063_REG_CLKO_F_MASK, i);
return -EINVAL;
}
static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
{
struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
unsigned int buf;
int ret;
ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
if (ret < 0)
return ret;
buf &= PCF85063_REG_CLKO_F_MASK;
if (enable) {
if (buf == PCF85063_REG_CLKO_F_OFF)
buf = PCF85063_REG_CLKO_F_32768HZ;
else
return 0;
} else {
if (buf != PCF85063_REG_CLKO_F_OFF)
buf = PCF85063_REG_CLKO_F_OFF;
else
return 0;
}
return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
PCF85063_REG_CLKO_F_MASK, buf);
}
static int pcf85063_clkout_prepare(struct clk_hw *hw)
{
return pcf85063_clkout_control(hw, 1);
}
static void pcf85063_clkout_unprepare(struct clk_hw *hw)
{
pcf85063_clkout_control(hw, 0);
}
static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
{
struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
unsigned int buf;
int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
if (ret < 0)
return 0;
return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
}
static const struct clk_ops pcf85063_clkout_ops = {
.prepare = pcf85063_clkout_prepare,
.unprepare = pcf85063_clkout_unprepare,
.is_prepared = pcf85063_clkout_is_prepared,
.recalc_rate = pcf85063_clkout_recalc_rate,
.round_rate = pcf85063_clkout_round_rate,
.set_rate = pcf85063_clkout_set_rate,
};
static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
{
struct clk *clk;
struct clk_init_data init;
struct device_node *node = pcf85063->rtc->dev.parent->of_node;
struct device_node *fixed_clock;
fixed_clock = of_get_child_by_name(node, "clock");
if (fixed_clock) {
/*
* skip registering square wave clock when a fixed
* clock has been registered. The fixed clock is
* registered automatically when being referenced.
*/
of_node_put(fixed_clock);
return NULL;
}
init.name = "pcf85063-clkout";
init.ops = &pcf85063_clkout_ops;
init.flags = 0;
init.parent_names = NULL;
init.num_parents = 0;
pcf85063->clkout_hw.init = &init;
/* optional override of the clockname */
of_property_read_string(node, "clock-output-names", &init.name);
/* register the clock */
clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
return clk;
}
#endif
static const struct pcf85063_config config_pcf85063 = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x0a,
},
};
static const struct pcf85063_config config_pcf85063tp = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x0a,
},
};
static const struct pcf85063_config config_pcf85063a = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x11,
},
.has_alarms = 1,
};
static const struct pcf85063_config config_rv8263 = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x11,
},
.has_alarms = 1,
.force_cap_7000 = 1,
};
static int pcf85063_probe(struct i2c_client *client)
{
struct pcf85063 *pcf85063;
unsigned int tmp;
int err;
const struct pcf85063_config *config;
struct nvmem_config nvmem_cfg = {
.name = "pcf85063_nvram",
.reg_read = pcf85063_nvmem_read,
.reg_write = pcf85063_nvmem_write,
.type = NVMEM_TYPE_BATTERY_BACKED,
.size = 1,
};
dev_dbg(&client->dev, "%s\n", __func__);
pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
GFP_KERNEL);
if (!pcf85063)
return -ENOMEM;
config = i2c_get_match_data(client);
if (!config)
return -ENODEV;
pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
if (IS_ERR(pcf85063->regmap))
return PTR_ERR(pcf85063->regmap);
i2c_set_clientdata(client, pcf85063);
err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
if (err) {
dev_err(&client->dev, "RTC chip is not present\n");
return err;
}
pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(pcf85063->rtc))
return PTR_ERR(pcf85063->rtc);
err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
config->force_cap_7000 ? 7000 : 0);
if (err < 0)
dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
err);
pcf85063->rtc->ops = &pcf85063_rtc_ops;
pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
if (config->has_alarms && client->irq > 0) {
unsigned long irqflags = IRQF_TRIGGER_LOW;
if (dev_fwnode(&client->dev))
irqflags = 0;
err = devm_request_threaded_irq(&client->dev, client->irq,
NULL, pcf85063_rtc_handle_irq,
irqflags | IRQF_ONESHOT,
"pcf85063", pcf85063);
if (err) {
dev_warn(&pcf85063->rtc->dev,
"unable to request IRQ, alarms disabled\n");
} else {
set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
device_init_wakeup(&client->dev, true);
err = dev_pm_set_wake_irq(&client->dev, client->irq);
if (err)
dev_err(&pcf85063->rtc->dev,
"failed to enable irq wake\n");
}
}
nvmem_cfg.priv = pcf85063->regmap;
devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
#ifdef CONFIG_COMMON_CLK
/* register clk in common clk framework */
pcf85063_clkout_register_clk(pcf85063);
#endif
return devm_rtc_register_device(pcf85063->rtc);
}
static const struct i2c_device_id pcf85063_ids[] = {
{ "pca85073a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
{ "pcf85063", .driver_data = (kernel_ulong_t)&config_pcf85063 },
{ "pcf85063tp", .driver_data = (kernel_ulong_t)&config_pcf85063tp },
{ "pcf85063a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
{ "rv8263", .driver_data = (kernel_ulong_t)&config_rv8263 },
{}
};
MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
#ifdef CONFIG_OF
static const struct of_device_id pcf85063_of_match[] = {
{ .compatible = "nxp,pca85073a", .data = &config_pcf85063a },
{ .compatible = "nxp,pcf85063", .data = &config_pcf85063 },
{ .compatible = "nxp,pcf85063tp", .data = &config_pcf85063tp },
{ .compatible = "nxp,pcf85063a", .data = &config_pcf85063a },
{ .compatible = "microcrystal,rv8263", .data = &config_rv8263 },
{}
};
MODULE_DEVICE_TABLE(of, pcf85063_of_match);
#endif
static struct i2c_driver pcf85063_driver = {
.driver = {
.name = "rtc-pcf85063",
.of_match_table = of_match_ptr(pcf85063_of_match),
},
.probe = pcf85063_probe,
.id_table = pcf85063_ids,
};
module_i2c_driver(pcf85063_driver);
MODULE_AUTHOR("Søren Andersen <[email protected]>");
MODULE_DESCRIPTION("PCF85063 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pcf85063.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* NXP PCF50633 RTC Driver
*
* (C) 2006-2008 by Openmoko, Inc.
* Author: Balaji Rao <[email protected]>
* All rights reserved.
*
* Broken down from monstrous PCF50633 driver mainly by
* Harald Welte, Andy Green and Werner Almesberger
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/err.h>
#include <linux/mfd/pcf50633/core.h>
#define PCF50633_REG_RTCSC 0x59 /* Second */
#define PCF50633_REG_RTCMN 0x5a /* Minute */
#define PCF50633_REG_RTCHR 0x5b /* Hour */
#define PCF50633_REG_RTCWD 0x5c /* Weekday */
#define PCF50633_REG_RTCDT 0x5d /* Day */
#define PCF50633_REG_RTCMT 0x5e /* Month */
#define PCF50633_REG_RTCYR 0x5f /* Year */
#define PCF50633_REG_RTCSCA 0x60 /* Alarm Second */
#define PCF50633_REG_RTCMNA 0x61 /* Alarm Minute */
#define PCF50633_REG_RTCHRA 0x62 /* Alarm Hour */
#define PCF50633_REG_RTCWDA 0x63 /* Alarm Weekday */
#define PCF50633_REG_RTCDTA 0x64 /* Alarm Day */
#define PCF50633_REG_RTCMTA 0x65 /* Alarm Month */
#define PCF50633_REG_RTCYRA 0x66 /* Alarm Year */
enum pcf50633_time_indexes {
PCF50633_TI_SEC,
PCF50633_TI_MIN,
PCF50633_TI_HOUR,
PCF50633_TI_WKDAY,
PCF50633_TI_DAY,
PCF50633_TI_MONTH,
PCF50633_TI_YEAR,
PCF50633_TI_EXTENT /* always last */
};
struct pcf50633_time {
u_int8_t time[PCF50633_TI_EXTENT];
};
struct pcf50633_rtc {
int alarm_enabled;
int alarm_pending;
struct pcf50633 *pcf;
struct rtc_device *rtc_dev;
};
static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50633_time *pcf)
{
rtc->tm_sec = bcd2bin(pcf->time[PCF50633_TI_SEC]);
rtc->tm_min = bcd2bin(pcf->time[PCF50633_TI_MIN]);
rtc->tm_hour = bcd2bin(pcf->time[PCF50633_TI_HOUR]);
rtc->tm_wday = bcd2bin(pcf->time[PCF50633_TI_WKDAY]);
rtc->tm_mday = bcd2bin(pcf->time[PCF50633_TI_DAY]);
rtc->tm_mon = bcd2bin(pcf->time[PCF50633_TI_MONTH]) - 1;
rtc->tm_year = bcd2bin(pcf->time[PCF50633_TI_YEAR]) + 100;
}
static void rtc2pcf_time(struct pcf50633_time *pcf, struct rtc_time *rtc)
{
pcf->time[PCF50633_TI_SEC] = bin2bcd(rtc->tm_sec);
pcf->time[PCF50633_TI_MIN] = bin2bcd(rtc->tm_min);
pcf->time[PCF50633_TI_HOUR] = bin2bcd(rtc->tm_hour);
pcf->time[PCF50633_TI_WKDAY] = bin2bcd(rtc->tm_wday);
pcf->time[PCF50633_TI_DAY] = bin2bcd(rtc->tm_mday);
pcf->time[PCF50633_TI_MONTH] = bin2bcd(rtc->tm_mon + 1);
pcf->time[PCF50633_TI_YEAR] = bin2bcd(rtc->tm_year % 100);
}
static int
pcf50633_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct pcf50633_rtc *rtc = dev_get_drvdata(dev);
int err;
if (enabled)
err = pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM);
else
err = pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM);
if (err < 0)
return err;
rtc->alarm_enabled = enabled;
return 0;
}
static int pcf50633_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcf50633_rtc *rtc;
struct pcf50633_time pcf_tm;
int ret;
rtc = dev_get_drvdata(dev);
ret = pcf50633_read_block(rtc->pcf, PCF50633_REG_RTCSC,
PCF50633_TI_EXTENT,
&pcf_tm.time[0]);
if (ret != PCF50633_TI_EXTENT) {
dev_err(dev, "Failed to read time\n");
return -EIO;
}
dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
pcf_tm.time[PCF50633_TI_DAY],
pcf_tm.time[PCF50633_TI_MONTH],
pcf_tm.time[PCF50633_TI_YEAR],
pcf_tm.time[PCF50633_TI_HOUR],
pcf_tm.time[PCF50633_TI_MIN],
pcf_tm.time[PCF50633_TI_SEC]);
pcf2rtc_time(tm, &pcf_tm);
dev_dbg(dev, "RTC_TIME: %ptRr\n", tm);
return 0;
}
static int pcf50633_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pcf50633_rtc *rtc;
struct pcf50633_time pcf_tm;
int alarm_masked, ret = 0;
rtc = dev_get_drvdata(dev);
dev_dbg(dev, "RTC_TIME: %ptRr\n", tm);
rtc2pcf_time(&pcf_tm, tm);
dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
pcf_tm.time[PCF50633_TI_DAY],
pcf_tm.time[PCF50633_TI_MONTH],
pcf_tm.time[PCF50633_TI_YEAR],
pcf_tm.time[PCF50633_TI_HOUR],
pcf_tm.time[PCF50633_TI_MIN],
pcf_tm.time[PCF50633_TI_SEC]);
alarm_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_ALARM);
if (!alarm_masked)
pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM);
/* Returns 0 on success */
ret = pcf50633_write_block(rtc->pcf, PCF50633_REG_RTCSC,
PCF50633_TI_EXTENT,
&pcf_tm.time[0]);
if (!alarm_masked)
pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM);
return ret;
}
static int pcf50633_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf50633_rtc *rtc;
struct pcf50633_time pcf_tm;
int ret = 0;
rtc = dev_get_drvdata(dev);
alrm->enabled = rtc->alarm_enabled;
alrm->pending = rtc->alarm_pending;
ret = pcf50633_read_block(rtc->pcf, PCF50633_REG_RTCSCA,
PCF50633_TI_EXTENT, &pcf_tm.time[0]);
if (ret != PCF50633_TI_EXTENT) {
dev_err(dev, "Failed to read time\n");
return -EIO;
}
pcf2rtc_time(&alrm->time, &pcf_tm);
return rtc_valid_tm(&alrm->time);
}
static int pcf50633_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf50633_rtc *rtc;
struct pcf50633_time pcf_tm;
int alarm_masked, ret = 0;
rtc = dev_get_drvdata(dev);
rtc2pcf_time(&pcf_tm, &alrm->time);
/* do like mktime does and ignore tm_wday */
pcf_tm.time[PCF50633_TI_WKDAY] = 7;
alarm_masked = pcf50633_irq_mask_get(rtc->pcf, PCF50633_IRQ_ALARM);
/* disable alarm interrupt */
if (!alarm_masked)
pcf50633_irq_mask(rtc->pcf, PCF50633_IRQ_ALARM);
/* Returns 0 on success */
ret = pcf50633_write_block(rtc->pcf, PCF50633_REG_RTCSCA,
PCF50633_TI_EXTENT, &pcf_tm.time[0]);
if (!alrm->enabled)
rtc->alarm_pending = 0;
if (!alarm_masked || alrm->enabled)
pcf50633_irq_unmask(rtc->pcf, PCF50633_IRQ_ALARM);
rtc->alarm_enabled = alrm->enabled;
return ret;
}
static const struct rtc_class_ops pcf50633_rtc_ops = {
.read_time = pcf50633_rtc_read_time,
.set_time = pcf50633_rtc_set_time,
.read_alarm = pcf50633_rtc_read_alarm,
.set_alarm = pcf50633_rtc_set_alarm,
.alarm_irq_enable = pcf50633_rtc_alarm_irq_enable,
};
static void pcf50633_rtc_irq(int irq, void *data)
{
struct pcf50633_rtc *rtc = data;
rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
rtc->alarm_pending = 1;
}
static int pcf50633_rtc_probe(struct platform_device *pdev)
{
struct pcf50633_rtc *rtc;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
rtc->pcf = dev_to_pcf50633(pdev->dev.parent);
platform_set_drvdata(pdev, rtc);
rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "pcf50633-rtc",
&pcf50633_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rtc_dev))
return PTR_ERR(rtc->rtc_dev);
pcf50633_register_irq(rtc->pcf, PCF50633_IRQ_ALARM,
pcf50633_rtc_irq, rtc);
return 0;
}
static void pcf50633_rtc_remove(struct platform_device *pdev)
{
struct pcf50633_rtc *rtc;
rtc = platform_get_drvdata(pdev);
pcf50633_free_irq(rtc->pcf, PCF50633_IRQ_ALARM);
}
static struct platform_driver pcf50633_rtc_driver = {
.driver = {
.name = "pcf50633-rtc",
},
.probe = pcf50633_rtc_probe,
.remove_new = pcf50633_rtc_remove,
};
module_platform_driver(pcf50633_rtc_driver);
MODULE_DESCRIPTION("PCF50633 RTC driver");
MODULE_AUTHOR("Balaji Rao <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pcf50633.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RTC subsystem, nvmem interface
*
* Copyright (C) 2017 Alexandre Belloni
*/
#include <linux/err.h>
#include <linux/types.h>
#include <linux/nvmem-consumer.h>
#include <linux/rtc.h>
int devm_rtc_nvmem_register(struct rtc_device *rtc,
struct nvmem_config *nvmem_config)
{
struct device *dev = rtc->dev.parent;
struct nvmem_device *nvmem;
if (!nvmem_config)
return -ENODEV;
nvmem_config->dev = dev;
nvmem_config->owner = rtc->owner;
nvmem = devm_nvmem_register(dev, nvmem_config);
if (IS_ERR(nvmem))
dev_err(dev, "failed to register nvmem device for RTC\n");
return PTR_ERR_OR_ZERO(nvmem);
}
EXPORT_SYMBOL_GPL(devm_rtc_nvmem_register);
| linux-master | drivers/rtc/nvmem.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Real Time Clock driver for AB-RTCMC-32.768kHz-EOZ9 chip.
* Copyright (C) 2019 Orolia
*
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/bitfield.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#define ABEOZ9_REG_CTRL1 0x00
#define ABEOZ9_REG_CTRL1_MASK GENMASK(7, 0)
#define ABEOZ9_REG_CTRL1_WE BIT(0)
#define ABEOZ9_REG_CTRL1_TE BIT(1)
#define ABEOZ9_REG_CTRL1_TAR BIT(2)
#define ABEOZ9_REG_CTRL1_EERE BIT(3)
#define ABEOZ9_REG_CTRL1_SRON BIT(4)
#define ABEOZ9_REG_CTRL1_TD0 BIT(5)
#define ABEOZ9_REG_CTRL1_TD1 BIT(6)
#define ABEOZ9_REG_CTRL1_CLKINT BIT(7)
#define ABEOZ9_REG_CTRL_INT 0x01
#define ABEOZ9_REG_CTRL_INT_AIE BIT(0)
#define ABEOZ9_REG_CTRL_INT_TIE BIT(1)
#define ABEOZ9_REG_CTRL_INT_V1IE BIT(2)
#define ABEOZ9_REG_CTRL_INT_V2IE BIT(3)
#define ABEOZ9_REG_CTRL_INT_SRIE BIT(4)
#define ABEOZ9_REG_CTRL_INT_FLAG 0x02
#define ABEOZ9_REG_CTRL_INT_FLAG_AF BIT(0)
#define ABEOZ9_REG_CTRL_INT_FLAG_TF BIT(1)
#define ABEOZ9_REG_CTRL_INT_FLAG_V1IF BIT(2)
#define ABEOZ9_REG_CTRL_INT_FLAG_V2IF BIT(3)
#define ABEOZ9_REG_CTRL_INT_FLAG_SRF BIT(4)
#define ABEOZ9_REG_CTRL_STATUS 0x03
#define ABEOZ9_REG_CTRL_STATUS_V1F BIT(2)
#define ABEOZ9_REG_CTRL_STATUS_V2F BIT(3)
#define ABEOZ9_REG_CTRL_STATUS_SR BIT(4)
#define ABEOZ9_REG_CTRL_STATUS_PON BIT(5)
#define ABEOZ9_REG_CTRL_STATUS_EEBUSY BIT(7)
#define ABEOZ9_REG_SEC 0x08
#define ABEOZ9_REG_MIN 0x09
#define ABEOZ9_REG_HOURS 0x0A
#define ABEOZ9_HOURS_PM BIT(6)
#define ABEOZ9_REG_DAYS 0x0B
#define ABEOZ9_REG_WEEKDAYS 0x0C
#define ABEOZ9_REG_MONTHS 0x0D
#define ABEOZ9_REG_YEARS 0x0E
#define ABEOZ9_SEC_LEN 7
#define ABEOZ9_REG_ALARM_SEC 0x10
#define ABEOZ9_BIT_ALARM_SEC GENMASK(6, 0)
#define ABEOZ9_REG_ALARM_MIN 0x11
#define ABEOZ9_BIT_ALARM_MIN GENMASK(6, 0)
#define ABEOZ9_REG_ALARM_HOURS 0x12
#define ABEOZ9_BIT_ALARM_HOURS_PM BIT(5)
#define ABEOZ9_BIT_ALARM_HOURS GENMASK(4, 0)
#define ABEOZ9_REG_ALARM_DAYS 0x13
#define ABEOZ9_BIT_ALARM_DAYS GENMASK(5, 0)
#define ABEOZ9_REG_ALARM_WEEKDAYS 0x14
#define ABEOZ9_BIT_ALARM_WEEKDAYS GENMASK(2, 0)
#define ABEOZ9_REG_ALARM_MONTHS 0x15
#define ABEOZ9_BIT_ALARM_MONTHS GENMASK(4, 0)
#define ABEOZ9_REG_ALARM_YEARS 0x16
#define ABEOZ9_ALARM_LEN 7
#define ABEOZ9_BIT_ALARM_AE BIT(7)
#define ABEOZ9_REG_REG_TEMP 0x20
#define ABEOZ953_TEMP_MAX 120
#define ABEOZ953_TEMP_MIN -60
#define ABEOZ9_REG_EEPROM 0x30
#define ABEOZ9_REG_EEPROM_MASK GENMASK(8, 0)
#define ABEOZ9_REG_EEPROM_THP BIT(0)
#define ABEOZ9_REG_EEPROM_THE BIT(1)
#define ABEOZ9_REG_EEPROM_FD0 BIT(2)
#define ABEOZ9_REG_EEPROM_FD1 BIT(3)
#define ABEOZ9_REG_EEPROM_R1K BIT(4)
#define ABEOZ9_REG_EEPROM_R5K BIT(5)
#define ABEOZ9_REG_EEPROM_R20K BIT(6)
#define ABEOZ9_REG_EEPROM_R80K BIT(7)
struct abeoz9_rtc_data {
struct rtc_device *rtc;
struct regmap *regmap;
struct device *hwmon_dev;
};
static int abeoz9_check_validity(struct device *dev)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
struct regmap *regmap = data->regmap;
int ret;
int val;
ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
if (ret < 0) {
dev_err(dev,
"unable to get CTRL_STATUS register (%d)\n", ret);
return ret;
}
if (val & ABEOZ9_REG_CTRL_STATUS_PON) {
dev_warn(dev, "power-on reset detected, date is invalid\n");
return -EINVAL;
}
if (val & ABEOZ9_REG_CTRL_STATUS_V1F) {
dev_warn(dev,
"voltage drops below VLOW1 threshold, date is invalid\n");
return -EINVAL;
}
if ((val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
dev_warn(dev,
"voltage drops below VLOW2 threshold, date is invalid\n");
return -EINVAL;
}
return 0;
}
static int abeoz9_reset_validity(struct regmap *regmap)
{
return regmap_update_bits(regmap, ABEOZ9_REG_CTRL_STATUS,
ABEOZ9_REG_CTRL_STATUS_V1F |
ABEOZ9_REG_CTRL_STATUS_V2F |
ABEOZ9_REG_CTRL_STATUS_PON,
0);
}
static int abeoz9_rtc_get_time(struct device *dev, struct rtc_time *tm)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABEOZ9_SEC_LEN];
int ret;
ret = abeoz9_check_validity(dev);
if (ret)
return ret;
ret = regmap_bulk_read(data->regmap, ABEOZ9_REG_SEC,
regs,
sizeof(regs));
if (ret) {
dev_err(dev, "reading RTC time failed (%d)\n", ret);
return ret;
}
tm->tm_sec = bcd2bin(regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] & 0x7F);
tm->tm_min = bcd2bin(regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] & 0x7F);
if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM) {
tm->tm_hour =
bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & 0x1f);
if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM)
tm->tm_hour += 12;
} else {
tm->tm_hour = bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC]);
}
tm->tm_mday = bcd2bin(regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC]);
tm->tm_wday = bcd2bin(regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC]);
tm->tm_mon = bcd2bin(regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC]) - 1;
tm->tm_year = bcd2bin(regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC]) + 100;
return ret;
}
static int abeoz9_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
struct regmap *regmap = data->regmap;
u8 regs[ABEOZ9_SEC_LEN];
int ret;
regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_sec);
regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_min);
regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_hour);
regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mday);
regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_wday);
regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mon + 1);
regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_year - 100);
ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_SEC,
regs,
sizeof(regs));
if (ret) {
dev_err(dev, "set RTC time failed (%d)\n", ret);
return ret;
}
return abeoz9_reset_validity(regmap);
}
static int abeoz9_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
struct regmap *regmap = data->regmap;
u8 regs[ABEOZ9_ALARM_LEN];
u8 val[2];
int ret;
ret = abeoz9_check_validity(dev);
if (ret)
return ret;
ret = regmap_bulk_read(regmap, ABEOZ9_REG_CTRL_INT, val, sizeof(val));
if (ret)
return ret;
alarm->enabled = val[0] & ABEOZ9_REG_CTRL_INT_AIE;
alarm->pending = val[1] & ABEOZ9_REG_CTRL_INT_FLAG_AF;
ret = regmap_bulk_read(regmap, ABEOZ9_REG_ALARM_SEC, regs, sizeof(regs));
if (ret)
return ret;
alarm->time.tm_sec = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_SEC, regs[0]));
alarm->time.tm_min = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_MIN, regs[1]));
alarm->time.tm_hour = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_HOURS, regs[2]));
if (FIELD_GET(ABEOZ9_BIT_ALARM_HOURS_PM, regs[2]))
alarm->time.tm_hour += 12;
alarm->time.tm_mday = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_DAYS, regs[3]));
return 0;
}
static int abeoz9_rtc_alarm_irq_enable(struct device *dev, u32 enable)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
return regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT,
ABEOZ9_REG_CTRL_INT_AIE,
FIELD_PREP(ABEOZ9_REG_CTRL_INT_AIE, enable));
}
static int abeoz9_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
u8 regs[ABEOZ9_ALARM_LEN] = {0};
int ret;
ret = regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG,
ABEOZ9_REG_CTRL_INT_FLAG_AF, 0);
if (ret)
return ret;
regs[0] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_SEC,
bin2bcd(alarm->time.tm_sec));
regs[1] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_MIN,
bin2bcd(alarm->time.tm_min));
regs[2] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_HOURS,
bin2bcd(alarm->time.tm_hour));
regs[3] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_DAYS,
bin2bcd(alarm->time.tm_mday));
ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_ALARM_SEC, regs,
sizeof(regs));
if (ret)
return ret;
return abeoz9_rtc_alarm_irq_enable(dev, alarm->enabled);
}
static irqreturn_t abeoz9_rtc_irq(int irq, void *dev)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
unsigned int val;
int ret;
ret = regmap_read(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG, &val);
if (ret)
return IRQ_NONE;
if (!FIELD_GET(ABEOZ9_REG_CTRL_INT_FLAG_AF, val))
return IRQ_NONE;
regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG,
ABEOZ9_REG_CTRL_INT_FLAG_AF, 0);
rtc_update_irq(data->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static int abeoz9_trickle_parse_dt(struct device_node *node)
{
u32 ohms = 0;
if (of_property_read_u32(node, "trickle-resistor-ohms", &ohms))
return 0;
switch (ohms) {
case 1000:
return ABEOZ9_REG_EEPROM_R1K;
case 5000:
return ABEOZ9_REG_EEPROM_R5K;
case 20000:
return ABEOZ9_REG_EEPROM_R20K;
case 80000:
return ABEOZ9_REG_EEPROM_R80K;
default:
return 0;
}
}
static int abeoz9_rtc_setup(struct device *dev, struct device_node *node)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
struct regmap *regmap = data->regmap;
int ret;
/* Enable Self Recovery, Clock for Watch and EEPROM refresh functions */
ret = regmap_update_bits(regmap, ABEOZ9_REG_CTRL1,
ABEOZ9_REG_CTRL1_MASK,
ABEOZ9_REG_CTRL1_WE |
ABEOZ9_REG_CTRL1_EERE |
ABEOZ9_REG_CTRL1_SRON);
if (ret < 0) {
dev_err(dev, "unable to set CTRL_1 register (%d)\n", ret);
return ret;
}
ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT, 0);
if (ret < 0) {
dev_err(dev,
"unable to set control CTRL_INT register (%d)\n",
ret);
return ret;
}
ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT_FLAG, 0);
if (ret < 0) {
dev_err(dev,
"unable to set control CTRL_INT_FLAG register (%d)\n",
ret);
return ret;
}
ret = abeoz9_trickle_parse_dt(node);
/* Enable built-in termometer */
ret |= ABEOZ9_REG_EEPROM_THE;
ret = regmap_update_bits(regmap, ABEOZ9_REG_EEPROM,
ABEOZ9_REG_EEPROM_MASK,
ret);
if (ret < 0) {
dev_err(dev, "unable to set EEPROM register (%d)\n", ret);
return ret;
}
return ret;
}
static const struct rtc_class_ops rtc_ops = {
.read_time = abeoz9_rtc_get_time,
.set_time = abeoz9_rtc_set_time,
.read_alarm = abeoz9_rtc_read_alarm,
.set_alarm = abeoz9_rtc_set_alarm,
.alarm_irq_enable = abeoz9_rtc_alarm_irq_enable,
};
static const struct regmap_config abeoz9_rtc_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x3f,
};
#if IS_REACHABLE(CONFIG_HWMON)
static int abeoz9z3_temp_read(struct device *dev,
enum hwmon_sensor_types type,
u32 attr, int channel, long *temp)
{
struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
struct regmap *regmap = data->regmap;
int ret;
unsigned int val;
ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
if (ret < 0)
return ret;
if ((val & ABEOZ9_REG_CTRL_STATUS_V1F) ||
(val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
dev_err(dev,
"thermometer might be disabled due to low voltage\n");
return -EINVAL;
}
switch (attr) {
case hwmon_temp_input:
ret = regmap_read(regmap, ABEOZ9_REG_REG_TEMP, &val);
if (ret < 0)
return ret;
*temp = 1000 * (val + ABEOZ953_TEMP_MIN);
return 0;
case hwmon_temp_max:
*temp = 1000 * ABEOZ953_TEMP_MAX;
return 0;
case hwmon_temp_min:
*temp = 1000 * ABEOZ953_TEMP_MIN;
return 0;
default:
return -EOPNOTSUPP;
}
}
static umode_t abeoz9_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (attr) {
case hwmon_temp_input:
case hwmon_temp_max:
case hwmon_temp_min:
return 0444;
default:
return 0;
}
}
static const u32 abeoz9_chip_config[] = {
HWMON_C_REGISTER_TZ,
0
};
static const struct hwmon_channel_info abeoz9_chip = {
.type = hwmon_chip,
.config = abeoz9_chip_config,
};
static const u32 abeoz9_temp_config[] = {
HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN,
0
};
static const struct hwmon_channel_info abeoz9_temp = {
.type = hwmon_temp,
.config = abeoz9_temp_config,
};
static const struct hwmon_channel_info * const abeoz9_info[] = {
&abeoz9_chip,
&abeoz9_temp,
NULL
};
static const struct hwmon_ops abeoz9_hwmon_ops = {
.is_visible = abeoz9_is_visible,
.read = abeoz9z3_temp_read,
};
static const struct hwmon_chip_info abeoz9_chip_info = {
.ops = &abeoz9_hwmon_ops,
.info = abeoz9_info,
};
static void abeoz9_hwmon_register(struct device *dev,
struct abeoz9_rtc_data *data)
{
data->hwmon_dev =
devm_hwmon_device_register_with_info(dev,
"abeoz9",
data,
&abeoz9_chip_info,
NULL);
if (IS_ERR(data->hwmon_dev)) {
dev_warn(dev, "unable to register hwmon device %ld\n",
PTR_ERR(data->hwmon_dev));
}
}
#else
static void abeoz9_hwmon_register(struct device *dev,
struct abeoz9_rtc_data *data)
{
}
#endif
static int abeoz9_probe(struct i2c_client *client)
{
struct abeoz9_rtc_data *data = NULL;
struct device *dev = &client->dev;
struct regmap *regmap;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_I2C_BLOCK))
return -ENODEV;
regmap = devm_regmap_init_i2c(client, &abeoz9_rtc_regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(dev, "regmap allocation failed: %d\n", ret);
return ret;
}
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->regmap = regmap;
dev_set_drvdata(dev, data);
ret = abeoz9_rtc_setup(dev, client->dev.of_node);
if (ret)
return ret;
data->rtc = devm_rtc_allocate_device(dev);
ret = PTR_ERR_OR_ZERO(data->rtc);
if (ret)
return ret;
data->rtc->ops = &rtc_ops;
data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
data->rtc->range_max = RTC_TIMESTAMP_END_2099;
clear_bit(RTC_FEATURE_ALARM, data->rtc->features);
if (client->irq > 0) {
unsigned long irqflags = IRQF_TRIGGER_LOW;
if (dev_fwnode(&client->dev))
irqflags = 0;
ret = devm_request_threaded_irq(dev, client->irq, NULL,
abeoz9_rtc_irq,
irqflags | IRQF_ONESHOT,
dev_name(dev), dev);
if (ret) {
dev_err(dev, "failed to request alarm irq\n");
return ret;
}
} else {
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, data->rtc->features);
}
if (client->irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
ret = device_init_wakeup(dev, true);
set_bit(RTC_FEATURE_ALARM, data->rtc->features);
}
ret = devm_rtc_register_device(data->rtc);
if (ret)
return ret;
abeoz9_hwmon_register(dev, data);
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id abeoz9_dt_match[] = {
{ .compatible = "abracon,abeoz9" },
{ },
};
MODULE_DEVICE_TABLE(of, abeoz9_dt_match);
#endif
static const struct i2c_device_id abeoz9_id[] = {
{ "abeoz9", 0 },
{ }
};
static struct i2c_driver abeoz9_driver = {
.driver = {
.name = "rtc-ab-eoz9",
.of_match_table = of_match_ptr(abeoz9_dt_match),
},
.probe = abeoz9_probe,
.id_table = abeoz9_id,
};
module_i2c_driver(abeoz9_driver);
MODULE_AUTHOR("Artem Panfilov <[email protected]>");
MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-EOZ9 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-ab-eoz9.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Real Time Clock interface for Linux on Atmel AT91RM9200
*
* Copyright (C) 2002 Rick Bronson
*
* Converted to RTC class model by Andrew Victor
*
* Ported to Linux 2.6 by Steven Scholz
* Based on s3c2410-rtc.c Simtec Electronics
*
* Based on sa1100-rtc.c by Nils Faerber
* Based on rtc.c by Paul Gortmaker
*/
#include <linux/bcd.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/ioctl.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/suspend.h>
#include <linux/time.h>
#include <linux/uaccess.h>
#define AT91_RTC_CR 0x00 /* Control Register */
#define AT91_RTC_UPDTIM BIT(0) /* Update Request Time Register */
#define AT91_RTC_UPDCAL BIT(1) /* Update Request Calendar Register */
#define AT91_RTC_MR 0x04 /* Mode Register */
#define AT91_RTC_HRMOD BIT(0) /* 12/24 hour mode */
#define AT91_RTC_NEGPPM BIT(4) /* Negative PPM correction */
#define AT91_RTC_CORRECTION GENMASK(14, 8) /* Slow clock correction */
#define AT91_RTC_HIGHPPM BIT(15) /* High PPM correction */
#define AT91_RTC_TIMR 0x08 /* Time Register */
#define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */
#define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */
#define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */
#define AT91_RTC_AMPM BIT(22) /* Ante Meridiem Post Meridiem Indicator */
#define AT91_RTC_CALR 0x0c /* Calendar Register */
#define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */
#define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */
#define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */
#define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */
#define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */
#define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */
#define AT91_RTC_SECEN BIT(7) /* Second Alarm Enable */
#define AT91_RTC_MINEN BIT(15) /* Minute Alarm Enable */
#define AT91_RTC_HOUREN BIT(23) /* Hour Alarm Enable */
#define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */
#define AT91_RTC_MTHEN BIT(23) /* Month Alarm Enable */
#define AT91_RTC_DATEEN BIT(31) /* Date Alarm Enable */
#define AT91_RTC_SR 0x18 /* Status Register */
#define AT91_RTC_ACKUPD BIT(0) /* Acknowledge for Update */
#define AT91_RTC_ALARM BIT(1) /* Alarm Flag */
#define AT91_RTC_SECEV BIT(2) /* Second Event */
#define AT91_RTC_TIMEV BIT(3) /* Time Event */
#define AT91_RTC_CALEV BIT(4) /* Calendar Event */
#define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */
#define AT91_RTC_IER 0x20 /* Interrupt Enable Register */
#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
#define AT91_RTC_VER 0x2c /* Valid Entry Register */
#define AT91_RTC_NVTIM BIT(0) /* Non valid Time */
#define AT91_RTC_NVCAL BIT(1) /* Non valid Calendar */
#define AT91_RTC_NVTIMALR BIT(2) /* Non valid Time Alarm */
#define AT91_RTC_NVCALALR BIT(3) /* Non valid Calendar Alarm */
#define AT91_RTC_CORR_DIVIDEND 3906000
#define AT91_RTC_CORR_LOW_RATIO 20
#define at91_rtc_read(field) \
readl_relaxed(at91_rtc_regs + field)
#define at91_rtc_write(field, val) \
writel_relaxed((val), at91_rtc_regs + field)
struct at91_rtc_config {
bool use_shadow_imr;
bool has_correction;
};
static const struct at91_rtc_config *at91_rtc_config;
static DECLARE_COMPLETION(at91_rtc_updated);
static DECLARE_COMPLETION(at91_rtc_upd_rdy);
static void __iomem *at91_rtc_regs;
static int irq;
static DEFINE_SPINLOCK(at91_rtc_lock);
static u32 at91_rtc_shadow_imr;
static bool suspended;
static DEFINE_SPINLOCK(suspended_lock);
static unsigned long cached_events;
static u32 at91_rtc_imr;
static struct clk *sclk;
static void at91_rtc_write_ier(u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&at91_rtc_lock, flags);
at91_rtc_shadow_imr |= mask;
at91_rtc_write(AT91_RTC_IER, mask);
spin_unlock_irqrestore(&at91_rtc_lock, flags);
}
static void at91_rtc_write_idr(u32 mask)
{
unsigned long flags;
spin_lock_irqsave(&at91_rtc_lock, flags);
at91_rtc_write(AT91_RTC_IDR, mask);
/*
* Register read back (of any RTC-register) needed to make sure
* IDR-register write has reached the peripheral before updating
* shadow mask.
*
* Note that there is still a possibility that the mask is updated
* before interrupts have actually been disabled in hardware. The only
* way to be certain would be to poll the IMR-register, which is
* the very register we are trying to emulate. The register read back
* is a reasonable heuristic.
*/
at91_rtc_read(AT91_RTC_SR);
at91_rtc_shadow_imr &= ~mask;
spin_unlock_irqrestore(&at91_rtc_lock, flags);
}
static u32 at91_rtc_read_imr(void)
{
unsigned long flags;
u32 mask;
if (at91_rtc_config->use_shadow_imr) {
spin_lock_irqsave(&at91_rtc_lock, flags);
mask = at91_rtc_shadow_imr;
spin_unlock_irqrestore(&at91_rtc_lock, flags);
} else {
mask = at91_rtc_read(AT91_RTC_IMR);
}
return mask;
}
/*
* Decode time/date into rtc_time structure
*/
static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
struct rtc_time *tm)
{
unsigned int time, date;
/* must read twice in case it changes */
do {
time = at91_rtc_read(timereg);
date = at91_rtc_read(calreg);
} while ((time != at91_rtc_read(timereg)) ||
(date != at91_rtc_read(calreg)));
tm->tm_sec = bcd2bin(FIELD_GET(AT91_RTC_SEC, time));
tm->tm_min = bcd2bin(FIELD_GET(AT91_RTC_MIN, time));
tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time));
/*
* The Calendar Alarm register does not have a field for
* the year - so these will return an invalid value.
*/
tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */
tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */
tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1; /* day of the week [0-6], Sunday=0 */
tm->tm_mon = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1;
tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date));
}
/*
* Read current time and date in RTC
*/
static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
{
at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
tm->tm_year = tm->tm_year - 1900;
dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
return 0;
}
/*
* Set current time and date in RTC
*/
static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
{
unsigned long cr;
dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
wait_for_completion(&at91_rtc_upd_rdy);
/* Stop Time/Calendar from counting */
cr = at91_rtc_read(AT91_RTC_CR);
at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
at91_rtc_write_ier(AT91_RTC_ACKUPD);
wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
at91_rtc_write_idr(AT91_RTC_ACKUPD);
at91_rtc_write(AT91_RTC_TIMR,
FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec))
| FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min))
| FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour)));
at91_rtc_write(AT91_RTC_CALR,
FIELD_PREP(AT91_RTC_CENT,
bin2bcd((tm->tm_year + 1900) / 100))
| FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100))
| FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1))
| FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1))
| FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday)));
/* Restart Time/Calendar */
cr = at91_rtc_read(AT91_RTC_CR);
at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV);
at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
at91_rtc_write_ier(AT91_RTC_SECEV);
return 0;
}
/*
* Read alarm time and date in RTC
*/
static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_time *tm = &alrm->time;
at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
tm->tm_year = -1;
alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
? 1 : 0;
dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm,
alrm->enabled ? "en" : "dis");
return 0;
}
/*
* Set alarm time and date in RTC
*/
static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_time tm = alrm->time;
at91_rtc_write_idr(AT91_RTC_ALARM);
at91_rtc_write(AT91_RTC_TIMALR,
FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec))
| FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min))
| FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour))
| AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
at91_rtc_write(AT91_RTC_CALALR,
FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1))
| FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday))
| AT91_RTC_DATEEN | AT91_RTC_MTHEN);
if (alrm->enabled) {
at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
at91_rtc_write_ier(AT91_RTC_ALARM);
}
dev_dbg(dev, "%s(): %ptR\n", __func__, &tm);
return 0;
}
static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled);
if (enabled) {
at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
at91_rtc_write_ier(AT91_RTC_ALARM);
} else
at91_rtc_write_idr(AT91_RTC_ALARM);
return 0;
}
static int at91_rtc_readoffset(struct device *dev, long *offset)
{
u32 mr = at91_rtc_read(AT91_RTC_MR);
long val = FIELD_GET(AT91_RTC_CORRECTION, mr);
if (!val) {
*offset = 0;
return 0;
}
val++;
if (!(mr & AT91_RTC_NEGPPM))
val = -val;
if (!(mr & AT91_RTC_HIGHPPM))
val *= AT91_RTC_CORR_LOW_RATIO;
*offset = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, val);
return 0;
}
static int at91_rtc_setoffset(struct device *dev, long offset)
{
long corr;
u32 mr;
if (offset > AT91_RTC_CORR_DIVIDEND / 2)
return -ERANGE;
if (offset < -AT91_RTC_CORR_DIVIDEND / 2)
return -ERANGE;
mr = at91_rtc_read(AT91_RTC_MR);
mr &= ~(AT91_RTC_NEGPPM | AT91_RTC_CORRECTION | AT91_RTC_HIGHPPM);
if (offset > 0)
mr |= AT91_RTC_NEGPPM;
else
offset = -offset;
/* offset less than 764 ppb, disable correction*/
if (offset < 764) {
at91_rtc_write(AT91_RTC_MR, mr & ~AT91_RTC_NEGPPM);
return 0;
}
/*
* 29208 ppb is the perfect cutoff between low range and high range
* low range values are never better than high range value after that.
*/
if (offset < 29208) {
corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset * AT91_RTC_CORR_LOW_RATIO);
} else {
corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset);
mr |= AT91_RTC_HIGHPPM;
}
if (corr > 128)
corr = 128;
mr |= FIELD_PREP(AT91_RTC_CORRECTION, corr - 1);
at91_rtc_write(AT91_RTC_MR, mr);
return 0;
}
/*
* IRQ handler for the RTC
*/
static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct rtc_device *rtc = platform_get_drvdata(pdev);
unsigned int rtsr;
unsigned long events = 0;
int ret = IRQ_NONE;
spin_lock(&suspended_lock);
rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
if (rtsr) { /* this interrupt is shared! Is it ours? */
if (rtsr & AT91_RTC_ALARM)
events |= (RTC_AF | RTC_IRQF);
if (rtsr & AT91_RTC_SECEV) {
complete(&at91_rtc_upd_rdy);
at91_rtc_write_idr(AT91_RTC_SECEV);
}
if (rtsr & AT91_RTC_ACKUPD)
complete(&at91_rtc_updated);
at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */
if (!suspended) {
rtc_update_irq(rtc, 1, events);
dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n",
__func__, events >> 8, events & 0x000000FF);
} else {
cached_events |= events;
at91_rtc_write_idr(at91_rtc_imr);
pm_system_wakeup();
}
ret = IRQ_HANDLED;
}
spin_unlock(&suspended_lock);
return ret;
}
static const struct at91_rtc_config at91rm9200_config = {
};
static const struct at91_rtc_config at91sam9x5_config = {
.use_shadow_imr = true,
};
static const struct at91_rtc_config sama5d4_config = {
.has_correction = true,
};
static const struct of_device_id at91_rtc_dt_ids[] = {
{
.compatible = "atmel,at91rm9200-rtc",
.data = &at91rm9200_config,
}, {
.compatible = "atmel,at91sam9x5-rtc",
.data = &at91sam9x5_config,
}, {
.compatible = "atmel,sama5d4-rtc",
.data = &sama5d4_config,
}, {
.compatible = "atmel,sama5d2-rtc",
.data = &sama5d4_config,
}, {
.compatible = "microchip,sam9x60-rtc",
.data = &sama5d4_config,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
static const struct rtc_class_ops at91_rtc_ops = {
.read_time = at91_rtc_readtime,
.set_time = at91_rtc_settime,
.read_alarm = at91_rtc_readalarm,
.set_alarm = at91_rtc_setalarm,
.alarm_irq_enable = at91_rtc_alarm_irq_enable,
};
static const struct rtc_class_ops sama5d4_rtc_ops = {
.read_time = at91_rtc_readtime,
.set_time = at91_rtc_settime,
.read_alarm = at91_rtc_readalarm,
.set_alarm = at91_rtc_setalarm,
.alarm_irq_enable = at91_rtc_alarm_irq_enable,
.set_offset = at91_rtc_setoffset,
.read_offset = at91_rtc_readoffset,
};
/*
* Initialize and install RTC driver
*/
static int __init at91_rtc_probe(struct platform_device *pdev)
{
struct rtc_device *rtc;
struct resource *regs;
int ret = 0;
at91_rtc_config = of_device_get_match_data(&pdev->dev);
if (!at91_rtc_config)
return -ENODEV;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(&pdev->dev, "no mmio resource defined\n");
return -ENXIO;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENXIO;
at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start,
resource_size(regs));
if (!at91_rtc_regs) {
dev_err(&pdev->dev, "failed to map registers, aborting.\n");
return -ENOMEM;
}
rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
platform_set_drvdata(pdev, rtc);
sclk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(sclk))
return PTR_ERR(sclk);
ret = clk_prepare_enable(sclk);
if (ret) {
dev_err(&pdev->dev, "Could not enable slow clock\n");
return ret;
}
at91_rtc_write(AT91_RTC_CR, 0);
at91_rtc_write(AT91_RTC_MR, at91_rtc_read(AT91_RTC_MR) & ~AT91_RTC_HRMOD);
/* Disable all interrupts */
at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
AT91_RTC_SECEV | AT91_RTC_TIMEV |
AT91_RTC_CALEV);
ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt,
IRQF_SHARED | IRQF_COND_SUSPEND,
"at91_rtc", pdev);
if (ret) {
dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
goto err_clk;
}
/* cpu init code should really have flagged this device as
* being wake-capable; if it didn't, do that here.
*/
if (!device_can_wakeup(&pdev->dev))
device_init_wakeup(&pdev->dev, 1);
if (at91_rtc_config->has_correction)
rtc->ops = &sama5d4_rtc_ops;
else
rtc->ops = &at91_rtc_ops;
rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
rtc->range_max = RTC_TIMESTAMP_END_2099;
ret = devm_rtc_register_device(rtc);
if (ret)
goto err_clk;
/* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
* completion.
*/
at91_rtc_write_ier(AT91_RTC_SECEV);
dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
return 0;
err_clk:
clk_disable_unprepare(sclk);
return ret;
}
/*
* Disable and remove the RTC driver
*/
static int __exit at91_rtc_remove(struct platform_device *pdev)
{
/* Disable all interrupts */
at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
AT91_RTC_SECEV | AT91_RTC_TIMEV |
AT91_RTC_CALEV);
clk_disable_unprepare(sclk);
return 0;
}
static void at91_rtc_shutdown(struct platform_device *pdev)
{
/* Disable all interrupts */
at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
AT91_RTC_SECEV | AT91_RTC_TIMEV |
AT91_RTC_CALEV);
}
#ifdef CONFIG_PM_SLEEP
/* AT91RM9200 RTC Power management control */
static int at91_rtc_suspend(struct device *dev)
{
/* this IRQ is shared with DBGU and other hardware which isn't
* necessarily doing PM like we are...
*/
at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
at91_rtc_imr = at91_rtc_read_imr()
& (AT91_RTC_ALARM|AT91_RTC_SECEV);
if (at91_rtc_imr) {
if (device_may_wakeup(dev)) {
unsigned long flags;
enable_irq_wake(irq);
spin_lock_irqsave(&suspended_lock, flags);
suspended = true;
spin_unlock_irqrestore(&suspended_lock, flags);
} else {
at91_rtc_write_idr(at91_rtc_imr);
}
}
return 0;
}
static int at91_rtc_resume(struct device *dev)
{
struct rtc_device *rtc = dev_get_drvdata(dev);
if (at91_rtc_imr) {
if (device_may_wakeup(dev)) {
unsigned long flags;
spin_lock_irqsave(&suspended_lock, flags);
if (cached_events) {
rtc_update_irq(rtc, 1, cached_events);
cached_events = 0;
}
suspended = false;
spin_unlock_irqrestore(&suspended_lock, flags);
disable_irq_wake(irq);
}
at91_rtc_write_ier(at91_rtc_imr);
}
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
static struct platform_driver at91_rtc_driver = {
.remove = __exit_p(at91_rtc_remove),
.shutdown = at91_rtc_shutdown,
.driver = {
.name = "at91_rtc",
.pm = &at91_rtc_pm_ops,
.of_match_table = at91_rtc_dt_ids,
},
};
module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe);
MODULE_AUTHOR("Rick Bronson");
MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:at91_rtc");
| linux-master | drivers/rtc/rtc-at91rm9200.c |
// SPDX-License-Identifier: GPL-2.0-only
/* drivers/rtc/rtc-rx4581.c
*
* written by Torben Hohn <[email protected]>
*
* Based on:
* drivers/rtc/rtc-max6902.c
*
* Copyright (C) 2006 8D Technologies inc.
* Copyright (C) 2004 Compulab Ltd.
*
* Driver for MAX6902 spi RTC
*
* and based on:
* drivers/rtc/rtc-rx8581.c
*
* An I2C driver for the Epson RX8581 RTC
*
* Author: Martyn Welch <[email protected]>
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
*
* Based on: rtc-pcf8563.c (An I2C driver for the Philips PCF8563 RTC)
* Copyright 2005-06 Tower Technologies
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
#define RX4581_REG_SC 0x00 /* Second in BCD */
#define RX4581_REG_MN 0x01 /* Minute in BCD */
#define RX4581_REG_HR 0x02 /* Hour in BCD */
#define RX4581_REG_DW 0x03 /* Day of Week */
#define RX4581_REG_DM 0x04 /* Day of Month in BCD */
#define RX4581_REG_MO 0x05 /* Month in BCD */
#define RX4581_REG_YR 0x06 /* Year in BCD */
#define RX4581_REG_RAM 0x07 /* RAM */
#define RX4581_REG_AMN 0x08 /* Alarm Min in BCD*/
#define RX4581_REG_AHR 0x09 /* Alarm Hour in BCD */
#define RX4581_REG_ADM 0x0A
#define RX4581_REG_ADW 0x0A
#define RX4581_REG_TMR0 0x0B
#define RX4581_REG_TMR1 0x0C
#define RX4581_REG_EXT 0x0D /* Extension Register */
#define RX4581_REG_FLAG 0x0E /* Flag Register */
#define RX4581_REG_CTRL 0x0F /* Control Register */
/* Flag Register bit definitions */
#define RX4581_FLAG_UF 0x20 /* Update */
#define RX4581_FLAG_TF 0x10 /* Timer */
#define RX4581_FLAG_AF 0x08 /* Alarm */
#define RX4581_FLAG_VLF 0x02 /* Voltage Low */
/* Control Register bit definitions */
#define RX4581_CTRL_UIE 0x20 /* Update Interrupt Enable */
#define RX4581_CTRL_TIE 0x10 /* Timer Interrupt Enable */
#define RX4581_CTRL_AIE 0x08 /* Alarm Interrupt Enable */
#define RX4581_CTRL_STOP 0x02 /* STOP bit */
#define RX4581_CTRL_RESET 0x01 /* RESET bit */
static int rx4581_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* high nibble must be '0' to write */
buf[0] = address & 0x0f;
buf[1] = data;
return spi_write_then_read(spi, buf, 2, NULL, 0);
}
static int rx4581_get_reg(struct device *dev, unsigned char address,
unsigned char *data)
{
struct spi_device *spi = to_spi_device(dev);
/* Set MSB to indicate read */
*data = address | 0x80;
return spi_write_then_read(spi, data, 1, data, 1);
}
/*
* In the routines that deal directly with the rx8581 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
*/
static int rx4581_get_datetime(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char date[7];
unsigned char data;
int err;
/* First we ensure that the "update flag" is not set, we read the
* time and date then re-read the "update flag". If the update flag
* has been set, we know that the time has changed during the read so
* we repeat the whole process again.
*/
err = rx4581_get_reg(dev, RX4581_REG_FLAG, &data);
if (err != 0) {
dev_err(dev, "Unable to read device flags\n");
return -EIO;
}
do {
/* If update flag set, clear it */
if (data & RX4581_FLAG_UF) {
err = rx4581_set_reg(dev,
RX4581_REG_FLAG, (data & ~RX4581_FLAG_UF));
if (err != 0) {
dev_err(dev, "Unable to write device "
"flags\n");
return -EIO;
}
}
/* Now read time and date */
date[0] = 0x80;
err = spi_write_then_read(spi, date, 1, date, 7);
if (err < 0) {
dev_err(dev, "Unable to read date\n");
return -EIO;
}
/* Check flag register */
err = rx4581_get_reg(dev, RX4581_REG_FLAG, &data);
if (err != 0) {
dev_err(dev, "Unable to read device flags\n");
return -EIO;
}
} while (data & RX4581_FLAG_UF);
if (data & RX4581_FLAG_VLF)
dev_info(dev,
"low voltage detected, date/time is not reliable.\n");
dev_dbg(dev,
"%s: raw data is sec=%02x, min=%02x, hr=%02x, "
"wday=%02x, mday=%02x, mon=%02x, year=%02x\n",
__func__,
date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
tm->tm_sec = bcd2bin(date[RX4581_REG_SC] & 0x7F);
tm->tm_min = bcd2bin(date[RX4581_REG_MN] & 0x7F);
tm->tm_hour = bcd2bin(date[RX4581_REG_HR] & 0x3F); /* rtc hr 0-23 */
tm->tm_wday = ilog2(date[RX4581_REG_DW] & 0x7F);
tm->tm_mday = bcd2bin(date[RX4581_REG_DM] & 0x3F);
tm->tm_mon = bcd2bin(date[RX4581_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
tm->tm_year = bcd2bin(date[RX4581_REG_YR]);
if (tm->tm_year < 70)
tm->tm_year += 100; /* assume we are in 1970...2069 */
dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__func__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
return 0;
}
static int rx4581_set_datetime(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
int err;
unsigned char buf[8], data;
dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__func__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
buf[0] = 0x00;
/* hours, minutes and seconds */
buf[RX4581_REG_SC+1] = bin2bcd(tm->tm_sec);
buf[RX4581_REG_MN+1] = bin2bcd(tm->tm_min);
buf[RX4581_REG_HR+1] = bin2bcd(tm->tm_hour);
buf[RX4581_REG_DM+1] = bin2bcd(tm->tm_mday);
/* month, 1 - 12 */
buf[RX4581_REG_MO+1] = bin2bcd(tm->tm_mon + 1);
/* year and century */
buf[RX4581_REG_YR+1] = bin2bcd(tm->tm_year % 100);
buf[RX4581_REG_DW+1] = (0x1 << tm->tm_wday);
/* Stop the clock */
err = rx4581_get_reg(dev, RX4581_REG_CTRL, &data);
if (err != 0) {
dev_err(dev, "Unable to read control register\n");
return -EIO;
}
err = rx4581_set_reg(dev, RX4581_REG_CTRL,
(data | RX4581_CTRL_STOP));
if (err != 0) {
dev_err(dev, "Unable to write control register\n");
return -EIO;
}
/* write register's data */
err = spi_write_then_read(spi, buf, 8, NULL, 0);
if (err != 0) {
dev_err(dev, "Unable to write to date registers\n");
return -EIO;
}
/* get VLF and clear it */
err = rx4581_get_reg(dev, RX4581_REG_FLAG, &data);
if (err != 0) {
dev_err(dev, "Unable to read flag register\n");
return -EIO;
}
err = rx4581_set_reg(dev, RX4581_REG_FLAG,
(data & ~(RX4581_FLAG_VLF)));
if (err != 0) {
dev_err(dev, "Unable to write flag register\n");
return -EIO;
}
/* Restart the clock */
err = rx4581_get_reg(dev, RX4581_REG_CTRL, &data);
if (err != 0) {
dev_err(dev, "Unable to read control register\n");
return -EIO;
}
err = rx4581_set_reg(dev, RX4581_REG_CTRL,
(data & ~(RX4581_CTRL_STOP)));
if (err != 0) {
dev_err(dev, "Unable to write control register\n");
return -EIO;
}
return 0;
}
static const struct rtc_class_ops rx4581_rtc_ops = {
.read_time = rx4581_get_datetime,
.set_time = rx4581_set_datetime,
};
static int rx4581_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
unsigned char tmp;
int res;
res = rx4581_get_reg(&spi->dev, RX4581_REG_SC, &tmp);
if (res != 0)
return res;
rtc = devm_rtc_device_register(&spi->dev, "rx4581",
&rx4581_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
spi_set_drvdata(spi, rtc);
return 0;
}
static const struct spi_device_id rx4581_id[] = {
{ "rx4581", 0 },
{ }
};
MODULE_DEVICE_TABLE(spi, rx4581_id);
static struct spi_driver rx4581_driver = {
.driver = {
.name = "rtc-rx4581",
},
.probe = rx4581_probe,
.id_table = rx4581_id,
};
module_spi_driver(rx4581_driver);
MODULE_DESCRIPTION("rx4581 spi RTC driver");
MODULE_AUTHOR("Torben Hohn");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rtc-rx4581");
| linux-master | drivers/rtc/rtc-rx4581.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Cadence
*
* Authors:
* Jan Kotas <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/rtc.h>
#include <linux/clk.h>
#include <linux/bcd.h>
#include <linux/bitfield.h>
#include <linux/interrupt.h>
#include <linux/pm_wakeirq.h>
/* Registers */
#define CDNS_RTC_CTLR 0x00
#define CDNS_RTC_HMR 0x04
#define CDNS_RTC_TIMR 0x08
#define CDNS_RTC_CALR 0x0C
#define CDNS_RTC_TIMAR 0x10
#define CDNS_RTC_CALAR 0x14
#define CDNS_RTC_AENR 0x18
#define CDNS_RTC_EFLR 0x1C
#define CDNS_RTC_IENR 0x20
#define CDNS_RTC_IDISR 0x24
#define CDNS_RTC_IMSKR 0x28
#define CDNS_RTC_STSR 0x2C
#define CDNS_RTC_KRTCR 0x30
/* Control */
#define CDNS_RTC_CTLR_TIME BIT(0)
#define CDNS_RTC_CTLR_CAL BIT(1)
#define CDNS_RTC_CTLR_TIME_CAL (CDNS_RTC_CTLR_TIME | CDNS_RTC_CTLR_CAL)
/* Status */
#define CDNS_RTC_STSR_VT BIT(0)
#define CDNS_RTC_STSR_VC BIT(1)
#define CDNS_RTC_STSR_VTA BIT(2)
#define CDNS_RTC_STSR_VCA BIT(3)
#define CDNS_RTC_STSR_VT_VC (CDNS_RTC_STSR_VT | CDNS_RTC_STSR_VC)
#define CDNS_RTC_STSR_VTA_VCA (CDNS_RTC_STSR_VTA | CDNS_RTC_STSR_VCA)
/* Keep RTC */
#define CDNS_RTC_KRTCR_KRTC BIT(0)
/* Alarm, Event, Interrupt */
#define CDNS_RTC_AEI_HOS BIT(0)
#define CDNS_RTC_AEI_SEC BIT(1)
#define CDNS_RTC_AEI_MIN BIT(2)
#define CDNS_RTC_AEI_HOUR BIT(3)
#define CDNS_RTC_AEI_DATE BIT(4)
#define CDNS_RTC_AEI_MNTH BIT(5)
#define CDNS_RTC_AEI_ALRM BIT(6)
/* Time */
#define CDNS_RTC_TIME_H GENMASK(7, 0)
#define CDNS_RTC_TIME_S GENMASK(14, 8)
#define CDNS_RTC_TIME_M GENMASK(22, 16)
#define CDNS_RTC_TIME_HR GENMASK(29, 24)
#define CDNS_RTC_TIME_PM BIT(30)
#define CDNS_RTC_TIME_CH BIT(31)
/* Calendar */
#define CDNS_RTC_CAL_DAY GENMASK(2, 0)
#define CDNS_RTC_CAL_M GENMASK(7, 3)
#define CDNS_RTC_CAL_D GENMASK(13, 8)
#define CDNS_RTC_CAL_Y GENMASK(23, 16)
#define CDNS_RTC_CAL_C GENMASK(29, 24)
#define CDNS_RTC_CAL_CH BIT(31)
#define CDNS_RTC_MAX_REGS_TRIES 3
struct cdns_rtc {
struct rtc_device *rtc_dev;
struct clk *pclk;
struct clk *ref_clk;
void __iomem *regs;
int irq;
};
static void cdns_rtc_set_enabled(struct cdns_rtc *crtc, bool enabled)
{
u32 reg = enabled ? 0x0 : CDNS_RTC_CTLR_TIME_CAL;
writel(reg, crtc->regs + CDNS_RTC_CTLR);
}
static bool cdns_rtc_get_enabled(struct cdns_rtc *crtc)
{
return !(readl(crtc->regs + CDNS_RTC_CTLR) & CDNS_RTC_CTLR_TIME_CAL);
}
static irqreturn_t cdns_rtc_irq_handler(int irq, void *id)
{
struct device *dev = id;
struct cdns_rtc *crtc = dev_get_drvdata(dev);
/* Reading the register clears it */
if (!(readl(crtc->regs + CDNS_RTC_EFLR) & CDNS_RTC_AEI_ALRM))
return IRQ_NONE;
rtc_update_irq(crtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static u32 cdns_rtc_time2reg(struct rtc_time *tm)
{
return FIELD_PREP(CDNS_RTC_TIME_S, bin2bcd(tm->tm_sec))
| FIELD_PREP(CDNS_RTC_TIME_M, bin2bcd(tm->tm_min))
| FIELD_PREP(CDNS_RTC_TIME_HR, bin2bcd(tm->tm_hour));
}
static void cdns_rtc_reg2time(u32 reg, struct rtc_time *tm)
{
tm->tm_sec = bcd2bin(FIELD_GET(CDNS_RTC_TIME_S, reg));
tm->tm_min = bcd2bin(FIELD_GET(CDNS_RTC_TIME_M, reg));
tm->tm_hour = bcd2bin(FIELD_GET(CDNS_RTC_TIME_HR, reg));
}
static int cdns_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
u32 reg;
/* If the RTC is disabled, assume the values are invalid */
if (!cdns_rtc_get_enabled(crtc))
return -EINVAL;
cdns_rtc_set_enabled(crtc, false);
reg = readl(crtc->regs + CDNS_RTC_TIMR);
cdns_rtc_reg2time(reg, tm);
reg = readl(crtc->regs + CDNS_RTC_CALR);
tm->tm_mday = bcd2bin(FIELD_GET(CDNS_RTC_CAL_D, reg));
tm->tm_mon = bcd2bin(FIELD_GET(CDNS_RTC_CAL_M, reg)) - 1;
tm->tm_year = bcd2bin(FIELD_GET(CDNS_RTC_CAL_Y, reg))
+ bcd2bin(FIELD_GET(CDNS_RTC_CAL_C, reg)) * 100 - 1900;
tm->tm_wday = bcd2bin(FIELD_GET(CDNS_RTC_CAL_DAY, reg)) - 1;
cdns_rtc_set_enabled(crtc, true);
return 0;
}
static int cdns_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
u32 timr, calr, stsr;
int ret = -EIO;
int year = tm->tm_year + 1900;
int tries;
cdns_rtc_set_enabled(crtc, false);
timr = cdns_rtc_time2reg(tm);
calr = FIELD_PREP(CDNS_RTC_CAL_D, bin2bcd(tm->tm_mday))
| FIELD_PREP(CDNS_RTC_CAL_M, bin2bcd(tm->tm_mon + 1))
| FIELD_PREP(CDNS_RTC_CAL_Y, bin2bcd(year % 100))
| FIELD_PREP(CDNS_RTC_CAL_C, bin2bcd(year / 100))
| FIELD_PREP(CDNS_RTC_CAL_DAY, tm->tm_wday + 1);
/* Update registers, check valid flags */
for (tries = 0; tries < CDNS_RTC_MAX_REGS_TRIES; tries++) {
writel(timr, crtc->regs + CDNS_RTC_TIMR);
writel(calr, crtc->regs + CDNS_RTC_CALR);
stsr = readl(crtc->regs + CDNS_RTC_STSR);
if ((stsr & CDNS_RTC_STSR_VT_VC) == CDNS_RTC_STSR_VT_VC) {
ret = 0;
break;
}
}
cdns_rtc_set_enabled(crtc, true);
return ret;
}
static int cdns_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
if (enabled) {
writel((CDNS_RTC_AEI_SEC | CDNS_RTC_AEI_MIN | CDNS_RTC_AEI_HOUR
| CDNS_RTC_AEI_DATE | CDNS_RTC_AEI_MNTH),
crtc->regs + CDNS_RTC_AENR);
writel(CDNS_RTC_AEI_ALRM, crtc->regs + CDNS_RTC_IENR);
} else {
writel(0, crtc->regs + CDNS_RTC_AENR);
writel(CDNS_RTC_AEI_ALRM, crtc->regs + CDNS_RTC_IDISR);
}
return 0;
}
static int cdns_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
u32 reg;
reg = readl(crtc->regs + CDNS_RTC_TIMAR);
cdns_rtc_reg2time(reg, &alarm->time);
reg = readl(crtc->regs + CDNS_RTC_CALAR);
alarm->time.tm_mday = bcd2bin(FIELD_GET(CDNS_RTC_CAL_D, reg));
alarm->time.tm_mon = bcd2bin(FIELD_GET(CDNS_RTC_CAL_M, reg)) - 1;
return 0;
}
static int cdns_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
int ret = -EIO;
int tries;
u32 timar, calar, stsr;
cdns_rtc_alarm_irq_enable(dev, 0);
timar = cdns_rtc_time2reg(&alarm->time);
calar = FIELD_PREP(CDNS_RTC_CAL_D, bin2bcd(alarm->time.tm_mday))
| FIELD_PREP(CDNS_RTC_CAL_M, bin2bcd(alarm->time.tm_mon + 1));
/* Update registers, check valid alarm flags */
for (tries = 0; tries < CDNS_RTC_MAX_REGS_TRIES; tries++) {
writel(timar, crtc->regs + CDNS_RTC_TIMAR);
writel(calar, crtc->regs + CDNS_RTC_CALAR);
stsr = readl(crtc->regs + CDNS_RTC_STSR);
if ((stsr & CDNS_RTC_STSR_VTA_VCA) == CDNS_RTC_STSR_VTA_VCA) {
ret = 0;
break;
}
}
if (!ret)
cdns_rtc_alarm_irq_enable(dev, alarm->enabled);
return ret;
}
static const struct rtc_class_ops cdns_rtc_ops = {
.read_time = cdns_rtc_read_time,
.set_time = cdns_rtc_set_time,
.read_alarm = cdns_rtc_read_alarm,
.set_alarm = cdns_rtc_set_alarm,
.alarm_irq_enable = cdns_rtc_alarm_irq_enable,
};
static int cdns_rtc_probe(struct platform_device *pdev)
{
struct cdns_rtc *crtc;
int ret;
unsigned long ref_clk_freq;
crtc = devm_kzalloc(&pdev->dev, sizeof(*crtc), GFP_KERNEL);
if (!crtc)
return -ENOMEM;
crtc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(crtc->regs))
return PTR_ERR(crtc->regs);
crtc->irq = platform_get_irq(pdev, 0);
if (crtc->irq < 0)
return -EINVAL;
crtc->pclk = devm_clk_get(&pdev->dev, "pclk");
if (IS_ERR(crtc->pclk)) {
ret = PTR_ERR(crtc->pclk);
dev_err(&pdev->dev,
"Failed to retrieve the peripheral clock, %d\n", ret);
return ret;
}
crtc->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
if (IS_ERR(crtc->ref_clk)) {
ret = PTR_ERR(crtc->ref_clk);
dev_err(&pdev->dev,
"Failed to retrieve the reference clock, %d\n", ret);
return ret;
}
crtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(crtc->rtc_dev))
return PTR_ERR(crtc->rtc_dev);
platform_set_drvdata(pdev, crtc);
ret = clk_prepare_enable(crtc->pclk);
if (ret) {
dev_err(&pdev->dev,
"Failed to enable the peripheral clock, %d\n", ret);
return ret;
}
ret = clk_prepare_enable(crtc->ref_clk);
if (ret) {
dev_err(&pdev->dev,
"Failed to enable the reference clock, %d\n", ret);
goto err_disable_pclk;
}
ref_clk_freq = clk_get_rate(crtc->ref_clk);
if ((ref_clk_freq != 1) && (ref_clk_freq != 100)) {
dev_err(&pdev->dev,
"Invalid reference clock frequency %lu Hz.\n",
ref_clk_freq);
ret = -EINVAL;
goto err_disable_ref_clk;
}
ret = devm_request_irq(&pdev->dev, crtc->irq,
cdns_rtc_irq_handler, 0,
dev_name(&pdev->dev), &pdev->dev);
if (ret) {
dev_err(&pdev->dev,
"Failed to request interrupt for the device, %d\n",
ret);
goto err_disable_ref_clk;
}
/* The RTC supports 01.01.1900 - 31.12.2999 */
crtc->rtc_dev->range_min = mktime64(1900, 1, 1, 0, 0, 0);
crtc->rtc_dev->range_max = mktime64(2999, 12, 31, 23, 59, 59);
crtc->rtc_dev->ops = &cdns_rtc_ops;
device_init_wakeup(&pdev->dev, true);
/* Always use 24-hour mode and keep the RTC values */
writel(0, crtc->regs + CDNS_RTC_HMR);
writel(CDNS_RTC_KRTCR_KRTC, crtc->regs + CDNS_RTC_KRTCR);
ret = devm_rtc_register_device(crtc->rtc_dev);
if (ret)
goto err_disable_wakeup;
return 0;
err_disable_wakeup:
device_init_wakeup(&pdev->dev, false);
err_disable_ref_clk:
clk_disable_unprepare(crtc->ref_clk);
err_disable_pclk:
clk_disable_unprepare(crtc->pclk);
return ret;
}
static void cdns_rtc_remove(struct platform_device *pdev)
{
struct cdns_rtc *crtc = platform_get_drvdata(pdev);
cdns_rtc_alarm_irq_enable(&pdev->dev, 0);
device_init_wakeup(&pdev->dev, 0);
clk_disable_unprepare(crtc->pclk);
clk_disable_unprepare(crtc->ref_clk);
}
#ifdef CONFIG_PM_SLEEP
static int cdns_rtc_suspend(struct device *dev)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(crtc->irq);
return 0;
}
static int cdns_rtc_resume(struct device *dev)
{
struct cdns_rtc *crtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(crtc->irq);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(cdns_rtc_pm_ops, cdns_rtc_suspend, cdns_rtc_resume);
static const struct of_device_id cdns_rtc_of_match[] = {
{ .compatible = "cdns,rtc-r109v3" },
{ },
};
MODULE_DEVICE_TABLE(of, cdns_rtc_of_match);
static struct platform_driver cdns_rtc_driver = {
.driver = {
.name = "cdns-rtc",
.of_match_table = cdns_rtc_of_match,
.pm = &cdns_rtc_pm_ops,
},
.probe = cdns_rtc_probe,
.remove_new = cdns_rtc_remove,
};
module_platform_driver(cdns_rtc_driver);
MODULE_AUTHOR("Jan Kotas <[email protected]>");
MODULE_DESCRIPTION("Cadence RTC driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:cdns-rtc");
| linux-master | drivers/rtc/rtc-cadence.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2022 NXP.
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#define BBNSM_CTRL 0x8
#define BBNSM_INT_EN 0x10
#define BBNSM_EVENTS 0x14
#define BBNSM_RTC_LS 0x40
#define BBNSM_RTC_MS 0x44
#define BBNSM_TA 0x50
#define RTC_EN 0x2
#define RTC_EN_MSK 0x3
#define TA_EN (0x2 << 2)
#define TA_DIS (0x1 << 2)
#define TA_EN_MSK (0x3 << 2)
#define RTC_INT_EN 0x2
#define TA_INT_EN (0x2 << 2)
#define BBNSM_EVENT_TA (0x2 << 2)
#define CNTR_TO_SECS_SH 15
struct bbnsm_rtc {
struct rtc_device *rtc;
struct regmap *regmap;
int irq;
struct clk *clk;
};
static u32 bbnsm_read_counter(struct bbnsm_rtc *bbnsm)
{
u32 rtc_msb, rtc_lsb;
unsigned int timeout = 100;
u32 time;
u32 tmp = 0;
do {
time = tmp;
/* read the msb */
regmap_read(bbnsm->regmap, BBNSM_RTC_MS, &rtc_msb);
/* read the lsb */
regmap_read(bbnsm->regmap, BBNSM_RTC_LS, &rtc_lsb);
/* convert to seconds */
tmp = (rtc_msb << 17) | (rtc_lsb >> 15);
} while (tmp != time && --timeout);
return time;
}
static int bbnsm_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct bbnsm_rtc *bbnsm = dev_get_drvdata(dev);
unsigned long time;
u32 val;
regmap_read(bbnsm->regmap, BBNSM_CTRL, &val);
if ((val & RTC_EN_MSK) != RTC_EN)
return -EINVAL;
time = bbnsm_read_counter(bbnsm);
rtc_time64_to_tm(time, tm);
return 0;
}
static int bbnsm_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct bbnsm_rtc *bbnsm = dev_get_drvdata(dev);
unsigned long time = rtc_tm_to_time64(tm);
/* disable the RTC first */
regmap_update_bits(bbnsm->regmap, BBNSM_CTRL, RTC_EN_MSK, 0);
/* write the 32bit sec time to 47 bit timer counter, leaving 15 LSBs blank */
regmap_write(bbnsm->regmap, BBNSM_RTC_LS, time << CNTR_TO_SECS_SH);
regmap_write(bbnsm->regmap, BBNSM_RTC_MS, time >> (32 - CNTR_TO_SECS_SH));
/* Enable the RTC again */
regmap_update_bits(bbnsm->regmap, BBNSM_CTRL, RTC_EN_MSK, RTC_EN);
return 0;
}
static int bbnsm_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct bbnsm_rtc *bbnsm = dev_get_drvdata(dev);
u32 bbnsm_events, bbnsm_ta;
regmap_read(bbnsm->regmap, BBNSM_TA, &bbnsm_ta);
rtc_time64_to_tm(bbnsm_ta, &alrm->time);
regmap_read(bbnsm->regmap, BBNSM_EVENTS, &bbnsm_events);
alrm->pending = (bbnsm_events & BBNSM_EVENT_TA) ? 1 : 0;
return 0;
}
static int bbnsm_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct bbnsm_rtc *bbnsm = dev_get_drvdata(dev);
/* enable the alarm event */
regmap_update_bits(bbnsm->regmap, BBNSM_CTRL, TA_EN_MSK, enable ? TA_EN : TA_DIS);
/* enable the alarm interrupt */
regmap_update_bits(bbnsm->regmap, BBNSM_INT_EN, TA_EN_MSK, enable ? TA_EN : TA_DIS);
return 0;
}
static int bbnsm_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct bbnsm_rtc *bbnsm = dev_get_drvdata(dev);
unsigned long time = rtc_tm_to_time64(&alrm->time);
/* disable the alarm */
regmap_update_bits(bbnsm->regmap, BBNSM_CTRL, TA_EN, TA_EN);
/* write the seconds to TA */
regmap_write(bbnsm->regmap, BBNSM_TA, time);
return bbnsm_rtc_alarm_irq_enable(dev, alrm->enabled);
}
static const struct rtc_class_ops bbnsm_rtc_ops = {
.read_time = bbnsm_rtc_read_time,
.set_time = bbnsm_rtc_set_time,
.read_alarm = bbnsm_rtc_read_alarm,
.set_alarm = bbnsm_rtc_set_alarm,
.alarm_irq_enable = bbnsm_rtc_alarm_irq_enable,
};
static irqreturn_t bbnsm_rtc_irq_handler(int irq, void *dev_id)
{
struct device *dev = dev_id;
struct bbnsm_rtc *bbnsm = dev_get_drvdata(dev);
u32 val;
regmap_read(bbnsm->regmap, BBNSM_EVENTS, &val);
if (val & BBNSM_EVENT_TA) {
bbnsm_rtc_alarm_irq_enable(dev, false);
/* clear the alarm event */
regmap_write_bits(bbnsm->regmap, BBNSM_EVENTS, TA_EN_MSK, BBNSM_EVENT_TA);
rtc_update_irq(bbnsm->rtc, 1, RTC_AF | RTC_IRQF);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int bbnsm_rtc_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct bbnsm_rtc *bbnsm;
int ret;
bbnsm = devm_kzalloc(&pdev->dev, sizeof(*bbnsm), GFP_KERNEL);
if (!bbnsm)
return -ENOMEM;
bbnsm->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(bbnsm->rtc))
return PTR_ERR(bbnsm->rtc);
bbnsm->regmap = syscon_node_to_regmap(np->parent);
if (IS_ERR(bbnsm->regmap)) {
dev_dbg(&pdev->dev, "bbnsm get regmap failed\n");
return PTR_ERR(bbnsm->regmap);
}
bbnsm->irq = platform_get_irq(pdev, 0);
if (bbnsm->irq < 0)
return bbnsm->irq;
platform_set_drvdata(pdev, bbnsm);
/* clear all the pending events */
regmap_write(bbnsm->regmap, BBNSM_EVENTS, 0x7A);
device_init_wakeup(&pdev->dev, true);
dev_pm_set_wake_irq(&pdev->dev, bbnsm->irq);
ret = devm_request_irq(&pdev->dev, bbnsm->irq, bbnsm_rtc_irq_handler,
IRQF_SHARED, "rtc alarm", &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "failed to request irq %d: %d\n",
bbnsm->irq, ret);
return ret;
}
bbnsm->rtc->ops = &bbnsm_rtc_ops;
bbnsm->rtc->range_max = U32_MAX;
return devm_rtc_register_device(bbnsm->rtc);
}
static const struct of_device_id bbnsm_dt_ids[] = {
{ .compatible = "nxp,imx93-bbnsm-rtc" },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, bbnsm_dt_ids);
static struct platform_driver bbnsm_rtc_driver = {
.driver = {
.name = "bbnsm_rtc",
.of_match_table = bbnsm_dt_ids,
},
.probe = bbnsm_rtc_probe,
};
module_platform_driver(bbnsm_rtc_driver);
MODULE_AUTHOR("Jacky Bai <[email protected]>");
MODULE_DESCRIPTION("NXP BBNSM RTC Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-nxp-bbnsm.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Microchip MPFS RTC driver
*
* Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
*
* Author: Daire McNamara <[email protected]>
* & Conor Dooley <[email protected]>
*/
#include "linux/bits.h"
#include "linux/iopoll.h"
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#define CONTROL_REG 0x00
#define MODE_REG 0x04
#define PRESCALER_REG 0x08
#define ALARM_LOWER_REG 0x0c
#define ALARM_UPPER_REG 0x10
#define COMPARE_LOWER_REG 0x14
#define COMPARE_UPPER_REG 0x18
#define DATETIME_LOWER_REG 0x20
#define DATETIME_UPPER_REG 0x24
#define CONTROL_RUNNING_BIT BIT(0)
#define CONTROL_START_BIT BIT(0)
#define CONTROL_STOP_BIT BIT(1)
#define CONTROL_ALARM_ON_BIT BIT(2)
#define CONTROL_ALARM_OFF_BIT BIT(3)
#define CONTROL_RESET_BIT BIT(4)
#define CONTROL_UPLOAD_BIT BIT(5)
#define CONTROL_DOWNLOAD_BIT BIT(6)
#define CONTROL_MATCH_BIT BIT(7)
#define CONTROL_WAKEUP_CLR_BIT BIT(8)
#define CONTROL_WAKEUP_SET_BIT BIT(9)
#define CONTROL_UPDATED_BIT BIT(10)
#define MODE_CLOCK_CALENDAR BIT(0)
#define MODE_WAKE_EN BIT(1)
#define MODE_WAKE_RESET BIT(2)
#define MODE_WAKE_CONTINUE BIT(3)
#define MAX_PRESCALER_COUNT GENMASK(25, 0)
#define DATETIME_UPPER_MASK GENMASK(29, 0)
#define ALARM_UPPER_MASK GENMASK(10, 0)
#define UPLOAD_TIMEOUT_US 50
struct mpfs_rtc_dev {
struct rtc_device *rtc;
void __iomem *base;
};
static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
{
u32 ctrl;
ctrl = readl(rtcdev->base + CONTROL_REG);
ctrl &= ~CONTROL_STOP_BIT;
ctrl |= CONTROL_START_BIT;
writel(ctrl, rtcdev->base + CONTROL_REG);
}
static void mpfs_rtc_clear_irq(struct mpfs_rtc_dev *rtcdev)
{
u32 val = readl(rtcdev->base + CONTROL_REG);
val &= ~(CONTROL_ALARM_ON_BIT | CONTROL_STOP_BIT);
val |= CONTROL_ALARM_OFF_BIT;
writel(val, rtcdev->base + CONTROL_REG);
/*
* Ensure that the posted write to the CONTROL_REG register completed before
* returning from this function. Not doing this may result in the interrupt
* only being cleared some time after this function returns.
*/
(void)readl(rtcdev->base + CONTROL_REG);
}
static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
{
struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
u64 time;
time = readl(rtcdev->base + DATETIME_LOWER_REG);
time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
rtc_time64_to_tm(time, tm);
return 0;
}
static int mpfs_rtc_settime(struct device *dev, struct rtc_time *tm)
{
struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
u32 ctrl, prog;
u64 time;
int ret;
time = rtc_tm_to_time64(tm);
writel((u32)time, rtcdev->base + DATETIME_LOWER_REG);
writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG);
ctrl = readl(rtcdev->base + CONTROL_REG);
ctrl &= ~CONTROL_STOP_BIT;
ctrl |= CONTROL_UPLOAD_BIT;
writel(ctrl, rtcdev->base + CONTROL_REG);
ret = read_poll_timeout(readl, prog, prog & CONTROL_UPLOAD_BIT, 0, UPLOAD_TIMEOUT_US,
false, rtcdev->base + CONTROL_REG);
if (ret) {
dev_err(dev, "timed out uploading time to rtc");
return ret;
}
mpfs_rtc_start(rtcdev);
return 0;
}
static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
u32 mode = readl(rtcdev->base + MODE_REG);
u64 time;
alrm->enabled = mode & MODE_WAKE_EN;
time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32;
time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK);
rtc_time64_to_tm(time, &alrm->time);
return 0;
}
static int mpfs_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
u32 mode, ctrl;
u64 time;
/* Disable the alarm before updating */
ctrl = readl(rtcdev->base + CONTROL_REG);
ctrl |= CONTROL_ALARM_OFF_BIT;
writel(ctrl, rtcdev->base + CONTROL_REG);
time = rtc_tm_to_time64(&alrm->time);
writel((u32)time, rtcdev->base + ALARM_LOWER_REG);
writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG);
/* Bypass compare register in alarm mode */
writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);
writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);
/* Configure the RTC to enable the alarm. */
ctrl = readl(rtcdev->base + CONTROL_REG);
mode = readl(rtcdev->base + MODE_REG);
if (alrm->enabled) {
mode = MODE_WAKE_EN | MODE_WAKE_CONTINUE;
/* Enable the alarm */
ctrl &= ~CONTROL_ALARM_OFF_BIT;
ctrl |= CONTROL_ALARM_ON_BIT;
}
ctrl &= ~CONTROL_STOP_BIT;
ctrl |= CONTROL_START_BIT;
writel(ctrl, rtcdev->base + CONTROL_REG);
writel(mode, rtcdev->base + MODE_REG);
return 0;
}
static int mpfs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
u32 ctrl;
ctrl = readl(rtcdev->base + CONTROL_REG);
ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT);
if (enabled)
ctrl |= CONTROL_ALARM_ON_BIT;
else
ctrl |= CONTROL_ALARM_OFF_BIT;
writel(ctrl, rtcdev->base + CONTROL_REG);
return 0;
}
static irqreturn_t mpfs_rtc_wakeup_irq_handler(int irq, void *dev)
{
struct mpfs_rtc_dev *rtcdev = dev;
mpfs_rtc_clear_irq(rtcdev);
rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static const struct rtc_class_ops mpfs_rtc_ops = {
.read_time = mpfs_rtc_readtime,
.set_time = mpfs_rtc_settime,
.read_alarm = mpfs_rtc_readalarm,
.set_alarm = mpfs_rtc_setalarm,
.alarm_irq_enable = mpfs_rtc_alarm_irq_enable,
};
static int mpfs_rtc_probe(struct platform_device *pdev)
{
struct mpfs_rtc_dev *rtcdev;
struct clk *clk;
unsigned long prescaler;
int wakeup_irq, ret;
rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
if (!rtcdev)
return -ENOMEM;
platform_set_drvdata(pdev, rtcdev);
rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtcdev->rtc))
return PTR_ERR(rtcdev->rtc);
rtcdev->rtc->ops = &mpfs_rtc_ops;
/* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
clk = devm_clk_get_enabled(&pdev->dev, "rtc");
if (IS_ERR(clk))
return PTR_ERR(clk);
rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtcdev->base)) {
dev_dbg(&pdev->dev, "invalid ioremap resources\n");
return PTR_ERR(rtcdev->base);
}
wakeup_irq = platform_get_irq(pdev, 0);
if (wakeup_irq <= 0) {
dev_dbg(&pdev->dev, "could not get wakeup irq\n");
return wakeup_irq;
}
ret = devm_request_irq(&pdev->dev, wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
dev_name(&pdev->dev), rtcdev);
if (ret) {
dev_dbg(&pdev->dev, "could not request wakeup irq\n");
return ret;
}
/* prescaler hardware adds 1 to reg value */
prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
if (prescaler > MAX_PRESCALER_COUNT) {
dev_dbg(&pdev->dev, "invalid prescaler %lu\n", prescaler);
return -EINVAL;
}
writel(prescaler, rtcdev->base + PRESCALER_REG);
dev_info(&pdev->dev, "prescaler set to: %lu\n", prescaler);
device_init_wakeup(&pdev->dev, true);
ret = dev_pm_set_wake_irq(&pdev->dev, wakeup_irq);
if (ret)
dev_err(&pdev->dev, "failed to enable irq wake\n");
return devm_rtc_register_device(rtcdev->rtc);
}
static void mpfs_rtc_remove(struct platform_device *pdev)
{
dev_pm_clear_wake_irq(&pdev->dev);
}
static const struct of_device_id mpfs_rtc_of_match[] = {
{ .compatible = "microchip,mpfs-rtc" },
{ }
};
MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
static struct platform_driver mpfs_rtc_driver = {
.probe = mpfs_rtc_probe,
.remove_new = mpfs_rtc_remove,
.driver = {
.name = "mpfs_rtc",
.of_match_table = mpfs_rtc_of_match,
},
};
module_platform_driver(mpfs_rtc_driver);
MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
MODULE_AUTHOR("Daire McNamara <[email protected]>");
MODULE_AUTHOR("Conor Dooley <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-mpfs.c |
// SPDX-License-Identifier: GPL-2.0-only
/* drivers/rtc/rtc-max6902.c
*
* Copyright (C) 2006 8D Technologies inc.
* Copyright (C) 2004 Compulab Ltd.
*
* Driver for MAX6902 spi RTC
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
#define MAX6902_REG_SECONDS 0x01
#define MAX6902_REG_MINUTES 0x03
#define MAX6902_REG_HOURS 0x05
#define MAX6902_REG_DATE 0x07
#define MAX6902_REG_MONTH 0x09
#define MAX6902_REG_DAY 0x0B
#define MAX6902_REG_YEAR 0x0D
#define MAX6902_REG_CONTROL 0x0F
#define MAX6902_REG_CENTURY 0x13
static int max6902_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* MSB must be '0' to write */
buf[0] = address & 0x7f;
buf[1] = data;
return spi_write_then_read(spi, buf, 2, NULL, 0);
}
static int max6902_get_reg(struct device *dev, unsigned char address,
unsigned char *data)
{
struct spi_device *spi = to_spi_device(dev);
/* Set MSB to indicate read */
*data = address | 0x80;
return spi_write_then_read(spi, data, 1, data, 1);
}
static int max6902_read_time(struct device *dev, struct rtc_time *dt)
{
int err, century;
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[8];
buf[0] = 0xbf; /* Burst read */
err = spi_write_then_read(spi, buf, 1, buf, 8);
if (err != 0)
return err;
/* The chip sends data in this order:
* Seconds, Minutes, Hours, Date, Month, Day, Year */
dt->tm_sec = bcd2bin(buf[0]);
dt->tm_min = bcd2bin(buf[1]);
dt->tm_hour = bcd2bin(buf[2]);
dt->tm_mday = bcd2bin(buf[3]);
dt->tm_mon = bcd2bin(buf[4]) - 1;
dt->tm_wday = bcd2bin(buf[5]);
dt->tm_year = bcd2bin(buf[6]);
/* Read century */
err = max6902_get_reg(dev, MAX6902_REG_CENTURY, &buf[0]);
if (err != 0)
return err;
century = bcd2bin(buf[0]) * 100;
dt->tm_year += century;
dt->tm_year -= 1900;
return 0;
}
static int max6902_set_time(struct device *dev, struct rtc_time *dt)
{
dt->tm_year = dt->tm_year + 1900;
/* Remove write protection */
max6902_set_reg(dev, MAX6902_REG_CONTROL, 0);
max6902_set_reg(dev, MAX6902_REG_SECONDS, bin2bcd(dt->tm_sec));
max6902_set_reg(dev, MAX6902_REG_MINUTES, bin2bcd(dt->tm_min));
max6902_set_reg(dev, MAX6902_REG_HOURS, bin2bcd(dt->tm_hour));
max6902_set_reg(dev, MAX6902_REG_DATE, bin2bcd(dt->tm_mday));
max6902_set_reg(dev, MAX6902_REG_MONTH, bin2bcd(dt->tm_mon + 1));
max6902_set_reg(dev, MAX6902_REG_DAY, bin2bcd(dt->tm_wday));
max6902_set_reg(dev, MAX6902_REG_YEAR, bin2bcd(dt->tm_year % 100));
max6902_set_reg(dev, MAX6902_REG_CENTURY, bin2bcd(dt->tm_year / 100));
/* Compulab used a delay here. However, the datasheet
* does not mention a delay being required anywhere... */
/* delay(2000); */
/* Write protect */
max6902_set_reg(dev, MAX6902_REG_CONTROL, 0x80);
return 0;
}
static const struct rtc_class_ops max6902_rtc_ops = {
.read_time = max6902_read_time,
.set_time = max6902_set_time,
};
static int max6902_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
unsigned char tmp;
int res;
spi->mode = SPI_MODE_3;
spi->bits_per_word = 8;
spi_setup(spi);
res = max6902_get_reg(&spi->dev, MAX6902_REG_SECONDS, &tmp);
if (res != 0)
return res;
rtc = devm_rtc_device_register(&spi->dev, "max6902",
&max6902_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
spi_set_drvdata(spi, rtc);
return 0;
}
static struct spi_driver max6902_driver = {
.driver = {
.name = "rtc-max6902",
},
.probe = max6902_probe,
};
module_spi_driver(max6902_driver);
MODULE_DESCRIPTION("max6902 spi RTC driver");
MODULE_AUTHOR("Raphael Assenat");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rtc-max6902");
| linux-master | drivers/rtc/rtc-max6902.c |
// SPDX-License-Identifier: GPL-2.0
/*
* pcap rtc code for Motorola EZX phones
*
* Copyright (c) 2008 guiming zhuo <[email protected]>
* Copyright (c) 2009 Daniel Ribeiro <[email protected]>
*
* Based on Motorola's rtc.c Copyright (c) 2003-2005 Motorola
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/mfd/ezx-pcap.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
struct pcap_rtc {
struct pcap_chip *pcap;
struct rtc_device *rtc;
};
static irqreturn_t pcap_rtc_irq(int irq, void *_pcap_rtc)
{
struct pcap_rtc *pcap_rtc = _pcap_rtc;
unsigned long rtc_events;
if (irq == pcap_to_irq(pcap_rtc->pcap, PCAP_IRQ_1HZ))
rtc_events = RTC_IRQF | RTC_UF;
else if (irq == pcap_to_irq(pcap_rtc->pcap, PCAP_IRQ_TODA))
rtc_events = RTC_IRQF | RTC_AF;
else
rtc_events = 0;
rtc_update_irq(pcap_rtc->rtc, 1, rtc_events);
return IRQ_HANDLED;
}
static int pcap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
unsigned long secs;
u32 tod; /* time of day, seconds since midnight */
u32 days; /* days since 1/1/1970 */
ezx_pcap_read(pcap_rtc->pcap, PCAP_REG_RTC_TODA, &tod);
secs = tod & PCAP_RTC_TOD_MASK;
ezx_pcap_read(pcap_rtc->pcap, PCAP_REG_RTC_DAYA, &days);
secs += (days & PCAP_RTC_DAY_MASK) * SEC_PER_DAY;
rtc_time64_to_tm(secs, tm);
return 0;
}
static int pcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
unsigned long secs = rtc_tm_to_time64(&alrm->time);
u32 tod, days;
tod = secs % SEC_PER_DAY;
ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_TODA, tod);
days = secs / SEC_PER_DAY;
ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_DAYA, days);
return 0;
}
static int pcap_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
unsigned long secs;
u32 tod, days;
ezx_pcap_read(pcap_rtc->pcap, PCAP_REG_RTC_TOD, &tod);
secs = tod & PCAP_RTC_TOD_MASK;
ezx_pcap_read(pcap_rtc->pcap, PCAP_REG_RTC_DAY, &days);
secs += (days & PCAP_RTC_DAY_MASK) * SEC_PER_DAY;
rtc_time64_to_tm(secs, tm);
return 0;
}
static int pcap_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
unsigned long secs = rtc_tm_to_time64(tm);
u32 tod, days;
tod = secs % SEC_PER_DAY;
ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_TOD, tod);
days = secs / SEC_PER_DAY;
ezx_pcap_write(pcap_rtc->pcap, PCAP_REG_RTC_DAY, days);
return 0;
}
static int pcap_rtc_irq_enable(struct device *dev, int pirq, unsigned int en)
{
struct pcap_rtc *pcap_rtc = dev_get_drvdata(dev);
if (en)
enable_irq(pcap_to_irq(pcap_rtc->pcap, pirq));
else
disable_irq(pcap_to_irq(pcap_rtc->pcap, pirq));
return 0;
}
static int pcap_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
{
return pcap_rtc_irq_enable(dev, PCAP_IRQ_TODA, en);
}
static const struct rtc_class_ops pcap_rtc_ops = {
.read_time = pcap_rtc_read_time,
.set_time = pcap_rtc_set_time,
.read_alarm = pcap_rtc_read_alarm,
.set_alarm = pcap_rtc_set_alarm,
.alarm_irq_enable = pcap_rtc_alarm_irq_enable,
};
static int __init pcap_rtc_probe(struct platform_device *pdev)
{
struct pcap_rtc *pcap_rtc;
int timer_irq, alarm_irq;
int err = -ENOMEM;
pcap_rtc = devm_kzalloc(&pdev->dev, sizeof(struct pcap_rtc),
GFP_KERNEL);
if (!pcap_rtc)
return err;
pcap_rtc->pcap = dev_get_drvdata(pdev->dev.parent);
platform_set_drvdata(pdev, pcap_rtc);
pcap_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pcap_rtc->rtc))
return PTR_ERR(pcap_rtc->rtc);
pcap_rtc->rtc->ops = &pcap_rtc_ops;
pcap_rtc->rtc->range_max = (1 << 14) * 86400ULL - 1;
timer_irq = pcap_to_irq(pcap_rtc->pcap, PCAP_IRQ_1HZ);
alarm_irq = pcap_to_irq(pcap_rtc->pcap, PCAP_IRQ_TODA);
err = devm_request_irq(&pdev->dev, timer_irq, pcap_rtc_irq, 0,
"RTC Timer", pcap_rtc);
if (err)
return err;
err = devm_request_irq(&pdev->dev, alarm_irq, pcap_rtc_irq, 0,
"RTC Alarm", pcap_rtc);
if (err)
return err;
return devm_rtc_register_device(pcap_rtc->rtc);
}
static int __exit pcap_rtc_remove(struct platform_device *pdev)
{
return 0;
}
static struct platform_driver pcap_rtc_driver = {
.remove = __exit_p(pcap_rtc_remove),
.driver = {
.name = "pcap-rtc",
},
};
module_platform_driver_probe(pcap_rtc_driver, pcap_rtc_probe);
MODULE_DESCRIPTION("Motorola pcap rtc driver");
MODULE_AUTHOR("guiming zhuo <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pcap.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/rtc/rtc-pcf8583.c
*
* Copyright (C) 2000 Russell King
* Copyright (C) 2008 Wolfram Sang & Juergen Beisert, Pengutronix
*
* Driver for PCF8583 RTC & RAM chip
*
* Converted to the generic RTC susbsystem by G. Liakhovetski (2006)
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/bcd.h>
struct rtc_mem {
unsigned int loc;
unsigned int nr;
unsigned char *data;
};
struct pcf8583 {
struct rtc_device *rtc;
unsigned char ctrl;
};
#define CTRL_STOP 0x80
#define CTRL_HOLD 0x40
#define CTRL_32KHZ 0x00
#define CTRL_MASK 0x08
#define CTRL_ALARMEN 0x04
#define CTRL_ALARM 0x02
#define CTRL_TIMER 0x01
static struct i2c_driver pcf8583_driver;
#define get_ctrl(x) ((struct pcf8583 *)i2c_get_clientdata(x))->ctrl
#define set_ctrl(x, v) get_ctrl(x) = v
#define CMOS_YEAR (64 + 128)
#define CMOS_CHECKSUM (63)
static int pcf8583_get_datetime(struct i2c_client *client, struct rtc_time *dt)
{
unsigned char buf[8], addr[1] = { 1 };
struct i2c_msg msgs[2] = {
{
.addr = client->addr,
.flags = 0,
.len = 1,
.buf = addr,
}, {
.addr = client->addr,
.flags = I2C_M_RD,
.len = 6,
.buf = buf,
}
};
int ret;
memset(buf, 0, sizeof(buf));
ret = i2c_transfer(client->adapter, msgs, 2);
if (ret == 2) {
dt->tm_year = buf[4] >> 6;
dt->tm_wday = buf[5] >> 5;
buf[4] &= 0x3f;
buf[5] &= 0x1f;
dt->tm_sec = bcd2bin(buf[1]);
dt->tm_min = bcd2bin(buf[2]);
dt->tm_hour = bcd2bin(buf[3]);
dt->tm_mday = bcd2bin(buf[4]);
dt->tm_mon = bcd2bin(buf[5]) - 1;
}
return ret == 2 ? 0 : -EIO;
}
static int pcf8583_set_datetime(struct i2c_client *client, struct rtc_time *dt, int datetoo)
{
unsigned char buf[8];
int ret, len = 6;
buf[0] = 0;
buf[1] = get_ctrl(client) | 0x80;
buf[2] = 0;
buf[3] = bin2bcd(dt->tm_sec);
buf[4] = bin2bcd(dt->tm_min);
buf[5] = bin2bcd(dt->tm_hour);
if (datetoo) {
len = 8;
buf[6] = bin2bcd(dt->tm_mday) | (dt->tm_year << 6);
buf[7] = bin2bcd(dt->tm_mon + 1) | (dt->tm_wday << 5);
}
ret = i2c_master_send(client, (char *)buf, len);
if (ret != len)
return -EIO;
buf[1] = get_ctrl(client);
ret = i2c_master_send(client, (char *)buf, 2);
return ret == 2 ? 0 : -EIO;
}
static int pcf8583_get_ctrl(struct i2c_client *client, unsigned char *ctrl)
{
*ctrl = get_ctrl(client);
return 0;
}
static int pcf8583_set_ctrl(struct i2c_client *client, unsigned char *ctrl)
{
unsigned char buf[2];
buf[0] = 0;
buf[1] = *ctrl;
set_ctrl(client, *ctrl);
return i2c_master_send(client, (char *)buf, 2);
}
static int pcf8583_read_mem(struct i2c_client *client, struct rtc_mem *mem)
{
unsigned char addr[1];
struct i2c_msg msgs[2] = {
{
.addr = client->addr,
.flags = 0,
.len = 1,
.buf = addr,
}, {
.addr = client->addr,
.flags = I2C_M_RD,
.len = mem->nr,
.buf = mem->data,
}
};
if (mem->loc < 8)
return -EINVAL;
addr[0] = mem->loc;
return i2c_transfer(client->adapter, msgs, 2) == 2 ? 0 : -EIO;
}
static int pcf8583_write_mem(struct i2c_client *client, struct rtc_mem *mem)
{
unsigned char buf[9];
int ret;
if (mem->loc < 8 || mem->nr > 8)
return -EINVAL;
buf[0] = mem->loc;
memcpy(buf + 1, mem->data, mem->nr);
ret = i2c_master_send(client, buf, mem->nr + 1);
return ret == mem->nr + 1 ? 0 : -EIO;
}
static int pcf8583_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char ctrl, year[2];
struct rtc_mem mem = {
.loc = CMOS_YEAR,
.nr = sizeof(year),
.data = year
};
int real_year, year_offset, err;
/*
* Ensure that the RTC is running.
*/
pcf8583_get_ctrl(client, &ctrl);
if (ctrl & (CTRL_STOP | CTRL_HOLD)) {
unsigned char new_ctrl = ctrl & ~(CTRL_STOP | CTRL_HOLD);
dev_warn(dev, "resetting control %02x -> %02x\n",
ctrl, new_ctrl);
err = pcf8583_set_ctrl(client, &new_ctrl);
if (err < 0)
return err;
}
if (pcf8583_get_datetime(client, tm) ||
pcf8583_read_mem(client, &mem))
return -EIO;
real_year = year[0];
/*
* The RTC year holds the LSB two bits of the current
* year, which should reflect the LSB two bits of the
* CMOS copy of the year. Any difference indicates
* that we have to correct the CMOS version.
*/
year_offset = tm->tm_year - (real_year & 3);
if (year_offset < 0)
/*
* RTC year wrapped. Adjust it appropriately.
*/
year_offset += 4;
tm->tm_year = (real_year + year_offset + year[1] * 100) - 1900;
return 0;
}
static int pcf8583_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char year[2], chk;
struct rtc_mem cmos_year = {
.loc = CMOS_YEAR,
.nr = sizeof(year),
.data = year
};
struct rtc_mem cmos_check = {
.loc = CMOS_CHECKSUM,
.nr = 1,
.data = &chk
};
unsigned int proper_year = tm->tm_year + 1900;
int ret;
/*
* The RTC's own 2-bit year must reflect the least
* significant two bits of the CMOS year.
*/
ret = pcf8583_set_datetime(client, tm, 1);
if (ret)
return ret;
ret = pcf8583_read_mem(client, &cmos_check);
if (ret)
return ret;
ret = pcf8583_read_mem(client, &cmos_year);
if (ret)
return ret;
chk -= year[1] + year[0];
year[1] = proper_year / 100;
year[0] = proper_year % 100;
chk += year[1] + year[0];
ret = pcf8583_write_mem(client, &cmos_year);
if (ret)
return ret;
ret = pcf8583_write_mem(client, &cmos_check);
return ret;
}
static const struct rtc_class_ops pcf8583_rtc_ops = {
.read_time = pcf8583_rtc_read_time,
.set_time = pcf8583_rtc_set_time,
};
static int pcf8583_probe(struct i2c_client *client)
{
struct pcf8583 *pcf8583;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
pcf8583 = devm_kzalloc(&client->dev, sizeof(struct pcf8583),
GFP_KERNEL);
if (!pcf8583)
return -ENOMEM;
i2c_set_clientdata(client, pcf8583);
pcf8583->rtc = devm_rtc_device_register(&client->dev,
pcf8583_driver.driver.name,
&pcf8583_rtc_ops, THIS_MODULE);
return PTR_ERR_OR_ZERO(pcf8583->rtc);
}
static const struct i2c_device_id pcf8583_id[] = {
{ "pcf8583", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcf8583_id);
static struct i2c_driver pcf8583_driver = {
.driver = {
.name = "pcf8583",
},
.probe = pcf8583_probe,
.id_table = pcf8583_id,
};
module_i2c_driver(pcf8583_driver);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("PCF8583 I2C RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-pcf8583.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* RTC driver for Maxim MAX8907
*
* Copyright (c) 2011-2012, NVIDIA Corporation.
*
* Based on drivers/rtc/rtc-max8925.c,
* Copyright (C) 2009-2010 Marvell International Ltd.
*/
#include <linux/bcd.h>
#include <linux/mfd/max8907.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/slab.h>
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_DATE,
RTC_MONTH,
RTC_YEAR1,
RTC_YEAR2,
};
#define TIME_NUM 8
#define ALARM_1SEC (1 << 7)
#define HOUR_12 (1 << 7)
#define HOUR_AM_PM (1 << 5)
#define ALARM0_IRQ (1 << 3)
#define ALARM1_IRQ (1 << 2)
#define ALARM0_STATUS (1 << 2)
#define ALARM1_STATUS (1 << 1)
struct max8907_rtc {
struct max8907 *max8907;
struct regmap *regmap;
struct rtc_device *rtc_dev;
int irq;
};
static irqreturn_t max8907_irq_handler(int irq, void *data)
{
struct max8907_rtc *rtc = data;
regmap_write(rtc->regmap, MAX8907_REG_ALARM0_CNTL, 0);
rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
return IRQ_HANDLED;
}
static void regs_to_tm(u8 *regs, struct rtc_time *tm)
{
tm->tm_year = bcd2bin(regs[RTC_YEAR2]) * 100 +
bcd2bin(regs[RTC_YEAR1]) - 1900;
tm->tm_mon = bcd2bin(regs[RTC_MONTH] & 0x1f) - 1;
tm->tm_mday = bcd2bin(regs[RTC_DATE] & 0x3f);
tm->tm_wday = (regs[RTC_WEEKDAY] & 0x07);
if (regs[RTC_HOUR] & HOUR_12) {
tm->tm_hour = bcd2bin(regs[RTC_HOUR] & 0x01f);
if (tm->tm_hour == 12)
tm->tm_hour = 0;
if (regs[RTC_HOUR] & HOUR_AM_PM)
tm->tm_hour += 12;
} else {
tm->tm_hour = bcd2bin(regs[RTC_HOUR] & 0x03f);
}
tm->tm_min = bcd2bin(regs[RTC_MIN] & 0x7f);
tm->tm_sec = bcd2bin(regs[RTC_SEC] & 0x7f);
}
static void tm_to_regs(struct rtc_time *tm, u8 *regs)
{
u8 high, low;
high = (tm->tm_year + 1900) / 100;
low = tm->tm_year % 100;
regs[RTC_YEAR2] = bin2bcd(high);
regs[RTC_YEAR1] = bin2bcd(low);
regs[RTC_MONTH] = bin2bcd(tm->tm_mon + 1);
regs[RTC_DATE] = bin2bcd(tm->tm_mday);
regs[RTC_WEEKDAY] = tm->tm_wday;
regs[RTC_HOUR] = bin2bcd(tm->tm_hour);
regs[RTC_MIN] = bin2bcd(tm->tm_min);
regs[RTC_SEC] = bin2bcd(tm->tm_sec);
}
static int max8907_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct max8907_rtc *rtc = dev_get_drvdata(dev);
u8 regs[TIME_NUM];
int ret;
ret = regmap_bulk_read(rtc->regmap, MAX8907_REG_RTC_SEC, regs,
TIME_NUM);
if (ret < 0)
return ret;
regs_to_tm(regs, tm);
return 0;
}
static int max8907_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct max8907_rtc *rtc = dev_get_drvdata(dev);
u8 regs[TIME_NUM];
tm_to_regs(tm, regs);
return regmap_bulk_write(rtc->regmap, MAX8907_REG_RTC_SEC, regs,
TIME_NUM);
}
static int max8907_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max8907_rtc *rtc = dev_get_drvdata(dev);
u8 regs[TIME_NUM];
unsigned int val;
int ret;
ret = regmap_bulk_read(rtc->regmap, MAX8907_REG_ALARM0_SEC, regs,
TIME_NUM);
if (ret < 0)
return ret;
regs_to_tm(regs, &alrm->time);
ret = regmap_read(rtc->regmap, MAX8907_REG_ALARM0_CNTL, &val);
if (ret < 0)
return ret;
alrm->enabled = !!(val & 0x7f);
return 0;
}
static int max8907_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct max8907_rtc *rtc = dev_get_drvdata(dev);
u8 regs[TIME_NUM];
int ret;
tm_to_regs(&alrm->time, regs);
/* Disable alarm while we update the target time */
ret = regmap_write(rtc->regmap, MAX8907_REG_ALARM0_CNTL, 0);
if (ret < 0)
return ret;
ret = regmap_bulk_write(rtc->regmap, MAX8907_REG_ALARM0_SEC, regs,
TIME_NUM);
if (ret < 0)
return ret;
if (alrm->enabled)
ret = regmap_write(rtc->regmap, MAX8907_REG_ALARM0_CNTL, 0x77);
return ret;
}
static const struct rtc_class_ops max8907_rtc_ops = {
.read_time = max8907_rtc_read_time,
.set_time = max8907_rtc_set_time,
.read_alarm = max8907_rtc_read_alarm,
.set_alarm = max8907_rtc_set_alarm,
};
static int max8907_rtc_probe(struct platform_device *pdev)
{
struct max8907 *max8907 = dev_get_drvdata(pdev->dev.parent);
struct max8907_rtc *rtc;
int ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
platform_set_drvdata(pdev, rtc);
rtc->max8907 = max8907;
rtc->regmap = max8907->regmap_rtc;
rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "max8907-rtc",
&max8907_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc->rtc_dev)) {
ret = PTR_ERR(rtc->rtc_dev);
dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
return ret;
}
rtc->irq = regmap_irq_get_virq(max8907->irqc_rtc,
MAX8907_IRQ_RTC_ALARM0);
if (rtc->irq < 0)
return rtc->irq;
ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
max8907_irq_handler,
IRQF_ONESHOT, "max8907-alarm0", rtc);
if (ret < 0)
dev_err(&pdev->dev, "Failed to request IRQ%d: %d\n",
rtc->irq, ret);
return ret;
}
static struct platform_driver max8907_rtc_driver = {
.driver = {
.name = "max8907-rtc",
},
.probe = max8907_rtc_probe,
};
module_platform_driver(max8907_rtc_driver);
MODULE_DESCRIPTION("Maxim MAX8907 RTC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-max8907.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* rtc-fm3130.c - RTC driver for Ramtron FM3130 I2C chip.
*
* Copyright (C) 2008 Sergey Lapin
* Based on ds1307 driver by James Chapman and David Brownell
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#define FM3130_RTC_CONTROL (0x0)
#define FM3130_CAL_CONTROL (0x1)
#define FM3130_RTC_SECONDS (0x2)
#define FM3130_RTC_MINUTES (0x3)
#define FM3130_RTC_HOURS (0x4)
#define FM3130_RTC_DAY (0x5)
#define FM3130_RTC_DATE (0x6)
#define FM3130_RTC_MONTHS (0x7)
#define FM3130_RTC_YEARS (0x8)
#define FM3130_ALARM_SECONDS (0x9)
#define FM3130_ALARM_MINUTES (0xa)
#define FM3130_ALARM_HOURS (0xb)
#define FM3130_ALARM_DATE (0xc)
#define FM3130_ALARM_MONTHS (0xd)
#define FM3130_ALARM_WP_CONTROL (0xe)
#define FM3130_CAL_CONTROL_BIT_nOSCEN (1 << 7) /* Osciallator enabled */
#define FM3130_RTC_CONTROL_BIT_LB (1 << 7) /* Low battery */
#define FM3130_RTC_CONTROL_BIT_AF (1 << 6) /* Alarm flag */
#define FM3130_RTC_CONTROL_BIT_CF (1 << 5) /* Century overflow */
#define FM3130_RTC_CONTROL_BIT_POR (1 << 4) /* Power on reset */
#define FM3130_RTC_CONTROL_BIT_AEN (1 << 3) /* Alarm enable */
#define FM3130_RTC_CONTROL_BIT_CAL (1 << 2) /* Calibration mode */
#define FM3130_RTC_CONTROL_BIT_WRITE (1 << 1) /* W=1 -> write mode W=0 normal */
#define FM3130_RTC_CONTROL_BIT_READ (1 << 0) /* R=1 -> read mode R=0 normal */
#define FM3130_CLOCK_REGS 7
#define FM3130_ALARM_REGS 5
struct fm3130 {
u8 reg_addr_time;
u8 reg_addr_alarm;
u8 regs[15];
struct i2c_msg msg[4];
struct i2c_client *client;
struct rtc_device *rtc;
int alarm_valid;
int data_valid;
};
static const struct i2c_device_id fm3130_id[] = {
{ "fm3130", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, fm3130_id);
#define FM3130_MODE_NORMAL 0
#define FM3130_MODE_WRITE 1
#define FM3130_MODE_READ 2
static void fm3130_rtc_mode(struct device *dev, int mode)
{
struct fm3130 *fm3130 = dev_get_drvdata(dev);
fm3130->regs[FM3130_RTC_CONTROL] =
i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
switch (mode) {
case FM3130_MODE_NORMAL:
fm3130->regs[FM3130_RTC_CONTROL] &=
~(FM3130_RTC_CONTROL_BIT_WRITE |
FM3130_RTC_CONTROL_BIT_READ);
break;
case FM3130_MODE_WRITE:
fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_WRITE;
break;
case FM3130_MODE_READ:
fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_READ;
break;
default:
dev_dbg(dev, "invalid mode %d\n", mode);
break;
}
i2c_smbus_write_byte_data(fm3130->client,
FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL]);
}
static int fm3130_get_time(struct device *dev, struct rtc_time *t)
{
struct fm3130 *fm3130 = dev_get_drvdata(dev);
int tmp;
if (!fm3130->data_valid) {
/* We have invalid data in RTC, probably due
to battery faults or other problems. Return EIO
for now, it will allow us to set data later instead
of error during probing which disables device */
return -EIO;
}
fm3130_rtc_mode(dev, FM3130_MODE_READ);
/* read the RTC date and time registers all at once */
tmp = i2c_transfer(fm3130->client->adapter, fm3130->msg, 2);
if (tmp != 2) {
dev_err(dev, "%s error %d\n", "read", tmp);
return -EIO;
}
fm3130_rtc_mode(dev, FM3130_MODE_NORMAL);
dev_dbg(dev, "%s: %15ph\n", "read", fm3130->regs);
t->tm_sec = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
t->tm_min = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
tmp = fm3130->regs[FM3130_RTC_HOURS] & 0x3f;
t->tm_hour = bcd2bin(tmp);
t->tm_wday = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x07) - 1;
t->tm_mday = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
tmp = fm3130->regs[FM3130_RTC_MONTHS] & 0x1f;
t->tm_mon = bcd2bin(tmp) - 1;
/* assume 20YY not 19YY, and ignore CF bit */
t->tm_year = bcd2bin(fm3130->regs[FM3130_RTC_YEARS]) + 100;
dev_dbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"read", t->tm_sec, t->tm_min,
t->tm_hour, t->tm_mday,
t->tm_mon, t->tm_year, t->tm_wday);
return 0;
}
static int fm3130_set_time(struct device *dev, struct rtc_time *t)
{
struct fm3130 *fm3130 = dev_get_drvdata(dev);
int tmp, i;
u8 *buf = fm3130->regs;
dev_dbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"write", t->tm_sec, t->tm_min,
t->tm_hour, t->tm_mday,
t->tm_mon, t->tm_year, t->tm_wday);
/* first register addr */
buf[FM3130_RTC_SECONDS] = bin2bcd(t->tm_sec);
buf[FM3130_RTC_MINUTES] = bin2bcd(t->tm_min);
buf[FM3130_RTC_HOURS] = bin2bcd(t->tm_hour);
buf[FM3130_RTC_DAY] = bin2bcd(t->tm_wday + 1);
buf[FM3130_RTC_DATE] = bin2bcd(t->tm_mday);
buf[FM3130_RTC_MONTHS] = bin2bcd(t->tm_mon + 1);
/* assume 20YY not 19YY */
tmp = t->tm_year - 100;
buf[FM3130_RTC_YEARS] = bin2bcd(tmp);
dev_dbg(dev, "%s: %15ph\n", "write", buf);
fm3130_rtc_mode(dev, FM3130_MODE_WRITE);
/* Writing time registers, we don't support multibyte transfers */
for (i = 0; i < FM3130_CLOCK_REGS; i++) {
i2c_smbus_write_byte_data(fm3130->client,
FM3130_RTC_SECONDS + i,
fm3130->regs[FM3130_RTC_SECONDS + i]);
}
fm3130_rtc_mode(dev, FM3130_MODE_NORMAL);
/* We assume here that data are valid once written */
if (!fm3130->data_valid)
fm3130->data_valid = 1;
return 0;
}
static int fm3130_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct fm3130 *fm3130 = dev_get_drvdata(dev);
int tmp;
struct rtc_time *tm = &alrm->time;
if (!fm3130->alarm_valid) {
/*
* We have invalid alarm in RTC, probably due to battery faults
* or other problems. Return EIO for now, it will allow us to
* set alarm value later instead of error during probing which
* disables device
*/
return -EIO;
}
/* read the RTC alarm registers all at once */
tmp = i2c_transfer(fm3130->client->adapter, &fm3130->msg[2], 2);
if (tmp != 2) {
dev_err(dev, "%s error %d\n", "read", tmp);
return -EIO;
}
dev_dbg(dev, "alarm read %02x %02x %02x %02x %02x\n",
fm3130->regs[FM3130_ALARM_SECONDS],
fm3130->regs[FM3130_ALARM_MINUTES],
fm3130->regs[FM3130_ALARM_HOURS],
fm3130->regs[FM3130_ALARM_DATE],
fm3130->regs[FM3130_ALARM_MONTHS]);
tm->tm_sec = bcd2bin(fm3130->regs[FM3130_ALARM_SECONDS] & 0x7F);
tm->tm_min = bcd2bin(fm3130->regs[FM3130_ALARM_MINUTES] & 0x7F);
tm->tm_hour = bcd2bin(fm3130->regs[FM3130_ALARM_HOURS] & 0x3F);
tm->tm_mday = bcd2bin(fm3130->regs[FM3130_ALARM_DATE] & 0x3F);
tm->tm_mon = bcd2bin(fm3130->regs[FM3130_ALARM_MONTHS] & 0x1F);
if (tm->tm_mon > 0)
tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
dev_dbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"read alarm", tm->tm_sec, tm->tm_min,
tm->tm_hour, tm->tm_mday,
tm->tm_mon, tm->tm_year, tm->tm_wday);
/* check if alarm enabled */
fm3130->regs[FM3130_RTC_CONTROL] =
i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
if ((fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AEN) &&
(~fm3130->regs[FM3130_RTC_CONTROL] &
FM3130_RTC_CONTROL_BIT_CAL)) {
alrm->enabled = 1;
}
return 0;
}
static int fm3130_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct fm3130 *fm3130 = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
int i;
dev_dbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"write alarm", tm->tm_sec, tm->tm_min,
tm->tm_hour, tm->tm_mday,
tm->tm_mon, tm->tm_year, tm->tm_wday);
fm3130->regs[FM3130_ALARM_SECONDS] =
(tm->tm_sec != -1) ? bin2bcd(tm->tm_sec) : 0x80;
fm3130->regs[FM3130_ALARM_MINUTES] =
(tm->tm_min != -1) ? bin2bcd(tm->tm_min) : 0x80;
fm3130->regs[FM3130_ALARM_HOURS] =
(tm->tm_hour != -1) ? bin2bcd(tm->tm_hour) : 0x80;
fm3130->regs[FM3130_ALARM_DATE] =
(tm->tm_mday != -1) ? bin2bcd(tm->tm_mday) : 0x80;
fm3130->regs[FM3130_ALARM_MONTHS] =
(tm->tm_mon != -1) ? bin2bcd(tm->tm_mon + 1) : 0x80;
dev_dbg(dev, "alarm write %02x %02x %02x %02x %02x\n",
fm3130->regs[FM3130_ALARM_SECONDS],
fm3130->regs[FM3130_ALARM_MINUTES],
fm3130->regs[FM3130_ALARM_HOURS],
fm3130->regs[FM3130_ALARM_DATE],
fm3130->regs[FM3130_ALARM_MONTHS]);
/* Writing time registers, we don't support multibyte transfers */
for (i = 0; i < FM3130_ALARM_REGS; i++) {
i2c_smbus_write_byte_data(fm3130->client,
FM3130_ALARM_SECONDS + i,
fm3130->regs[FM3130_ALARM_SECONDS + i]);
}
fm3130->regs[FM3130_RTC_CONTROL] =
i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
/* enable or disable alarm */
if (alrm->enabled) {
i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
(fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_CAL)) |
FM3130_RTC_CONTROL_BIT_AEN);
} else {
i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_CAL) &
~(FM3130_RTC_CONTROL_BIT_AEN));
}
/* We assume here that data is valid once written */
if (!fm3130->alarm_valid)
fm3130->alarm_valid = 1;
return 0;
}
static int fm3130_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct fm3130 *fm3130 = dev_get_drvdata(dev);
int ret = 0;
fm3130->regs[FM3130_RTC_CONTROL] =
i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
dev_dbg(dev, "alarm_irq_enable: enable=%d, FM3130_RTC_CONTROL=%02x\n",
enabled, fm3130->regs[FM3130_RTC_CONTROL]);
switch (enabled) {
case 0: /* alarm off */
ret = i2c_smbus_write_byte_data(fm3130->client,
FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_CAL) &
~(FM3130_RTC_CONTROL_BIT_AEN));
break;
case 1: /* alarm on */
ret = i2c_smbus_write_byte_data(fm3130->client,
FM3130_RTC_CONTROL, (fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_CAL)) |
FM3130_RTC_CONTROL_BIT_AEN);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static const struct rtc_class_ops fm3130_rtc_ops = {
.read_time = fm3130_get_time,
.set_time = fm3130_set_time,
.read_alarm = fm3130_read_alarm,
.set_alarm = fm3130_set_alarm,
.alarm_irq_enable = fm3130_alarm_irq_enable,
};
static struct i2c_driver fm3130_driver;
static int fm3130_probe(struct i2c_client *client)
{
struct fm3130 *fm3130;
int err = -ENODEV;
int tmp;
struct i2c_adapter *adapter = client->adapter;
if (!i2c_check_functionality(adapter,
I2C_FUNC_I2C | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
return -EIO;
fm3130 = devm_kzalloc(&client->dev, sizeof(struct fm3130), GFP_KERNEL);
if (!fm3130)
return -ENOMEM;
fm3130->client = client;
i2c_set_clientdata(client, fm3130);
fm3130->reg_addr_time = FM3130_RTC_SECONDS;
fm3130->reg_addr_alarm = FM3130_ALARM_SECONDS;
/* Messages to read time */
fm3130->msg[0].addr = client->addr;
fm3130->msg[0].flags = 0;
fm3130->msg[0].len = 1;
fm3130->msg[0].buf = &fm3130->reg_addr_time;
fm3130->msg[1].addr = client->addr;
fm3130->msg[1].flags = I2C_M_RD;
fm3130->msg[1].len = FM3130_CLOCK_REGS;
fm3130->msg[1].buf = &fm3130->regs[FM3130_RTC_SECONDS];
/* Messages to read alarm */
fm3130->msg[2].addr = client->addr;
fm3130->msg[2].flags = 0;
fm3130->msg[2].len = 1;
fm3130->msg[2].buf = &fm3130->reg_addr_alarm;
fm3130->msg[3].addr = client->addr;
fm3130->msg[3].flags = I2C_M_RD;
fm3130->msg[3].len = FM3130_ALARM_REGS;
fm3130->msg[3].buf = &fm3130->regs[FM3130_ALARM_SECONDS];
fm3130->alarm_valid = 0;
fm3130->data_valid = 0;
tmp = i2c_transfer(adapter, fm3130->msg, 4);
if (tmp != 4) {
dev_dbg(&client->dev, "read error %d\n", tmp);
err = -EIO;
goto exit_free;
}
fm3130->regs[FM3130_RTC_CONTROL] =
i2c_smbus_read_byte_data(client, FM3130_RTC_CONTROL);
fm3130->regs[FM3130_CAL_CONTROL] =
i2c_smbus_read_byte_data(client, FM3130_CAL_CONTROL);
/* Disabling calibration mode */
if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) {
i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_CAL));
dev_warn(&client->dev, "Disabling calibration mode!\n");
}
/* Disabling read and write modes */
if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_WRITE ||
fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_READ) {
i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_READ |
FM3130_RTC_CONTROL_BIT_WRITE));
dev_warn(&client->dev, "Disabling READ or WRITE mode!\n");
}
/* oscillator off? turn it on, so clock can tick. */
if (fm3130->regs[FM3130_CAL_CONTROL] & FM3130_CAL_CONTROL_BIT_nOSCEN)
i2c_smbus_write_byte_data(client, FM3130_CAL_CONTROL,
fm3130->regs[FM3130_CAL_CONTROL] &
~(FM3130_CAL_CONTROL_BIT_nOSCEN));
/* low battery? clear flag, and warn */
if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_LB) {
i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
fm3130->regs[FM3130_RTC_CONTROL] &
~(FM3130_RTC_CONTROL_BIT_LB));
dev_warn(&client->dev, "Low battery!\n");
}
/* check if Power On Reset bit is set */
if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_POR) {
i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
fm3130->regs[FM3130_RTC_CONTROL] &
~FM3130_RTC_CONTROL_BIT_POR);
dev_dbg(&client->dev, "POR bit is set\n");
}
/* ACS is controlled by alarm */
i2c_smbus_write_byte_data(client, FM3130_ALARM_WP_CONTROL, 0x80);
/* alarm registers sanity check */
tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
if (tmp > 59)
goto bad_alarm;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
if (tmp > 59)
goto bad_alarm;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
if (tmp > 23)
goto bad_alarm;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
if (tmp == 0 || tmp > 31)
goto bad_alarm;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
if (tmp == 0 || tmp > 12)
goto bad_alarm;
fm3130->alarm_valid = 1;
bad_alarm:
/* clock registers sanity chek */
tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
if (tmp > 59)
goto bad_clock;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
if (tmp > 59)
goto bad_clock;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
if (tmp > 23)
goto bad_clock;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x7);
if (tmp == 0 || tmp > 7)
goto bad_clock;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
if (tmp == 0 || tmp > 31)
goto bad_clock;
tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
if (tmp == 0 || tmp > 12)
goto bad_clock;
fm3130->data_valid = 1;
bad_clock:
if (!fm3130->data_valid || !fm3130->alarm_valid)
dev_dbg(&client->dev, "%s: %15ph\n", "bogus registers",
fm3130->regs);
/* We won't bail out here because we just got invalid data.
Time setting from u-boot doesn't work anyway */
fm3130->rtc = devm_rtc_device_register(&client->dev, client->name,
&fm3130_rtc_ops, THIS_MODULE);
if (IS_ERR(fm3130->rtc)) {
err = PTR_ERR(fm3130->rtc);
dev_err(&client->dev,
"unable to register the class device\n");
goto exit_free;
}
return 0;
exit_free:
return err;
}
static struct i2c_driver fm3130_driver = {
.driver = {
.name = "rtc-fm3130",
},
.probe = fm3130_probe,
.id_table = fm3130_id,
};
module_i2c_driver(fm3130_driver);
MODULE_DESCRIPTION("RTC driver for FM3130");
MODULE_AUTHOR("Sergey Lapin <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-fm3130.c |
// SPDX-License-Identifier: GPL-2.0
/*
* RTC driver for the Micro Crystal RV8803
*
* Copyright (C) 2015 Micro Crystal SA
* Alexandre Belloni <[email protected]>
*
*/
#include <linux/bcd.h>
#include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/log2.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/rtc.h>
#define RV8803_I2C_TRY_COUNT 4
#define RV8803_SEC 0x00
#define RV8803_MIN 0x01
#define RV8803_HOUR 0x02
#define RV8803_WEEK 0x03
#define RV8803_DAY 0x04
#define RV8803_MONTH 0x05
#define RV8803_YEAR 0x06
#define RV8803_RAM 0x07
#define RV8803_ALARM_MIN 0x08
#define RV8803_ALARM_HOUR 0x09
#define RV8803_ALARM_WEEK_OR_DAY 0x0A
#define RV8803_EXT 0x0D
#define RV8803_FLAG 0x0E
#define RV8803_CTRL 0x0F
#define RV8803_OSC_OFFSET 0x2C
#define RV8803_EXT_WADA BIT(6)
#define RV8803_FLAG_V1F BIT(0)
#define RV8803_FLAG_V2F BIT(1)
#define RV8803_FLAG_AF BIT(3)
#define RV8803_FLAG_TF BIT(4)
#define RV8803_FLAG_UF BIT(5)
#define RV8803_CTRL_RESET BIT(0)
#define RV8803_CTRL_EIE BIT(2)
#define RV8803_CTRL_AIE BIT(3)
#define RV8803_CTRL_TIE BIT(4)
#define RV8803_CTRL_UIE BIT(5)
#define RX8803_CTRL_CSEL GENMASK(7, 6)
#define RX8900_BACKUP_CTRL 0x18
#define RX8900_FLAG_SWOFF BIT(2)
#define RX8900_FLAG_VDETOFF BIT(3)
enum rv8803_type {
rv_8803,
rx_8803,
rx_8804,
rx_8900
};
struct rv8803_data {
struct i2c_client *client;
struct rtc_device *rtc;
struct mutex flags_lock;
u8 ctrl;
u8 backup;
u8 alarm_invalid:1;
enum rv8803_type type;
};
static int rv8803_read_reg(const struct i2c_client *client, u8 reg)
{
int try = RV8803_I2C_TRY_COUNT;
s32 ret;
/*
* There is a 61µs window during which the RTC does not acknowledge I2C
* transfers. In that case, ensure that there are multiple attempts.
*/
do
ret = i2c_smbus_read_byte_data(client, reg);
while ((ret == -ENXIO || ret == -EIO) && --try);
if (ret < 0)
dev_err(&client->dev, "Unable to read register 0x%02x\n", reg);
return ret;
}
static int rv8803_read_regs(const struct i2c_client *client,
u8 reg, u8 count, u8 *values)
{
int try = RV8803_I2C_TRY_COUNT;
s32 ret;
do
ret = i2c_smbus_read_i2c_block_data(client, reg, count, values);
while ((ret == -ENXIO || ret == -EIO) && --try);
if (ret != count) {
dev_err(&client->dev,
"Unable to read registers 0x%02x..0x%02x\n",
reg, reg + count - 1);
return ret < 0 ? ret : -EIO;
}
return 0;
}
static int rv8803_write_reg(const struct i2c_client *client, u8 reg, u8 value)
{
int try = RV8803_I2C_TRY_COUNT;
s32 ret;
do
ret = i2c_smbus_write_byte_data(client, reg, value);
while ((ret == -ENXIO || ret == -EIO) && --try);
if (ret)
dev_err(&client->dev, "Unable to write register 0x%02x\n", reg);
return ret;
}
static int rv8803_write_regs(const struct i2c_client *client,
u8 reg, u8 count, const u8 *values)
{
int try = RV8803_I2C_TRY_COUNT;
s32 ret;
do
ret = i2c_smbus_write_i2c_block_data(client, reg, count,
values);
while ((ret == -ENXIO || ret == -EIO) && --try);
if (ret)
dev_err(&client->dev,
"Unable to write registers 0x%02x..0x%02x\n",
reg, reg + count - 1);
return ret;
}
static int rv8803_regs_init(struct rv8803_data *rv8803)
{
int ret;
ret = rv8803_write_reg(rv8803->client, RV8803_OSC_OFFSET, 0x00);
if (ret)
return ret;
ret = rv8803_write_reg(rv8803->client, RV8803_CTRL,
FIELD_PREP(RX8803_CTRL_CSEL, 1)); /* 2s */
if (ret)
return ret;
ret = rv8803_write_regs(rv8803->client, RV8803_ALARM_MIN, 3,
(u8[]){ 0, 0, 0 });
if (ret)
return ret;
return rv8803_write_reg(rv8803->client, RV8803_RAM, 0x00);
}
static int rv8803_regs_configure(struct rv8803_data *rv8803);
static int rv8803_regs_reset(struct rv8803_data *rv8803, bool full)
{
/*
* The RV-8803 resets all registers to POR defaults after voltage-loss,
* the Epson RTCs don't, so we manually reset the remainder here.
*/
if (full || rv8803->type == rx_8803 || rv8803->type == rx_8900) {
int ret = rv8803_regs_init(rv8803);
if (ret)
return ret;
}
return rv8803_regs_configure(rv8803);
}
static irqreturn_t rv8803_handle_irq(int irq, void *dev_id)
{
struct i2c_client *client = dev_id;
struct rv8803_data *rv8803 = i2c_get_clientdata(client);
unsigned long events = 0;
int flags;
mutex_lock(&rv8803->flags_lock);
flags = rv8803_read_reg(client, RV8803_FLAG);
if (flags <= 0) {
mutex_unlock(&rv8803->flags_lock);
return IRQ_NONE;
}
if (flags & RV8803_FLAG_V1F)
dev_warn(&client->dev, "Voltage low, temperature compensation stopped.\n");
if (flags & RV8803_FLAG_V2F)
dev_warn(&client->dev, "Voltage low, data loss detected.\n");
if (flags & RV8803_FLAG_TF) {
flags &= ~RV8803_FLAG_TF;
rv8803->ctrl &= ~RV8803_CTRL_TIE;
events |= RTC_PF;
}
if (flags & RV8803_FLAG_AF) {
flags &= ~RV8803_FLAG_AF;
rv8803->ctrl &= ~RV8803_CTRL_AIE;
events |= RTC_AF;
}
if (flags & RV8803_FLAG_UF) {
flags &= ~RV8803_FLAG_UF;
rv8803->ctrl &= ~RV8803_CTRL_UIE;
events |= RTC_UF;
}
if (events) {
rtc_update_irq(rv8803->rtc, 1, events);
rv8803_write_reg(client, RV8803_FLAG, flags);
rv8803_write_reg(rv8803->client, RV8803_CTRL, rv8803->ctrl);
}
mutex_unlock(&rv8803->flags_lock);
return IRQ_HANDLED;
}
static int rv8803_get_time(struct device *dev, struct rtc_time *tm)
{
struct rv8803_data *rv8803 = dev_get_drvdata(dev);
u8 date1[7];
u8 date2[7];
u8 *date = date1;
int ret, flags;
if (rv8803->alarm_invalid) {
dev_warn(dev, "Corruption detected, data may be invalid.\n");
return -EINVAL;
}
flags = rv8803_read_reg(rv8803->client, RV8803_FLAG);
if (flags < 0)
return flags;
if (flags & RV8803_FLAG_V2F) {
dev_warn(dev, "Voltage low, data is invalid.\n");
return -EINVAL;
}
ret = rv8803_read_regs(rv8803->client, RV8803_SEC, 7, date);
if (ret)
return ret;
if ((date1[RV8803_SEC] & 0x7f) == bin2bcd(59)) {
ret = rv8803_read_regs(rv8803->client, RV8803_SEC, 7, date2);
if (ret)
return ret;
if ((date2[RV8803_SEC] & 0x7f) != bin2bcd(59))
date = date2;
}
tm->tm_sec = bcd2bin(date[RV8803_SEC] & 0x7f);
tm->tm_min = bcd2bin(date[RV8803_MIN] & 0x7f);
tm->tm_hour = bcd2bin(date[RV8803_HOUR] & 0x3f);
tm->tm_wday = ilog2(date[RV8803_WEEK] & 0x7f);
tm->tm_mday = bcd2bin(date[RV8803_DAY] & 0x3f);
tm->tm_mon = bcd2bin(date[RV8803_MONTH] & 0x1f) - 1;
tm->tm_year = bcd2bin(date[RV8803_YEAR]) + 100;
return 0;
}
static int rv8803_set_time(struct device *dev, struct rtc_time *tm)
{
struct rv8803_data *rv8803 = dev_get_drvdata(dev);
u8 date[7];
int ctrl, flags, ret;
ctrl = rv8803_read_reg(rv8803->client, RV8803_CTRL);
if (ctrl < 0)
return ctrl;
/* Stop the clock */
ret = rv8803_write_reg(rv8803->client, RV8803_CTRL,
ctrl | RV8803_CTRL_RESET);
if (ret)
return ret;
date[RV8803_SEC] = bin2bcd(tm->tm_sec);
date[RV8803_MIN] = bin2bcd(tm->tm_min);
date[RV8803_HOUR] = bin2bcd(tm->tm_hour);
date[RV8803_WEEK] = 1 << (tm->tm_wday);
date[RV8803_DAY] = bin2bcd(tm->tm_mday);
date[RV8803_MONTH] = bin2bcd(tm->tm_mon + 1);
date[RV8803_YEAR] = bin2bcd(tm->tm_year - 100);
ret = rv8803_write_regs(rv8803->client, RV8803_SEC, 7, date);
if (ret)
return ret;
/* Restart the clock */
ret = rv8803_write_reg(rv8803->client, RV8803_CTRL,
ctrl & ~RV8803_CTRL_RESET);
if (ret)
return ret;
mutex_lock(&rv8803->flags_lock);
flags = rv8803_read_reg(rv8803->client, RV8803_FLAG);
if (flags < 0) {
mutex_unlock(&rv8803->flags_lock);
return flags;
}
if ((flags & RV8803_FLAG_V2F) || rv8803->alarm_invalid) {
/*
* If we sense corruption in the alarm registers, but see no
* voltage loss flag, we can't rely on other registers having
* sensible values. Reset them fully.
*/
ret = rv8803_regs_reset(rv8803, rv8803->alarm_invalid);
if (ret) {
mutex_unlock(&rv8803->flags_lock);
return ret;
}
rv8803->alarm_invalid = false;
}
ret = rv8803_write_reg(rv8803->client, RV8803_FLAG,
flags & ~(RV8803_FLAG_V1F | RV8803_FLAG_V2F));
mutex_unlock(&rv8803->flags_lock);
return ret;
}
static int rv8803_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rv8803_data *rv8803 = dev_get_drvdata(dev);
struct i2c_client *client = rv8803->client;
u8 alarmvals[3];
int flags, ret;
ret = rv8803_read_regs(client, RV8803_ALARM_MIN, 3, alarmvals);
if (ret)
return ret;
flags = rv8803_read_reg(client, RV8803_FLAG);
if (flags < 0)
return flags;
alarmvals[0] &= 0x7f;
alarmvals[1] &= 0x3f;
alarmvals[2] &= 0x3f;
if (!bcd_is_valid(alarmvals[0]) ||
!bcd_is_valid(alarmvals[1]) ||
!bcd_is_valid(alarmvals[2]))
goto err_invalid;
alrm->time.tm_sec = 0;
alrm->time.tm_min = bcd2bin(alarmvals[0]);
alrm->time.tm_hour = bcd2bin(alarmvals[1]);
alrm->time.tm_mday = bcd2bin(alarmvals[2]);
alrm->enabled = !!(rv8803->ctrl & RV8803_CTRL_AIE);
alrm->pending = (flags & RV8803_FLAG_AF) && alrm->enabled;
if ((unsigned int)alrm->time.tm_mday > 31 ||
(unsigned int)alrm->time.tm_hour >= 24 ||
(unsigned int)alrm->time.tm_min >= 60)
goto err_invalid;
return 0;
err_invalid:
rv8803->alarm_invalid = true;
return -EINVAL;
}
static int rv8803_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct i2c_client *client = to_i2c_client(dev);
struct rv8803_data *rv8803 = dev_get_drvdata(dev);
u8 alarmvals[3];
u8 ctrl[2];
int ret, err;
/* The alarm has no seconds, round up to nearest minute */
if (alrm->time.tm_sec) {
time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
alarm_time += 60 - alrm->time.tm_sec;
rtc_time64_to_tm(alarm_time, &alrm->time);
}
mutex_lock(&rv8803->flags_lock);
ret = rv8803_read_regs(client, RV8803_FLAG, 2, ctrl);
if (ret) {
mutex_unlock(&rv8803->flags_lock);
return ret;
}
alarmvals[0] = bin2bcd(alrm->time.tm_min);
alarmvals[1] = bin2bcd(alrm->time.tm_hour);
alarmvals[2] = bin2bcd(alrm->time.tm_mday);
if (rv8803->ctrl & (RV8803_CTRL_AIE | RV8803_CTRL_UIE)) {
rv8803->ctrl &= ~(RV8803_CTRL_AIE | RV8803_CTRL_UIE);
err = rv8803_write_reg(rv8803->client, RV8803_CTRL,
rv8803->ctrl);
if (err) {
mutex_unlock(&rv8803->flags_lock);
return err;
}
}
ctrl[0] &= ~RV8803_FLAG_AF;
err = rv8803_write_reg(rv8803->client, RV8803_FLAG, ctrl[0]);
mutex_unlock(&rv8803->flags_lock);
if (err)
return err;
err = rv8803_write_regs(rv8803->client, RV8803_ALARM_MIN, 3, alarmvals);
if (err)
return err;
if (alrm->enabled) {
if (rv8803->rtc->uie_rtctimer.enabled)
rv8803->ctrl |= RV8803_CTRL_UIE;
if (rv8803->rtc->aie_timer.enabled)
rv8803->ctrl |= RV8803_CTRL_AIE;
err = rv8803_write_reg(rv8803->client, RV8803_CTRL,
rv8803->ctrl);
if (err)
return err;
}
return 0;
}
static int rv8803_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct i2c_client *client = to_i2c_client(dev);
struct rv8803_data *rv8803 = dev_get_drvdata(dev);
int ctrl, flags, err;
ctrl = rv8803->ctrl;
if (enabled) {
if (rv8803->rtc->uie_rtctimer.enabled)
ctrl |= RV8803_CTRL_UIE;
if (rv8803->rtc->aie_timer.enabled)
ctrl |= RV8803_CTRL_AIE;
} else {
if (!rv8803->rtc->uie_rtctimer.enabled)
ctrl &= ~RV8803_CTRL_UIE;
if (!rv8803->rtc->aie_timer.enabled)
ctrl &= ~RV8803_CTRL_AIE;
}
mutex_lock(&rv8803->flags_lock);
flags = rv8803_read_reg(client, RV8803_FLAG);
if (flags < 0) {
mutex_unlock(&rv8803->flags_lock);
return flags;
}
flags &= ~(RV8803_FLAG_AF | RV8803_FLAG_UF);
err = rv8803_write_reg(client, RV8803_FLAG, flags);
mutex_unlock(&rv8803->flags_lock);
if (err)
return err;
if (ctrl != rv8803->ctrl) {
rv8803->ctrl = ctrl;
err = rv8803_write_reg(client, RV8803_CTRL, rv8803->ctrl);
if (err)
return err;
}
return 0;
}
static int rv8803_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
struct i2c_client *client = to_i2c_client(dev);
struct rv8803_data *rv8803 = dev_get_drvdata(dev);
unsigned int vl = 0;
int flags, ret = 0;
switch (cmd) {
case RTC_VL_READ:
flags = rv8803_read_reg(client, RV8803_FLAG);
if (flags < 0)
return flags;
if (flags & RV8803_FLAG_V1F) {
dev_warn(&client->dev, "Voltage low, temperature compensation stopped.\n");
vl = RTC_VL_ACCURACY_LOW;
}
if (flags & RV8803_FLAG_V2F)
vl |= RTC_VL_DATA_INVALID;
return put_user(vl, (unsigned int __user *)arg);
case RTC_VL_CLR:
mutex_lock(&rv8803->flags_lock);
flags = rv8803_read_reg(client, RV8803_FLAG);
if (flags < 0) {
mutex_unlock(&rv8803->flags_lock);
return flags;
}
flags &= ~RV8803_FLAG_V1F;
ret = rv8803_write_reg(client, RV8803_FLAG, flags);
mutex_unlock(&rv8803->flags_lock);
if (ret)
return ret;
return 0;
default:
return -ENOIOCTLCMD;
}
}
static int rv8803_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return rv8803_write_reg(priv, RV8803_RAM, *(u8 *)val);
}
static int rv8803_nvram_read(void *priv, unsigned int offset,
void *val, size_t bytes)
{
int ret;
ret = rv8803_read_reg(priv, RV8803_RAM);
if (ret < 0)
return ret;
*(u8 *)val = ret;
return 0;
}
static const struct rtc_class_ops rv8803_rtc_ops = {
.read_time = rv8803_get_time,
.set_time = rv8803_set_time,
.ioctl = rv8803_ioctl,
.read_alarm = rv8803_get_alarm,
.set_alarm = rv8803_set_alarm,
.alarm_irq_enable = rv8803_alarm_irq_enable,
};
static int rx8900_trickle_charger_init(struct rv8803_data *rv8803)
{
struct i2c_client *client = rv8803->client;
struct device_node *node = client->dev.of_node;
int err;
u8 flags;
if (!node)
return 0;
if (rv8803->type != rx_8900)
return 0;
err = i2c_smbus_read_byte_data(rv8803->client, RX8900_BACKUP_CTRL);
if (err < 0)
return err;
flags = (u8)err;
flags &= ~(RX8900_FLAG_VDETOFF | RX8900_FLAG_SWOFF);
flags |= rv8803->backup;
return i2c_smbus_write_byte_data(rv8803->client, RX8900_BACKUP_CTRL,
flags);
}
/* configure registers with values different than the Power-On reset defaults */
static int rv8803_regs_configure(struct rv8803_data *rv8803)
{
int err;
err = rv8803_write_reg(rv8803->client, RV8803_EXT, RV8803_EXT_WADA);
if (err)
return err;
err = rx8900_trickle_charger_init(rv8803);
if (err) {
dev_err(&rv8803->client->dev, "failed to init charger\n");
return err;
}
return 0;
}
static const struct i2c_device_id rv8803_id[] = {
{ "rv8803", rv_8803 },
{ "rv8804", rx_8804 },
{ "rx8803", rx_8803 },
{ "rx8900", rx_8900 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rv8803_id);
static int rv8803_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
struct rv8803_data *rv8803;
int err, flags;
struct nvmem_config nvmem_cfg = {
.name = "rv8803_nvram",
.word_size = 1,
.stride = 1,
.size = 1,
.reg_read = rv8803_nvram_read,
.reg_write = rv8803_nvram_write,
.priv = client,
};
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_SMBUS_I2C_BLOCK)) {
dev_err(&adapter->dev, "doesn't support I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK\n");
return -EIO;
}
rv8803 = devm_kzalloc(&client->dev, sizeof(struct rv8803_data),
GFP_KERNEL);
if (!rv8803)
return -ENOMEM;
mutex_init(&rv8803->flags_lock);
rv8803->client = client;
if (client->dev.of_node) {
rv8803->type = (uintptr_t)of_device_get_match_data(&client->dev);
} else {
const struct i2c_device_id *id = i2c_match_id(rv8803_id, client);
rv8803->type = id->driver_data;
}
i2c_set_clientdata(client, rv8803);
flags = rv8803_read_reg(client, RV8803_FLAG);
if (flags < 0)
return flags;
if (flags & RV8803_FLAG_V1F)
dev_warn(&client->dev, "Voltage low, temperature compensation stopped.\n");
if (flags & RV8803_FLAG_V2F)
dev_warn(&client->dev, "Voltage low, data loss detected.\n");
if (flags & RV8803_FLAG_AF)
dev_warn(&client->dev, "An alarm maybe have been missed.\n");
rv8803->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(rv8803->rtc))
return PTR_ERR(rv8803->rtc);
if (client->irq > 0) {
unsigned long irqflags = IRQF_TRIGGER_LOW;
if (dev_fwnode(&client->dev))
irqflags = 0;
err = devm_request_threaded_irq(&client->dev, client->irq,
NULL, rv8803_handle_irq,
irqflags | IRQF_ONESHOT,
"rv8803", client);
if (err) {
dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
client->irq = 0;
}
}
if (!client->irq)
clear_bit(RTC_FEATURE_ALARM, rv8803->rtc->features);
if (of_property_read_bool(client->dev.of_node, "epson,vdet-disable"))
rv8803->backup |= RX8900_FLAG_VDETOFF;
if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
rv8803->backup |= RX8900_FLAG_SWOFF;
err = rv8803_regs_configure(rv8803);
if (err)
return err;
rv8803->rtc->ops = &rv8803_rtc_ops;
rv8803->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rv8803->rtc->range_max = RTC_TIMESTAMP_END_2099;
err = devm_rtc_register_device(rv8803->rtc);
if (err)
return err;
devm_rtc_nvmem_register(rv8803->rtc, &nvmem_cfg);
rv8803->rtc->max_user_freq = 1;
return 0;
}
static const __maybe_unused struct of_device_id rv8803_of_match[] = {
{
.compatible = "microcrystal,rv8803",
.data = (void *)rv_8803
},
{
.compatible = "epson,rx8803",
.data = (void *)rx_8803
},
{
.compatible = "epson,rx8804",
.data = (void *)rx_8804
},
{
.compatible = "epson,rx8900",
.data = (void *)rx_8900
},
{ }
};
MODULE_DEVICE_TABLE(of, rv8803_of_match);
static struct i2c_driver rv8803_driver = {
.driver = {
.name = "rtc-rv8803",
.of_match_table = of_match_ptr(rv8803_of_match),
},
.probe = rv8803_probe,
.id_table = rv8803_id,
};
module_i2c_driver(rv8803_driver);
MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
MODULE_DESCRIPTION("Micro Crystal RV8803 RTC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-rv8803.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2010 Orex Computed Radiography
*/
/*
* This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
* to implement a Linux RTC. Times and alarms are truncated to seconds.
* Since the RTC framework performs API locking via rtc->ops_lock the
* only simultaneous accesses we need to deal with is updating DryIce
* registers while servicing an alarm.
*
* Note that reading the DSR (DryIce Status Register) automatically clears
* the WCF (Write Complete Flag). All DryIce writes are synchronized to the
* LP (Low Power) domain and set the WCF upon completion. Writes to the
* DIER (DryIce Interrupt Enable Register) are the only exception. These
* occur at normal bus speeds and do not set WCF. Periodic interrupts are
* not supported by the hardware.
*/
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/of.h>
/* DryIce Register Definitions */
#define DTCMR 0x00 /* Time Counter MSB Reg */
#define DTCLR 0x04 /* Time Counter LSB Reg */
#define DCAMR 0x08 /* Clock Alarm MSB Reg */
#define DCALR 0x0c /* Clock Alarm LSB Reg */
#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
#define DCR 0x10 /* Control Reg */
#define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
#define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
#define DCR_KSSL (1 << 27) /* Key-select soft lock */
#define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */
#define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */
#define DCR_TCHL (1 << 18) /* Timer-counter hard lock */
#define DCR_TCSL (1 << 17) /* Timer-counter soft lock */
#define DCR_FSHL (1 << 16) /* Failure state hard lock */
#define DCR_TCE (1 << 3) /* Time Counter Enable */
#define DCR_MCE (1 << 2) /* Monotonic Counter Enable */
#define DSR 0x14 /* Status Reg */
#define DSR_WTD (1 << 23) /* Wire-mesh tamper detected */
#define DSR_ETBD (1 << 22) /* External tamper B detected */
#define DSR_ETAD (1 << 21) /* External tamper A detected */
#define DSR_EBD (1 << 20) /* External boot detected */
#define DSR_SAD (1 << 19) /* SCC alarm detected */
#define DSR_TTD (1 << 18) /* Temperature tamper detected */
#define DSR_CTD (1 << 17) /* Clock tamper detected */
#define DSR_VTD (1 << 16) /* Voltage tamper detected */
#define DSR_WBF (1 << 10) /* Write Busy Flag (synchronous) */
#define DSR_WNF (1 << 9) /* Write Next Flag (synchronous) */
#define DSR_WCF (1 << 8) /* Write Complete Flag (synchronous)*/
#define DSR_WEF (1 << 7) /* Write Error Flag */
#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
#define DSR_MCO (1 << 3) /* monotonic counter overflow */
#define DSR_TCO (1 << 2) /* time counter overflow */
#define DSR_NVF (1 << 1) /* Non-Valid Flag */
#define DSR_SVF (1 << 0) /* Security Violation Flag */
#define DIER 0x18 /* Interrupt Enable Reg (synchronous) */
#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
#define DIER_SVIE (1 << 0) /* Security-violation Interrupt Enable */
#define DMCR 0x1c /* DryIce Monotonic Counter Reg */
#define DTCR 0x28 /* DryIce Tamper Configuration Reg */
#define DTCR_MOE (1 << 9) /* monotonic overflow enabled */
#define DTCR_TOE (1 << 8) /* time overflow enabled */
#define DTCR_WTE (1 << 7) /* wire-mesh tamper enabled */
#define DTCR_ETBE (1 << 6) /* external B tamper enabled */
#define DTCR_ETAE (1 << 5) /* external A tamper enabled */
#define DTCR_EBE (1 << 4) /* external boot tamper enabled */
#define DTCR_SAIE (1 << 3) /* SCC enabled */
#define DTCR_TTE (1 << 2) /* temperature tamper enabled */
#define DTCR_CTE (1 << 1) /* clock tamper enabled */
#define DTCR_VTE (1 << 0) /* voltage tamper enabled */
#define DGPR 0x3c /* DryIce General Purpose Reg */
/**
* struct imxdi_dev - private imxdi rtc data
* @pdev: pointer to platform dev
* @rtc: pointer to rtc struct
* @ioaddr: IO registers pointer
* @clk: input reference clock
* @dsr: copy of the DSR register
* @irq_lock: interrupt enable register (DIER) lock
* @write_wait: registers write complete queue
* @write_mutex: serialize registers write
* @work: schedule alarm work
*/
struct imxdi_dev {
struct platform_device *pdev;
struct rtc_device *rtc;
void __iomem *ioaddr;
struct clk *clk;
u32 dsr;
spinlock_t irq_lock;
wait_queue_head_t write_wait;
struct mutex write_mutex;
struct work_struct work;
};
/* Some background:
*
* The DryIce unit is a complex security/tamper monitor device. To be able do
* its job in a useful manner it runs a bigger statemachine to bring it into
* security/tamper failure state and once again to bring it out of this state.
*
* This unit can be in one of three states:
*
* - "NON-VALID STATE"
* always after the battery power was removed
* - "FAILURE STATE"
* if one of the enabled security events has happened
* - "VALID STATE"
* if the unit works as expected
*
* Everything stops when the unit enters the failure state including the RTC
* counter (to be able to detect the time the security event happened).
*
* The following events (when enabled) let the DryIce unit enter the failure
* state:
*
* - wire-mesh-tamper detect
* - external tamper B detect
* - external tamper A detect
* - temperature tamper detect
* - clock tamper detect
* - voltage tamper detect
* - RTC counter overflow
* - monotonic counter overflow
* - external boot
*
* If we find the DryIce unit in "FAILURE STATE" and the TDCHL cleared, we
* can only detect this state. In this case the unit is completely locked and
* must force a second "SYSTEM POR" to bring the DryIce into the
* "NON-VALID STATE" + "FAILURE STATE" where a recovery is possible.
* If the TDCHL is set in the "FAILURE STATE" we are out of luck. In this case
* a battery power cycle is required.
*
* In the "NON-VALID STATE" + "FAILURE STATE" we can clear the "FAILURE STATE"
* and recover the DryIce unit. By clearing the "NON-VALID STATE" as the last
* task, we bring back this unit into life.
*/
/*
* Do a write into the unit without interrupt support.
* We do not need to check the WEF here, because the only reason this kind of
* write error can happen is if we write to the unit twice within the 122 us
* interval. This cannot happen, since we are using this function only while
* setting up the unit.
*/
static void di_write_busy_wait(const struct imxdi_dev *imxdi, u32 val,
unsigned reg)
{
/* do the register write */
writel(val, imxdi->ioaddr + reg);
/*
* now it takes four 32,768 kHz clock cycles to take
* the change into effect = 122 us
*/
usleep_range(130, 200);
}
static void di_report_tamper_info(struct imxdi_dev *imxdi, u32 dsr)
{
u32 dtcr;
dtcr = readl(imxdi->ioaddr + DTCR);
dev_emerg(&imxdi->pdev->dev, "DryIce tamper event detected\n");
/* the following flags force a transition into the "FAILURE STATE" */
if (dsr & DSR_VTD)
dev_emerg(&imxdi->pdev->dev, "%sVoltage Tamper Event\n",
dtcr & DTCR_VTE ? "" : "Spurious ");
if (dsr & DSR_CTD)
dev_emerg(&imxdi->pdev->dev, "%s32768 Hz Clock Tamper Event\n",
dtcr & DTCR_CTE ? "" : "Spurious ");
if (dsr & DSR_TTD)
dev_emerg(&imxdi->pdev->dev, "%sTemperature Tamper Event\n",
dtcr & DTCR_TTE ? "" : "Spurious ");
if (dsr & DSR_SAD)
dev_emerg(&imxdi->pdev->dev,
"%sSecure Controller Alarm Event\n",
dtcr & DTCR_SAIE ? "" : "Spurious ");
if (dsr & DSR_EBD)
dev_emerg(&imxdi->pdev->dev, "%sExternal Boot Tamper Event\n",
dtcr & DTCR_EBE ? "" : "Spurious ");
if (dsr & DSR_ETAD)
dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper A Event\n",
dtcr & DTCR_ETAE ? "" : "Spurious ");
if (dsr & DSR_ETBD)
dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper B Event\n",
dtcr & DTCR_ETBE ? "" : "Spurious ");
if (dsr & DSR_WTD)
dev_emerg(&imxdi->pdev->dev, "%sWire-mesh Tamper Event\n",
dtcr & DTCR_WTE ? "" : "Spurious ");
if (dsr & DSR_MCO)
dev_emerg(&imxdi->pdev->dev,
"%sMonotonic-counter Overflow Event\n",
dtcr & DTCR_MOE ? "" : "Spurious ");
if (dsr & DSR_TCO)
dev_emerg(&imxdi->pdev->dev, "%sTimer-counter Overflow Event\n",
dtcr & DTCR_TOE ? "" : "Spurious ");
}
static void di_what_is_to_be_done(struct imxdi_dev *imxdi,
const char *power_supply)
{
dev_emerg(&imxdi->pdev->dev, "Please cycle the %s power supply in order to get the DryIce/RTC unit working again\n",
power_supply);
}
static int di_handle_failure_state(struct imxdi_dev *imxdi, u32 dsr)
{
u32 dcr;
dev_dbg(&imxdi->pdev->dev, "DSR register reports: %08X\n", dsr);
/* report the cause */
di_report_tamper_info(imxdi, dsr);
dcr = readl(imxdi->ioaddr + DCR);
if (dcr & DCR_FSHL) {
/* we are out of luck */
di_what_is_to_be_done(imxdi, "battery");
return -ENODEV;
}
/*
* with the next SYSTEM POR we will transit from the "FAILURE STATE"
* into the "NON-VALID STATE" + "FAILURE STATE"
*/
di_what_is_to_be_done(imxdi, "main");
return -ENODEV;
}
static int di_handle_valid_state(struct imxdi_dev *imxdi, u32 dsr)
{
/* initialize alarm */
di_write_busy_wait(imxdi, DCAMR_UNSET, DCAMR);
di_write_busy_wait(imxdi, 0, DCALR);
/* clear alarm flag */
if (dsr & DSR_CAF)
di_write_busy_wait(imxdi, DSR_CAF, DSR);
return 0;
}
static int di_handle_invalid_state(struct imxdi_dev *imxdi, u32 dsr)
{
u32 dcr, sec;
/*
* lets disable all sources which can force the DryIce unit into
* the "FAILURE STATE" for now
*/
di_write_busy_wait(imxdi, 0x00000000, DTCR);
/* and lets protect them at runtime from any change */
di_write_busy_wait(imxdi, DCR_TDCSL, DCR);
sec = readl(imxdi->ioaddr + DTCMR);
if (sec != 0)
dev_warn(&imxdi->pdev->dev,
"The security violation has happened at %u seconds\n",
sec);
/*
* the timer cannot be set/modified if
* - the TCHL or TCSL bit is set in DCR
*/
dcr = readl(imxdi->ioaddr + DCR);
if (!(dcr & DCR_TCE)) {
if (dcr & DCR_TCHL) {
/* we are out of luck */
di_what_is_to_be_done(imxdi, "battery");
return -ENODEV;
}
if (dcr & DCR_TCSL) {
di_what_is_to_be_done(imxdi, "main");
return -ENODEV;
}
}
/*
* - the timer counter stops/is stopped if
* - its overflow flag is set (TCO in DSR)
* -> clear overflow bit to make it count again
* - NVF is set in DSR
* -> clear non-valid bit to make it count again
* - its TCE (DCR) is cleared
* -> set TCE to make it count
* - it was never set before
* -> write a time into it (required again if the NVF was set)
*/
/* state handled */
di_write_busy_wait(imxdi, DSR_NVF, DSR);
/* clear overflow flag */
di_write_busy_wait(imxdi, DSR_TCO, DSR);
/* enable the counter */
di_write_busy_wait(imxdi, dcr | DCR_TCE, DCR);
/* set and trigger it to make it count */
di_write_busy_wait(imxdi, sec, DTCMR);
/* now prepare for the valid state */
return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));
}
static int di_handle_invalid_and_failure_state(struct imxdi_dev *imxdi, u32 dsr)
{
u32 dcr;
/*
* now we must first remove the tamper sources in order to get the
* device out of the "FAILURE STATE"
* To disable any of the following sources we need to modify the DTCR
*/
if (dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD |
DSR_TTD | DSR_CTD | DSR_VTD | DSR_MCO | DSR_TCO)) {
dcr = __raw_readl(imxdi->ioaddr + DCR);
if (dcr & DCR_TDCHL) {
/*
* the tamper register is locked. We cannot disable the
* tamper detection. The TDCHL can only be reset by a
* DRYICE POR, but we cannot force a DRYICE POR in
* software because we are still in "FAILURE STATE".
* We need a DRYICE POR via battery power cycling....
*/
/*
* out of luck!
* we cannot disable them without a DRYICE POR
*/
di_what_is_to_be_done(imxdi, "battery");
return -ENODEV;
}
if (dcr & DCR_TDCSL) {
/* a soft lock can be removed by a SYSTEM POR */
di_what_is_to_be_done(imxdi, "main");
return -ENODEV;
}
}
/* disable all sources */
di_write_busy_wait(imxdi, 0x00000000, DTCR);
/* clear the status bits now */
di_write_busy_wait(imxdi, dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD |
DSR_EBD | DSR_SAD | DSR_TTD | DSR_CTD | DSR_VTD |
DSR_MCO | DSR_TCO), DSR);
dsr = readl(imxdi->ioaddr + DSR);
if ((dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |
DSR_WCF | DSR_WEF)) != 0)
dev_warn(&imxdi->pdev->dev,
"There are still some sources of pain in DSR: %08x!\n",
dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |
DSR_WCF | DSR_WEF));
/*
* now we are trying to clear the "Security-violation flag" to
* get the DryIce out of this state
*/
di_write_busy_wait(imxdi, DSR_SVF, DSR);
/* success? */
dsr = readl(imxdi->ioaddr + DSR);
if (dsr & DSR_SVF) {
dev_crit(&imxdi->pdev->dev,
"Cannot clear the security violation flag. We are ending up in an endless loop!\n");
/* last resort */
di_what_is_to_be_done(imxdi, "battery");
return -ENODEV;
}
/*
* now we have left the "FAILURE STATE" and ending up in the
* "NON-VALID STATE" time to recover everything
*/
return di_handle_invalid_state(imxdi, dsr);
}
static int di_handle_state(struct imxdi_dev *imxdi)
{
int rc;
u32 dsr;
dsr = readl(imxdi->ioaddr + DSR);
switch (dsr & (DSR_NVF | DSR_SVF)) {
case DSR_NVF:
dev_warn(&imxdi->pdev->dev, "Invalid stated unit detected\n");
rc = di_handle_invalid_state(imxdi, dsr);
break;
case DSR_SVF:
dev_warn(&imxdi->pdev->dev, "Failure stated unit detected\n");
rc = di_handle_failure_state(imxdi, dsr);
break;
case DSR_NVF | DSR_SVF:
dev_warn(&imxdi->pdev->dev,
"Failure+Invalid stated unit detected\n");
rc = di_handle_invalid_and_failure_state(imxdi, dsr);
break;
default:
dev_notice(&imxdi->pdev->dev, "Unlocked unit detected\n");
rc = di_handle_valid_state(imxdi, dsr);
}
return rc;
}
/*
* enable a dryice interrupt
*/
static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
{
unsigned long flags;
spin_lock_irqsave(&imxdi->irq_lock, flags);
writel(readl(imxdi->ioaddr + DIER) | intr,
imxdi->ioaddr + DIER);
spin_unlock_irqrestore(&imxdi->irq_lock, flags);
}
/*
* disable a dryice interrupt
*/
static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
{
unsigned long flags;
spin_lock_irqsave(&imxdi->irq_lock, flags);
writel(readl(imxdi->ioaddr + DIER) & ~intr,
imxdi->ioaddr + DIER);
spin_unlock_irqrestore(&imxdi->irq_lock, flags);
}
/*
* This function attempts to clear the dryice write-error flag.
*
* A dryice write error is similar to a bus fault and should not occur in
* normal operation. Clearing the flag requires another write, so the root
* cause of the problem may need to be fixed before the flag can be cleared.
*/
static void clear_write_error(struct imxdi_dev *imxdi)
{
int cnt;
dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
/* clear the write error flag */
writel(DSR_WEF, imxdi->ioaddr + DSR);
/* wait for it to take effect */
for (cnt = 0; cnt < 1000; cnt++) {
if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
return;
udelay(10);
}
dev_err(&imxdi->pdev->dev,
"ERROR: Cannot clear write-error flag!\n");
}
/*
* Write a dryice register and wait until it completes.
*
* This function uses interrupts to determine when the
* write has completed.
*/
static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
{
int ret;
int rc = 0;
/* serialize register writes */
mutex_lock(&imxdi->write_mutex);
/* enable the write-complete interrupt */
di_int_enable(imxdi, DIER_WCIE);
imxdi->dsr = 0;
/* do the register write */
writel(val, imxdi->ioaddr + reg);
/* wait for the write to finish */
ret = wait_event_interruptible_timeout(imxdi->write_wait,
imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
if (ret < 0) {
rc = ret;
goto out;
} else if (ret == 0) {
dev_warn(&imxdi->pdev->dev,
"Write-wait timeout "
"val = 0x%08x reg = 0x%08x\n", val, reg);
}
/* check for write error */
if (imxdi->dsr & DSR_WEF) {
clear_write_error(imxdi);
rc = -EIO;
}
out:
mutex_unlock(&imxdi->write_mutex);
return rc;
}
/*
* read the seconds portion of the current time from the dryice time counter
*/
static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
unsigned long now;
now = readl(imxdi->ioaddr + DTCMR);
rtc_time64_to_tm(now, tm);
return 0;
}
/*
* set the seconds portion of dryice time counter and clear the
* fractional part.
*/
static int dryice_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
u32 dcr, dsr;
int rc;
dcr = readl(imxdi->ioaddr + DCR);
dsr = readl(imxdi->ioaddr + DSR);
if (!(dcr & DCR_TCE) || (dsr & DSR_SVF)) {
if (dcr & DCR_TCHL) {
/* we are even more out of luck */
di_what_is_to_be_done(imxdi, "battery");
return -EPERM;
}
if ((dcr & DCR_TCSL) || (dsr & DSR_SVF)) {
/* we are out of luck for now */
di_what_is_to_be_done(imxdi, "main");
return -EPERM;
}
}
/* zero the fractional part first */
rc = di_write_wait(imxdi, 0, DTCLR);
if (rc != 0)
return rc;
rc = di_write_wait(imxdi, rtc_tm_to_time64(tm), DTCMR);
if (rc != 0)
return rc;
return di_write_wait(imxdi, readl(imxdi->ioaddr + DCR) | DCR_TCE, DCR);
}
static int dryice_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
if (enabled)
di_int_enable(imxdi, DIER_CAIE);
else
di_int_disable(imxdi, DIER_CAIE);
return 0;
}
/*
* read the seconds portion of the alarm register.
* the fractional part of the alarm register is always zero.
*/
static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
u32 dcamr;
dcamr = readl(imxdi->ioaddr + DCAMR);
rtc_time64_to_tm(dcamr, &alarm->time);
/* alarm is enabled if the interrupt is enabled */
alarm->enabled = (readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
/* don't allow the DSR read to mess up DSR_WCF */
mutex_lock(&imxdi->write_mutex);
/* alarm is pending if the alarm flag is set */
alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
mutex_unlock(&imxdi->write_mutex);
return 0;
}
/*
* set the seconds portion of dryice alarm register
*/
static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
int rc;
/* write the new alarm time */
rc = di_write_wait(imxdi, rtc_tm_to_time64(&alarm->time), DCAMR);
if (rc)
return rc;
if (alarm->enabled)
di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
else
di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
return 0;
}
static const struct rtc_class_ops dryice_rtc_ops = {
.read_time = dryice_rtc_read_time,
.set_time = dryice_rtc_set_time,
.alarm_irq_enable = dryice_rtc_alarm_irq_enable,
.read_alarm = dryice_rtc_read_alarm,
.set_alarm = dryice_rtc_set_alarm,
};
/*
* interrupt handler for dryice "normal" and security violation interrupt
*/
static irqreturn_t dryice_irq(int irq, void *dev_id)
{
struct imxdi_dev *imxdi = dev_id;
u32 dsr, dier;
irqreturn_t rc = IRQ_NONE;
dier = readl(imxdi->ioaddr + DIER);
dsr = readl(imxdi->ioaddr + DSR);
/* handle the security violation event */
if (dier & DIER_SVIE) {
if (dsr & DSR_SVF) {
/*
* Disable the interrupt when this kind of event has
* happened.
* There cannot be more than one event of this type,
* because it needs a complex state change
* including a main power cycle to get again out of
* this state.
*/
di_int_disable(imxdi, DIER_SVIE);
/* report the violation */
di_report_tamper_info(imxdi, dsr);
rc = IRQ_HANDLED;
}
}
/* handle write complete and write error cases */
if (dier & DIER_WCIE) {
/*If the write wait queue is empty then there is no pending
operations. It means the interrupt is for DryIce -Security.
IRQ must be returned as none.*/
if (list_empty_careful(&imxdi->write_wait.head))
return rc;
/* DSR_WCF clears itself on DSR read */
if (dsr & (DSR_WCF | DSR_WEF)) {
/* mask the interrupt */
di_int_disable(imxdi, DIER_WCIE);
/* save the dsr value for the wait queue */
imxdi->dsr |= dsr;
wake_up_interruptible(&imxdi->write_wait);
rc = IRQ_HANDLED;
}
}
/* handle the alarm case */
if (dier & DIER_CAIE) {
/* DSR_WCF clears itself on DSR read */
if (dsr & DSR_CAF) {
/* mask the interrupt */
di_int_disable(imxdi, DIER_CAIE);
/* finish alarm in user context */
schedule_work(&imxdi->work);
rc = IRQ_HANDLED;
}
}
return rc;
}
/*
* post the alarm event from user context so it can sleep
* on the write completion.
*/
static void dryice_work(struct work_struct *work)
{
struct imxdi_dev *imxdi = container_of(work,
struct imxdi_dev, work);
/* dismiss the interrupt (ignore error) */
di_write_wait(imxdi, DSR_CAF, DSR);
/* pass the alarm event to the rtc framework. */
rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
}
/*
* probe for dryice rtc device
*/
static int __init dryice_rtc_probe(struct platform_device *pdev)
{
struct imxdi_dev *imxdi;
int norm_irq, sec_irq;
int rc;
imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
if (!imxdi)
return -ENOMEM;
imxdi->pdev = pdev;
imxdi->ioaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(imxdi->ioaddr))
return PTR_ERR(imxdi->ioaddr);
spin_lock_init(&imxdi->irq_lock);
norm_irq = platform_get_irq(pdev, 0);
if (norm_irq < 0)
return norm_irq;
/* the 2nd irq is the security violation irq
* make this optional, don't break the device tree ABI
*/
sec_irq = platform_get_irq(pdev, 1);
if (sec_irq <= 0)
sec_irq = IRQ_NOTCONNECTED;
init_waitqueue_head(&imxdi->write_wait);
INIT_WORK(&imxdi->work, dryice_work);
mutex_init(&imxdi->write_mutex);
imxdi->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(imxdi->rtc))
return PTR_ERR(imxdi->rtc);
imxdi->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(imxdi->clk))
return PTR_ERR(imxdi->clk);
rc = clk_prepare_enable(imxdi->clk);
if (rc)
return rc;
/*
* Initialize dryice hardware
*/
/* mask all interrupts */
writel(0, imxdi->ioaddr + DIER);
rc = di_handle_state(imxdi);
if (rc != 0)
goto err;
rc = devm_request_irq(&pdev->dev, norm_irq, dryice_irq,
IRQF_SHARED, pdev->name, imxdi);
if (rc) {
dev_warn(&pdev->dev, "interrupt not available.\n");
goto err;
}
rc = devm_request_irq(&pdev->dev, sec_irq, dryice_irq,
IRQF_SHARED, pdev->name, imxdi);
if (rc) {
dev_warn(&pdev->dev, "security violation interrupt not available.\n");
/* this is not an error, see above */
}
platform_set_drvdata(pdev, imxdi);
device_init_wakeup(&pdev->dev, true);
dev_pm_set_wake_irq(&pdev->dev, norm_irq);
imxdi->rtc->ops = &dryice_rtc_ops;
imxdi->rtc->range_max = U32_MAX;
rc = devm_rtc_register_device(imxdi->rtc);
if (rc)
goto err;
return 0;
err:
clk_disable_unprepare(imxdi->clk);
return rc;
}
static int __exit dryice_rtc_remove(struct platform_device *pdev)
{
struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
flush_work(&imxdi->work);
/* mask all interrupts */
writel(0, imxdi->ioaddr + DIER);
clk_disable_unprepare(imxdi->clk);
return 0;
}
static const struct of_device_id dryice_dt_ids[] = {
{ .compatible = "fsl,imx25-rtc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dryice_dt_ids);
static struct platform_driver dryice_rtc_driver = {
.driver = {
.name = "imxdi_rtc",
.of_match_table = dryice_dt_ids,
},
.remove = __exit_p(dryice_rtc_remove),
};
module_platform_driver_probe(dryice_rtc_driver, dryice_rtc_probe);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_AUTHOR("Baruch Siach <[email protected]>");
MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-imxdi.c |
// SPDX-License-Identifier: GPL-2.0+
/*
* Renesas RZ/N1 Real Time Clock interface for Linux
*
* Copyright:
* - 2014 Renesas Electronics Europe Limited
* - 2022 Schneider Electric
*
* Authors:
* - Michel Pollet <[email protected]>, <[email protected]>
* - Miquel Raynal <[email protected]>
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/rtc.h>
#define RZN1_RTC_CTL0 0x00
#define RZN1_RTC_CTL0_SLSB_SUBU 0
#define RZN1_RTC_CTL0_SLSB_SCMP BIT(4)
#define RZN1_RTC_CTL0_AMPM BIT(5)
#define RZN1_RTC_CTL0_CE BIT(7)
#define RZN1_RTC_CTL1 0x04
#define RZN1_RTC_CTL1_ALME BIT(4)
#define RZN1_RTC_CTL2 0x08
#define RZN1_RTC_CTL2_WAIT BIT(0)
#define RZN1_RTC_CTL2_WST BIT(1)
#define RZN1_RTC_CTL2_WUST BIT(5)
#define RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST)
#define RZN1_RTC_SEC 0x14
#define RZN1_RTC_MIN 0x18
#define RZN1_RTC_HOUR 0x1c
#define RZN1_RTC_WEEK 0x20
#define RZN1_RTC_DAY 0x24
#define RZN1_RTC_MONTH 0x28
#define RZN1_RTC_YEAR 0x2c
#define RZN1_RTC_SUBU 0x38
#define RZN1_RTC_SUBU_DEV BIT(7)
#define RZN1_RTC_SUBU_DECR BIT(6)
#define RZN1_RTC_ALM 0x40
#define RZN1_RTC_ALH 0x44
#define RZN1_RTC_ALW 0x48
#define RZN1_RTC_SECC 0x4c
#define RZN1_RTC_MINC 0x50
#define RZN1_RTC_HOURC 0x54
#define RZN1_RTC_WEEKC 0x58
#define RZN1_RTC_DAYC 0x5c
#define RZN1_RTC_MONTHC 0x60
#define RZN1_RTC_YEARC 0x64
struct rzn1_rtc {
struct rtc_device *rtcdev;
void __iomem *base;
};
static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm)
{
tm->tm_sec = readl(rtc->base + RZN1_RTC_SECC);
tm->tm_min = readl(rtc->base + RZN1_RTC_MINC);
tm->tm_hour = readl(rtc->base + RZN1_RTC_HOURC);
tm->tm_wday = readl(rtc->base + RZN1_RTC_WEEKC);
tm->tm_mday = readl(rtc->base + RZN1_RTC_DAYC);
tm->tm_mon = readl(rtc->base + RZN1_RTC_MONTHC);
tm->tm_year = readl(rtc->base + RZN1_RTC_YEARC);
}
static unsigned int rzn1_rtc_tm_to_wday(struct rtc_time *tm)
{
time64_t time;
unsigned int days;
u32 secs;
time = rtc_tm_to_time64(tm);
days = div_s64_rem(time, 86400, &secs);
/* day of the week, 1970-01-01 was a Thursday */
return (days + 4) % 7;
}
static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
u32 val, secs;
/*
* The RTC was not started or is stopped and thus does not carry the
* proper time/date.
*/
val = readl(rtc->base + RZN1_RTC_CTL2);
if (val & RZN1_RTC_CTL2_STOPPED)
return -EINVAL;
rzn1_rtc_get_time_snapshot(rtc, tm);
secs = readl(rtc->base + RZN1_RTC_SECC);
if (tm->tm_sec != secs)
rzn1_rtc_get_time_snapshot(rtc, tm);
tm->tm_sec = bcd2bin(tm->tm_sec);
tm->tm_min = bcd2bin(tm->tm_min);
tm->tm_hour = bcd2bin(tm->tm_hour);
tm->tm_wday = bcd2bin(tm->tm_wday);
tm->tm_mday = bcd2bin(tm->tm_mday);
tm->tm_mon = bcd2bin(tm->tm_mon);
tm->tm_year = bcd2bin(tm->tm_year);
return 0;
}
static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
u32 val;
int ret;
tm->tm_sec = bin2bcd(tm->tm_sec);
tm->tm_min = bin2bcd(tm->tm_min);
tm->tm_hour = bin2bcd(tm->tm_hour);
tm->tm_wday = bin2bcd(rzn1_rtc_tm_to_wday(tm));
tm->tm_mday = bin2bcd(tm->tm_mday);
tm->tm_mon = bin2bcd(tm->tm_mon);
tm->tm_year = bin2bcd(tm->tm_year);
val = readl(rtc->base + RZN1_RTC_CTL2);
if (!(val & RZN1_RTC_CTL2_STOPPED)) {
/* Hold the counter if it was counting up */
writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2);
/* Wait for the counter to stop: two 32k clock cycles */
usleep_range(61, 100);
ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val,
val & RZN1_RTC_CTL2_WST, 0, 100);
if (ret)
return ret;
}
writel(tm->tm_sec, rtc->base + RZN1_RTC_SEC);
writel(tm->tm_min, rtc->base + RZN1_RTC_MIN);
writel(tm->tm_hour, rtc->base + RZN1_RTC_HOUR);
writel(tm->tm_wday, rtc->base + RZN1_RTC_WEEK);
writel(tm->tm_mday, rtc->base + RZN1_RTC_DAY);
writel(tm->tm_mon, rtc->base + RZN1_RTC_MONTH);
writel(tm->tm_year, rtc->base + RZN1_RTC_YEAR);
writel(0, rtc->base + RZN1_RTC_CTL2);
return 0;
}
static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id)
{
struct rzn1_rtc *rtc = dev_id;
rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF);
return IRQ_HANDLED;
}
static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
u32 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
if (enable)
ctl1 |= RZN1_RTC_CTL1_ALME;
else
ctl1 &= ~RZN1_RTC_CTL1_ALME;
writel(ctl1, rtc->base + RZN1_RTC_CTL1);
return 0;
}
static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
unsigned int min, hour, wday, delta_days;
time64_t alarm;
u32 ctl1;
int ret;
ret = rzn1_rtc_read_time(dev, tm);
if (ret)
return ret;
min = readl(rtc->base + RZN1_RTC_ALM);
hour = readl(rtc->base + RZN1_RTC_ALH);
wday = readl(rtc->base + RZN1_RTC_ALW);
tm->tm_sec = 0;
tm->tm_min = bcd2bin(min);
tm->tm_hour = bcd2bin(hour);
delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7;
tm->tm_wday = fls(wday) - 1;
if (delta_days) {
alarm = rtc_tm_to_time64(tm) + (delta_days * 86400);
rtc_time64_to_tm(alarm, tm);
}
ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
alrm->enabled = !!(ctl1 & RZN1_RTC_CTL1_ALME);
return 0;
}
static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time, tm_now;
unsigned long alarm, farest;
unsigned int days_ahead, wday;
int ret;
ret = rzn1_rtc_read_time(dev, &tm_now);
if (ret)
return ret;
/* We cannot set alarms more than one week ahead */
farest = rtc_tm_to_time64(&tm_now) + rtc->rtcdev->alarm_offset_max;
alarm = rtc_tm_to_time64(tm);
if (time_after(alarm, farest))
return -ERANGE;
/* Convert alarm day into week day */
days_ahead = tm->tm_mday - tm_now.tm_mday;
wday = (tm_now.tm_wday + days_ahead) % 7;
writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM);
writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH);
writel(BIT(wday), rtc->base + RZN1_RTC_ALW);
rzn1_rtc_alarm_irq_enable(dev, alrm->enabled);
return 0;
}
static int rzn1_rtc_read_offset(struct device *dev, long *offset)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
unsigned int ppb_per_step;
bool subtract;
u32 val;
val = readl(rtc->base + RZN1_RTC_SUBU);
ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051;
subtract = val & RZN1_RTC_SUBU_DECR;
val &= 0x3F;
if (!val)
*offset = 0;
else if (subtract)
*offset = -(((~val) & 0x3F) + 1) * ppb_per_step;
else
*offset = (val - 1) * ppb_per_step;
return 0;
}
static int rzn1_rtc_set_offset(struct device *dev, long offset)
{
struct rzn1_rtc *rtc = dev_get_drvdata(dev);
int stepsh, stepsl, steps;
u32 subu = 0, ctl2;
int ret;
/*
* Check which resolution mode (every 20 or 60s) can be used.
* Between 2 and 124 clock pulses can be added or substracted.
*
* In 20s mode, the minimum resolution is 2 / (32768 * 20) which is
* close to 3051 ppb. In 60s mode, the resolution is closer to 1017.
*/
stepsh = DIV_ROUND_CLOSEST(offset, 1017);
stepsl = DIV_ROUND_CLOSEST(offset, 3051);
if (stepsh >= -0x3E && stepsh <= 0x3E) {
/* 1017 ppb per step */
steps = stepsh;
subu |= RZN1_RTC_SUBU_DEV;
} else if (stepsl >= -0x3E && stepsl <= 0x3E) {
/* 3051 ppb per step */
steps = stepsl;
} else {
return -ERANGE;
}
if (!steps)
return 0;
if (steps > 0) {
subu |= steps + 1;
} else {
subu |= RZN1_RTC_SUBU_DECR;
subu |= (~(-steps - 1)) & 0x3F;
}
ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,
!(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000);
if (ret)
return ret;
writel(subu, rtc->base + RZN1_RTC_SUBU);
return 0;
}
static const struct rtc_class_ops rzn1_rtc_ops = {
.read_time = rzn1_rtc_read_time,
.set_time = rzn1_rtc_set_time,
.read_alarm = rzn1_rtc_read_alarm,
.set_alarm = rzn1_rtc_set_alarm,
.alarm_irq_enable = rzn1_rtc_alarm_irq_enable,
.read_offset = rzn1_rtc_read_offset,
.set_offset = rzn1_rtc_set_offset,
};
static int rzn1_rtc_probe(struct platform_device *pdev)
{
struct rzn1_rtc *rtc;
int alarm_irq;
int ret;
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
platform_set_drvdata(pdev, rtc);
rtc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->base))
return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n");
alarm_irq = platform_get_irq(pdev, 0);
if (alarm_irq < 0)
return alarm_irq;
rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc->rtcdev))
return PTR_ERR(rtc->rtcdev);
rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
rtc->rtcdev->alarm_offset_max = 7 * 86400;
rtc->rtcdev->ops = &rzn1_rtc_ops;
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features);
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret < 0)
return ret;
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret < 0)
return ret;
/*
* Ensure the clock counter is enabled.
* Set 24-hour mode and possible oscillator offset compensation in SUBU mode.
*/
writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
rtc->base + RZN1_RTC_CTL0);
/* Disable all interrupts */
writel(0, rtc->base + RZN1_RTC_CTL1);
ret = devm_request_irq(&pdev->dev, alarm_irq, rzn1_rtc_alarm_irq, 0,
dev_name(&pdev->dev), rtc);
if (ret) {
dev_err(&pdev->dev, "RTC timer interrupt not available\n");
goto dis_runtime_pm;
}
ret = devm_rtc_register_device(rtc->rtcdev);
if (ret)
goto dis_runtime_pm;
return 0;
dis_runtime_pm:
pm_runtime_put(&pdev->dev);
return ret;
}
static void rzn1_rtc_remove(struct platform_device *pdev)
{
pm_runtime_put(&pdev->dev);
}
static const struct of_device_id rzn1_rtc_of_match[] = {
{ .compatible = "renesas,rzn1-rtc" },
{},
};
MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match);
static struct platform_driver rzn1_rtc_driver = {
.probe = rzn1_rtc_probe,
.remove_new = rzn1_rtc_remove,
.driver = {
.name = "rzn1-rtc",
.of_match_table = rzn1_rtc_of_match,
},
};
module_platform_driver(rzn1_rtc_driver);
MODULE_AUTHOR("Michel Pollet <[email protected]");
MODULE_AUTHOR("Miquel Raynal <[email protected]");
MODULE_DESCRIPTION("RZ/N1 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-rzn1.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Driver for ST M41T93 SPI RTC
*
* (c) 2010 Nikolaus Voss, Weinmann Medical GmbH
*/
#include <linux/bcd.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#define M41T93_REG_SSEC 0
#define M41T93_REG_ST_SEC 1
#define M41T93_REG_MIN 2
#define M41T93_REG_CENT_HOUR 3
#define M41T93_REG_WDAY 4
#define M41T93_REG_DAY 5
#define M41T93_REG_MON 6
#define M41T93_REG_YEAR 7
#define M41T93_REG_ALM_HOUR_HT 0xc
#define M41T93_REG_FLAGS 0xf
#define M41T93_FLAG_ST (1 << 7)
#define M41T93_FLAG_OF (1 << 2)
#define M41T93_FLAG_BL (1 << 4)
#define M41T93_FLAG_HT (1 << 6)
static inline int m41t93_set_reg(struct spi_device *spi, u8 addr, u8 data)
{
u8 buf[2];
/* MSB must be '1' to write */
buf[0] = addr | 0x80;
buf[1] = data;
return spi_write(spi, buf, sizeof(buf));
}
static int m41t93_set_time(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
int tmp;
u8 buf[9] = {0x80}; /* write cmd + 8 data bytes */
u8 * const data = &buf[1]; /* ptr to first data byte */
dev_dbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"write", tm->tm_sec, tm->tm_min,
tm->tm_hour, tm->tm_mday,
tm->tm_mon, tm->tm_year, tm->tm_wday);
if (tm->tm_year < 100) {
dev_warn(&spi->dev, "unsupported date (before 2000-01-01).\n");
return -EINVAL;
}
tmp = spi_w8r8(spi, M41T93_REG_FLAGS);
if (tmp < 0)
return tmp;
if (tmp & M41T93_FLAG_OF) {
dev_warn(&spi->dev, "OF bit is set, resetting.\n");
m41t93_set_reg(spi, M41T93_REG_FLAGS, tmp & ~M41T93_FLAG_OF);
tmp = spi_w8r8(spi, M41T93_REG_FLAGS);
if (tmp < 0) {
return tmp;
} else if (tmp & M41T93_FLAG_OF) {
/* OF cannot be immediately reset: oscillator has to be
* restarted. */
u8 reset_osc = buf[M41T93_REG_ST_SEC] | M41T93_FLAG_ST;
dev_warn(&spi->dev,
"OF bit is still set, kickstarting clock.\n");
m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc);
reset_osc &= ~M41T93_FLAG_ST;
m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc);
}
}
data[M41T93_REG_SSEC] = 0;
data[M41T93_REG_ST_SEC] = bin2bcd(tm->tm_sec);
data[M41T93_REG_MIN] = bin2bcd(tm->tm_min);
data[M41T93_REG_CENT_HOUR] = bin2bcd(tm->tm_hour) |
((tm->tm_year/100-1) << 6);
data[M41T93_REG_DAY] = bin2bcd(tm->tm_mday);
data[M41T93_REG_WDAY] = bin2bcd(tm->tm_wday + 1);
data[M41T93_REG_MON] = bin2bcd(tm->tm_mon + 1);
data[M41T93_REG_YEAR] = bin2bcd(tm->tm_year % 100);
return spi_write(spi, buf, sizeof(buf));
}
static int m41t93_get_time(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
const u8 start_addr = 0;
u8 buf[8];
int century_after_1900;
int tmp;
int ret = 0;
/* Check status of clock. Two states must be considered:
1. halt bit (HT) is set: the clock is running but update of readout
registers has been disabled due to power failure. This is normal
case after poweron. Time is valid after resetting HT bit.
2. oscillator fail bit (OF) is set: time is invalid.
*/
tmp = spi_w8r8(spi, M41T93_REG_ALM_HOUR_HT);
if (tmp < 0)
return tmp;
if (tmp & M41T93_FLAG_HT) {
dev_dbg(&spi->dev, "HT bit is set, reenable clock update.\n");
m41t93_set_reg(spi, M41T93_REG_ALM_HOUR_HT,
tmp & ~M41T93_FLAG_HT);
}
tmp = spi_w8r8(spi, M41T93_REG_FLAGS);
if (tmp < 0)
return tmp;
if (tmp & M41T93_FLAG_OF) {
ret = -EINVAL;
dev_warn(&spi->dev, "OF bit is set, write time to restart.\n");
}
if (tmp & M41T93_FLAG_BL)
dev_warn(&spi->dev, "BL bit is set, replace battery.\n");
/* read actual time/date */
tmp = spi_write_then_read(spi, &start_addr, 1, buf, sizeof(buf));
if (tmp < 0)
return tmp;
tm->tm_sec = bcd2bin(buf[M41T93_REG_ST_SEC]);
tm->tm_min = bcd2bin(buf[M41T93_REG_MIN]);
tm->tm_hour = bcd2bin(buf[M41T93_REG_CENT_HOUR] & 0x3f);
tm->tm_mday = bcd2bin(buf[M41T93_REG_DAY]);
tm->tm_mon = bcd2bin(buf[M41T93_REG_MON]) - 1;
tm->tm_wday = bcd2bin(buf[M41T93_REG_WDAY] & 0x0f) - 1;
century_after_1900 = (buf[M41T93_REG_CENT_HOUR] >> 6) + 1;
tm->tm_year = bcd2bin(buf[M41T93_REG_YEAR]) + century_after_1900 * 100;
dev_dbg(dev, "%s secs=%d, mins=%d, "
"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
"read", tm->tm_sec, tm->tm_min,
tm->tm_hour, tm->tm_mday,
tm->tm_mon, tm->tm_year, tm->tm_wday);
return ret;
}
static const struct rtc_class_ops m41t93_rtc_ops = {
.read_time = m41t93_get_time,
.set_time = m41t93_set_time,
};
static struct spi_driver m41t93_driver;
static int m41t93_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
int res;
spi->bits_per_word = 8;
spi_setup(spi);
res = spi_w8r8(spi, M41T93_REG_WDAY);
if (res < 0 || (res & 0xf8) != 0) {
dev_err(&spi->dev, "not found 0x%x.\n", res);
return -ENODEV;
}
rtc = devm_rtc_device_register(&spi->dev, m41t93_driver.driver.name,
&m41t93_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
spi_set_drvdata(spi, rtc);
return 0;
}
static struct spi_driver m41t93_driver = {
.driver = {
.name = "rtc-m41t93",
},
.probe = m41t93_probe,
};
module_spi_driver(m41t93_driver);
MODULE_AUTHOR("Nikolaus Voss <[email protected]>");
MODULE_DESCRIPTION("Driver for ST M41T93 SPI RTC");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:rtc-m41t93");
| linux-master | drivers/rtc/rtc-m41t93.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An I2C driver for the Epson RX8581 RTC
*
* Author: Martyn Welch <[email protected]>
* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
*
* Based on: rtc-pcf8563.c (An I2C driver for the Philips PCF8563 RTC)
* Copyright 2005-06 Tower Technologies
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/log2.h>
#define RX8581_REG_SC 0x00 /* Second in BCD */
#define RX8581_REG_MN 0x01 /* Minute in BCD */
#define RX8581_REG_HR 0x02 /* Hour in BCD */
#define RX8581_REG_DW 0x03 /* Day of Week */
#define RX8581_REG_DM 0x04 /* Day of Month in BCD */
#define RX8581_REG_MO 0x05 /* Month in BCD */
#define RX8581_REG_YR 0x06 /* Year in BCD */
#define RX8581_REG_RAM 0x07 /* RAM */
#define RX8581_REG_AMN 0x08 /* Alarm Min in BCD*/
#define RX8581_REG_AHR 0x09 /* Alarm Hour in BCD */
#define RX8581_REG_ADM 0x0A
#define RX8581_REG_ADW 0x0A
#define RX8581_REG_TMR0 0x0B
#define RX8581_REG_TMR1 0x0C
#define RX8581_REG_EXT 0x0D /* Extension Register */
#define RX8581_REG_FLAG 0x0E /* Flag Register */
#define RX8581_REG_CTRL 0x0F /* Control Register */
/* Flag Register bit definitions */
#define RX8581_FLAG_UF 0x20 /* Update */
#define RX8581_FLAG_TF 0x10 /* Timer */
#define RX8581_FLAG_AF 0x08 /* Alarm */
#define RX8581_FLAG_VLF 0x02 /* Voltage Low */
/* Control Register bit definitions */
#define RX8581_CTRL_UIE 0x20 /* Update Interrupt Enable */
#define RX8581_CTRL_TIE 0x10 /* Timer Interrupt Enable */
#define RX8581_CTRL_AIE 0x08 /* Alarm Interrupt Enable */
#define RX8581_CTRL_STOP 0x02 /* STOP bit */
#define RX8581_CTRL_RESET 0x01 /* RESET bit */
#define RX8571_USER_RAM 0x10
#define RX8571_NVRAM_SIZE 0x10
struct rx8581 {
struct regmap *regmap;
struct rtc_device *rtc;
};
struct rx85x1_config {
struct regmap_config regmap;
unsigned int num_nvram;
};
/*
* In the routines that deal directly with the rx8581 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
*/
static int rx8581_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned char date[7];
unsigned int data;
int err;
struct rx8581 *rx8581 = i2c_get_clientdata(client);
/* First we ensure that the "update flag" is not set, we read the
* time and date then re-read the "update flag". If the update flag
* has been set, we know that the time has changed during the read so
* we repeat the whole process again.
*/
err = regmap_read(rx8581->regmap, RX8581_REG_FLAG, &data);
if (err < 0)
return err;
if (data & RX8581_FLAG_VLF) {
dev_warn(dev,
"low voltage detected, date/time is not reliable.\n");
return -EINVAL;
}
do {
/* If update flag set, clear it */
if (data & RX8581_FLAG_UF) {
err = regmap_write(rx8581->regmap, RX8581_REG_FLAG,
data & ~RX8581_FLAG_UF);
if (err < 0)
return err;
}
/* Now read time and date */
err = regmap_bulk_read(rx8581->regmap, RX8581_REG_SC, date,
sizeof(date));
if (err < 0)
return err;
/* Check flag register */
err = regmap_read(rx8581->regmap, RX8581_REG_FLAG, &data);
if (err < 0)
return err;
} while (data & RX8581_FLAG_UF);
dev_dbg(dev, "%s: raw data is sec=%02x, min=%02x, hr=%02x, "
"wday=%02x, mday=%02x, mon=%02x, year=%02x\n",
__func__,
date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
tm->tm_sec = bcd2bin(date[RX8581_REG_SC] & 0x7F);
tm->tm_min = bcd2bin(date[RX8581_REG_MN] & 0x7F);
tm->tm_hour = bcd2bin(date[RX8581_REG_HR] & 0x3F); /* rtc hr 0-23 */
tm->tm_wday = ilog2(date[RX8581_REG_DW] & 0x7F);
tm->tm_mday = bcd2bin(date[RX8581_REG_DM] & 0x3F);
tm->tm_mon = bcd2bin(date[RX8581_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
tm->tm_year = bcd2bin(date[RX8581_REG_YR]) + 100;
dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__func__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
return 0;
}
static int rx8581_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
int err;
unsigned char buf[7];
struct rx8581 *rx8581 = i2c_get_clientdata(client);
dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__func__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
/* hours, minutes and seconds */
buf[RX8581_REG_SC] = bin2bcd(tm->tm_sec);
buf[RX8581_REG_MN] = bin2bcd(tm->tm_min);
buf[RX8581_REG_HR] = bin2bcd(tm->tm_hour);
buf[RX8581_REG_DM] = bin2bcd(tm->tm_mday);
/* month, 1 - 12 */
buf[RX8581_REG_MO] = bin2bcd(tm->tm_mon + 1);
/* year and century */
buf[RX8581_REG_YR] = bin2bcd(tm->tm_year - 100);
buf[RX8581_REG_DW] = (0x1 << tm->tm_wday);
/* Stop the clock */
err = regmap_update_bits(rx8581->regmap, RX8581_REG_CTRL,
RX8581_CTRL_STOP, RX8581_CTRL_STOP);
if (err < 0)
return err;
/* write register's data */
err = regmap_bulk_write(rx8581->regmap, RX8581_REG_SC,
buf, sizeof(buf));
if (err < 0)
return err;
/* get VLF and clear it */
err = regmap_update_bits(rx8581->regmap, RX8581_REG_FLAG,
RX8581_FLAG_VLF, 0);
if (err < 0)
return err;
/* Restart the clock */
return regmap_update_bits(rx8581->regmap, RX8581_REG_CTRL,
RX8581_CTRL_STOP, 0);
}
static const struct rtc_class_ops rx8581_rtc_ops = {
.read_time = rx8581_rtc_read_time,
.set_time = rx8581_rtc_set_time,
};
static int rx8571_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct rx8581 *rx8581 = priv;
return regmap_bulk_read(rx8581->regmap, RX8571_USER_RAM + offset,
val, bytes);
}
static int rx8571_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct rx8581 *rx8581 = priv;
return regmap_bulk_write(rx8581->regmap, RX8571_USER_RAM + offset,
val, bytes);
}
static int rx85x1_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct rx8581 *rx8581 = priv;
unsigned int tmp_val;
int ret;
ret = regmap_read(rx8581->regmap, RX8581_REG_RAM, &tmp_val);
(*(unsigned char *)val) = (unsigned char) tmp_val;
return ret;
}
static int rx85x1_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
struct rx8581 *rx8581 = priv;
unsigned char tmp_val;
tmp_val = *((unsigned char *)val);
return regmap_write(rx8581->regmap, RX8581_REG_RAM,
(unsigned int)tmp_val);
}
static const struct rx85x1_config rx8581_config = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xf,
},
.num_nvram = 1
};
static const struct rx85x1_config rx8571_config = {
.regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0x1f,
},
.num_nvram = 2
};
static int rx8581_probe(struct i2c_client *client)
{
struct rx8581 *rx8581;
const struct rx85x1_config *config = &rx8581_config;
const void *data = of_device_get_match_data(&client->dev);
static struct nvmem_config nvmem_cfg[] = {
{
.name = "rx85x1-",
.word_size = 1,
.stride = 1,
.size = 1,
.reg_read = rx85x1_nvram_read,
.reg_write = rx85x1_nvram_write,
}, {
.name = "rx8571-",
.word_size = 1,
.stride = 1,
.size = RX8571_NVRAM_SIZE,
.reg_read = rx8571_nvram_read,
.reg_write = rx8571_nvram_write,
},
};
int ret, i;
dev_dbg(&client->dev, "%s\n", __func__);
if (data)
config = data;
rx8581 = devm_kzalloc(&client->dev, sizeof(struct rx8581), GFP_KERNEL);
if (!rx8581)
return -ENOMEM;
i2c_set_clientdata(client, rx8581);
rx8581->regmap = devm_regmap_init_i2c(client, &config->regmap);
if (IS_ERR(rx8581->regmap))
return PTR_ERR(rx8581->regmap);
rx8581->rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(rx8581->rtc))
return PTR_ERR(rx8581->rtc);
rx8581->rtc->ops = &rx8581_rtc_ops;
rx8581->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rx8581->rtc->range_max = RTC_TIMESTAMP_END_2099;
rx8581->rtc->start_secs = 0;
rx8581->rtc->set_start_time = true;
ret = devm_rtc_register_device(rx8581->rtc);
for (i = 0; i < config->num_nvram; i++) {
nvmem_cfg[i].priv = rx8581;
devm_rtc_nvmem_register(rx8581->rtc, &nvmem_cfg[i]);
}
return ret;
}
static const struct i2c_device_id rx8581_id[] = {
{ "rx8581", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rx8581_id);
static const __maybe_unused struct of_device_id rx8581_of_match[] = {
{ .compatible = "epson,rx8571", .data = &rx8571_config },
{ .compatible = "epson,rx8581", .data = &rx8581_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rx8581_of_match);
static struct i2c_driver rx8581_driver = {
.driver = {
.name = "rtc-rx8581",
.of_match_table = of_match_ptr(rx8581_of_match),
},
.probe = rx8581_probe,
.id_table = rx8581_id,
};
module_i2c_driver(rx8581_driver);
MODULE_AUTHOR("Martyn Welch <[email protected]>");
MODULE_DESCRIPTION("Epson RX-8571/RX-8581 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-rx8581.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
* chips.
*
* Copyright (C) 2011-2014 Joshua Kinard <[email protected]>.
* Copyright (C) 2009 Matthias Fuchs <[email protected]>.
*
* References:
* DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
* DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
* DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
* Application Note 90, Using the Multiplex Bus RTC Extended Features.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/workqueue.h>
#include <linux/rtc/ds1685.h>
#ifdef CONFIG_PROC_FS
#include <linux/proc_fs.h>
#endif
/* ----------------------------------------------------------------------- */
/*
* Standard read/write
* all registers are mapped in CPU address space
*/
/**
* ds1685_read - read a value from an rtc register.
* @rtc: pointer to the ds1685 rtc structure.
* @reg: the register address to read.
*/
static u8
ds1685_read(struct ds1685_priv *rtc, int reg)
{
return readb((u8 __iomem *)rtc->regs +
(reg * rtc->regstep));
}
/**
* ds1685_write - write a value to an rtc register.
* @rtc: pointer to the ds1685 rtc structure.
* @reg: the register address to write.
* @value: value to write to the register.
*/
static void
ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
{
writeb(value, ((u8 __iomem *)rtc->regs +
(reg * rtc->regstep)));
}
/* ----------------------------------------------------------------------- */
/*
* Indirect read/write functions
* access happens via address and data register mapped in CPU address space
*/
/**
* ds1685_indirect_read - read a value from an rtc register.
* @rtc: pointer to the ds1685 rtc structure.
* @reg: the register address to read.
*/
static u8
ds1685_indirect_read(struct ds1685_priv *rtc, int reg)
{
writeb(reg, rtc->regs);
return readb(rtc->data);
}
/**
* ds1685_indirect_write - write a value to an rtc register.
* @rtc: pointer to the ds1685 rtc structure.
* @reg: the register address to write.
* @value: value to write to the register.
*/
static void
ds1685_indirect_write(struct ds1685_priv *rtc, int reg, u8 value)
{
writeb(reg, rtc->regs);
writeb(value, rtc->data);
}
/* ----------------------------------------------------------------------- */
/* Inlined functions */
/**
* ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
* @rtc: pointer to the ds1685 rtc structure.
* @val: u8 time value to consider converting.
* @bcd_mask: u8 mask value if BCD mode is used.
* @bin_mask: u8 mask value if BIN mode is used.
*
* Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
*/
static inline u8
ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
{
if (rtc->bcd_mode)
return (bcd2bin(val) & bcd_mask);
return (val & bin_mask);
}
/**
* ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
* @rtc: pointer to the ds1685 rtc structure.
* @val: u8 time value to consider converting.
* @bin_mask: u8 mask value if BIN mode is used.
* @bcd_mask: u8 mask value if BCD mode is used.
*
* Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
*/
static inline u8
ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
{
if (rtc->bcd_mode)
return (bin2bcd(val) & bcd_mask);
return (val & bin_mask);
}
/**
* ds1685_rtc_check_mday - check validity of the day of month.
* @rtc: pointer to the ds1685 rtc structure.
* @mday: day of month.
*
* Returns -EDOM if the day of month is not within 1..31 range.
*/
static inline int
ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
{
if (rtc->bcd_mode) {
if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
return -EDOM;
} else {
if (mday < 1 || mday > 31)
return -EDOM;
}
return 0;
}
/**
* ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
* @rtc: pointer to the ds1685 rtc structure.
*/
static inline void
ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
{
rtc->write(rtc, RTC_CTRL_A,
(rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
}
/**
* ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
* @rtc: pointer to the ds1685 rtc structure.
*/
static inline void
ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
{
rtc->write(rtc, RTC_CTRL_A,
(rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
}
/**
* ds1685_rtc_begin_data_access - prepare the rtc for data access.
* @rtc: pointer to the ds1685 rtc structure.
*
* This takes several steps to prepare the rtc for access to get/set time
* and alarm values from the rtc registers:
* - Sets the SET bit in Control Register B.
* - Reads Ext Control Register 4A and checks the INCR bit.
* - If INCR is active, a short delay is added before Ext Control Register 4A
* is read again in a loop until INCR is inactive.
* - Switches the rtc to bank 1. This allows access to all relevant
* data for normal rtc operation, as bank 0 contains only the nvram.
*/
static inline void
ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
{
/* Set the SET bit in Ctrl B */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
/* Switch to Bank 1 */
ds1685_rtc_switch_to_bank1(rtc);
/* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
cpu_relax();
}
/**
* ds1685_rtc_end_data_access - end data access on the rtc.
* @rtc: pointer to the ds1685 rtc structure.
*
* This ends what was started by ds1685_rtc_begin_data_access:
* - Switches the rtc back to bank 0.
* - Clears the SET bit in Control Register B.
*/
static inline void
ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
{
/* Switch back to Bank 0 */
ds1685_rtc_switch_to_bank0(rtc);
/* Clear the SET bit in Ctrl B */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
}
/**
* ds1685_rtc_get_ssn - retrieve the silicon serial number.
* @rtc: pointer to the ds1685 rtc structure.
* @ssn: u8 array to hold the bits of the silicon serial number.
*
* This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
* first byte is the model number, the next six bytes are the serial number
* digits, and the final byte is a CRC check byte. Together, they form the
* silicon serial number.
*
* These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
* called first before calling this function, else data will be read out of
* the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
*/
static inline void
ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
{
ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* Read/Set Time & Alarm functions */
/**
* ds1685_rtc_read_time - reads the time registers.
* @dev: pointer to device structure.
* @tm: pointer to rtc_time structure.
*/
static int
ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
u8 century;
u8 seconds, minutes, hours, wday, mday, month, years;
/* Fetch the time info from the RTC registers. */
ds1685_rtc_begin_data_access(rtc);
seconds = rtc->read(rtc, RTC_SECS);
minutes = rtc->read(rtc, RTC_MINS);
hours = rtc->read(rtc, RTC_HRS);
wday = rtc->read(rtc, RTC_WDAY);
mday = rtc->read(rtc, RTC_MDAY);
month = rtc->read(rtc, RTC_MONTH);
years = rtc->read(rtc, RTC_YEAR);
century = rtc->read(rtc, RTC_CENTURY);
ds1685_rtc_end_data_access(rtc);
/* bcd2bin if needed, perform fixups, and store to rtc_time. */
years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
RTC_YEAR_BIN_MASK);
century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
RTC_CENTURY_MASK);
tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
RTC_SECS_BIN_MASK);
tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
RTC_MINS_BIN_MASK);
tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
RTC_HRS_24_BIN_MASK);
tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
RTC_WDAY_MASK) - 1);
tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
RTC_MDAY_BIN_MASK);
tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
RTC_MONTH_BIN_MASK) - 1);
tm->tm_year = ((years + (century * 100)) - 1900);
tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
return 0;
}
/**
* ds1685_rtc_set_time - sets the time registers.
* @dev: pointer to device structure.
* @tm: pointer to rtc_time structure.
*/
static int
ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
/* Fetch the time info from rtc_time. */
seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
RTC_SECS_BCD_MASK);
minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
RTC_MINS_BCD_MASK);
hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK);
wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
RTC_WDAY_MASK);
mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
RTC_MDAY_BCD_MASK);
month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
RTC_MONTH_BCD_MASK);
years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
RTC_CENTURY_MASK, RTC_CENTURY_MASK);
/*
* Perform Sanity Checks:
* - Months: !> 12, Month Day != 0.
* - Month Day !> Max days in current month.
* - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
*/
if ((tm->tm_mon > 11) || (mday == 0))
return -EDOM;
if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
return -EDOM;
if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
(tm->tm_sec >= 60) || (wday > 7))
return -EDOM;
/*
* Set the data mode to use and store the time values in the
* RTC registers.
*/
ds1685_rtc_begin_data_access(rtc);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (rtc->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
rtc->write(rtc, RTC_SECS, seconds);
rtc->write(rtc, RTC_MINS, minutes);
rtc->write(rtc, RTC_HRS, hours);
rtc->write(rtc, RTC_WDAY, wday);
rtc->write(rtc, RTC_MDAY, mday);
rtc->write(rtc, RTC_MONTH, month);
rtc->write(rtc, RTC_YEAR, years);
rtc->write(rtc, RTC_CENTURY, century);
ds1685_rtc_end_data_access(rtc);
return 0;
}
/**
* ds1685_rtc_read_alarm - reads the alarm registers.
* @dev: pointer to device structure.
* @alrm: pointer to rtc_wkalrm structure.
*
* There are three primary alarm registers: seconds, minutes, and hours.
* A fourth alarm register for the month date is also available in bank1 for
* kickstart/wakeup features. The DS1685/DS1687 manual states that a
* "don't care" value ranging from 0xc0 to 0xff may be written into one or
* more of the three alarm bytes to act as a wildcard value. The fourth
* byte doesn't support a "don't care" value.
*/
static int
ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
int ret;
/* Fetch the alarm info from the RTC alarm registers. */
ds1685_rtc_begin_data_access(rtc);
seconds = rtc->read(rtc, RTC_SECS_ALARM);
minutes = rtc->read(rtc, RTC_MINS_ALARM);
hours = rtc->read(rtc, RTC_HRS_ALARM);
mday = rtc->read(rtc, RTC_MDAY_ALARM);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
ds1685_rtc_end_data_access(rtc);
/* Check the month date for validity. */
ret = ds1685_rtc_check_mday(rtc, mday);
if (ret)
return ret;
/*
* Check the three alarm bytes.
*
* The Linux RTC system doesn't support the "don't care" capability
* of this RTC chip. We check for it anyways in case support is
* added in the future and only assign when we care.
*/
if (likely(seconds < 0xc0))
alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
RTC_SECS_BCD_MASK,
RTC_SECS_BIN_MASK);
if (likely(minutes < 0xc0))
alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
RTC_MINS_BCD_MASK,
RTC_MINS_BIN_MASK);
if (likely(hours < 0xc0))
alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
RTC_HRS_24_BCD_MASK,
RTC_HRS_24_BIN_MASK);
/* Write the data to rtc_wkalrm. */
alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
RTC_MDAY_BIN_MASK);
alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
return 0;
}
/**
* ds1685_rtc_set_alarm - sets the alarm in registers.
* @dev: pointer to device structure.
* @alrm: pointer to rtc_wkalrm structure.
*/
static int
ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
u8 ctrlb, seconds, minutes, hours, mday;
int ret;
/* Fetch the alarm info and convert to BCD. */
seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
RTC_SECS_BIN_MASK,
RTC_SECS_BCD_MASK);
minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
RTC_MINS_BIN_MASK,
RTC_MINS_BCD_MASK);
hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK);
mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
RTC_MDAY_BIN_MASK,
RTC_MDAY_BCD_MASK);
/* Check the month date for validity. */
ret = ds1685_rtc_check_mday(rtc, mday);
if (ret)
return ret;
/*
* Check the three alarm bytes.
*
* The Linux RTC system doesn't support the "don't care" capability
* of this RTC chip because rtc_valid_tm tries to validate every
* field, and we only support four fields. We put the support
* here anyways for the future.
*/
if (unlikely(seconds >= 0xc0))
seconds = 0xff;
if (unlikely(minutes >= 0xc0))
minutes = 0xff;
if (unlikely(hours >= 0xc0))
hours = 0xff;
alrm->time.tm_mon = -1;
alrm->time.tm_year = -1;
alrm->time.tm_wday = -1;
alrm->time.tm_yday = -1;
alrm->time.tm_isdst = -1;
/* Disable the alarm interrupt first. */
ds1685_rtc_begin_data_access(rtc);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
/* Read ctrlc to clear RTC_CTRL_C_AF. */
rtc->read(rtc, RTC_CTRL_C);
/*
* Set the data mode to use and store the time values in the
* RTC registers.
*/
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (rtc->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
rtc->write(rtc, RTC_SECS_ALARM, seconds);
rtc->write(rtc, RTC_MINS_ALARM, minutes);
rtc->write(rtc, RTC_HRS_ALARM, hours);
rtc->write(rtc, RTC_MDAY_ALARM, mday);
/* Re-enable the alarm if needed. */
if (alrm->enabled) {
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlb |= RTC_CTRL_B_AIE;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
}
/* Done! */
ds1685_rtc_end_data_access(rtc);
return 0;
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* /dev/rtcX Interface functions */
/**
* ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
* @dev: pointer to device structure.
* @enabled: flag indicating whether to enable or disable.
*/
static int
ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
/* Flip the requisite interrupt-enable bit. */
if (enabled)
rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
RTC_CTRL_B_AIE));
else
rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
~(RTC_CTRL_B_AIE)));
/* Read Control C to clear all the flag bits. */
rtc->read(rtc, RTC_CTRL_C);
return 0;
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* IRQ handler */
/**
* ds1685_rtc_extended_irq - take care of extended interrupts
* @rtc: pointer to the ds1685 rtc structure.
* @pdev: platform device pointer.
*/
static void
ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev)
{
u8 ctrl4a, ctrl4b;
ds1685_rtc_switch_to_bank1(rtc);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
/*
* Check for a kickstart interrupt. With Vcc applied, this
* typically means that the power button was pressed, so we
* begin the shutdown sequence.
*/
if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
/* Briefly disable kickstarts to debounce button presses. */
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) &
~(RTC_CTRL_4B_KSE)));
/* Clear the kickstart flag. */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_KF)));
/*
* Sleep 500ms before re-enabling kickstarts. This allows
* adequate time to avoid reading signal jitter as additional
* button presses.
*/
msleep(500);
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) |
RTC_CTRL_4B_KSE));
/* Call the platform pre-poweroff function. Else, shutdown. */
if (rtc->prepare_poweroff != NULL)
rtc->prepare_poweroff();
else
ds1685_rtc_poweroff(pdev);
}
/*
* Check for a wake-up interrupt. With Vcc applied, this is
* essentially a second alarm interrupt, except it takes into
* account the 'date' register in bank1 in addition to the
* standard three alarm registers.
*/
if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_WF)));
/* Call the platform wake_alarm function if defined. */
if (rtc->wake_alarm != NULL)
rtc->wake_alarm();
else
dev_warn(&pdev->dev,
"Wake Alarm IRQ just occurred!\n");
}
/*
* Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
* when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
* each byte to a logic 1. This has no effect on any extended
* NV-SRAM that might be present, nor on the time/calendar/alarm
* registers. After a ram-clear is completed, there is a minimum
* recovery time of ~150ms in which all reads/writes are locked out.
* NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
* catch this scenario.
*/
if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_RF)));
msleep(150);
/* Call the platform post_ram_clear function if defined. */
if (rtc->post_ram_clear != NULL)
rtc->post_ram_clear();
else
dev_warn(&pdev->dev,
"RAM-Clear IRQ just occurred!\n");
}
ds1685_rtc_switch_to_bank0(rtc);
}
/**
* ds1685_rtc_irq_handler - IRQ handler.
* @irq: IRQ number.
* @dev_id: platform device pointer.
*/
static irqreturn_t
ds1685_rtc_irq_handler(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, ctrlc;
unsigned long events = 0;
u8 num_irqs = 0;
/* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
if (unlikely(!rtc))
return IRQ_HANDLED;
rtc_lock(rtc->dev);
/* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
/* Is the IRQF bit set? */
if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
/*
* We need to determine if it was one of the standard
* events: PF, AF, or UF. If so, we handle them and
* update the RTC core.
*/
if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
events = RTC_IRQF;
/* Check for a periodic interrupt. */
if ((ctrlb & RTC_CTRL_B_PIE) &&
(ctrlc & RTC_CTRL_C_PF)) {
events |= RTC_PF;
num_irqs++;
}
/* Check for an alarm interrupt. */
if ((ctrlb & RTC_CTRL_B_AIE) &&
(ctrlc & RTC_CTRL_C_AF)) {
events |= RTC_AF;
num_irqs++;
}
/* Check for an update interrupt. */
if ((ctrlb & RTC_CTRL_B_UIE) &&
(ctrlc & RTC_CTRL_C_UF)) {
events |= RTC_UF;
num_irqs++;
}
} else {
/*
* One of the "extended" interrupts was received that
* is not recognized by the RTC core.
*/
ds1685_rtc_extended_irq(rtc, pdev);
}
}
rtc_update_irq(rtc->dev, num_irqs, events);
rtc_unlock(rtc->dev);
return events ? IRQ_HANDLED : IRQ_NONE;
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* ProcFS interface */
#ifdef CONFIG_PROC_FS
#define NUM_REGS 6 /* Num of control registers. */
#define NUM_BITS 8 /* Num bits per register. */
#define NUM_SPACES 4 /* Num spaces between each bit. */
/*
* Periodic Interrupt Rates.
*/
static const char *ds1685_rtc_pirq_rate[16] = {
"none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
"0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
"15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
};
/*
* Square-Wave Output Frequencies.
*/
static const char *ds1685_rtc_sqw_freq[16] = {
"none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
"512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
};
/**
* ds1685_rtc_proc - procfs access function.
* @dev: pointer to device structure.
* @seq: pointer to seq_file structure.
*/
static int
ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
u8 ctrla, ctrlb, ctrld, ctrl4a, ctrl4b, ssn[8];
char *model;
/* Read all the relevant data from the control registers. */
ds1685_rtc_switch_to_bank1(rtc);
ds1685_rtc_get_ssn(rtc, ssn);
ctrla = rtc->read(rtc, RTC_CTRL_A);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrld = rtc->read(rtc, RTC_CTRL_D);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
ds1685_rtc_switch_to_bank0(rtc);
/* Determine the RTC model. */
switch (ssn[0]) {
case RTC_MODEL_DS1685:
model = "DS1685/DS1687\0";
break;
case RTC_MODEL_DS1689:
model = "DS1689/DS1693\0";
break;
case RTC_MODEL_DS17285:
model = "DS17285/DS17287\0";
break;
case RTC_MODEL_DS17485:
model = "DS17485/DS17487\0";
break;
case RTC_MODEL_DS17885:
model = "DS17885/DS17887\0";
break;
default:
model = "Unknown\0";
break;
}
/* Print out the information. */
seq_printf(seq,
"Model\t\t: %s\n"
"Oscillator\t: %s\n"
"12/24hr\t\t: %s\n"
"DST\t\t: %s\n"
"Data mode\t: %s\n"
"Battery\t\t: %s\n"
"Aux batt\t: %s\n"
"Update IRQ\t: %s\n"
"Periodic IRQ\t: %s\n"
"Periodic Rate\t: %s\n"
"SQW Freq\t: %s\n"
"Serial #\t: %8phC\n",
model,
((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
(!(ctrl4b & RTC_CTRL_4B_E32K) ?
ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
(!((ctrl4b & RTC_CTRL_4B_E32K)) ?
ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
ssn);
return 0;
}
#else
#define ds1685_rtc_proc NULL
#endif /* CONFIG_PROC_FS */
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* RTC Class operations */
static const struct rtc_class_ops
ds1685_rtc_ops = {
.proc = ds1685_rtc_proc,
.read_time = ds1685_rtc_read_time,
.set_time = ds1685_rtc_set_time,
.read_alarm = ds1685_rtc_read_alarm,
.set_alarm = ds1685_rtc_set_alarm,
.alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
};
/* ----------------------------------------------------------------------- */
static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
size_t size)
{
struct ds1685_priv *rtc = priv;
struct mutex *rtc_mutex = &rtc->dev->ops_lock;
ssize_t count;
u8 *buf = val;
int err;
err = mutex_lock_interruptible(rtc_mutex);
if (err)
return err;
ds1685_rtc_switch_to_bank0(rtc);
/* Read NVRAM in time and bank0 registers. */
for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
count++, size--) {
if (count < NVRAM_SZ_TIME)
*buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
else
*buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
}
#ifndef CONFIG_RTC_DRV_DS1689
if (size > 0) {
ds1685_rtc_switch_to_bank1(rtc);
#ifndef CONFIG_RTC_DRV_DS1685
/* Enable burst-mode on DS17x85/DS17x87 */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) |
RTC_CTRL_4A_BME));
/* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
* reading with burst-mode */
rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
(pos - NVRAM_TOTAL_SZ_BANK0));
#endif
/* Read NVRAM in bank1 registers. */
for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
count++, size--) {
#ifdef CONFIG_RTC_DRV_DS1685
/* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
* before each read. */
rtc->write(rtc, RTC_BANK1_RAM_ADDR,
(pos - NVRAM_TOTAL_SZ_BANK0));
#endif
*buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
pos++;
}
#ifndef CONFIG_RTC_DRV_DS1685
/* Disable burst-mode on DS17x85/DS17x87 */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) &
~(RTC_CTRL_4A_BME)));
#endif
ds1685_rtc_switch_to_bank0(rtc);
}
#endif /* !CONFIG_RTC_DRV_DS1689 */
mutex_unlock(rtc_mutex);
return 0;
}
static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
size_t size)
{
struct ds1685_priv *rtc = priv;
struct mutex *rtc_mutex = &rtc->dev->ops_lock;
ssize_t count;
u8 *buf = val;
int err;
err = mutex_lock_interruptible(rtc_mutex);
if (err)
return err;
ds1685_rtc_switch_to_bank0(rtc);
/* Write NVRAM in time and bank0 registers. */
for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
count++, size--)
if (count < NVRAM_SZ_TIME)
rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
*buf++);
else
rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
#ifndef CONFIG_RTC_DRV_DS1689
if (size > 0) {
ds1685_rtc_switch_to_bank1(rtc);
#ifndef CONFIG_RTC_DRV_DS1685
/* Enable burst-mode on DS17x85/DS17x87 */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) |
RTC_CTRL_4A_BME));
/* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
* writing with burst-mode */
rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
(pos - NVRAM_TOTAL_SZ_BANK0));
#endif
/* Write NVRAM in bank1 registers. */
for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
count++, size--) {
#ifdef CONFIG_RTC_DRV_DS1685
/* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
* before each read. */
rtc->write(rtc, RTC_BANK1_RAM_ADDR,
(pos - NVRAM_TOTAL_SZ_BANK0));
#endif
rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
pos++;
}
#ifndef CONFIG_RTC_DRV_DS1685
/* Disable burst-mode on DS17x85/DS17x87 */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) &
~(RTC_CTRL_4A_BME)));
#endif
ds1685_rtc_switch_to_bank0(rtc);
}
#endif /* !CONFIG_RTC_DRV_DS1689 */
mutex_unlock(rtc_mutex);
return 0;
}
/* ----------------------------------------------------------------------- */
/* SysFS interface */
/**
* ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
* @dev: pointer to device structure.
* @attr: pointer to device_attribute structure.
* @buf: pointer to char array to hold the output.
*/
static ssize_t
ds1685_rtc_sysfs_battery_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
u8 ctrld;
ctrld = rtc->read(rtc, RTC_CTRL_D);
return sprintf(buf, "%s\n",
(ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
}
static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
/**
* ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
* @dev: pointer to device structure.
* @attr: pointer to device_attribute structure.
* @buf: pointer to char array to hold the output.
*/
static ssize_t
ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
u8 ctrl4a;
ds1685_rtc_switch_to_bank1(rtc);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ds1685_rtc_switch_to_bank0(rtc);
return sprintf(buf, "%s\n",
(ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
}
static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
/**
* ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
* @dev: pointer to device structure.
* @attr: pointer to device_attribute structure.
* @buf: pointer to char array to hold the output.
*/
static ssize_t
ds1685_rtc_sysfs_serial_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
u8 ssn[8];
ds1685_rtc_switch_to_bank1(rtc);
ds1685_rtc_get_ssn(rtc, ssn);
ds1685_rtc_switch_to_bank0(rtc);
return sprintf(buf, "%8phC\n", ssn);
}
static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
/*
* struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
*/
static struct attribute*
ds1685_rtc_sysfs_misc_attrs[] = {
&dev_attr_battery.attr,
&dev_attr_auxbatt.attr,
&dev_attr_serial.attr,
NULL,
};
/*
* struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
*/
static const struct attribute_group
ds1685_rtc_sysfs_misc_grp = {
.name = "misc",
.attrs = ds1685_rtc_sysfs_misc_attrs,
};
/* ----------------------------------------------------------------------- */
/* Driver Probe/Removal */
/**
* ds1685_rtc_probe - initializes rtc driver.
* @pdev: pointer to platform_device structure.
*/
static int
ds1685_rtc_probe(struct platform_device *pdev)
{
struct rtc_device *rtc_dev;
struct ds1685_priv *rtc;
struct ds1685_rtc_platform_data *pdata;
u8 ctrla, ctrlb, hours;
unsigned char am_pm;
int ret = 0;
struct nvmem_config nvmem_cfg = {
.name = "ds1685_nvram",
.size = NVRAM_TOTAL_SZ,
.reg_read = ds1685_nvram_read,
.reg_write = ds1685_nvram_write,
};
/* Get the platform data. */
pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
if (!pdata)
return -ENODEV;
/* Allocate memory for the rtc device. */
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
if (!rtc)
return -ENOMEM;
/* Setup resources and access functions */
switch (pdata->access_type) {
case ds1685_reg_direct:
rtc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->regs))
return PTR_ERR(rtc->regs);
rtc->read = ds1685_read;
rtc->write = ds1685_write;
break;
case ds1685_reg_indirect:
rtc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rtc->regs))
return PTR_ERR(rtc->regs);
rtc->data = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(rtc->data))
return PTR_ERR(rtc->data);
rtc->read = ds1685_indirect_read;
rtc->write = ds1685_indirect_write;
break;
}
if (!rtc->read || !rtc->write)
return -ENXIO;
/* Get the register step size. */
if (pdata->regstep > 0)
rtc->regstep = pdata->regstep;
else
rtc->regstep = 1;
/* Platform pre-shutdown function, if defined. */
if (pdata->plat_prepare_poweroff)
rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
/* Platform wake_alarm function, if defined. */
if (pdata->plat_wake_alarm)
rtc->wake_alarm = pdata->plat_wake_alarm;
/* Platform post_ram_clear function, if defined. */
if (pdata->plat_post_ram_clear)
rtc->post_ram_clear = pdata->plat_post_ram_clear;
/* set the driver data. */
platform_set_drvdata(pdev, rtc);
/* Turn the oscillator on if is not already on (DV1 = 1). */
ctrla = rtc->read(rtc, RTC_CTRL_A);
if (!(ctrla & RTC_CTRL_A_DV1))
ctrla |= RTC_CTRL_A_DV1;
/* Enable the countdown chain (DV2 = 0) */
ctrla &= ~(RTC_CTRL_A_DV2);
/* Clear RS3-RS0 in Control A. */
ctrla &= ~(RTC_CTRL_A_RS_MASK);
/*
* All done with Control A. Switch to Bank 1 for the remainder of
* the RTC setup so we have access to the extended functions.
*/
ctrla |= RTC_CTRL_A_DV0;
rtc->write(rtc, RTC_CTRL_A, ctrla);
/* Default to 32768kHz output. */
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
/* Set the SET bit in Control B so we can do some housekeeping. */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
/* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
cpu_relax();
/*
* If the platform supports BCD mode, then set DM=0 in Control B.
* Otherwise, set DM=1 for BIN mode.
*/
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (pdata->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->bcd_mode = pdata->bcd_mode;
/*
* Disable Daylight Savings Time (DSE = 0).
* The RTC has hardcoded timezone information that is rendered
* obselete. We'll let the OS deal with DST settings instead.
*/
if (ctrlb & RTC_CTRL_B_DSE)
ctrlb &= ~(RTC_CTRL_B_DSE);
/* Force 24-hour mode (2412 = 1). */
if (!(ctrlb & RTC_CTRL_B_2412)) {
/* Reinitialize the time hours. */
hours = rtc->read(rtc, RTC_HRS);
am_pm = hours & RTC_HRS_AMPM_MASK;
hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
RTC_HRS_12_BIN_MASK);
hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
/* Enable 24-hour mode. */
ctrlb |= RTC_CTRL_B_2412;
/* Write back to Control B, including DM & DSE bits. */
rtc->write(rtc, RTC_CTRL_B, ctrlb);
/* Write the time hours back. */
rtc->write(rtc, RTC_HRS,
ds1685_rtc_bin2bcd(rtc, hours,
RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK));
/* Reinitialize the alarm hours. */
hours = rtc->read(rtc, RTC_HRS_ALARM);
am_pm = hours & RTC_HRS_AMPM_MASK;
hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
RTC_HRS_12_BIN_MASK);
hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
/* Write the alarm hours back. */
rtc->write(rtc, RTC_HRS_ALARM,
ds1685_rtc_bin2bcd(rtc, hours,
RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK));
} else {
/* 24-hour mode is already set, so write Control B back. */
rtc->write(rtc, RTC_CTRL_B, ctrlb);
}
/* Unset the SET bit in Control B so the RTC can update. */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
/* Check the main battery. */
if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
dev_warn(&pdev->dev,
"Main battery is exhausted! RTC may be invalid!\n");
/* Check the auxillary battery. It is optional. */
if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
dev_warn(&pdev->dev,
"Aux battery is exhausted or not available.\n");
/* Read Ctrl B and clear PIE/AIE/UIE. */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
/* Reading Ctrl C auto-clears PF/AF/UF. */
rtc->read(rtc, RTC_CTRL_C);
/* Read Ctrl 4B and clear RIE/WIE/KSE. */
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
/* Clear RF/WF/KF in Ctrl 4A. */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
/*
* Re-enable KSE to handle power button events. We do not enable
* WIE or RIE by default.
*/
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
rtc_dev = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(rtc_dev))
return PTR_ERR(rtc_dev);
rtc_dev->ops = &ds1685_rtc_ops;
/* Century bit is useless because leap year fails in 1900 and 2100 */
rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
/* Maximum periodic rate is 8192Hz (0.122070ms). */
rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
/* See if the platform doesn't support UIE. */
if (pdata->uie_unsupported)
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc_dev->features);
rtc->dev = rtc_dev;
/*
* Fetch the IRQ and setup the interrupt handler.
*
* Not all platforms have the IRQF pin tied to something. If not, the
* RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
* there won't be an automatic way of notifying the kernel about it,
* unless ctrlc is explicitly polled.
*/
rtc->irq_num = platform_get_irq(pdev, 0);
if (rtc->irq_num <= 0) {
clear_bit(RTC_FEATURE_ALARM, rtc_dev->features);
} else {
/* Request an IRQ. */
ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num,
NULL, ds1685_rtc_irq_handler,
IRQF_SHARED | IRQF_ONESHOT,
pdev->name, pdev);
/* Check to see if something came back. */
if (unlikely(ret)) {
dev_warn(&pdev->dev,
"RTC interrupt not available\n");
rtc->irq_num = 0;
}
}
/* Setup complete. */
ds1685_rtc_switch_to_bank0(rtc);
ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp);
if (ret)
return ret;
nvmem_cfg.priv = rtc;
ret = devm_rtc_nvmem_register(rtc_dev, &nvmem_cfg);
if (ret)
return ret;
return devm_rtc_register_device(rtc_dev);
}
/**
* ds1685_rtc_remove - removes rtc driver.
* @pdev: pointer to platform_device structure.
*/
static void
ds1685_rtc_remove(struct platform_device *pdev)
{
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
/* Read Ctrl B and clear PIE/AIE/UIE. */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) &
~(RTC_CTRL_B_PAU_MASK)));
/* Reading Ctrl C auto-clears PF/AF/UF. */
rtc->read(rtc, RTC_CTRL_C);
/* Read Ctrl 4B and clear RIE/WIE/KSE. */
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) &
~(RTC_CTRL_4B_RWK_MASK)));
/* Manually clear RF/WF/KF in Ctrl 4A. */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) &
~(RTC_CTRL_4A_RWK_MASK)));
}
/*
* ds1685_rtc_driver - rtc driver properties.
*/
static struct platform_driver ds1685_rtc_driver = {
.driver = {
.name = "rtc-ds1685",
},
.probe = ds1685_rtc_probe,
.remove_new = ds1685_rtc_remove,
};
module_platform_driver(ds1685_rtc_driver);
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* Poweroff function */
/**
* ds1685_rtc_poweroff - uses the RTC chip to power the system off.
* @pdev: pointer to platform_device structure.
*/
void __noreturn
ds1685_rtc_poweroff(struct platform_device *pdev)
{
u8 ctrla, ctrl4a, ctrl4b;
struct ds1685_priv *rtc;
/* Check for valid RTC data, else, spin forever. */
if (unlikely(!pdev)) {
pr_emerg("platform device data not available, spinning forever ...\n");
while(1);
unreachable();
} else {
/* Get the rtc data. */
rtc = platform_get_drvdata(pdev);
/*
* Disable our IRQ. We're powering down, so we're not
* going to worry about cleaning up. Most of that should
* have been taken care of by the shutdown scripts and this
* is the final function call.
*/
if (rtc->irq_num)
disable_irq_nosync(rtc->irq_num);
/* Oscillator must be on and the countdown chain enabled. */
ctrla = rtc->read(rtc, RTC_CTRL_A);
ctrla |= RTC_CTRL_A_DV1;
ctrla &= ~(RTC_CTRL_A_DV2);
rtc->write(rtc, RTC_CTRL_A, ctrla);
/*
* Read Control 4A and check the status of the auxillary
* battery. This must be present and working (VRT2 = 1)
* for wakeup and kickstart functionality to be useful.
*/
ds1685_rtc_switch_to_bank1(rtc);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
if (ctrl4a & RTC_CTRL_4A_VRT2) {
/* Clear all of the interrupt flags on Control 4A. */
ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
/*
* The auxillary battery is present and working.
* Enable extended functions (ABE=1), enable
* wake-up (WIE=1), and enable kickstart (KSE=1)
* in Control 4B.
*/
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
RTC_CTRL_4B_KSE);
rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
}
/* Set PAB to 1 in Control 4A to power the system down. */
dev_warn(&pdev->dev, "Powerdown.\n");
msleep(20);
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a | RTC_CTRL_4A_PAB));
/* Spin ... we do not switch back to bank0. */
while(1);
unreachable();
}
}
EXPORT_SYMBOL_GPL(ds1685_rtc_poweroff);
/* ----------------------------------------------------------------------- */
MODULE_AUTHOR("Joshua Kinard <[email protected]>");
MODULE_AUTHOR("Matthias Fuchs <[email protected]>");
MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-ds1685");
| linux-master | drivers/rtc/rtc-ds1685.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* A RTC driver for the Simtek STK17TA8
*
* By Thomas Hommel <[email protected]>
*
* Based on the DS1553 driver from
* Atsushi Nemoto <[email protected]>
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>
#define RTC_REG_SIZE 0x20000
#define RTC_OFFSET 0x1fff0
#define RTC_FLAGS (RTC_OFFSET + 0)
#define RTC_CENTURY (RTC_OFFSET + 1)
#define RTC_SECONDS_ALARM (RTC_OFFSET + 2)
#define RTC_MINUTES_ALARM (RTC_OFFSET + 3)
#define RTC_HOURS_ALARM (RTC_OFFSET + 4)
#define RTC_DATE_ALARM (RTC_OFFSET + 5)
#define RTC_INTERRUPTS (RTC_OFFSET + 6)
#define RTC_WATCHDOG (RTC_OFFSET + 7)
#define RTC_CALIBRATION (RTC_OFFSET + 8)
#define RTC_SECONDS (RTC_OFFSET + 9)
#define RTC_MINUTES (RTC_OFFSET + 10)
#define RTC_HOURS (RTC_OFFSET + 11)
#define RTC_DAY (RTC_OFFSET + 12)
#define RTC_DATE (RTC_OFFSET + 13)
#define RTC_MONTH (RTC_OFFSET + 14)
#define RTC_YEAR (RTC_OFFSET + 15)
#define RTC_SECONDS_MASK 0x7f
#define RTC_DAY_MASK 0x07
#define RTC_CAL_MASK 0x3f
/* Bits in the Calibration register */
#define RTC_STOP 0x80
/* Bits in the Flags register */
#define RTC_FLAGS_AF 0x40
#define RTC_FLAGS_PF 0x20
#define RTC_WRITE 0x02
#define RTC_READ 0x01
/* Bits in the Interrupts register */
#define RTC_INTS_AIE 0x40
struct rtc_plat_data {
struct rtc_device *rtc;
void __iomem *ioaddr;
unsigned long last_jiffies;
int irq;
unsigned int irqen;
int alrm_sec;
int alrm_min;
int alrm_hour;
int alrm_mday;
spinlock_t lock;
};
static int stk17ta8_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
u8 flags;
flags = readb(pdata->ioaddr + RTC_FLAGS);
writeb(flags | RTC_WRITE, pdata->ioaddr + RTC_FLAGS);
writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR);
writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH);
writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY);
writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE);
writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS);
writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES);
writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS);
writeb(bin2bcd((tm->tm_year + 1900) / 100), ioaddr + RTC_CENTURY);
writeb(flags & ~RTC_WRITE, pdata->ioaddr + RTC_FLAGS);
return 0;
}
static int stk17ta8_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
unsigned int year, month, day, hour, minute, second, week;
unsigned int century;
u8 flags;
/* give enough time to update RTC in case of continuous read */
if (pdata->last_jiffies == jiffies)
msleep(1);
pdata->last_jiffies = jiffies;
flags = readb(pdata->ioaddr + RTC_FLAGS);
writeb(flags | RTC_READ, ioaddr + RTC_FLAGS);
second = readb(ioaddr + RTC_SECONDS) & RTC_SECONDS_MASK;
minute = readb(ioaddr + RTC_MINUTES);
hour = readb(ioaddr + RTC_HOURS);
day = readb(ioaddr + RTC_DATE);
week = readb(ioaddr + RTC_DAY) & RTC_DAY_MASK;
month = readb(ioaddr + RTC_MONTH);
year = readb(ioaddr + RTC_YEAR);
century = readb(ioaddr + RTC_CENTURY);
writeb(flags & ~RTC_READ, ioaddr + RTC_FLAGS);
tm->tm_sec = bcd2bin(second);
tm->tm_min = bcd2bin(minute);
tm->tm_hour = bcd2bin(hour);
tm->tm_mday = bcd2bin(day);
tm->tm_wday = bcd2bin(week);
tm->tm_mon = bcd2bin(month) - 1;
/* year is 1900 + tm->tm_year */
tm->tm_year = bcd2bin(year) + bcd2bin(century) * 100 - 1900;
return 0;
}
static void stk17ta8_rtc_update_alarm(struct rtc_plat_data *pdata)
{
void __iomem *ioaddr = pdata->ioaddr;
unsigned long irqflags;
u8 flags;
spin_lock_irqsave(&pdata->lock, irqflags);
flags = readb(ioaddr + RTC_FLAGS);
writeb(flags | RTC_WRITE, ioaddr + RTC_FLAGS);
writeb(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_mday),
ioaddr + RTC_DATE_ALARM);
writeb(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_hour),
ioaddr + RTC_HOURS_ALARM);
writeb(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_min),
ioaddr + RTC_MINUTES_ALARM);
writeb(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_sec),
ioaddr + RTC_SECONDS_ALARM);
writeb(pdata->irqen ? RTC_INTS_AIE : 0, ioaddr + RTC_INTERRUPTS);
readb(ioaddr + RTC_FLAGS); /* clear interrupts */
writeb(flags & ~RTC_WRITE, ioaddr + RTC_FLAGS);
spin_unlock_irqrestore(&pdata->lock, irqflags);
}
static int stk17ta8_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
pdata->alrm_mday = alrm->time.tm_mday;
pdata->alrm_hour = alrm->time.tm_hour;
pdata->alrm_min = alrm->time.tm_min;
pdata->alrm_sec = alrm->time.tm_sec;
if (alrm->enabled)
pdata->irqen |= RTC_AF;
stk17ta8_rtc_update_alarm(pdata);
return 0;
}
static int stk17ta8_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
return 0;
}
static irqreturn_t stk17ta8_rtc_interrupt(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
void __iomem *ioaddr = pdata->ioaddr;
unsigned long events = 0;
spin_lock(&pdata->lock);
/* read and clear interrupt */
if (readb(ioaddr + RTC_FLAGS) & RTC_FLAGS_AF) {
events = RTC_IRQF;
if (readb(ioaddr + RTC_SECONDS_ALARM) & 0x80)
events |= RTC_UF;
else
events |= RTC_AF;
rtc_update_irq(pdata->rtc, 1, events);
}
spin_unlock(&pdata->lock);
return events ? IRQ_HANDLED : IRQ_NONE;
}
static int stk17ta8_rtc_alarm_irq_enable(struct device *dev,
unsigned int enabled)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
if (enabled)
pdata->irqen |= RTC_AF;
else
pdata->irqen &= ~RTC_AF;
stk17ta8_rtc_update_alarm(pdata);
return 0;
}
static const struct rtc_class_ops stk17ta8_rtc_ops = {
.read_time = stk17ta8_rtc_read_time,
.set_time = stk17ta8_rtc_set_time,
.read_alarm = stk17ta8_rtc_read_alarm,
.set_alarm = stk17ta8_rtc_set_alarm,
.alarm_irq_enable = stk17ta8_rtc_alarm_irq_enable,
};
static int stk17ta8_nvram_read(void *priv, unsigned int pos, void *val,
size_t bytes)
{
struct rtc_plat_data *pdata = priv;
void __iomem *ioaddr = pdata->ioaddr;
u8 *buf = val;
for (; bytes; bytes--)
*buf++ = readb(ioaddr + pos++);
return 0;
}
static int stk17ta8_nvram_write(void *priv, unsigned int pos, void *val,
size_t bytes)
{
struct rtc_plat_data *pdata = priv;
void __iomem *ioaddr = pdata->ioaddr;
u8 *buf = val;
for (; bytes; bytes--)
writeb(*buf++, ioaddr + pos++);
return 0;
}
static int stk17ta8_rtc_probe(struct platform_device *pdev)
{
unsigned int cal;
unsigned int flags;
struct rtc_plat_data *pdata;
void __iomem *ioaddr;
int ret = 0;
struct nvmem_config nvmem_cfg = {
.name = "stk17ta8_nvram",
.word_size = 1,
.stride = 1,
.size = RTC_OFFSET,
.reg_read = stk17ta8_nvram_read,
.reg_write = stk17ta8_nvram_write,
};
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
ioaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ioaddr))
return PTR_ERR(ioaddr);
pdata->ioaddr = ioaddr;
pdata->irq = platform_get_irq(pdev, 0);
/* turn RTC on if it was not on */
cal = readb(ioaddr + RTC_CALIBRATION);
if (cal & RTC_STOP) {
cal &= RTC_CAL_MASK;
flags = readb(ioaddr + RTC_FLAGS);
writeb(flags | RTC_WRITE, ioaddr + RTC_FLAGS);
writeb(cal, ioaddr + RTC_CALIBRATION);
writeb(flags & ~RTC_WRITE, ioaddr + RTC_FLAGS);
}
if (readb(ioaddr + RTC_FLAGS) & RTC_FLAGS_PF)
dev_warn(&pdev->dev, "voltage-low detected.\n");
spin_lock_init(&pdata->lock);
pdata->last_jiffies = jiffies;
platform_set_drvdata(pdev, pdata);
if (pdata->irq > 0) {
writeb(0, ioaddr + RTC_INTERRUPTS);
if (devm_request_irq(&pdev->dev, pdata->irq,
stk17ta8_rtc_interrupt,
IRQF_SHARED,
pdev->name, pdev) < 0) {
dev_warn(&pdev->dev, "interrupt not available.\n");
pdata->irq = 0;
}
}
pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pdata->rtc))
return PTR_ERR(pdata->rtc);
pdata->rtc->ops = &stk17ta8_rtc_ops;
nvmem_cfg.priv = pdata;
ret = devm_rtc_nvmem_register(pdata->rtc, &nvmem_cfg);
if (ret)
return ret;
return devm_rtc_register_device(pdata->rtc);
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:stk17ta8");
static struct platform_driver stk17ta8_rtc_driver = {
.probe = stk17ta8_rtc_probe,
.driver = {
.name = "stk17ta8",
},
};
module_platform_driver(stk17ta8_rtc_driver);
MODULE_AUTHOR("Thomas Hommel <[email protected]>");
MODULE_DESCRIPTION("Simtek STK17TA8 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-stk17ta8.c |
// SPDX-License-Identifier: GPL-2.0-only
/* rtc-ds1347.c
*
* Driver for Dallas Semiconductor DS1347 Low Current, SPI Compatible
* Real Time Clock
*
* Author : Raghavendra Chandra Ganiga <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
#include <linux/regmap.h>
/* Registers in ds1347 rtc */
#define DS1347_SECONDS_REG 0x01
#define DS1347_MINUTES_REG 0x03
#define DS1347_HOURS_REG 0x05
#define DS1347_DATE_REG 0x07
#define DS1347_MONTH_REG 0x09
#define DS1347_DAY_REG 0x0B
#define DS1347_YEAR_REG 0x0D
#define DS1347_CONTROL_REG 0x0F
#define DS1347_CENTURY_REG 0x13
#define DS1347_STATUS_REG 0x17
#define DS1347_CLOCK_BURST 0x3F
#define DS1347_WP_BIT BIT(7)
#define DS1347_NEOSC_BIT BIT(7)
#define DS1347_OSF_BIT BIT(2)
static const struct regmap_range ds1347_ranges[] = {
{
.range_min = DS1347_SECONDS_REG,
.range_max = DS1347_STATUS_REG,
},
};
static const struct regmap_access_table ds1347_access_table = {
.yes_ranges = ds1347_ranges,
.n_yes_ranges = ARRAY_SIZE(ds1347_ranges),
};
static int ds1347_read_time(struct device *dev, struct rtc_time *dt)
{
struct regmap *map = dev_get_drvdata(dev);
unsigned int status, century, secs;
unsigned char buf[8];
int err;
err = regmap_read(map, DS1347_STATUS_REG, &status);
if (err)
return err;
if (status & DS1347_OSF_BIT)
return -EINVAL;
do {
err = regmap_bulk_read(map, DS1347_CLOCK_BURST, buf, 8);
if (err)
return err;
err = regmap_read(map, DS1347_CENTURY_REG, ¢ury);
if (err)
return err;
err = regmap_read(map, DS1347_SECONDS_REG, &secs);
if (err)
return err;
} while (buf[0] != secs);
dt->tm_sec = bcd2bin(buf[0]);
dt->tm_min = bcd2bin(buf[1] & 0x7f);
dt->tm_hour = bcd2bin(buf[2] & 0x3F);
dt->tm_mday = bcd2bin(buf[3]);
dt->tm_mon = bcd2bin(buf[4]) - 1;
dt->tm_wday = bcd2bin(buf[5]) - 1;
dt->tm_year = (bcd2bin(century) * 100) + bcd2bin(buf[6]) - 1900;
return 0;
}
static int ds1347_set_time(struct device *dev, struct rtc_time *dt)
{
struct regmap *map = dev_get_drvdata(dev);
unsigned int century;
unsigned char buf[8];
int err;
err = regmap_update_bits(map, DS1347_STATUS_REG,
DS1347_NEOSC_BIT, DS1347_NEOSC_BIT);
if (err)
return err;
buf[0] = bin2bcd(dt->tm_sec);
buf[1] = bin2bcd(dt->tm_min);
buf[2] = (bin2bcd(dt->tm_hour) & 0x3F);
buf[3] = bin2bcd(dt->tm_mday);
buf[4] = bin2bcd(dt->tm_mon + 1);
buf[5] = bin2bcd(dt->tm_wday + 1);
buf[6] = bin2bcd(dt->tm_year % 100);
buf[7] = bin2bcd(0x00);
err = regmap_bulk_write(map, DS1347_CLOCK_BURST, buf, 8);
if (err)
return err;
century = (dt->tm_year / 100) + 19;
err = regmap_write(map, DS1347_CENTURY_REG, bin2bcd(century));
if (err)
return err;
return regmap_update_bits(map, DS1347_STATUS_REG,
DS1347_NEOSC_BIT | DS1347_OSF_BIT, 0);
}
static const struct rtc_class_ops ds1347_rtc_ops = {
.read_time = ds1347_read_time,
.set_time = ds1347_set_time,
};
static int ds1347_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
struct regmap_config config;
struct regmap *map;
int err;
memset(&config, 0, sizeof(config));
config.reg_bits = 8;
config.val_bits = 8;
config.read_flag_mask = 0x80;
config.max_register = 0x3F;
config.wr_table = &ds1347_access_table;
/* spi setup with ds1347 in mode 3 and bits per word as 8 */
spi->mode = SPI_MODE_3;
spi->bits_per_word = 8;
spi_setup(spi);
map = devm_regmap_init_spi(spi, &config);
if (IS_ERR(map)) {
dev_err(&spi->dev, "ds1347 regmap init spi failed\n");
return PTR_ERR(map);
}
spi_set_drvdata(spi, map);
/* Disable the write protect of rtc */
err = regmap_update_bits(map, DS1347_CONTROL_REG, DS1347_WP_BIT, 0);
if (err)
return err;
rtc = devm_rtc_allocate_device(&spi->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &ds1347_rtc_ops;
rtc->range_min = RTC_TIMESTAMP_BEGIN_0000;
rtc->range_max = RTC_TIMESTAMP_END_9999;
return devm_rtc_register_device(rtc);
}
static struct spi_driver ds1347_driver = {
.driver = {
.name = "ds1347",
},
.probe = ds1347_probe,
};
module_spi_driver(ds1347_driver);
MODULE_DESCRIPTION("DS1347 SPI RTC DRIVER");
MODULE_AUTHOR("Raghavendra C Ganiga <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-ds1347.c |
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#define SNVS_LPREGISTER_OFFSET 0x34
/* These register offsets are relative to LP (Low Power) range */
#define SNVS_LPCR 0x04
#define SNVS_LPSR 0x18
#define SNVS_LPSRTCMR 0x1c
#define SNVS_LPSRTCLR 0x20
#define SNVS_LPTAR 0x24
#define SNVS_LPPGDR 0x30
#define SNVS_LPCR_SRTC_ENV (1 << 0)
#define SNVS_LPCR_LPTA_EN (1 << 1)
#define SNVS_LPCR_LPWUI_EN (1 << 3)
#define SNVS_LPSR_LPTA (1 << 0)
#define SNVS_LPPGDR_INIT 0x41736166
#define CNTR_TO_SECS_SH 15
/* The maximum RTC clock cycles that are allowed to pass between two
* consecutive clock counter register reads. If the values are corrupted a
* bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
* we end at 10ms which should be enough for most cases. If it once takes
* longer than expected we do a retry.
*/
#define MAX_RTC_READ_DIFF_CYCLES 320
struct snvs_rtc_data {
struct rtc_device *rtc;
struct regmap *regmap;
int offset;
int irq;
struct clk *clk;
};
/* Read 64 bit timer register, which could be in inconsistent state */
static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
{
u32 msb, lsb;
regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
return (u64)msb << 32 | lsb;
}
/* Read the secure real time counter, taking care to deal with the cases of the
* counter updating while being read.
*/
static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
{
u64 read1, read2;
s64 diff;
unsigned int timeout = 100;
/* As expected, the registers might update between the read of the LSB
* reg and the MSB reg. It's also possible that one register might be
* in partially modified state as well.
*/
read1 = rtc_read_lpsrt(data);
do {
read2 = read1;
read1 = rtc_read_lpsrt(data);
diff = read1 - read2;
} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
if (!timeout)
dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
/* Convert 47-bit counter to 32-bit raw second count */
return (u32) (read1 >> CNTR_TO_SECS_SH);
}
/* Just read the lsb from the counter, dealing with inconsistent state */
static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
{
u32 count1, count2;
s32 diff;
unsigned int timeout = 100;
regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
do {
count2 = count1;
regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
diff = count1 - count2;
} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
if (!timeout) {
dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
return -ETIMEDOUT;
}
*lsb = count1;
return 0;
}
static int rtc_write_sync_lp(struct snvs_rtc_data *data)
{
u32 count1, count2;
u32 elapsed;
unsigned int timeout = 1000;
int ret;
ret = rtc_read_lp_counter_lsb(data, &count1);
if (ret)
return ret;
/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
do {
ret = rtc_read_lp_counter_lsb(data, &count2);
if (ret)
return ret;
elapsed = count2 - count1; /* wrap around _is_ handled! */
} while (elapsed < 3 && --timeout);
if (!timeout) {
dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
return -ETIMEDOUT;
}
return 0;
}
static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
{
int timeout = 1000;
u32 lpcr;
regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
enable ? SNVS_LPCR_SRTC_ENV : 0);
while (--timeout) {
regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
if (enable) {
if (lpcr & SNVS_LPCR_SRTC_ENV)
break;
} else {
if (!(lpcr & SNVS_LPCR_SRTC_ENV))
break;
}
}
if (!timeout)
return -ETIMEDOUT;
return 0;
}
static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
unsigned long time;
int ret;
ret = clk_enable(data->clk);
if (ret)
return ret;
time = rtc_read_lp_counter(data);
rtc_time64_to_tm(time, tm);
clk_disable(data->clk);
return 0;
}
static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
unsigned long time = rtc_tm_to_time64(tm);
int ret;
ret = clk_enable(data->clk);
if (ret)
return ret;
/* Disable RTC first */
ret = snvs_rtc_enable(data, false);
if (ret)
return ret;
/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
/* Enable RTC again */
ret = snvs_rtc_enable(data, true);
clk_disable(data->clk);
return ret;
}
static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
u32 lptar, lpsr;
int ret;
ret = clk_enable(data->clk);
if (ret)
return ret;
regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
rtc_time64_to_tm(lptar, &alrm->time);
regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
clk_disable(data->clk);
return 0;
}
static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
int ret;
ret = clk_enable(data->clk);
if (ret)
return ret;
regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
ret = rtc_write_sync_lp(data);
clk_disable(data->clk);
return ret;
}
static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
unsigned long time = rtc_tm_to_time64(&alrm->time);
int ret;
ret = clk_enable(data->clk);
if (ret)
return ret;
regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
ret = rtc_write_sync_lp(data);
if (ret)
return ret;
regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
/* Clear alarm interrupt status bit */
regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
clk_disable(data->clk);
return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
}
static const struct rtc_class_ops snvs_rtc_ops = {
.read_time = snvs_rtc_read_time,
.set_time = snvs_rtc_set_time,
.read_alarm = snvs_rtc_read_alarm,
.set_alarm = snvs_rtc_set_alarm,
.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
};
static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
{
struct device *dev = dev_id;
struct snvs_rtc_data *data = dev_get_drvdata(dev);
u32 lpsr;
u32 events = 0;
clk_enable(data->clk);
regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
if (lpsr & SNVS_LPSR_LPTA) {
events |= (RTC_AF | RTC_IRQF);
/* RTC alarm should be one-shot */
snvs_rtc_alarm_irq_enable(dev, 0);
rtc_update_irq(data->rtc, 1, events);
}
/* clear interrupt status */
regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
clk_disable(data->clk);
return events ? IRQ_HANDLED : IRQ_NONE;
}
static const struct regmap_config snvs_rtc_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
};
static void snvs_rtc_action(void *data)
{
clk_disable_unprepare(data);
}
static int snvs_rtc_probe(struct platform_device *pdev)
{
struct snvs_rtc_data *data;
int ret;
void __iomem *mmio;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(data->rtc))
return PTR_ERR(data->rtc);
data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
if (IS_ERR(data->regmap)) {
dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
mmio = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(mmio))
return PTR_ERR(mmio);
data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
} else {
data->offset = SNVS_LPREGISTER_OFFSET;
of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
}
if (IS_ERR(data->regmap)) {
dev_err(&pdev->dev, "Can't find snvs syscon\n");
return -ENODEV;
}
data->irq = platform_get_irq(pdev, 0);
if (data->irq < 0)
return data->irq;
data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
if (IS_ERR(data->clk)) {
data->clk = NULL;
} else {
ret = clk_prepare_enable(data->clk);
if (ret) {
dev_err(&pdev->dev,
"Could not prepare or enable the snvs clock\n");
return ret;
}
}
ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
if (ret)
return ret;
platform_set_drvdata(pdev, data);
/* Initialize glitch detect */
regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
/* Clear interrupt status */
regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
/* Enable RTC */
ret = snvs_rtc_enable(data, true);
if (ret) {
dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
return ret;
}
device_init_wakeup(&pdev->dev, true);
ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
if (ret)
dev_err(&pdev->dev, "failed to enable irq wake\n");
ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
IRQF_SHARED, "rtc alarm", &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "failed to request irq %d: %d\n",
data->irq, ret);
return ret;
}
data->rtc->ops = &snvs_rtc_ops;
data->rtc->range_max = U32_MAX;
return devm_rtc_register_device(data->rtc);
}
static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
clk_disable(data->clk);
return 0;
}
static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
{
struct snvs_rtc_data *data = dev_get_drvdata(dev);
if (data->clk)
return clk_enable(data->clk);
return 0;
}
static const struct dev_pm_ops snvs_rtc_pm_ops = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
};
static const struct of_device_id snvs_dt_ids[] = {
{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, snvs_dt_ids);
static struct platform_driver snvs_rtc_driver = {
.driver = {
.name = "snvs_rtc",
.pm = &snvs_rtc_pm_ops,
.of_match_table = snvs_dt_ids,
},
.probe = snvs_rtc_probe,
};
module_platform_driver(snvs_rtc_driver);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-snvs.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Seiko Instruments S-35390A RTC Driver
*
* Copyright (c) 2007 Byron Bradley
*/
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/i2c.h>
#include <linux/bitrev.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#include <linux/delay.h>
#define S35390A_CMD_STATUS1 0
#define S35390A_CMD_STATUS2 1
#define S35390A_CMD_TIME1 2
#define S35390A_CMD_TIME2 3
#define S35390A_CMD_INT2_REG1 5
#define S35390A_BYTE_YEAR 0
#define S35390A_BYTE_MONTH 1
#define S35390A_BYTE_DAY 2
#define S35390A_BYTE_WDAY 3
#define S35390A_BYTE_HOURS 4
#define S35390A_BYTE_MINS 5
#define S35390A_BYTE_SECS 6
#define S35390A_ALRM_BYTE_WDAY 0
#define S35390A_ALRM_BYTE_HOURS 1
#define S35390A_ALRM_BYTE_MINS 2
/* flags for STATUS1 */
#define S35390A_FLAG_POC BIT(0)
#define S35390A_FLAG_BLD BIT(1)
#define S35390A_FLAG_INT2 BIT(2)
#define S35390A_FLAG_24H BIT(6)
#define S35390A_FLAG_RESET BIT(7)
/* flag for STATUS2 */
#define S35390A_FLAG_TEST BIT(0)
/* INT2 pin output mode */
#define S35390A_INT2_MODE_MASK 0x0E
#define S35390A_INT2_MODE_NOINTR 0x00
#define S35390A_INT2_MODE_ALARM BIT(1) /* INT2AE */
#define S35390A_INT2_MODE_PMIN_EDG BIT(2) /* INT2ME */
#define S35390A_INT2_MODE_FREQ BIT(3) /* INT2FE */
#define S35390A_INT2_MODE_PMIN (BIT(3) | BIT(2)) /* INT2FE | INT2ME */
static const struct i2c_device_id s35390a_id[] = {
{ "s35390a", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, s35390a_id);
static const __maybe_unused struct of_device_id s35390a_of_match[] = {
{ .compatible = "s35390a" },
{ .compatible = "sii,s35390a" },
{ }
};
MODULE_DEVICE_TABLE(of, s35390a_of_match);
struct s35390a {
struct i2c_client *client[8];
struct rtc_device *rtc;
int twentyfourhour;
};
static int s35390a_set_reg(struct s35390a *s35390a, int reg, char *buf, int len)
{
struct i2c_client *client = s35390a->client[reg];
struct i2c_msg msg[] = {
{
.addr = client->addr,
.len = len,
.buf = buf
},
};
if ((i2c_transfer(client->adapter, msg, 1)) != 1)
return -EIO;
return 0;
}
static int s35390a_get_reg(struct s35390a *s35390a, int reg, char *buf, int len)
{
struct i2c_client *client = s35390a->client[reg];
struct i2c_msg msg[] = {
{
.addr = client->addr,
.flags = I2C_M_RD,
.len = len,
.buf = buf
},
};
if ((i2c_transfer(client->adapter, msg, 1)) != 1)
return -EIO;
return 0;
}
static int s35390a_init(struct s35390a *s35390a)
{
u8 buf;
int ret;
unsigned initcount = 0;
/*
* At least one of POC and BLD are set, so reinitialise chip. Keeping
* this information in the hardware to know later that the time isn't
* valid is unfortunately not possible because POC and BLD are cleared
* on read. So the reset is best done now.
*
* The 24H bit is kept over reset, so set it already here.
*/
initialize:
buf = S35390A_FLAG_RESET | S35390A_FLAG_24H;
ret = s35390a_set_reg(s35390a, S35390A_CMD_STATUS1, &buf, 1);
if (ret < 0)
return ret;
ret = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &buf, 1);
if (ret < 0)
return ret;
if (buf & (S35390A_FLAG_POC | S35390A_FLAG_BLD)) {
/* Try up to five times to reset the chip */
if (initcount < 5) {
++initcount;
goto initialize;
} else
return -EIO;
}
return 1;
}
/*
* Returns <0 on error, 0 if rtc is setup fine and 1 if the chip was reset.
* To keep the information if an irq is pending, pass the value read from
* STATUS1 to the caller.
*/
static int s35390a_read_status(struct s35390a *s35390a, char *status1)
{
int ret;
ret = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, status1, 1);
if (ret < 0)
return ret;
if (*status1 & S35390A_FLAG_POC) {
/*
* Do not communicate for 0.5 seconds since the power-on
* detection circuit is in operation.
*/
msleep(500);
return 1;
} else if (*status1 & S35390A_FLAG_BLD)
return 1;
/*
* If both POC and BLD are unset everything is fine.
*/
return 0;
}
static int s35390a_disable_test_mode(struct s35390a *s35390a)
{
char buf[1];
if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
return -EIO;
if (!(buf[0] & S35390A_FLAG_TEST))
return 0;
buf[0] &= ~S35390A_FLAG_TEST;
return s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
}
static char s35390a_hr2reg(struct s35390a *s35390a, int hour)
{
if (s35390a->twentyfourhour)
return bin2bcd(hour);
if (hour < 12)
return bin2bcd(hour);
return 0x40 | bin2bcd(hour - 12);
}
static int s35390a_reg2hr(struct s35390a *s35390a, char reg)
{
unsigned hour;
if (s35390a->twentyfourhour)
return bcd2bin(reg & 0x3f);
hour = bcd2bin(reg & 0x3f);
if (reg & 0x40)
hour += 12;
return hour;
}
static int s35390a_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
struct s35390a *s35390a = i2c_get_clientdata(client);
int i;
char buf[7], status;
dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d mday=%d, "
"mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
tm->tm_wday);
if (s35390a_read_status(s35390a, &status) == 1)
s35390a_init(s35390a);
buf[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 100);
buf[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon + 1);
buf[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
buf[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
buf[S35390A_BYTE_HOURS] = s35390a_hr2reg(s35390a, tm->tm_hour);
buf[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
buf[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
/* This chip expects the bits of each byte to be in reverse order */
for (i = 0; i < 7; ++i)
buf[i] = bitrev8(buf[i]);
return s35390a_set_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
}
static int s35390a_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[7], status;
int i, err;
if (s35390a_read_status(s35390a, &status) == 1)
return -EINVAL;
err = s35390a_get_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
if (err < 0)
return err;
/* This chip returns the bits of each byte in reverse order */
for (i = 0; i < 7; ++i)
buf[i] = bitrev8(buf[i]);
tm->tm_sec = bcd2bin(buf[S35390A_BYTE_SECS]);
tm->tm_min = bcd2bin(buf[S35390A_BYTE_MINS]);
tm->tm_hour = s35390a_reg2hr(s35390a, buf[S35390A_BYTE_HOURS]);
tm->tm_wday = bcd2bin(buf[S35390A_BYTE_WDAY]);
tm->tm_mday = bcd2bin(buf[S35390A_BYTE_DAY]);
tm->tm_mon = bcd2bin(buf[S35390A_BYTE_MONTH]) - 1;
tm->tm_year = bcd2bin(buf[S35390A_BYTE_YEAR]) + 100;
dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, mday=%d, "
"mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
tm->tm_wday);
return 0;
}
static int s35390a_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct i2c_client *client = to_i2c_client(dev);
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[3], sts = 0;
int err, i;
dev_dbg(&client->dev, "%s: alm is secs=%d, mins=%d, hours=%d mday=%d, "\
"mon=%d, year=%d, wday=%d\n", __func__, alm->time.tm_sec,
alm->time.tm_min, alm->time.tm_hour, alm->time.tm_mday,
alm->time.tm_mon, alm->time.tm_year, alm->time.tm_wday);
/* disable interrupt (which deasserts the irq line) */
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
/* clear pending interrupt (in STATUS1 only), if any */
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &sts, sizeof(sts));
if (err < 0)
return err;
if (alm->enabled)
sts = S35390A_INT2_MODE_ALARM;
else
sts = S35390A_INT2_MODE_NOINTR;
/* set interupt mode*/
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
if (alm->time.tm_wday != -1)
buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
else
buf[S35390A_ALRM_BYTE_WDAY] = 0;
buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
alm->time.tm_hour) | 0x80;
buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
if (alm->time.tm_hour >= 12)
buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
for (i = 0; i < 3; ++i)
buf[i] = bitrev8(buf[i]);
err = s35390a_set_reg(s35390a, S35390A_CMD_INT2_REG1, buf,
sizeof(buf));
return err;
}
static int s35390a_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct i2c_client *client = to_i2c_client(dev);
struct s35390a *s35390a = i2c_get_clientdata(client);
char buf[3], sts;
int i, err;
err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
if (err < 0)
return err;
if ((sts & S35390A_INT2_MODE_MASK) != S35390A_INT2_MODE_ALARM) {
/*
* When the alarm isn't enabled, the register to configure
* the alarm time isn't accessible.
*/
alm->enabled = 0;
return 0;
} else {
alm->enabled = 1;
}
err = s35390a_get_reg(s35390a, S35390A_CMD_INT2_REG1, buf, sizeof(buf));
if (err < 0)
return err;
/* This chip returns the bits of each byte in reverse order */
for (i = 0; i < 3; ++i)
buf[i] = bitrev8(buf[i]);
/*
* B0 of the three matching registers is an enable flag. Iff it is set
* the configured value is used for matching.
*/
if (buf[S35390A_ALRM_BYTE_WDAY] & 0x80)
alm->time.tm_wday =
bcd2bin(buf[S35390A_ALRM_BYTE_WDAY] & ~0x80);
if (buf[S35390A_ALRM_BYTE_HOURS] & 0x80)
alm->time.tm_hour =
s35390a_reg2hr(s35390a,
buf[S35390A_ALRM_BYTE_HOURS] & ~0x80);
if (buf[S35390A_ALRM_BYTE_MINS] & 0x80)
alm->time.tm_min = bcd2bin(buf[S35390A_ALRM_BYTE_MINS] & ~0x80);
/* alarm triggers always at s=0 */
alm->time.tm_sec = 0;
dev_dbg(&client->dev, "%s: alm is mins=%d, hours=%d, wday=%d\n",
__func__, alm->time.tm_min, alm->time.tm_hour,
alm->time.tm_wday);
return 0;
}
static int s35390a_rtc_ioctl(struct device *dev, unsigned int cmd,
unsigned long arg)
{
struct i2c_client *client = to_i2c_client(dev);
struct s35390a *s35390a = i2c_get_clientdata(client);
char sts;
int err;
switch (cmd) {
case RTC_VL_READ:
/* s35390a_reset set lowvoltage flag and init RTC if needed */
err = s35390a_read_status(s35390a, &sts);
if (err < 0)
return err;
if (copy_to_user((void __user *)arg, &err, sizeof(int)))
return -EFAULT;
break;
case RTC_VL_CLR:
/* update flag and clear register */
err = s35390a_init(s35390a);
if (err < 0)
return err;
break;
default:
return -ENOIOCTLCMD;
}
return 0;
}
static const struct rtc_class_ops s35390a_rtc_ops = {
.read_time = s35390a_rtc_read_time,
.set_time = s35390a_rtc_set_time,
.set_alarm = s35390a_rtc_set_alarm,
.read_alarm = s35390a_rtc_read_alarm,
.ioctl = s35390a_rtc_ioctl,
};
static int s35390a_probe(struct i2c_client *client)
{
int err, err_read;
unsigned int i;
struct s35390a *s35390a;
char buf, status1;
struct device *dev = &client->dev;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
s35390a = devm_kzalloc(dev, sizeof(struct s35390a), GFP_KERNEL);
if (!s35390a)
return -ENOMEM;
s35390a->client[0] = client;
i2c_set_clientdata(client, s35390a);
/* This chip uses multiple addresses, use dummy devices for them */
for (i = 1; i < 8; ++i) {
s35390a->client[i] = devm_i2c_new_dummy_device(dev,
client->adapter,
client->addr + i);
if (IS_ERR(s35390a->client[i])) {
dev_err(dev, "Address %02x unavailable\n",
client->addr + i);
return PTR_ERR(s35390a->client[i]);
}
}
s35390a->rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(s35390a->rtc))
return PTR_ERR(s35390a->rtc);
err_read = s35390a_read_status(s35390a, &status1);
if (err_read < 0) {
dev_err(dev, "error resetting chip\n");
return err_read;
}
if (status1 & S35390A_FLAG_24H)
s35390a->twentyfourhour = 1;
else
s35390a->twentyfourhour = 0;
if (status1 & S35390A_FLAG_INT2) {
/* disable alarm (and maybe test mode) */
buf = 0;
err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &buf, 1);
if (err < 0) {
dev_err(dev, "error disabling alarm");
return err;
}
} else {
err = s35390a_disable_test_mode(s35390a);
if (err < 0) {
dev_err(dev, "error disabling test mode\n");
return err;
}
}
device_set_wakeup_capable(dev, 1);
s35390a->rtc->ops = &s35390a_rtc_ops;
s35390a->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
s35390a->rtc->range_max = RTC_TIMESTAMP_END_2099;
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, s35390a->rtc->features);
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, s35390a->rtc->features );
if (status1 & S35390A_FLAG_INT2)
rtc_update_irq(s35390a->rtc, 1, RTC_AF);
return devm_rtc_register_device(s35390a->rtc);
}
static struct i2c_driver s35390a_driver = {
.driver = {
.name = "rtc-s35390a",
.of_match_table = of_match_ptr(s35390a_of_match),
},
.probe = s35390a_probe,
.id_table = s35390a_id,
};
module_i2c_driver(s35390a_driver);
MODULE_AUTHOR("Byron Bradley <[email protected]>");
MODULE_DESCRIPTION("S35390A RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-s35390a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An I2C driver for the Intersil ISL 12022
*
* Author: Roman Fietze <[email protected]>
*
* Based on the Philips PCF8563 RTC
* by Alessandro Zummo <[email protected]>.
*/
#include <linux/bcd.h>
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/hwmon.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
/* ISL register offsets */
#define ISL12022_REG_SC 0x00
#define ISL12022_REG_MN 0x01
#define ISL12022_REG_HR 0x02
#define ISL12022_REG_DT 0x03
#define ISL12022_REG_MO 0x04
#define ISL12022_REG_YR 0x05
#define ISL12022_REG_DW 0x06
#define ISL12022_REG_SR 0x07
#define ISL12022_REG_INT 0x08
#define ISL12022_REG_PWR_VBAT 0x0a
#define ISL12022_REG_BETA 0x0d
#define ISL12022_REG_TEMP_L 0x28
/* ISL register bits */
#define ISL12022_HR_MIL (1 << 7) /* military or 24 hour time */
#define ISL12022_SR_LBAT85 (1 << 2)
#define ISL12022_SR_LBAT75 (1 << 1)
#define ISL12022_INT_WRTC (1 << 6)
#define ISL12022_INT_FO_MASK GENMASK(3, 0)
#define ISL12022_INT_FO_OFF 0x0
#define ISL12022_INT_FO_32K 0x1
#define ISL12022_REG_VB85_MASK GENMASK(5, 3)
#define ISL12022_REG_VB75_MASK GENMASK(2, 0)
#define ISL12022_BETA_TSE (1 << 7)
static umode_t isl12022_hwmon_is_visible(const void *data,
enum hwmon_sensor_types type,
u32 attr, int channel)
{
if (type == hwmon_temp && attr == hwmon_temp_input)
return 0444;
return 0;
}
/*
* A user-initiated temperature conversion is not started by this function,
* so the temperature is updated once every ~60 seconds.
*/
static int isl12022_hwmon_read_temp(struct device *dev, long *mC)
{
struct regmap *regmap = dev_get_drvdata(dev);
int temp, ret;
__le16 buf;
ret = regmap_bulk_read(regmap, ISL12022_REG_TEMP_L, &buf, sizeof(buf));
if (ret)
return ret;
/*
* Temperature is represented as a 10-bit number, unit half-Kelvins.
*/
temp = le16_to_cpu(buf);
temp *= 500;
temp -= 273000;
*mC = temp;
return 0;
}
static int isl12022_hwmon_read(struct device *dev,
enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
if (type == hwmon_temp && attr == hwmon_temp_input)
return isl12022_hwmon_read_temp(dev, val);
return -EOPNOTSUPP;
}
static const struct hwmon_channel_info * const isl12022_hwmon_info[] = {
HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
NULL
};
static const struct hwmon_ops isl12022_hwmon_ops = {
.is_visible = isl12022_hwmon_is_visible,
.read = isl12022_hwmon_read,
};
static const struct hwmon_chip_info isl12022_hwmon_chip_info = {
.ops = &isl12022_hwmon_ops,
.info = isl12022_hwmon_info,
};
static void isl12022_hwmon_register(struct device *dev)
{
struct regmap *regmap = dev_get_drvdata(dev);
struct device *hwmon;
int ret;
if (!IS_REACHABLE(CONFIG_HWMON))
return;
ret = regmap_update_bits(regmap, ISL12022_REG_BETA,
ISL12022_BETA_TSE, ISL12022_BETA_TSE);
if (ret) {
dev_warn(dev, "unable to enable temperature sensor\n");
return;
}
hwmon = devm_hwmon_device_register_with_info(dev, "isl12022", regmap,
&isl12022_hwmon_chip_info,
NULL);
if (IS_ERR(hwmon))
dev_warn(dev, "unable to register hwmon device: %pe\n", hwmon);
}
/*
* In the routines that deal directly with the isl12022 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
*/
static int isl12022_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct regmap *regmap = dev_get_drvdata(dev);
uint8_t buf[ISL12022_REG_INT + 1];
int ret;
ret = regmap_bulk_read(regmap, ISL12022_REG_SC, buf, sizeof(buf));
if (ret)
return ret;
dev_dbg(dev,
"raw data is sec=%02x, min=%02x, hr=%02x, mday=%02x, mon=%02x, year=%02x, wday=%02x, sr=%02x, int=%02x",
buf[ISL12022_REG_SC],
buf[ISL12022_REG_MN],
buf[ISL12022_REG_HR],
buf[ISL12022_REG_DT],
buf[ISL12022_REG_MO],
buf[ISL12022_REG_YR],
buf[ISL12022_REG_DW],
buf[ISL12022_REG_SR],
buf[ISL12022_REG_INT]);
tm->tm_sec = bcd2bin(buf[ISL12022_REG_SC] & 0x7F);
tm->tm_min = bcd2bin(buf[ISL12022_REG_MN] & 0x7F);
tm->tm_hour = bcd2bin(buf[ISL12022_REG_HR] & 0x3F);
tm->tm_mday = bcd2bin(buf[ISL12022_REG_DT] & 0x3F);
tm->tm_wday = buf[ISL12022_REG_DW] & 0x07;
tm->tm_mon = bcd2bin(buf[ISL12022_REG_MO] & 0x1F) - 1;
tm->tm_year = bcd2bin(buf[ISL12022_REG_YR]) + 100;
dev_dbg(dev, "%s: %ptR\n", __func__, tm);
return 0;
}
static int isl12022_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct regmap *regmap = dev_get_drvdata(dev);
int ret;
uint8_t buf[ISL12022_REG_DW + 1];
dev_dbg(dev, "%s: %ptR\n", __func__, tm);
/* Ensure the write enable bit is set. */
ret = regmap_update_bits(regmap, ISL12022_REG_INT,
ISL12022_INT_WRTC, ISL12022_INT_WRTC);
if (ret)
return ret;
/* hours, minutes and seconds */
buf[ISL12022_REG_SC] = bin2bcd(tm->tm_sec);
buf[ISL12022_REG_MN] = bin2bcd(tm->tm_min);
buf[ISL12022_REG_HR] = bin2bcd(tm->tm_hour) | ISL12022_HR_MIL;
buf[ISL12022_REG_DT] = bin2bcd(tm->tm_mday);
/* month, 1 - 12 */
buf[ISL12022_REG_MO] = bin2bcd(tm->tm_mon + 1);
/* year and century */
buf[ISL12022_REG_YR] = bin2bcd(tm->tm_year % 100);
buf[ISL12022_REG_DW] = tm->tm_wday & 0x07;
return regmap_bulk_write(regmap, ISL12022_REG_SC, buf, sizeof(buf));
}
static int isl12022_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
struct regmap *regmap = dev_get_drvdata(dev);
u32 user, val;
int ret;
switch (cmd) {
case RTC_VL_READ:
ret = regmap_read(regmap, ISL12022_REG_SR, &val);
if (ret)
return ret;
user = 0;
if (val & ISL12022_SR_LBAT85)
user |= RTC_VL_BACKUP_LOW;
if (val & ISL12022_SR_LBAT75)
user |= RTC_VL_BACKUP_EMPTY;
return put_user(user, (u32 __user *)arg);
default:
return -ENOIOCTLCMD;
}
}
static const struct rtc_class_ops isl12022_rtc_ops = {
.ioctl = isl12022_rtc_ioctl,
.read_time = isl12022_rtc_read_time,
.set_time = isl12022_rtc_set_time,
};
static const struct regmap_config regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.use_single_write = true,
};
static int isl12022_register_clock(struct device *dev)
{
struct regmap *regmap = dev_get_drvdata(dev);
struct clk_hw *hw;
int ret;
if (!device_property_present(dev, "#clock-cells")) {
/*
* Disabling the F_OUT pin reduces the power
* consumption in battery mode by ~25%.
*/
regmap_update_bits(regmap, ISL12022_REG_INT, ISL12022_INT_FO_MASK,
ISL12022_INT_FO_OFF);
return 0;
}
if (!IS_ENABLED(CONFIG_COMMON_CLK))
return 0;
/*
* For now, only support a fixed clock of 32768Hz (the reset default).
*/
ret = regmap_update_bits(regmap, ISL12022_REG_INT,
ISL12022_INT_FO_MASK, ISL12022_INT_FO_32K);
if (ret)
return ret;
hw = devm_clk_hw_register_fixed_rate(dev, "isl12022", NULL, 0, 32768);
if (IS_ERR(hw))
return PTR_ERR(hw);
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
static const u32 trip_levels[2][7] = {
{ 2125000, 2295000, 2550000, 2805000, 3060000, 4250000, 4675000 },
{ 1875000, 2025000, 2250000, 2475000, 2700000, 3750000, 4125000 },
};
static void isl12022_set_trip_levels(struct device *dev)
{
struct regmap *regmap = dev_get_drvdata(dev);
u32 levels[2] = {0, 0};
int ret, i, j, x[2];
u8 val, mask;
device_property_read_u32_array(dev, "isil,battery-trip-levels-microvolt",
levels, 2);
for (i = 0; i < 2; i++) {
for (j = 0; j < ARRAY_SIZE(trip_levels[i]) - 1; j++) {
if (levels[i] <= trip_levels[i][j])
break;
}
x[i] = j;
}
val = FIELD_PREP(ISL12022_REG_VB85_MASK, x[0]) |
FIELD_PREP(ISL12022_REG_VB75_MASK, x[1]);
mask = ISL12022_REG_VB85_MASK | ISL12022_REG_VB75_MASK;
ret = regmap_update_bits(regmap, ISL12022_REG_PWR_VBAT, mask, val);
if (ret)
dev_warn(dev, "unable to set battery alarm levels: %d\n", ret);
/*
* Force a write of the TSE bit in the BETA register, in order
* to trigger an update of the LBAT75 and LBAT85 bits in the
* status register. In battery backup mode, those bits have
* another meaning, so without this, they may contain stale
* values for up to a minute after power-on.
*/
regmap_write_bits(regmap, ISL12022_REG_BETA,
ISL12022_BETA_TSE, ISL12022_BETA_TSE);
}
static int isl12022_probe(struct i2c_client *client)
{
struct rtc_device *rtc;
struct regmap *regmap;
int ret;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
regmap = devm_regmap_init_i2c(client, ®map_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "regmap allocation failed\n");
return PTR_ERR(regmap);
}
dev_set_drvdata(&client->dev, regmap);
ret = isl12022_register_clock(&client->dev);
if (ret)
return ret;
isl12022_set_trip_levels(&client->dev);
isl12022_hwmon_register(&client->dev);
rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &isl12022_rtc_ops;
rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
rtc->range_max = RTC_TIMESTAMP_END_2099;
return devm_rtc_register_device(rtc);
}
static const struct of_device_id isl12022_dt_match[] = {
{ .compatible = "isl,isl12022" }, /* for backward compat., don't use */
{ .compatible = "isil,isl12022" },
{ },
};
MODULE_DEVICE_TABLE(of, isl12022_dt_match);
static const struct i2c_device_id isl12022_id[] = {
{ "isl12022", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, isl12022_id);
static struct i2c_driver isl12022_driver = {
.driver = {
.name = "rtc-isl12022",
.of_match_table = isl12022_dt_match,
},
.probe = isl12022_probe,
.id_table = isl12022_id,
};
module_i2c_driver(isl12022_driver);
MODULE_AUTHOR("[email protected]");
MODULE_DESCRIPTION("ISL 12022 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-isl12022.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Real Time Clock (RTC) Driver for i.MX53
* Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
* Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
*/
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>
#include <linux/rtc.h>
#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
#define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
#define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
#define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
#define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
#define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
#define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
#define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
#define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
#define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
#define SRTC_LPCR 0x10 /* LP Control Reg */
#define SRTC_LPSR 0x14 /* LP Status Reg */
#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
/* max. number of retries to read registers, 120 was max during test */
#define REG_READ_TIMEOUT 2000
struct mxc_rtc_data {
struct rtc_device *rtc;
void __iomem *ioaddr;
struct clk *clk;
spinlock_t lock; /* protects register access */
int irq;
};
/*
* This function does write synchronization for writes to the lp srtc block.
* To take care of the asynchronous CKIL clock, all writes from the IP domain
* will be synchronized to the CKIL domain.
* The caller should hold the pdata->lock
*/
static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
{
unsigned int i;
/* Wait for 3 CKIL cycles */
for (i = 0; i < 3; i++) {
const u32 count = readl(ioaddr + SRTC_LPSCLR);
unsigned int timeout = REG_READ_TIMEOUT;
while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
if (!--timeout) {
dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
return;
}
}
}
}
/* This function is the RTC interrupt service routine. */
static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
{
struct device *dev = dev_id;
struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
u32 lp_status;
u32 lp_cr;
spin_lock(&pdata->lock);
if (clk_enable(pdata->clk)) {
spin_unlock(&pdata->lock);
return IRQ_NONE;
}
lp_status = readl(ioaddr + SRTC_LPSR);
lp_cr = readl(ioaddr + SRTC_LPCR);
/* update irq data & counter */
if (lp_status & SRTC_LPSR_ALP) {
if (lp_cr & SRTC_LPCR_ALP)
rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
/* disable further lp alarm interrupts */
lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
}
/* Update interrupt enables */
writel(lp_cr, ioaddr + SRTC_LPCR);
/* clear interrupt status */
writel(lp_status, ioaddr + SRTC_LPSR);
mxc_rtc_sync_lp_locked(dev, ioaddr);
clk_disable(pdata->clk);
spin_unlock(&pdata->lock);
return IRQ_HANDLED;
}
/*
* Enable clk and aquire spinlock
* @return 0 if successful; non-zero otherwise.
*/
static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
{
int ret;
spin_lock_irq(&pdata->lock);
ret = clk_enable(pdata->clk);
if (ret) {
spin_unlock_irq(&pdata->lock);
return ret;
}
return 0;
}
static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
{
clk_disable(pdata->clk);
spin_unlock_irq(&pdata->lock);
return 0;
}
/*
* This function reads the current RTC time into tm in Gregorian date.
*
* @param tm contains the RTC time value upon return
*
* @return 0 if successful; non-zero otherwise.
*/
static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
const int clk_failed = clk_enable(pdata->clk);
if (!clk_failed) {
const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
rtc_time64_to_tm(now, tm);
clk_disable(pdata->clk);
return 0;
}
return clk_failed;
}
/*
* This function sets the internal RTC time based on tm in Gregorian date.
*
* @param tm the time value to be set in the RTC
*
* @return 0 if successful; non-zero otherwise.
*/
static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
time64_t time = rtc_tm_to_time64(tm);
int ret;
ret = mxc_rtc_lock(pdata);
if (ret)
return ret;
writel(time, pdata->ioaddr + SRTC_LPSCMR);
mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
return mxc_rtc_unlock(pdata);
}
/*
* This function reads the current alarm value into the passed in \b alrm
* argument. It updates the \b alrm's pending field value based on the whether
* an alarm interrupt occurs or not.
*
* @param alrm contains the RTC alarm value upon return
*
* @return 0 if successful; non-zero otherwise.
*/
static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
int ret;
ret = mxc_rtc_lock(pdata);
if (ret)
return ret;
rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
return mxc_rtc_unlock(pdata);
}
/*
* Enable/Disable alarm interrupt
* The caller should hold the pdata->lock
*/
static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
unsigned int enable)
{
u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
if (enable)
lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
else
lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
}
static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
{
struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
int ret = mxc_rtc_lock(pdata);
if (ret)
return ret;
mxc_rtc_alarm_irq_enable_locked(pdata, enable);
return mxc_rtc_unlock(pdata);
}
/*
* This function sets the RTC alarm based on passed in alrm.
*
* @param alrm the alarm value to be set in the RTC
*
* @return 0 if successful; non-zero otherwise.
*/
static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
const time64_t time = rtc_tm_to_time64(&alrm->time);
struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
int ret = mxc_rtc_lock(pdata);
if (ret)
return ret;
writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
/* clear alarm interrupt status bit */
writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
mxc_rtc_unlock(pdata);
return ret;
}
static const struct rtc_class_ops mxc_rtc_ops = {
.read_time = mxc_rtc_read_time,
.set_time = mxc_rtc_set_time,
.read_alarm = mxc_rtc_read_alarm,
.set_alarm = mxc_rtc_set_alarm,
.alarm_irq_enable = mxc_rtc_alarm_irq_enable,
};
static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
{
unsigned int timeout = REG_READ_TIMEOUT;
while (!(readl(ioaddr) & flag)) {
if (!--timeout)
return -EBUSY;
}
return 0;
}
static int mxc_rtc_probe(struct platform_device *pdev)
{
struct mxc_rtc_data *pdata;
void __iomem *ioaddr;
int ret = 0;
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pdata->ioaddr))
return PTR_ERR(pdata->ioaddr);
ioaddr = pdata->ioaddr;
pdata->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pdata->clk)) {
dev_err(&pdev->dev, "unable to get rtc clock!\n");
return PTR_ERR(pdata->clk);
}
spin_lock_init(&pdata->lock);
pdata->irq = platform_get_irq(pdev, 0);
if (pdata->irq < 0)
return pdata->irq;
device_init_wakeup(&pdev->dev, 1);
ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
if (ret)
dev_err(&pdev->dev, "failed to enable irq wake\n");
ret = clk_prepare_enable(pdata->clk);
if (ret)
return ret;
/* initialize glitch detect */
writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
/* clear lp interrupt status */
writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
/* move out of init state */
writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
if (ret) {
dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
clk_disable_unprepare(pdata->clk);
return ret;
}
/* move out of non-valid state */
writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
if (ret) {
dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
clk_disable_unprepare(pdata->clk);
return ret;
}
pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pdata->rtc)) {
clk_disable_unprepare(pdata->clk);
return PTR_ERR(pdata->rtc);
}
pdata->rtc->ops = &mxc_rtc_ops;
pdata->rtc->range_max = U32_MAX;
clk_disable(pdata->clk);
platform_set_drvdata(pdev, pdata);
ret =
devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
pdev->name, &pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "interrupt not available.\n");
clk_unprepare(pdata->clk);
return ret;
}
ret = devm_rtc_register_device(pdata->rtc);
if (ret < 0)
clk_unprepare(pdata->clk);
return ret;
}
static void mxc_rtc_remove(struct platform_device *pdev)
{
struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
clk_disable_unprepare(pdata->clk);
}
static const struct of_device_id mxc_ids[] = {
{ .compatible = "fsl,imx53-rtc", },
{}
};
MODULE_DEVICE_TABLE(of, mxc_ids);
static struct platform_driver mxc_rtc_driver = {
.driver = {
.name = "mxc_rtc_v2",
.of_match_table = mxc_ids,
},
.probe = mxc_rtc_probe,
.remove_new = mxc_rtc_remove,
};
module_platform_driver(mxc_rtc_driver);
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-mxc_v2.c |
// SPDX-License-Identifier: GPL-2.0-only
/* rtc-max6916.c
*
* Driver for MAXIM max6916 Low Current, SPI Compatible
* Real Time Clock
*
* Author : Venkat Prashanth B U <[email protected]>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
/* Registers in max6916 rtc */
#define MAX6916_SECONDS_REG 0x01
#define MAX6916_MINUTES_REG 0x02
#define MAX6916_HOURS_REG 0x03
#define MAX6916_DATE_REG 0x04
#define MAX6916_MONTH_REG 0x05
#define MAX6916_DAY_REG 0x06
#define MAX6916_YEAR_REG 0x07
#define MAX6916_CONTROL_REG 0x08
#define MAX6916_STATUS_REG 0x0C
#define MAX6916_CLOCK_BURST 0x3F
static int max6916_read_reg(struct device *dev, unsigned char address,
unsigned char *data)
{
struct spi_device *spi = to_spi_device(dev);
*data = address | 0x80;
return spi_write_then_read(spi, data, 1, data, 1);
}
static int max6916_write_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
buf[0] = address & 0x7F;
buf[1] = data;
return spi_write_then_read(spi, buf, 2, NULL, 0);
}
static int max6916_read_time(struct device *dev, struct rtc_time *dt)
{
struct spi_device *spi = to_spi_device(dev);
int err;
unsigned char buf[8];
buf[0] = MAX6916_CLOCK_BURST | 0x80;
err = spi_write_then_read(spi, buf, 1, buf, 8);
if (err)
return err;
dt->tm_sec = bcd2bin(buf[0]);
dt->tm_min = bcd2bin(buf[1]);
dt->tm_hour = bcd2bin(buf[2] & 0x3F);
dt->tm_mday = bcd2bin(buf[3]);
dt->tm_mon = bcd2bin(buf[4]) - 1;
dt->tm_wday = bcd2bin(buf[5]) - 1;
dt->tm_year = bcd2bin(buf[6]) + 100;
return 0;
}
static int max6916_set_time(struct device *dev, struct rtc_time *dt)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[9];
if (dt->tm_year < 100 || dt->tm_year > 199) {
dev_err(&spi->dev, "Year must be between 2000 and 2099. It's %d.\n",
dt->tm_year + 1900);
return -EINVAL;
}
buf[0] = MAX6916_CLOCK_BURST & 0x7F;
buf[1] = bin2bcd(dt->tm_sec);
buf[2] = bin2bcd(dt->tm_min);
buf[3] = (bin2bcd(dt->tm_hour) & 0X3F);
buf[4] = bin2bcd(dt->tm_mday);
buf[5] = bin2bcd(dt->tm_mon + 1);
buf[6] = bin2bcd(dt->tm_wday + 1);
buf[7] = bin2bcd(dt->tm_year % 100);
buf[8] = bin2bcd(0x00);
/* write the rtc settings */
return spi_write_then_read(spi, buf, 9, NULL, 0);
}
static const struct rtc_class_ops max6916_rtc_ops = {
.read_time = max6916_read_time,
.set_time = max6916_set_time,
};
static int max6916_probe(struct spi_device *spi)
{
struct rtc_device *rtc;
unsigned char data;
int res;
/* spi setup with max6916 in mode 3 and bits per word as 8 */
spi->mode = SPI_MODE_3;
spi->bits_per_word = 8;
spi_setup(spi);
/* RTC Settings */
res = max6916_read_reg(&spi->dev, MAX6916_SECONDS_REG, &data);
if (res)
return res;
/* Disable the write protect of rtc */
max6916_read_reg(&spi->dev, MAX6916_CONTROL_REG, &data);
data = data & ~(1 << 7);
max6916_write_reg(&spi->dev, MAX6916_CONTROL_REG, data);
/*Enable oscillator,disable oscillator stop flag, glitch filter*/
max6916_read_reg(&spi->dev, MAX6916_STATUS_REG, &data);
data = data & 0x1B;
max6916_write_reg(&spi->dev, MAX6916_STATUS_REG, data);
/* display the settings */
max6916_read_reg(&spi->dev, MAX6916_CONTROL_REG, &data);
dev_info(&spi->dev, "MAX6916 RTC CTRL Reg = 0x%02x\n", data);
max6916_read_reg(&spi->dev, MAX6916_STATUS_REG, &data);
dev_info(&spi->dev, "MAX6916 RTC Status Reg = 0x%02x\n", data);
rtc = devm_rtc_device_register(&spi->dev, "max6916",
&max6916_rtc_ops, THIS_MODULE);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
spi_set_drvdata(spi, rtc);
return 0;
}
static struct spi_driver max6916_driver = {
.driver = {
.name = "max6916",
},
.probe = max6916_probe,
};
module_spi_driver(max6916_driver);
MODULE_DESCRIPTION("MAX6916 SPI RTC DRIVER");
MODULE_AUTHOR("Venkat Prashanth B U <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-max6916.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ST M48T59 RTC driver
*
* Copyright (c) 2007 Wind River Systems, Inc.
*
* Author: Mark Zhan <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/rtc/m48t59.h>
#include <linux/bcd.h>
#include <linux/slab.h>
#ifndef NO_IRQ
#define NO_IRQ (-1)
#endif
#define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
#define M48T59_WRITE(val, reg) \
(pdata->write_byte(dev, pdata->offset + reg, val))
#define M48T59_SET_BITS(mask, reg) \
M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg))
#define M48T59_CLEAR_BITS(mask, reg) \
M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))
struct m48t59_private {
void __iomem *ioaddr;
int irq;
struct rtc_device *rtc;
spinlock_t lock; /* serialize the NVRAM and RTC access */
};
/*
* This is the generic access method when the chip is memory-mapped
*/
static void
m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
{
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
writeb(val, m48t59->ioaddr+ofs);
}
static u8
m48t59_mem_readb(struct device *dev, u32 ofs)
{
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
return readb(m48t59->ioaddr+ofs);
}
/*
* NOTE: M48T59 only uses BCD mode
*/
static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
unsigned long flags;
u8 val;
spin_lock_irqsave(&m48t59->lock, flags);
/* Issue the READ command */
M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
/* tm_mon is 0-11 */
tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
tm->tm_mday = bcd2bin(M48T59_READ(M48T59_MDAY));
val = M48T59_READ(M48T59_WDAY);
if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
(val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
dev_dbg(dev, "Century bit is enabled\n");
tm->tm_year += 100; /* one century */
}
#ifdef CONFIG_SPARC
/* Sun SPARC machines count years since 1968 */
tm->tm_year += 68;
#endif
tm->tm_wday = bcd2bin(val & 0x07);
tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
tm->tm_min = bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
tm->tm_sec = bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);
/* Clear the READ bit */
M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
spin_unlock_irqrestore(&m48t59->lock, flags);
dev_dbg(dev, "RTC read time %ptR\n", tm);
return 0;
}
static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
unsigned long flags;
u8 val = 0;
int year = tm->tm_year;
#ifdef CONFIG_SPARC
/* Sun SPARC machines count years since 1968 */
year -= 68;
#endif
dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
year + 1900, tm->tm_mon, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
if (year < 0)
return -EINVAL;
spin_lock_irqsave(&m48t59->lock, flags);
/* Issue the WRITE command */
M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
/* tm_mon is 0-11 */
M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);
if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
val = (M48T59_WDAY_CEB | M48T59_WDAY_CB);
val |= (bin2bcd(tm->tm_wday) & 0x07);
M48T59_WRITE(val, M48T59_WDAY);
/* Clear the WRITE bit */
M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
spin_unlock_irqrestore(&m48t59->lock, flags);
return 0;
}
/*
* Read alarm time and date in RTC
*/
static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
unsigned long flags;
u8 val;
/* If no irq, we don't support ALARM */
if (m48t59->irq == NO_IRQ)
return -EIO;
spin_lock_irqsave(&m48t59->lock, flags);
/* Issue the READ command */
M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
#ifdef CONFIG_SPARC
/* Sun SPARC machines count years since 1968 */
tm->tm_year += 68;
#endif
/* tm_mon is 0-11 */
tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
val = M48T59_READ(M48T59_WDAY);
if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
tm->tm_year += 100; /* one century */
tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));
/* Clear the READ bit */
M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
spin_unlock_irqrestore(&m48t59->lock, flags);
dev_dbg(dev, "RTC read alarm time %ptR\n", tm);
return rtc_valid_tm(tm);
}
/*
* Set alarm time and date in RTC
*/
static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
struct rtc_time *tm = &alrm->time;
u8 mday, hour, min, sec;
unsigned long flags;
int year = tm->tm_year;
#ifdef CONFIG_SPARC
/* Sun SPARC machines count years since 1968 */
year -= 68;
#endif
/* If no irq, we don't support ALARM */
if (m48t59->irq == NO_IRQ)
return -EIO;
if (year < 0)
return -EINVAL;
/*
* 0xff means "always match"
*/
mday = tm->tm_mday;
mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
if (mday == 0xff)
mday = M48T59_READ(M48T59_MDAY);
hour = tm->tm_hour;
hour = (hour < 24) ? bin2bcd(hour) : 0x00;
min = tm->tm_min;
min = (min < 60) ? bin2bcd(min) : 0x00;
sec = tm->tm_sec;
sec = (sec < 60) ? bin2bcd(sec) : 0x00;
spin_lock_irqsave(&m48t59->lock, flags);
/* Issue the WRITE command */
M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
M48T59_WRITE(mday, M48T59_ALARM_DATE);
M48T59_WRITE(hour, M48T59_ALARM_HOUR);
M48T59_WRITE(min, M48T59_ALARM_MIN);
M48T59_WRITE(sec, M48T59_ALARM_SEC);
/* Clear the WRITE bit */
M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
spin_unlock_irqrestore(&m48t59->lock, flags);
dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
year + 1900, tm->tm_mon, tm->tm_mday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
return 0;
}
/*
* Handle commands from user-space
*/
static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
unsigned long flags;
spin_lock_irqsave(&m48t59->lock, flags);
if (enabled)
M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
else
M48T59_WRITE(0x00, M48T59_INTR);
spin_unlock_irqrestore(&m48t59->lock, flags);
return 0;
}
static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
unsigned long flags;
u8 val;
spin_lock_irqsave(&m48t59->lock, flags);
val = M48T59_READ(M48T59_FLAGS);
spin_unlock_irqrestore(&m48t59->lock, flags);
seq_printf(seq, "battery\t\t: %s\n",
(val & M48T59_FLAGS_BF) ? "low" : "normal");
return 0;
}
/*
* IRQ handler for the RTC
*/
static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
{
struct device *dev = (struct device *)dev_id;
struct m48t59_plat_data *pdata = dev_get_platdata(dev);
struct m48t59_private *m48t59 = dev_get_drvdata(dev);
u8 event;
spin_lock(&m48t59->lock);
event = M48T59_READ(M48T59_FLAGS);
spin_unlock(&m48t59->lock);
if (event & M48T59_FLAGS_AF) {
rtc_update_irq(m48t59->rtc, 1, (RTC_AF | RTC_IRQF));
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static const struct rtc_class_ops m48t59_rtc_ops = {
.read_time = m48t59_rtc_read_time,
.set_time = m48t59_rtc_set_time,
.read_alarm = m48t59_rtc_readalarm,
.set_alarm = m48t59_rtc_setalarm,
.proc = m48t59_rtc_proc,
.alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
};
static int m48t59_nvram_read(void *priv, unsigned int offset, void *val,
size_t size)
{
struct platform_device *pdev = priv;
struct device *dev = &pdev->dev;
struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
ssize_t cnt = 0;
unsigned long flags;
u8 *buf = val;
spin_lock_irqsave(&m48t59->lock, flags);
for (; cnt < size; cnt++)
*buf++ = M48T59_READ(cnt);
spin_unlock_irqrestore(&m48t59->lock, flags);
return 0;
}
static int m48t59_nvram_write(void *priv, unsigned int offset, void *val,
size_t size)
{
struct platform_device *pdev = priv;
struct device *dev = &pdev->dev;
struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
ssize_t cnt = 0;
unsigned long flags;
u8 *buf = val;
spin_lock_irqsave(&m48t59->lock, flags);
for (; cnt < size; cnt++)
M48T59_WRITE(*buf++, cnt);
spin_unlock_irqrestore(&m48t59->lock, flags);
return 0;
}
static int m48t59_rtc_probe(struct platform_device *pdev)
{
struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
struct m48t59_private *m48t59 = NULL;
struct resource *res;
int ret = -ENOMEM;
struct nvmem_config nvmem_cfg = {
.name = "m48t59-",
.word_size = 1,
.stride = 1,
.reg_read = m48t59_nvram_read,
.reg_write = m48t59_nvram_write,
.priv = pdev,
};
/* This chip could be memory-mapped or I/O-mapped */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!res)
return -EINVAL;
}
if (res->flags & IORESOURCE_IO) {
/* If we are I/O-mapped, the platform should provide
* the operations accessing chip registers.
*/
if (!pdata || !pdata->write_byte || !pdata->read_byte)
return -EINVAL;
} else if (res->flags & IORESOURCE_MEM) {
/* we are memory-mapped */
if (!pdata) {
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
GFP_KERNEL);
if (!pdata)
return -ENOMEM;
/* Ensure we only kmalloc platform data once */
pdev->dev.platform_data = pdata;
}
if (!pdata->type)
pdata->type = M48T59RTC_TYPE_M48T59;
/* Try to use the generic memory read/write ops */
if (!pdata->write_byte)
pdata->write_byte = m48t59_mem_writeb;
if (!pdata->read_byte)
pdata->read_byte = m48t59_mem_readb;
}
m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
if (!m48t59)
return -ENOMEM;
m48t59->ioaddr = pdata->ioaddr;
if (!m48t59->ioaddr) {
/* ioaddr not mapped externally */
m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!m48t59->ioaddr)
return ret;
}
/* Try to get irq number. We also can work in
* the mode without IRQ.
*/
m48t59->irq = platform_get_irq_optional(pdev, 0);
if (m48t59->irq <= 0)
m48t59->irq = NO_IRQ;
if (m48t59->irq != NO_IRQ) {
ret = devm_request_irq(&pdev->dev, m48t59->irq,
m48t59_rtc_interrupt, IRQF_SHARED,
"rtc-m48t59", &pdev->dev);
if (ret)
return ret;
}
m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(m48t59->rtc))
return PTR_ERR(m48t59->rtc);
switch (pdata->type) {
case M48T59RTC_TYPE_M48T59:
pdata->offset = 0x1ff0;
break;
case M48T59RTC_TYPE_M48T02:
clear_bit(RTC_FEATURE_ALARM, m48t59->rtc->features);
pdata->offset = 0x7f0;
break;
case M48T59RTC_TYPE_M48T08:
clear_bit(RTC_FEATURE_ALARM, m48t59->rtc->features);
pdata->offset = 0x1ff0;
break;
default:
dev_err(&pdev->dev, "Unknown RTC type\n");
return -ENODEV;
}
spin_lock_init(&m48t59->lock);
platform_set_drvdata(pdev, m48t59);
m48t59->rtc->ops = &m48t59_rtc_ops;
nvmem_cfg.size = pdata->offset;
ret = devm_rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
if (ret)
return ret;
ret = devm_rtc_register_device(m48t59->rtc);
if (ret)
return ret;
return 0;
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:rtc-m48t59");
static struct platform_driver m48t59_rtc_driver = {
.driver = {
.name = "rtc-m48t59",
},
.probe = m48t59_rtc_probe,
};
module_platform_driver(m48t59_rtc_driver);
MODULE_AUTHOR("Mark Zhan <[email protected]>");
MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-m48t59.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* rtc-twl.c -- TWL Real Time Clock interface
*
* Copyright (C) 2007 MontaVista Software, Inc
* Author: Alexandre Rusev <[email protected]>
*
* Based on original TI driver twl4030-rtc.c
* Copyright (C) 2006 Texas Instruments, Inc.
*
* Based on rtc-omap.c
* Copyright (C) 2003 MontaVista Software, Inc.
* Author: George G. Davis <[email protected]> or <[email protected]>
* Copyright (C) 2006 David Brownell
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/twl.h>
enum twl_class {
TWL_4030 = 0,
TWL_6030,
};
/*
* RTC block register offsets (use TWL_MODULE_RTC)
*/
enum {
REG_SECONDS_REG = 0,
REG_MINUTES_REG,
REG_HOURS_REG,
REG_DAYS_REG,
REG_MONTHS_REG,
REG_YEARS_REG,
REG_WEEKS_REG,
REG_ALARM_SECONDS_REG,
REG_ALARM_MINUTES_REG,
REG_ALARM_HOURS_REG,
REG_ALARM_DAYS_REG,
REG_ALARM_MONTHS_REG,
REG_ALARM_YEARS_REG,
REG_RTC_CTRL_REG,
REG_RTC_STATUS_REG,
REG_RTC_INTERRUPTS_REG,
REG_RTC_COMP_LSB_REG,
REG_RTC_COMP_MSB_REG,
};
static const u8 twl4030_rtc_reg_map[] = {
[REG_SECONDS_REG] = 0x00,
[REG_MINUTES_REG] = 0x01,
[REG_HOURS_REG] = 0x02,
[REG_DAYS_REG] = 0x03,
[REG_MONTHS_REG] = 0x04,
[REG_YEARS_REG] = 0x05,
[REG_WEEKS_REG] = 0x06,
[REG_ALARM_SECONDS_REG] = 0x07,
[REG_ALARM_MINUTES_REG] = 0x08,
[REG_ALARM_HOURS_REG] = 0x09,
[REG_ALARM_DAYS_REG] = 0x0A,
[REG_ALARM_MONTHS_REG] = 0x0B,
[REG_ALARM_YEARS_REG] = 0x0C,
[REG_RTC_CTRL_REG] = 0x0D,
[REG_RTC_STATUS_REG] = 0x0E,
[REG_RTC_INTERRUPTS_REG] = 0x0F,
[REG_RTC_COMP_LSB_REG] = 0x10,
[REG_RTC_COMP_MSB_REG] = 0x11,
};
static const u8 twl6030_rtc_reg_map[] = {
[REG_SECONDS_REG] = 0x00,
[REG_MINUTES_REG] = 0x01,
[REG_HOURS_REG] = 0x02,
[REG_DAYS_REG] = 0x03,
[REG_MONTHS_REG] = 0x04,
[REG_YEARS_REG] = 0x05,
[REG_WEEKS_REG] = 0x06,
[REG_ALARM_SECONDS_REG] = 0x08,
[REG_ALARM_MINUTES_REG] = 0x09,
[REG_ALARM_HOURS_REG] = 0x0A,
[REG_ALARM_DAYS_REG] = 0x0B,
[REG_ALARM_MONTHS_REG] = 0x0C,
[REG_ALARM_YEARS_REG] = 0x0D,
[REG_RTC_CTRL_REG] = 0x10,
[REG_RTC_STATUS_REG] = 0x11,
[REG_RTC_INTERRUPTS_REG] = 0x12,
[REG_RTC_COMP_LSB_REG] = 0x13,
[REG_RTC_COMP_MSB_REG] = 0x14,
};
/* RTC_CTRL_REG bitfields */
#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
#define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
/* RTC_STATUS_REG bitfields */
#define BIT_RTC_STATUS_REG_RUN_M 0x02
#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
#define BIT_RTC_STATUS_REG_ALARM_M 0x40
#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
/* RTC_INTERRUPTS_REG bitfields */
#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
#define ALL_TIME_REGS 6
/*----------------------------------------------------------------------*/
struct twl_rtc {
struct device *dev;
struct rtc_device *rtc;
u8 *reg_map;
/*
* Cache the value for timer/alarm interrupts register; this is
* only changed by callers holding rtc ops lock (or resume).
*/
unsigned char rtc_irq_bits;
bool wake_enabled;
#ifdef CONFIG_PM_SLEEP
unsigned char irqstat;
#endif
enum twl_class class;
};
/*
* Supports 1 byte read from TWL RTC register.
*/
static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg)
{
int ret;
ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
if (ret < 0)
pr_err("Could not read TWL register %X - error %d\n", reg, ret);
return ret;
}
/*
* Supports 1 byte write to TWL RTC registers.
*/
static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg)
{
int ret;
ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg]));
if (ret < 0)
pr_err("Could not write TWL register %X - error %d\n",
reg, ret);
return ret;
}
/*
* Enable 1/second update and/or alarm interrupts.
*/
static int set_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
{
unsigned char val;
int ret;
/* if the bit is set, return from here */
if (twl_rtc->rtc_irq_bits & bit)
return 0;
val = twl_rtc->rtc_irq_bits | bit;
val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
if (ret == 0)
twl_rtc->rtc_irq_bits = val;
return ret;
}
/*
* Disable update and/or alarm interrupts.
*/
static int mask_rtc_irq_bit(struct twl_rtc *twl_rtc, unsigned char bit)
{
unsigned char val;
int ret;
/* if the bit is clear, return from here */
if (!(twl_rtc->rtc_irq_bits & bit))
return 0;
val = twl_rtc->rtc_irq_bits & ~bit;
ret = twl_rtc_write_u8(twl_rtc, val, REG_RTC_INTERRUPTS_REG);
if (ret == 0)
twl_rtc->rtc_irq_bits = val;
return ret;
}
static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
struct platform_device *pdev = to_platform_device(dev);
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
int irq = platform_get_irq(pdev, 0);
int ret;
if (enabled) {
ret = set_rtc_irq_bit(twl_rtc,
BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
if (device_can_wakeup(dev) && !twl_rtc->wake_enabled) {
enable_irq_wake(irq);
twl_rtc->wake_enabled = true;
}
} else {
ret = mask_rtc_irq_bit(twl_rtc,
BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
if (twl_rtc->wake_enabled) {
disable_irq_wake(irq);
twl_rtc->wake_enabled = false;
}
}
return ret;
}
/*
* Gets current TWL RTC time and date parameters.
*
* The RTC's time/alarm representation is not what gmtime(3) requires
* Linux to use:
*
* - Months are 1..12 vs Linux 0-11
* - Years are 0..99 vs Linux 1900..N (we assume 21st century)
*/
static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
unsigned char rtc_data[ALL_TIME_REGS];
int ret;
u8 save_control;
u8 rtc_control;
ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
if (ret < 0) {
dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
return ret;
}
/* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
if (twl_rtc->class == TWL_6030) {
if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
ret = twl_rtc_write_u8(twl_rtc, save_control,
REG_RTC_CTRL_REG);
if (ret < 0) {
dev_err(dev, "%s clr GET_TIME, error %d\n",
__func__, ret);
return ret;
}
}
}
/* Copy RTC counting registers to static registers or latches */
rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
/* for twl6030/32 enable read access to static shadowed registers */
if (twl_rtc->class == TWL_6030)
rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
ret = twl_rtc_write_u8(twl_rtc, rtc_control, REG_RTC_CTRL_REG);
if (ret < 0) {
dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
return ret;
}
ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
(twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
if (ret < 0) {
dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
return ret;
}
/* for twl6030 restore original state of rtc control register */
if (twl_rtc->class == TWL_6030) {
ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
if (ret < 0) {
dev_err(dev, "%s: restore CTRL_REG, error %d\n",
__func__, ret);
return ret;
}
}
tm->tm_sec = bcd2bin(rtc_data[0]);
tm->tm_min = bcd2bin(rtc_data[1]);
tm->tm_hour = bcd2bin(rtc_data[2]);
tm->tm_mday = bcd2bin(rtc_data[3]);
tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
tm->tm_year = bcd2bin(rtc_data[5]) + 100;
return ret;
}
static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
unsigned char save_control;
unsigned char rtc_data[ALL_TIME_REGS];
int ret;
rtc_data[0] = bin2bcd(tm->tm_sec);
rtc_data[1] = bin2bcd(tm->tm_min);
rtc_data[2] = bin2bcd(tm->tm_hour);
rtc_data[3] = bin2bcd(tm->tm_mday);
rtc_data[4] = bin2bcd(tm->tm_mon + 1);
rtc_data[5] = bin2bcd(tm->tm_year - 100);
/* Stop RTC while updating the TC registers */
ret = twl_rtc_read_u8(twl_rtc, &save_control, REG_RTC_CTRL_REG);
if (ret < 0)
goto out;
save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
if (ret < 0)
goto out;
/* update all the time registers in one shot */
ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
(twl_rtc->reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
if (ret < 0) {
dev_err(dev, "rtc_set_time error %d\n", ret);
goto out;
}
/* Start back RTC */
save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
ret = twl_rtc_write_u8(twl_rtc, save_control, REG_RTC_CTRL_REG);
out:
return ret;
}
/*
* Gets current TWL RTC alarm time.
*/
static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
unsigned char rtc_data[ALL_TIME_REGS];
int ret;
ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
if (ret < 0) {
dev_err(dev, "rtc_read_alarm error %d\n", ret);
return ret;
}
/* some of these fields may be wildcard/"match all" */
alm->time.tm_sec = bcd2bin(rtc_data[0]);
alm->time.tm_min = bcd2bin(rtc_data[1]);
alm->time.tm_hour = bcd2bin(rtc_data[2]);
alm->time.tm_mday = bcd2bin(rtc_data[3]);
alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
/* report cached alarm enable state */
if (twl_rtc->rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
alm->enabled = 1;
return ret;
}
static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
unsigned char alarm_data[ALL_TIME_REGS];
int ret;
ret = twl_rtc_alarm_irq_enable(dev, 0);
if (ret)
goto out;
alarm_data[0] = bin2bcd(alm->time.tm_sec);
alarm_data[1] = bin2bcd(alm->time.tm_min);
alarm_data[2] = bin2bcd(alm->time.tm_hour);
alarm_data[3] = bin2bcd(alm->time.tm_mday);
alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
/* update all the alarm registers in one shot */
ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
twl_rtc->reg_map[REG_ALARM_SECONDS_REG], ALL_TIME_REGS);
if (ret) {
dev_err(dev, "rtc_set_alarm error %d\n", ret);
goto out;
}
if (alm->enabled)
ret = twl_rtc_alarm_irq_enable(dev, 1);
out:
return ret;
}
static irqreturn_t twl_rtc_interrupt(int irq, void *data)
{
struct twl_rtc *twl_rtc = data;
unsigned long events;
int ret = IRQ_NONE;
int res;
u8 rd_reg;
res = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
if (res)
goto out;
/*
* Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
* only one (ALARM or RTC) interrupt source may be enabled
* at time, we also could check our results
* by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
*/
if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
events = RTC_IRQF | RTC_AF;
else
events = RTC_IRQF | RTC_PF;
res = twl_rtc_write_u8(twl_rtc, BIT_RTC_STATUS_REG_ALARM_M,
REG_RTC_STATUS_REG);
if (res)
goto out;
if (twl_rtc->class == TWL_4030) {
/* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
* needs 2 reads to clear the interrupt. One read is done in
* do_twl_pwrirq(). Doing the second read, to clear
* the bit.
*
* FIXME the reason PWR_ISR1 needs an extra read is that
* RTC_IF retriggered until we cleared REG_ALARM_M above.
* But re-reading like this is a bad hack; by doing so we
* risk wrongly clearing status for some other IRQ (losing
* the interrupt). Be smarter about handling RTC_UF ...
*/
res = twl_i2c_read_u8(TWL4030_MODULE_INT,
&rd_reg, TWL4030_INT_PWR_ISR1);
if (res)
goto out;
}
/* Notify RTC core on event */
rtc_update_irq(twl_rtc->rtc, 1, events);
ret = IRQ_HANDLED;
out:
return ret;
}
static const struct rtc_class_ops twl_rtc_ops = {
.read_time = twl_rtc_read_time,
.set_time = twl_rtc_set_time,
.read_alarm = twl_rtc_read_alarm,
.set_alarm = twl_rtc_set_alarm,
.alarm_irq_enable = twl_rtc_alarm_irq_enable,
};
static int twl_nvram_read(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return twl_i2c_read((long)priv, val, offset, bytes);
}
static int twl_nvram_write(void *priv, unsigned int offset, void *val,
size_t bytes)
{
return twl_i2c_write((long)priv, val, offset, bytes);
}
/*----------------------------------------------------------------------*/
static int twl_rtc_probe(struct platform_device *pdev)
{
struct twl_rtc *twl_rtc;
struct nvmem_config nvmem_cfg;
struct device_node *np = pdev->dev.of_node;
int ret = -EINVAL;
int irq = platform_get_irq(pdev, 0);
u8 rd_reg;
if (!np) {
dev_err(&pdev->dev, "no DT info\n");
return -EINVAL;
}
if (irq <= 0)
return ret;
twl_rtc = devm_kzalloc(&pdev->dev, sizeof(*twl_rtc), GFP_KERNEL);
if (!twl_rtc)
return -ENOMEM;
if (twl_class_is_4030()) {
twl_rtc->class = TWL_4030;
twl_rtc->reg_map = (u8 *)twl4030_rtc_reg_map;
} else if (twl_class_is_6030()) {
twl_rtc->class = TWL_6030;
twl_rtc->reg_map = (u8 *)twl6030_rtc_reg_map;
} else {
dev_err(&pdev->dev, "TWL Class not supported.\n");
return -EINVAL;
}
ret = twl_rtc_read_u8(twl_rtc, &rd_reg, REG_RTC_STATUS_REG);
if (ret < 0)
return ret;
if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
dev_warn(&pdev->dev, "Power up reset detected.\n");
if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
/* Clear RTC Power up reset and pending alarm interrupts */
ret = twl_rtc_write_u8(twl_rtc, rd_reg, REG_RTC_STATUS_REG);
if (ret < 0)
return ret;
if (twl_rtc->class == TWL_6030) {
twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
REG_INT_MSK_LINE_A);
twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
REG_INT_MSK_STS_A);
}
ret = twl_rtc_write_u8(twl_rtc, BIT_RTC_CTRL_REG_STOP_RTC_M,
REG_RTC_CTRL_REG);
if (ret < 0)
return ret;
/* ensure interrupts are disabled, bootloaders can be strange */
ret = twl_rtc_write_u8(twl_rtc, 0, REG_RTC_INTERRUPTS_REG);
if (ret < 0)
dev_warn(&pdev->dev, "unable to disable interrupt\n");
/* init cached IRQ enable bits */
ret = twl_rtc_read_u8(twl_rtc, &twl_rtc->rtc_irq_bits,
REG_RTC_INTERRUPTS_REG);
if (ret < 0)
return ret;
platform_set_drvdata(pdev, twl_rtc);
device_init_wakeup(&pdev->dev, 1);
twl_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
&twl_rtc_ops, THIS_MODULE);
if (IS_ERR(twl_rtc->rtc))
return PTR_ERR(twl_rtc->rtc);
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
twl_rtc_interrupt,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
dev_name(&twl_rtc->rtc->dev), twl_rtc);
if (ret < 0) {
dev_err(&pdev->dev, "IRQ is not free.\n");
return ret;
}
memset(&nvmem_cfg, 0, sizeof(nvmem_cfg));
nvmem_cfg.name = "twl-secured-";
nvmem_cfg.type = NVMEM_TYPE_BATTERY_BACKED;
nvmem_cfg.reg_read = twl_nvram_read,
nvmem_cfg.reg_write = twl_nvram_write,
nvmem_cfg.word_size = 1;
nvmem_cfg.stride = 1;
if (twl_class_is_4030()) {
/* 20 bytes SECURED_REG area */
nvmem_cfg.size = 20;
nvmem_cfg.priv = (void *)TWL_MODULE_SECURED_REG;
devm_rtc_nvmem_register(twl_rtc->rtc, &nvmem_cfg);
/* 8 bytes BACKUP area */
nvmem_cfg.name = "twl-backup-";
nvmem_cfg.size = 8;
nvmem_cfg.priv = (void *)TWL4030_MODULE_BACKUP;
devm_rtc_nvmem_register(twl_rtc->rtc, &nvmem_cfg);
} else {
/* 8 bytes SECURED_REG area */
nvmem_cfg.size = 8;
nvmem_cfg.priv = (void *)TWL_MODULE_SECURED_REG;
devm_rtc_nvmem_register(twl_rtc->rtc, &nvmem_cfg);
}
return 0;
}
/*
* Disable all TWL RTC module interrupts.
* Sets status flag to free.
*/
static void twl_rtc_remove(struct platform_device *pdev)
{
struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
/* leave rtc running, but disable irqs */
mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
if (twl_rtc->class == TWL_6030) {
twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
REG_INT_MSK_LINE_A);
twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
REG_INT_MSK_STS_A);
}
}
static void twl_rtc_shutdown(struct platform_device *pdev)
{
struct twl_rtc *twl_rtc = platform_get_drvdata(pdev);
/* mask timer interrupts, but leave alarm interrupts on to enable
power-on when alarm is triggered */
mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
}
#ifdef CONFIG_PM_SLEEP
static int twl_rtc_suspend(struct device *dev)
{
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
twl_rtc->irqstat = twl_rtc->rtc_irq_bits;
mask_rtc_irq_bit(twl_rtc, BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
return 0;
}
static int twl_rtc_resume(struct device *dev)
{
struct twl_rtc *twl_rtc = dev_get_drvdata(dev);
set_rtc_irq_bit(twl_rtc, twl_rtc->irqstat);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
static const struct of_device_id twl_rtc_of_match[] = {
{.compatible = "ti,twl4030-rtc", },
{ },
};
MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
static struct platform_driver twl4030rtc_driver = {
.probe = twl_rtc_probe,
.remove_new = twl_rtc_remove,
.shutdown = twl_rtc_shutdown,
.driver = {
.name = "twl_rtc",
.pm = &twl_rtc_pm_ops,
.of_match_table = twl_rtc_of_match,
},
};
module_platform_driver(twl4030rtc_driver);
MODULE_AUTHOR("Texas Instruments, MontaVista Software");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-twl.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Oleksij Rempel <[email protected]>
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
/* Miscellaneous registers */
/* Interrupt Location Register */
#define HW_ILR 0x00
#define BM_RTCALF BIT(1)
#define BM_RTCCIF BIT(0)
/* Clock Control Register */
#define HW_CCR 0x08
/* Calibration counter disable */
#define BM_CCALOFF BIT(4)
/* Reset internal oscillator divider */
#define BM_CTCRST BIT(1)
/* Clock Enable */
#define BM_CLKEN BIT(0)
/* Counter Increment Interrupt Register */
#define HW_CIIR 0x0C
#define BM_CIIR_IMYEAR BIT(7)
#define BM_CIIR_IMMON BIT(6)
#define BM_CIIR_IMDOY BIT(5)
#define BM_CIIR_IMDOW BIT(4)
#define BM_CIIR_IMDOM BIT(3)
#define BM_CIIR_IMHOUR BIT(2)
#define BM_CIIR_IMMIN BIT(1)
#define BM_CIIR_IMSEC BIT(0)
/* Alarm Mask Register */
#define HW_AMR 0x10
#define BM_AMR_IMYEAR BIT(7)
#define BM_AMR_IMMON BIT(6)
#define BM_AMR_IMDOY BIT(5)
#define BM_AMR_IMDOW BIT(4)
#define BM_AMR_IMDOM BIT(3)
#define BM_AMR_IMHOUR BIT(2)
#define BM_AMR_IMMIN BIT(1)
#define BM_AMR_IMSEC BIT(0)
#define BM_AMR_OFF 0xff
/* Consolidated time registers */
#define HW_CTIME0 0x14
#define BM_CTIME0_DOW_S 24
#define BM_CTIME0_DOW_M 0x7
#define BM_CTIME0_HOUR_S 16
#define BM_CTIME0_HOUR_M 0x1f
#define BM_CTIME0_MIN_S 8
#define BM_CTIME0_MIN_M 0x3f
#define BM_CTIME0_SEC_S 0
#define BM_CTIME0_SEC_M 0x3f
#define HW_CTIME1 0x18
#define BM_CTIME1_YEAR_S 16
#define BM_CTIME1_YEAR_M 0xfff
#define BM_CTIME1_MON_S 8
#define BM_CTIME1_MON_M 0xf
#define BM_CTIME1_DOM_S 0
#define BM_CTIME1_DOM_M 0x1f
#define HW_CTIME2 0x1C
#define BM_CTIME2_DOY_S 0
#define BM_CTIME2_DOY_M 0xfff
/* Time counter registers */
#define HW_SEC 0x20
#define HW_MIN 0x24
#define HW_HOUR 0x28
#define HW_DOM 0x2C
#define HW_DOW 0x30
#define HW_DOY 0x34
#define HW_MONTH 0x38
#define HW_YEAR 0x3C
#define HW_CALIBRATION 0x40
#define BM_CALDIR_BACK BIT(17)
#define BM_CALVAL_M 0x1ffff
/* General purpose registers */
#define HW_GPREG0 0x44
#define HW_GPREG1 0x48
#define HW_GPREG2 0x4C
#define HW_GPREG3 0x50
#define HW_GPREG4 0x54
/* Alarm register group */
#define HW_ALSEC 0x60
#define HW_ALMIN 0x64
#define HW_ALHOUR 0x68
#define HW_ALDOM 0x6C
#define HW_ALDOW 0x70
#define HW_ALDOY 0x74
#define HW_ALMON 0x78
#define HW_ALYEAR 0x7C
struct asm9260_rtc_priv {
struct device *dev;
void __iomem *iobase;
struct rtc_device *rtc;
struct clk *clk;
};
static irqreturn_t asm9260_rtc_irq(int irq, void *dev_id)
{
struct asm9260_rtc_priv *priv = dev_id;
u32 isr;
unsigned long events = 0;
rtc_lock(priv->rtc);
isr = ioread32(priv->iobase + HW_CIIR);
if (!isr) {
rtc_unlock(priv->rtc);
return IRQ_NONE;
}
iowrite32(0, priv->iobase + HW_CIIR);
rtc_unlock(priv->rtc);
events |= RTC_AF | RTC_IRQF;
rtc_update_irq(priv->rtc, 1, events);
return IRQ_HANDLED;
}
static int asm9260_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct asm9260_rtc_priv *priv = dev_get_drvdata(dev);
u32 ctime0, ctime1, ctime2;
ctime0 = ioread32(priv->iobase + HW_CTIME0);
ctime1 = ioread32(priv->iobase + HW_CTIME1);
ctime2 = ioread32(priv->iobase + HW_CTIME2);
if (ctime1 != ioread32(priv->iobase + HW_CTIME1)) {
/*
* woops, counter flipped right now. Now we are safe
* to reread.
*/
ctime0 = ioread32(priv->iobase + HW_CTIME0);
ctime1 = ioread32(priv->iobase + HW_CTIME1);
ctime2 = ioread32(priv->iobase + HW_CTIME2);
}
tm->tm_sec = (ctime0 >> BM_CTIME0_SEC_S) & BM_CTIME0_SEC_M;
tm->tm_min = (ctime0 >> BM_CTIME0_MIN_S) & BM_CTIME0_MIN_M;
tm->tm_hour = (ctime0 >> BM_CTIME0_HOUR_S) & BM_CTIME0_HOUR_M;
tm->tm_wday = (ctime0 >> BM_CTIME0_DOW_S) & BM_CTIME0_DOW_M;
tm->tm_mday = (ctime1 >> BM_CTIME1_DOM_S) & BM_CTIME1_DOM_M;
tm->tm_mon = (ctime1 >> BM_CTIME1_MON_S) & BM_CTIME1_MON_M;
tm->tm_year = (ctime1 >> BM_CTIME1_YEAR_S) & BM_CTIME1_YEAR_M;
tm->tm_yday = (ctime2 >> BM_CTIME2_DOY_S) & BM_CTIME2_DOY_M;
return 0;
}
static int asm9260_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct asm9260_rtc_priv *priv = dev_get_drvdata(dev);
/*
* make sure SEC counter will not flip other counter on write time,
* real value will be written at the enf of sequence.
*/
iowrite32(0, priv->iobase + HW_SEC);
iowrite32(tm->tm_year, priv->iobase + HW_YEAR);
iowrite32(tm->tm_mon, priv->iobase + HW_MONTH);
iowrite32(tm->tm_mday, priv->iobase + HW_DOM);
iowrite32(tm->tm_wday, priv->iobase + HW_DOW);
iowrite32(tm->tm_yday, priv->iobase + HW_DOY);
iowrite32(tm->tm_hour, priv->iobase + HW_HOUR);
iowrite32(tm->tm_min, priv->iobase + HW_MIN);
iowrite32(tm->tm_sec, priv->iobase + HW_SEC);
return 0;
}
static int asm9260_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct asm9260_rtc_priv *priv = dev_get_drvdata(dev);
alrm->time.tm_year = ioread32(priv->iobase + HW_ALYEAR);
alrm->time.tm_mon = ioread32(priv->iobase + HW_ALMON);
alrm->time.tm_mday = ioread32(priv->iobase + HW_ALDOM);
alrm->time.tm_wday = ioread32(priv->iobase + HW_ALDOW);
alrm->time.tm_yday = ioread32(priv->iobase + HW_ALDOY);
alrm->time.tm_hour = ioread32(priv->iobase + HW_ALHOUR);
alrm->time.tm_min = ioread32(priv->iobase + HW_ALMIN);
alrm->time.tm_sec = ioread32(priv->iobase + HW_ALSEC);
alrm->enabled = ioread32(priv->iobase + HW_AMR) ? 1 : 0;
alrm->pending = ioread32(priv->iobase + HW_CIIR) ? 1 : 0;
return rtc_valid_tm(&alrm->time);
}
static int asm9260_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct asm9260_rtc_priv *priv = dev_get_drvdata(dev);
iowrite32(alrm->time.tm_year, priv->iobase + HW_ALYEAR);
iowrite32(alrm->time.tm_mon, priv->iobase + HW_ALMON);
iowrite32(alrm->time.tm_mday, priv->iobase + HW_ALDOM);
iowrite32(alrm->time.tm_wday, priv->iobase + HW_ALDOW);
iowrite32(alrm->time.tm_yday, priv->iobase + HW_ALDOY);
iowrite32(alrm->time.tm_hour, priv->iobase + HW_ALHOUR);
iowrite32(alrm->time.tm_min, priv->iobase + HW_ALMIN);
iowrite32(alrm->time.tm_sec, priv->iobase + HW_ALSEC);
iowrite32(alrm->enabled ? 0 : BM_AMR_OFF, priv->iobase + HW_AMR);
return 0;
}
static int asm9260_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct asm9260_rtc_priv *priv = dev_get_drvdata(dev);
iowrite32(enabled ? 0 : BM_AMR_OFF, priv->iobase + HW_AMR);
return 0;
}
static const struct rtc_class_ops asm9260_rtc_ops = {
.read_time = asm9260_rtc_read_time,
.set_time = asm9260_rtc_set_time,
.read_alarm = asm9260_rtc_read_alarm,
.set_alarm = asm9260_rtc_set_alarm,
.alarm_irq_enable = asm9260_alarm_irq_enable,
};
static int asm9260_rtc_probe(struct platform_device *pdev)
{
struct asm9260_rtc_priv *priv;
struct device *dev = &pdev->dev;
int irq_alarm, ret;
u32 ccr;
priv = devm_kzalloc(dev, sizeof(struct asm9260_rtc_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
platform_set_drvdata(pdev, priv);
irq_alarm = platform_get_irq(pdev, 0);
if (irq_alarm < 0)
return irq_alarm;
priv->iobase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->iobase))
return PTR_ERR(priv->iobase);
priv->clk = devm_clk_get(dev, "ahb");
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
ret = clk_prepare_enable(priv->clk);
if (ret) {
dev_err(dev, "Failed to enable clk!\n");
return ret;
}
ccr = ioread32(priv->iobase + HW_CCR);
/* if dev is not enabled, reset it */
if ((ccr & (BM_CLKEN | BM_CTCRST)) != BM_CLKEN) {
iowrite32(BM_CTCRST, priv->iobase + HW_CCR);
ccr = 0;
}
iowrite32(BM_CLKEN | ccr, priv->iobase + HW_CCR);
iowrite32(0, priv->iobase + HW_CIIR);
iowrite32(BM_AMR_OFF, priv->iobase + HW_AMR);
priv->rtc = devm_rtc_device_register(dev, dev_name(dev),
&asm9260_rtc_ops, THIS_MODULE);
if (IS_ERR(priv->rtc)) {
ret = PTR_ERR(priv->rtc);
dev_err(dev, "Failed to register RTC device: %d\n", ret);
goto err_return;
}
ret = devm_request_threaded_irq(dev, irq_alarm, NULL,
asm9260_rtc_irq, IRQF_ONESHOT,
dev_name(dev), priv);
if (ret < 0) {
dev_err(dev, "can't get irq %i, err %d\n",
irq_alarm, ret);
goto err_return;
}
return 0;
err_return:
clk_disable_unprepare(priv->clk);
return ret;
}
static void asm9260_rtc_remove(struct platform_device *pdev)
{
struct asm9260_rtc_priv *priv = platform_get_drvdata(pdev);
/* Disable alarm matching */
iowrite32(BM_AMR_OFF, priv->iobase + HW_AMR);
clk_disable_unprepare(priv->clk);
}
static const struct of_device_id asm9260_dt_ids[] = {
{ .compatible = "alphascale,asm9260-rtc", },
{}
};
MODULE_DEVICE_TABLE(of, asm9260_dt_ids);
static struct platform_driver asm9260_rtc_driver = {
.probe = asm9260_rtc_probe,
.remove_new = asm9260_rtc_remove,
.driver = {
.name = "asm9260-rtc",
.of_match_table = asm9260_dt_ids,
},
};
module_platform_driver(asm9260_rtc_driver);
MODULE_AUTHOR("Oleksij Rempel <[email protected]>");
MODULE_DESCRIPTION("Alphascale asm9260 SoC Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-asm9260.c |
// SPDX-License-Identifier: GPL-2.0
/*
* An rtc/i2c driver for the Dallas DS1672
* Copyright 2005-06 Tower Technologies
*
* Author: Alessandro Zummo <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/rtc.h>
#include <linux/module.h>
/* Registers */
#define DS1672_REG_CNT_BASE 0
#define DS1672_REG_CONTROL 4
#define DS1672_REG_TRICKLE 5
#define DS1672_REG_CONTROL_EOSC 0x80
/*
* In the routines that deal directly with the ds1672 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
* Time is set to UTC.
*/
static int ds1672_read_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
unsigned long time;
unsigned char addr = DS1672_REG_CONTROL;
unsigned char buf[4];
struct i2c_msg msgs[] = {
{/* setup read ptr */
.addr = client->addr,
.len = 1,
.buf = &addr
},
{/* read date */
.addr = client->addr,
.flags = I2C_M_RD,
.len = 1,
.buf = buf
},
};
/* read control register */
if ((i2c_transfer(client->adapter, &msgs[0], 2)) != 2) {
dev_warn(&client->dev, "Unable to read the control register\n");
return -EIO;
}
if (buf[0] & DS1672_REG_CONTROL_EOSC) {
dev_warn(&client->dev, "Oscillator not enabled. Set time to enable.\n");
return -EINVAL;
}
addr = DS1672_REG_CNT_BASE;
msgs[1].len = 4;
/* read date registers */
if ((i2c_transfer(client->adapter, &msgs[0], 2)) != 2) {
dev_err(&client->dev, "%s: read error\n", __func__);
return -EIO;
}
dev_dbg(&client->dev,
"%s: raw read data - counters=%02x,%02x,%02x,%02x\n",
__func__, buf[0], buf[1], buf[2], buf[3]);
time = ((unsigned long)buf[3] << 24) | (buf[2] << 16) |
(buf[1] << 8) | buf[0];
rtc_time64_to_tm(time, tm);
dev_dbg(&client->dev, "%s: tm is %ptR\n", __func__, tm);
return 0;
}
static int ds1672_set_time(struct device *dev, struct rtc_time *tm)
{
struct i2c_client *client = to_i2c_client(dev);
int xfer;
unsigned char buf[6];
unsigned long secs = rtc_tm_to_time64(tm);
buf[0] = DS1672_REG_CNT_BASE;
buf[1] = secs & 0x000000FF;
buf[2] = (secs & 0x0000FF00) >> 8;
buf[3] = (secs & 0x00FF0000) >> 16;
buf[4] = (secs & 0xFF000000) >> 24;
buf[5] = 0; /* set control reg to enable counting */
xfer = i2c_master_send(client, buf, 6);
if (xfer != 6) {
dev_err(&client->dev, "%s: send: %d\n", __func__, xfer);
return -EIO;
}
return 0;
}
static const struct rtc_class_ops ds1672_rtc_ops = {
.read_time = ds1672_read_time,
.set_time = ds1672_set_time,
};
static int ds1672_probe(struct i2c_client *client)
{
int err = 0;
struct rtc_device *rtc;
dev_dbg(&client->dev, "%s\n", __func__);
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
rtc = devm_rtc_allocate_device(&client->dev);
if (IS_ERR(rtc))
return PTR_ERR(rtc);
rtc->ops = &ds1672_rtc_ops;
rtc->range_max = U32_MAX;
err = devm_rtc_register_device(rtc);
if (err)
return err;
i2c_set_clientdata(client, rtc);
return 0;
}
static const struct i2c_device_id ds1672_id[] = {
{ "ds1672", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ds1672_id);
static const __maybe_unused struct of_device_id ds1672_of_match[] = {
{ .compatible = "dallas,ds1672" },
{ }
};
MODULE_DEVICE_TABLE(of, ds1672_of_match);
static struct i2c_driver ds1672_driver = {
.driver = {
.name = "rtc-ds1672",
.of_match_table = of_match_ptr(ds1672_of_match),
},
.probe = ds1672_probe,
.id_table = ds1672_id,
};
module_i2c_driver(ds1672_driver);
MODULE_AUTHOR("Alessandro Zummo <[email protected]>");
MODULE_DESCRIPTION("Dallas/Maxim DS1672 timekeeper driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-ds1672.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An I2C and SPI driver for the NXP PCF2127/29/31 RTC
* Copyright 2013 Til-Technologies
*
* Author: Renaud Cerrato <[email protected]>
*
* Watchdog and tamper functions
* Author: Bruno Thomsen <[email protected]>
*
* PCF2131 support
* Author: Hugo Villeneuve <[email protected]>
*
* based on the other drivers in this same directory.
*
* Datasheets: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
* https://www.nxp.com/docs/en/data-sheet/PCF2131DS.pdf
*/
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
/* Control register 1 */
#define PCF2127_REG_CTRL1 0x00
#define PCF2127_BIT_CTRL1_POR_OVRD BIT(3)
#define PCF2127_BIT_CTRL1_TSF1 BIT(4)
#define PCF2127_BIT_CTRL1_STOP BIT(5)
/* Control register 2 */
#define PCF2127_REG_CTRL2 0x01
#define PCF2127_BIT_CTRL2_AIE BIT(1)
#define PCF2127_BIT_CTRL2_TSIE BIT(2)
#define PCF2127_BIT_CTRL2_AF BIT(4)
#define PCF2127_BIT_CTRL2_TSF2 BIT(5)
#define PCF2127_BIT_CTRL2_WDTF BIT(6)
/* Control register 3 */
#define PCF2127_REG_CTRL3 0x02
#define PCF2127_BIT_CTRL3_BLIE BIT(0)
#define PCF2127_BIT_CTRL3_BIE BIT(1)
#define PCF2127_BIT_CTRL3_BLF BIT(2)
#define PCF2127_BIT_CTRL3_BF BIT(3)
#define PCF2127_BIT_CTRL3_BTSE BIT(4)
/* Time and date registers */
#define PCF2127_REG_TIME_BASE 0x03
#define PCF2127_BIT_SC_OSF BIT(7)
/* Alarm registers */
#define PCF2127_REG_ALARM_BASE 0x0A
#define PCF2127_BIT_ALARM_AE BIT(7)
/* CLKOUT control register */
#define PCF2127_REG_CLKOUT 0x0f
#define PCF2127_BIT_CLKOUT_OTPR BIT(5)
/* Watchdog registers */
#define PCF2127_REG_WD_CTL 0x10
#define PCF2127_BIT_WD_CTL_TF0 BIT(0)
#define PCF2127_BIT_WD_CTL_TF1 BIT(1)
#define PCF2127_BIT_WD_CTL_CD0 BIT(6)
#define PCF2127_BIT_WD_CTL_CD1 BIT(7)
#define PCF2127_REG_WD_VAL 0x11
/* Tamper timestamp1 registers */
#define PCF2127_REG_TS1_BASE 0x12
#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
/*
* RAM registers
* PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
* battery backed and can survive a power outage.
* PCF2129/31 doesn't have this feature.
*/
#define PCF2127_REG_RAM_ADDR_MSB 0x1A
#define PCF2127_REG_RAM_WRT_CMD 0x1C
#define PCF2127_REG_RAM_RD_CMD 0x1D
/* Watchdog timer value constants */
#define PCF2127_WD_VAL_STOP 0
/* PCF2127/29 watchdog timer value constants */
#define PCF2127_WD_CLOCK_HZ_X1000 1000 /* 1Hz */
#define PCF2127_WD_MIN_HW_HEARTBEAT_MS 500
/* PCF2131 watchdog timer value constants */
#define PCF2131_WD_CLOCK_HZ_X1000 250 /* 1/4Hz */
#define PCF2131_WD_MIN_HW_HEARTBEAT_MS 4000
#define PCF2127_WD_DEFAULT_TIMEOUT_S 60
/* Mask for currently enabled interrupts */
#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
#define PCF2127_CTRL2_IRQ_MASK ( \
PCF2127_BIT_CTRL2_AF | \
PCF2127_BIT_CTRL2_WDTF | \
PCF2127_BIT_CTRL2_TSF2)
#define PCF2127_MAX_TS_SUPPORTED 4
/* Control register 4 */
#define PCF2131_REG_CTRL4 0x03
#define PCF2131_BIT_CTRL4_TSF4 BIT(4)
#define PCF2131_BIT_CTRL4_TSF3 BIT(5)
#define PCF2131_BIT_CTRL4_TSF2 BIT(6)
#define PCF2131_BIT_CTRL4_TSF1 BIT(7)
/* Control register 5 */
#define PCF2131_REG_CTRL5 0x04
#define PCF2131_BIT_CTRL5_TSIE4 BIT(4)
#define PCF2131_BIT_CTRL5_TSIE3 BIT(5)
#define PCF2131_BIT_CTRL5_TSIE2 BIT(6)
#define PCF2131_BIT_CTRL5_TSIE1 BIT(7)
/* Software reset register */
#define PCF2131_REG_SR_RESET 0x05
#define PCF2131_SR_RESET_READ_PATTERN (BIT(2) | BIT(5))
#define PCF2131_SR_RESET_CPR_CMD (PCF2131_SR_RESET_READ_PATTERN | BIT(7))
/* Time and date registers */
#define PCF2131_REG_TIME_BASE 0x07
/* Alarm registers */
#define PCF2131_REG_ALARM_BASE 0x0E
/* CLKOUT control register */
#define PCF2131_REG_CLKOUT 0x13
/* Watchdog registers */
#define PCF2131_REG_WD_CTL 0x35
#define PCF2131_REG_WD_VAL 0x36
/* Tamper timestamp1 registers */
#define PCF2131_REG_TS1_BASE 0x14
/* Tamper timestamp2 registers */
#define PCF2131_REG_TS2_BASE 0x1B
/* Tamper timestamp3 registers */
#define PCF2131_REG_TS3_BASE 0x22
/* Tamper timestamp4 registers */
#define PCF2131_REG_TS4_BASE 0x29
/* Interrupt mask registers */
#define PCF2131_REG_INT_A_MASK1 0x31
#define PCF2131_REG_INT_A_MASK2 0x32
#define PCF2131_REG_INT_B_MASK1 0x33
#define PCF2131_REG_INT_B_MASK2 0x34
#define PCF2131_BIT_INT_BLIE BIT(0)
#define PCF2131_BIT_INT_BIE BIT(1)
#define PCF2131_BIT_INT_AIE BIT(2)
#define PCF2131_BIT_INT_WD_CD BIT(3)
#define PCF2131_BIT_INT_SI BIT(4)
#define PCF2131_BIT_INT_MI BIT(5)
#define PCF2131_CTRL2_IRQ_MASK ( \
PCF2127_BIT_CTRL2_AF | \
PCF2127_BIT_CTRL2_WDTF)
#define PCF2131_CTRL4_IRQ_MASK ( \
PCF2131_BIT_CTRL4_TSF4 | \
PCF2131_BIT_CTRL4_TSF3 | \
PCF2131_BIT_CTRL4_TSF2 | \
PCF2131_BIT_CTRL4_TSF1)
enum pcf21xx_type {
PCF2127,
PCF2129,
PCF2131,
PCF21XX_LAST_ID
};
struct pcf21xx_ts_config {
u8 reg_base; /* Base register to read timestamp values. */
/*
* If the TS input pin is driven to GND, an interrupt can be generated
* (supported by all variants).
*/
u8 gnd_detect_reg; /* Interrupt control register address. */
u8 gnd_detect_bit; /* Interrupt bit. */
/*
* If the TS input pin is driven to an intermediate level between GND
* and supply, an interrupt can be generated (optional feature depending
* on variant).
*/
u8 inter_detect_reg; /* Interrupt control register address. */
u8 inter_detect_bit; /* Interrupt bit. */
u8 ie_reg; /* Interrupt enable control register. */
u8 ie_bit; /* Interrupt enable bit. */
};
struct pcf21xx_config {
int type; /* IC variant */
int max_register;
unsigned int has_nvmem:1;
unsigned int has_bit_wd_ctl_cd0:1;
unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
u8 reg_time_base; /* Time/date base register. */
u8 regs_alarm_base; /* Alarm function base registers. */
u8 reg_wd_ctl; /* Watchdog control register. */
u8 reg_wd_val; /* Watchdog value register. */
u8 reg_clkout; /* Clkout register. */
int wdd_clock_hz_x1000; /* Watchdog clock in Hz multiplicated by 1000 */
int wdd_min_hw_heartbeat_ms;
unsigned int ts_count;
struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED];
struct attribute_group attribute_group;
};
struct pcf2127 {
struct rtc_device *rtc;
struct watchdog_device wdd;
struct regmap *regmap;
const struct pcf21xx_config *cfg;
bool irq_enabled;
time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */
bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */
};
/*
* In the routines that deal directly with the pcf2127 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
*/
static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
unsigned char buf[7];
int ret;
/*
* Avoid reading CTRL2 register as it causes WD_VAL register
* value to reset to 0 which means watchdog is stopped.
*/
ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base,
buf, sizeof(buf));
if (ret) {
dev_err(dev, "%s: read error\n", __func__);
return ret;
}
/* Clock integrity is not guaranteed when OSF flag is set. */
if (buf[0] & PCF2127_BIT_SC_OSF) {
/*
* no need clear the flag here,
* it will be cleared once the new date is saved
*/
dev_warn(dev,
"oscillator stop detected, date/time is not reliable\n");
return -EINVAL;
}
dev_dbg(dev,
"%s: raw data is sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
__func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
tm->tm_sec = bcd2bin(buf[0] & 0x7F);
tm->tm_min = bcd2bin(buf[1] & 0x7F);
tm->tm_hour = bcd2bin(buf[2] & 0x3F);
tm->tm_mday = bcd2bin(buf[3] & 0x3F);
tm->tm_wday = buf[4] & 0x07;
tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1;
tm->tm_year = bcd2bin(buf[6]);
tm->tm_year += 100;
dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__func__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
return 0;
}
static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
unsigned char buf[7];
int i = 0, err;
dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__func__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
/* hours, minutes and seconds */
buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
buf[i++] = bin2bcd(tm->tm_min);
buf[i++] = bin2bcd(tm->tm_hour);
buf[i++] = bin2bcd(tm->tm_mday);
buf[i++] = tm->tm_wday & 0x07;
/* month, 1 - 12 */
buf[i++] = bin2bcd(tm->tm_mon + 1);
/* year */
buf[i++] = bin2bcd(tm->tm_year - 100);
/* Write access to time registers:
* PCF2127/29: no special action required.
* PCF2131: requires setting the STOP and CPR bits. STOP bit needs to
* be cleared after time registers are updated.
*/
if (pcf2127->cfg->type == PCF2131) {
err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
PCF2127_BIT_CTRL1_STOP,
PCF2127_BIT_CTRL1_STOP);
if (err) {
dev_dbg(dev, "setting STOP bit failed\n");
return err;
}
err = regmap_write(pcf2127->regmap, PCF2131_REG_SR_RESET,
PCF2131_SR_RESET_CPR_CMD);
if (err) {
dev_dbg(dev, "sending CPR cmd failed\n");
return err;
}
}
/* write time register's data */
err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i);
if (err) {
dev_dbg(dev, "%s: err=%d", __func__, err);
return err;
}
if (pcf2127->cfg->type == PCF2131) {
/* Clear STOP bit (PCF2131 only) after write is completed. */
err = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
PCF2127_BIT_CTRL1_STOP, 0);
if (err) {
dev_dbg(dev, "clearing STOP bit failed\n");
return err;
}
}
return 0;
}
static int pcf2127_rtc_ioctl(struct device *dev,
unsigned int cmd, unsigned long arg)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
int val, touser = 0;
int ret;
switch (cmd) {
case RTC_VL_READ:
ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
if (ret)
return ret;
if (val & PCF2127_BIT_CTRL3_BLF)
touser |= RTC_VL_BACKUP_LOW;
if (val & PCF2127_BIT_CTRL3_BF)
touser |= RTC_VL_BACKUP_SWITCH;
return put_user(touser, (unsigned int __user *)arg);
case RTC_VL_CLR:
return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
PCF2127_BIT_CTRL3_BF, 0);
default:
return -ENOIOCTLCMD;
}
}
static int pcf2127_nvmem_read(void *priv, unsigned int offset,
void *val, size_t bytes)
{
struct pcf2127 *pcf2127 = priv;
int ret;
unsigned char offsetbuf[] = { offset >> 8, offset };
ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
offsetbuf, 2);
if (ret)
return ret;
return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
val, bytes);
}
static int pcf2127_nvmem_write(void *priv, unsigned int offset,
void *val, size_t bytes)
{
struct pcf2127 *pcf2127 = priv;
int ret;
unsigned char offsetbuf[] = { offset >> 8, offset };
ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
offsetbuf, 2);
if (ret)
return ret;
return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
val, bytes);
}
/* watchdog driver */
static int pcf2127_wdt_ping(struct watchdog_device *wdd)
{
int wd_val;
struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
/*
* Compute counter value of WATCHDG_TIM_VAL to obtain desired period
* in seconds, depending on the source clock frequency.
*/
wd_val = ((wdd->timeout * pcf2127->cfg->wdd_clock_hz_x1000) / 1000) + 1;
return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wd_val);
}
/*
* Restart watchdog timer if feature is active.
*
* Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
* since register also contain control/status flags for other features.
* Always call this function after reading CTRL2 register.
*/
static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
{
int ret = 0;
if (watchdog_active(wdd)) {
ret = pcf2127_wdt_ping(wdd);
if (ret)
dev_err(wdd->parent,
"%s: watchdog restart failed, ret=%d\n",
__func__, ret);
}
return ret;
}
static int pcf2127_wdt_start(struct watchdog_device *wdd)
{
return pcf2127_wdt_ping(wdd);
}
static int pcf2127_wdt_stop(struct watchdog_device *wdd)
{
struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
PCF2127_WD_VAL_STOP);
}
static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int new_timeout)
{
dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
new_timeout, wdd->timeout);
wdd->timeout = new_timeout;
return pcf2127_wdt_active_ping(wdd);
}
static const struct watchdog_info pcf2127_wdt_info = {
.identity = "NXP PCF2127/PCF2129 Watchdog",
.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
};
static const struct watchdog_ops pcf2127_watchdog_ops = {
.owner = THIS_MODULE,
.start = pcf2127_wdt_start,
.stop = pcf2127_wdt_stop,
.ping = pcf2127_wdt_ping,
.set_timeout = pcf2127_wdt_set_timeout,
};
/*
* Compute watchdog period, t, in seconds, from the WATCHDG_TIM_VAL register
* value, n, and the clock frequency, f1000, in Hz x 1000.
*
* The PCF2127/29 datasheet gives t as:
* t = n / f
* The PCF2131 datasheet gives t as:
* t = (n - 1) / f
* For both variants, the watchdog is triggered when the WATCHDG_TIM_VAL reaches
* the value 1, and not zero. Consequently, the equation from the PCF2131
* datasheet seems to be the correct one for both variants.
*/
static int pcf2127_watchdog_get_period(int n, int f1000)
{
return (1000 * (n - 1)) / f1000;
}
static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
{
int ret;
if (!IS_ENABLED(CONFIG_WATCHDOG) ||
!device_property_read_bool(dev, "reset-source"))
return 0;
pcf2127->wdd.parent = dev;
pcf2127->wdd.info = &pcf2127_wdt_info;
pcf2127->wdd.ops = &pcf2127_watchdog_ops;
pcf2127->wdd.min_timeout =
pcf2127_watchdog_get_period(
2, pcf2127->cfg->wdd_clock_hz_x1000);
pcf2127->wdd.max_timeout =
pcf2127_watchdog_get_period(
255, pcf2127->cfg->wdd_clock_hz_x1000);
pcf2127->wdd.timeout = PCF2127_WD_DEFAULT_TIMEOUT_S;
dev_dbg(dev, "%s clock = %d Hz / 1000\n", __func__,
pcf2127->cfg->wdd_clock_hz_x1000);
pcf2127->wdd.min_hw_heartbeat_ms = pcf2127->cfg->wdd_min_hw_heartbeat_ms;
pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
/* Test if watchdog timer is started by bootloader */
if (pcf2127->cfg->wd_val_reg_readable) {
u32 wdd_timeout;
ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
&wdd_timeout);
if (ret)
return ret;
if (wdd_timeout)
set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
}
return devm_watchdog_register_device(dev, &pcf2127->wdd);
}
/* Alarm */
static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
u8 buf[5];
unsigned int ctrl2;
int ret;
ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
if (ret)
return ret;
ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
if (ret)
return ret;
ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
buf, sizeof(buf));
if (ret)
return ret;
alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
return 0;
}
static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
int ret;
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
PCF2127_BIT_CTRL2_AIE,
enable ? PCF2127_BIT_CTRL2_AIE : 0);
if (ret)
return ret;
return pcf2127_wdt_active_ping(&pcf2127->wdd);
}
static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
uint8_t buf[5];
int ret;
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
PCF2127_BIT_CTRL2_AF, 0);
if (ret)
return ret;
ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
if (ret)
return ret;
buf[0] = bin2bcd(alrm->time.tm_sec);
buf[1] = bin2bcd(alrm->time.tm_min);
buf[2] = bin2bcd(alrm->time.tm_hour);
buf[3] = bin2bcd(alrm->time.tm_mday);
buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base,
buf, sizeof(buf));
if (ret)
return ret;
return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
}
/*
* This function reads one timestamp function data, caller is responsible for
* calling pcf2127_wdt_active_ping()
*/
static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts,
int ts_id)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
struct rtc_time tm;
int ret;
unsigned char data[7];
ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base,
data, sizeof(data));
if (ret) {
dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
return ret;
}
dev_dbg(dev,
"%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
__func__, data[1], data[2], data[3], data[4], data[5], data[6]);
tm.tm_sec = bcd2bin(data[1] & 0x7F);
tm.tm_min = bcd2bin(data[2] & 0x7F);
tm.tm_hour = bcd2bin(data[3] & 0x3F);
tm.tm_mday = bcd2bin(data[4] & 0x3F);
/* TS_MO register (month) value range: 1-12 */
tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
tm.tm_year = bcd2bin(data[6]);
if (tm.tm_year < 70)
tm.tm_year += 100; /* assume we are in 1970...2069 */
ret = rtc_valid_tm(&tm);
if (ret) {
dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
return ret;
}
*ts = rtc_tm_to_time64(&tm);
return 0;
};
static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
int ret;
if (ts_id >= pcf2127->cfg->ts_count)
return;
/* Let userspace read the first timestamp */
if (pcf2127->ts_valid[ts_id])
return;
ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id);
if (!ret)
pcf2127->ts_valid[ts_id] = true;
}
static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
unsigned int ctrl2;
int ret = 0;
ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
if (ret)
return IRQ_NONE;
if (pcf2127->cfg->ts_count == 1) {
/* PCF2127/29 */
unsigned int ctrl1;
ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
if (ret)
return IRQ_NONE;
if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
return IRQ_NONE;
if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
pcf2127_rtc_ts_snapshot(dev, 0);
if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
} else {
/* PCF2131. */
unsigned int ctrl4;
ret = regmap_read(pcf2127->regmap, PCF2131_REG_CTRL4, &ctrl4);
if (ret)
return IRQ_NONE;
if (!(ctrl4 & PCF2131_CTRL4_IRQ_MASK || ctrl2 & PCF2131_CTRL2_IRQ_MASK))
return IRQ_NONE;
if (ctrl4 & PCF2131_CTRL4_IRQ_MASK) {
int i;
int tsf_bit = PCF2131_BIT_CTRL4_TSF1; /* Start at bit 7. */
for (i = 0; i < pcf2127->cfg->ts_count; i++) {
if (ctrl4 & tsf_bit)
pcf2127_rtc_ts_snapshot(dev, i);
tsf_bit = tsf_bit >> 1;
}
regmap_write(pcf2127->regmap, PCF2131_REG_CTRL4,
ctrl4 & ~PCF2131_CTRL4_IRQ_MASK);
}
if (ctrl2 & PCF2131_CTRL2_IRQ_MASK)
regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
ctrl2 & ~PCF2131_CTRL2_IRQ_MASK);
}
if (ctrl2 & PCF2127_BIT_CTRL2_AF)
rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
pcf2127_wdt_active_ping(&pcf2127->wdd);
return IRQ_HANDLED;
}
static const struct rtc_class_ops pcf2127_rtc_ops = {
.ioctl = pcf2127_rtc_ioctl,
.read_time = pcf2127_rtc_read_time,
.set_time = pcf2127_rtc_set_time,
.read_alarm = pcf2127_rtc_read_alarm,
.set_alarm = pcf2127_rtc_set_alarm,
.alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
};
/* sysfs interface */
static ssize_t timestamp_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count, int ts_id)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
int ret;
if (ts_id >= pcf2127->cfg->ts_count)
return 0;
if (pcf2127->irq_enabled) {
pcf2127->ts_valid[ts_id] = false;
} else {
/* Always clear GND interrupt bit. */
ret = regmap_update_bits(pcf2127->regmap,
pcf2127->cfg->ts[ts_id].gnd_detect_reg,
pcf2127->cfg->ts[ts_id].gnd_detect_bit,
0);
if (ret) {
dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret);
return ret;
}
if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
/* Clear intermediate level interrupt bit if supported. */
ret = regmap_update_bits(pcf2127->regmap,
pcf2127->cfg->ts[ts_id].inter_detect_reg,
pcf2127->cfg->ts[ts_id].inter_detect_bit,
0);
if (ret) {
dev_err(dev, "%s: update TS intermediate level detect ret=%d\n",
__func__, ret);
return ret;
}
}
ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
if (ret)
return ret;
}
return count;
}
static ssize_t timestamp0_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
return timestamp_store(dev, attr, buf, count, 0);
};
static ssize_t timestamp1_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
return timestamp_store(dev, attr, buf, count, 1);
};
static ssize_t timestamp2_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
return timestamp_store(dev, attr, buf, count, 2);
};
static ssize_t timestamp3_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
return timestamp_store(dev, attr, buf, count, 3);
};
static ssize_t timestamp_show(struct device *dev,
struct device_attribute *attr, char *buf,
int ts_id)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
int ret;
time64_t ts;
if (ts_id >= pcf2127->cfg->ts_count)
return 0;
if (pcf2127->irq_enabled) {
if (!pcf2127->ts_valid[ts_id])
return 0;
ts = pcf2127->ts[ts_id];
} else {
u8 valid_low = 0;
u8 valid_inter = 0;
unsigned int ctrl;
/* Check if TS input pin is driven to GND, supported by all
* variants.
*/
ret = regmap_read(pcf2127->regmap,
pcf2127->cfg->ts[ts_id].gnd_detect_reg,
&ctrl);
if (ret)
return 0;
valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit;
if (pcf2127->cfg->ts[ts_id].inter_detect_bit) {
/* Check if TS input pin is driven to intermediate level
* between GND and supply, if supported by variant.
*/
ret = regmap_read(pcf2127->regmap,
pcf2127->cfg->ts[ts_id].inter_detect_reg,
&ctrl);
if (ret)
return 0;
valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit;
}
if (!valid_low && !valid_inter)
return 0;
ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id);
if (ret)
return 0;
ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
if (ret)
return ret;
}
return sprintf(buf, "%llu\n", (unsigned long long)ts);
}
static ssize_t timestamp0_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return timestamp_show(dev, attr, buf, 0);
};
static ssize_t timestamp1_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return timestamp_show(dev, attr, buf, 1);
};
static ssize_t timestamp2_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return timestamp_show(dev, attr, buf, 2);
};
static ssize_t timestamp3_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
return timestamp_show(dev, attr, buf, 3);
};
static DEVICE_ATTR_RW(timestamp0);
static DEVICE_ATTR_RW(timestamp1);
static DEVICE_ATTR_RW(timestamp2);
static DEVICE_ATTR_RW(timestamp3);
static struct attribute *pcf2127_attrs[] = {
&dev_attr_timestamp0.attr,
NULL
};
static struct attribute *pcf2131_attrs[] = {
&dev_attr_timestamp0.attr,
&dev_attr_timestamp1.attr,
&dev_attr_timestamp2.attr,
&dev_attr_timestamp3.attr,
NULL
};
static struct pcf21xx_config pcf21xx_cfg[] = {
[PCF2127] = {
.type = PCF2127,
.max_register = 0x1d,
.has_nvmem = 1,
.has_bit_wd_ctl_cd0 = 1,
.wd_val_reg_readable = 1,
.has_int_a_b = 0,
.reg_time_base = PCF2127_REG_TIME_BASE,
.regs_alarm_base = PCF2127_REG_ALARM_BASE,
.reg_wd_ctl = PCF2127_REG_WD_CTL,
.reg_wd_val = PCF2127_REG_WD_VAL,
.reg_clkout = PCF2127_REG_CLKOUT,
.wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
.wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
.ts_count = 1,
.ts[0] = {
.reg_base = PCF2127_REG_TS1_BASE,
.gnd_detect_reg = PCF2127_REG_CTRL1,
.gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
.inter_detect_reg = PCF2127_REG_CTRL2,
.inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
.ie_reg = PCF2127_REG_CTRL2,
.ie_bit = PCF2127_BIT_CTRL2_TSIE,
},
.attribute_group = {
.attrs = pcf2127_attrs,
},
},
[PCF2129] = {
.type = PCF2129,
.max_register = 0x19,
.has_nvmem = 0,
.has_bit_wd_ctl_cd0 = 0,
.wd_val_reg_readable = 1,
.has_int_a_b = 0,
.reg_time_base = PCF2127_REG_TIME_BASE,
.regs_alarm_base = PCF2127_REG_ALARM_BASE,
.reg_wd_ctl = PCF2127_REG_WD_CTL,
.reg_wd_val = PCF2127_REG_WD_VAL,
.reg_clkout = PCF2127_REG_CLKOUT,
.wdd_clock_hz_x1000 = PCF2127_WD_CLOCK_HZ_X1000,
.wdd_min_hw_heartbeat_ms = PCF2127_WD_MIN_HW_HEARTBEAT_MS,
.ts_count = 1,
.ts[0] = {
.reg_base = PCF2127_REG_TS1_BASE,
.gnd_detect_reg = PCF2127_REG_CTRL1,
.gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1,
.inter_detect_reg = PCF2127_REG_CTRL2,
.inter_detect_bit = PCF2127_BIT_CTRL2_TSF2,
.ie_reg = PCF2127_REG_CTRL2,
.ie_bit = PCF2127_BIT_CTRL2_TSIE,
},
.attribute_group = {
.attrs = pcf2127_attrs,
},
},
[PCF2131] = {
.type = PCF2131,
.max_register = 0x36,
.has_nvmem = 0,
.has_bit_wd_ctl_cd0 = 0,
.wd_val_reg_readable = 0,
.has_int_a_b = 1,
.reg_time_base = PCF2131_REG_TIME_BASE,
.regs_alarm_base = PCF2131_REG_ALARM_BASE,
.reg_wd_ctl = PCF2131_REG_WD_CTL,
.reg_wd_val = PCF2131_REG_WD_VAL,
.reg_clkout = PCF2131_REG_CLKOUT,
.wdd_clock_hz_x1000 = PCF2131_WD_CLOCK_HZ_X1000,
.wdd_min_hw_heartbeat_ms = PCF2131_WD_MIN_HW_HEARTBEAT_MS,
.ts_count = 4,
.ts[0] = {
.reg_base = PCF2131_REG_TS1_BASE,
.gnd_detect_reg = PCF2131_REG_CTRL4,
.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF1,
.inter_detect_bit = 0,
.ie_reg = PCF2131_REG_CTRL5,
.ie_bit = PCF2131_BIT_CTRL5_TSIE1,
},
.ts[1] = {
.reg_base = PCF2131_REG_TS2_BASE,
.gnd_detect_reg = PCF2131_REG_CTRL4,
.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF2,
.inter_detect_bit = 0,
.ie_reg = PCF2131_REG_CTRL5,
.ie_bit = PCF2131_BIT_CTRL5_TSIE2,
},
.ts[2] = {
.reg_base = PCF2131_REG_TS3_BASE,
.gnd_detect_reg = PCF2131_REG_CTRL4,
.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF3,
.inter_detect_bit = 0,
.ie_reg = PCF2131_REG_CTRL5,
.ie_bit = PCF2131_BIT_CTRL5_TSIE3,
},
.ts[3] = {
.reg_base = PCF2131_REG_TS4_BASE,
.gnd_detect_reg = PCF2131_REG_CTRL4,
.gnd_detect_bit = PCF2131_BIT_CTRL4_TSF4,
.inter_detect_bit = 0,
.ie_reg = PCF2131_REG_CTRL5,
.ie_bit = PCF2131_BIT_CTRL5_TSIE4,
},
.attribute_group = {
.attrs = pcf2131_attrs,
},
},
};
/*
* Enable timestamp function and corresponding interrupt(s).
*/
static int pcf2127_enable_ts(struct device *dev, int ts_id)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
int ret;
if (ts_id >= pcf2127->cfg->ts_count) {
dev_err(dev, "%s: invalid tamper detection ID (%d)\n",
__func__, ts_id);
return -EINVAL;
}
/* Enable timestamp function. */
ret = regmap_update_bits(pcf2127->regmap,
pcf2127->cfg->ts[ts_id].reg_base,
PCF2127_BIT_TS_CTRL_TSOFF |
PCF2127_BIT_TS_CTRL_TSM,
PCF2127_BIT_TS_CTRL_TSM);
if (ret) {
dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n",
__func__, ts_id);
return ret;
}
/*
* Enable interrupt generation when TSF timestamp flag is set.
* Interrupt signals are open-drain outputs and can be left floating if
* unused.
*/
ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg,
pcf2127->cfg->ts[ts_id].ie_bit,
pcf2127->cfg->ts[ts_id].ie_bit);
if (ret) {
dev_err(dev, "%s: tamper detection TSIE%d config failed\n",
__func__, ts_id);
return ret;
}
return ret;
}
/* Route all interrupt sources to INT A pin. */
static int pcf2127_configure_interrupt_pins(struct device *dev)
{
struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
int ret;
/* Mask bits need to be cleared to enable corresponding
* interrupt source.
*/
ret = regmap_write(pcf2127->regmap,
PCF2131_REG_INT_A_MASK1, 0);
if (ret)
return ret;
ret = regmap_write(pcf2127->regmap,
PCF2131_REG_INT_A_MASK2, 0);
if (ret)
return ret;
return ret;
}
static int pcf2127_probe(struct device *dev, struct regmap *regmap,
int alarm_irq, const struct pcf21xx_config *config)
{
struct pcf2127 *pcf2127;
int ret = 0;
unsigned int val;
dev_dbg(dev, "%s\n", __func__);
pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
if (!pcf2127)
return -ENOMEM;
pcf2127->regmap = regmap;
pcf2127->cfg = config;
dev_set_drvdata(dev, pcf2127);
pcf2127->rtc = devm_rtc_allocate_device(dev);
if (IS_ERR(pcf2127->rtc))
return PTR_ERR(pcf2127->rtc);
pcf2127->rtc->ops = &pcf2127_rtc_ops;
pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
/*
* PCF2127/29 do not work correctly when setting alarms at 1s intervals.
* PCF2131 is ok.
*/
if (pcf2127->cfg->type == PCF2127 || pcf2127->cfg->type == PCF2129) {
set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features);
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features);
}
clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
if (alarm_irq > 0) {
unsigned long flags;
/*
* If flags = 0, devm_request_threaded_irq() will use IRQ flags
* obtained from device tree.
*/
if (dev_fwnode(dev))
flags = 0;
else
flags = IRQF_TRIGGER_LOW;
ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
pcf2127_rtc_irq,
flags | IRQF_ONESHOT,
dev_name(dev), dev);
if (ret) {
dev_err(dev, "failed to request alarm irq\n");
return ret;
}
pcf2127->irq_enabled = true;
}
if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
device_init_wakeup(dev, true);
set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
}
if (pcf2127->cfg->has_int_a_b) {
/* Configure int A/B pins, independently of alarm_irq. */
ret = pcf2127_configure_interrupt_pins(dev);
if (ret) {
dev_err(dev, "failed to configure interrupt pins\n");
return ret;
}
}
if (pcf2127->cfg->has_nvmem) {
struct nvmem_config nvmem_cfg = {
.priv = pcf2127,
.reg_read = pcf2127_nvmem_read,
.reg_write = pcf2127_nvmem_write,
.size = 512,
};
ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
}
/*
* The "Power-On Reset Override" facility prevents the RTC to do a reset
* after power on. For normal operation the PORO must be disabled.
*/
ret = regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
PCF2127_BIT_CTRL1_POR_OVRD);
if (ret < 0)
return ret;
ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val);
if (ret < 0)
return ret;
if (!(val & PCF2127_BIT_CLKOUT_OTPR)) {
ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout,
PCF2127_BIT_CLKOUT_OTPR);
if (ret < 0)
return ret;
msleep(100);
}
/*
* Watchdog timer enabled and reset pin /RST activated when timed out.
* Select 1Hz clock source for watchdog timer (1/4Hz for PCF2131).
* Note: Countdown timer disabled and not available.
* For pca2129, pcf2129 and pcf2131, only bit[7] is for Symbol WD_CD
* of register watchdg_tim_ctl. The bit[6] is labeled
* as T. Bits labeled as T must always be written with
* logic 0.
*/
ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl,
PCF2127_BIT_WD_CTL_CD1 |
PCF2127_BIT_WD_CTL_CD0 |
PCF2127_BIT_WD_CTL_TF1 |
PCF2127_BIT_WD_CTL_TF0,
PCF2127_BIT_WD_CTL_CD1 |
(pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
PCF2127_BIT_WD_CTL_TF1);
if (ret) {
dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
return ret;
}
pcf2127_watchdog_init(dev, pcf2127);
/*
* Disable battery low/switch-over timestamp and interrupts.
* Clear battery interrupt flags which can block new trigger events.
* Note: This is the default chip behaviour but added to ensure
* correct tamper timestamp and interrupt function.
*/
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
PCF2127_BIT_CTRL3_BTSE |
PCF2127_BIT_CTRL3_BIE |
PCF2127_BIT_CTRL3_BLIE, 0);
if (ret) {
dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
__func__);
return ret;
}
/*
* Enable timestamp functions 1 to 4.
*/
for (int i = 0; i < pcf2127->cfg->ts_count; i++) {
ret = pcf2127_enable_ts(dev, i);
if (ret)
return ret;
}
ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group);
if (ret) {
dev_err(dev, "%s: tamper sysfs registering failed\n",
__func__);
return ret;
}
return devm_rtc_register_device(pcf2127->rtc);
}
#ifdef CONFIG_OF
static const struct of_device_id pcf2127_of_match[] = {
{ .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] },
{ .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] },
{ .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] },
{ .compatible = "nxp,pcf2131", .data = &pcf21xx_cfg[PCF2131] },
{}
};
MODULE_DEVICE_TABLE(of, pcf2127_of_match);
#endif
#if IS_ENABLED(CONFIG_I2C)
static int pcf2127_i2c_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct i2c_client *client = to_i2c_client(dev);
int ret;
ret = i2c_master_send(client, data, count);
if (ret != count)
return ret < 0 ? ret : -EIO;
return 0;
}
static int pcf2127_i2c_gather_write(void *context,
const void *reg, size_t reg_size,
const void *val, size_t val_size)
{
struct device *dev = context;
struct i2c_client *client = to_i2c_client(dev);
int ret;
void *buf;
if (WARN_ON(reg_size != 1))
return -EINVAL;
buf = kmalloc(val_size + 1, GFP_KERNEL);
if (!buf)
return -ENOMEM;
memcpy(buf, reg, 1);
memcpy(buf + 1, val, val_size);
ret = i2c_master_send(client, buf, val_size + 1);
kfree(buf);
if (ret != val_size + 1)
return ret < 0 ? ret : -EIO;
return 0;
}
static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct device *dev = context;
struct i2c_client *client = to_i2c_client(dev);
int ret;
if (WARN_ON(reg_size != 1))
return -EINVAL;
ret = i2c_master_send(client, reg, 1);
if (ret != 1)
return ret < 0 ? ret : -EIO;
ret = i2c_master_recv(client, val, val_size);
if (ret != val_size)
return ret < 0 ? ret : -EIO;
return 0;
}
/*
* The reason we need this custom regmap_bus instead of using regmap_init_i2c()
* is that the STOP condition is required between set register address and
* read register data when reading from registers.
*/
static const struct regmap_bus pcf2127_i2c_regmap = {
.write = pcf2127_i2c_write,
.gather_write = pcf2127_i2c_gather_write,
.read = pcf2127_i2c_read,
};
static struct i2c_driver pcf2127_i2c_driver;
static const struct i2c_device_id pcf2127_i2c_id[] = {
{ "pcf2127", PCF2127 },
{ "pcf2129", PCF2129 },
{ "pca2129", PCF2129 },
{ "pcf2131", PCF2131 },
{ }
};
MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
static int pcf2127_i2c_probe(struct i2c_client *client)
{
struct regmap *regmap;
static struct regmap_config config = {
.reg_bits = 8,
.val_bits = 8,
};
const struct pcf21xx_config *variant;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
return -ENODEV;
if (client->dev.of_node) {
variant = of_device_get_match_data(&client->dev);
if (!variant)
return -ENODEV;
} else {
enum pcf21xx_type type =
i2c_match_id(pcf2127_i2c_id, client)->driver_data;
if (type >= PCF21XX_LAST_ID)
return -ENODEV;
variant = &pcf21xx_cfg[type];
}
config.max_register = variant->max_register,
regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
&client->dev, &config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
__func__, PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return pcf2127_probe(&client->dev, regmap, client->irq, variant);
}
static struct i2c_driver pcf2127_i2c_driver = {
.driver = {
.name = "rtc-pcf2127-i2c",
.of_match_table = of_match_ptr(pcf2127_of_match),
},
.probe = pcf2127_i2c_probe,
.id_table = pcf2127_i2c_id,
};
static int pcf2127_i2c_register_driver(void)
{
return i2c_add_driver(&pcf2127_i2c_driver);
}
static void pcf2127_i2c_unregister_driver(void)
{
i2c_del_driver(&pcf2127_i2c_driver);
}
#else
static int pcf2127_i2c_register_driver(void)
{
return 0;
}
static void pcf2127_i2c_unregister_driver(void)
{
}
#endif
#if IS_ENABLED(CONFIG_SPI_MASTER)
static struct spi_driver pcf2127_spi_driver;
static const struct spi_device_id pcf2127_spi_id[];
static int pcf2127_spi_probe(struct spi_device *spi)
{
static struct regmap_config config = {
.reg_bits = 8,
.val_bits = 8,
.read_flag_mask = 0xa0,
.write_flag_mask = 0x20,
};
struct regmap *regmap;
const struct pcf21xx_config *variant;
if (spi->dev.of_node) {
variant = of_device_get_match_data(&spi->dev);
if (!variant)
return -ENODEV;
} else {
enum pcf21xx_type type = spi_get_device_id(spi)->driver_data;
if (type >= PCF21XX_LAST_ID)
return -ENODEV;
variant = &pcf21xx_cfg[type];
}
config.max_register = variant->max_register,
regmap = devm_regmap_init_spi(spi, &config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
__func__, PTR_ERR(regmap));
return PTR_ERR(regmap);
}
return pcf2127_probe(&spi->dev, regmap, spi->irq, variant);
}
static const struct spi_device_id pcf2127_spi_id[] = {
{ "pcf2127", PCF2127 },
{ "pcf2129", PCF2129 },
{ "pca2129", PCF2129 },
{ "pcf2131", PCF2131 },
{ }
};
MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
static struct spi_driver pcf2127_spi_driver = {
.driver = {
.name = "rtc-pcf2127-spi",
.of_match_table = of_match_ptr(pcf2127_of_match),
},
.probe = pcf2127_spi_probe,
.id_table = pcf2127_spi_id,
};
static int pcf2127_spi_register_driver(void)
{
return spi_register_driver(&pcf2127_spi_driver);
}
static void pcf2127_spi_unregister_driver(void)
{
spi_unregister_driver(&pcf2127_spi_driver);
}
#else
static int pcf2127_spi_register_driver(void)
{
return 0;
}
static void pcf2127_spi_unregister_driver(void)
{
}
#endif
static int __init pcf2127_init(void)
{
int ret;
ret = pcf2127_i2c_register_driver();
if (ret) {
pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
return ret;
}
ret = pcf2127_spi_register_driver();
if (ret) {
pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
pcf2127_i2c_unregister_driver();
}
return ret;
}
module_init(pcf2127_init)
static void __exit pcf2127_exit(void)
{
pcf2127_spi_unregister_driver();
pcf2127_i2c_unregister_driver();
}
module_exit(pcf2127_exit)
MODULE_AUTHOR("Renaud Cerrato <[email protected]>");
MODULE_DESCRIPTION("NXP PCF2127/29/31 RTC driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/rtc/rtc-pcf2127.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* An rtc driver for the Dallas DS1553
*
* Copyright (C) 2006 Atsushi Nemoto <[email protected]>
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>
#include <linux/rtc.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/module.h>
#define RTC_REG_SIZE 0x2000
#define RTC_OFFSET 0x1ff0
#define RTC_FLAGS (RTC_OFFSET + 0)
#define RTC_SECONDS_ALARM (RTC_OFFSET + 2)
#define RTC_MINUTES_ALARM (RTC_OFFSET + 3)
#define RTC_HOURS_ALARM (RTC_OFFSET + 4)
#define RTC_DATE_ALARM (RTC_OFFSET + 5)
#define RTC_INTERRUPTS (RTC_OFFSET + 6)
#define RTC_WATCHDOG (RTC_OFFSET + 7)
#define RTC_CONTROL (RTC_OFFSET + 8)
#define RTC_CENTURY (RTC_OFFSET + 8)
#define RTC_SECONDS (RTC_OFFSET + 9)
#define RTC_MINUTES (RTC_OFFSET + 10)
#define RTC_HOURS (RTC_OFFSET + 11)
#define RTC_DAY (RTC_OFFSET + 12)
#define RTC_DATE (RTC_OFFSET + 13)
#define RTC_MONTH (RTC_OFFSET + 14)
#define RTC_YEAR (RTC_OFFSET + 15)
#define RTC_CENTURY_MASK 0x3f
#define RTC_SECONDS_MASK 0x7f
#define RTC_DAY_MASK 0x07
/* Bits in the Control/Century register */
#define RTC_WRITE 0x80
#define RTC_READ 0x40
/* Bits in the Seconds register */
#define RTC_STOP 0x80
/* Bits in the Flags register */
#define RTC_FLAGS_AF 0x40
#define RTC_FLAGS_BLF 0x10
/* Bits in the Interrupts register */
#define RTC_INTS_AE 0x80
struct rtc_plat_data {
struct rtc_device *rtc;
void __iomem *ioaddr;
unsigned long last_jiffies;
int irq;
unsigned int irqen;
int alrm_sec;
int alrm_min;
int alrm_hour;
int alrm_mday;
spinlock_t lock;
};
static int ds1553_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
u8 century;
century = bin2bcd((tm->tm_year + 1900) / 100);
writeb(RTC_WRITE, pdata->ioaddr + RTC_CONTROL);
writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR);
writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH);
writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY);
writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE);
writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS);
writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES);
writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS);
/* RTC_CENTURY and RTC_CONTROL share same register */
writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr + RTC_CENTURY);
writeb(century & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
return 0;
}
static int ds1553_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
unsigned int year, month, day, hour, minute, second, week;
unsigned int century;
/* give enough time to update RTC in case of continuous read */
if (pdata->last_jiffies == jiffies)
msleep(1);
pdata->last_jiffies = jiffies;
writeb(RTC_READ, ioaddr + RTC_CONTROL);
second = readb(ioaddr + RTC_SECONDS) & RTC_SECONDS_MASK;
minute = readb(ioaddr + RTC_MINUTES);
hour = readb(ioaddr + RTC_HOURS);
day = readb(ioaddr + RTC_DATE);
week = readb(ioaddr + RTC_DAY) & RTC_DAY_MASK;
month = readb(ioaddr + RTC_MONTH);
year = readb(ioaddr + RTC_YEAR);
century = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
writeb(0, ioaddr + RTC_CONTROL);
tm->tm_sec = bcd2bin(second);
tm->tm_min = bcd2bin(minute);
tm->tm_hour = bcd2bin(hour);
tm->tm_mday = bcd2bin(day);
tm->tm_wday = bcd2bin(week);
tm->tm_mon = bcd2bin(month) - 1;
/* year is 1900 + tm->tm_year */
tm->tm_year = bcd2bin(year) + bcd2bin(century) * 100 - 1900;
return 0;
}
static void ds1553_rtc_update_alarm(struct rtc_plat_data *pdata)
{
void __iomem *ioaddr = pdata->ioaddr;
unsigned long flags;
spin_lock_irqsave(&pdata->lock, flags);
writeb(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_mday),
ioaddr + RTC_DATE_ALARM);
writeb(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_hour),
ioaddr + RTC_HOURS_ALARM);
writeb(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_min),
ioaddr + RTC_MINUTES_ALARM);
writeb(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
0x80 : bin2bcd(pdata->alrm_sec),
ioaddr + RTC_SECONDS_ALARM);
writeb(pdata->irqen ? RTC_INTS_AE : 0, ioaddr + RTC_INTERRUPTS);
readb(ioaddr + RTC_FLAGS); /* clear interrupts */
spin_unlock_irqrestore(&pdata->lock, flags);
}
static int ds1553_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
pdata->alrm_mday = alrm->time.tm_mday;
pdata->alrm_hour = alrm->time.tm_hour;
pdata->alrm_min = alrm->time.tm_min;
pdata->alrm_sec = alrm->time.tm_sec;
if (alrm->enabled)
pdata->irqen |= RTC_AF;
ds1553_rtc_update_alarm(pdata);
return 0;
}
static int ds1553_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
return 0;
}
static irqreturn_t ds1553_rtc_interrupt(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
void __iomem *ioaddr = pdata->ioaddr;
unsigned long events = 0;
spin_lock(&pdata->lock);
/* read and clear interrupt */
if (readb(ioaddr + RTC_FLAGS) & RTC_FLAGS_AF) {
events = RTC_IRQF;
if (readb(ioaddr + RTC_SECONDS_ALARM) & 0x80)
events |= RTC_UF;
else
events |= RTC_AF;
rtc_update_irq(pdata->rtc, 1, events);
}
spin_unlock(&pdata->lock);
return events ? IRQ_HANDLED : IRQ_NONE;
}
static int ds1553_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
if (pdata->irq <= 0)
return -EINVAL;
if (enabled)
pdata->irqen |= RTC_AF;
else
pdata->irqen &= ~RTC_AF;
ds1553_rtc_update_alarm(pdata);
return 0;
}
static const struct rtc_class_ops ds1553_rtc_ops = {
.read_time = ds1553_rtc_read_time,
.set_time = ds1553_rtc_set_time,
.read_alarm = ds1553_rtc_read_alarm,
.set_alarm = ds1553_rtc_set_alarm,
.alarm_irq_enable = ds1553_rtc_alarm_irq_enable,
};
static int ds1553_nvram_read(void *priv, unsigned int pos, void *val,
size_t bytes)
{
struct platform_device *pdev = priv;
struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
void __iomem *ioaddr = pdata->ioaddr;
u8 *buf = val;
for (; bytes; bytes--)
*buf++ = readb(ioaddr + pos++);
return 0;
}
static int ds1553_nvram_write(void *priv, unsigned int pos, void *val,
size_t bytes)
{
struct platform_device *pdev = priv;
struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
void __iomem *ioaddr = pdata->ioaddr;
u8 *buf = val;
for (; bytes; bytes--)
writeb(*buf++, ioaddr + pos++);
return 0;
}
static int ds1553_rtc_probe(struct platform_device *pdev)
{
unsigned int cen, sec;
struct rtc_plat_data *pdata;
void __iomem *ioaddr;
int ret = 0;
struct nvmem_config nvmem_cfg = {
.name = "ds1553_nvram",
.word_size = 1,
.stride = 1,
.size = RTC_OFFSET,
.reg_read = ds1553_nvram_read,
.reg_write = ds1553_nvram_write,
.priv = pdev,
};
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
ioaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ioaddr))
return PTR_ERR(ioaddr);
pdata->ioaddr = ioaddr;
pdata->irq = platform_get_irq(pdev, 0);
/* turn RTC on if it was not on */
sec = readb(ioaddr + RTC_SECONDS);
if (sec & RTC_STOP) {
sec &= RTC_SECONDS_MASK;
cen = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
writeb(sec, ioaddr + RTC_SECONDS);
writeb(cen & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
}
if (readb(ioaddr + RTC_FLAGS) & RTC_FLAGS_BLF)
dev_warn(&pdev->dev, "voltage-low detected.\n");
spin_lock_init(&pdata->lock);
pdata->last_jiffies = jiffies;
platform_set_drvdata(pdev, pdata);
pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(pdata->rtc))
return PTR_ERR(pdata->rtc);
pdata->rtc->ops = &ds1553_rtc_ops;
ret = devm_rtc_register_device(pdata->rtc);
if (ret)
return ret;
if (pdata->irq > 0) {
writeb(0, ioaddr + RTC_INTERRUPTS);
if (devm_request_irq(&pdev->dev, pdata->irq,
ds1553_rtc_interrupt,
0, pdev->name, pdev) < 0) {
dev_warn(&pdev->dev, "interrupt not available.\n");
pdata->irq = 0;
}
}
devm_rtc_nvmem_register(pdata->rtc, &nvmem_cfg);
return 0;
}
/* work with hotplug and coldplug */
MODULE_ALIAS("platform:rtc-ds1553");
static struct platform_driver ds1553_rtc_driver = {
.probe = ds1553_rtc_probe,
.driver = {
.name = "rtc-ds1553",
},
};
module_platform_driver(ds1553_rtc_driver);
MODULE_AUTHOR("Atsushi Nemoto <[email protected]>");
MODULE_DESCRIPTION("Dallas DS1553 RTC driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/rtc/rtc-ds1553.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Real Time Clock interface for XScale PXA27x and PXA3xx
*
* Copyright (C) 2008 Robert Jarzmik
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of.h>
#include "rtc-sa1100.h"
#define RTC_DEF_DIVIDER (32768 - 1)
#define RTC_DEF_TRIM 0
#define MAXFREQ_PERIODIC 1000
/*
* PXA Registers and bits definitions
*/
#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
#define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */
#define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
#define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
#define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
#define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
#define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
#define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */
#define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */
#define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */
#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define RTSR_AL (1 << 0) /* RTC alarm detected */
#define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
| RTSR_SWAL1 | RTSR_SWAL2)
#define RYxR_YEAR_S 9
#define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S)
#define RYxR_MONTH_S 5
#define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
#define RYxR_DAY_MASK 0x1f
#define RDxR_WOM_S 20
#define RDxR_WOM_MASK (0x7 << RDxR_WOM_S)
#define RDxR_DOW_S 17
#define RDxR_DOW_MASK (0x7 << RDxR_DOW_S)
#define RDxR_HOUR_S 12
#define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S)
#define RDxR_MIN_S 6
#define RDxR_MIN_MASK (0x3f << RDxR_MIN_S)
#define RDxR_SEC_MASK 0x3f
#define RTSR 0x08
#define RTTR 0x0c
#define RDCR 0x10
#define RYCR 0x14
#define RDAR1 0x18
#define RYAR1 0x1c
#define RTCPICR 0x34
#define PIAR 0x38
#define rtc_readl(pxa_rtc, reg) \
__raw_readl((pxa_rtc)->base + (reg))
#define rtc_writel(pxa_rtc, reg, value) \
__raw_writel((value), (pxa_rtc)->base + (reg))
struct pxa_rtc {
struct sa1100_rtc sa1100_rtc;
struct resource *ress;
void __iomem *base;
struct rtc_device *rtc;
spinlock_t lock; /* Protects this structure */
};
static u32 ryxr_calc(struct rtc_time *tm)
{
return ((tm->tm_year + 1900) << RYxR_YEAR_S)
| ((tm->tm_mon + 1) << RYxR_MONTH_S)
| tm->tm_mday;
}
static u32 rdxr_calc(struct rtc_time *tm)
{
return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
| (tm->tm_hour << RDxR_HOUR_S)
| (tm->tm_min << RDxR_MIN_S)
| tm->tm_sec;
}
static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
{
tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
tm->tm_mday = (rycr & RYxR_DAY_MASK);
tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
tm->tm_sec = rdcr & RDxR_SEC_MASK;
}
static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
u32 rtsr;
rtsr = rtc_readl(pxa_rtc, RTSR);
rtsr &= ~RTSR_TRIG_MASK;
rtsr &= ~mask;
rtc_writel(pxa_rtc, RTSR, rtsr);
}
static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
{
u32 rtsr;
rtsr = rtc_readl(pxa_rtc, RTSR);
rtsr &= ~RTSR_TRIG_MASK;
rtsr |= mask;
rtc_writel(pxa_rtc, RTSR, rtsr);
}
static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
u32 rtsr;
unsigned long events = 0;
spin_lock(&pxa_rtc->lock);
/* clear interrupt sources */
rtsr = rtc_readl(pxa_rtc, RTSR);
rtc_writel(pxa_rtc, RTSR, rtsr);
/* temporary disable rtc interrupts */
rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
/* clear alarm interrupt if it has occurred */
if (rtsr & RTSR_RDAL1)
rtsr &= ~RTSR_RDALE1;
/* update irq data & counter */
if (rtsr & RTSR_RDAL1)
events |= RTC_AF | RTC_IRQF;
if (rtsr & RTSR_HZ)
events |= RTC_UF | RTC_IRQF;
if (rtsr & RTSR_PIAL)
events |= RTC_PF | RTC_IRQF;
rtc_update_irq(pxa_rtc->rtc, 1, events);
/* enable back rtc interrupts */
rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
spin_unlock(&pxa_rtc->lock);
return IRQ_HANDLED;
}
static int pxa_rtc_open(struct device *dev)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
int ret;
ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
"rtc 1Hz", dev);
if (ret < 0) {
dev_err(dev, "can't get irq %i, err %d\n",
pxa_rtc->sa1100_rtc.irq_1hz, ret);
goto err_irq_1Hz;
}
ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
"rtc Alrm", dev);
if (ret < 0) {
dev_err(dev, "can't get irq %i, err %d\n",
pxa_rtc->sa1100_rtc.irq_alarm, ret);
goto err_irq_Alrm;
}
return 0;
err_irq_Alrm:
free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
err_irq_1Hz:
return ret;
}
static void pxa_rtc_release(struct device *dev)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
spin_lock_irq(&pxa_rtc->lock);
rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
spin_unlock_irq(&pxa_rtc->lock);
free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
}
static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
spin_lock_irq(&pxa_rtc->lock);
if (enabled)
rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
else
rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
spin_unlock_irq(&pxa_rtc->lock);
return 0;
}
static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
u32 rycr, rdcr;
rycr = rtc_readl(pxa_rtc, RYCR);
rdcr = rtc_readl(pxa_rtc, RDCR);
tm_calc(rycr, rdcr, tm);
return 0;
}
static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
return 0;
}
static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
u32 rtsr, ryar, rdar;
ryar = rtc_readl(pxa_rtc, RYAR1);
rdar = rtc_readl(pxa_rtc, RDAR1);
tm_calc(ryar, rdar, &alrm->time);
rtsr = rtc_readl(pxa_rtc, RTSR);
alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
return 0;
}
static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
u32 rtsr;
spin_lock_irq(&pxa_rtc->lock);
rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
rtsr = rtc_readl(pxa_rtc, RTSR);
if (alrm->enabled)
rtsr |= RTSR_RDALE1;
else
rtsr &= ~RTSR_RDALE1;
rtc_writel(pxa_rtc, RTSR, rtsr);
spin_unlock_irq(&pxa_rtc->lock);
return 0;
}
static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
seq_printf(seq, "update_IRQ\t: %s\n",
(rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
seq_printf(seq, "periodic_IRQ\t: %s\n",
(rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
return 0;
}
static const struct rtc_class_ops pxa_rtc_ops = {
.read_time = pxa_rtc_read_time,
.set_time = pxa_rtc_set_time,
.read_alarm = pxa_rtc_read_alarm,
.set_alarm = pxa_rtc_set_alarm,
.alarm_irq_enable = pxa_alarm_irq_enable,
.proc = pxa_rtc_proc,
};
static int __init pxa_rtc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pxa_rtc *pxa_rtc;
struct sa1100_rtc *sa1100_rtc;
int ret;
pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
if (!pxa_rtc)
return -ENOMEM;
sa1100_rtc = &pxa_rtc->sa1100_rtc;
spin_lock_init(&pxa_rtc->lock);
platform_set_drvdata(pdev, pxa_rtc);
pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!pxa_rtc->ress) {
dev_err(dev, "No I/O memory resource defined\n");
return -ENXIO;
}
sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
if (sa1100_rtc->irq_1hz < 0)
return -ENXIO;
sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
if (sa1100_rtc->irq_alarm < 0)
return -ENXIO;
sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
if (IS_ERR(sa1100_rtc->rtc))
return PTR_ERR(sa1100_rtc->rtc);
pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
resource_size(pxa_rtc->ress));
if (!pxa_rtc->base) {
dev_err(dev, "Unable to map pxa RTC I/O memory\n");
return -ENOMEM;
}
pxa_rtc_open(dev);
sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
sa1100_rtc->rtar = pxa_rtc->base + 0x4;
sa1100_rtc->rttr = pxa_rtc->base + 0xc;
ret = sa1100_rtc_init(pdev, sa1100_rtc);
if (ret) {
dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
return ret;
}
rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
&pxa_rtc_ops, THIS_MODULE);
if (IS_ERR(pxa_rtc->rtc)) {
ret = PTR_ERR(pxa_rtc->rtc);
dev_err(dev, "Failed to register RTC device -> %d\n", ret);
return ret;
}
device_init_wakeup(dev, 1);
return 0;
}
static int __exit pxa_rtc_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
pxa_rtc_release(dev);
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id pxa_rtc_dt_ids[] = {
{ .compatible = "marvell,pxa-rtc" },
{}
};
MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
#endif
#ifdef CONFIG_PM_SLEEP
static int pxa_rtc_suspend(struct device *dev)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
return 0;
}
static int pxa_rtc_resume(struct device *dev)
{
struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
static struct platform_driver pxa_rtc_driver = {
.remove = __exit_p(pxa_rtc_remove),
.driver = {
.name = "pxa-rtc",
.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
.pm = &pxa_rtc_pm_ops,
},
};
module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
MODULE_AUTHOR("Robert Jarzmik <[email protected]>");
MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-rtc");
| linux-master | drivers/rtc/rtc-pxa.c |
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