anchor.diff:      {V2, TS2} = H2,
       VEqual = V1 =:= V2,
       TSEqual = riak_dt_vclock:equal(TS1, TS2),
  -    if VEqual andalso TSEqual ->
  +    case VEqual andalso TSEqual of
  +	true ->
               eq(T1, T2);
  -        true ->
  +        false ->
               false
       end;
   eq(_, _) ->
  
positive.code: %% since there can be diverged value in this register.
  -spec value(mvreg()) -> [term()].
  value(MVReg) ->
      [Val || {Val, _TS} <- MVReg].
  
  %% @doc query for this `mvreg()' of its timestamp.
  %% `timestamp' is the only query option.
  -spec value(mv_q(), mvreg()) -> [term()].
  value(timestamp, MVReg) ->
      [TS || {_Val, TS} <- MVReg].
  
  %% @doc Assign `Value' to this register. The vector clock of this
  %% register will be incremented by one for the corresponding `Actor'.
  
negative.code: %%
  %% This kind of update is supposed to be linealizable so the operation
  %% issuer does not need to provide the vector clock it has observed.
  -spec update(mvreg_op(), actor(), mvreg()) -> {ok, mvreg()}.
  update({assign, Value}, Actor, MVReg) ->
      VV = inc_vv(MVReg, Actor),
      NewMVReg = [{Value, VV}],
  