anchor.diff:  update(Op, Actor, Reg, _Ctx) ->
       update(Op, Actor, Reg).
   
  -%% @doc Increment one for the corresponding vector clock of this actor.
  +%% @doc Find a least-uppder bound for all non-compatible vector clocks in MVReg 
  +%% (if there is any) and then increment timestamp for `Actor' by one.
   incVV(MVReg, Actor) ->
       TSL = [TS || {_Val, TS}<- MVReg],
       [H|T] = TSL,
  
positive.code: %% that both registers contain the same value and timestamp.
  -spec equal(mvreg(), mvreg()) -> boolean().
  equal(MVReg1, MVReg2) ->
      V1 = value(MVReg1),
      TS1 = value(timestamp, MVReg1),
      V2 = value(MVReg2),
      TS2 = value(timestamp, MVReg2),
      if V1 == V2 andalso TS1 == TS2 ->
              true;
          true ->
              false
      end.
  %equal(_, _) ->
  %    false.
  
  -spec stats(mvreg()) -> [{atom(), number()}].
  stats(MVReg) ->
  
negative.code: -define(V1_VERS, 1).
  
  %% @doc Encode an effecient binary representation of an `mvreg()'
  %% Not working yet...
  -spec to_binary(mvreg()) -> binary().
  to_binary(MVReg) ->
      <<?TAG:8/integer, ?V1_VERS:8/integer, (riak_dt:to_binary(MVReg))/binary>>.
  