anchor.diff:      {ok, MVRA1_1} = update({assign, value1}, actor1, MVRA1_0),
       %% Propagate a timestamp that is not compatible with the current ones
       {ok, MVRMerge1} = update({propagate, value2, VCA2}, nothing, MVRA1_1),
  -    ?assert(equal([value1, value2], value(MVRMerge1))),
  -    ?assert(equal([VCA1, VCA2], value(timestamp, MVRMerge1))),
  +    ?assertEqual(lists:sort([value1, value2]), lists:sort(value(MVRMerge1))),
  +    ?assertEqual(lists:sort([VCA1, VCA2]), lists:sort(value(timestamp, MVRMerge1))),
       VCA12 = riak_dt_vclock:increment(actor2, VCA1),
       %% Propagate a timestamp that dominates all current ones
       {ok, MVRMerge2} = update({propagate, value2, VCA12}, nothing, MVRMerge1),
  -    ?assert(equal([value2], value(MVRMerge2))),
  -    ?assert(equal([VCA12], value(timestamp, MVRMerge2))),
  +    ?assertEqual([value2], value(MVRMerge2)),
  +    ?assertEqual([VCA12], value(timestamp, MVRMerge2)),
       %% Propagate a timestamp that is dominated by the current one
       {ok, MVRMerge3} = update({propagate, value3, VCA1}, nothing, MVRMerge2),
  -    ?assert(equal([value2], value(MVRMerge3))),
  -    ?assert(equal([VCA12], value(timestamp, MVRMerge3))).
  +    ?assertEqual([value2], value(MVRMerge3)),
  +    ?assertEqual([VCA12], value(timestamp, MVRMerge3)).
       
   %% Test if a diverged MVReg merges all timestamp after being updated.
   update_assign_diverge_test() ->
  
positive.code: %% that both registers contain the same value and timestamp.
  -spec equal(mvreg(), mvreg()) -> boolean().
  equal(MVReg1, MVReg2) ->
      V1 = value(MVReg1),
      TS1 = value(timestamp, MVReg1),
      V2 = value(MVReg2),
      TS2 = value(timestamp, MVReg2),
      if V1 == V2 andalso TS1 == TS2 ->
              true;
          true ->
              false
      end.
  %equal(_, _) ->
  %    false.
  
  -spec stats(mvreg()) -> [{atom(), number()}].
  stats(MVReg) ->
  
negative.code: update(Op, Actor, Reg, _Ctx) ->
      update(Op, Actor, Reg).
  
  %% @doc Find a least-uppder bound for all non-compatible vector clocks in MVReg 
  %% (if there is any) and then increment timestamp for `Actor' by one.
  incVV(MVReg, Actor) ->
      TSL = [TS || {_Val, TS}<- MVReg],
      [H|T] = TSL,
  