anchor.diff:      cg_bin_opt([{move,S,Dst}|Is]);
   cg_bin_opt([{move,{integer,0},D},{bs_add,Fail,[D,S,U],Dst}|Is]) ->
       cg_bin_opt([{bs_add,Fail,[{integer,0},S,U],Dst}|Is]);
  -cg_bin_opt([{move,{integer,Bytes},D},{Op,Fail,D,Extra,Regs0,Flags,D}|Is])
  +cg_bin_opt([{move,{integer,Bytes},D},{Op,Fail,D,Extra,Regs,Flags,D}|Is])
     when Op =:= bs_init2; Op =:= bs_init_bits ->
  -    Regs = cg_bo_newregs(Regs0, D),
       cg_bin_opt([{Op,Fail,Bytes,Extra,Regs,Flags,D}|Is]);
   cg_bin_opt([{move,Src1,Dst},{bs_add,Fail,[Dst,Src2,U],Dst}|Is]) ->
       cg_bin_opt([{bs_add,Fail,[Src1,Src2,U],Dst}|Is]);
   cg_bin_opt([I|Is]) ->
       [I|cg_bin_opt(Is)];
   cg_bin_opt([]) -> [].
  -
  -cg_bo_newregs(R, {x,X}) when R-1 =:= X -> R-1;
  -cg_bo_newregs(R, _) -> R.
  -
  -%% Common for new and old binary code generation.
   
   cg_bin_put({bin_seg,[],S0,U,T,Fs,[E0,Next]}, Fail, Bef) ->
       S1 = cg_reg_arg(S0, Bef),
  
positive.code:     {[{put_list,S1,S2,Ret}], Int1, St};
  set_cg([{var,R}], {binary,Segs}, Le, Vdb, Bef,
         #cg{in_catch=InCatch, bfail=Bfail}=St) ->
      Int0 = Bef#sr{reg=put_reg(R, Bef#sr.reg)},
      Target = fetch_reg(R, Int0#sr.reg),
      Fail = {f,Bfail},
      Temp = find_scratch_reg(Int0#sr.reg),
      PutCode = cg_bin_put(Segs, Fail, Bef),
      {Sis,Int1} =
  	case InCatch of
  
negative.code: %%
  %%  put_list for constructing a cons is an atomic instruction
  %%  which can safely resuse one of the source registers as target.
  
  set_cg([{var,R}], {cons,Es}, Le, Vdb, Bef, St) ->
      [S1,S2] = cg_reg_args(Es, Bef),
  