anchor.diff:      ?assert(riak_dt_vclock:equal(VC1_4, VC_MVR2)).
       
   
  +%% Do we need a merge? Anyway its functionality is very similar to propagate.
   %merge_test() ->
   %    LWW1 = {old_value, 3},
   %    LWW2 = {new_value, 4},
  
positive.code: value(timestamp, MVReg) ->
      [TS || {_Val, TS} <- MVReg].
  
  %% @doc Assign a `Value' to the `mvreg()'
  %% associating the update with time `TS'. This kind of update is supposed to be
  %% linealizable so the assigner does not need to provide the
  %% timestamp it has observed. The update is only applied if the timestamp
  %% dominate the current one.
  -spec update(mvreg_op(), term(), mvreg()) ->
                      {ok, mvreg()}.
  update({assign, Value, TS}, Actor, MVReg) ->
      case dominate_ts(TS, Actor, MVReg) of 
          true ->
              VV = incVV(MVReg, Actor),
              NewMVReg = [{Value, VV}],
  
negative.code: update(Op, Actor, Reg, _Ctx) ->
      update(Op, Actor, Reg).
  
  %% @doc Find a least-uppder bound for all non-compatible vector clocks in MVReg 
  %% (if there is any) and then increment timestamp for `Actor' by one.
  incVV(MVReg, Actor) ->
      TSL = [TS || {_Val, TS}<- MVReg],
      [H|T] = TSL,
  