anchor.diff:  update(Op, Actor, Reg, _Ctx) ->
       update(Op, Actor, Reg).
   
  -%% @doc Increment one for the corresponding vector clock of this actor.
  +%% @doc Find a least-uppder bound for all non-compatible vector clocks in MVReg 
  +%% (if there is any) and then increment timestamp for `Actor' by one.
   incVV(MVReg, Actor) ->
       TSL = [TS || {_Val, TS}<- MVReg],
       [H|T] = TSL,
  
positive.code:             merge_to(T, lists:append(MVReg2, [H]))
      end.
  
  
  is_dominated([], _VC) ->
      false;
  is_dominated([H|T], VC) ->
      case riak_dt_vclock:dominates(H, VC) of 
          true ->
              true;
          false ->
              is_dominated(T, VC)
      end.
  
  
  
negative.code: -define(V1_VERS, 1).
  
  %% @doc Encode an effecient binary representation of an `mvreg()'
  %% Not working yet...
  -spec to_binary(mvreg()) -> binary().
  to_binary(MVReg) ->
      <<?TAG:8/integer, ?V1_VERS:8/integer, (riak_dt:to_binary(MVReg))/binary>>.
  