<gh_stars>0
#-
# Copyright (c) 2017 <NAME>
# All rights reserved.
#
# This software was developed by the University of Cambridge Computer
# Laboratory as part of the Rigorous Engineering of Mainstream Systems (REMS)
# project, funded by EPSRC grant EP/K008528/1.
#
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#
# Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
# license agreements.  See the NOTICE file distributed with this work for
# additional information regarding copyright ownership.  BERI licenses this
# file to you under the BERI Hardware-Software License, Version 1.0 (the
# "License"); you may not use this file except in compliance with the
# License.  You may obtain a copy of the License at:
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#   http://www.beri-open-systems.org/legal/license-1-0.txt
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# Unless required by applicable law or agreed to in writing, Work distributed
# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, either express or implied.  See the License for the
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from beritest_tools import BaseBERITestCase, is_feature_supported

class test_x_msa_ri(BaseBERITestCase):
    EXPECTED_EXCEPTIONS = 1

    def test_x_msa_ri(self):
        self.assertRegisterEqual(self.MIPS.v0, 1, "This test should raise exactly one exception")

    def test_x_msa_ri_csc_bigimm(self):
        if is_feature_supported("capabilities") and is_feature_supported("experimental_csc"):
            self.assertCompressedTrapInfo(self.MIPS.s1, mips_cause=self.MIPS.Cause.COP_Unusable, trap_count=1,
                msg="CSC (BigImm) is supported -> should raise a coprocessor disabled exception")
        else:
            # instruction should not be supported and raise R
            self.assertCompressedTrapInfo(self.MIPS.s1, mips_cause=self.MIPS.Cause.ReservedInstruction, trap_count=1,
                msg="CSC (BigImm) is not supported -> should raise a RI exception")
