I sometimes make mistake when changing VHDL code to add new functionality that, the new signals added into the VHDL process are not reset when the reset state is asserted. This mistake could be quite harmless sometimes but at other times it can lead to design failure in simulation or even hardware.

What tool do I use to ensure that all signals and variables used inside a process are assigned an initial value in the process, maybe when reset is asserted or maybe every clock cycle?