I'm trying to connect two latches made by 74xx chips (normal output: 7404, 7408, 7432...), so that the inverted main output signal is latched into the first circuit on the falling edge and into the second circuit on the rising edge. Thus the main output will switch from low to high and vice versa every clock cycle.

The clock is a debounced push-button connected to a inverted to create sharp edges. 
The timing is done by sending the clock signal through more inverters.

Each circuit works perfectly when tested individually, but as soon as I connect the output of the first one to a input of the second one, it only latches correctly about 20% of the time.

To fix this problem I added a 1uF capacitor.

When testing the circuit, I found that on one AND-gate the output goes low before any input goes low. I tested it with a simple S-R-latch to check wich signal goes low first.

Here's the schematics:

![schematic](https://i.stack.imgur.com/LHo2o.png)

[simulate this circuit](/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fLHo2o.png) – Schematic created using [CircuitLab](https://www.circuitlab.com/)

Here's the breadboard:
[![enter image description here](https://i.stack.imgur.com/FZd34.jpg)](https://i.stack.imgur.com/FZd34.jpg)

The yellow wires at the bottom create a S-R-latch that I used for testing.
The testing showed that the output of the first AND-gate on the third chip goes low first, then the clock signal (first input), then the output of the first OR-gate (second input). 

What should happen (3rd chip, 1st gate):
Clock goes low -> output goes low -> 2nd input on the 2nd AND-gate goes low AFTER the clock on the 2nd AND-gate goes high -> latch successful

What seems to happen:
Output goes low (??) -> clock and 2nd input go low (on time) -> 2nd input on the 2nd AND-gate goes low BEFORE the clock on the 2nd AND-gate goes high -> latch unsuccessful

One might think that the output goes low too early, because the 2nd input goes low before the clock does. But that can't happen because the signal of the 2nd input depends on the same clock and goes through more transistors (is delayed). Yet holding the second input stable with a capacitor solves the problem.

So, how can the output of that gate go low before any of the inputs? 

Why do both circuits work when separate (which means the 2nd input of their first AND-gates is manually pulled high or low) but not when the second latch gets its signal from the first one and vice versa?