I'm learning VHDL for programming a FPGA, basic (but hard-for-me) projects. I have this ALU. It is supossed to be a 4-bit ALU. But when I want to make the **Add** operation the value of `result` is `UUUU`. For all other operations is working fine.

Any advise?

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port (
                clk: in std_logic;
                reset: in std_logic;
                operation: in std_logic_vector (2 downto 0)
          );
end ALU;

architecture Behavioral of ALU is
    signal A : std_logic_vector (3 downto 0) := "0001";
    signal B : std_logic_vector (3 downto 0) := "1111";
    signal result : std_logic_vector (7 downto 0);
    signal flags : std_logic_vector (2 downto 0);   -- [S,OF,Z] 
begin

    process (operation) begin
        flags <= (others => '0');
        result <= (others => '0');
        case operation is
            when "000" => 
                result <= std_logic_vector((unsigned("0000"&A) + unsigned(B)));
                flags(1) <= result(4);
            when "001" =>
                if (A >= B) then
                    result <= std_logic_vector(unsigned("0000"&A) - unsigned(B));
                    flags(2) <= '0';
                else
                    result <= std_logic_vector(unsigned("0000"&B) - unsigned(A));
                    flags(2) <= '1';
                end if;
            when "010" =>
                result <= "0000"&A and "0000"&B;
            when "011" =>
                result <= "0000"&A or "0000"&B;
            when "100" =>
                result <= "0000"&A xor "0000"&B;
            when "101" =>
                result <= not ("1111"&A);
            when "110"  =>
                result <= not ("1111"&B);
            when "111" =>
                result <= std_logic_vector(unsigned(A) * unsigned(B));
            when others =>
                result <= (others => 'Z');
        end case;
    end process;

end Behavioral;

```