I have a Verilog array defined as :

```
logic [ 0 : num_elements - 1 ] [ element_width - 1 ] some_array ;

```

I want to assign every array element with a vector that is all ones: "11...1".
I tried this but I get an error:

```
some_array <= { num_elements { element_width { 1'b1 } } } ;

```

What's the correct syntax ?