With the following makefile snippet:

```
main: main.o f1.o f2.o
    $(CC) $(CFLAGS) -o program main.o f1.o f2.o

main.o: main.cc
    $(CC) $(CFLAGS) -c main.cc

f1.o: f1.cc
    $(CC) $(CFLAGS) -c f1.cc

f2.o: f2.cc
    $(CC) $(CFLAGS) -c f2.cc

```

If I just change one file, only that file get recompiled when I rerun make, as desired. However, I'm having a hard time generalizing this without having to list each file individually. When I try something like:

```
$(OBJECTS): $(SOURCES)
    $(CC) $(CFLAGS) -o $@ -c $(patsubst %.o,%.cc,$@)

```

It builds each object file individually, but each object file depends on ALL my sources, so a change in any one file causing a full recompile. What's a good way to accomplish this?