I have the following module that is a simple register:

```
module linear_out
(
    input clock,
    input resetn,
    input [31:0] x,
    output reg [31:0] y
);

    always @(posedge clock)
        if (!resetn)
            y <= 32'h00000000;
        else
            y <= x;

endmodule

```

When I synthetize it with Quartus II and I check the *fmax* in *Timing Analyzer from Quartus II*, the *fmax* advice that: *No paths to report*, but the output is registered... If instead of set only one register, I set two, the *fmax* already shows a value.

But, I don't get it: Why is it? Is it neccesary set 2 or more clock cycles to get a syntetyzable design with a *known fmax*?