I'm writing a Verilog program which would repeatedly run and change the value of the varible clk from 0 to 1, back to 0 and so on, running infinite times. Here's the code of the module:

```
module FirstQuestion(
output clk
);
reg clk;

initial
begin
    while(1)
    begin
        clk = 0;
        #10
        clk = 1;
    end
end    
endmodule

```

However, the output waveform is just showing 0 as the output. The mistake, I know must be trivial one. Can the mistake be just pointed and corrected out?
Here is the code for testbench:

```
module FirstQuestion_tb;

wire ty;

FirstQuestion mygate(.clk(ty));
integer i;
initial 
begin
    $monitor(ty);
    //for(i=0; i<10; i=i+1);

end

endmodule

```