I am somewhat confused with why someone would want to buffer a CMOS logic gate and what the advantages are to doing so. Let's say I have a certain CMOS logic gate such as a NAND gate as shown below:

[![enter image description here](https://i.stack.imgur.com/29dSh.png)](https://i.stack.imgur.com/29dSh.png)

This is fairly simple to understand in terms of logic and input voltage levels. You would call this CMOS NAND gate "unbuffered". What I want to understand is if you add two NOT gates to the output of this circuit, you would still have the same CMOS NAND gate but it would be considered "buffered". Could someone explain me what are the advantages of adding additional NOT gates at the output of a logic block and how do they buffer your output?

The circuit I am asking about would look like this:

![schematic](https://i.stack.imgur.com/TxKqO.png)

[simulate this circuit](/plugins/schematics?image=http%3a%2f%2fi.stack.imgur.com%2fTxKqO.png) – Schematic created using [CircuitLab](https://www.circuitlab.com/)