If I have the following VHDL-200X architecture:

```
architecture my_arc of my_entity is
    signal test_char   : std_logic_vector(7 downto 0);
    signal test_char_c : character;
    signal test_char_i : integer;
begin
    test_char   <= "01001010";
    test_char_i <= to_integer(unsigned(test_char));
    test_char_c <= character'val(test_char_i);
end architecture my_arc;

```

...and simulate it (in Xilinx iSim 14.1), `test_char_c` does not change from its initial value of `NUL` even though `test_char_i` takes the value `74`. If, however, I replace the last line in the architecture with:

```
    process(test_char_i)
    begin
        test_char_c <= character'val(test_char_i);
    end process;

```

...then `test_char_c` takes on the value `J` as I'd expect.

I thought that a bare signal assignment will be updated concurrently if *any* signal on the right hand side changes. In other words, it's equivalent to a process that is sensitive to all signals involved in the assignment.

Why doesn't `test_char_c` get updated in the first instance?

**Edit:** Changing `test_char_i` to a `natural` doesn't change the result.