This [discussion of Verilog relational operators at ASIC World](http://www.asic-world.com/verilog/operators1.html) clearly has at least one mistake:

> 
> * The result is a scalar value (example a < b)
> * 0 if the relation is false (a is bigger then b)
> * 1 if the relation is true (a is smaller then b)
> * x if any of the operands has unknown x bits (if a or b contains X)
> 
> 
> Note: If any operand is x or z, then the result of that test is
>  treated as false (0)
> 
> 
> 

Clearly, "a is bigger than b" should be "a is bigger *than or equal to* b". 

There is something else that looks wrong to me, but I don't know if it's just because I'm a Verilog novice. The last bullet point seems to contradict the subsequent note, unless there is a difference between an operand having all unknown bits (in which case the result of a relational operator will be x) and an operand being x (in which case the result will be 0).

Is there a difference between an operand being x and all of its bits being X? I know Verilog is case-sensitive.