The following question reads:
Suppose that a CPU issues a read for an instruction and that read does not cause a page fault to be generated. Assuming that the MMU uses a TLB to do the address translation and that there is a single page table, what is the maximum number of cache misses that can occur throughout the entire process of translating the virtual address to a physical address and retrieving the instruction? (Assume, that there is only a level-1 cache for the DRAM.)

I do understand that the TLB is used to reduce the huge consequential cost of fetching from memory, but I don't understand virtual memory enough to be able to answer this question -I'm also aware that that TLB misses are rare. Anyways, I'd appreciate it if anyone can help me understand this problem.

Thanks in advance!