I found an intel document which states memory barriers are required when string (not `std::string`, but assembly string instructions) are used, to prevent them being re-ordered by the CPU. 

However, are memory barriers also required when two threads (on two different cores) are accessing the same memory? The scenario I had in mind is where one of the CPUs which doesn't "own" the cache line writes to this memory and the core writes to its store buffer (as opposed to its cache). A memory barrier is required to flush the value from the store buffer to the cache, so the other core can obtain this value?

I am unsure whether, on Intel, the MESI protocol handles this?

(what I have tried to (badly) explain above is better-described in the below paper, pages 6-12):

<http://www.puppetmastertrading.com/images/hwViewForSwHackers.pdf>

The above paper is very general and I am unsure how Intel CPUs practically handle the problem.