I have a VHDL memory core which requires me to multiplex between two clocks. The Write clock operates at 200 Mhz and Read clock operates at 100 Mhz. I think this can be done using `BUFGMUX` (correct me if there is a better way to do this)

Is it possible to somehow infer this in VHDL instead of instantiating it ? What are your experiences with this ? Can you post some sample code ?

**\* EDIT \***

The READ ports are completely occupied and need to be used simultaneously. The write operation will occur only once in the start as an initialization step.

RRS