I am kind of new to PCB Design. I have a few confusions on my board layout, in order to reduce EMI in routing. I am designing a two-layer PCB design

1. I am aware that when you route traces over different layer and if they cross each other, coupling occurs between the cross-sectional area where the two traces meet as they create a parasitic capacitance. But if it definitely has to cross, then it has to cross at 90 degrees. My question is: Is this applicable for all kind of traces where a power trace crosses an analog or digital trace?
2. Since the power trace has the lowest impedance because of its wider trace, is it possible to crossover two power traces on different layers?
3. How wide should be the trace length, if I am taking it all over the board for a star connection (as daisy chaining is a bad practice)?
4. Is it correct to add decoupling capacitors on the cross-sectional area over the weaker trace?

I am working with low power circuits, where the voltage is 3.3V and the microcontroller runs at 8 MHz, a 1 MHz buck-boost with a couple of analog and digital sensors. I have also made sure that the analog and digital ground are separated and directly meet at the origin (i.e. a battery). 

Also, is there any signal integrity simulation software available as open source?

Any suggestions and tips apart from this are also welcome. Thank you.