I am having trouble learning how to model n bit wide mux's in verilog.

I am trying to gate level model a 2 bit wide multiplexer, here is my current code:

```
module _2bit_mux_2_1(m,x,y,s);

    output m[1:0];

    input x[1:0];
    input y[1:0];

    input s;

    and (t0,s,y[0]),
        (t1,sbar,x[0])
        (t0,s,y[1]),
        (t1,sbar,x[1]);

    not (sbar,s);

    or (m[1:0],t0,t1);
endmodule

```

I am receiving the following error messages:

> 
> 
> ```
> [Synth 8-2715] syntax error near ( 
> 
> port m must not be declared to be an array 
> 
> part-select of memory m is not allowed
> 
> ```
> 
> 

Can anyone help me out or point me in the right direction for some easy understanding of how to implement this?