Assume I have the following constraints file which specifies only one single input:

```
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { Switch }];

```

And the following top file which also lists `input A` and `output B` in it's `port` specification:

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test11 is
port (
    Switch      : in std_logic;
    A           : in std_logic;
    B           : out std_logic
);
end test11;

architecture Behavioral of test11 is
begin
    B <= A xor Switch;
end Behavioral;

```

This compiles just fine.

Are `A` and `B` assigned to some random pins? Are they tied to `'0'` or `'1'`?