Here's my makefile:

```
AS=nasm
ASFLAGS=-f elf64

%: %.o
        ${LD} -o $@ $<

```

Suppose I have a source file `foo.s`, I can run `make foo.o` then `make foo` to make the executable `foo`.

```
$ make foo.o
nasm -f elf64  -o foo.o foo.s
$ make foo
ld -o foo foo.o

```

But if I run `make foo` directly, `cc` is used instead.

```
$ rm foo foo.o
$ make foo
cc -f elf64   foo.s   -o foo
cc: error: elf64: No such file or directory
cc: error: unrecognized command line option ‘-f’
make: *** [<builtin>: foo] Error 1

```

This is explained in [the documentation](https://www.gnu.org/software/make/manual/make.html#Catalogue-of-Rules), at the end of the section "Linking a single object file".

How should I write my makefile so that I can run `make foo` to make `foo.o` from `foo.s` and then `foo` from `foo.o` automatically?