I would like to delay a signal several cycles in vhdl, but I have problems using [how to delay a signal for several cycles in vhdl](https://stackoverflow.com/questions/7918133/how-to-delay-a-signal-for-several-cycles-in-vhdl/) 

Wouldn't I need a registered signal? I mean, something like:

---

```
a_store and a_store_registered would be std_logic_vector(cycles_delayed-1 downto 0)

```

---

```
process(clk)
begin
    if rising_edge(clk) then
      a_store_registered <= a_store;
    end if;
end process;    
a_out <= a_store_registered(cycles_delayed-1);

process(a_store_registered, a)
begin    
      a_store <= a_store_registered(size-2 downto 0) & a;
end process;

```

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