I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see [page 6 of this Micron technical note](http://www.micron.com/~/media/Documents/Products/Technical%20Note/DRAM/TN4702.pdf). I'm also easily convinced that trace length-matching matters when you're talking about 8cm traces or passing through a DIMM connector.

However I'm not convinced that trace-length matching is terribly important in a highly-optimized layout where you've got a memory chip butted directly up against the ASIC/FPGA that controls it, and the traces are all less than 1.5cm long. In a situation like that the "wiggles" required to match trace length will significantly increase the floor on the equalized trace length, probably doubling it.

Does anybody have actual scope plots showing the improvement, if any, gained by trace length matching when all traces are less than ~1.8cm long?

Of particular note the highest-speed memory standard (GDDR5) explicitly abandoned trace-length matching since it requires the component be on the same board as the controller (no DIMMs) and located very nearby. The JEDEC spec explicitly instructs board designers **not** to match trace lengths, but rather to minimize them independently instead.