I am trying to make a behavorial model of a Serial Adder in Modelsim. 

So, in the design I am trying to pass the Carry\_out to the Carry\_in after one clock cycle.

The design is: 

one bit, each from two n-bit numbers enter the adder along with the carry.

Initially the carry is 0 but in the next clock cycle the carry\_out from the addition of the previous bits are again passed as the carry\_in and addition is done with the next two bits, one from each number.

Here is the code:

```
library ieee;

use ieee.std_logic_1164.all;

entity serial_adder is

    port (a,b: in std_logic;
        s: out std_logic;
        cin,cout: inout std_logic);
end serial_adder;

architecture serial_adder_arch of serial_adder is
begin
    process(a,b,cin,cout)
    begin
    if (a='0' and b ='0' and cin ='0')
    then s <='0';
         cout <='0';
    elsif (a='0' and b ='0' and cin ='1')
    then s <='1';
         cout <='0';
    elsif (a='0' and b ='1' and cin ='0')
    then s <='1';
         cout <='0';
    elsif (a='0' and b ='1' and cin ='1')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='0' and cin ='0')
    then s <='1';
         cout <='0';
    elsif (a='1' and b ='0' and cin ='1')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='1' and cin ='0')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='1' and cin ='1')
    then s <='1';
         cout <='1';
    end if;
    cin <= cout after 50 ps;
    end process;

end serial_adder_arch;

```

After simulation, I am seeing that the delay that I am giving using 'after' is not working. I am getting no delay and the `cout` is not getting assigned to `cin`