I am trying to instantiate a VHDL component in a Verilog design as a part of testing a divide function in another complex design. Getting syntax error:

> 
> Error (10170): Verilog HDL syntax error at deldel.v(29) near text:
>  "["; expecting ")".......
> 
> 
> 

My VHDL file:

```
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.NUMERIC_STD.ALL;

entity divide_test is
    port(
            odabir      : in std_logic_vector(9 downto 0);
            rezultat    : out std_logic_vector(9 downto 0)
            );
end divide_test;

architecture behavioral of divide_test is

    constant deljenik0  : unsigned(23 downto 0) := x"000999"; --2457
    constant deljenik1  : unsigned(23 downto 0) := x"000FA7"; --4007
    constant deljenik2  : unsigned(23 downto 0) := x"000288"; --648
    constant delilac        : unsigned(23 downto 0) := x"000015"; --21

    signal rez_temp : unsigned(23 downto 0);
    signal od_temp  : integer range 0 to 3;

begin
    od_temp <= to_integer(unsigned(odabir));
    rezultat <= std_logic_vector(rez_temp(9 downto 0));
    deljenje: process(od_temp)
    begin
        case  od_temp is
            when 0 => rez_temp <= x"000000";
            when 1 => rez_temp <= deljenik0/delilac; --150
            when 2 => rez_temp <= deljenik1/delilac; --200
            when 3 => rez_temp <= deljenik2/delilac; --32
        end case;
    end process;

end behavioral;

```

My Verilog file:

```
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module deldel(

    //////////// LED //////////
    output           [9:0]      LEDR,

    //////////// SW //////////
    input            [9:0]      SW
);

//=======================================================
//  REG/WIRE declarations
//=======================================================

//=======================================================
//  Structural coding
//=======================================================

divide_test u0(
    .odabir[1] (SW[0]),
    .odabir[0] (SW[1]),
    .rezultat[0] (LEDR[0]),
    .rezultat[1] (LEDR[1]),
    .rezultat[2] (LEDR[2]),
    .rezultat[3] (LEDR[3]),
    .rezultat[4] (LEDR[4]),
    .rezultat[5] (LEDR[5]),
    .rezultat[6] (LEDR[6]),
    .rezultat[7] (LEDR[7]),
);

endmodule

```

Verilog file is generic, created from "DE1SoC\_SystemBuilder". I am trying to connect SW0 and SW1 from DE1Soc board to select one from three operation and show the result with eight LEDs on DE1Soc board!

What am I missing?