I know Verilog for only like 2 months, 3 months tops. I am absolutely frustrated about this one thing, which I would refer to as *race condition* if it was happening in some other, non-HDLanguage I know. Here are the files in their most simplified form, describing the case:

The `circuit.v`

```
module circuit(f, x, clk, rst);

    output f;
    input x, clk, rst;

    wire d, q;

    d_flip_flop flipper (q, d, clk, rst);

    assign f = q;
    assign d = x;

endmodule

```

The `d_flip_flop.v`

```
module d_flip_flop(q, d, clk, rst);

    output reg q;
    input d, clk, rst;

    always @(posedge clk, posedge rst)
    begin
        if (rst)
            q <= 1'b0;
        else
            q <= d;
    end

endmodule

```

And I test these with this `tester.v`

```
module tester;

    reg x, clk, rst;
    wire f;

    circuit uut (f, x, clk, rst);

    initial clk <= 0;
    always #10 clk <= ~clk;

    initial
    begin
        x <= 0;
        rst <= 0;

        rst <= #2 1;
        rst <= #4 0;

        #10 x <= 1;
    end

endmodule

```

And here's the waveform I get:

![waveform](https://i.stack.imgur.com/mTYuZ.png)

What I see from that waveform is that Verilog has decided that it should first process the change in `clk`, hence perform the `q <= d;`; and only then process the change in `x`, hence perform `assign d = x;`.

What I said there probably doesn't even make sense in the hardware, but whatever.

Now: I have people around me, so called the assistants of the lecture, more experienced and presumably more knowledgeable, claiming that a *properly written* Verilog sequential module always considers the changes as happened, as the clock hits posedge. Even in this extremely simple example, however, I see it to be otherwise (and probably not necessarily, either).

So, the question is, what should I be doing to turn this into a *properly written* Verilog sequential module? How could I make my bad code to be a good one like the others? Or is there just no such thing, and Verilog is just proudly non-deterministic in such cases?