I know that webassembly currently supports a 32 bit architecture, so I am supposing that, like RISCV32, that its base instruction set has instructions which are 32 bit wide (Of course, RISCV32 supports 16-bit compressed instructions and 48-bit ones as well). RISC-V's instructions are interpreted mostly as left-endian (in terms of bit indices).

For example, in RISC-V, we can have an instruction like `lui` (load upper-immediate to register), that embeds a 20-bit immediate into an instruction, has a 5-bit field to encode the desitination register, and a 7-bit format to specify the opcode. Among other things, the opcode contains two bits at the beginning that connote whether the instruction is compressed or not. This is encoded in the specification, where `lui` has an `LUI` opcode.:

[![RISC-V opcode listing](https://i.stack.imgur.com/Atdvs.png)](https://i.stack.imgur.com/Atdvs.png)

RISC-V instructions have a variety of different layouts specified in the specification as well, and for example, the `lui` instruction takes the "U" format, so we know exactly where the 20-bit field is and where the 5-bit destination register is in the serialization:
[![RISC-V instruction layouts](https://i.stack.imgur.com/JyKB9.png)](https://i.stack.imgur.com/JyKB9.png)

What is the bit width of a wasm instruction? What are the possible layouts of a wasm instruction? Are there compressed instruction formats for webassembly, such as 16-bit instructions for very common operations?

If webassembly instructions are variable-width, how is the width of an instruction encoded for the interpreter?