In VHDL the Integer type is defined as a 32-bit signed integer. Most guidelines recommend that it must be constrained when used for synthesis if don't want a full 32-bit bus. My question is regarding your experience with various synthesis tools and the following piece of code. My assumption is that the non-dependent signals would be optimized away, but there might be other issues.

```
signal x : integer;

process(x) is
    constant alpha : integer := 12;
    variable y : integer;
begin
   y := (alpha*y + (100-alpha)*x) / 100;
   result <= to_signed( y, 16);
end process;

```