I have the following code.

```
module tb;

reg clk;
reg clk_2;
reg [15:0] from_flop;
reg [15:0] to_flop;

initial begin
        clk = 0; 
        clk_2 = 0;
        from_flop = 1;
end

always #10 clk = ~clk;

always @(posedge clk) begin
        clk_2 <= ~clk_2;
end

always @(posedge clk) begin
        from_flop <= from_flop + 1; 
end

always @(posedge clk_2) begin
        to_flop <= from_flop; 
end

endmodule

```

However, at time instant 10ns, from\_flop and to\_flop both get value = 2. This is contrary to what I was expecting. I was expecting from\_flop to change from 1 to 2 at 10ns, and to\_flop to change from x to 1 at 10ns.

Why is this happening and how to code such that this doesn't happen?