I was wondering if someone can tell me what is the best way to give name to different states in Verilog? For example instead of the following case

```
case (a)
  1'b0 : statement1;
  1'b1 : statement2;
  1'bx : statement3;
  1'bz : statement4;
endcase

```

It is much better to have a piece of code with this format

```
case (a)
  Load : statement1;
  Store : statement2;
  Check : statement3;
  Reset : statement4;
endcase

```