I'm looking into creating a system in VHDL that filters an image after receiving it through an FTDI usb-to-serial device. As part of this, I believe I've identified the states that my CPLD should be in, but I have never created a complex state machine in VHDL before, so I'm questioning whether my methods are sound. Currently, the basic outline for my state machine is thus:

```
begin
    process(clk, reset, USB_RXFN, USB_TXEN)
    begin
        case state is
            when IDLE =>
            when NEGOTIATING =>
            when RECEIVING =>
            when FILTERING =>
            when TRANSMITTING =>
            when OTHERS  => -- this should never happen but go to IDLE
    end process;

```

My problem here is that every state machine tutorial I've been able to find changes state on every rising edge (or similar, but once per clock) and this device should sit in IDLE a lot and only transition to NEGOTIATING when USB\_RXFN goes low, stay in NEGOTIATING until that's done, stay in RECEIVING until the entire image has been transferred etc...

Is there something fundamentally flawed in my approach? Are CPLD's simply unsuited for this purpose? Or is it possible to stay in a state for more than a single clock and the tutorials are just written that way for simplicity?