I am trying to make a counter that depends on a signal. The signal is high for two cycles and low for next two and this continues till the end. During the high pulse, count should start from 0, 1 . When the pulse is low count is 'x and from next high it continues from 2, 3 then again 'x for two cycles (upcounts only when pulse is high) and then again 4, 5. I am new to Verilog and this is an assignment.

When I made the following code I am getting counts 1 2 x 1 2 x always. Any help?

```
always@(posedge clk or posedge rst)
If(rst)
Count <= 0;
else 
Count <= signal; 

assign signal  = pulse ? Count + 1: 'x; 

```

I am getting 1 2 x x1 2 x x instead of. 1 2 x x 3 4 x x 5 6 x x etc. Any help is appreciated.