I'm looking to design a bus functional model for SPI and UART bus. First, I want to understand if my perception of a bus functional model is correct.

It is supposed to simulate bus transactions, without worrying about the underlying implementation specifics. 

For instance,
If I were to build a BFM for an SPI bus, the design should be able to simulate transactions on the SPI acting as a master based on some protocol for example reading instructions from a file and then showing them on a simulator accordingly,

For example a generic data transfer instruction, like send\_write(0x0c, 0x0f), that sends data byte 0c to the slave address 0f, should drive the Chip Select line low and send the data bits accordingly on the clock edge based on the SPI mode, is my understanding of BFM correct in this case?

Now what I don't understand this is, how is it helpful?
Where in between the DUT and the TestBench does a BFM sit, and how does it help a system designer.

I also want to know if there are any reference BFMs that have been built and tested that are available to study,

I'd appreciate if someone could help me with an example, preferably in System Verilog.