I was trying to implement Dual-priority encoder but I get following warnings during synthesize:

> 
> WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a
>  combinatorial loop: done, first<3>, req[0]\_done\_AND\_6\_o, f.
> 
> 
> WARNING:Xst:2170 - Unit prEnc : the following signal(s) form a
>  combinatorial loop: f.
> 
> 
> 

I got no idea how and where my signals form a combinatorial loop. 

Here is the code. 

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prEnc is
port( req : in std_logic_vector(7 downto 0);
        first : out std_logic_vector(3 downto 0);
        second : out std_logic_vector(3 downto 0)
);
end prEnc;

architecture Behavioral of prEnc is
signal f, done : std_logic ;
begin
process (req,f,done)
begin
    first <= "0000";
    second <= "0000";
    f <= '0';
    done <= '0';

    if req(7) = '1' then
        first <= "1000";
        f <= '1';
    end if ;
    if req(6) = '1' then
        if f = '0' then
            first <= "0111";
            f <= '1';
        else 
            second <= "0111";
            done <= '1';
        end if;
    end if;
    if req(5) = '1' and done = '0' then
        if f = '0' then
            first <= "0110";
            f <= '1';
        else
            second <= "0110";
            done <= '1';
        end if;
    end if;
    if req(4) = '1' and done = '0' then
        if f = '0' then
            first <= "0101";
            f <= '1';
        else 
            second <= "0101";
            done <= '1';
        end if;
    end if;
    if req(3) = '1' and done = '0' then
        if f = '0' then
            first <= "0100";
            f <= '1';
        else 
            second <= "0100";
            done <= '1';
        end if;
    end if;
    if req(2) = '1' and done = '0' then
        if f = '0' then
            first <= "0011";
            f <= '1';
        else 
            second <= "0011";
            done <= '1';
        end if;
    end if;
    if req(1) = '1' and done = '0' then
        if f = '0' then
            first <= "0010";
            f <= '1';
        else 
            second <= "0010";
            done <= '1';
        end if;
    end if;
    if req(0) = '1' and done = '0' then
        if f = '0' then
            first <= "0001";
            f <= '1';
        else 
            second <= "0001";
            done <= '1';
        end if;
    end if;
end process;

end Behavioral;

```