I'm having some problems understanding the timing behaviors I observe in Logisim. I've isolated some cases which illustrate the problem.

Say I have a register (1-bit, to keep it simple), which is being fed a logical 1 on its input D. Upon the clock the register is set to 1, as expected:

![register being set to 1 upon clock](https://i.stack.imgur.com/tUKZi.png)

For this to work, the D input must already be receiving the logical 1 when the clock signal arrives. If, by using an N-type transistor, we only let the data line be high when the clock is high, then the register will no longer be correctly set, due to the delay introduced by the transistor:

![sync problem introduced](https://dl.dropbox.com/u/140506/logisim/reg1.png)

Indeed, if we add two NOT gates to the clock line that is sufficient to delay the clock signal (relative to the data line) and make sure the D input receives the logical 1 on time again, allowing the register to be correctly set:

![delay clock with two NOT gates](https://i.stack.imgur.com/A13zJ.png)

Of course, that is a horrible kludge and cannot be relied upon, since gate timings can vary due to component tolerances and other reasons. Still, so far so good, all of these behaviors made sense to me. What I don't understand is the following two cases. 

I thought: if I put an N-type transistor in the clock line, to only let the clock signal pass after the data signal has passed its respective transistor, that should synchronize everything up. But it doesn't work:

![sync with N-type transistor](https://i.stack.imgur.com/2mEs0.png)

It also doesn't work with a "Controlled Buffer" component:

![sync with controlled buffer](https://dl.dropbox.com/u/140506/logisim/reg3-1.png)

Even more surprisingly, if I use a P-type transistor then the register is set, even though the register's clock input is floating, instead of set to high:

![sync with P-type transistor](https://dl.dropbox.com/u/140506/logisim/reg4.png)

Can you please explain me these last two behaviors?