please can anyone help me convert the following Verilog to vhdl. Thank you.

```
//Module to inject errors into Hamming Code
 module InjectError(input [7:0] Din,
input [4:0] Pin,
output [7:0] Dout,
output [4:0] Pout,
input [12:0] Ein);
 assign {Dout, Pout} = {Din, Pin} ^ Ein;
 endmodule

```