I am writing a VHDL code to impelemt 8 bit serial adder with accumulator.
When i do simulation, the output is always zeros! And some times it gives me the same number but with a shift ! 
 I dont know what is the problem, i tried to put A,B as inout but didnt work as well. Can anybody help please. 

This is the code:

```
entity SA is

Port ( st : in std_logic;
        A,B: inout std_logic_vector ( 7 downto 0);
       clk : in std_logic;
       acc : out bit_vector(7 downto 0)); end SA; 
architecture Behavioral of SA is

 signal ps,ns: integer range 0 to 7;

signal C,D: bit_vector (7 downto 0);

signal ci,ciplus,si,sh:bit;

begin

 si<=A(0) xor B(0) xor ci ;
 ciplus <=(A(0) and B(0)) or (A(0) and ci ) or ( B(0) and ci );

   process(ps,st)
   begin
  case ps  is
  when 0=> if(st='0')then 
      ns<=0;
      else
       ns<=1;
       sh<='1';
       end if;
       when 1 to 6 => sh<='1';
       ns<= ps+1;
        when 7=> sh<='1';
        ns <=0;
        end case;
        end process;

        process(clk)
        begin
        if(clk 'event and clk ='1')then
             ps <= ns;
        ci<= ciplus;
                end if;
        if(sh='1') then 
        C<=si & A(7 downto 1) ;
         D<=B(0) & B(7 downto 1);
        end if;

        end process;

        acc<= C;

        end Behavioral;

```

`