I've a module that have a 8bit input and a serial output, I want to serialize input data and synchronize it with a clock.

I want to set my data when falling edge then wait when clock rise, when clock fall again I set another data. I don't want to connect the directly reference clock to the output because when I don't use this module I want a 1 state on clock output.

I've tried this code:

```
process(Clock, ModuleReset)
    begin
        if ModuleReset = '0' then
            OutData <= '0';
            OutCK <= '0';
            counter <= 7;
        elsif falling_edge(Clock) then
                OutCK <= '0';
                OutData <= Data(counter);
        elsif rising_edge(Clock) then
                OutCK <= '1';
        end if;
end process;

```

The synthesizer gives me this error:

> 
> "Asynchronous load of non-constant data for SCK is not supported" 
> 
> 
> 

When I separate the code in two blocks like this:

```
process(Clock, ModuleReset)
    begin
        if ModuleReset = '0' then
            OutData <= '0';
            OutCK <= '0';
            counter <= 7;
        elsif falling_edge(Clock) then
                OutCK <= '0';
                OutData <= Data(counter);
end process;

process(Clock)
        if rising_edge(Clock) then
                OutCK <= '1';
        end if;
end process;

```

I have these two errors:

> 
> "Multiple non tristate drivers for net SCK"  
> 
>  "Unresolved tristate drivers for net SCK" 
> 
> 
> 

Another code I've tried is:

```
process(Clock, ModuleReset)
    if ModuleEN = '1' then
       OutCK <= Clock;
    end if;
    begin
        if ModuleReset = '0' then
            OutData <= '0';
            OutCK <= '0';
            counter <= 7;
        elsif falling_edge(Clock) then
                OutCK <= '0';
                OutData <= Data(counter);
        end if;
end process;

```

But the output clock looks strange with a different frequency.