I am trying to create a UART receiver in Verilog for my FPGA. I was following this guide <http://www.fpga4fun.com/SerialInterface4.html>

According to it the standard practice for asynchronous communication is to oversample the signal at 16 times the BAUD rate. This makes sense to me since I would need to do this to detect the first drop quickly and synchronize with the transmitting clock.

What I am wondering is why not just sample at the same frequency as the clock on my FPGA which is a lot fast than 16x the BAUD (my clock is 100 MHz). Is there any harm in doing this? I know it would probably just consume more power, but would it work or is there something I am missing?