I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. The rapid-recompile button is always grayed out, I don't even know what it does, I've never had the option. A lot of times, I'm not changing my design just SignalTap, but Quartus wants to recompile everything which seems like a waste of time. Is there a way speed up the compile time (or changes to only apply to SignalTap)? Using Quartus 15.1