I'm trying to instantiate some modules in Verilog using a `generate` block since I'm going to be instantiating a variable amount of them.

```
genvar i;
generate
    for (i=1; i<=10; i=i+1) begin
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

```

`a` & `b` are declared as input arrays to the parent module and `out` is declared as a array of wires.

What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me:

```
Error (10644): Verilog HDL error at driver.v(63): this block requires a name

```

Line 63 is the for loop above. Any help is appreciated!