Trying to design a Z80 based computer that starts from an EEPROM, loads CP/M to RAM and pages out (switches off) EEPROM to allow CP/M to access full 64K RAM. What is a good way of achieving this ? My current thought process is initially mapping EEPROM to the bottom of TPA (see image), say between 0x1000 to 0x2FFF, use a single JP 0x1000 instruction at 0x0000. Let the code to load CP/M CCP/BDOS and BIOS as well as a small piece of code somewhere on the rest of TPA (say 0x3000) that disables EEPROM and jumps to BDOS. Then jump to 0x3000 when I finish loading everything.

Sounds a bit complicated, is there a more practical way of doing it that you can think of?

Main question is then how to disable EEPROM, all I can think of is a TTL based latch addressed a yet unused portion of TPA to bring CE of EEPROM to high permanently (until the next reset or power cycle). Any recommendations here ?

[![CPM](https://i.stack.imgur.com/u2a8o.gif)](https://i.stack.imgur.com/u2a8o.gif)