My question here is with reference to [this question previously asked](https://electronics.stackexchange.com/questions/241130/introduce-delay-on-a-single-bit-signal-w-r-t-input-clock).
Currently, I am able to generate delays for each signal as desired.

Next, I want to generate different delays for alternate `vsync` rising edges.
Example:

* If it is the first rising edge of `vsync`, then generate delay equal to 4 clock cycles on output (i.e., `vsync_o`).
* If it is the second rising edge of `vsync`, then generate delay equal to 2 clk cycles on output (i.e., `vsync_o`).

So the delays I want on the output should alternate between 4 clock cycles and 2 clock cycles.

I am not able to figure out how to do this. I am currently initializing a counter which does not reset (so I can compute the number of vsync pulses).....but this will ultimately saturate. Is there a better method or am I missing something? 

I have written the following code. Will this lead to any problems which can be avoided otherwise?

```
`timescale 1ns / 1ps

module Sync_Delay( clk_27,  vsync,   hsync,          
                            vsync_o, hsync_o );

 input clk_27;

 input wire vsync;
 input wire hsync;

 output reg vsync_o;
 output reg hsync_o;

 reg[20:0] v_bits;
 reg[2:0] h_bits;

 reg cnt = 0;

 always @ (posedge vsync)
 begin
     cnt = !cnt;
 end

 always @ (posedge clk_27)
    begin
    if (cnt == 0)
       begin
       vsync_o <= vsync;
       hsync_o <= hsync;
       end
    else
       begin
       vsync_o <= v_bits[20];
       v_bits <= {v_bits[19:0], vsync};
       hsync_o <= h_bits[2];
       h_bits <= {h_bits[1:0], hsync};
       end
 end
endmodule

```

I notice a difference in pulse width between the input and output signal, which is not desirable.