Please help to resolve one randomization-constraint related issue that I am facing.

So in my seqItem, I have a `write_addr` random variable. This variable controls the location in memory where the data should be written.
I want to implement different writing address changing modes like random-address, given range address, ascending and descending type. 
I have params\_pkg, where user defines the address change type and my TB generates write\_addr values correspondingly.

I was thinking to implement this using constraints, like by enableing/disabling the constrains get the required behavioral:

```
class seqItem extends uvm_sequence_item;
    `uvm_object_param_utils(seqItem)

    randc logic [541-1:515] wfifo_addr;
   if (params_pkg::writeAddressType == "WriteGivenRangeAddress") begin
        constraint wArrdGivnRangCnstr {
            this.wfifo_addr  inside {[params_pkg::addrLowValue:params_pkg::addrHighValue]};
       }
 end
  function new (string name="seqItem");
        super.new(name);
        this.wArrdGivnRangCnstr.constraint_mode(0);
    endfunction

endclass

```

However there is no way to generate ascending or descending address values using constraints. Because to have ascending address, the seqitem code needs to know the `write_addr` variable value from the previous randomization, which I could not implement.

My question is: whether it is possible to have ascending `write_addr` values using constraints?

And second, the example code that I posted is not working, simulator gives error saying that generate constraints are not allowed. Most probably this is something not supported in System Verilog. Am I right?