I'm still learning VHDL for synthesis purposes on a custom Xilinx Spartan-6 based board. My design includes a lot of FSM and I've just learned in a previous question that the single process implementation is a lot better and much easier to use.

I also learned that initialization values for signals are actually synthetizable.

So here is the question: do I really need a reset signal to put the FSM in idle with default outputs, **IF** I don't need to interrupt the FSM mid flow OR I already have another signal that stops it?