i am trying to write a SVA assertion for a handshake procedure. 

In my searches I have found the following:

```
property p_handshake(clk,req,ack);
@(posedge clk)
req |=> !req [*1:max] ##0 ack;
endproperty
assert property(p_handshake(clock,valid,done));

```

However, my "done" signal is allowed to come many cycles after the valid cycle goes high. How do you make this statement ensure that "done" is asserted at *any* point after valid is asserted, without valid being deasserted?