I encountered a problem during preparing an assembler x86 project which subject is to write a program getting L1 data, L1 code, L2 and L3 cache size. 

I tried to find something in Intel Documentation & in the Internet but I failed. 

THE MAIN PROBLEM IS: In case of AMD processors it is just to set EAX register to 80000005h & 80000006h values and get desired data from ECX and EDX registers but in case of Intel I can obtain this information only for L2. 

What should I do to get L1 & L3 cache size for Intel processors ?