I have been working on a vhdl program that accepts 2 inputs, a 3-bit input and a 4-bit input. The 3-bit input represents "2 to the power of n", ie an input of 010(which is 2) would equal 2^2=4. An input of 110(which is 6) would yield 2^6 which is 64. This is to be multiplied by a 4-bit input from 0000 to 1111, and the answer stored as 8-bits. However, when I try to solve for this in VHDL, I keep getting the error "Expression error at midterm\_q\_one.vhd(34): expression has 12 elements, but must have 8 elements". I am new to VHDL, and searching online has yielded little result. I want a way for my output, in this case hex, to store the product of my 2 inputs as an 8 bit value but don't know how. Any help would be greatly appreciated and below is my code. Thanks!

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity midterm_q_one is
port(en: in std_logic;
     reset: in std_logic;
      three_bit: in std_logic_vector(2 downto 0);
      four_bit: in std_logic_vector(3 downto 0);
      hex: out std_logic_vector(7 downto 0)
);
end midterm_q_one;

architecture arch of midterm_q_one is
signal temp : std_logic_vector(7 downto 0);
begin
    process(en, reset, three_bit, four_bit)
    begin
if(reset = '1') then
    temp <= "00000000";--reset to decimal 0
elsif(en = '1') then
        case three_bit is
            when "000" => temp <= "00000001";--1
            when "001" => temp <= "00000010";--2
            when "010" => temp <= "00000100";--4
            when "011" => temp <= "00001000";--8
            when "100" => temp <= "00010000";--16
            when "101" => temp <= "00100000";--32
            when "110" => temp <= "01000000";--64
            when "111" => temp <= "10000000";--128
       end case;
end if;
hex <= temp * four_bit;
    end process;
    end arch;

```