I am trying to use the SPI0 component of a Zynq XC7Z010 to read data from a 12-bit rotary encoder which uses an SSI protocol.

* I have a small example project set up in Vivado which enables the SPI0 to use EMIO ports and sets the pins I want to use.
* I also have the xspips driver working and am able to receive data from the encoder.
* The problem I am facing is that I could only set up a clock signal which is idle low, while the encoder expects an idle high clock.

	+ Due to this, the first bits received are unusable, and I had to do some bit-manipulation to recover these bits (the encoder starts repeating the same data again after the 12 bit transmission).

With an oscilloscope I tested out that the sent out clock signal is always idle low, whether the CLK\_ACTIVE\_LOW option is set or not for the SPI, so I concluded that that option is only for how the Zynq interprets the clock signal. 

How can I have a clock signal that is high by default? Do I have to manually invert it in the Vivado generated VHDL wrapper, or is there a simpler solution?

Measured clock signal for a 2 byte transfer when ACTIVE\_LOW is enabled: 
[![enter image description here](https://i.stack.imgur.com/XGnho.jpg)](https://i.stack.imgur.com/XGnho.jpg)
and when it is disabled: 
[![enter image description here](https://i.stack.imgur.com/5Lm32.jpg)](https://i.stack.imgur.com/5Lm32.jpg)