I'm trying to do one of the exercises on the book I'm studying from. The idea is to turn on/off LEDS depending on switches. But I got a place design error when tried to run implementation (synthesis ok):

> 
> ERROR:[Place 30-574] Poor placement for routing between an IO pin and
>  BUFG. If this sub optimal condition is acceptable for this design, you
>  may use the CLOCK\_DEDICATED\_ROUTE constraint in the .xdc file to
>  demote this message to a WARNING. However, the use of this override is
>  highly discouraged. These examples can be used directly in the .xdc
>  file to override this clock rule.
> 
> 
> 

I'm learning FPGA design so clearly not an expert at it. After trying to "debug" and isolate the error, I found that this works:

```
module led_pattern(led, l_sw, r_sw);

output reg [15:0] led;
input [1:0] r_sw;
input [15:14] l_sw;

always @ (r_sw or l_sw)
begin
if (r_sw[0] == 1'b1)
    begin
        led[0] = 1'b1;
        led[1] = 1'b1;
    end
else
    begin
        led[0] = 1'b0;
        led[1] = 1'b0;
    end
if (r_sw[0] == 1'b0 && r_sw[1] == 1'b0 && l_sw[14] == 1'b0 && l_sw[15] == 1'b0)
    begin
        led[7] = 1'b1;
        led[8] = 1'b1;
    end
else
    begin
        led[7] = 1'b0;
        led[8] = 1'b0;
    end
end

endmodule

```

but this doesn't (it triggers the above quoted error):

```
module led_pattern(led, l_sw, r_sw);

output reg [15:0] led;
input [1:0] r_sw;
input [15:14] l_sw;

always @ (r_sw or l_sw)
begin
if (r_sw[0] == 1'b1)
    begin
        led[0] = 1'b1;
        led[1] = 1'b1;
    end
else if (r_sw[0] == 1'b0)
    begin
        led[0] = 1'b0;
        led[1] = 1'b0;
     end

if (r_sw[0] == 1'b0 && r_sw[1] == 1'b0 && l_sw[14] == 1'b0 && l_sw[15] == 1'b0)
    begin
        led[7] = 1'b1;
        led[8] = 1'b1;
    end
else
    begin
        led[7] = 1'b0;
        led[8] = 1'b0;
    end
end

endmodule

```

Note that the only difference is in the former I used else statement and in the latter I used "else if". Finally, the part of top module where I'm instantiating led\_pattern is:

```
module top(LED, AN, CA, CB, CC, CD, CE, CF, CG, SW);

// Ports declaration
input [15:0] SW;
output [7:0] AN;
output CA,CB,CC,CD,CE,CF, CG;
output [15:0] LED;
wire [6:0] seg = {CG, CF, CE, CD, CC, CB, CA}; 
reg [3:0] seg_value;
led_pattern sys(LED, SW[15:14], SW[1:0]);

```

didn't put the rest of the code because might not be necessary.

Note: I'm not using clocks here (at least not on purpose, maybe yes by accident?). led is used for LEDS on NEXYS4 DDR and l\_sw, r\_sw are switches from the board. This is purely combinatorial.

**What could be causing that place error?**