A lot of VHDL structures has the option for an `optional_label` before the declaration, but what is this label used for?

Here is a process declaration example from [vdlande](https://www.ics.uci.edu/~jmoorkan/vhdlref/process.html) showing the option for a label:

```
optional_label: process (optional sensitivity list)
    -- declarations
begin
    -- sequential statements
end process optional_label;

```