I have variable in my Makefile:

```
SRCP = \
 main.c \
 lib1/src/file1.c \
 lib2/src/file2.c

```

Folders `lib1/src` and `lib2/src` may consist other sources, but I need compil only files in `SRCP` var.

I know one variant:

```
OBJ_DIR = ./Release/Obj
OBJ = $(SRC:.c=.o)
$(OBJ): $(SRCP)
    for source in $(SRCP); do \
        $(CC) $(CLAGS) -c $$source -o $(OBJ_DIR)/$@; \
    done

```

But not informative. In console I see `$source` instead `main.c` (or any name).

My makefile with errors:

```
.PHONY: all clean

PROJECT = hello

IAR_TARGET = ./Release
EXE_DIR = $(IAR_TARGET)/Exe
OBJ_DIR = $(IAR_TARGET)/Obj

COMPILE_OPTS = -mcpu=cortex-m3 -mthumb -Wall -g -O0
INCLUDE_DIRS = -I . \
 -I lib/inc

SRCP = \
 main.c \
 lib/src/stm32f10x_tim.c \
 lib/src/stm32f10x_adc.c

LIB = -L ./lib/src

SRC := $(notdir $(SRCP))

OBJ_FILES := $(addprefix $(OBJ_DIR)/,$(notdir $(SRCP:.c=.o)))

CC = arm-none-eabi-gcc
CFLAGS = $(COMPILE_OPTS) $(INCLUDE_DIRS)

# mkdir -p $(EXE_DIR) $(OBJ_DIR)
all: $(EXE_DIR)/$(PROJECT).elf

# Linker invocation
$(EXE_DIR)/$(PROJECT).elf: $(OBJ_FILES)
    $(CC) $(CFLAGS) $(OBJ_FILES) -o $(EXE_DIR)/$(PROJECT).elf

# Rules
%.o: %.c
    $(CC) $(CFLAGS) -c $< -o $@

clean:
    rm -rf $(IAR_TARGET)

```

Error: `make: *** No rule to make target 'Release/Obj/main.o', needed by 'Release/Exe/hello.elf'. Stop.`

What is the correct version you know?