Sometimes I got warnings in Xilinx ISE:

> 
> Latches may be generated from incomplete case or if statements. We do
>  not recommend the use of latches in FPGA/CPLD designs, as they may
>  lead to timing problems.
> 
> 
> 

But if I use rising\_edge() function, then there is no warning even if I have an incomplete case, like:

```
process (clk, rst)
begin   
    if (rst = '1') then
        test <= '0';
    elsif (rising_edge(clk)) then
        test <= '1';
    end if;
end process;

```

So why latches in FPGA are considered as an ugly design? And why using rising\_edge() function can avoid those warnings? (In fact, I think using rising\_edge() function will also introducing a latch)