{- Copyright 2020 The Project Oak Authors
  
   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the License at
  
       http://www.apache.org/licenses/LICENSE-2.0
  
   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an "AS IS" BASIS,
   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.
-}


module Main where

import Cava2SystemVerilog
import LUTTests

main :: IO ()
main = do writeSystemVerilog lut1_inv_netlist
          writeTestBench lut1_inv_tb
          writeSystemVerilog lut2_and_nelist
          writeTestBench lut2_and_tb
          writeSystemVerilog lut3_mux_nelist
          writeTestBench lut3_mux_tb
          writeSystemVerilog lut4_and_nelist
          writeTestBench lut4_and_tb
          writeSystemVerilog lut5_and_nelist
          writeTestBench lut5_and_tb
          writeSystemVerilog lut6_and_nelist
          writeTestBench lut6_and_tb


