riscv:
  incdirs: [
    include,
  ]
  files: [
    alu.sv,
    alu_div.sv,
    compressed_decoder.sv,
    controller.sv,
    cs_registers.sv,
    debug_unit.sv,
    decoder.sv,
    exc_controller.sv,
    ex_stage.sv,
    hwloop_controller.sv,
    hwloop_regs.sv,
    id_stage.sv,
    if_stage.sv,
    load_store_unit.sv,
    mult.sv,
    prefetch_buffer.sv,
    prefetch_L0_buffer.sv,
    riscv_core.sv,
  ]
riscv_vip_rtl:
  incdirs: [
    include,
  ]
  files: [
    riscv_tracer.sv,
    riscv_simchecker.sv,
  ]
riscv_regfile_rtl:
  incdirs: [
    include,
  ]
  files: [
    register_file.sv,
  ]
riscv_regfile_fpga:
  incdirs: [
    include,
  ]
  files: [
    register_file_ff.sv,
  ]


riscv:
  incdirs: [
    include,
  ]
  files: [
    alu.sv,
    alu_div.sv,
    compressed_decoder.sv,
    controller.sv,
    cs_registers.sv,
    debug_unit.sv,
    decoder.sv,
    exc_controller.sv,
    ex_stage.sv,
    hwloop_controller.sv,
    hwloop_regs.sv,
    id_stage.sv,
    if_stage.sv,
    load_store_unit.sv,
    mult.sv,
    prefetch_buffer.sv,
    prefetch_L0_buffer.sv,
    riscv_core.sv,
  ]
riscv_vip_rtl:
  targets: [
    rtl,
  ]
  incdirs: [
    include,
  ]
  files: [
    riscv_tracer.sv,
    riscv_simchecker.sv,
  ]
riscv_regfile_rtl:
  targets: [
    rtl,
  ]
  incdirs: [
    include,
  ]
  files: [
    register_file.sv,
  ]
riscv_regfile_fpga:
  targets: [
    xilinx,
  ]
  incdirs: [
    include,
  ]
  files: [
    register_file_ff.sv,
  ]


Add proper targets for sub-ips
Add proper targets for sub-ips
