
x266 - open H.266 codec software & hardware implementation
==========================================

x266 is an open source highly optimal software/hardware co-design architecture implementation of the next generation H.266 video codec.

It is demonstration research of industrialized implement video coding H.266. as soon as H.266 specification release, I will publishing my industrialize H.266 codec.

x266 based on Software/Hardware Cooperative concept and flexible task distributed and resource reuse architecture.


Building
========



Prebuilt
=================

- C/C++ interface code can be obtained from /src_c<br>
- Verilog code can be obtained from /src_ver<br>


License
=======

x266 is distributed under the terms of the Private/Education ONLY License.
See COPYRIGHT for more details.

See `LICENSE.TXT` for more details.

Creator on November 2015<br>
Copyright (c) 2015-2017 Min Chen<br>
Contact: Min Chen <chenm003@gmail.com><br>


x266 - open H.266 codec software & hardware implementation
==========================================

x266 is an open source highly optimal software/hardware co-design architecture implementation of the next generation H.266 video codec.

It is demonstration research of industrialized implement video coding H.266. as soon as H.266 specification release, I will publishing my industrialize H.266 codec.

x266 based on Software/Hardware Cooperative concept and flexible task distributed and resource reuse architecture.


Building
========

- RISC-V<br>
    build onestage<br>
    ./run_asm.sh onestage<br>
    ./run_bmark.sh onestage<br>


Prebuilt
=================

- C/C++ interface code can be obtained from /src_c<br>
- Verilog code can be obtained from /src_ver<br>


License
=======

x266 is distributed under the terms of the Private/Education ONLY License.
See COPYRIGHT for more details.

See `LICENSE.TXT` for more details.

Creator on November 2015<br>
Copyright (c) 2015-2017 Min Chen<br>
Contact: Min Chen <chenm003@gmail.com><br>

Update readme.md for RISC-V CPU and testbench
[RISCV] Update readme.md for RISC-V CPU and testbench
