An [i8080](https://en.wikipedia.org/wiki/Intel_8080) cycle accurable CPU build from logic gates and ROMs. 

**NOTE**: Requires DLS 0.13.0 and up (schematic version 2.1).

## Schematic
### <a name="i8080 System"></a>i8080 System with a 512x320 1bpp display
[Schematic](i8080 System.sch)
![i8080 System](images/i8080_system.png "i8080 System")

### i8080 CPU [Large version](https://raw.githubusercontent.com/jdryg/dls-schematics/raw/master/i8080/images/i8080_large.png)
![i8080 CPU](images/i8080_cpu.png "i8080 CPU")

### i8080 ALU
![i8080 ALU](images/i8080_alu.png "i8080 Arithmetic/Logic Unit")

### i8080 Register File
![i8080 Register File](images/i8080_rf.png "i8080 Register File")

### i8080 Internal Data Bus
![i8080 Internal Data Bus](images/i8080_internal_data_bus.png "i8080 Internal Data Bus")

An [i8080](https://en.wikipedia.org/wiki/Intel_8080) cycle accurable CPU build from logic gates and ROMs. 

**NOTE**: Requires DLS 0.13.0 and up (schematic version 2.1).

## Schematic
### <a name="i8080 System"></a>i8080 System with a 512x320 1bpp display
[Schematic](i8080 System.sch)
![i8080 System](images/i8080_system.png "i8080 System")

### i8080 CPU [Large version](https://raw.githubusercontent.com/jdryg/dls-schematics/master/i8080/images/i8080_large.png)
![i8080 CPU](images/i8080_cpu.png "i8080 CPU")

### i8080 ALU
![i8080 ALU](images/i8080_alu.png "i8080 Arithmetic/Logic Unit")

### i8080 Register File
![i8080 Register File](images/i8080_rf.png "i8080 Register File")

### i8080 Internal Data Bus
![i8080 Internal Data Bus](images/i8080_internal_data_bus.png "i8080 Internal Data Bus")

Fix link to large image
Fix link to large image
