# RISC-V Metadata

This directory contains metadata for the RISC-V Instruction Set

|File|Description|
|:---|:----------|
|`codecs`      |Instruction encodings|
|`compression` |Compressed instruction metadata|
|`constraints` |Constraint definitions|
|`csrs`        |CPU Specific Registers|
|`descriptions`|Instruction long descriptions|
|`enums`       |Enumerated types|
|`extensions`  |Instruction set extensions|
|`formats`     |Disassembly formats|
|`instructions`|Instruction pseudo code|
|`opcodes`     |Opcode encoding information|
|`operands`    |Bit encodings of operands|
|`registers`   |Registers and their ABI names|
|`types`       |Instruction types|
# RISC-V Metadata

This directory contains metadata for the RISC-V Instruction Set

|File|Description|
|:---|:----------|
|`codecs`      |Instruction encodings|
|`compression` |Compressed instruction metadata|
|`constraints` |Constraint definitions|
|`csrs`        |Control and status registers|
|`descriptions`|Instruction long descriptions|
|`enums`       |Enumerated types|
|`extensions`  |Instruction set extensions|
|`formats`     |Disassembly formats|
|`instructions`|Instruction pseudo code|
|`opcodes`     |Opcode encoding information|
|`operands`    |Bit encodings of operands|
|`registers`   |Registers and their ABI names|
|`types`       |Instruction types|
Update description for control and status registers
Update description for control and status registers
