BCM2836 per-CPU interrupt controller

The BCM2836 has a per-cpu interrupt controller for the timer, PMU
events, and SMP IPIs.  One of the CPUs may receive interrupts for the
peripheral (GPU) events, which chain to the BCM2835-style interrupt
controller.

Required properties:

- compatible:	 	Should be "brcm,bcm2836-l1-intc"
- reg:			Specifies base physical address and size of the
			  registers
- interrupt-controller:	Identifies the node as an interrupt controller
- #interrupt-cells:	Specifies the number of cells needed to encode an
			  interrupt source. The value shall be 1

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

The interrupt sources are as follows:

0: CNTPSIRQ
1: CNTPNSIRQ
2: CNTHPIRQ
3: CNTVIRQ
8: GPU_FAST
9: PMU_FAST

Example:

local_intc: local_intc {
	compatible = "brcm,bcm2836-l1-intc";
	reg = <0x40000000 0x100>;
	interrupt-controller;
	#interrupt-cells = <1>;
	interrupt-parent = <&local_intc>;
};

Add documentation for the bcm2836 interrupt controller
irqchip: Add documentation for the bcm2836 interrupt controller

This is a new per-cpu root interrupt controller on the Raspberry Pi 2,
which will chain to the bcm2835 interrupt controller for peripheral
interrupts.

Signed-off-by: Eric Anholt <96f164ad4d9b2b0dacf8ebee2bb1eeb3aa69adf1@anholt.net>
Acked-by: Stephen Warren <5ef2a23ba3aff51d1cfc8c113c1ec34b608b3b13@wwwdotorg.org>
Cc: 823ee39736cc6e52f417843340e48a8067371f8c@lists.infradead.org
Cc: Lee Jones <cdedbaf433217656e9df940dd535438abed9f74c@kernel.org>
Cc: Jason Cooper <68c46a606457643eab92053c1c05574abb26f861@lakedaemon.net>
Cc: f99ef57ccac738b558d0fc2e44478b3c5def9522@lists.infradead.org
Link: http://lkml.kernel.org/r/1438902033-31477-4-git-send-email-96f164ad4d9b2b0dacf8ebee2bb1eeb3aa69adf1@anholt.net
Signed-off-by: Thomas Gleixner <00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de>
