# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# Authors: Nathan Binkert

from m5.params import *
from m5.proxy import *
from MemObject import MemObject

class PioDevice(MemObject):
    type = 'PioDevice'
    abstract = True
    pio = SlavePort("Programmed I/O port")
    system = Param.System(Parent.any, "System this device is part of")

class BasicPioDevice(PioDevice):
    type = 'BasicPioDevice'
    abstract = True
    pio_addr = Param.Addr("Device Address")
    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")

class DmaDevice(PioDevice):
    type = 'DmaDevice'
    abstract = True
    dma = MasterPort("DMA port")
    min_backoff_delay = Param.Latency('4ns',
      "min time between a nack packet being received and the next request made by the device")
    max_backoff_delay = Param.Latency('10us',
      "max time between a nack packet being received and the next request made by the device")



class IsaFake(BasicPioDevice):
    type = 'IsaFake'
    pio_size = Param.Addr(0x8, "Size of address range")
    ret_data8 = Param.UInt8(0xFF, "Default data to return")
    ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
    ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
    ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
    ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
    update_data = Param.Bool(False, "Update the data that is returned on writes")
    warn_access = Param.String("", "String to print when device is accessed")
    fake_mem = Param.Bool(False,
      "Is this device acting like a memory and thus may get a cache line sized req")

class BadAddr(IsaFake):
    pio_addr = 0
    ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")


