#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake.  If not, see <http://www.gnu.org/licenses/>.
#


import string
from string import Template
import fetch
from makefile_writer import MakefileWriter
import logging


class ToolControls(MakefileWriter):

    def detect_version(self, path):
        pass
  
    def get_keys(self):
        tool_info = {
            'name': 'Aldec Active-HDL',
            'id': 'aldec',
            'windows_bin': 'vsimsa',
            'linux_bin': None
        }
        return tool_info

    def get_standard_libraries(self):
        ALDEC_STANDARD_LIBS = ['ieee', 'std']
        return ALDEC_STANDARD_LIBS

    def generate_simulation_makefile(self, fileset, top_module):
        # TODO: ??
        from srcfile import VHDLFile, VerilogFile, SVFile
        makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
ALDEC_CRAP := \
run.command \
library.cfg

#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd

simulation:
""")
        makefile_text_1 = makefile_tmplt_1.substitute(
            top_module=top_module.top_module
        )
        self.write(makefile_text_1)

        self.writeln("\t\techo \"# Active-HDL command file, generated by HDLMake\" > run.command")
        self.writeln()

        self.writeln("\t\techo \"# Create library and set as default target\" >> run.command")
        self.writeln("\t\techo \"alib work\" >> run.command")
        self.writeln("\t\techo \"set worklib work\" >> run.command")
        self.writeln()

        self.writeln("\t\techo \"# Compiling HDL source files\" >> run.command") 
        for vl in fileset.filter(VerilogFile):
            self.writeln("\t\techo \"alog " + vl.rel_path() + "\" >> run.command")
        for sv in fileset.filter(SVFile):
            self.writeln("\t\techo \"alog " + sv.rel_path() + "\" >> run.command")
        for vhdl in fileset.filter(VHDLFile):
            self.writeln("\t\techo \"acom " + vhdl.rel_path() + "\" >> run.command")
        self.writeln()
 
        makefile_tmplt_2 = string.Template("""      
\t\tvsimsa -do run.command

sim_pre_cmd:
\t\t${sim_pre_cmd}

sim_post_cmd:
\t\t${sim_post_cmd}

#target for cleaning all intermediate stuff
clean:
\t\trm -rf $$(ALDEC_CRAP) work

#target for cleaning final files
mrproper: clean
\t\trm -f *.vcd *.asdb

.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation

""")

        if top_module.sim_pre_cmd:
            sim_pre_cmd = top_module.sim_pre_cmd
        else:
            sim_pre_cmd = ''

        if top_module.sim_post_cmd:
            sim_post_cmd = top_module.sim_post_cmd
        else:
            sim_post_cmd = ''

        makefile_text_2 = makefile_tmplt_2.substitute(
            sim_pre_cmd=sim_pre_cmd,
            sim_post_cmd=sim_post_cmd,
        )
        self.write(makefile_text_2)

