# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Steve Reinhardt

import m5
from m5.objects import *
m5.util.addToPath('../configs/common')

class MyCache(BaseCache):
    assoc = 2
    block_size = 64
    hit_latency = 2
    response_latency = 2
    mshrs = 10
    tgts_per_mshr = 5

class MyL1Cache(MyCache):
    is_top_level = True
    tgts_per_mshr = 20

cpu = DerivO3CPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                              MyL1Cache(size = '256kB'),
                              MyCache(size = '2MB'))
# @todo Note that the L2 latency here is unmodified and 2 cycles,
# should set hit latency and response latency to 20 cycles as for
# other scripts
cpu.clock = '2GHz'

system = System(cpu = cpu,
                physmem = SimpleMemory(),
                membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)

root = Root(full_system = False, system = system)
