[arch][arm64] change CACHE_LINE to 64 for cortex a53,57 and 72
#define PAGE_SIZE (1UL << PAGE_SIZE_SHIFT)
#define USER_PAGE_SIZE (1UL << USER_PAGE_SIZE_SHIFT)
+#if ARM64_CPU_CORTEX_A53 || ARM64_CPU_CORTEX_A57 || ARM64_CPU_CORTEX_A72
+#define CACHE_LINE 64
+#else
#define CACHE_LINE 32
-
+#endif
