remove FCLK_CLK0 from dac_test
-# Create processing_system7
-cell xilinx.com:ip:processing_system7:5.5 ps_0 {
- PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
-} {
- M_AXI_GP0_ACLK ps_0/FCLK_CLK0
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
- make_external {FIXED_IO, DDR}
- Master Disable
- Slave Disable
-} [get_bd_cells ps_0]
-
+# Create clk_wiz
cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
PRIMITIVE PLL
PRIM_IN_FREQ.VALUE_SRC USER
@@ -28,6 +15,20 @@ cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
clk_in1_n adc_clk_n_i
}
+# Create processing_system7
+cell xilinx.com:ip:processing_system7:5.5 ps_0 {
+ PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
+} {
+ M_AXI_GP0_ACLK pll_0/clk_out1
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
+ make_external {FIXED_IO, DDR}
+ Master Disable
+ Slave Disable
+} [get_bd_cells ps_0]
+
# Create dds_compiler
cell xilinx.com:ip:dds_compiler:6.0 dds_0 {
DDS_CLOCK_RATE 125
