chip/max32660/pwrseq_regs.h: Format with clang-format
BRANCH=none
TEST=none
Tricium: disable
@@ -172,21 +172,24 @@ typedef struct {
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \
- (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \
+ (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
+ << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \
LP_CTRL_OVR_0_9V \
Setting \
*/
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \
- (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \
+ (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
+ << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \
LP_CTRL_OVR_1_0V \
Setting \
*/
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \
- (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \
+ (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
+ << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \
LP_CTRL_OVR_1_1V \
Setting \
*/
@@ -379,7 +382,8 @@ typedef struct {
*/
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \
- ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \
+ ((uint32_t)(0x3FFFUL \
+ << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \
LP_WAKEFL_WAKEST \
\ \
\ \ \ Mask \
@@ -392,7 +396,8 @@ typedef struct {
*/
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \
- ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \
+ ((uint32_t)(0x3FFFUL \
+ << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \
LPWK_EN_WAKEEN \
\ \
\ \ \ Mask \
