[tb] Add wake up register and decoder in control registers
@@ -29,7 +29,8 @@ module ctrl_registers #(
// Control registers
output logic [DataWidth-1:0] tcdm_start_address_o,
output logic [DataWidth-1:0] tcdm_end_address_o,
- output logic [DataWidth-1:0] num_cores_o
+ output logic [DataWidth-1:0] num_cores_o,
+ output logic [NumCores-1:0] wake_up_o
);
import mempool_pkg::*;
@@ -49,12 +50,15 @@ module ctrl_registers #(
// [3:0]: tcdm_start_address (ro)
// [7:4]: tcdm_end_address (ro)
// [11:8]: num_cores (ro)
+ // [15:12]:wake_up (rw)
localparam logic [NumRegs-1:0][DataWidth-1:0] RegRstVal = '{
+ {DataWidth{1'b0}},
NumCores,
TCDMBaseAddr + TCDMSize,
TCDMBaseAddr
};
localparam logic [NumRegs-1:0][DataWidthInBytes-1:0] AxiReadOnly = '{
+ ReadWriteReg,
ReadOnlyReg,
ReadOnlyReg,
ReadOnlyReg
@@ -67,9 +71,12 @@ module ctrl_registers #(
logic [DataWidth-1:0] tcdm_start_address;
logic [DataWidth-1:0] tcdm_end_address;
logic [DataWidth-1:0] num_cores;
+ logic [DataWidth-1:0] wake_up;
+ logic [RegNumBytes-1:0] wr_active_d;
+ logic [RegNumBytes-1:0] wr_active_q;
axi_lite_regs #(
- .RegNumBytes (DataWidthInBytes * NumRegs),
+ .RegNumBytes (RegNumBytes ),
.AxiAddrWidth(AddrWidth ),
.AxiDataWidth(DataWidth ),
.AxiReadOnly (AxiReadOnly ),
@@ -81,11 +88,11 @@ module ctrl_registers #(
.rst_ni (rst_ni ),
.axi_req_i (axi_lite_slave_req_i ),
.axi_resp_o (axi_lite_slave_resp_o ),
- .wr_active_o(/* Unused */ ),
+ .wr_active_o(wr_active_d ),
.rd_active_o(/* Unused */ ),
.reg_d_i ('0 ),
.reg_load_i ('0 ),
- .reg_q_o ({num_cores, tcdm_end_address, tcdm_start_address})
+ .reg_q_o ({wake_up, num_cores, tcdm_end_address, tcdm_start_address})
);
/***************
@@ -96,4 +103,23 @@ module ctrl_registers #(
assign tcdm_end_address_o = tcdm_end_address;
assign num_cores_o = num_cores;
+ // converts 32 bit wake up to 256 bit
+ always_comb begin
+ wake_up_o = '0;
+ if (wr_active_q[15:12]) begin
+ if (wake_up < NumCores) begin
+ wake_up_o = 1 << wake_up;
+ end else if (wake_up == -1) begin
+ wake_up_o = '1;
+ end
+ end
+ end
+
+ // register to add +1 latency to the wr_active signal
+ always_ff @ (posedge clk_i) begin
+ if (clk_i == 1'b1) begin
+ wr_active_q <= wr_active_d;
+ end
+ end
+
endmodule : ctrl_registers
