set m_axi_awcache to 4'b0110 in axis_ram_writer
@@ -140,7 +140,7 @@ module axis_ram_writer #
assign m_axi_awlen = 4'd15;
assign m_axi_awsize = ADDR_SIZE;
assign m_axi_awburst = 2'b01;
- assign m_axi_awcache = 4'b1111;
+ assign m_axi_awcache = 4'b0110;
assign m_axi_awvalid = int_awvalid_reg;
assign m_axi_wid = int_awid_reg;
assign m_axi_wdata = int_wdata_wire[AXI_DATA_WIDTH-1:0];
