esp32c3/memprot: Correct the split line address calculation
@@ -42,6 +42,18 @@ extern "C" {
#define I_D_SPLIT_LINE_SHIFT 0x9
#define I_D_FAULT_ADDR_SHIFT 0x2
+typedef union {
+ struct {
+ uint32_t cat0 : 2;
+ uint32_t cat1 : 2;
+ uint32_t cat2 : 2;
+ uint32_t res0 : 8;
+ uint32_t splitaddr : 8;
+ uint32_t res1 : 10;
+ };
+ uint32_t val;
+} constrain_reg_fields_t;
+
static inline void memprot_ll_set_iram0_dram0_split_line_lock(void)
{
REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, 1);
@@ -54,9 +66,21 @@ static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void)
static inline void* memprot_ll_get_split_addr_from_reg(uint32_t regval, uint32_t base)
{
- return (void*)
- (base + ((regval & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M)
- >> (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S - I_D_SPLIT_LINE_SHIFT)));
+ constrain_reg_fields_t reg_val;
+ reg_val.val = regval;
+
+ uint32_t off = reg_val.splitaddr << 9;
+
+ if (reg_val.cat0 == 0x1 || reg_val.cat0 == 0x2) {
+ return (void *)(base + off);
+ } else if (reg_val.cat1 == 0x1 || reg_val.cat1 == 0x2) {
+ return (void *)(base + I_D_SRAM_SEGMENT_SIZE + off);
+ } else if (reg_val.cat2 == 0x1 || reg_val.cat2 == 0x2) {
+ return (void *)(base + (2 * I_D_SRAM_SEGMENT_SIZE) + off);
+ } else {
+ /* Either the register was not configured at all or incorrectly configured */
+ return NULL;
+ }
}
/* ******************************************************************************************************
