Simplify writeback pipeline muxing
I had been attempting to optimize the logic, but this is probably
unnecessary.
@@ -352,12 +352,11 @@ module writeback_stage(
// wb_rollback_en is derived combinatorially from the instruction
// that is about to retire, so this doesn't need to check
// wb_rollback_thread_idx like other places.
- unique case ({fx5_instruction_valid, ix_instruction_valid, dd_instruction_valid})
+ if (fx5_instruction_valid)
+ begin
//
// Floating point pipeline result
//
- 3'b100:
- begin
if (fx5_instruction.has_dest && !wb_rollback_en)
writeback_en_nxt = 1;
@@ -372,12 +371,11 @@ module writeback_stage(
writeback_reg_nxt = fx5_instruction.dest_reg;
writeback_last_subcycle_nxt = last_subcycle_mx;
end
-
+ else if (ix_instruction_valid)
+ begin
//
// Integer pipeline result
//
- 3'b010:
- begin
if (ix_instruction.branch
&& (ix_instruction.branch_type == BRANCH_CALL_OFFSET
|| ix_instruction.branch_type == BRANCH_CALL_REGISTER))
@@ -405,12 +403,11 @@ module writeback_stage(
writeback_reg_nxt = ix_instruction.dest_reg;
writeback_last_subcycle_nxt = last_subcycle_sx;
end
-
+ else if (dd_instruction_valid)
+ begin
//
// Memory pipeline result
//
- 3'b001:
- begin
writeback_en_nxt = dd_instruction.has_dest && !wb_rollback_en;
writeback_thread_idx_nxt = dd_thread_idx;
if (!dd_instruction.cache_control)
@@ -472,10 +469,6 @@ module writeback_stage(
writeback_reg_nxt = dd_instruction.dest_reg;
writeback_last_subcycle_nxt = last_subcycle_dd;
end
-
- default:
- ;
- endcase
end
always_ff @(posedge clk)
