Use HasHierarchicalBusTopology mixin
@@ -22,6 +22,7 @@ import freechips.rocketchip.util.{DontTouch}
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
*/
class System(implicit p: Parameters) extends Subsystem
+ with HasHierarchicalBusTopology
with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort
@@ -29,25 +30,6 @@ class System(implicit p: Parameters) extends Subsystem
with HasPeripheryBootROM
{
override lazy val module = new SystemModule(this)
-
- // The sbus masters the cbus; here we convert TL-UH -> TL-UL
- sbus.crossToBus(cbus, NoCrossing)
-
- // The cbus masters the pbus; which might be clocked slower
- cbus.crossToBus(pbus, SynchronousCrossing())
-
- // The fbus masters the sbus; both are TL-UH or TL-C
- FlipRendering { implicit p =>
- sbus.crossFromBus(fbus, SynchronousCrossing())
- }
-
- // The sbus masters the mbus; here we convert TL-C -> TL-UH
- private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
- private val (in, out, halt) = coherenceManager(this)
- if (nBanks != 0) {
- sbus.coupleTo("coherence_manager") { in :*= _ }
- mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
- }
}
/**
