aha, fixed clearing request done bit. tests passed
@@ -281,6 +281,9 @@ void process_can(uint8_t can_number) {
puts("process CAN TX\n");
#endif
+ // check for empty mailbox
+ CAN_FIFOMailBox_TypeDef to_send;
+ if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
// add successfully transmitted message to my fifo
if ((CAN->TSR & CAN_TSR_RQCP0) == CAN_TSR_RQCP0) {
can_txd_cnt += 1;
@@ -307,12 +310,10 @@ void process_can(uint8_t can_number) {
}
// clear interrupt
+ // careful, this can also be cleared by requesting a transmission
CAN->TSR |= CAN_TSR_RQCP0;
}
- // check for empty mailbox
- CAN_FIFOMailBox_TypeDef to_send;
- if ((CAN->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
if (pop(can_queues[bus_number], &to_send)) {
can_tx_cnt += 1;
// only send if we have received a packet
