SLW: Add opal_slw_set_reg support for power9
This OPAL call is made from Linux to OPAL to configure values in
various SPRs after wakeup from a deep idle state.
#include <libfdt/libfdt.h>
#include <opal-api.h>
+#include <p9_stop_api.H>
#include <p8_pore_table_gen_api.H>
#include <sbe_xip_image.h>
@@ -1402,15 +1403,26 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
struct cpu_thread *c = find_cpu_by_pir(cpu_pir);
struct proc_chip *chip;
- void *image;
int rc;
- int i;
- int spr_is_supported = 0;
assert(c);
chip = get_chip(c->chip_id);
assert(chip);
- image = (void *) chip->slw_base;
+
+ if (proc_gen == proc_gen_p9) {
+ if (!chip->homer_base) {
+ log_simple_error(&e_info(OPAL_RC_SLW_REG),
+ "SLW: HOMER base not set %x\n",
+ chip->id);
+ return OPAL_INTERNAL_ERROR;
+ }
+ rc = p9_stop_save_cpureg((void *)chip->homer_base,
+ sprn, val, cpu_pir);
+
+ } else if (proc_gen == proc_gen_p8) {
+ int spr_is_supported = 0;
+ void *image;
+ int i;
/* Check of the SPR is supported by libpore */
for (i = 0; i < SLW_SPR_REGS_SIZE ; i++) {
@@ -1425,18 +1437,26 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
c->pir);
return OPAL_UNSUPPORTED;
}
-
- rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, sprn,
- val, cpu_get_core_index(c),
+ image = (void *)chip->slw_base;
+ rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
+ sprn, val,
+ cpu_get_core_index(c),
cpu_get_thread_index(c));
+ } else {
+ log_simple_error(&e_info(OPAL_RC_SLW_REG),
+ "SLW: proc_gen not supported\n");
+ return OPAL_UNSUPPORTED;
+
+ }
if (rc) {
log_simple_error(&e_info(OPAL_RC_SLW_REG),
- "SLW: Failed to set spr for CPU %x\n",
- c->pir);
+ "SLW: Failed to set spr %llx for CPU %x, RC=0x%x\n",
+ sprn, c->pir, rc);
return OPAL_INTERNAL_ERROR;
}
-
+ prlog(PR_DEBUG, "SLW: restore spr:0x%llx on c:0x%x with 0x%llx\n",
+ sprn, c->pir, val);
return OPAL_SUCCESS;
}
