board/hyperdebug: Increase clock speed
Optimize gpio edge detection latency, by increasing CPU clock speed from
16Mhz to 104MHz.
Tested-by: Jes Klinke
#define CONFIG_LTO
-/* 48 MHz SYSCLK clock frequency */
-#define CPU_CLOCK 48000000
-
/* Configure the flash */
#undef CONFIG_RO_SIZE
#undef CONFIG_FW_PSTATE_OFF
#else /* !SECTION_IS_RO */
+/*
+ * PLL configuration. Freq = STM32_HSE_CLOCK or HSI (16MHz) * N / M / R.
+ *
+ * In our case, 16MHz * 13 / 1 / 2 = 104MHz.
+ */
+
+#undef STM32_PLLM
+#undef STM32_PLLN
+#undef STM32_PLLR
+#define STM32_PLLM 1
+#define STM32_PLLN 13
+#define STM32_PLLR 2
+
+#define STM32_USE_PLL
+
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_ROM_BASE 0x0
