set writer_0/AXI_ID_WIDTH to 3 in adc_test
@@ -173,6 +173,7 @@ cell xilinx.com:ip:axis_dwidth_converter conv_0 {
# Create axis_ram_writer
cell pavel-demin:user:axis_ram_writer writer_0 {
ADDR_WIDTH 16
+ AXI_ID_WIDTH 3
} {
S_AXIS conv_0/M_AXIS
M_AXI ps_0/S_AXI_ACP
