Fixed decoding of MASK register
@@ -905,7 +905,7 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REG_ENCODING_REG:
{
ZYDIS_ASSERT(info->details.modrm.isDecoded);
- uint8_t value = info->details.modrm.reg | (context->cache.R << 3);
+ uint8_t value = info->details.modrm.reg;
// R' only exists for EVEX and MVEX. No encoding check needed
switch (registerClass)
{
@@ -914,7 +914,10 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REGCLASS_ZMM:
value |= (context->cache.R2 << 4);
break;
+ case ZYDIS_REGCLASS_MASK:
+ break;
default:
+ value |= (context->cache.R << 3);
break;
}
return value;
@@ -935,7 +938,7 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REG_ENCODING_RM:
{
ZYDIS_ASSERT(info->details.modrm.isDecoded);
- uint8_t value = info->details.modrm.rm | (context->cache.B << 3);
+ uint8_t value = info->details.modrm.rm;
// We have to check the instruction-encoding, because the extension by X is only valid
// for EVEX and MVEX instructions
if ((info->encoding == ZYDIS_INSTRUCTION_ENCODING_EVEX) ||
@@ -948,7 +951,10 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REGCLASS_ZMM:
value |= (context->cache.X << 4);
break;
+ case ZYDIS_REGCLASS_MASK:
+ break;
default:
+ value |= (context->cache.B << 3);
break;
}
}
