stm32/boards/NUCLEO_F767ZI: Fix up comments about HCLK computation.
#define MICROPY_BOARD_EARLY_INIT NUCLEO_F767ZI_board_early_init
void NUCLEO_F767ZI_board_early_init(void);
-// HSE is 25MHz
-// VCOClock = HSE * PLLN / PLLM = 25 MHz * 432 / 25 = 432 MHz
-// SYSCLK = VCOClock / PLLP = 432 MHz / 2 = 216 MHz
-// USB/SDMMC/RNG Clock = VCOClock / PLLQ = 432 MHz / 9 = 48 MHz
+// HSE is 8MHz
#define MICROPY_HW_CLK_PLLM (4)
#define MICROPY_HW_CLK_PLLN (216)
#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
#define MICROPY_HW_CLK_PLLQ (9)
-
-// From the reference manual, for 2.7V to 3.6V
-// 151-180 MHz => 5 wait states
-// 181-210 MHz => 6 wait states
-// 211-216 MHz => 7 wait states
-#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states
+#define MICROPY_HW_FLASH_LATENCY (FLASH_LATENCY_7) // 210-216 MHz needs 7 wait states
// UART config
#define MICROPY_HW_UART2_TX (pin_D5)
