foramt drv_clk
-#include "project.h"
#include "binary.h"
#include "defines.h"
+#include "project.h"
// the clock is already set, we turn pll off and set a new multiplier
-void setclock(void)
-{
+void setclock(void) {
// turn on HSI
RCC->CR |= 1;
// wait for HSI ready
- while((RCC->CR & RCC_CR_HSIRDY) == 0)
- {
+ while ((RCC->CR & RCC_CR_HSIRDY) == 0) {
}
// set clock source HSI
RCC->CFGR &= (0xFFFFFFFC);
// wait for switch
- while( (RCC->CFGR&B00001100) )
- {
-
+ while ((RCC->CFGR & B00001100)) {
}
// turn pll off
RCC->CR &= (uint32_t)0xFEFFFFFF;
- while((RCC->CR & RCC_CR_PLLRDY) != 0)
- {
+ while ((RCC->CR & RCC_CR_PLLRDY) != 0) {
}
//reset pll settings
@@ -41,8 +36,7 @@ void setclock(void)
//PLL on
RCC->CR |= RCC_CR_PLLON;
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
+ while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
}
//set PLL as source
// RCC->CFGR&=(0xFFFFFF|B11111110);
@@ -54,14 +48,12 @@ void setclock(void)
//wait until PLL is the clock
#ifdef ENABLE_OVERCLOCK
// only if overclocked as it is redundant
- while( (RCC->CFGR&B00001100) != B00001000 )
- {
+ while ((RCC->CFGR & B00001100) != B00001000) {
}
#endif
}
-void clk_init(void)
-{
+void clk_init(void) {
// reset clock to default values
// sets clock to 48Mhz
@@ -74,7 +66,4 @@ void clk_init(void)
// set clock to 64Mhz (PLL max multiplier)
setclock();
#endif
-
-
}
-
