remove sync and add level in axis_gate_controller
@@ -12,12 +12,11 @@ module axis_gate_controller
input wire s_axis_tvalid,
output wire [31:0] poff,
- output wire sync,
+ output wire [15:0] level,
output wire dout
);
reg int_tready_reg, int_tready_next;
- reg int_sync_reg, int_sync_next;
reg int_dout_reg, int_dout_next;
reg int_enbl_reg, int_enbl_next;
reg [31:0] int_cntr_reg, int_cntr_next;
@@ -28,7 +27,6 @@ module axis_gate_controller
if(~aresetn)
begin
int_tready_reg <= 1'b0;
- int_sync_reg <= 1'b0;
int_dout_reg <= 1'b0;
int_enbl_reg <= 1'b0;
int_cntr_reg <= 32'd0;
@@ -37,7 +35,6 @@ module axis_gate_controller
else
begin
int_tready_reg <= int_tready_next;
- int_sync_reg <= int_sync_next;
int_dout_reg <= int_dout_next;
int_enbl_reg <= int_enbl_next;
int_cntr_reg <= int_cntr_next;
@@ -48,7 +45,6 @@ module axis_gate_controller
always @*
begin
int_tready_next = int_tready_reg;
- int_sync_next = int_sync_reg;
int_dout_next = int_dout_reg;
int_enbl_next = int_enbl_reg;
int_cntr_next = int_cntr_reg;
@@ -66,18 +62,17 @@ module axis_gate_controller
begin
int_cntr_next = int_cntr_reg + 1'b1;
- if(int_cntr_reg == int_data_reg[31:0])
+ if(int_cntr_reg == 32'd0)
begin
- int_sync_next = 1'b1;
int_dout_next = 1'b1;
end
- if(int_cntr_reg == int_data_reg[63:32])
+ if(int_cntr_reg == int_data_reg[31:0])
begin
int_dout_next = 1'b0;
end
- if(int_cntr_reg == int_data_reg[95:64])
+ if(int_cntr_reg == int_data_reg[63:32])
begin
int_enbl_next = 1'b0;
end
@@ -87,16 +82,11 @@ module axis_gate_controller
begin
int_tready_next = 1'b0;
end
-
- if(int_sync_reg)
- begin
- int_sync_next = 1'b0;
- end
end
assign s_axis_tready = int_tready_reg;
- assign poff = int_data_reg[127:96];
- assign sync = int_sync_reg;
+ assign poff = int_data_reg[95:64];
+ assign level = int_data_reg[111:96];
assign dout = int_dout_reg;
endmodule
