[firechip] Remove unneeded HasDefaultBusConfiguration
@@ -14,29 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
-/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */
-trait HasDefaultBusConfiguration {
- this: BaseSubsystem =>
- // The sbus masters the cbus; here we convert TL-UH -> TL-UL
- sbus.crossToBus(cbus, NoCrossing)
-
- // The cbus masters the pbus; which might be clocked slower
- cbus.crossToBus(pbus, SynchronousCrossing())
-
- // The fbus masters the sbus; both are TL-UH or TL-C
- FlipRendering { implicit p =>
- sbus.crossFromBus(fbus, SynchronousCrossing())
- }
-
- // The sbus masters the mbus; here we convert TL-C -> TL-UH
- private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
- private val (in, out, halt) = coherenceManager(this)
- if (nBanks != 0) {
- sbus.coupleTo("coherence_manager") { in :*= _ }
- mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
- }
-}
-
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
* TracerV endpoint can match on.
*/
