connect packetizer reset signal to DIO0_N in adc_recorder
@@ -36,6 +36,14 @@ cell xilinx.com:ip:proc_sys_reset rst_0 {} {
ext_reset_in const_0/dout
}
+# GPIO
+
+# Delete input/output port
+delete_bd_objs [get_bd_ports exp_n_tri_io]
+
+# Create output port
+create_bd_port -dir O -from 7 -to 0 exp_n_tri_io
+
# ADC
# Create axis_red_pitaya_adc
@@ -90,6 +98,16 @@ cell pavel-demin:user:port_slicer slice_4 {
din cfg_0/cfg_data
}
+# Create xlconcat
+cell xilinx.com:ip:xlconcat concat_0 {
+ NUM_PORTS 2
+ IN0_WIDTH 1
+ IN1_WIDTH 7
+} {
+ In0 slice_2/dout
+ dout exp_n_tri_io
+}
+
# Create axis_broadcaster
cell xilinx.com:ip:axis_broadcaster bcast_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
