[arch][riscv] stub out arch_enter_uspace for riscv
Copied implementation from ARM and then stubbed it out.
#include <lk/trace.h>
#include <lk/debug.h>
#include <stdint.h>
+#include <stdlib.h>
#include <arch/riscv.h>
#include <arch/ops.h>
#include <arch/mp.h>
@@ -108,6 +109,41 @@ void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3
PANIC_UNIMPLEMENTED;
}
+#if RISCV_S_MODE
+/* switch to user mode, set the user stack pointer to user_stack_top, get into user space */
+void arch_enter_uspace(vaddr_t entry_point, vaddr_t user_stack_top) {
+ DEBUG_ASSERT(IS_ALIGNED(user_stack_top, 8));
+
+ thread_t *ct = get_current_thread();
+
+ vaddr_t kernel_stack_top = (uintptr_t)ct->stack + ct->stack_size;
+ kernel_stack_top = ROUNDDOWN(kernel_stack_top, 8);
+
+ PANIC_UNIMPLEMENTED;
+
+#if 0
+
+ uint32_t spsr = CPSR_MODE_USR;
+ spsr |= (entry_point & 1) ? CPSR_THUMB : 0;
+
+ arch_disable_ints();
+
+ asm volatile(
+ "ldmia %[ustack], { sp }^;"
+ "msr spsr, %[spsr];"
+ "mov sp, %[kstack];"
+ "movs pc, %[entry];"
+ :
+ : [ustack]"r"(&user_stack_top),
+ [kstack]"r"(kernel_stack_top),
+ [entry]"r"(entry_point),
+ [spsr]"r"(spsr)
+ : "memory");
+#endif
+ __UNREACHABLE;
+}
+#endif
+
/* unimplemented cache operations */
#if RISCV_NO_CACHE_OPS
void arch_disable_cache(uint flags) { }
