[snitch] Make ro-cache's address region ports packed arrays
@@ -35,8 +35,8 @@ module snitch_read_only_cache #(
input logic enable_i,
input logic flush_valid_i,
output logic flush_ready_o,
- input logic [AxiAddrWidth-1:0] start_addr_i [NrAddrRules],
- input logic [AxiAddrWidth-1:0] end_addr_i [NrAddrRules],
+ input logic [NrAddrRules-1:0][AxiAddrWidth-1:0] start_addr_i,
+ input logic [NrAddrRules-1:0][AxiAddrWidth-1:0] end_addr_i,
input slv_req_t axi_slv_req_i,
output slv_rsp_t axi_slv_rsp_o,
output mst_req_t axi_mst_req_o,
