hal: Fix max value for clkdiv_pre in ESP32-S3 SPI master clock config
@@ -676,8 +676,8 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
if (pre <= 0) {
pre = 1;
}
- if (pre > 8192) {
- pre = 8192;
+ if (pre > 16) {
+ pre = 16;
}
errval = abs(spi_ll_freq_for_pre_n(fapb, pre, n) - hz);
if (bestn == -1 || errval <= besterr) {
