disable TREADY for FIR filter in sdr_transceiver/rx.tcl
@@ -174,7 +174,6 @@ cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
CLOCK_FREQUENCY 125
OUTPUT_ROUNDING_MODE Convergent_Rounding_to_Even
OUTPUT_WIDTH 25
- M_DATA_HAS_TREADY true
HAS_ARESETN true
} {
S_AXIS_DATA conv_0/M_AXIS
