replace xlslice with port_slicer in scanner/block_design.tcl
@@ -70,70 +70,70 @@ cell pavel-demin:user:axi_cfg_register:1.0 cfg_0 {
AXI_DATA_WIDTH 32
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_1 {
DIN_WIDTH 416 DIN_FROM 0 DIN_TO 0
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_2 {
DIN_WIDTH 416 DIN_FROM 1 DIN_TO 1
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_3 {
DIN_WIDTH 416 DIN_FROM 2 DIN_TO 2
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_4 {
DIN_WIDTH 416 DIN_FROM 3 DIN_TO 3
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_5 {
DIN_WIDTH 416 DIN_FROM 23 DIN_TO 16
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_6 {
DIN_WIDTH 416 DIN_FROM 31 DIN_TO 24
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_7 {
DIN_WIDTH 416 DIN_FROM 127 DIN_TO 32
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_8 {
DIN_WIDTH 416 DIN_FROM 223 DIN_TO 128
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_9 {
DIN_WIDTH 416 DIN_FROM 319 DIN_TO 224
} {
din cfg_0/cfg_data
}
-# Create xlslice
+# Create port_slicer
cell pavel-demin:user:port_slicer:1.0 slice_10 {
DIN_WIDTH 416 DIN_FROM 415 DIN_TO 320
} {
