Core(A): Fixed __get_CP64 and __set_CP64 for IAR.
The rsr/wsr intrinsics does not work for 64-bit registers.
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
- #define __get_CP64(cp, op1, RT, CRm) \
- ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRm))
+ #define __get_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
- #define __set_CP64(cp, op1, RT, CRm) \
- (__arm_wsr("p" # cp ":" # op1 ":c" # CRm, (RT)))
+ #define __set_CP64(cp, op1, Rt, CRm) \
+ __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
