remove FCLK_CLK0 from bare_metal_test
+# Create clk_wiz
+cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
+ PRIMITIVE PLL
+ PRIM_IN_FREQ.VALUE_SRC USER
+ PRIM_IN_FREQ 125.0
+ PRIM_SOURCE Differential_clock_capable_pin
+ CLKOUT1_USED true
+ CLKOUT1_REQUESTED_OUT_FREQ 125.0
+ USE_RESET false
+} {
+ clk_in1_p adc_clk_p_i
+ clk_in1_n adc_clk_n_i
+}
+
# Create processing_system7
cell xilinx.com:ip:processing_system7:5.5 ps_0 {
PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
} {
- M_AXI_GP0_ACLK ps_0/FCLK_CLK0
+ M_AXI_GP0_ACLK pll_0/clk_out1
}
# Create all required interconnections
@@ -12,21 +26,12 @@ apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
Slave Disable
} [get_bd_cells ps_0]
-# Create proc_sys_reset
-cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_0
-# Create clk_wiz
-cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
- PRIMITIVE PLL
- PRIM_IN_FREQ.VALUE_SRC USER
- PRIM_IN_FREQ 125.0
- PRIM_SOURCE Differential_clock_capable_pin
- CLKOUT1_USED true
- CLKOUT1_REQUESTED_OUT_FREQ 125.0
- USE_RESET false
-} {
- clk_in1_p adc_clk_p_i
- clk_in1_n adc_clk_n_i
+# Create proc_sys_reset
+cell xilinx.com:ip:proc_sys_reset:5.0 rst_0 {} {
+ ext_reset_in const_0/dout
}
# ADC
@@ -43,7 +48,7 @@ cell pavel-demin:user:axis_red_pitaya_adc:2.0 adc_0 {} {
cell xilinx.com:ip:c_counter_binary:12.0 cntr_0 {
Output_Width 32
} {
- CLK ps_0/FCLK_CLK0
+ CLK pll_0/clk_out1
}
# Create xlslice
