ATTN: Enable flush instruction cache bit in HID register
In P9, we have to enable "flush the instruction cache" bit along with
"attn instruction support" bit to trigger attention.
#define SPR_HID0_POWER8_HILE PPC_BIT(19)
#define SPR_HID0_POWER9_HILE PPC_BIT(4)
#define SPR_HID0_POWER8_ENABLE_ATTN PPC_BIT(31)
-#define SPR_HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
+#define SPR_HID0_POWER9_ENABLE_ATTN (PPC_BIT(2) | PPC_BIT(3))
#define SPR_HID0_POWER9_RADIX PPC_BIT(8)
/* PVR bits */
