[axi] Ignore all assertions in Verilator
@@ -367,7 +367,6 @@ module axi_id_remap #(
assert ($bits(mst_req_o.ar.id) == AxiMstPortIdWidth);
assert ($bits(mst_resp_i.r.id) == AxiMstPortIdWidth);
end
- `endif
default disable iff (!rst_ni);
assert property (@(posedge clk_i) slv_req_i.aw_valid && slv_resp_o.aw_ready
|-> mst_req_o.aw_valid && mst_resp_i.aw_ready);
@@ -383,6 +382,7 @@ module axi_id_remap #(
|=> mst_req_o.ar_valid && $stable(mst_req_o.ar.id));
assert property (@(posedge clk_i) mst_req_o.aw_valid && !mst_resp_i.aw_ready
|=> mst_req_o.aw_valid && $stable(mst_req_o.aw.id));
+ `endif
// pragma translate_on
endmodule
