replace 1'd0 with 1'b0 in axi_sts_register.v
@@ -93,10 +93,9 @@ module axi_sts_register #
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
- // Patch for opt_design errors due to trimming of unused paths
+ assign s_axi_awready = 1'b0;
+ assign s_axi_wready = 1'b0;
assign s_axi_bresp = 2'd0;
- assign s_axi_awready = 1'd0;
- assign s_axi_bvalid = 1'd0;
- assign s_axi_wready = 1'd0;
+ assign s_axi_bvalid = 1'b0;
endmodule
