stm32: add stm32l431 ec in chip/stm32 : watchdog
stm32l431 related driver: watchdog.
The stm32l476g-eval is the only board which would be impacted.
BRANCH=main
TEST=make buildall
* value large enough that we reload before the worst-case watchdog delay
* (fastest LSI clock).
*/
+#ifdef CHIP_FAMILY_STM32L4
+#define LSI_CLOCK 34000
+#else
#define LSI_CLOCK 56000
+#endif
+
+/* The timeout value is multiplied by 1000 to be converted into ms */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_CLOCK)
/*
* Use largest prescaler divider = /256. This gives a worst-case watchdog
* clock of 56000/256 = 218 Hz, and a maximum timeout period of (4095/218 Hz) =
* 18.7 sec.
+ *
+ * For STM32L4, Max LSI is 34000. Watchdog clock is 34000 / 256 = 132Hz,
+ * Max timeout = 4095 / 132 = 31 sec.
*/
#define IWDG_PRESCALER 6
#define IWDG_PRESCALER_DIV (4 << IWDG_PRESCALER)
@@ -44,6 +54,12 @@ DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
int watchdog_init(void)
{
+#ifdef CHIP_FAMILY_STM32L4
+ timestamp_t tickstart, ticknow;
+
+ /* Enable watchdog registers */
+ STM32_IWDG_KR = STM32_IWDG_KR_START;
+#endif
/* Unlock watchdog registers */
STM32_IWDG_KR = STM32_IWDG_KR_UNLOCK;
@@ -53,7 +69,20 @@ int watchdog_init(void)
/* Set the reload value of the watchdog counter */
STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS *
(LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000);
+#ifdef CHIP_FAMILY_STM32L4
+ tickstart = get_time();
+ /* Wait for SR */
+ while (STM32_IWDG_SR != 0x00u) {
+ ticknow = get_time();
+ if ((ticknow.val - tickstart.val) >
+ HAL_IWDG_DEFAULT_TIMEOUT * 1000) {
+ return EC_ERROR_TIMEOUT;
+ }
+ }
+ /* Reload the watchdog */
+ STM32_IWDG_KR = STM32_IWDG_KR_RELOAD;
+#else
/* Start the watchdog (and re-lock registers) */
STM32_IWDG_KR = STM32_IWDG_KR_START;
@@ -80,7 +109,7 @@ int watchdog_init(void)
* except in case of low-power mode entry.
*/
-
+#endif
#ifdef CONFIG_WATCHDOG_HELP
/* Use a harder timer to warn about an impending watchdog reset */
hwtimer_setup_watchdog();
