chip/it83xx/spi.c: Format with clang-format
BRANCH=none
TEST=none
/* Max data size for a version 3 request/response packet. */
#define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE
-#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \
- EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
+#define SPI_MAX_RESPONSE_SIZE \
+ (SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH)
static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = {
EC_SPI_PROCESSING,
@@ -145,8 +145,8 @@ static void spi_send_response_packet(struct host_packet *pkt)
/* Append our past-end byte, which we reserved space for. */
for (i = 0; i < EC_SPI_PAST_END_LENGTH; i++)
- ((uint8_t *)pkt->response)[pkt->response_size + i]
- = EC_SPI_PAST_END;
+ ((uint8_t *)pkt->response)[pkt->response_size + i] =
+ EC_SPI_PAST_END;
tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH +
EC_SPI_PAST_END_LENGTH;
@@ -327,8 +327,8 @@ static void spi_init(void)
* bit3 : Rx FIFO1 will not be overwrited once it's full.
* bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high.
*/
- IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC
- | IT83XX_SPI_RXFAR;
+ IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC |
+ IT83XX_SPI_RXFAR;
/*
* Interrupt mask register (0b:Enable, 1b:Mask)
* bit5 : Rx byte reach interrupt mask
@@ -395,8 +395,7 @@ static enum ec_status _spi_get_protocol_info(struct host_cmd_handler_args *args)
return EC_SUCCESS;
}
-DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO,
- _spi_get_protocol_info,
+DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, _spi_get_protocol_info,
EC_VER_MASK(0));
enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args)
