used register slice for NVMe axi_interconnect_2, to improve timing
@@ -201,6 +201,8 @@ CONFIG.NUM_MI {2} \
CONFIG.NUM_SI {2} \
CONFIG.S00_HAS_DATA_FIFO {2} \
CONFIG.S01_HAS_DATA_FIFO {2} \
+CONFIG.M00_HAS_REGSLICE {1} \
+CONFIG.M01_HAS_REGSLICE {1} \
CONFIG.STRATEGY {2} \
] $axi_interconnect_2 >> $log_file
