RAA489000: Organize header file
Put register definitions in ascending order and note some definitions
are no longer applicable.
BRANCH=None
TEST=make -j buildall
/* Vendor registers */
#define RAA489000_TCPC_SETTING1 0x80
+#define RAA489000_VBUS_CURRENT_TARGET 0x92
+#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94
#define RAA489000_TYPEC_SETTING1 0xC0
#define RAA489000_PD_PHYSICAL_SETTING1 0xE0
#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8
-#define RAA489000_VBUS_CURRENT_TARGET 0x92
-#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94
+/* TCPC_SETTING_1 */
+#define RAA489000_TCPCV1_0_EN BIT(0)
+#define RAA489000_TCPC_PWR_CNTRL BIT(4)
+/* VBUS_CURRENT_TARGET */
#define RAA489000_VBUS_CURRENT_TARGET_VALUE 0x61 /* 3.104A */
+
+/* VBUS_OCP_UV_THRESHOLD */
/* Detect voltage level of overcurrent protection during Sourcing VBUS */
#define RAA489000_OCP_THRESHOLD_VALUE 0x00BE /* 4.75V */
+/* TYPEC_SETTING1 - only older silicon */
/* Enables for reverse current protection */
#define RAA489000_SETTING1_IP2_EN BIT(9)
#define RAA489000_SETTING1_IP1_EN BIT(8)
/* CC debounce enable */
#define RAA489000_SETTING1_CC_DB_EN BIT(0)
-/* TCPC_SETTING_1 */
-#define RAA489000_TCPCV1_0_EN BIT(0)
-#define RAA489000_TCPC_PWR_CNTRL BIT(4)
-
/* PD_PHYSICAL_SETTING_1 */
#define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9)
#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8)
