fix axis_pps_counter
@@ -17,11 +17,23 @@ module axis_pps_counter #
output wire m_axis_tvalid
);
- reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
- reg int_enbl_reg, int_enbl_next;
- reg [2:0] int_data_reg;
-
- wire int_edge_wire;
+ reg [CNTR_WIDTH-1:0] int_cntr_reg;
+ reg int_enbl_reg;
+ reg [1:0] int_data_reg;
+
+ wire int_edge_wire, int_pps_wire;
+
+ xpm_cdc_single #(
+ .DEST_SYNC_FF(4),
+ .INIT_SYNC_FF(0),
+ .SRC_INPUT_REG(0),
+ .SIM_ASSERT_CHK(0)
+ ) cdc_0 (
+ .src_in(pps_data),
+ .src_clk(),
+ .dest_out(int_pps_wire),
+ .dest_clk(aclk)
+ );
always @(posedge aclk)
begin
@@ -29,33 +41,17 @@ module axis_pps_counter #
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
- int_data_reg <= 3'd0;
+ int_data_reg <= 2'd0;
end
else
begin
- int_cntr_reg <= int_cntr_next;
- int_enbl_reg <= int_enbl_next;
- int_data_reg <= {int_data_reg[1:0], pps_data};
+ int_cntr_reg <= int_edge_wire ? {(CNTR_WIDTH){1'b0}} : int_cntr_reg + 1'b1;
+ int_enbl_reg <= int_edge_wire ? 1'b1 : int_enbl_reg;
+ int_data_reg <= {int_data_reg[0], ~int_pps_wire};
end
end
- assign int_edge_wire = ~int_data_reg[2] & int_data_reg[1];
-
- always @*
- begin
- int_cntr_next = int_cntr_reg + 1'b1;
- int_enbl_next = int_enbl_reg;
-
- if(~int_enbl_reg & int_edge_wire)
- begin
- int_enbl_next = 1'b1;
- end
-
- if(int_edge_wire)
- begin
- int_cntr_next = {(CNTR_WIDTH){1'b0}};
- end
- end
+ assign int_edge_wire = int_data_reg[1] & ~int_data_reg[0];
assign m_axis_tdata = {{(AXIS_TDATA_WIDTH-CNTR_WIDTH){1'b0}}, int_cntr_reg};
assign m_axis_tvalid = int_enbl_reg & int_edge_wire;
