Add a little more to the human-readable docs based on hwtest and rnndb.
@@ -26,7 +26,76 @@ MMIO registers
Interrupts
==========
-.. todo:: write me
+The PGRAPH registers dealing with interrupts are:
+
+.. reg:: 32 nv3-pgraph-intr Interrupt status
+
+ Status of interrupts generated by PGRAPH. On read, returns 1 for bits
+ corresponding to pending interrupts. On write, if 1 is written to a bit,
+ its interrupt gets cleared, if 0 is written nothing happens.
+
+ - bit 0: INVALID - something was wrong with the submitted method. Detailed
+ status is available in the INVALID register. Clearing this bit will also
+ clear the INVALID register. In turn, clearing the INVALID register will
+ clear this bit.
+ - bit 4: CONTEXT_SWITCH - a CTX_SWITCH method was submitted and the channel
+ id and/or SUBCONTEXT_ID is different from the current one.
+ - bit 8: VBLANK - the vertical blanking period has started on PFB. This
+ is really PFB's interrupt. It is delivered to a different PMC line than
+ other PGRAPH interrupts. See :ref:`NV1 PFB <nv1-pfb>` for details.
+ - bit 12: XY_RANGE - an X or Y coordinate used for rendering was out of the
+ -0x8000..0x7fff range supported by the rasterizer
+ - bit 16: MISSING_METHOD - the final method to do an operation was submitted
+ without first submitting other required methods
+ - bit 20: MISSING_FORMAT - the format of the destination surface is not
+ supported by PGRAPH.
+ - bit 24: CLIP_SOFTWARE - a drawing operation was attempted with SOFTWARE bit
+ set in CLIPRECT_CTRL.
+ - bit 28: NOTIFY - a method on which notify interrupt was requested has been
+ executed
+
+.. reg:: 32 nv3-pgraph-intr-en Interrupt enable
+
+ Interrupt enable bitmask. Set to enable, clear to disable. Interrupts that
+ are masked will still show up in INTR when they're triggered, but won't
+ cause the PGRAPH or PFB interrupt line to go active. Has same bitfields
+ as INTR.
+
+Interrupts other than VBLANK are delivered to PMC interrupt line 12. VBLANK
+interrupt is delivered to PMC interrupt line 24.
+
+The INVALID interrupt is further controlled by these registers:
+
+.. reg:: 32 nv3-pgraph-invalid INVALID interrupt status
+
+ Status of INVALID subinterrupts. Works like INTR. Clearing this register
+ will also clear the INVALID bit in INTR register. In turn, clearing INVALID
+ bit in INTR will also clear this register.
+
+ - bit 0: INVALID_METHOD - the method that was submitted does not exist
+ - bit 4: INVALID_VALUE - the method was submitted with invalid parameter
+ - bit 8: INVALID_NOTIFY - a NOTIFY method was submitted, but NOTIFY_VALID
+ was not set in graph object options
+ - bit 12: DOUBLE_NOTIFY - a NOTIFY method was submitted with NOTIFY_PENDING
+ already set
+ - bit 16: CTXSW_NOTIFY - a CTX_SWITCH method was submitted with NOTIFY_PENDING
+ set
+
+.. reg:: 32 nv3-pgraph-invalid-en INVALID interrupt enable
+
+ INVALID interrupt enable bitmask. Set to enable, clear to disable. Same
+ bitfields as INVALID. If any interrupt active in INVALID is also enabled
+ here, interrupt line to PMC will be active. Note that this register does
+ *not* affect triggering the INVALID bit in INTR and the interrupt status
+ from INTR&INTR_EN will be effectively ORed with INVALID&INVALID_EN. Thus
+ the contents of INVALID_EN will only matter when INTR_EN.INVALID is set
+ to 0.
+
+The INTR and INVALID registers are special and can be written by host even
+if ACCESS.HOST is not set.
+
+Note that interrupts that are disabled will still cause PGRAPH to halt and
+disable FIFO/HOST bits in ACCESS.
Method submission
