added reset constrain for PCIe RC
############################################################################
##
-set_false_path -from [get_pins nvme_reset_n_q_reg/C] -to [get_pins {a0/nvme_top_i/axi_pcie3_1/inst/pcie3_ip_i/inst/gt_top_i/phy_rst_i/rrst_n_r_reg[?]/CLR}]
-
+set_false_path -from [get_ports sys_rst_n]
# ------------------------------
# Pin Locations & I/O Standards
# ------------------------------
