chip/stm32/adc-stm32l4.c: Format with clang-format
BRANCH=none
TEST=none
@@ -51,15 +51,15 @@ uint8_t adc1_initialized;
#endif
static const struct dma_option dma_continuous = {
- STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+ STM32_DMAC_ADC,
+ (void *)&STM32_ADC_DR,
STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT |
STM32_DMA_CCR_CIRC,
};
static const struct adc_profile_t profile = {
/* Sample all channels continuously using DMA */
- .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD |
- STM32_ADC_CFGR1_CONT |
+ .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT |
STM32_ADC_CFGR1_DMACFG,
.cfgr2_reg = 0,
.smpr_reg = CONFIG_ADC_SAMPLE_TIME,
@@ -172,7 +172,8 @@ int adc_read_channel(enum adc_channel ch)
/* wait for the end of calibration */
wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US *
- (CPU_CLOCK / (100000 * 2))) / 10);
+ (CPU_CLOCK / (100000 * 2))) /
+ 10);
while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) {
if (wait_loop_index-- == 0)
break;
@@ -181,8 +182,9 @@ int adc_read_channel(enum adc_channel ch)
/* Enable ADC */
STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY;
STM32_ADC1_CR |= STM32_ADC1_CR_ADEN;
- wait_loop_index = ((ADC_ENABLE_TIMEOUT_US *
- (CPU_CLOCK / (100000 * 2))) / 10);
+ wait_loop_index =
+ ((ADC_ENABLE_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) /
+ 10);
while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) {
wait_loop_index--;
if (wait_loop_index == 0)
@@ -196,8 +198,8 @@ int adc_read_channel(enum adc_channel ch)
STM32_ADC1_CR |= BIT(3); /* JADSTART */
/* Wait for end of injected conversion */
- wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US *
- (CPU_CLOCK / (100000 * 2))) / 10);
+ wait_loop_index =
+ ((ADC_CONVERSION_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / 10);
while (!(STM32_ADC1_ISR & BIT(6))) {
if (wait_loop_index-- == 0)
break;
