Update BridgeBinders with new HarnessRAM clocking
@@ -70,8 +70,9 @@ class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { port =>
implicit val p = GetSystemParameters(system)
- val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
- SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
+ val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
+ val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
+ SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
}
Nil
}
