rnndb: Add v5+ Falcon microcode cpuctl alias register
Seen across a range of Falcons (PDAEMON, PGRAPH (FECS, GPCCS), PSEC2 and PDISPLAY).
Appears related to bring up secretful v5+ Falcon cores where privileged or heavy
secure mode is enabled.
Bitfield are the same as main cpuctl register, so abstract.
Source (nvpgu):
https://nv-tegra.nvidia.com/gitweb/?p=linux-nvgpu.git;a=blob;f=drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h;hb=refs/tags/tegra-l4t-r28.2#l765
<!-- always 1f? -->
</bitset>
+<bitset name="uc_cpuctl">
+ <bitfield pos="0" name="RESET_TLB_TRIGGER"/>
+ <bitfield pos="1" name="START_TRIGGER"/>
+ <bitfield pos="2" name="RESET_UNK2_TRIGGER"/>
+ <bitfield pos="3" name="RESET_UNK3_TRIGGER"/>
+ <bitfield pos="4" name="STOPPED"/>
+ <bitfield pos="5" name="SLEEPING"/>
+</bitset>
+
<group name="falcon_base">
<reg32 offset="0x000" name="INTR_TRIGGER" access="w" type="falcon_intr"/>
<reg32 offset="0x004" name="INTR_ACK" access="w" type="falcon_intr"/>
<bitfield pos="31" name="ENABLED"/>
</reg32>
- <reg32 offset="0x100" name="UC_CTRL">
- <bitfield pos="0" name="RESET_TLB_TRIGGER"/>
- <bitfield pos="1" name="START_TRIGGER"/>
- <bitfield pos="2" name="RESET_UNK2_TRIGGER"/>
- <bitfield pos="3" name="RESET_UNK3_TRIGGER"/>
- <bitfield pos="4" name="STOPPED"/>
- <bitfield pos="5" name="SLEEPING"/>
- </reg32>
+ <reg32 offset="0x100" name="UC_CTRL" type="uc_cpuctl"/>
<reg32 offset="0x104" name="ENTRY"/>
<bitfield pos="30" name="UAS" variants="GF119-"/> <!-- unified address space -->
<bitfield pos="31" name="UNK31" variants="GF119-"/> <!-- auto fill -->
</reg32>
+
+ <reg32 offset="0x130" name="UC_CTRL_ALIAS" type="uc_cpuctl" variants="GM107-"/> <!-- v5+ secretful? -->
+
<reg32 offset="0x134" name="UNK134" variants="GM107-"> <!-- v5+ secretful? -->
<!-- bits 3, default 3 -->
</reg32>
