remove unused PLL clock outputs from iir_test/block_design.tcl
@@ -6,9 +6,6 @@ cell xilinx.com:ip:clk_wiz pll_0 {
PRIM_SOURCE Differential_clock_capable_pin
CLKOUT1_USED true
CLKOUT1_REQUESTED_OUT_FREQ 125.0
- CLKOUT2_USED true
- CLKOUT2_REQUESTED_OUT_FREQ 250.0
- CLKOUT2_REQUESTED_PHASE -90.0
USE_RESET false
} {
clk_in1_p adc_clk_p_i
