chip/npcx/gpio_chip-npcx7.h: Format with clang-format
BRANCH=none
TEST=none
Tricium: disable
#define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5)
#define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6)
#ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \
+#define NPCX_WUI_GPIO_E_7 \
+ WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \
*/
#endif
#define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3)
#define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4)
#ifndef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \
+#define NPCX_WUI_GPIO_7_1 \
+ WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \
support*/
#endif
/* PSL module (Optional) */
#ifdef NPCX_PSL_MODE_SUPPORT
-#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \
+#define NPCX_ALT_GPIO_D_2 \
+ ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \
*/
-#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \
+#define NPCX_ALT_GPIO_0_0 \
+ ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \
*/
#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */
#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */
#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1)
#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7)
#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \
+#define NPCX_LVOL_CTRL_2_6 \
+ NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \
*/
#else
#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7)
#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7)
#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0)
#ifdef NPCX_EXT32K_OSC_SUPPORT
-#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE /* Remove 1.8V support since \
+#define NPCX_LVOL_CTRL_3_3 \
+ NPCX_GPIO_NONE /* Remove 1.8V support since \
CLKOUT*/
#else
#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1)
