Correct mask of EN_LPFP and LPFP_CFG bits
The masks were incorrect, so attempts to write LPFP_CFG would clear the SIM and BDU bits.
@@ -66,8 +66,8 @@ LPS33HW_REGISTER_VALUE(LPS33HW_INTERRUPT_CFG, LPS33HW_INTERRUPT_CFG_PLE, 1, 0x02
LPS33HW_REGISTER_VALUE(LPS33HW_INTERRUPT_CFG, LPS33HW_INTERRUPT_CFG_PHE, 0, 0x01);
LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_ODR, 4, 0x70);
-LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_EN_LPFP, 3, 0x04);
-LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_LPFP_CFG, 2, 0x03);
+LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_EN_LPFP, 3, 0x08);
+LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_LPFP_CFG, 2, 0x04);
LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_BDU, 1, 0x02);
LPS33HW_REGISTER_VALUE(LPS33HW_CTRL_REG1, LPS33HW_CTRL_REG1_SIM, 0, 0x01);
