chip/stm32/clock-stm32l.c: Format with clang-format
BRANCH=none
TEST=none
@@ -86,8 +86,8 @@ static void clock_set_osc(enum clock_osc osc)
switch (osc) {
case OSC_HSI:
/* Ensure that HSI is ON */
- wait_for_ready(&STM32_RCC_CR,
- STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY);
+ wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_HSION,
+ STM32_RCC_CR_HSIRDY);
/* Disable LPSDSR */
STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR;
@@ -137,8 +137,8 @@ static void clock_set_osc(enum clock_osc osc)
(STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) |
STM32_RCC_ICSCR_MSIRANGE_1MHZ;
/* Ensure that MSI is ON */
- wait_for_ready(&STM32_RCC_CR,
- STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY);
+ wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_MSION,
+ STM32_RCC_CR_MSIRDY);
/* Switch to MSI */
STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI;
@@ -208,7 +208,6 @@ void clock_enable_module(enum module_id module, int enable)
/* Only change clock if needed */
if ((!!new_mask) != (!!clock_mask)) {
-
/* Flush UART before switching clock speed */
cflush();
@@ -379,6 +378,5 @@ static int command_clock(int argc, char **argv)
ccprintf("Clock frequency is now %d Hz\n", freq);
return EC_SUCCESS;
}
-DECLARE_CONSOLE_COMMAND(clock, command_clock,
- "hsi | msi",
+DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | msi",
"Set clock frequency");
