CMSIS-Core(M): Fixed ARM MPU implementation for Cortex-M0+.
Cortex-M0+ does not have a dedicated memory fault and used hard fault instead.
@@ -108,7 +108,9 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
}
/** Disable the MPU.
@@ -117,7 +119,9 @@ __STATIC_INLINE void ARM_MPU_Disable()
{
__DSB();
__ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
