add delay between gate_0/level and mult_0/B in pulsed_nmr/tx.tcl
@@ -95,6 +95,16 @@ cell xilinx.com:ip:dds_compiler dds_0 {
aresetn slice_1/dout
}
+# Create c_shift_ram
+cell xilinx.com:ip:c_shift_ram delay_0 {
+ WIDTH.VALUE_SRC USER
+ WIDTH 16
+ DEPTH 11
+} {
+ D gate_0/level
+ CLK /pll_0/clk_out1
+}
+
# Create axis_lfsr
cell pavel-demin:user:axis_lfsr lfsr_0 {} {
aclk /pll_0/clk_out1
@@ -112,12 +122,11 @@ cell xilinx.com:ip:xbip_dsp48_macro mult_0 {
P_WIDTH 15
} {
A dds_0/m_axis_data_tdata
- B gate_0/level
+ B delay_0/Q
CARRYIN lfsr_0/m_axis_tdata
CLK /pll_0/clk_out1
}
-
# Create xbip_dsp48_macro
cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
@@ -135,7 +144,7 @@ cell xilinx.com:ip:xbip_dsp48_macro mult_1 {
}
# Create c_shift_ram
-cell xilinx.com:ip:c_shift_ram delay_0 {
+cell xilinx.com:ip:c_shift_ram delay_1 {
WIDTH.VALUE_SRC USER
WIDTH 1
DEPTH 14
@@ -149,7 +158,7 @@ cell pavel-demin:user:axis_zeroer zeroer_0 {
AXIS_TDATA_WIDTH 16
} {
s_axis_tdata mult_0/P
- s_axis_tvalid delay_0/Q
+ s_axis_tvalid delay_1/Q
aclk /pll_0/clk_out1
}
