baseboard/guybrush/baseboard.c: Format with clang-format
BRANCH=none
TEST=none
@@ -145,8 +145,6 @@ const struct i2c_port_t i2c_ports[] = {
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-
const struct charger_config_t chg_chips[] = {
{
.i2c_port = I2C_PORT_CHARGER,
@@ -389,8 +387,7 @@ DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
int board_set_active_charge_port(int port)
{
- int is_valid_port = (port >= 0 &&
- port < CONFIG_USB_PD_PORT_MAX_COUNT);
+ int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
int i;
int rv;
@@ -505,7 +502,9 @@ int board_is_i2c_port_powered(int port)
case I2C_PORT_THERMAL_AP:
/* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */
return chipset_in_state(CHIPSET_STATE_ANY_OFF |
- CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1;
+ CHIPSET_STATE_ANY_SUSPEND) ?
+ 0 :
+ 1;
default:
return 1;
}
@@ -516,8 +515,7 @@ int board_is_i2c_port_powered(int port)
* the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
* current limits.
*/
-int board_aoz1380_set_vbus_source_current_limit(int port,
- enum tcpc_rp_value rp)
+int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
{
int rv;
@@ -528,12 +526,11 @@ int board_aoz1380_set_vbus_source_current_limit(int port,
return rv;
}
-void board_set_charge_limit(int port, int supplier, int charge_ma,
- int max_ma, int charge_mv)
+void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma,
+ int charge_mv)
{
- charge_set_input_current_limit(MAX(charge_ma,
- CONFIG_CHARGER_INPUT_CURRENT),
- charge_mv);
+ charge_set_input_current_limit(
+ MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
}
void sbu_fault_interrupt(enum ioex_signal signal)
@@ -893,13 +890,11 @@ static void baseboard_check_groupc_low(void)
if (!gpio_get_level(GPIO_EN_PWR_S0_R) &&
gpio_get_level(GPIO_PG_GROUPC_S0_OD))
CPRINTSCHIP("WARN: PG_GROUPC_S0_OD high while EN_PWR_S0_R low");
-
}
DECLARE_DEFERRED(baseboard_check_groupc_low);
void baseboard_en_pwr_s0(enum gpio_signal signal)
{
-
/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
gpio_set_level(GPIO_EN_PWR_S0_R,
gpio_get_level(GPIO_SLP_S3_L) &&
