add int_enbl_reg and int_data_reg to axis_pulse_generator
@@ -19,7 +19,9 @@ module axis_pulse_generator
reg int_tready_reg, int_tready_next;
reg int_sync_reg, int_sync_next;
reg int_dout_reg, int_dout_next;
+ reg int_enbl_reg, int_enbl_next;
reg [31:0] int_cntr_reg, int_cntr_next;
+ reg [127:0] int_data_reg, int_data_next;
always @(posedge aclk)
begin
@@ -28,14 +30,18 @@ module axis_pulse_generator
int_tready_reg <= 1'b0;
int_sync_reg <= 1'b0;
int_dout_reg <= 1'b0;
+ int_enbl_reg <= 1'b0;
int_cntr_reg <= 32'd0;
+ int_data_reg <= 128'd0;
end
else
begin
int_tready_reg <= int_tready_next;
int_sync_reg <= int_sync_next;
int_dout_reg <= int_dout_next;
+ int_enbl_reg <= int_enbl_next;
int_cntr_reg <= int_cntr_next;
+ int_data_reg <= int_data_next;
end
end
@@ -44,33 +50,40 @@ module axis_pulse_generator
int_tready_next = int_tready_reg;
int_sync_next = int_sync_reg;
int_dout_next = int_dout_reg;
+ int_enbl_next = int_enbl_reg;
int_cntr_next = int_cntr_reg;
+ int_data_next = int_data_reg;
- if(s_axis_tvalid)
+ if(~int_enbl_reg & s_axis_tvalid)
begin
- if(int_cntr_reg == s_axis_tdata[31:0])
+ int_tready_next = 1'b1;
+ int_enbl_next = 1'b1;
+ int_cntr_next = 32'd0;
+ int_data_next = s_axis_tdata;
+ end
+
+ if(int_enbl_reg)
+ begin
+ int_cntr_next = int_cntr_reg + 1'b1;
+
+ if(int_cntr_reg == int_data_reg[31:0])
begin
int_sync_next = 1'b1;
int_dout_next = 1'b1;
end
- if(int_cntr_reg == s_axis_tdata[63:32])
+ if(int_cntr_reg == int_data_reg[63:32])
begin
int_dout_next = 1'b0;
end
- if(int_cntr_reg < s_axis_tdata[95:64])
+ if(int_cntr_reg == int_data_reg[95:64])
begin
- int_cntr_next = int_cntr_reg + 1'b1;
- end
- else
- begin
- int_tready_next = 1'b1;
+ int_enbl_next = 1'b0;
end
if(int_tready_reg)
begin
- int_cntr_next = 32'd0;
int_tready_next = 1'b0;
end
@@ -82,7 +95,7 @@ module axis_pulse_generator
end
assign s_axis_tready = int_tready_reg;
- assign poff = s_axis_tdata[127:96];
+ assign poff = int_data_reg[127:96];
assign sync = int_sync_reg;
assign dout = int_dout_reg;
