Link coding conventions to wiki page
[ci skip]
@@ -138,60 +138,4 @@ To reformat Python code:
Python scripts should be written to be compatible with both Python 2
and Python 3.
-The OpenCores guidelines give a good set of rules for SystemVerilog sources,
-which this project generally follows (with some exceptions, which should be
-obvious)
-
-http://cdn.opencores.org/downloads/opencores_coding_guidelines.pdf
-
-This project also uses the following additional conventions:
-
-- Use `logic` to define nets and flops rather than `reg` and `wire`
-- For non-generic components, make the instance name be the same as the component name<br>
- No:
-
- ```SystemVerilog
- writeback_stage wback(
- ```
-
- Yes:
-
- ```SystemVerilog
- writeback_stage writeback_stage(
- ```
-
-- Use verilog-2001 style port definitions, specifying direction and type in one
- definition. Group module ports by source/destination and add a comment for
- each group. Prefix signals that go between non-generic components with an
- abbreviation of the source module
-
- ```SystemVerilog
- // From io_request_queue
- input scalar_t ior_read_value,
- input logic ior_rollback_en,
-
- // From control registers
- input scalar_t cr_creg_read_val,
- input thread_bitmap_t cr_interrupt_en,
- input scalar_t cr_fault_handler,
- ```
-
-- Instantiate srams using sram_1r1w and sram_2r1w
-- Use always_ff and always_comb to avoid inferred latches or sensitivity list bugs.
-- Signals often use the following suffixes:
-
- |Suffix|Meaning |
- |------|--------|
- | _en | Use for a signal that enables some operation. Internal enables are always active high. |
- | _oh | One-hot. No more than one signal will be set, corresponding to the index |
- | _idx | Signal is an index. Usually used when one-hot signals of the same name are also present |
- | _t | Typedef |
- | _gen | Generated block |
- | _nxt | Combinational logic that generates the next value (input) for a flop. Used to distinguish the input from the output of the flop |
-
-- Don't use translate_off/translate on. Use ``ifdef SIMULATION` where necessary
- (this should be rare).
-- Use unique and unique0 in front of case statements wherever appropriate. Don't use
- full_case/parallel_case pragmas.
-- assert should only be inside an always_ff and shouldn't be reachable when reset
- is high. Otherwise it may trip incorrectly.
+Additional coding conventions are found [here](https://github.com/jbush001/NyuziProcessor/wiki/HDL-Conventions).
