Update SiFive submodules to CHIPS fork
url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"]
path = generators/sifive-blocks
- url = https://github.com/sifive/sifive-blocks.git
+ url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
url = https://github.com/firesim/icenet.git
[submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache
- url = https://github.com/sifive/block-inclusivecache-sifive.git
+ url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
path = toolchains/riscv-tools/riscv-gnu-toolchain
url = https://github.com/riscv/riscv-gnu-toolchain.git
url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"]
path = fpga/fpga-shells
- url = https://github.com/sifive/fpga-shells.git
+ url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git
