Add support for manually adjusting DRAM latency with a ShiftQueue
package chipyard.harness
import chisel3._
-import chisel3.experimental.{Analog, BaseModule}
+import chisel3.util._
+import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
@@ -10,6 +11,7 @@ import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
@@ -137,7 +139,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({
}
})
-class WithBlackBoxSimMem extends OverrideHarnessBinder({
+class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBinder({
(system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
(ports zip system.memAXI4Node.edges.in).map { case (port, edge) =>
@@ -146,6 +148,24 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({
val clockFreq = p(MemoryBusKey).dtsFrequency.get
val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName("simdram")
mem.io.axi <> port.bits
+ // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781
+ def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = {
+ require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.")
+ val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits)))
+ d.bits := irr.bits
+ d.valid := irr.valid
+ irr.ready := d.ready
+ d
+ }
+ if (additionalLatency > 0) {
+ withClockAndReset (port.clock, port.reset) {
+ mem.io.axi.aw <> ShiftQueue(Decoupled(port.bits.aw), additionalLatency)
+ mem.io.axi.w <> ShiftQueue(Decoupled(port.bits.w ), additionalLatency)
+ port.bits.b <> ShiftQueue(Decoupled(mem.io.axi.b), additionalLatency)
+ mem.io.axi.ar <> ShiftQueue(Decoupled(port.bits.ar), additionalLatency)
+ port.bits.r <> ShiftQueue(Decoupled(mem.io.axi.r), additionalLatency)
+ }
+ }
mem.io.clock := port.clock
mem.io.reset := port.reset
}
