[snitch] Make number of register write ports parameterizable
Currently only either 1 or 2 write ports are supported.
@@ -1851,6 +1851,35 @@ module snitch #(
endcase
end
+ if (RegNrWritePorts == 1) begin
+ always_comb begin
+ gpr_we[0] = 1'b0;
+ gpr_waddr[0] = rd;
+ gpr_wdata[0] = alu_writeback;
+ // external interfaces
+ lsu_pready = 1'b0;
+ acc_pready_o = 1'b0;
+ retire_acc = 1'b0;
+ retire_load = 1'b0;
+
+ if (retire_i) begin
+ gpr_we[0] = 1'b1;
+ // if we are not retiring another instruction retire the load now
+ end else if (lsu_pvalid) begin
+ retire_load = 1'b1;
+ gpr_we[0] = 1'b1;
+ gpr_waddr[0] = lsu_rd;
+ gpr_wdata[0] = ld_result[31:0];
+ lsu_pready = 1'b1;
+ end else if (acc_pvalid_i) begin
+ retire_acc = 1'b1;
+ gpr_we[0] = 1'b1;
+ gpr_waddr[0] = acc_pid_i;
+ gpr_wdata[0] = acc_pdata_i[31:0];
+ acc_pready_o = 1'b1;
+ end
+ end
+ end else if (RegNrWritePorts == 2) begin
always_comb begin
gpr_we[0] = 1'b0;
gpr_waddr[0] = rd;
@@ -1893,6 +1922,9 @@ module snitch #(
end
end
end
+ end else begin
+ $fatal(1, "[snitch] Unsupported RegNrWritePorts.");
+ end
// --------------------------
// RISC-V Formal Interface
