update adc_recorder_trigger
@@ -174,10 +174,12 @@ cell xilinx.com:ip:cic_compiler cic_0 {
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 16
USE_XTREME_DSP_SLICE false
+ HAS_ARESETN true
} {
S_AXIS_DATA bcast_0/M00_AXIS
S_AXIS_CONFIG rate_0/M_AXIS
aclk pll_0/clk_out1
+ aresetn rst_0/peripheral_aresetn
}
# Create cic_compiler
@@ -195,10 +197,12 @@ cell xilinx.com:ip:cic_compiler cic_1 {
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 16
USE_XTREME_DSP_SLICE false
+ HAS_ARESETN true
} {
S_AXIS_DATA bcast_0/M01_AXIS
S_AXIS_CONFIG rate_1/M_AXIS
aclk pll_0/clk_out1
+ aresetn rst_0/peripheral_aresetn
}
# Create axis_combiner
@@ -227,9 +231,12 @@ cell xilinx.com:ip:fir_compiler fir_0 {
CLOCK_FREQUENCY 125
OUTPUT_ROUNDING_MODE Truncate_LSBs
OUTPUT_WIDTH 16
+ M_DATA_HAS_TREADY true
+ HAS_ARESETN true
} {
S_AXIS_DATA comb_0/M_AXIS
aclk pll_0/clk_out1
+ aresetn rst_0/peripheral_aresetn
}
# Create axis_trigger
@@ -258,23 +265,13 @@ cell pavel-demin:user:axis_oscilloscope scope_0 {
aresetn slice_0/dout
}
-# Create axis_dwidth_converter
-cell xilinx.com:ip:axis_dwidth_converter conv_0 {
- S_TDATA_NUM_BYTES.VALUE_SRC USER
- S_TDATA_NUM_BYTES 4
- M_TDATA_NUM_BYTES 8
-} {
- S_AXIS scope_0/M_AXIS
- aclk pll_0/clk_out1
- aresetn slice_0/dout
-}
-
# Create axis_ram_writer
cell pavel-demin:user:axis_ram_writer writer_0 {
ADDR_WIDTH 22
AXI_ID_WIDTH 3
+ AXIS_TDATA_WIDTH 32
} {
- S_AXIS conv_0/M_AXIS
+ S_AXIS scope_0/M_AXIS
M_AXI ps_0/S_AXI_ACP
cfg_data slice_3/dout
aclk pll_0/clk_out1
