Doxygen: Added cross-reference from RTX5 hardware requirements to CMSIS-Core(A) IRQ Controller API.
@@ -1172,13 +1172,13 @@ Timer Peripheral | An arbitrary timer peripheral generates the kernel
Exception Handler | RTX implements exception handlers for SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction interrupt.
Core Registers | The processor status is read using the following core registers: CPSR, CPACR and FPSCR.
LDREX, STREX instruction | Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions.
-Interrupt Controller | An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in %irq_ctrl_gic.c using the IRQ Controller API
+Interrupt Controller | An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in %irq_ctrl_gic.c using the <a class="el" href="../../Core_A/html/group__irq__ctrl__gr.html">IRQ Controller API</a>.
The interface files to the processor hardware are:
- <b>%irq_ca.s</b> defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
- <b>%rtx_core_ca.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- <b>%os_tick.h</b> is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the timer peripheral.
- - <b>%irq_ctrl.h</b> is the IRQ Controller API that defines the interface functions to the interrupt controller.
+ - <b>%irq_ctrl.h</b> is the <a class="el" href="../../Core_A/html/group__irq__ctrl__gr.html">IRQ Controller API</a> that defines the interface functions to the interrupt controller.
\note
- The CMSIS-Core variable \c SystemCoreClock is used to configure the timer peripheral.
