added timing constrains for the action_reset -> ddr3_reset path (ha_pclock ->ref200clk)
@@ -10,6 +10,11 @@ set_min_delay -from [get_pins a0/*ddr3_reset_n_q_reg/C] -to [get_pins a0/*ddr3s
set_max_delay -from [get_pins a0/*ddr3_reset_n_q_reg/C] -to [get_pins {a0/*ddr3sdram_bank1/inst/axi_ctrl_top_0/axi_ctrl_reg_bank_0/inst_reg[3].axi_ctrl_reg/data_reg*/S}] 3.0
set_min_delay -from [get_pins a0/*ddr3_reset_n_q_reg/C] -to [get_pins {a0/*ddr3sdram_bank1/inst/axi_ctrl_top_0/axi_ctrl_reg_bank_0/inst_reg[3].axi_ctrl_reg/data_reg*/S}] -0.5
+##
+set_false_path -from [get_pins a0/donut_i/ctrl_mgr/afu_reset_*_reg/C] -to [get_pins a0/ddr3_reset_m_reg_inv/D]
+set_false_path -from [get_pins a0/action_reset_q_reg/C] -to [get_pins a0/ddr3_reset_m_reg_inv/D]
+set_false_path -from [get_pins a0/action_reset_qq_reg/C] -to [get_pins a0/ddr3_reset_m_reg_inv/D]
+
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