replace int_wid with int_awid in axis_ram_writer
@@ -50,7 +50,7 @@ module axis_ram_writer #
reg int_awvalid_reg, int_awvalid_next;
reg int_wvalid_reg, int_wvalid_next;
reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
- reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
+ reg [AXI_ID_WIDTH-1:0] int_awid_reg, int_awid_next;
wire int_full_wire, int_empty_wire, int_rden_wire;
wire int_wlast_wire, int_tready_wire;
@@ -84,14 +84,14 @@ module axis_ram_writer #
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_addr_reg <= {(ADDR_WIDTH){1'b0}};
- int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
+ int_awid_reg <= {(AXI_ID_WIDTH){1'b0}};
end
else
begin
int_awvalid_reg <= int_awvalid_next;
int_wvalid_reg <= int_wvalid_next;
int_addr_reg <= int_addr_next;
- int_wid_reg <= int_wid_next;
+ int_awid_reg <= int_awid_next;
end
end
@@ -100,7 +100,7 @@ module axis_ram_writer #
int_awvalid_next = int_awvalid_reg;
int_wvalid_next = int_wvalid_reg;
int_addr_next = int_addr_reg;
- int_wid_next = int_wid_reg;
+ int_awid_next = int_awid_reg;
if(~int_empty_wire & ~int_awvalid_reg & ~int_wvalid_reg)
begin
@@ -120,7 +120,7 @@ module axis_ram_writer #
if(m_axi_wready & int_wlast_wire)
begin
- int_wid_next = int_wid_reg + 1'b1;
+ int_awid_next = int_awid_reg + 1'b1;
if(int_empty_wire)
begin
int_wvalid_next = 1'b0;
@@ -134,14 +134,14 @@ module axis_ram_writer #
assign sts_data = int_addr_reg;
- assign m_axi_awid = int_wid_reg;
+ assign m_axi_awid = int_awid_reg;
assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
assign m_axi_awlen = 4'd15;
assign m_axi_awsize = ADDR_SIZE;
assign m_axi_awburst = 2'b01;
assign m_axi_awcache = 4'b1111;
assign m_axi_awvalid = int_awvalid_reg;
- assign m_axi_wid = int_wid_reg;
+ assign m_axi_wid = int_awid_reg;
assign m_axi_wdata = int_wdata_wire[AXI_DATA_WIDTH-1:0];
assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wlast = int_wlast_wire;
