Fixed register decoding for XOP and VEX instructions (again)
@@ -980,6 +980,11 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
case ZYDIS_REG_ENCODING_IS4:
{
uint8_t value = (info->details.imm[0].value.ubyte >> 4) & 0x0F;
+ // We have to check the instruction-encoding, because the extension by bit [3] is only
+ // valid for EVEX and MVEX instructions
+ if ((info->encoding == ZYDIS_INSTRUCTION_ENCODING_EVEX) ||
+ (info->encoding == ZYDIS_INSTRUCTION_ENCODING_MVEX))
+ {
switch (registerClass)
{
case ZYDIS_REGCLASS_XMM:
@@ -989,6 +994,7 @@ static uint8_t ZydisCalcRegisterId(ZydisDecoderContext* context, ZydisInstructio
default:
break;
}
+ }
return value;
}
case ZYDIS_REG_ENCODING_MASK:
