[hardware] Shuffle AXI channels for maximum DMA bandwidth
@@ -377,6 +377,13 @@ module mempool_group
axi_tile_req_t [NumAXIMastersPerGroup-1:0] axi_mst_req;
axi_tile_resp_t [NumAXIMastersPerGroup-1:0] axi_mst_resp;
+ axi_tile_req_t [NumTilesPerGroup+NumDmasPerGroup-1:0] axi_slv_req;
+ axi_tile_resp_t [NumTilesPerGroup+NumDmasPerGroup-1:0] axi_slv_resp;
+
+ for (genvar i = 0; i < NumDmasPerGroup; i++) begin : gen_axi_slv_vec
+ assign axi_slv_req[i*(NumTilesPerDma+1)+:NumTilesPerDma+1] = {axi_dma_req[i],axi_tile_req[i*NumTilesPerDma+:NumTilesPerDma]};
+ assign {axi_dma_resp[i],axi_tile_resp[i*NumTilesPerDma+:NumTilesPerDma]} = axi_slv_resp[i*(NumTilesPerDma+1)+:NumTilesPerDma+1];
+ end : gen_axi_slv_vec
axi_hier_interco #(
.NumSlvPorts (NumTilesPerGroup+NumDmasPerGroup),
@@ -400,8 +407,8 @@ module mempool_group
.rst_ni (rst_ni ),
.test_i (1'b0 ),
.ro_cache_ctrl_i (ro_cache_ctrl_q),
- .slv_req_i ({axi_dma_req,axi_tile_req} ),
- .slv_resp_o ({axi_dma_resp,axi_tile_resp}),
+ .slv_req_i (axi_slv_req ),
+ .slv_resp_o (axi_slv_resp ),
.mst_req_o (axi_mst_req ),
.mst_resp_i (axi_mst_resp )
);
