arch/s5j: add coherent dcache support
@@ -117,6 +117,12 @@ CMN_UASRCS += arm_signal_handler.S
endif
endif
+ifeq ($(CONFIG_ELF),y)
+CMN_CSRCS += arm_coherent_dcache.c
+else ifeq ($(CONFIG_MODULE),y)
+CMN_CSRCS += arm_coherent_dcache.c
+endif
+
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += s5j_timerisr.c
endif
