Cavium OcteonTX: cache line fix
According to Nitin Saxena ThunderX2 machine has 64B cache line whilst
all others are 128B. According to Damjan, Nitin's previous patch broke
compilation for all non-Cavium machines. This patch should make
everything happy again.
@@ -32,11 +32,15 @@ if(CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64.*|AARCH64.*)")
endforeach()
# Implementer 0x43 - Cavium
# Part 0x0af - ThunderX2 is 64B, rest all are 128B
- if (${CPU_IMPLEMENTER} STREQUAL "0x43" AND ${CPU_PART} STREQUAL "0x0af")
+ if (${CPU_IMPLEMENTER} STREQUAL "0x43")
+ if (${CPU_PART} STREQUAL "0x0af")
set(VPP_LOG2_CACHE_LINE_SIZE 6)
else()
set(VPP_LOG2_CACHE_LINE_SIZE 7)
endif()
+ else()
+ set(VPP_LOG2_CACHE_LINE_SIZE 6)
+ endif()
math(EXPR VPP_CACHE_LINE_SIZE "1 << ${VPP_LOG2_CACHE_LINE_SIZE}")
message(STATUS "ARM AArch64 CPU implementer ${CPU_IMPLEMENTER} part ${CPU_PART} cacheline size ${VPP_CACHE_LINE_SIZE}")
else()
