remove FCLK_CLK0 from base_system
-# Create processing_system7
-cell xilinx.com:ip:processing_system7:5.5 ps_0 {
- PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
- PCW_USE_S_AXI_HP0 1
-} {
- M_AXI_GP0_ACLK ps_0/FCLK_CLK0
- S_AXI_HP0_ACLK ps_0/FCLK_CLK0
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
- make_external {FIXED_IO, DDR}
- Master Disable
- Slave Disable
-} [get_bd_cells ps_0]
-
-# PLL
-
# Create clk_wiz
cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
PRIMITIVE PLL
@@ -24,11 +6,24 @@ cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
PRIM_SOURCE Differential_clock_capable_pin
CLKOUT1_USED true
CLKOUT1_REQUESTED_OUT_FREQ 125.0
- CLKOUT2_USED true
- CLKOUT2_REQUESTED_OUT_FREQ 250.0
- CLKOUT2_REQUESTED_PHASE -90.0
USE_RESET false
} {
clk_in1_p adc_clk_p_i
clk_in1_n adc_clk_n_i
}
+
+# Create processing_system7
+cell xilinx.com:ip:processing_system7:5.5 ps_0 {
+ PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
+ PCW_USE_S_AXI_HP0 1
+} {
+ M_AXI_GP0_ACLK pll_0/clk_out1
+ S_AXI_HP0_ACLK pll_0/clk_out1
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
+ make_external {FIXED_IO, DDR}
+ Master Disable
+ Slave Disable
+} [get_bd_cells ps_0]
