chip/stm32/clock-stm32f0.c: Format with clang-format
BRANCH=none
TEST=none
@@ -137,8 +137,7 @@ void config_hispeed_clock(void)
while ((STM32_RCC_CFGR & 0xc) != 0x8)
;
/* F03X and F05X and F070 don't have HSI48 */
-#elif defined(CHIP_VARIANT_STM32F03X) || \
-defined(CHIP_VARIANT_STM32F05X) || \
+#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \
defined(CHIP_VARIANT_STM32F070)
/* If PLL is the clock source, PLL has already been set up. */
if ((STM32_RCC_CFGR & 0xc) == 0x8)
@@ -331,8 +330,8 @@ void __idle(void)
/* Set deep sleep bit */
CPU_SCB_SYSCTRL |= 0x4;
- set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY,
- &rtc0, 0);
+ set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0,
+ 0);
asm("wfi");
CPU_SCB_SYSCTRL &= ~0x4;
@@ -496,8 +495,7 @@ static int command_idle_stats(int argc, char **argv)
return EC_SUCCESS;
}
-DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats,
- "",
+DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "",
"Print last idle stats");
#endif /* CONFIG_CMD_IDLE_STATS */
#endif
