message: sv2017: example p338: add missing module wrap
diff: +module top;
  clocking bus @(posedge clock1);
  default input #10ns output #2ns;
  input data, ready, enable = top.mem1.enable;
  output negedge ack;
  input #1step addr;
  endclocking
  +endmodule
  \ No newline at end of file
  