message: sv2017: example p339: add missing module wrap
diff: +module top;
  clocking dram @(clk);
  input #1ps address;
  input #5 output #6 data;
  @@ -6,5 +7,4 @@ endclocking
  clocking cd1 @(posedge phi1);
  input #1step state = top.cpu1.state;
  endclocking
  -
  -
  +endmodule
  \ No newline at end of file
  