message: verilog_to_basic_hdl_sim_model: register new transformations
diff: @@ -12,6 +12,9 @@ from hdlConvertor.translate._verilog_to_basic_hdl_sim_model\
  .discover_stm_outputs import discover_stm_outputs_context
  from hdlConvertor.translate._verilog_to_basic_hdl_sim_model\
  .verilog_operands_to_basic_hdl_sim_model import BasicHdlSimModelTranslateVerilogOperands
  +from hdlConvertor.translate._verilog_to_basic_hdl_sim_model\
  + .assignment_to_update_assignment import AssignmentToUpdateAssignment
  +from hdlConvertor.translate._verilog_to_basic_hdl_sim_model.apply_io_scope_to_signal_names import ApplyIoScopeToSignalNames
  def verilog_to_basic_hdl_sim_model(context):
  @@ -20,12 +23,16 @@ def verilog_to_basic_hdl_sim_model(context):
  """
  link_module_dec_def(context)
  name_scope = NameScope.make_top(False)
  +
  DiscoverDeclarations(name_scope).visit_HdlContext(context)
  ResolveNames(name_scope).visit_HdlContext(context)
  wrap_module_statements_to_processes(context)
  BasicHdlSimModelTranslateVerilogOperands().visit_HdlContext(context)
  VerilogTypesToBasicHdlSimModel().visit_HdlContext(context)
  stm_outputs = discover_stm_outputs_context(context)
  +
  AddUniqueLabelsToAllProcesses(name_scope, stm_outputs).context(context)
  + AssignmentToUpdateAssignment().visit_HdlContext(context)
  + ApplyIoScopeToSignalNames().visit_HdlContext(context)
  return context, stm_outputs, name_scope
  