message: sv2017: example p340: add missing module wrap
diff: +module top;
  clocking mem @(clock);
  input instruction = { opcode, regA, regB[3:1] };
  endclocking
  @@ -20,5 +21,7 @@ input enable;
  endclocking
  initial begin
  end
  +
  assign cmd = enable ? cmd_reg: 'x;
  endprogram
  +endmodule
  \ No newline at end of file
  