message: readme: add ref. on similar projects
diff: @@ -94,11 +94,13 @@ for o in d.objs:
  * [pyVHDLParser](https://github.com/Paebbels/pyVHDLParser) - python vhdl parser with 2008 support
  * [rust_hdl](https://github.com/kraigher/rust_hdl) - rust vhdl 2008 parser
  * [slang](https://github.com/MikePopoloski/slang) - Parser and compiler library for SystemVerilog.
  +* [sv-parser](https://github.com/dalance/sv-parser) - Rust, SystemVerilog parser library fully complient with IEEE 1800-2017
  * [systemc-clang](https://github.com/anikau31/systemc-clang) - SystemC Parser using the Clang Front-end
  * [v2sc](https://github.com/denisgav/v2sc) - vhdl to systemc
  * [veelox](https://github.com/martinda/veelox) - Java+ANTLR, An experiment in SystemVerilog Preprocessing
  * [verilog-parser](https://github.com/ben-marshall/verilog-parser) - A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  * [vbpp](https://github.com/balanx/vbpp) - C, Verilog PreProcessor
  +* [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog) - JS, Verilog grammar for tree-sitter
  * [Verilog-Perl](https://metacpan.org/pod/Verilog-Perl)
  * [vpp.pl](https://www.beyond-circuits.com/wordpress/vpp-pl-man-page/) - verilog preprocessor with integrated Perl
  * [sv2v](https://github.com/zachjs/sv2v)- Haskell, SystemVerilog to Verilog
  