message: msvc: msvc friendly PortParser::addTypeSpecToPorts
diff: @@ -8,7 +8,7 @@ using namespace Verilog2001;
  std::vector<Port*>* PortParser::addTypeSpecToPorts(Direction direction,
  Verilog2001Parser::Net_typeContext* net_type, bool signed_,
  Verilog2001Parser::Range_Context* range_, std::vector<Port*> * ports) {
  - if ((net_type != nullptr) and (net_type->getText() != "wire")) {
  + if ((net_type != nullptr) && (net_type->getText() != "wire")) {
  NotImplementedLogger::print(
  "PortParser.addTypeSpecToPorts.net_type different than wire");
  }
  