message: add debug messages if interrupt is pending
diff: @@ -733,11 +733,11 @@ fn local_apic_write(x2apic_msr: u32, value: u64) {
  // The ICR1 register in xAPIC mode also has a Delivery Status bit.
  // Wait until previous interrupt was deliverd.
  // This bit does not exist in x2APIC mode (cf. Intel Vol. 3A, 10.12.9).
  - while (unsafe { core::ptr::read_volatile(value_ref) }
  - & APIC_ICR_DELIVERY_STATUS_PENDING)
  + if (unsafe { core::ptr::read_volatile(value_ref) } & APIC_ICR_DELIVERY_STATUS_PENDING)
  > 0
  {
  spin_loop_hint();
  + info!("Previous interrupt is missing");
  }
  // Instead of a single 64-bit ICR register, xAPIC has two 32-bit registers (ICR1 and ICR2).
  