anvil: Fix udev build without egl
@@ -371,9 +371,9 @@ impl<S: SessionNotifier, Data: 'static> UdevHandlerImpl<S, Data> {
let connector_infos: Vec<ConnectorInfo> = res_handles
.connectors()
.iter()
- .map(|conn| device.resource_info::<ConnectorInfo>(*conn).unwrap())
- .filter(|conn| conn.connection_state() == ConnectorState::Connected)
- .inspect(|conn| info!(logger, "Connected: {:?}", conn.connector_type()))
+ .map(|conn| device.get_connector_info(*conn).unwrap())
+ .filter(|conn| conn.state() == ConnectorState::Connected)
+ .inspect(|conn| info!(logger, "Connected: {:?}", conn.interface()))
.collect();
let mut backends = HashMap::new();
@@ -383,7 +383,8 @@ impl<S: SessionNotifier, Data: 'static> UdevHandlerImpl<S, Data> {
let encoder_infos = connector_info
.encoders()
.iter()
- .flat_map(|encoder_handle| device.resource_info::<EncoderInfo>(*encoder_handle))
+ .filter_map(|e| *e)
+ .flat_map(|encoder_handle| device.get_encoder_info(encoder_handle))
.collect::<Vec<EncoderInfo>>();
for encoder_info in encoder_infos {
for crtc in res_handles.filter_crtcs(encoder_info.possible_crtcs()) {
