Adding information about DSP timing specifications
@@ -849,6 +849,22 @@ const APP: () = {
}
}
+ /// Main DSP processing routine for Stabilizer.
+ ///
+ /// # Note
+ /// Processing time for the DSP application code is bounded by the following constraints:
+ ///
+ /// DSP application code starts after the ADC has generated a batch of samples and must be
+ /// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
+ /// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
+ ///
+ /// The DSP application code must also fill out the next DAC output buffer in time such that the
+ /// DAC can switch to it when it has completed the current buffer. If this constraint is not met
+ /// it's possible that old DAC codes will be generated on the output and the output samples will
+ /// be delayed by 1 batch.
+ ///
+ /// Because the ADC and DAC operate at the same rate, these two constraints actually implement
+ /// the same time bounds, meeting one also means the other is also met.
#[task(binds=DMA1_STR3, resources=[adcs, dacs, iir_state, iir_ch, dds_output, input_stamper], priority=2)]
fn process(c: process::Context) {
let adc_samples = [
