Autoformat scb.rs by rustfmt
@@ -7,9 +7,9 @@ use volatile_register::RW;
#[cfg(not(armv6m))]
use super::cpuid::CsselrCacheType;
#[cfg(not(armv6m))]
-use super::CPUID;
-#[cfg(not(armv6m))]
use super::CBP;
+#[cfg(not(armv6m))]
+use super::CPUID;
use super::SCB;
/// Register block
@@ -604,13 +604,18 @@ impl SCB {
/// Initiate a system reset request to reset the MCU
pub fn system_reset(&mut self) -> ! {
::asm::dsb();
- unsafe { self.aircr.modify(|r|
+ unsafe {
+ self.aircr.modify(
+ |r| {
SCB_AIRCR_VECTKEY | // otherwise the write is ignored
r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged
- SCB_AIRCR_SYSRESETREQ // set the bit
- ) };
+ SCB_AIRCR_SYSRESETREQ
+ }, // set the bit
+ )
+ };
::asm::dsb();
- loop { // wait for the reset
+ loop {
+ // wait for the reset
::asm::nop(); // avoid rust-lang/rust#28728
}
}
@@ -632,9 +637,7 @@ impl SCB {
/// Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending
pub fn is_pendsv_pending() -> bool {
- unsafe {
- (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET
- }
+ unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET }
}
/// Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt
@@ -655,9 +658,7 @@ impl SCB {
/// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
#[inline]
pub fn is_pendst_pending() -> bool {
- unsafe {
- (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET
- }
+ unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET }
}
/// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
