adding language verilog
* adding language verilog
* Update languages.yaml
straighter lines look better
* more v straightening and updated chip value
@@ -2347,6 +2347,34 @@ Vala:
- magenta
- white
chip: '#A56DE2'
+Verilog:
+ type: programming
+ ascii: |
+ {0} _.._ _.._ _.._
+ {0} _.._ _.._ _.._
+ {0} _.._ _.._ _.._
+ {0} _......................._
+ {0} _.{1}----- -----{0}._
+ {0}_..._.{1} --- --- {0}._..._
+ {0}_..._.{1} --- --- {0}._..._
+ {0} _.{1} --- --- {0}._
+ {0} _.{1} --- --- {0}._
+ {0}_..._.{1} --- --- {0}._..._
+ {0}_..._.{1} --- --- {0}._..._
+ {0} _.{1} --- --- {0}._
+ {0} _.{1} --- --- {0}._
+ {0}_..._.{1} ----- {0}._..._
+ {0}_..._.{1} --- {0}._..._
+ {0} _.{1} - {0}._
+ {0} _......................._
+ {0} _.._ _.._ _.._
+ {0} _.._ _.._ _.._
+ {0} _.._ _.._ _.._
+ colors:
+ ansi:
+ - white
+ - magenta
+ chip: '#b2b7f8'
Vhdl:
type: programming
ascii: |
