Make RCC lookup optional
@@ -156,12 +156,19 @@ fn main() {
};
// Load RCC register for chip
- let chip_family = chip.family.to_ascii_lowercase();
- let rcc_family = chip_family.strip_prefix("stm32").unwrap();
+ let rcc = chip.peripherals.iter().find_map(|(name, p)| {
+ if name == "RCC" {
+ p.block.as_ref().map(|block| {
+ let bi = BlockInfo::parse(block);
let rcc_reg_path = Path::new(&dir)
.join("registers")
- .join(&format!("rcc_{}.yaml", &rcc_family[0..2]));
- let rcc: ir::IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap();
+ .join(&format!("{}_{}.yaml", bi.module, bi.version));
+ serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap()
+ })
+ } else {
+ None
+ }
+ });
let mut peripheral_versions: HashMap<String, String> = HashMap::new();
let mut pin_table: Vec<Vec<String>> = Vec::new();
@@ -254,6 +261,7 @@ fn main() {
}
if let Some(clock) = &p.clock {
+ if let Some(rcc) = &rcc {
// Workaround for clock registers being split on some chip families. Assume fields are
// named after peripheral and look for first field matching and use that register.
let en = find_reg_for_field(&rcc, clock, &format!("{}EN", name));
@@ -281,6 +289,7 @@ fn main() {
}
}
}
+ }
dev.peripherals.push(ir_peri);
}
