Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
@@ -5,6 +5,7 @@ use core::mem::MaybeUninit;
#[cfg_attr(rcc_f0, path = "f0.rs")]
#[cfg_attr(rcc_f1, path = "f1.rs")]
+#[cfg_attr(rcc_f2, path = "f2.rs")]
#[cfg_attr(rcc_f3, path = "f3.rs")]
#[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]
#[cfg_attr(rcc_f7, path = "f7.rs")]
@@ -39,11 +40,11 @@ pub struct Clocks {
// AHB
pub ahb1: Hertz,
#[cfg(any(
- rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb, rcc_wl5
+ rcc_l4, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb, rcc_wl5
))]
pub ahb2: Hertz,
#[cfg(any(
- rcc_l4, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5
+ rcc_l4, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5
))]
pub ahb3: Hertz,
#[cfg(any(rcc_h7, rcc_h7ab))]
