readme: update compile flow
Extend the expected compile flow outliend in the README with new
insights gained into the necessary steps to concretize the very abstract
and high level modelling of SystemVerilog, such that it be representable
in LLHD.
@@ -25,9 +25,14 @@ Elaboration
- apply default values
- merge ANSI and non-ANSI ports
- `always_{ff,latch,comb}` -> `always`
-- typecheck and evaluate const exprs
-- specialize generic instances
+ - flatten nested design elements and sort hierarchy items
- assign and check types (can be one step)
+- evaluate const exprs
+- specialize generic instances
+- lower to MIR
+ - evaluate generate constructs
+ - determine scheduling
+- perform static analyses (future work)
- lower to LLHD
- link and emit output file
