def METHOD_NAME(test, ImmGen):
    for t in test.tests:
        x_len = 32
        with open(f'tests/resources/{t}.hex', 'r') as file_:
            contents = [line.rstrip() for line in file_.readlines()]
            loadmem = load_mem(contents, x_len)
        class DUT(m.Circuit):
            io = m.IO(done=m.Out(m.Bit)) + m.ClockIO(has_reset=True)
            core = Core(x_len,
                        data_path_kwargs=m.generator.ParamDict(ImmGen=ImmGen))()
            core.host.fromhost.data.undriven()
            core.host.fromhost.valid @= False
            # reverse concat because we're using utils with chisel ordering
            _hex = [concat(*reversed(x)) for x in loadmem]
            imem = m.Memory(1 << 20, m.UInt[x_len])()
            dmem = m.Memory(1 << 20, m.UInt[x_len])()
            INIT, RUN = False, True
            state = m.Register(init=INIT)()
            cycle = m.Register(m.UInt[32])()
            n = len(_hex)
            counter = Counter(
                n,
                has_enable=True,
                has_cout=True,
                reset_type=m.Reset
            )()
            counter.CE @= m.enable(state.O == INIT)
            cntr, done = counter.O, counter.COUT
            iaddr = (core.icache.req.data.addr // (x_len // 8))[:20]
            daddr = (core.dcache.req.data.addr // (x_len // 8))[:20]
            dmem.RADDR @= daddr
            dmem_data = dmem.RDATA
            imem.RADDR @= iaddr
            imem_data = imem.RDATA
            write = 0
            for i in range(x_len // 8):
                sel = m.Bit(name=f"sel_{i}")
                sel @= core.dcache.req.valid & core.dcache.req.data.mask[i]
                write |= m.zext_to(m.mux(
                    [dmem_data, core.dcache.req.data.data],
                    sel
                )[8 * i:8 * (i + 1)], 32) << (8 * i)
            core.RESET @= m.reset(state.O == INIT)
            core.icache.resp.valid @= state.O == RUN
            core.dcache.resp.valid @= state.O == RUN
            core.icache.resp.data.data @= m.Register(m.UInt[x_len])()(imem_data)
            core.dcache.resp.data.data @= m.Register(m.UInt[x_len])()(dmem_data)
            chunk = m.mux(_hex, cntr)
            imem.WADDR @= m.zext_to(cntr, 20)
            imem.WDATA @= chunk
            imem.WE @= m.enable(state.O == INIT)
            dmem.WADDR @= m.mux([daddr, m.zext_to(cntr, 20)], state.O == RUN)
            dmem.WDATA @= m.mux([write, chunk], state.O == RUN)
            dmem.WE @= m.enable(
                (state.O == INIT) | (core.dcache.req.valid &
                                     core.dcache.req.data.mask.reduce_or())
            )
            state.I @= state.O
            cycle.I @= cycle.O
            with m.when(state.O == RUN):
                cycle.I @= cycle.O + 1
            with m.elsewhen(done):
                state.I @= RUN
            debug = False
            if debug:
                m.display("LOADMEM[%x] <= %x", cntr * (x_len // 8),
                          chunk).when(m.posedge(io.CLK)).if_(state.O == INIT)
                m.display("INST[%x] => %x", iaddr * (x_len // 8),
                          dmem_data).when(m.posedge(io.CLK)).if_(
                              (state.O == RUN) & core.icache.req.valid)
                m.display("MEM[%x] <= %x", daddr * (x_len // 8),
                          write).when(m.posedge(io.CLK)).if_(
                              (state.O == RUN) & core.dcache.req.valid &
                              core.dcache.req.data.mask.reduce_or())
                m.display("MEM[%x] => %x", daddr * (x_len // 8),
                          dmem_data).when(m.posedge(io.CLK)).if_(
                              (state.O == RUN) & core.dcache.req.valid &
                              ~core.dcache.req.data.mask.reduce_or())
                m.display("cycles: %d", cycle.O).when(m.posedge(io.CLK)).if_(
                    io.done.value() == 1)
            f.assert_immediate(cycle.O < test.maxcycles)
            io.done @= core.host.tohost != 0
            f.assert_immediate((core.host.tohost >> 1) == 0,
                               failure_msg=("* tohost: %d *", core.host.tohost))
    tester = ResetTester(DUT, DUT.CLK)
    tester.reset()
    tester.wait_until_high(DUT.done)
    tester.compile_and_run(
        "verilator",
        magma_output="mlir-verilog",
        magma_opts={
            "flatten_all_tuples": True,
            "disallow_local_variables": True,
            "check_circt_opt_version": False,
        },
        flags=[
            '-Wno-unused',
            '-Wno-PINCONNECTEMPTY',
            '-Wno-undriven',
            '--assert',
        ],
    )