def METHOD_NAME(num, network):
    netPort = network.getNextPort()
    cpu = sst.Component("cpu_%d"%num, "memHierarchy.streamCPU")
    cpu.addParams({
        "commFreq": 1,
        "memSize": mem_size - 1,
        "num_loadstore": niter,
        })
    iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface")
    l1 = sst.Component("l1_%d"%num, "memHierarchy.Cache")
    l1.addParams({
        "debug": debug,
        "debug_level" : debug_level,
        "cache_size": "2KiB",
        "access_latency_cycles" : 4,
        "cache_frequency": "1GHz",
        "associativity" : 4,
        "cache_line_size": 64,
        "L1": 1,
        "network_bw" : netBW,
        })
    cpuLink = sst.Link("cpu-cache-%d"%num)
    cpuLink.connect( (iface, "port", "500ps"), (l1, "high_network_0", "500ps"))
    rtrLink = sst.Link("L1-net-%d"%num)
    rtrLink.connect( (l1, "directory", "500ps"), (network.rtr, "port%d"%netPort, "500ps") )