def METHOD_NAME():
    class _Top(m.Circuit):
        name = "test_inline_verilog2_passthrough_wire"
        T = m.AnonProduct[dict(x=m.Bit, y=m.Bits[4])]
        io = m.IO(I=m.In(T), O=m.Out(T))
        io.O @= io.I
        m.inline_verilog2("assert {io.I.y[0]} == {io.I.y[1]}")
        m.inline_verilog2("assert {io.I.y[1:3]} == {io.I.y[2:4]}")
    _compile_and_check(_Top)