def METHOD_NAME():
    nonlocal dini
    nonlocal douti
    if c0.width:
        widthn = int(c0.width.msb.value) - int(c0.width.lsb.value) + 1
    else:
        widthn = 1
    # Connect to clock net, not general I/O
    if c0.name in iclks:
        return 'clk'
    elif type(c0) is pyverilog.vparser.ast.Input:
        if c0.width:
            slice_ = '%u:%u' % (dini + widthn - 1, dini)
        else:
            slice_ = dini
        dini += widthn
        assert dini <= dinn
        return 'din[%s]' % slice_
    elif type(c0) is pyverilog.vparser.ast.Output:
        if c0.width:
            slice_ = '%u:%u' % (douti + widthn - 1, douti)
        else:
            slice_ = douti
        douti += widthn
        assert douti <= doutn
        return 'dout[%s]' % slice_
    else:
        assert 0