def METHOD_NAME(self, valid, data_in):
    assert len(data_in) == self.interconnect_input_ports, "Should feed proper length data"
    for i in range(self.banks):
        self.data_out[i] = [0 for z in range(self.fw_int)]
        # self.data_out[i] = [0] * len(data_in[0])
    for i in range(self.interconnect_input_ports):
        if (valid[i]):
            to_get = self.addr_gens[i]
            if (self.banks == 1):
                self.data_out[0] = data_in[i]
                break
            else:
                self.data_out[to_get.get_address() >> (self.mem_addr_width)] = data_in[i]
    return self.data_out