def METHOD_NAME(self):
    self.bitcell = factory.create(module_type="rom_base_cell")
    # Adds nmos_lower,nmos_upper to the module
    self.ptx_width = self.tx_size * drc("minwidth_tx")
    self.nmos = factory.create(module_type="ptx",
                                width=self.ptx_width)
    # Space it in the center
    self.nmos_lower = self.add_inst(name="mux_tx1",
                                    mod=self.nmos)
    self.connect_inst(["bl", "sel", "bl_out", "gnd"])