def METHOD_NAME():
    # See #1133 (https://github.com/phanrahan/magma/issues/1133).
    class _Top(m.Circuit):
        name = "test_inline_verilog2_wire_insertion_bad_verilog"
        io = m.IO(I=m.In(m.Bits[32]), O=m.Out(m.Bit))
        m.inline_verilog2("`ifdef LOGGING_ON")
        m.inline_verilog2("$display(\"%x\", {io.I[0]});")
        m.inline_verilog2("`endif LOGGING_ON")
        io.O @= io.I[0]
    _compile_and_check(_Top)