def METHOD_NAME(kernel_xml):
    """Parse an XML file to get the names of AXI ports in a design.
    The argument is the filename for a `kernel.xml` file that is also an
    input to the Xilinx `.xo` packaging step (which describes the
    physical ports in the design and how the logical arguments are
    mapped onto these ports). We extract the names of all AXI master
    ports.
    """
    tree = ET.parse(kernel_xml)
    root = tree.getroot()
    for port in root.iter("port"):
        if port.attrib["mode"] == "master":
            yield port.attrib["name"]