def METHOD_NAME(segmk, ps, site, actual_ps):
    # all of these bits are inverted
    ks = [
        ('IS_CLKARDCLK_INVERTED', 'ZINV_CLKARDCLK'),
        ('IS_CLKBWRCLK_INVERTED', 'ZINV_CLKBWRCLK'),
        ('IS_REGCLKARDRCLK_INVERTED', 'ZINV_REGCLKARDRCLK'),
        ('IS_REGCLKB_INVERTED', 'ZINV_REGCLKB'),
        ('IS_ENARDEN_INVERTED', 'ZINV_ENARDEN'),
        ('IS_ENBWREN_INVERTED', 'ZINV_ENBWREN'),
        ('IS_RSTRAMARSTRAM_INVERTED', 'ZINV_RSTRAMARSTRAM'),
        ('IS_RSTRAMB_INVERTED', 'ZINV_RSTRAMB'),
        ('IS_RSTREGARSTREG_INVERTED', 'ZINV_RSTREGARSTREG'),
        ('IS_RSTREGB_INVERTED', 'ZINV_RSTREGB'),
    ]
    for param, tagname in ks:
        # The CLK inverts sometimes are changed during synthesis, resulting
        # in addition inversions.  Take this into account.
        if param in actual_ps:
            tag = 1 ^ verilog.parsei(actual_ps[param])
        elif param == 'IS_REGCLKARDRCLK_INVERTED':
            if verilog.parsei(ps['DOA_REG']):
                # When DOA_REG == 1, REGCLKARDRCLK follows the CLKARDCLK setting.
                tag = 1 ^ verilog.parsei(actual_ps['IS_CLKARDCLK_INVERTED'])
            else:
                # When DOA_REG == 0, REGCLKARDRCLK is always inverted.
                tag = 0
            segmk.add_site_tag(site, tagname, tag)
        elif param == 'IS_REGCLKB_INVERTED':
            if verilog.parsei(ps['DOB_REG']):
                # When DOB_REG == 1, REGCLKB follows the CLKBWRCLK setting.
                tag = 1 ^ verilog.parsei(actual_ps['IS_CLKBWRCLK_INVERTED'])
            else:
                # When DOB_REG == 0, REGCLKB is always inverted.
                tag = 0
        else:
            tag = 1 ^ verilog.parsei(ps[param])
        segmk.add_site_tag(site, tagname, tag)