def METHOD_NAME():
    class _Top(m.Circuit):
        name = "inline_verilog2_share_default_clocks"
        io = m.IO(x=m.In(m.Bit), y=m.In(m.Bit)) + m.ClockIO(has_reset=True)
        clk = m.Clock()
        rst = m.Reset()
        m.inline_verilog2(
            "assert property (@(posedge {clk}) "
            "disable iff (! {rst}) {io.x} |-> ##1 {io.y});"
        )
        m.inline_verilog2(
            "assert property (@(posedge {clk}) "
            "disable iff (! {rst}) {io.x} |-> ##1 {io.y});"
        )
    _compile_and_check(_Top)