def METHOD_NAME():
    name = f'ckt_{get_test_id()}'.upper()
    netlist = ota_six(name)
    constraints = [
        {"constraint": "PowerPorts", "ports": ["VCCX"]},
        {"constraint": "GroundPorts", "ports": ["VSSX"]},
        {"constraint": "ConfigureCompiler", "auto_constraint": False}
    ]
    example = build_example(name, netlist, constraints)
    generate_hierarchy(example, name, out_path, False, pdk_path)
    gen_const_path = out_path / f'{name}.verilog.json'
    with open(gen_const_path, "r") as fp:
        gen_const = next(x for x in json.load(fp)['modules'] if x['name'] == name)["constraints"]
        gen_const = [c for c in gen_const if not isinstance(c, constraint.GroupBlocks)]
        assert len(gen_const) == 2, f"{gen_const}"
    clean_data(name)