def METHOD_NAME(self):
    """ Create the module instances used in this design """
    self.cell_inst = {}
    for col in range(self.column_size):
        for row in range(self.row_size):
            name = "bit_r{0}_c{1}".format(row, col)
            self.cell_inst[row, col]=self.add_inst(name=name,
                                                   mod=self.cell)
            self.connect_inst(self.get_bitcell_pins(row, col))
            # If it is a "core" cell, it could be trimmed for sim time
            if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
                self.trim_insts.add(name)