def METHOD_NAME():
    class Logic(m.Generator2):
        def __init__(self, width=None):
            T = m.Bit if width is None else m.Bits[width]
            self.io = io = m.IO(I=m.In(T), O=m.Out(T))
            io.O @= ~io.I
    class LogicAsserts(m.Generator2):
        def __init__(self, dut, width=None):
            T = m.Bit if width is None else m.Bits[width]
            self.width = width
            self.io = io = m.IO(I=m.In(T), O=m.In(T), other=m.In(m.Bit))
            m.inline_verilog("{I} {O} {other}", I=io.I, O=io.O, other=io.other)
            self.bind2_args = [m.bits(dut.I)[0]]
    m.bind2(Logic, LogicAsserts)
    class Top(m.Circuit):
        T = m.Bits[2]
        io = m.IO(I=m.In(T), O=m.Out(T))
        I = m.bits(list(map(lambda x: Logic()()(x), io.I)))
        io.O @= Logic(2)()(I)
    opts = {
        "output": "mlir",
        "use_native_bind_processor": True,
    }
    _assert_compilation(Top, "test_bind2_generator", "mlir", opts)
    class _CheckLogicAssertsAreBoundModulesPass(CircuitPass):
        def __call__(self, defn):
            if not isinstance(defn, LogicAsserts):
                return
            assert is_bound_module(defn)
    assert not is_bound_module(Top)
    _CheckLogicAssertsAreBoundModulesPass(Top).run()