def METHOD_NAME(self):
    """ Create the module instances used in this design """
    self.cell_inst = {}
    self.array_layout = []
    alternate_bitcell = (self.rows + 1) % 2
    for row in range(self.rows + 2):
        row_layout = []
        name="rca_{0}".format(row)
        # Top/bottom cell are always dummy cells.
        # Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
        # Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
        if (row < self.rows + 1 and row > 0):
            if alternate_bitcell == 0:
                row_layout.append(self.rowend1)
                self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
                self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
                alternate_bitcell = 1
            else:
                row_layout.append(self.rowend2)
                self.cell_inst[row] = self.add_inst(name=name, mod=self.rowend2)
                self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
                alternate_bitcell = 0
        elif (row == 0):
            row_layout.append(self.bottom_corner)
            self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
            self.connect_inst(self.get_corner_pins())
        elif (row == self.rows + 1):
            row_layout.append(self.top_corner)
            self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
            self.connect_inst(self.get_corner_pins())
        self.array_layout.append(row_layout)