def METHOD_NAME():
    # Check that 2 modules that differ only in their inlined modules (e.g. one
    # displays in "%d" format, the other "%x") are uniquified.
    class Foo(m.Circuit):
        io = m.IO(I=m.In(m.Bit))
        m.inline_verilog2("always @(*) $display(\"%d\\n\", {io.I});")
    Bar = Foo
    class Foo(m.Circuit):
        io = m.IO(I=m.In(m.Bit))
        m.inline_verilog2("always @(*) $display(\"%x\\n\", {io.I});")
    class _Top(m.Circuit):
        name = "inline_verilog2_uniquification"
        io = m.IO(I=m.In(m.Bit))
        Bar()(io.I)
        Foo()(io.I)
    _compile_and_check(_Top)