def METHOD_NAME(m):
    '''Return input signals containing clock like names'''
    ret = set()
    for port in m.portlist.ports:
        c0 = port_child(port)
        if type(c0) is pyverilog.vparser.ast.Input and c0.name.lower().find(
                'clk') >= 0:
            ret.add(c0.name)
    return ret