def METHOD_NAME(self, board: AbstractBoard) -> None:
    requires(coherence_protocol_required=CoherenceProtocol.MI_EXAMPLE)
    self.ruby_system = RubySystem()
    # Ruby's global network.
    self.ruby_system.network = SimplePt2Pt(self.ruby_system)
    # MI Example users 5 virtual networks.
    self.ruby_system.number_of_virtual_networks = 5
    self.ruby_system.network.number_of_virtual_networks = 5
    # There is a single global list of all of the controllers to make it
    # easier to connect everything to the global network. This can be
    # customized depending on the topology/network requirements.
    # Create one controller for each L1 cache (and the cache mem obj.)
    # Create a single directory controller (Really the memory cntrl).
    self._controllers = []
    for i, core in enumerate(board.get_processor().get_cores()):
        cache = L1Cache(
            size=self._size,
            assoc=self._assoc,
            network=self.ruby_system.network,
            core=core,
            cache_line_size=board.get_cache_line_size(),
            target_isa=board.get_processor().get_isa(),
            clk_domain=board.get_clock_domain(),
        )
        cache.sequencer = RubySequencer(
            version=i,
            dcache=cache.cacheMemory,
            clk_domain=cache.clk_domain,
        )
        if board.has_io_bus():
            cache.sequencer.connectIOPorts(board.get_io_bus())
        cache.ruby_system = self.ruby_system
        core.connect_icache(cache.sequencer.in_ports)
        core.connect_dcache(cache.sequencer.in_ports)
        core.connect_walker_ports(
            cache.sequencer.in_ports, cache.sequencer.in_ports
        )
        # Connect the interrupt ports
        if board.get_processor().get_isa() == ISA.X86:
            int_req_port = cache.sequencer.interrupt_out_port
            int_resp_port = cache.sequencer.in_ports
            core.connect_interrupt(int_req_port, int_resp_port)
        else:
            core.connect_interrupt()
        cache.ruby_system = self.ruby_system
        self._controllers.append(cache)
    # Create the directory controllers
    self._directory_controllers = []
    for range, port in board.get_mem_ports():
        dir = Directory(
            self.ruby_system.network,
            board.get_cache_line_size(),
            range,
            port,
        )
        dir.ruby_system = self.ruby_system
        self._directory_controllers.append(dir)
    # Create the DMA Controllers, if required.
    self._dma_controllers = []
    if board.has_dma_ports():
        dma_ports = board.get_dma_ports()
        for i, port in enumerate(dma_ports):
            ctrl = DMAController(
                self.ruby_system.network, board.get_cache_line_size()
            )
            ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
            ctrl.ruby_system = self.ruby_system
            ctrl.dma_sequencer.ruby_system = self.ruby_system
            self._dma_controllers.append(ctrl)
    self.ruby_system.num_of_sequencers = len(self._controllers) + len(
        self._dma_controllers
    )
    # Connect the controllers.
    self.ruby_system.controllers = self._controllers
    self.ruby_system.directory_controllers = self._directory_controllers
    if len(self._dma_controllers) != 0:
        self.ruby_system.dma_controllers = self._dma_controllers
    self.ruby_system.network.connectControllers(
        self._controllers
        + self._directory_controllers
        + self._dma_controllers
    )
    self.ruby_system.network.setup_buffers()
    # Set up a proxy port for the system_port. Used for load binaries and
    # other functional-only things.
    self.ruby_system.sys_port_proxy = RubyPortProxy()
    board.connect_system_port(self.ruby_system.sys_port_proxy.in_ports)