def METHOD_NAME(cls):
    # for now only allow Bit or Array(n, Bit)
    for name, port in cls.interface.ports.items():
        if isinstance(port, ArrayKind):
            if not isinstance(port.T, BitKind):
                print('Error: Argument', port, 'must be a an Array(n,Bit)')
    s = 'module {} :\n'.format(cls.__name__)
    for name, port in cls.interface.ports.items():
        if port.is_input():
            direction = "output"
        elif port.is_output():
            direction = "input"
        else:
            raise NotImplementedError()  # Does FIRRTL have an inout?
        s += '{} {} : {}\n'.format(direction, name, get_type(port))
    s += "\n"  # Newline after port declaration for readability
    import re
    if cls.firrtl:
        s += cls.firrtl + '\n'
    else:
        # declare a wire for each instance output
        for instance in cls.instances:
            for port in instance.interface.ports.values():
                if port.is_output():
                    s += 'wire {} : {}\n'.format(get_name(port), get_type(port))
        #print('compile instances')
        # emit the structured verilog for each instance
        for instance in cls.instances:
            if getattr(instance, "firrtl_op", False):
                s += compile_primitive(instance)
            else:
                drive_undriven_clock_types_in_inst(cls, instance)
                s += compileinstance(instance)
        # assign to module output arguments
        for input in cls.interface.inputs():
            output = input.value()
            if output:
                iname = get_name(input)
                oname = get_name(output)
                s += '%s <= %s\n' % (iname, oname)
    return "\n  ".join(s.splitlines())