def METHOD_NAME():
    tester = f.SynchronousTester(Queue(4, m.Bits[2]))
    tester.advance_cycle()
    for i in range(4):
        tester.circuit.enq.data = i
        tester.circuit.enq.valid = 1
        tester.circuit.enq.ready.expect(1)
        tester.advance_cycle()
    tester.circuit.enq.valid = 0
    tester.circuit.enq.ready.expect(0)
    for i in range(4):
        tester.circuit.deq.data.expect(i)
        tester.circuit.deq.valid.expect(1)
        tester.circuit.deq.ready = 1
        tester.advance_cycle()
    tester.circuit.deq.valid.expect(0)
    with tempfile.TemporaryDirectory() as tempdir:
        tester.compile_and_run("verilator", magma_output="mlir-verilog",
                               magma_opts={"check_circt_opt_version": False},
                               directory=tempdir)