def METHOD_NAME(self, load_slews):
    """
    Return the analytical model results for the SRAM.
    """
    if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
        debug.warning("In analytical mode, all ports have the timing of the first read port.")
    # Probe set to 0th bit, does not matter for analytical delay.
    self.set_probe('0' * self.bank_addr_size, 0)
    self.create_graph()
    self.set_internal_spice_names()
    self.create_measurement_names()
    port = self.read_ports[0]
    self.graph.get_all_paths('{}{}'.format("clk", port),
                             '{}{}_{}'.format(self.dout_name, port, self.probe_data))
    # Select the path with the bitline (bl)
    bl_name, br_name = self.get_bl_name(self.graph.all_paths, port)
    bl_path = [path for path in self.graph.all_paths if bl_name in path][0]
    # Set delay/power for slews and loads
    port_data = self.get_empty_measure_data_dict()
    power = self.analytical_power(load_slews)
    debug.info(1, 'Slew (ns), Load (fF), Delay(ns), Slew(ns)')
    max_delay = 0.0
    for load,slew in load_slews:
        # Calculate delay based on slew and load
        # Calculations expect Farad, input is Femto-Farad
        load_farad = load*1e-15
        #load_farad = 0.052275e-12
        slew = 0
        path_delays = self.graph.get_timing(bl_path, self.corner, slew, load_farad, self.params)
        total_delay = self.sum_delays(path_delays)
        delay_ns = total_delay.delay/1e-9
        slew_ns = total_delay.slew/1e-9
        max_delay = max(max_delay, total_delay.delay)
        debug.info(1,'{}, {}, {}, {}'.format(slew,
                                             load,
                                             delay_ns,
                                             slew_ns))
        # Delay is only calculated on a single port and replicated for now.
        for port in self.all_ports:
            for mname in self.delay_meas_names + self.power_meas_names:
                if "power" in mname:
                    port_data[port][mname].append(power.dynamic)
                elif "delay" in mname and port in self.read_ports:
                    port_data[port][mname].append(total_delay.delay / 1e-9)
                elif "slew" in mname and port in self.read_ports:
                    port_data[port][mname].append(total_delay.slew / 1e-9)
    # Margin for error in period. Calculated by averaging required margin for a small and large
    # memory. FIXME: margin is quite large, should be looked into.
    period_margin = 1.85
    sram_data = {"min_period": (max_delay / 1e-9) * 2 * period_margin,
                 "leakage_power": power.leakage}
    debug.info(2, "SRAM Data:\n{}".format(sram_data))
    debug.info(2, "Port Data:\n{}".format(port_data))
    return (sram_data, port_data)