def METHOD_NAME(self):
    assert hasattr(self, "reset_address")
    verilog_filename = os.path.join(self.platform.output_dir, "gateware", "minerva.v")
    self.elaborate(
        reset_address    = self.reset_address,
        with_icache      = True,
        with_dcache      = True,
        with_muldiv      = True,
        verilog_filename = verilog_filename)
    self.platform.add_source(verilog_filename)
    self.specials += Instance("minerva_cpu", **self.cpu_params)