def METHOD_NAME(self):
    res = ModuleResult.FAILED
    (tseg_base, tseg_limit, tseg_size) = self.cs.cpu.get_TSEG()
    self.logger.log("[*] TSEG      : 0x{:016X} - 0x{:016X} (size = 0x{:08X})".format(tseg_base, tseg_limit, tseg_size))
    if self.cs.cpu.check_SMRR_supported():
        (smram_base, smram_limit, smram_size) = self.cs.cpu.get_SMRR_SMRAM()
        self.logger.log("[*] SMRR range: 0x{:016X} - 0x{:016X} (size = 0x{:08X})\n".format(smram_base, smram_limit, smram_size))
    else:
        smram_base = 0
        smram_limit = 0
        self.logger.log("[*] SMRR is not supported\n")
    self.logger.log("[*] Checking TSEG range configuration..")
    if (0 == smram_base) and (0 == smram_limit):
        res = ModuleResult.WARNING
        self.logger.log_warning("TSEG is properly configured but can't determine if it covers entire SMRAM")
    else:
        if (tseg_base <= smram_base) and (smram_limit <= tseg_limit):
            self.logger.log_good("TSEG range covers entire SMRAM")
            if self.check_tseg_locks() == ModuleResult.PASSED:
                res = ModuleResult.PASSED
                self.logger.log_passed("TSEG is properly configured. SMRAM is protected from DMA attacks")
            else:
                self.logger.log_failed("TSEG is properly configured, but the configuration is not locked.")
        else:
            self.logger.log_bad("TSEG range doesn't cover entire SMRAM")
            self.logger.log_failed("TSEG is not properly configured. Portions of SMRAM may be vulnerable to DMA attacks")
    return res