def METHOD_NAME(self, board: AbstractBoard) -> None:
    if board.has_coherent_io():
        self._setup_coherent_io_bridge(board)
    for core in board.get_processor().get_cores():
        core.connect_icache(self.membus.cpu_side_ports)
        core.connect_dcache(self.membus.cpu_side_ports)
        core.connect_walker_ports(
            self.membus.cpu_side_ports, self.membus.cpu_side_ports
        )
        if board.get_processor().get_isa() == ISA.X86:
            int_req_port = self.membus.mem_side_ports
            int_resp_port = self.membus.cpu_side_ports
            core.connect_interrupt(int_req_port, int_resp_port)
        else:
            core.connect_interrupt()
    # Set up the system port for functional access from the simulator.
    board.connect_system_port(self.membus.cpu_side_ports)
    for _, port in board.get_memory().get_mem_ports():
        self.membus.mem_side_ports = port