def METHOD_NAME(dtype,
              name="pipeline_test",
              input_device_memory="ddr",
              input_device_bank="0",
              output_device_memory="ddr",
              output_device_bank="1"):
    n = dace.symbol("N")
    k = dace.symbol("K")
    m = dace.symbol("M")
    sdfg = dace.SDFG(name)
    pre_state = sdfg.add_state(name + "_pre")
    state = sdfg.add_state(name)
    post_state = sdfg.add_state(name + "_post")
    sdfg.add_edge(pre_state, state, dace.InterstateEdge())
    sdfg.add_edge(state, post_state, dace.InterstateEdge())
    _, desc_input_host = sdfg.add_array("a", (n, k, m), dtype)
    _, desc_output_host = sdfg.add_array("b", (n, k, m), dtype)
    desc_input_device = copy.copy(desc_input_host)
    desc_input_device.storage = dace.StorageType.FPGA_Global
    desc_input_device.location["memorytype"] = input_device_memory
    desc_input_device.location["bank"] = input_device_bank
    desc_input_device.transient = True
    desc_output_device = copy.copy(desc_output_host)
    desc_output_device.storage = dace.StorageType.FPGA_Global
    desc_output_device.location["memorytype"] = output_device_memory
    desc_output_device.location["bank"] = output_device_bank
    desc_output_device.transient = True
    sdfg.add_datadesc("a_device", desc_input_device)
    sdfg.add_datadesc("b_device", desc_output_device)
    # Host to device
    pre_read = pre_state.add_read("a")
    pre_write = pre_state.add_write("a_device")
    pre_state.add_memlet_path(pre_read, pre_write, memlet=dace.Memlet("a_device[0:N, 0:K, 0:M]"))
    # Device to host
    post_read = post_state.add_read("b_device")
    post_write = post_state.add_write("b")
    post_state.add_memlet_path(post_read, post_write, memlet=dace.Memlet("b[0:N, 0:K, 0:M]"))
    # Compute state
    read_memory = state.add_read("a_device")
    write_memory = state.add_write("b_device")
    # Memory streams
    sdfg.add_stream("a_stream", dtype, storage=dace.StorageType.FPGA_Local, transient=True)
    sdfg.add_stream("b_stream", dtype, storage=dace.StorageType.FPGA_Local, transient=True)
    produce_input_stream = state.add_write("a_stream")
    consume_input_stream = state.add_read("a_stream")
    produce_output_stream = state.add_write("b_stream")
    consume_output_stream = state.add_write("b_stream")
    entry, exit = state.add_pipeline(name, {
        "n": "0:N",
        "k": "0:K",
        "m": "0:M",
    },
                                     schedule=dace.ScheduleType.FPGA_Device,
                                     init_size=k * m,
                                     init_overlap=True,
                                     drain_size=k * m,
                                     drain_overlap=True,
                                     additional_iterators={'user_var': 0})
    # for the sake of testing, use the additional user_var to set to zero the last element of each row
    tasklet = state.add_tasklet(
        name, {"_in"}, {"_out"}, """\