def METHOD_NAME(platform, variant="standard"):
    vdir = get_data_mod("cpu", "blackparrot").data_location
    bp_litex = os.path.join(vdir, "bp_litex")
    filename = os.path.join(bp_litex, {
        "standard": "flist.fpga",
        "sim"     : "flist.verilator"
    }[variant])
    with open(filename) as openfileobject:
        for line in openfileobject:
            temp = line
            if (temp[0] == '/' and temp[1] == '/'):
                continue
            elif ("+incdir+" in temp) :
                s1 = line.find('$')
                vdir = os.path.expandvars(line[s1:]).strip()
                platform.add_verilog_include_path(vdir)
            elif (temp[0]=='$') :
                vdir = os.path.expandvars(line).strip()
                platform.add_source(vdir, "systemverilog")
            elif (temp[0] == '/'):
                assert("No support for absolute path for now")