def METHOD_NAME(wb):
    """ Finds bitslip and delay values that can be used with the implemented DDR design."""
    nbitslips = 8
    ndelays = 32
    nmodules = 2
    nwords = 16
    final_bitslip = None
    final_delay = None
    for bitslip in range(nbitslips):
        print("bitslip {:d}: |".format(bitslip), end="")
        for delay in range(ndelays):
            for module in range(nmodules):
                wb.regs.ddrphy_dly_sel.write(1 << module)
                wb.regs.ddrphy_rdly_dq_rst.write(1)
                wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
                for i in range(bitslip):
                    wb.regs.ddrphy_rdly_dq_bitslip.write(1)
                for i in range(delay):
                    wb.regs.ddrphy_rdly_dq_inc.write(1)
            write_pattern(wb, nwords)
            errors = check_pattern(wb, nwords)
            if errors:
                print("..|", end="")
            else:
                print("{:02d}|".format(delay), end="")
                final_bitslip = bitslip if final_bitslip is None else final_bitslip
                final_delay = delay if final_delay is None else final_delay
            sys.stdout.flush()
        print("")
    assert final_bitslip is not None and final_delay is not None, "bitslip/delay values not found"
    return final_bitslip, final_delay