def METHOD_NAME(self,
                            banks_tall,
                            banks_wide,
                            macro_width,
                            macro_depth):
    '''
    Hook up the set of single port memories
    '''
    self._sub_addr = self.var("addr_macro", self.addr_width_macro)
    self.wire(self._sub_addr, self._addr[self.addr_width_macro - 1, 0])
    # Hook up the grid of SRAM banks
    for i in range(banks_tall):
        for j in range(banks_wide):
            self.add_child(f"sram_d{i}_w{j}", SRAMStub(macro_width, macro_depth))
            self.wire(self[f"sram_d{i}_w{j}"].ports.i_clk, self._clk)
            self.wire(self[f"sram_d{i}_w{j}"].ports.i_rst_n, self._rst_n)
            self.wire(self[f"sram_d{i}_w{j}"].ports.i_addr, self._sub_addr)
            if (banks_tall > 1):
                self.wire(self[f"sram_d{i}_w{j}"].ports.i_wen,
                          self._wen & (self._addr[self.full_addr - 1,
                                                  self.addr_width_macro] == i))
                self.wire(self[f"sram_d{i}_w{j}"].ports.i_cen,
                          (self._ren | self._wen) & (self._addr[self.full_addr - 1,
                                                     self.addr_width_macro] == i))
            else:
                self.wire(self[f"sram_d{i}_w{j}"].ports.i_wen, self._wen)
                self.wire(self[f"sram_d{i}_w{j}"].ports.i_cen, (self._ren | self._wen))
            # Send the data across horizontally based on j and the macro width
            self.wire(self[f"sram_d{i}_w{j}"].ports.i_data,
                      self._wr_data[((j + 1) * macro_width) - 1, j * macro_width])
    for i in range(banks_tall):
        if (banks_wide > 1):
            self.wire(self._memory_space[i],
                      concat(*[self[f"sram_d{i}_w{j}"].ports.o_data
                               for j in range(banks_wide)]))
        else:
            self.wire(self._memory_space, self[f"sram_d{i}_w{j}"].ports.o_data)
    if (banks_tall > 1):
        self.wire(self._rd_data, self._memory_space[self._bank_sel_reg])
    else:
        self.wire(self._rd_data, self._memory_space)
    return 0