def METHOD_NAME(
    input_ckt: pathlib.Path,
    design_name: str,
    pdk_dir: pathlib.Path,
    config_path: pathlib.Path,
    flat=0
):
    """
    Reads input spice file, converts to a graph format and create hierarchies in the graph
    Parameters
    ----------
    input_ckt : input circuit path
        DESCRIPTION.
    design_name : name of top level subckt in design
        DESCRIPTION.
    flat : TYPE, flat/hierarchical
        DESCRIPTION. The default is 0.
    Returns
    -------
    updated_ckt_list : list of reduced graphs for each subckt
        DESCRIPTION. reduced graphs are subckts after identification of hierarchies
    library : TYPE, list of library graphs
        DESCRIPTION.libraries are used to create hierarchies
    """
    logger.info("Starting topology identification...")
    input_dir = input_ckt.parents[0]
    logger.debug(f"Reading subckt {input_ckt}")
    # TODO: flatten should be separate pass
    ckt_parser = read_models(pdk_dir, config_path)
    with open(input_ckt) as f:
        lines = f.read()
    ckt_parser.parse(lines)
    library = read_lib(pdk_dir, config_path)
    primitive_library = order_lib(library)
    const_parse = ConstraintParser(pdk_dir, input_dir)
    # TODO FLAT implementation
    create_data = CreateDatabase(ckt_parser, const_parse)
    ckt_data = create_data.read_inputs(design_name)
    create_data.add_generators(pdk_dir)
    logger.debug(f"START preprocessing from top {design_name.upper()}")
    preprocess_stack_parallel(ckt_data, design_name.upper())
    logger.debug("\n###### FINAL CIRCUIT AFTER preprocessing ###### \n")
    logger.debug(ckt_parser)
    return ckt_data, primitive_library