def METHOD_NAME(bus, pads, mode="master", axi_full=False):
    """
    Connect to pads (I/O pins) on the Platform.
    This function connects the AXI bus signals to the respective pads on the Platform, taking into
    account their roles (master or slave) for each channel type.
    Parameters:
        bus      : AXI bus interface.
        pads     : FPGA pad interface.
        mode     : Role for connection (master or slave).
        axi_full : Boolean flag to indicate if AXI full is being used.
    Returns:
        list: List of statements to create the necessary connections.
    """
    assert mode in ["slave", "master"]
    r = []
    def swap_mode(mode): return "master" if mode == "slave" else "slave"
    channel_modes = {
        "aw": mode,
        "w" : mode,
        "b" : swap_mode(mode),
        "ar": mode,
        "r" : swap_mode(mode),
    }
    # Loop to connect each channel.
    for channel, mode in channel_modes.items():
        ch = getattr(bus, channel)
        sig_list = [("valid", 1)] + ch.description.payload_layout + ch.description.param_layout
        if channel in ["w", "r"] and axi_full:
            sig_list += [("last",  1)]
        # Loop to connect each signal within a channel.
        for name, width in sig_list:
            if (name == "dest"):
                continue # No DEST.
            if (channel == "w") and (name == "id") and (bus.version == "axi4"):
                continue # No WID on AXI4.
            sig  = getattr(ch, name)
            pad  = getattr(pads, channel + name)
            if mode == "master":
                r.append(pad.eq(sig))
            else:
                r.append(sig.eq(pad))
        for name, width in [("ready", 1)]:
            sig  = getattr(ch, name)
            pad  = getattr(pads, channel + name)
            if mode == "master":
                r.append(sig.eq(pad))
            else:
                r.append(pad.eq(sig))
    return r