def METHOD_NAME(self, verilog_name):
    """ Write a behavioral Verilog model. """
    self.vf = open(verilog_name, "w")
    self.vf.write("// OpenROM ROM model\n")
    #basic info
    self.vf.write("// Words: {0}\n".format(self.num_words))
    self.vf.write("// Word size: {0}\n".format(self.word_size))
    self.vf.write("// Word per Row: {0}\n".format(self.words_per_row))
    self.vf.write("// Data Type: {0}\n".format(self.data_type))
    self.vf.write("// Data File: {0}\n".format(self.rom_data))
    self.vf.write("\n")
    try:
        self.vdd_name = spice["power"]
    except KeyError:
        self.vdd_name = "vdd"
    try:
        self.gnd_name = spice["ground"]
    except KeyError:
        self.gnd_name = "gnd"
    #add multiple banks later
    self.vf.write("module {0}(\n".format(self.name))
    self.vf.write("`ifdef USE_POWER_PINS\n")
    self.vf.write("    {},\n".format(self.vdd_name))
    self.vf.write("    {},\n".format(self.gnd_name))
    self.vf.write("`endif\n")
    for port in self.all_ports:
        if port in self.read_ports:
            self.vf.write("// Port {0}: R\n".format(port))
            self.vf.write("    clk{0},csb{0},addr{0},dout{0}".format(port))
        # Continue for every port on a new line
        if port != self.all_ports[-1]:
            self.vf.write(",\n")
    self.vf.write("\n  );\n\n")
    self.vf.write("  parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
    self.vf.write("  parameter ADDR_WIDTH = {0} ;\n".format(math.ceil(math.log(self.num_words,2))))
    self.vf.write("  parameter ROM_DEPTH = 1 << ADDR_WIDTH;\n")
    self.vf.write("  // FIXME: This delay is arbitrary.\n")
    self.vf.write("  parameter DELAY = 3 ;\n")
    self.vf.write("  parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n")
    self.vf.write("  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n")
    self.vf.write("\n")
    self.vf.write("`ifdef USE_POWER_PINS\n")
    self.vf.write("    inout {};\n".format(self.vdd_name))
    self.vf.write("    inout {};\n".format(self.gnd_name))
    self.vf.write("`endif\n")
    for port in self.all_ports:
        self.add_inputs_outputs(port)
    self.vf.write("\n")
    # This is the memory array itself
    self.vf.write("  reg [DATA_WIDTH-1:0]    mem [0:ROM_DEPTH-1];\n\n")
    #write memory init here
    self.vf.write(f"  initial begin\n")
    if self.data_type == "bin":
        self.vf.write(f"    $readmemb(\"{self.rom_data}\",mem,0,ROM_DEPTH-1);\n")
    elif self.data_type == "hex":
        self.vf.write(f"    $readmemh(\"{self.rom_data}\",mem,0, ROM_DEPTH-1);\n")
    else:
        raise ValueError(f"Data type: {self.data_type} is not supported!")
    self.vf.write(f"  end\n\n")
    for port in self.all_ports:
        self.register_inputs(port)
    for port in self.all_ports:
        if port in self.read_ports:
            self.add_read_block(port)
    self.vf.write("\n")
    self.vf.write("endmodule\n")
    self.vf.close()