def METHOD_NAME():
    from litex.build.parser import LiteXArgumentParser
    parser = LiteXArgumentParser(platform=xilinx_kcu105.Platform, description="LiteX SoC on KCU105.")
    parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
    ethopts = parser.target_group.add_mutually_exclusive_group()
    ethopts.add_argument("--with-ethernet",   action="store_true",    help="Enable Ethernet support.")
    ethopts.add_argument("--with-etherbone",  action="store_true",    help="Enable Etherbone support.")
    parser.add_target_argument("--eth-ip",    default="192.168.1.50", help="Ethernet/Etherbone IP address.")
    parser.add_target_argument("--with-pcie", action="store_true",    help="Enable PCIe support.")
    parser.add_target_argument("--driver",    action="store_true",    help="Generate PCIe driver.")
    parser.add_target_argument("--with-sata", action="store_true",    help="Enable SATA support (over SFP2SATA).")
    args = parser.parse_args()
    soc = BaseSoC(
        sys_clk_freq   = args.sys_clk_freq,
        with_ethernet  = args.with_ethernet,
        with_etherbone = args.with_etherbone,
        eth_ip         = args.eth_ip,
        with_pcie      = args.with_pcie,
        with_sata      = args.with_sata,
        **parser.soc_argdict
	)
    builder = Builder(soc, **parser.builder_argdict)
    if args.build:
        builder.build(**parser.toolchain_argdict)
    if args.driver:
        generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
    if args.load:
        prog = soc.platform.create_programmer()
        prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))