def METHOD_NAME(self, chipstream):
    shreg  = []
    offset = 0
    synced = False
    prev   = 0
    bits   = []
    while True:
        while len(shreg) < 64:
            try:
                shreg.append(next(chipstream))
            except StopIteration:
                return
        synced_now = False
        for sync_offset in (0, 1):
            if shreg[sync_offset:sync_offset + 16] == [0,1,0,0,0,1,0,0,1,0,0,0,1,0,0,1]:
                if not synced or sync_offset != 0:
                    self._log("sync=K.A1 chip-off=%d", offset + sync_offset)
                offset += sync_offset + 16
                shreg   = shreg[sync_offset + 16:]
                synced  = True
                prev    = 1
                bits    = []
                yield (1, 0xA1)
                synced_now = True
            if synced_now: break
        if synced_now:
            continue
        elif not synced and len(shreg) >= 1:
            offset += 1
            shreg   = shreg[1:]
        if synced and len(shreg) >= 2:
            if shreg[0:2] == [0,1]:
                curr = 1
            elif prev == 1 and shreg[0:2] == [0,0]:
                curr = 0
            elif prev == 0 and shreg[0:2] == [1,0]:
                curr = 0
            else:
                synced = False
                self._log("desync chip-off=%d bitno=%d prev=%d cell=%d%d",
                          offset, len(bits), prev, *shreg[0:2])
            if synced:
                offset += 2
                shreg   = shreg[2:]
                prev    = curr
                bits.append(curr)
                if len(bits) == 8:
                    yield (0, sum(bit << (7 - n) for n, bit in enumerate(bits)))
                    bits = []