def METHOD_NAME(self, port, definition):
    if port.is_mixed():
        return self._recurse(port, definition)
    if not port.driven():
        return False
    value = port.value()
    if isinstance(port, Tuple):
        return self._recurse(port, definition)
    if isinstance(port, Array):
        # Avoid recursion when possible (for Array2) by checking the nested
        # array type and only descending if necessary
        # Note(leonardt): If value is anon, we need to check the children
        # via recursion in case the children are named types (since
        # .value() will return Array[N, T.flip()], the anon value may not
        # have the namedtypes in its type)
        if (
            is_clock_or_nested_clock(type(port), _NAMED_TYPES) or
            is_clock_or_nested_clock(type(value), _NAMED_TYPES) or
            (
                value.anon() and
                isinstance(value, AggregateWireable) and
                value.has_elaborated_children()
            )
        ):
            for child, _ in port.connection_iter():
                if not self.METHOD_NAME(child, definition):
                    return False
            return True
        else:
            return self.METHOD_NAME(value, definition)
    if not (isinstance(port, _NAMED_TYPES) or
            isinstance(value, _NAMED_TYPES)):
        return self.METHOD_NAME(value, definition)
    undirected_t = type(port).qualify(Direction.Undirected)
    if issubclass(type(value), undirected_t):
        return self.METHOD_NAME(value, definition)
    port_is_clock_type = isinstance(port, (AsyncReset, AsyncResetN, Clock))
    if port_is_clock_type:
        T = Out(type(port))
    else:
        T = In(type(value))
    with definition.open():
        port.unwire(value)
        in_type, out_type = type(port), type(value)
        if not port_is_clock_type:
            # value is the clock type, flip wrap types
            out_type, in_type = in_type, out_type
        inst = self.define_wrap(T, in_type, out_type)()
        wire(convertbit(value, in_type), getattr(inst, "in"))
        wire(inst.out, convertbit(port, out_type))
    return True