def METHOD_NAME(caplog):
    caplog.set_level(logging.WARN)
    class main(m.Circuit):
        name = "main"
        io = m.IO(I=m.In(m.Bits[2]), O=m.Out(m.Bit))
        and2 = And2()
        m.wire(io.I[1], and2.I1)
    m.compile("build/test_unwired_output", main, "verilog")
    assert check_files_equal(__file__, f"build/test_unwired_output.v",
                             f"gold/test_unwired_output.v")
    assert caplog.records[-2].msg == "main.And2_inst0.I0 not connected"
    assert caplog.records[-1].msg == "main.O is unwired"