def METHOD_NAME(num, network):
    netPort = network.getNextPort()
    mem = sst.Component("mem%d"%num, "memHierarchy.MemController")
    mem.addParams({
        "debug": debug,
        "debug_level" : debug_level,
        "clock" : "1GHz"
        })
    memback = mem.setSubComponent("backend", "memHierarchy.simpleMem")
    memback.addParams({
        "mem_size" : "1MiB"
    })
    dc = sst.Component("dc%d"%num, "memHierarchy.DirectoryController")
    dc.addParams({
        "debug": debug,
        "debug_level" : debug_level,
        "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize
        "clock": "1GHz",
        "network_bw": netBW,
        "addr_range_start" : num * (mem_size // num_mem),
        "addr_range_end" : (num+1) * (mem_size // num_mem) -1,
        })
    memLink = sst.Link("MemDir_%d"%num)
    memLink.connect( (dc, "memory", "500ps"), (mem, "direct_link", "500ps") )
    dcLink = sst.Link("DCNet%d"%num)
    dcLink.connect( (dc, "network", "500ps"), (network.rtr, "port%d"%netPort, "500ps") )