def METHOD_NAME(self, arch):
    proj = angr.Project(os.path.join(location, arch, "veritesting_skm"))
    # start the analysis after the call to lexer_read_line
    state = proj.factory.blank_state(addr=0x4024AE, remove_options={angr.sim_options.UNICORN})
    # set up the structures for the user_input
    byte = claripy.BVS("user_byte", 8)  # Symbolic variable for user_input
    SPACE = claripy.Or((byte == 32), (byte == 9))
    NUM = claripy.And(byte >= 48, byte <= 57)
    NL = byte == 10
    MULOP = claripy.Or(byte == 42, byte == 47)
    ADDOP = claripy.Or(byte == 43, byte == 45)
    constraint = claripy.Or(NUM, ADDOP, MULOP, NL, SPACE)
    state.add_constraints(constraint)
    # set up memory
    LINEPTR = 0xCAFEBABE  # fake addr
    state.memory.store(LINEPTR, byte)
    state.memory.store(LINEPTR + 1, 0)  # NULL term the string!
    # stack
    state.regs.rax = LINEPTR
    state.regs.rbp = 0xDEADBEEF  # STACK
    state.regs.rdi = LINEPTR  # 64 bit Intel calling convention - RDI gets arg0
    simgr = proj.factory.simgr(state, veritesting=True)
    is_successful = 0x402517
    should_abort = 0x402521
    simgr.explore(find=is_successful, avoid=should_abort)
    assert simgr.found