diff --git a/fusesoc/section/__init__.py b/fusesoc/section/__init__.py
index <HASH>..<HASH> 100644
--- a/fusesoc/section/__init__.py
+++ b/fusesoc/section/__init__.py
@@ -235,7 +235,10 @@ Verilog top module      : {top_module}
         args += ['-DVL_PRINTF=printf']
         args += ['-DVM_TRACE=1']
         args += ['-DVM_COVERAGE=0']
-        args += ['-I'+os.getenv('SYSTEMC_INCLUDE')]
+        if os.getenv('SYSTEMC_INCLUDE'):
+            args += ['-I'+os.getenv('SYSTEMC_INCLUDE')]
+        if os.getenv('SYSTEMC'):
+            args += ['-I'+os.path.join(os.getenv('SYSTEMC'),'include')]
         args += ['-Wno-deprecated']
         if os.getenv('SYSTEMC_CXX_FLAGS'):
              args += [os.getenv('SYSTEMC_CXX_FLAGS')]
section/verilator: add $(SYSTEMC)/include to include dirs

Also, only add the SYSTEMC_INCLUDE environment variable to
the include dirs if it's set.