Add missing RV64 instructions in waycontrol comp. for rv6s; all 64-bit tests now pass!
MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_waycontrol.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_waycontrol.h
@@ -27,17 +27,21 @@ private:
// Arithmetic-immediate instructions
case RVInstr::ADDI: case RVInstr::SLTI: case RVInstr::SLTIU: case RVInstr::XORI:
case RVInstr::ORI: case RVInstr::ANDI: case RVInstr::SLLI: case RVInstr::SRLI:
- case RVInstr::SRAI:
+ case RVInstr::SRAI: case RVInstr::ADDIW: case RVInstr::SLLIW: case RVInstr::SRLIW:
+ case RVInstr::SRAIW:
// Arithmetic instructions
case RVInstr::MUL: case RVInstr::MULH: case RVInstr:: MULHSU: case RVInstr::MULHU:
case RVInstr::DIV: case RVInstr::DIVU: case RVInstr::REM: case RVInstr::REMU:
case RVInstr::ADD: case RVInstr::SUB: case RVInstr::SLL: case RVInstr::SLT:
case RVInstr::SLTU: case RVInstr::XOR: case RVInstr::SRL: case RVInstr::SRA:
- case RVInstr::OR: case RVInstr::AND:
+ case RVInstr::OR: case RVInstr::AND: case RVInstr::ADDW: case RVInstr::SUBW:
+ case RVInstr::SLLW: case RVInstr::SRLW: case RVInstr::SRAW: case RVInstr::MULW:
+ case RVInstr::DIVW: case RVInstr::DIVUW: case RVInstr::REMW: case RVInstr::REMUW:
// Load instructions
- case RVInstr::LB: case RVInstr::LH: case RVInstr::LW: case RVInstr::LBU: case RVInstr::LHU:
+ case RVInstr::LB: case RVInstr::LH: case RVInstr::LW: case RVInstr::LBU:
+ case RVInstr::LHU: case RVInstr::LWU: case RVInstr::LD: case RVInstr::SD:
// Jump instructions
case RVInstr::JALR:

MODIFY
test/tst_riscv.cpp
test/tst_riscv.cpp
@@ -59,6 +59,11 @@ private:
private slots:
+ void testRV64_SingleCycle() { runTests(ProcessorID::RV64_SS, RISCV64_TEST_DIR); }
+ void testRV64_5StagePipeline() { runTests(ProcessorID::RV64_5S, RISCV64_TEST_DIR); }
+ void testRV64_5StagePipelineNOFW() { runTests(ProcessorID::RV64_5S_NO_FW, RISCV64_TEST_DIR); }
+ void testRV64_6SDual() { runTests(ProcessorID::RV64_6S_DUAL, RISCV64_TEST_DIR); }
+
void testRV32_SingleCycle() { runTests(ProcessorID::RV32_SS, RISCV32_TEST_DIR); }
void testRV32_5StagePipeline() { runTests(ProcessorID::RV32_5S, RISCV32_TEST_DIR); }
void testRV32_5StagePipelineNOFW() { runTests(ProcessorID::RV32_5S_NO_FW, RISCV32_TEST_DIR); }
@@ -152,7 +157,7 @@ void tst_RISCV::runTests(const ProcessorID& id, const QString& testdir) {
qInfo() << "Running test: " << m_currentTest;
// Assemble test file
- auto f = QFile(RISCV32_TEST_DIR + QString(QDir::separator()) + test);
+ auto f = QFile(testdir + QString(QDir::separator()) + test);
if (!f.open(QIODevice::ReadOnly)) {
QFAIL("Could not open test file");
}

Add missing RV64 instructions in waycontrol comp. for rv6s; all 64-bit tests now pass!