Enable RV-C for intermediate 5 stage processors
MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -471,7 +471,7 @@ public:
}
static ProcessorISAInfo supportsISA() {
- return ProcessorISAInfo{std::make_shared<ISAInfo<XLenToRVISA<XLEN>()>>(QStringList()), {"M"}};
+ return ProcessorISAInfo{std::make_shared<ISAInfo<XLenToRVISA<XLEN>()>>(QStringList()), {"M", "C"}};
}
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); }

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -421,7 +421,7 @@ public:
}
static ProcessorISAInfo supportsISA() {
- return ProcessorISAInfo{std::make_shared<ISAInfo<XLenToRVISA<XLEN>()>>(QStringList()), {"M"}};
+ return ProcessorISAInfo{std::make_shared<ISAInfo<XLenToRVISA<XLEN>()>>(QStringList()), {"M", "C"}};
}
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); };

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -454,7 +454,7 @@ public:
}
static ProcessorISAInfo supportsISA() {
- return ProcessorISAInfo{std::make_shared<ISAInfo<XLenToRVISA<XLEN>()>>(QStringList()), {"M"}};
+ return ProcessorISAInfo{std::make_shared<ISAInfo<XLenToRVISA<XLEN>()>>(QStringList()), {"M", "C"}};
}
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); };

Enable RV-C for intermediate 5 stage processors