Add 64-bit processors to ProcessorRegistry
MODIFY
external/VSRTL
external/VSRTL
-Subproject commit 45237b8882ce10d1db6010c44da11752f94be133
+Subproject commit e124e1d2be0b8393704067fc82e5125164ea7a22

MODIFY
src/editor/codeeditor.cpp
src/editor/codeeditor.cpp
@@ -210,7 +210,7 @@ void CodeEditor::setSourceType(SourceType type, const std::set<QString>& support
switch (m_sourceType) {
case SourceType::Assembly: {
auto* isa = ProcessorHandler::currentISA();
- if (isa->isaID() == ISA::RV32I) {
+ if (isa->isaID() == ISA::RV32I || isa->isaID() == ISA::RV64I) {
m_highlighter = std::make_unique<RVSyntaxHighlighter>(document(), m_errors, supportedOpcodes);
} else {
Q_ASSERT(false && "Unknown ISA selected");

MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
#include "assembler/program.h"
#include "assembler/rv32i_assembler.h"
+#include "assembler/rv64i_assembler.h"
#include "syscall/riscv_syscall.h"
@@ -182,8 +183,10 @@ void ProcessorHandler::_clearBreakpoints() {
void ProcessorHandler::createAssemblerForCurrentISA() {
const auto& ISA = _currentISA();
- if (auto* rvisa = dynamic_cast<const ISAInfo<ISA::RV32I>*>(ISA)) {
- m_currentAssembler = std::make_shared<Assembler::RV32I_Assembler>(rvisa);
+ if (auto* rv32isa = dynamic_cast<const ISAInfo<ISA::RV32I>*>(ISA)) {
+ m_currentAssembler = std::make_shared<Assembler::RV32I_Assembler>(rv32isa);
+ } else if (auto* rv64isa = dynamic_cast<const ISAInfo<ISA::RV64I>*>(ISA)) {
+ m_currentAssembler = std::make_shared<Assembler::RV64I_Assembler>(rv64isa);
} else {
Q_UNREACHABLE();
}

MODIFY
src/processorregistry.h
src/processorregistry.h
@@ -21,7 +21,22 @@ Q_NAMESPACE
// =============================== Processors =================================
// The order of the ProcessorID enum defines the order of which the processors will appear in the processor selection
// dialog.
-enum ProcessorID { RV32_SS, RV32_5S_NO_FW_HZ, RV32_5S_NO_HZ, RV32_5S_NO_FW, RV32_5S, RV32_6S_DUAL, NUM_PROCESSORS };
+enum ProcessorID {
+ TEST,
+ RV32_SS,
+ RV32_5S_NO_FW_HZ,
+ RV32_5S_NO_HZ,
+ RV32_5S_NO_FW,
+ RV32_5S,
+ RV32_6S_DUAL,
+ RV64_SS,
+ RV64_5S_NO_FW_HZ,
+ RV64_5S_NO_HZ,
+ RV64_5S_NO_FW,
+ RV64_5S,
+ RV64_6S_DUAL,
+ NUM_PROCESSORS
+};
Q_ENUM_NS(Ripes::ProcessorID); // Register with the metaobject system
// ============================================================================
@@ -70,20 +85,33 @@ public:
return std::make_unique<vsrtl::core::RV5S_NO_HZ<32>>(extensions);
case ProcessorID::RV32_5S_NO_FW:
return std::make_unique<vsrtl::core::RV5S_NO_FW<32>>(extensions);
+ case ProcessorID::RV64_5S_NO_FW_HZ:
+ return std::make_unique<vsrtl::core::RV5S_NO_FW_HZ<64>>(extensions);
+ case ProcessorID::RV64_5S:
+ return std::make_unique<vsrtl::core::RV5S<64>>(extensions);
+ case ProcessorID::RV64_6S_DUAL:
+ return std::make_unique<vsrtl::core::RV6S_DUAL<64>>(extensions);
+ case ProcessorID::RV64_SS:
+ return std::make_unique<vsrtl::core::RVSS<64>>(extensions);
+ case ProcessorID::RV64_5S_NO_HZ:
+ return std::make_unique<vsrtl::core::RV5S_NO_HZ<64>>(extensions);
+ case ProcessorID::RV64_5S_NO_FW:
+ return std::make_unique<vsrtl::core::RV5S_NO_FW<64>>(extensions);
case ProcessorID::NUM_PROCESSORS:
+ default:
Q_UNREACHABLE();
}
- Q_UNREACHABLE();
}
private:
ProcessorRegistry() {
// Initialize processors
+ for (int xlen : {32, 64}) {
// RISC-V single cycle
ProcessorDescription desc;
- desc.id = ProcessorID::RV32_SS;
- desc.isa = vsrtl::core::RVSS<32>::ISA();
+ desc.id = xlen == 32 ? ProcessorID::RV32_SS : ProcessorID::RV64_SS;
+ desc.isa = xlen == 32 ? vsrtl::core::RVSS<32>::ISA() : vsrtl::core::RVSS<64>::ISA();
desc.name = "Single-cycle processor";
desc.description = "A single cycle processor";
desc.layouts = {{"Standard", ":/layouts/RISC-V/rvss/rv_ss_standard_layout.json", {QPointF{0.5, 0}}},
@@ -93,8 +121,8 @@ private:
// RISC-V 5-stage without forwarding or hazard detection
desc = ProcessorDescription();
- desc.id = ProcessorID::RV32_5S_NO_FW_HZ;
- desc.isa = vsrtl::core::RV5S_NO_FW_HZ<32>::ISA();
+ desc.id = xlen == 32 ? ProcessorID::RV32_5S_NO_FW_HZ : ProcessorID::RV64_5S_NO_FW_HZ;
+ desc.isa = xlen == 32 ? vsrtl::core::RV5S_NO_FW_HZ<32>::ISA() : vsrtl::core::RV5S_NO_FW_HZ<64>::ISA();
desc.name = "5-stage processor w/o forwarding or hazard detection";
desc.description = "A 5-stage in-order processor with no forwarding or hazard detection/elimination.";
desc.layouts = {
@@ -110,11 +138,12 @@ private:
// RISC-V 5-stage without hazard detection
desc = ProcessorDescription();
- desc.id = ProcessorID::RV32_5S_NO_HZ;
- desc.isa = vsrtl::core::RV5S_NO_HZ<32>::ISA();
+ desc.id = xlen == 32 ? ProcessorID::RV32_5S_NO_HZ : ProcessorID::RV64_5S_NO_HZ;
+ desc.isa = xlen == 32 ? vsrtl::core::RV5S_NO_HZ<32>::ISA() : vsrtl::core::RV5S_NO_HZ<64>::ISA();
desc.name = "5-stage processor w/o hazard detection";
desc.description = "A 5-stage in-order processor with forwarding but no hazard detection/elimination.";
- desc.layouts = {{"Standard",
+ desc.layouts = {
+ {"Standard",
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0}, QPointF{0.75, 0}, QPointF{0.88, 0}}},
{"Extended",
@@ -125,11 +154,12 @@ private:
// RISC-V 5-stage without forwarding unit
desc = ProcessorDescription();
- desc.id = ProcessorID::RV32_5S_NO_FW;
- desc.isa = vsrtl::core::RV5S_NO_FW<32>::ISA();
- desc.name = "5-Stage Processor w/o forwarding unit";
+ desc.id = xlen == 32 ? ProcessorID::RV32_5S_NO_FW : ProcessorID::RV64_5S_NO_FW;
+ desc.isa = xlen == 32 ? vsrtl::core::RV5S_NO_FW<32>::ISA() : vsrtl::core::RV5S_NO_FW<64>::ISA();
+ desc.name = "5-Stage processor w/o forwarding unit";
desc.description = "A 5-stage in-order processor with hazard detection/elimination but no forwarding unit.";
- desc.layouts = {{"Standard",
+ desc.layouts = {
+ {"Standard",
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0}, QPointF{0.75, 0}, QPointF{0.88, 0}}},
{"Extended",
@@ -138,13 +168,14 @@ private:
desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
m_descriptions[desc.id] = desc;
- // RISC-V 5-stage without forwarding or hazard detection
+ // RISC-V 5-stage
desc = ProcessorDescription();
- desc.id = ProcessorID::RV32_5S;
- desc.isa = vsrtl::core::RV5S<32>::ISA();
+ desc.id = xlen == 32 ? ProcessorID::RV32_5S : ProcessorID::RV64_5S;
+ desc.isa = xlen == 32 ? vsrtl::core::RV5S<32>::ISA() : vsrtl::core::RV5S<64>::ISA();
desc.name = "5-stage processor";
desc.description = "A 5-stage in-order processor with hazard detection/elimination and forwarding.";
- desc.layouts = {{"Standard",
+ desc.layouts = {
+ {"Standard",
":/layouts/RISC-V/rv5s/rv5s_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.29, 0}, QPointF{0.55, 0}, QPointF{0.75, 0}, QPointF{0.87, 0}}},
{"Extended",
@@ -155,11 +186,12 @@ private:
// RISC-V 6-stage dual issue
desc = ProcessorDescription();
- desc.id = ProcessorID::RV32_6S_DUAL;
- desc.isa = vsrtl::core::RV6S_DUAL<32>::ISA();
+ desc.id = xlen == 32 ? ProcessorID::RV32_6S_DUAL : ProcessorID::RV64_6S_DUAL;
+ desc.isa = xlen == 32 ? vsrtl::core::RV6S_DUAL<32>::ISA() : vsrtl::core::RV6S_DUAL<64>::ISA();
desc.name = "6-stage dual-issue processor";
desc.description =
- "A 6-stage dual-issue in-order processor. Each way may execute arithmetic instructions, whereas way 1 is "
+ "A 6-stage dual-issue in-order processor. Each way may execute arithmetic instructions, whereas way 1 "
+ "is "
"reserved for controlflow and ecall instructions, and way 2 for memory accessing instructions.";
desc.layouts = {{"Extended",
":/layouts/RISC-V/rv6s_dual/rv6s_dual_extended_layout.json",
@@ -169,6 +201,7 @@ private:
desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
m_descriptions[desc.id] = desc;
}
+ }
static ProcessorRegistry& instance() {
static ProcessorRegistry pr;

MODIFY
src/processorselectiondialog.cpp
src/processorselectiondialog.cpp
@@ -17,12 +17,14 @@ ProcessorSelectionDialog::ProcessorSelectionDialog(QWidget* parent)
// Initialize top level ISA items
m_ui->processors->setHeaderHidden(true);
- std::map<ISA, QTreeWidgetItem*> isaItems;
- std::map<ISA, std::map<unsigned, QTreeWidgetItem*>> isaRegWidthItems;
+ std::map<QString, QTreeWidgetItem*> isaFamilyItems;
+ std::map<QTreeWidgetItem*, std::map<unsigned, QTreeWidgetItem*>> isaFamilyRegWidthItems;
for (const auto& isa : ISAFamilyNames) {
- auto* isaItem = new QTreeWidgetItem({isa.second});
- isaRegWidthItems[isa.first];
- isaItems[isa.first] = isaItem;
+ if (isaFamilyItems.count(isa.second) == 0) {
+ isaFamilyItems[isa.second] = new QTreeWidgetItem({isa.second});
+ }
+ auto* isaItem = isaFamilyItems.at(isa.second);
+ isaFamilyRegWidthItems[isaItem] = {};
isaItem->setFlags(isaItem->flags() & ~(Qt::ItemIsSelectable));
m_ui->processors->insertTopLevelItem(m_ui->processors->topLevelItemCount(), isaItem);
}
@@ -40,8 +42,9 @@ ProcessorSelectionDialog::ProcessorSelectionDialog(QWidget* parent)
processorItem->setFont(ProcessorColumn, font);
selectedItem = processorItem;
}
-
- auto& regWidthItemsForISA = isaRegWidthItems.at(desc.second.isa->isaID());
+ const QString& isaFamily = ISAFamilyNames.at(desc.second.isa->isaID());
+ QTreeWidgetItem* familyItem = isaFamilyItems.at(isaFamily);
+ auto& regWidthItemsForISA = isaFamilyRegWidthItems.at(familyItem);
auto isaRegWidthItem = regWidthItemsForISA.find(desc.second.isa->bits());
if (isaRegWidthItem == regWidthItemsForISA.end()) {
// Create reg width item
@@ -49,10 +52,8 @@ ProcessorSelectionDialog::ProcessorSelectionDialog(QWidget* parent)
widthItem->setFlags(widthItem->flags() & ~(Qt::ItemIsSelectable));
regWidthItemsForISA[desc.second.isa->bits()] = widthItem;
isaRegWidthItem = regWidthItemsForISA.find(desc.second.isa->bits());
- isaItems.at(desc.second.isa->isaID())
- ->insertChild(isaItems.at(desc.second.isa->isaID())->childCount(), widthItem);
+ familyItem->insertChild(familyItem->childCount(), widthItem);
}
-
isaRegWidthItem->second->insertChild(isaRegWidthItem->second->childCount(), processorItem);
}
@@ -92,6 +93,10 @@ QStringList ProcessorSelectionDialog::getEnabledExtensions() const {
}
void ProcessorSelectionDialog::selectionChanged(QTreeWidgetItem* current, QTreeWidgetItem*) {
+ if (current == nullptr) {
+ return;
+ }
+
QVariant selectedItemData = current->data(ProcessorColumn, Qt::UserRole);
const bool validSelection = selectedItemData.canConvert<ProcessorID>();
m_ui->buttonBox->button(QDialogButtonBox::Ok)->setEnabled(validSelection);

Add 64-bit processors to ProcessorRegistry