Use opcode enums where applicable
MODIFY
src/assembler/rv32i_assembler.cpp
src/assembler/rv32i_assembler.cpp
@@ -235,16 +235,16 @@ void RV32I_Assembler::enableExtI(const ISAInfoBase* isa, InstrVec& instructions,
// Assembler functors
instructions.push_back(std::shared_ptr<Instruction>(
- new Instruction(Opcode(Token("ecall"), {OpPart(0b1110011, 0, 6), OpPart(0, 7, 31)}), {})));
+ new Instruction(Opcode(Token("ecall"), {OpPart(RVISA::Opcode::ECALL, 0, 6), OpPart(0, 7, 31)}), {})));
- instructions.push_back(UType(Token("lui"), 0b0110111));
+ instructions.push_back(UType(Token("lui"), RVISA::Opcode::LUI));
instructions.push_back(std::shared_ptr<Instruction>(new Instruction(
- Opcode(Token("auipc"), {OpPart(0b0010111, 0, 6)}),
+ Opcode(Token("auipc"), {OpPart(RVISA::Opcode::AUIPC, 0, 6)}),
{std::make_shared<Reg>(isa, 1, 7, 11, "rd"),
std::make_shared<Imm>(2, 32, Imm::Repr::Hex, std::vector{ImmPart(0, 12, 31)}, Imm::SymbolType::Absolute)})));
- instructions.push_back(JType(Token("jal"), 0b1101111));
+ instructions.push_back(JType(Token("jal"), RVISA::Opcode::JAL));
instructions.push_back(JALRType(Token("jalr")));

MODIFY
src/assembler/rvassembler_common.h
src/assembler/rvassembler_common.h
@@ -8,7 +8,7 @@ namespace Assembler {
#define BType(name, funct3) \
std::shared_ptr<Instruction>(new Instruction( \
- Opcode(name, {OpPart(0b1100011, 0, 6), OpPart(funct3, 12, 14)}), \
+ Opcode(name, {OpPart(RVISA::Opcode::BRANCH, 0, 6), OpPart(funct3, 12, 14)}), \
{std::make_shared<Reg>(isa, 1, 15, 19, "rs1"), std::make_shared<Reg>(isa, 2, 20, 24, "rs2"), \
std::make_shared<Imm>( \
3, 13, Imm::Repr::Signed, \
@@ -26,7 +26,7 @@ namespace Assembler {
#define LoadType(name, funct3) \
std::shared_ptr<Instruction>( \
- new Instruction(Opcode(name, {OpPart(0b0000011, 0, 6), OpPart(funct3, 12, 14)}), \
+ new Instruction(Opcode(name, {OpPart(RVISA::Opcode::LOAD, 0, 6), OpPart(funct3, 12, 14)}), \
{std::make_shared<Reg>(isa, 1, 7, 11, "rd"), std::make_shared<Reg>(isa, 3, 15, 19, "rs1"), \
std::make_shared<Imm>(2, 12, Imm::Repr::Signed, std::vector{ImmPart(0, 20, 31)})}))
@@ -53,7 +53,7 @@ namespace Assembler {
#define SType(name, funct3) \
std::shared_ptr<Instruction>(new Instruction( \
- Opcode(name, {OpPart(0b0100011, 0, 6), OpPart(funct3, 12, 14)}), \
+ Opcode(name, {OpPart(RVISA::Opcode::STORE, 0, 6), OpPart(funct3, 12, 14)}), \
{std::make_shared<Reg>(isa, 3, 15, 19, "rs1"), \
std::make_shared<Imm>(2, 12, Imm::Repr::Signed, std::vector{ImmPart(5, 25, 31), ImmPart(0, 7, 11)}), \
std::make_shared<Reg>(isa, 1, 20, 24, "rs2")}))
@@ -75,7 +75,7 @@ namespace Assembler {
#define JALRType(name) \
std::shared_ptr<Instruction>( \
- new Instruction(Opcode(name, {OpPart(0b1100111, 0, 6), OpPart(0b000, 12, 14)}), \
+ new Instruction(Opcode(name, {OpPart(RVISA::Opcode::JALR, 0, 6), OpPart(0b000, 12, 14)}), \
{std::make_shared<Reg>(isa, 1, 7, 11, "rd"), std::make_shared<Reg>(isa, 2, 15, 19, "rs1"), \
std::make_shared<Imm>(3, 12, Imm::Repr::Signed, std::vector{ImmPart(0, 20, 31)})}))

MODIFY
src/isa/rv64isainfo.h
src/isa/rv64isainfo.h
@@ -8,7 +8,7 @@ namespace Ripes {
template <>
class ISAInfo<ISA::RV64I> : public ISAInfoBase {
public:
- ISAInfo<ISA::RV32I>(const QStringList extensions) {
+ ISAInfo<ISA::RV64I>(const QStringList extensions) {
// Validate extensions
for (const auto& ext : extensions) {
if (supportsExtension(ext)) {
@@ -19,7 +19,7 @@ public:
}
}
- QString name() const override { return "RV32I"; }
+ QString name() const override { return "RV64I"; }
ISA isaID() const override { return ISA::RV64I; }
unsigned int regCnt() const override { return 32; }
@@ -33,7 +33,7 @@ public:
return RVISA::RegDescs.size() > static_cast<int>(i) ? RVISA::RegDescs.at(static_cast<int>(i)) : QString();
}
bool regIsReadOnly(unsigned i) const override { return i == 0; }
- unsigned int bits() const override { return 32; }
+ unsigned int bits() const override { return 64; }
int spReg() const override { return 2; }
int gpReg() const override { return 3; }
int syscallReg() const override { return 17; }
@@ -52,7 +52,7 @@ public:
}
QString CCmarch() const override {
- QString march = "rv32i";
+ QString march = "rv64i";
// Proceed in canonical order
for (const auto& ext : {"M", "A", "F", "D"}) {
@@ -63,7 +63,7 @@ public:
return march;
}
- QString CCmabi() const override { return "ilp32"; }
+ QString CCmabi() const override { return "lp64"; }
QString elfSupportsFlags(unsigned flags) const override {
/** We expect no flags for RV32IM compiled RISC-V executables.
@@ -72,9 +72,9 @@ public:
if (flags == 0)
return QString();
QString err;
- for (const auto& flag : RVISA::ELFFlagStrings) {
+ for (const auto& flag : RVABI::ELFFlagStrings) {
if (flags & flag.first) {
- err += "ELF flag '" + RVISA::ELFFlagStrings.at(flag.first) + "' unsupported<br/>";
+ err += "ELF flag '" + RVABI::ELFFlagStrings.at(flag.first) + "' unsupported<br/>";
}
}
return err;

MODIFY
src/processors/RISC-V/riscv.h
src/processors/RISC-V/riscv.h
#pragma once
#include <functional>
-#include "../../isa/rv32isainfo.h"
+#include "../../isa/rvisainfo_common.h"
#include "VSRTL/core/vsrtl_enum.h"
#include "VSRTL/interface/vsrtl_binutils.h"
#include "VSRTL/interface/vsrtl_defines.h"
#include "rv_instrparser.h"
+#include "../../isa/rv32isainfo.h"
+#include "../../isa/rv64isainfo.h"
+
namespace Ripes {
#define RV_INSTR_WIDTH 32

MODIFY
src/processors/RISC-V/rv_decode.h
src/processors/RISC-V/rv_decode.h
@@ -17,13 +17,13 @@ public:
// clang-format off
switch(l7) {
- case 0b0110111: return RVInstr::LUI;
- case 0b0010111: return RVInstr::AUIPC;
- case 0b1101111: return RVInstr::JAL;
- case 0b1100111: return RVInstr::JALR;
- case 0b1110011: return RVInstr::ECALL;
+ case RVISA::Opcode::LUI: return RVInstr::LUI;
+ case RVISA::Opcode::AUIPC: return RVInstr::AUIPC;
+ case RVISA::Opcode::JAL: return RVInstr::JAL;
+ case RVISA::Opcode::JALR: return RVInstr::JALR;
+ case RVISA::Opcode::ECALL: return RVInstr::ECALL;
- case 0b0010011: {
+ case RVISA::Opcode::OPIMM: {
// I-Type
const auto fields = RVInstrParser::getParser()->decodeI32Instr(instr.uValue());
switch(fields[2]) {
@@ -45,7 +45,7 @@ public:
break;
}
- case 0b0110011: {
+ case RVISA::Opcode::OP: {
// R-Type
const auto fields = RVInstrParser::getParser()->decodeR32Instr(instr.uValue());
if (fields[0] == 0b1) {
@@ -93,7 +93,7 @@ public:
}
- case 0b0000011: {
+ case RVISA::Opcode::LOAD: {
// Load instruction
const auto fields = RVInstrParser::getParser()->decodeI32Instr(instr.uValue());
switch (fields[2]) {
@@ -107,7 +107,7 @@ public:
break;
}
- case 0b0100011: {
+ case RVISA::Opcode::STORE: {
// Store instructions
const auto fields = RVInstrParser::getParser()->decodeS32Instr(instr.uValue());
switch (fields[3]) {
@@ -119,7 +119,7 @@ public:
break;
}
- case 0b1100011: {
+ case RVISA::Opcode::BRANCH: {
// Branch instruction
const auto fields = RVInstrParser::getParser()->decodeB32Instr(instr.uValue());
switch (fields[4]) {

Use opcode enums where applicable