Make FinalizeReason fields an enum
MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
#include "processorhandler.h"
#include "processorregistry.h"
-#include "processors/ripesprocessor.h"
+#include "processors/interface/ripesprocessor.h"
#include "processors/ripesvsrtlprocessor.h"
#include "ripessettings.h"
#include "statusmanager.h"
@@ -346,8 +346,10 @@ bool ProcessorHandler::_isExecutableAddress(uint32_t address) const {
void ProcessorHandler::_checkValidExecutionRange() const {
const auto pc = m_currentProcessor->nextFetchedAddress();
- FinalizeReason fr;
- fr.exitedExecutableRegion = !_isExecutableAddress(pc);
+ unsigned fr = 0;
+ if (!_isExecutableAddress(pc)) {
+ fr |= RipesProcessor::FinalizeReason::exitedExecutableRegion;
+ }
m_currentProcessor->finalize(fr);
}

MODIFY
src/processorregistry.h
src/processorregistry.h
#include <memory>
#include "isa/isainfo.h"
-#include "processors/ripesprocessor.h"
+#include "processors/interface/ripesprocessor.h"
#include "processors/RISC-V/rv5s/rv5s.h"
#include "processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h"

MODIFY
src/processors/CMakeLists.txt
src/processors/CMakeLists.txt
@@ -13,7 +13,7 @@ endmacro()
macro(create_vsrtl_processor isa name)
file(GLOB LIB_SOURCES ${isa}/${name}/*.cpp)
- file(GLOB LIB_HEADERS RipesVSRTLProcessor.h ${isa}/${name}/*.h)
+ file(GLOB LIB_HEADERS interface/* RipesVSRTLProcessor.h ${isa}/${name}/*.h)
add_library(${name} ${LIB_SOURCES} ${LIB_HEADERS})
target_link_libraries(${name} ${VSRTL_CORE_LIB} ${isa}_lib)
target_include_directories(${name} PUBLIC ${isa})

MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
@@ -420,13 +420,13 @@ public:
AddressSpaceMM& getMemory() override { return *m_memory; }
unsigned int getRegister(RegisterFileType, unsigned i) const override { return registerFile->getRegister(i); }
AddressSpace& getArchRegisters() override { return *m_regMem; }
- void finalize(const FinalizeReason& fr) override {
- if (fr.exitSyscall && !ecallChecker->isSysCallExiting()) {
+ void finalize(const unsigned& fr) override {
+ if ((fr & FinalizeReason::exitSyscall) && !ecallChecker->isSysCallExiting()) {
// An exit system call was executed. Record the cycle of the execution, and enable the ecallChecker's system
// call exiting signal.
m_syscallExitCycle = m_cycleCount;
}
- ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
+ ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || (fr & FinalizeReason::exitSyscall));
}
const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -396,13 +396,13 @@ public:
AddressSpaceMM& getMemory() override { return *m_memory; }
unsigned int getRegister(RegisterFileType, unsigned i) const override { return registerFile->getRegister(i); }
AddressSpace& getArchRegisters() override { return *m_regMem; }
- void finalize(const FinalizeReason& fr) override {
- if (fr.exitSyscall && !ecallChecker->isSysCallExiting()) {
+ void finalize(const unsigned& fr) override {
+ if ((fr & FinalizeReason::exitSyscall) && !ecallChecker->isSysCallExiting()) {
// An exit system call was executed. Record the cycle of the execution, and enable the ecallChecker's system
// call exiting signal.
m_syscallExitCycle = m_cycleCount;
}
- ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
+ ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || (fr & FinalizeReason::exitSyscall));
}
const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -347,13 +347,13 @@ public:
AddressSpaceMM& getMemory() override { return *m_memory; }
unsigned int getRegister(RegisterFileType, unsigned i) const override { return registerFile->getRegister(i); }
AddressSpace& getArchRegisters() override { return *m_regMem; }
- void finalize(const FinalizeReason& fr) override {
- if (fr.exitSyscall && !ecallChecker->isSysCallExiting()) {
+ void finalize(const unsigned& fr) override {
+ if ((fr & FinalizeReason::exitSyscall) && !ecallChecker->isSysCallExiting()) {
// An exit system call was executed. Record the cycle of the execution, and enable the ecallChecker's system
// call exiting signal.
m_syscallExitCycle = m_cycleCount;
}
- ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
+ ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || (fr & FinalizeReason::exitSyscall));
}
const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -380,13 +380,13 @@ public:
AddressSpaceMM& getMemory() override { return *m_memory; }
unsigned int getRegister(RegisterFileType, unsigned i) const override { return registerFile->getRegister(i); }
AddressSpace& getArchRegisters() override { return *m_regMem; }
- void finalize(const FinalizeReason& fr) override {
- if (fr.exitSyscall && !ecallChecker->isSysCallExiting()) {
+ void finalize(const unsigned& fr) override {
+ if ((fr & FinalizeReason::exitSyscall) && !ecallChecker->isSysCallExiting()) {
// An exit system call was executed. Record the cycle of the execution, and enable the ecallChecker's system
// call exiting signal.
m_syscallExitCycle = m_cycleCount;
}
- ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
+ ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || (fr & FinalizeReason::exitSyscall));
}
const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
@@ -726,13 +726,13 @@ public:
AddressSpaceMM& getMemory() override { return *m_memory; }
unsigned int getRegister(RegisterFileType, unsigned i) const override { return registerFile->getRegister(i); }
AddressSpace& getArchRegisters() override { return *m_regMem; }
- void finalize(const FinalizeReason& fr) override {
- if (fr.exitSyscall && !ecallChecker->isSysCallExiting()) {
+ void finalize(const unsigned& fr) override {
+ if ((fr & FinalizeReason::exitSyscall) && !ecallChecker->isSysCallExiting()) {
// An exit system call was executed. Record the cycle of the execution, and enable the ecallChecker's
// system call exiting signal.
m_syscallExitCycle = m_cycleCount;
}
- ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
+ ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || (fr & FinalizeReason::exitSyscall));
}
const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF_1, IF_2}; };

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -166,8 +166,8 @@ public:
AddressSpaceMM& getMemory() override { return *m_memory; }
unsigned int getRegister(RegisterFileType, unsigned i) const override { return registerFile->getRegister(i); }
AddressSpace& getArchRegisters() override { return *m_regMem; }
- void finalize(const FinalizeReason& fr) override {
- if (fr.any()) {
+ void finalize(const unsigned& fr) override {
+ if (fr) {
// Allow one additional clock cycle to clear the current instruction
m_finishInNextCycle = true;
}

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
@@ -31,9 +31,12 @@ struct StageInfo {
* Transmitted to the processor to indicate the reason for why the finalization sequence has been initialized.
*/
struct FinalizeReason {
- bool exitedExecutableRegion = false;
- bool exitSyscall = false;
- bool any() const { return exitedExecutableRegion || exitSyscall; }
+ enum Reason { exitedExecutableRegion = 0b1, exitSyscall = 0b10 };
+ FinalizeReason(unsigned _r = 0) : reason(_r) {}
+ unsigned reason;
+ bool any() const { return reason; }
+ bool is(Reason r) const { return reason & r; };
+ void set(Reason r) { reason |= r; }
};
/**

MODIFY
src/processors/ripesvsrtlprocessor.h
src/processors/ripesvsrtlprocessor.h
*/
#include "VSRTL/core/vsrtl_design.h"
-#include "ripesprocessor.h"
+#include "interface/ripesprocessor.h"
namespace Ripes {
@@ -13,7 +13,7 @@ class RipesVSRTLProcessor : public RipesProcessor, public vsrtl::core::Design {
public:
RipesVSRTLProcessor(std::string name) : Design(name) {
// VSRTL provides reversible simulation
- m_features.isReversible = true;
+ m_features = {Features::isReversible | Features::hasDCacheInterface | Features::hasICacheInterface};
// Shim signal emissions from VSRTL to RipesProcessor
designWasClocked.Connect(&processorWasClocked, &Gallant::Signal0<>::Emit);

MODIFY
src/processortab.cpp
src/processortab.cpp
#include "VSRTL/graphics/vsrtl_widget.h"
-#include "processors/ripesprocessor.h"
+#include "processors/interface/ripesprocessor.h"
namespace Ripes {

MODIFY
src/syscall/control.h
src/syscall/control.h
@@ -16,8 +16,7 @@ public:
ExitSyscall() : BaseSyscall("Exit", "Exits the program with code 0") {}
void execute() {
SystemIO::printString("\nProgram exited with code: 0");
- FinalizeReason fr;
- fr.exitSyscall = true;
+ auto fr = RipesProcessor::FinalizeReason::exitSyscall;
ProcessorHandler::getProcessorNonConst()->finalize(fr);
}
};
@@ -31,8 +30,7 @@ public:
void execute() {
SystemIO::printString("\nProgram exited with code: " +
QString::number(BaseSyscall::getArg(RegisterFileType::GPR, 0)));
- FinalizeReason fr;
- fr.exitSyscall = true;
+ auto fr(RipesProcessor::FinalizeReason::exitSyscall);
ProcessorHandler::getProcessorNonConst()->finalize(fr);
}
};

Make FinalizeReason fields an enum