Disallow processor clocking when processor is finished
MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
@@ -134,7 +134,7 @@ class ProcessorClocker : public QRunnable {
public:
explicit ProcessorClocker(bool& finished) : m_finished(finished) {}
void run() override {
- ProcessorHandler::getProcessorNonConst()->clockProcessor();
+ ProcessorHandler::getProcessorNonConst()->clock();
ProcessorHandler::checkProcessorFinished();
if (ProcessorHandler::checkBreakpoint()) {
ProcessorHandler::stopRun();
@@ -166,7 +166,7 @@ void ProcessorHandler::_run() {
}
while (!(_checkBreakpoint() || m_currentProcessor->finished() || m_stopRunningFlag)) {
- m_currentProcessor->clockProcessor();
+ m_currentProcessor->clock();
}
if (vsrtl_proc) {

MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
@@ -453,7 +453,7 @@ public:
setSynchronousValue(registerFile->_wr_mem, i, v);
}
- void clock() override {
+ void clockProcessor() override {
// An instruction has been retired if the instruction in the WB stage is valid and the PC is within the
// executable range of the program
if (memwb_reg->valid_out.uValue() != 0 && isExecutableAddress(memwb_reg->pc_out.uValue())) {

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -429,7 +429,7 @@ public:
setSynchronousValue(registerFile->_wr_mem, i, v);
}
- void clock() override {
+ void clockProcessor() override {
// An instruction has been retired if the instruction in the WB stage is valid and the PC is within the
// executable range of the program
if (memwb_reg->valid_out.uValue() != 0 && isExecutableAddress(memwb_reg->pc_out.uValue())) {

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -379,7 +379,7 @@ public:
setSynchronousValue(registerFile->_wr_mem, i, v);
}
- void clock() override {
+ void clockProcessor() override {
// An instruction has been retired if the instruction in the WB stage is valid and the PC is within the
// executable range of the program
if (memwb_reg->valid_out.uValue() != 0 && isExecutableAddress(memwb_reg->pc_out.uValue())) {

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -412,7 +412,7 @@ public:
setSynchronousValue(registerFile->_wr_mem, i, v);
}
- void clock() override {
+ void clockProcessor() override {
// An instruction has been retired if the instruction in the WB stage is valid and the PC is within the
// executable range of the program
if (memwb_reg->valid_out.uValue() != 0 && isExecutableAddress(memwb_reg->pc_out.uValue())) {

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
@@ -774,7 +774,7 @@ public:
return amount;
}
- void clock() override {
+ void clockProcessor() override {
// An instruction has been retired if the instruction in the WB stage is valid and the PC is within the
// executable range of the program
m_instructionsRetired += instructionsRetired();

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -187,7 +187,7 @@ public:
setSynchronousValue(registerFile->_wr_mem, i, v);
}
- void clock() override {
+ void clockProcessor() override {
// Single cycle processor; 1 instruction retired per cycle!
m_instructionsRetired++;

MODIFY
src/processors/interface/ripesprocessor.h
src/processors/interface/ripesprocessor.h
@@ -179,9 +179,12 @@ public:
/**
* @brief clock
- * Clocks the processor
+ * Clocks the processor.
*/
- virtual void clockProcessor() = 0;
+ void clock() {
+ if (!finished())
+ clockProcessor();
+ }
/**
* @brief finalize
@@ -255,6 +258,12 @@ public:
/** ======================================================================*/
protected:
+ /**
+ * @brief clock
+ * Implementation of processor clocking.
+ */
+ virtual void clockProcessor() = 0;
+
// m_features should be adjusted accordingly during processor construction
unsigned m_features;
bool m_emitsSignals = true;

MODIFY
src/processors/ripesvsrtlprocessor.h
src/processors/ripesvsrtlprocessor.h
@@ -27,7 +27,6 @@ public:
reset();
}
- virtual void clockProcessor() override { clock(); }
virtual void reverseProcessor() override { reverse(); }
long long getInstructionsRetired() const override { return m_instructionsRetired; }

MODIFY
test/tst_cosimulate.cpp
test/tst_cosimulate.cpp
@@ -196,7 +196,7 @@ void tst_Cosimulate::executeSimulator(Trace& trace, const Trace* refTrace) {
Registers preRegs = dumpRegs();
do {
- ProcessorHandler::get()->getProcessorNonConst()->clockProcessor();
+ ProcessorHandler::get()->getProcessorNonConst()->clock();
cycles++;
Registers regs = dumpRegs();

MODIFY
test/tst_riscv.cpp
test/tst_riscv.cpp
@@ -120,7 +120,7 @@ QString tst_RISCV::executeSimulator() {
bool maxCyclesReached = false;
unsigned cycles = 0;
do {
- ProcessorHandler::getProcessorNonConst()->clockProcessor();
+ ProcessorHandler::getProcessorNonConst()->clock();
cycles++;

Disallow processor clocking when processor is finished #139