Rename RV5SWOF to RV5S_NO_FW_HZ
MODIFY
src/processorregistry.h
src/processorregistry.h
#include "processors/ripesprocessor.h"
#include "processors/RISC-V/rv5s/rv5s.h"
-#include "processors/RISC-V/rv5swof/rv5swof.h"
+#include "processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h"
#include "processors/RISC-V/rvss/rvss.h"
namespace Ripes {
// =============================== Processors =================================
-enum class ProcessorID { RISCV_SS, RISCV_5S, RISCV_5S_WOF };
+enum class ProcessorID { RISCV_SS, RISCV_5S, RISCV_5S_NO_FW_HZ };
// ============================================================================
using RegisterInitialization = std::map<unsigned, uint32_t>;
@@ -47,8 +47,8 @@ public:
static const ProcessorDescription& getDescription(ProcessorID id) { return instance().m_descriptions[id]; }
static std::unique_ptr<vsrtl::core::RipesProcessor> constructProcessor(ProcessorID id) {
switch (id) {
- case ProcessorID::RISCV_5S_WOF:
- return std::make_unique<vsrtl::core::RV5SWOF>();
+ case ProcessorID::RISCV_5S_NO_FW_HZ:
+ return std::make_unique<vsrtl::core::RV5S_NO_FW_HZ>();
case ProcessorID::RISCV_5S:
return std::make_unique<vsrtl::core::RV5S>();
case ProcessorID::RISCV_SS: {
@@ -86,15 +86,18 @@ private:
// RISC-V 5-stage without forwarding
desc = ProcessorDescription();
- desc.id = ProcessorID::RISCV_5S_WOF;
+ desc.id = ProcessorID::RISCV_5S_NO_FW_HZ;
desc.isa = ISAInfo<ISA::RV32IM>::instance();
- desc.name = "RISC-V 5-Stage Processor wo/ forwarding";
+ desc.name = "RISC-V 5-Stage Processor wo/ forwarding or hazard detection";
desc.description =
- "A 5-Stage in-order RISC-V processor with no hazard detection and forwarding. \n\nThe user is expected to "
+ "A 5-Stage in-order RISC-V processor with no forwarding or hazard detection. \n\nThe user is expected to "
"resolve all data hazard through insertions of NOP instructions to correctly schedule the code.";
- desc.layouts = {
- {"Standard", ":/layouts/RISC-V/rv5swof/rv5swof_standard_layout.json", {0.08, 0.3, 0.53, 0.72, 0.88}},
- {"Extended", ":/layouts/RISC-V/rv5swof/rv5swof_extended_layout.json", {0.08, 0.28, 0.53, 0.74, 0.9}}};
+ desc.layouts = {{"Standard",
+ ":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json",
+ {0.08, 0.3, 0.53, 0.72, 0.88}},
+ {"Extended",
+ ":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json",
+ {0.08, 0.28, 0.53, 0.74, 0.9}}};
desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
m_descriptions[desc.id] = desc;
}

MODIFY
src/processors/CMakeLists.txt
src/processors/CMakeLists.txt
@@ -23,4 +23,4 @@ endmacro()
create_isa_lib(RISC-V)
create_processor(RISC-V rvss)
create_processor(RISC-V rv5s)
-create_processor(RISC-V rv5swof)
+create_processor(RISC-V rv5s_no_fw_hz)

MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
#include "../rv_registerfile.h"
// Stage separating registers
-#include "../rv5swof/rv5swof_ifid.h"
+#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h"
#include "rv5s_exmem.h"
#include "rv5s_idex.h"
#include "rv5s_memwb.h"

MODIFY
src/processors/RISC-V/rv5s/rv5s_exmem.h
src/processors/RISC-V/rv5s/rv5s_exmem.h
#include "../riscv.h"
-#include "../rv5swof/rv5swof_exmem.h"
+#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_exmem.h"
namespace vsrtl {
namespace core {

MODIFY
src/processors/RISC-V/rv5s/rv5s_idex.h
src/processors/RISC-V/rv5s/rv5s_idex.h
#include "../riscv.h"
-#include "../rv5swof/rv5swof_idex.h"
+#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_idex.h"
namespace vsrtl {
namespace core {
@@ -14,7 +14,7 @@ using namespace Ripes;
/**
* @brief The RV5S_IDEX class
- * A specialization of the default IDEX stage separating register utilized by the RV5SWOF processor. Storage of register
+ * A specialization of the default IDEX stage separating register utilized by the rv5s_no_fw_hz processor. Storage of register
* read indices is added, which are required by the forwarding unit.
*/
class RV5S_IDEX : public IDEX {

MODIFY
src/processors/RISC-V/rv5s/rv5s_memwb.h
src/processors/RISC-V/rv5s/rv5s_memwb.h
#include "../riscv.h"
-#include "../rv5swof/rv5swof_memwb.h"
+#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_memwb.h"
namespace vsrtl {
namespace core {

RENAME
src/processors/RISC-V/rv5swof/rv5swof.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
#include "../rv_registerfile.h"
// Stage separating registers
-#include "rv5swof_exmem.h"
-#include "rv5swof_idex.h"
-#include "rv5swof_ifid.h"
-#include "rv5swof_memwb.h"
+#include "rv5s_no_fw_hz_exmem.h"
+#include "rv5s_no_fw_hz_idex.h"
+#include "rv5s_no_fw_hz_ifid.h"
+#include "rv5s_no_fw_hz_memwb.h"
namespace vsrtl {
namespace core {
using namespace Ripes;
-class RV5SWOF : public RipesProcessor {
+class RV5S_NO_FW_HZ : public RipesProcessor {
public:
enum Stage { IF = 0, ID = 1, EX = 2, MEM = 3, WB = 4, STAGECOUNT };
- RV5SWOF() : RipesProcessor("5-Stage RISC-V Processor without forwarding") {
+ RV5S_NO_FW_HZ() : RipesProcessor("5-Stage RISC-V Processor without forwarding or hazard detection") {
// -----------------------------------------------------------------------
// Program counter
pc_reg->out >> pc_4->op1;

RENAME
src/processors/RISC-V/rv5swof/rv5swof_exmem.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_exmem.h
RENAME
src/processors/RISC-V/rv5swof/rv5swof_extended_layout.json
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json
"Italic": false,
"PtSize": 17,
"Text": {
- "str": "5-Stage RISC-V Processor wo/ Forwarding & Hazard Detection "
+ "str": "5-Stage RISC-V Processor wo/ Forwarding or Hazard Detection "
},
"Pos": {
"x": 832.1175988593237,

RENAME
src/processors/RISC-V/rv5swof/rv5swof_idex.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_idex.h
RENAME
src/processors/RISC-V/rv5swof/rv5swof_ifid.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h
RENAME
src/processors/RISC-V/rv5swof/rv5swof_memwb.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_memwb.h
RENAME
src/processors/RISC-V/rv5swof/rv5swof_standard_layout.json
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json
"Italic": false,
"PtSize": 15,
"Text": {
- "str": "5-Stage RISC-V Processor wo/ Forwarding & Hazard Detection "
+ "str": "5-Stage RISC-V Processor wo/ Forwarding or Hazard Detection "
},
"Pos": {
"x": 645.2405380886537,

MODIFY
src/processors/layouts.qrc
src/processors/layouts.qrc
<file>RISC-V/rvss/rv_ss_extended_layout.json</file>
<file>RISC-V/rvss/rv_ss_standard_layout.json</file>
<file>RISC-V/rv5s/rv5s_standard_layout.json</file>
- <file>RISC-V/rv5swof/rv5swof_standard_layout.json</file>
<file>RISC-V/rv5s/rv5s_extended_layout.json</file>
- <file>RISC-V/rv5swof/rv5swof_extended_layout.json</file>
+ <file>RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json</file>
+ <file>RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json</file>
</qresource>
</RCC>

Rename RV5SWOF to RV5S_NO_FW_HZ