add test cases for inner phi rewiring
ADD
tests/alive-tv/loops/fp_fraction.srctgt.ll
+; TEST-ARGS: -src-unroll=23
+; XFAIL: Value mismatch
+; requires creating phi in exit block
+
+; https://godbolt.org/z/dKxzKx
+
+define i32 @src(i32 %0) {
+ br label %2
+
+2: ; preds = %2, %1
+ %3 = phi i32 [ %0, %1 ], [ %6, %2 ]
+ %4 = and i32 %3, 8388608
+ %5 = icmp eq i32 %4, 0
+ %6 = shl i32 %3, 1
+ br i1 %5, label %2, label %7
+
+7: ; preds = %2
+ ret i32 %3
+}
+
+define i32 @tgt(i32 %0) {
+ %2 = and i32 %0, 8388608
+ %3 = icmp eq i32 %2, 0
+ br i1 %3, label %4, label %9
+
+4: ; preds = %1
+ %5 = and i32 %0, 8388607
+ %6 = tail call i32 @llvm.ctlz.i32(i32 %5, i1 true)
+ %7 = add nsw i32 %6, -8
+ %8 = shl i32 %0, %7
+ br label %9
+
+9: ; preds = %4, %1
+ %10 = phi i32 [ %0, %1 ], [ %8, %4 ]
+ ret i32 %10
+}
+
+declare i32 @llvm.ctlz.i32(i32, i1 immarg)

ADD
tests/alive-tv/loops/phi1-fail.srctgt.ll
+; TEST-ARGS: -src-unroll=3 -tgt-unroll=3
+; ERROR: Value mismatch
+
+define i32 @src() {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %if.end ], [ 0, %entry ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ br label %if.cont
+
+if.cont:
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %exit, label %if.end
+
+if.end:
+ br label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt() {
+ ret i32 2
+}

ADD
tests/alive-tv/loops/phi1.srctgt.ll
+; TEST-ARGS: -src-unroll=3 -tgt-unroll=3
+
+define i32 @src() {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %if.end ], [ 0, %entry ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ br label %if.cont
+
+if.cont:
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %exit, label %if.end
+
+if.end:
+ br label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt() {
+ ret i32 3
+}

ADD
tests/alive-tv/loops/phi2-fail.srctgt.ll
+; TEST-ARGS: -src-unroll=2 -tgt-unroll=2
+; ERROR: Value mismatch
+
+define i32 @src() {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %header ], [ 0, %entry ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %exit, label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt() {
+ ret i32 2
+}

ADD
tests/alive-tv/loops/phi2.srctgt.ll
+; TEST-ARGS: -src-unroll=2 -tgt-unroll=2
+
+define i32 @src() {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %header ], [ 0, %entry ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %exit, label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt() {
+ ret i32 3
+}

ADD
tests/alive-tv/loops/phi3-fail.srctgt.ll
+; TEST-ARGS: -src-unroll=3 -tgt-unroll=3
+; ERROR: Value mismatch
+
+define i32 @src() {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %if.cont ], [ 0, %entry ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %a, label %b
+
+a:
+ br label %if.cont
+
+b:
+ br label %if.cont
+
+if.cont:
+ %ph2 = phi i1 [ 1, %a ], [ 0, %b ]
+ br i1 %ph2, label %exit, label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt() {
+ ret i32 2
+}

ADD
tests/alive-tv/loops/phi3.srctgt.ll
+; TEST-ARGS: -src-unroll=3 -tgt-unroll=3
+
+define i32 @src() {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %if.cont ], [ 0, %entry ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %a, label %b
+
+a:
+ br label %if.cont
+
+b:
+ br label %if.cont
+
+if.cont:
+ %ph2 = phi i1 [ 1, %a ], [ 0, %b ]
+ br i1 %ph2, label %exit, label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt() {
+ ret i32 3
+}

ADD
tests/alive-tv/loops/phi4-fail.srctgt.ll
+; TEST-ARGS: -src-unroll=2 -tgt-unroll=2
+; ERROR: Value mismatch
+
+define i32 @src(i1 %bool) {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br i1 %bool, label %a, label %b
+
+a:
+ br label %header
+
+b:
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %header ], [ 0, %a ], [ 0, %b ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %exit, label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt(i1 %bool) {
+ ret i32 2
+}
\ No newline at end of file

ADD
tests/alive-tv/loops/phi4.srctgt.ll
+; TEST-ARGS: -src-unroll=2 -tgt-unroll=2
+
+define i32 @src(i1 %bool) {
+entry:
+ %i = alloca i32, align 4
+ store i32 0, i32* %i, align 4
+ br i1 %bool, label %a, label %b
+
+a:
+ br label %header
+
+b:
+ br label %header
+
+header:
+ %ph = phi i32 [ %inc, %header ], [ 0, %a ], [ 0, %b ]
+ %inc = add i32 %ph, 1
+ store i32 %inc, i32* %i, align 4
+ %cmp2 = icmp sge i32 %inc, 3
+ br i1 %cmp2, label %exit, label %header
+
+exit:
+ %l = load i32, i32* %i, align 4
+ ret i32 %l
+}
+
+define i32 @tgt(i1 %bool) {
+ ret i32 3
+}

add test cases for inner phi rewiring (#553)