Rename various cache-related enums
MODIFY
src/cacheconfigwidget.h
src/cacheconfigwidget.h
@@ -33,5 +33,5 @@ private:
} // namespace Ripes
-Q_DECLARE_METATYPE(Ripes::CacheReplPlcy);
+Q_DECLARE_METATYPE(Ripes::CacheSim::ReplPolicy);
Q_DECLARE_METATYPE(Ripes::CacheSim::CachePreset);

MODIFY
src/cachegraphic.cpp
src/cachegraphic.cpp
@@ -84,7 +84,7 @@ void CacheGraphic::dataChanged(const CacheSim::CacheTransaction& transaction) {
// Update LRU fields.
// This field must be updated for all
- if (m_cache.getReplacementPolicy() == CacheReplPlcy::LRU && m_cache.getWays() > 1) {
+ if (m_cache.getReplacementPolicy() == CacheSim::ReplPolicy::LRU && m_cache.getWays() > 1) {
if (auto* currentAccessLine = m_cache.getLine(transaction.lineIdx)) {
for (const auto& way : m_cacheTextItems[transaction.lineIdx]) {
// If LRU was just initialized, the actual (software) LRU value may be very large. Mask to the
@@ -169,13 +169,13 @@ void CacheGraphic::initializeControlBits() {
x = m_bitWidth / 2 - fm.horizontalAdvance("0") / 2;
line[setIdx].valid = drawText("0", x, y);
- if (m_cache.getWritePolicy() == CacheWrPlcy::WriteBack) {
+ if (m_cache.getWritePolicy() == CacheSim::WritePolicy::WriteBack) {
// Create dirty bit field
x = m_widthBeforeDirty + m_bitWidth / 2 - fm.horizontalAdvance("0") / 2;
line[setIdx].dirty = drawText("0", x, y);
}
- if (m_cache.getReplacementPolicy() == CacheReplPlcy::LRU && m_cache.getWays() > 1) {
+ if (m_cache.getReplacementPolicy() == CacheSim::ReplPolicy::LRU && m_cache.getWays() > 1) {
// Create LRU field
const QString lruText = QString::number(m_cache.getWays() - 1);
x = m_widthBeforeLRU + m_lruWidth / 2 - fm.horizontalAdvance(lruText) / 2;
@@ -219,7 +219,7 @@ void CacheGraphic::cacheParametersChanged() {
validItem->setToolTip("Valid bit");
horizontalAdvance += m_bitWidth;
- if (m_cache.getWritePolicy() == CacheWrPlcy::WriteBack) {
+ if (m_cache.getWritePolicy() == CacheSim::WritePolicy::WriteBack) {
m_widthBeforeDirty = horizontalAdvance;
// Draw dirty bit column
@@ -232,7 +232,7 @@ void CacheGraphic::cacheParametersChanged() {
m_widthBeforeLRU = horizontalAdvance;
- if (m_cache.getReplacementPolicy() == CacheReplPlcy::LRU && m_cache.getWays() > 1) {
+ if (m_cache.getReplacementPolicy() == CacheSim::ReplPolicy::LRU && m_cache.getWays() > 1) {
// Draw LRU bit column
new QGraphicsLineItem(horizontalAdvance + m_lruWidth, 0, horizontalAdvance + m_lruWidth, m_cacheHeight, this);
const QString LRUBitText = "LRU";

MODIFY
src/cachesim.cpp
src/cachesim.cpp
@@ -34,14 +34,14 @@ CacheSim::CacheSize CacheSim::getCacheSize() const {
size.components.push_back("Valid bits: " + QString::number(componentBits));
size.bits += componentBits;
- if (m_wrPolicy == CacheWrPlcy::WriteBack) {
+ if (m_wrPolicy == WritePolicy::WriteBack) {
// Dirty bits
unsigned componentBits = entries; // 1 bit per entry
size.components.push_back("Dirty bits: " + QString::number(componentBits));
size.bits += componentBits;
}
- if (m_replPolicy == CacheReplPlcy::LRU) {
+ if (m_replPolicy == ReplPolicy::LRU) {
// LRU bits
componentBits = getWaysBits() * entries;
size.components.push_back("LRU bits: " + QString::number(componentBits));
@@ -67,11 +67,11 @@ void CacheSim::evictAndUpdate(CacheTransaction& transaction) {
CacheWay* currentWay = nullptr;
// Update based on replacement policy
- if (m_replPolicy == CacheReplPlcy::Random) {
+ if (m_replPolicy == ReplPolicy::Random) {
// Select a random way
transaction.wayIdx = std::rand() % getWays();
currentWay = &cacheLine[transaction.wayIdx];
- } else if (m_replPolicy == CacheReplPlcy::LRU) {
+ } else if (m_replPolicy == ReplPolicy::LRU) {
if (getWays() == 1) {
// Nothing to do if we are in LRU and only have 1 set
transaction.wayIdx = 0;
@@ -154,7 +154,7 @@ void CacheSim::analyzeCacheAccess(CacheTransaction& transaction) {
updateHitRate();
}
-void CacheSim::read(uint32_t address) {
+void CacheSim::access(uint32_t address, AccessType access) {
address = address & ~0b11; // Disregard unaligned accesses
CacheTransaction transaction;
transaction.address = address;
@@ -167,7 +167,7 @@ void CacheSim::read(uint32_t address) {
emit dataChanged(transaction);
}
-void CacheSim::write(uint32_t address) {}
+
void CacheSim::undo() {}
unsigned CacheSim::getLineIdx(const uint32_t address) const {

MODIFY
src/cachesim.h
src/cachesim.h
namespace Ripes {
-enum class CacheWrPlcy { WriteThrough, WriteBack };
-enum class CacheReplPlcy { Random, LRU };
-static std::map<CacheReplPlcy, QString> s_cachePolicyStrings{{CacheReplPlcy::Random, "Random"},
- {CacheReplPlcy::LRU, "LRU"}};
-
class CacheSim : public QObject {
Q_OBJECT
public:
+ enum class WritePolicy { WriteThrough, WriteBack };
+ enum class ReplPolicy { Random, LRU };
+ enum class AccessType { Read, Write };
+
struct CacheSize {
unsigned bits = 0;
std::vector<QString> components;
@@ -56,23 +55,22 @@ public:
CacheSim(QObject* parent);
- void setWritePolicy(CacheWrPlcy policy) {
+ void setWritePolicy(WritePolicy policy) {
m_wrPolicy = policy;
updateConfiguration();
}
- void setReplacementPolicy(CacheReplPlcy policy) {
+ void setReplacementPolicy(ReplPolicy policy) {
m_replPolicy = policy;
updateConfiguration();
}
- void read(uint32_t address);
- void write(uint32_t address);
+ void access(uint32_t address, AccessType type);
void undo();
void reset();
- CacheReplPlcy getReplacementPolicy() const { return m_replPolicy; }
- CacheWrPlcy getWritePolicy() const { return m_wrPolicy; }
+ ReplPolicy getReplacementPolicy() const { return m_replPolicy; }
+ WritePolicy getWritePolicy() const { return m_wrPolicy; }
double getHitRate() const { return m_hitrate; }
CacheSize getCacheSize() const;
@@ -112,8 +110,8 @@ private:
void analyzeCacheAccess(CacheTransaction& transaction);
void updateConfiguration();
- CacheReplPlcy m_replPolicy = CacheReplPlcy::LRU;
- CacheWrPlcy m_wrPolicy = CacheWrPlcy::WriteBack;
+ ReplPolicy m_replPolicy = ReplPolicy::LRU;
+ WritePolicy m_wrPolicy = WritePolicy::WriteBack;
unsigned m_blockMask = -1;
unsigned m_lineMask = -1;
@@ -145,4 +143,7 @@ private:
std::map<unsigned, CacheAccessTrace> m_accessTrace;
};
+static std::map<CacheSim::ReplPolicy, QString> s_cachePolicyStrings{{CacheSim::ReplPolicy::Random, "Random"},
+ {CacheSim::ReplPolicy::LRU, "LRU"}};
+
} // namespace Ripes

Rename various cache-related enums