Address various compiler warnings
MODIFY
src/assembler/assembler.h
src/assembler/assembler.h
@@ -154,7 +154,7 @@ protected:
}
}
- virtual std::variant<Error, LineTokens> splitCommentFromLine(const LineTokens& tokens, int sourceLine) const {
+ virtual std::variant<Error, LineTokens> splitCommentFromLine(const LineTokens& tokens) const {
if (tokens.size() == 0) {
return {tokens};
}
@@ -295,7 +295,7 @@ protected:
* if it is a blank symbol (no other information on line).
*/
Symbols carry;
- for (unsigned i = 0; i < program.size(); i++) {
+ for (int i = 0; i < program.size(); i++) {
const auto& line = program.at(i);
if (line.isEmpty())
continue;
@@ -323,7 +323,7 @@ protected:
runOperation(directiveAndRest, DirectiveLinePair, splitDirectivesFromLine, symbolsAndRest.second, i);
tsl.directive = directiveAndRest.first;
- runOperation(remainingTokens, LineTokens, splitCommentFromLine, directiveAndRest.second, i);
+ runOperation(remainingTokens, LineTokens, splitCommentFromLine, directiveAndRest.second);
tsl.tokens = remainingTokens;
if (tsl.tokens.empty() && tsl.directive.isEmpty()) {
if (!tsl.symbols.empty()) {
@@ -359,7 +359,7 @@ protected:
* Labels and directives are only kept for the first expanded op.
*/
const auto& eops = expandedOps.value();
- for (int j = 0; j < eops.size(); j++) {
+ for (size_t j = 0; j < eops.size(); j++) {
TokenizedSrcLine tsl;
tsl.tokens = eops.at(j);
tsl.sourceLine = tokenizedLine.sourceLine;

MODIFY
src/assembler/instruction.h
src/assembler/instruction.h
@@ -66,7 +66,7 @@ using DisassembleRes = std::variant<Error, AssemblerTmp::LineTokens>;
struct OpPart {
OpPart(unsigned _value, BitRange _range) : value(_value), range(_range) {}
OpPart(unsigned _value, unsigned _start, unsigned _stop) : value(_value), range({_start, _stop}) {}
- const bool matches(uint32_t instruction) const { return range.decode(instruction) == value; }
+ bool matches(uint32_t instruction) const { return range.decode(instruction) == value; }
const unsigned value;
const BitRange range;
@@ -95,8 +95,6 @@ struct Opcode : public Field {
return std::nullopt;
}
- bool operator==(uint32_t instruction) const {}
-
const QString name;
const std::vector<OpPart> opParts;
};
@@ -122,8 +120,7 @@ struct Reg : public Field {
instruction |= m_range.apply(reg);
return std::nullopt;
}
- std::optional<AssemblerTmp::Error> decode(const uint32_t instruction, const uint32_t address,
- const ReverseSymbolMap& symbolMap,
+ std::optional<AssemblerTmp::Error> decode(const uint32_t instruction, const uint32_t, const ReverseSymbolMap&,
AssemblerTmp::LineTokens& line) const override {
const unsigned regNumber = m_range.decode(instruction);
const QString registerName = ISA::instance()->regName(regNumber);
@@ -173,8 +170,8 @@ struct Imm : public Field {
const QString& immToken = line.tokens[tokenIndex];
// Accept base 10, 16 and 2
- uint32_t uvalue;
- int32_t svalue;
+ uint32_t uvalue = 0;
+ int32_t svalue = 0;
if (repr == Repr::Signed) {
svalue = immToken.toInt(&success, 10);
} else {

MODIFY
src/assembler/matcher.h
src/assembler/matcher.h
@@ -78,7 +78,7 @@ private:
for (const auto& instr : instructions) {
if (auto instrRef = instr.get()) {
- const int nOpParts = instrRef->getOpcode().opParts.size();
+ const size_t nOpParts = instrRef->getOpcode().opParts.size();
if (nOpParts < fieldDepth) {
assert(
false &&

MODIFY
src/assembler/rv32i_assembler.cpp
src/assembler/rv32i_assembler.cpp
@@ -156,7 +156,7 @@ void RV32I_Assembler::enableExtI(RVInstrVec& instructions, RVPseudoInstrVec& pse
})));
pseudoInstructions.push_back(std::shared_ptr<RVPseudoInstr>(new RVPseudoInstr(
- "ret", {RVPseudoInstr::reg()}, [](const RVPseudoInstr&, const AssemblerTmp::TokenizedSrcLine& line) {
+ "ret", {RVPseudoInstr::reg()}, [](const RVPseudoInstr&, const AssemblerTmp::TokenizedSrcLine&) {
std::vector<AssemblerTmp::LineTokens> v;
v.push_back(QStringList() << "jalr"
<< "x0"
@@ -403,7 +403,7 @@ void RV32I_Assembler::enableExtM(RVInstrVec& instructions, RVPseudoInstrVec&) co
instructions.push_back(RType("remu", 0b111, 0b0000001));
}
-void RV32I_Assembler::enableExtF(RVInstrVec& instructions, RVPseudoInstrVec& pseudoInstructions) const {
+void RV32I_Assembler::enableExtF(RVInstrVec&, RVPseudoInstrVec&) const {
// Pseudo-op functors
// Assembler functors

MODIFY
src/isainfo.h
src/isainfo.h
@@ -152,9 +152,15 @@ public:
ISA isaID() const override { return ISA::RV32IM; }
unsigned int regCnt() const override { return 32; }
- QString regName(unsigned i) const override { return RVRegNames.size() > i ? RVRegNames.at(i) : QString(); }
- QString regAlias(unsigned i) const override { return RVRegAliases.size() > i ? RVRegAliases.at(i) : QString(); }
- QString regInfo(unsigned i) const override { return RVRegDescs.size() > i ? RVRegDescs.at(i) : QString(); }
+ QString regName(unsigned i) const override {
+ return RVRegNames.size() > static_cast<int>(i) ? RVRegNames.at(static_cast<int>(i)) : QString();
+ }
+ QString regAlias(unsigned i) const override {
+ return RVRegAliases.size() > static_cast<int>(i) ? RVRegAliases.at(static_cast<int>(i)) : QString();
+ }
+ QString regInfo(unsigned i) const override {
+ return RVRegDescs.size() > static_cast<int>(i) ? RVRegDescs.at(static_cast<int>(i)) : QString();
+ }
bool regIsReadOnly(unsigned i) const override { return i == 0; }
unsigned int bits() const override { return 32; }
int spReg() const override { return 2; }

Address various compiler warnings