Fix incorrect call to vsrtl::Design base clock/reset functions
MODIFY
src/processors/interface/ripesprocessor.h
src/processors/interface/ripesprocessor.h
@@ -234,7 +234,7 @@ public:
* @brief reverse
* Reverses the processor, undoing the latest clock cycle
*/
- virtual void reverse(){};
+ virtual void reverseProcessor(){};
/**
* @brief setMaxReverseCycles
* @p cycles denotes the maximum number of cycles that the processor is expected to be able to reverse.

MODIFY
src/processors/ripesvsrtlprocessor.h
src/processors/ripesvsrtlprocessor.h
@@ -23,10 +23,11 @@ public:
virtual void resetProcessor() override {
m_instructionsRetired = 0;
- Design::reset();
+ reset();
}
- virtual void clockProcessor() override { Design::clock(); }
+ virtual void clockProcessor() override { clock(); }
+ virtual void reverseProcessor() override { reverse(); }
long long getInstructionsRetired() const override { return m_instructionsRetired; }
long long getCycleCount() const override { return m_cycleCount; }

Fix incorrect call to vsrtl::Design base clock/reset functions