Make RegBase, a base class for Registers
MODIFY
src/pipeline.cpp
src/pipeline.cpp
#include "pipeline.h"
-Pipeline::Pipeline() {}
+Pipeline::Pipeline() {
+ registerRegs();
+}
+
+void Pipeline::registerRegs() {
+ // Registers all registers in m_regs
+ m_regs.push_back(&r_IFID);
+}
void Pipeline::immGen() {
// Generates an immediate value on the basis of an instruction opcode
@@ -26,3 +33,10 @@ void Pipeline::immGen() {
}
}
}
+
+void Pipeline::clock() {
+ // Clocks all registered registers
+ for (const auto& reg : m_regs) {
+ reg->clock();
+ }
+}

MODIFY
src/pipeline.h
src/pipeline.h
@@ -8,12 +8,15 @@ public:
Pipeline();
private:
+ void registerRegs();
void immGen();
+ void clock();
// Signals
Signal<64> imm;
// Registers
+ std::vector<RegBase*> m_regs;
Reg<32> r_IFID;
};

MODIFY
src/pipelineobjects.h
src/pipelineobjects.h
@@ -61,11 +61,17 @@ private:
// Register class
// I/O of registers are handled via. the -> operator
// reg1 -> reg2 connects m_current of reg1 to m_next of reg2
+
+class RegBase {
+public:
+ virtual void clock() = 0;
+};
+
template <int n>
-class Reg {
+class Reg : public RegBase {
public:
Reg() { ASSERT_SIZE }
- void clock() { m_current = *m_next; }
+ void clock() override { m_current = *m_next; }
uint32_t value() const { return (uint32_t)m_current; }
// Signal assignment operator

Make RegBase, a base class for Registers