Also pop access traces when undoing
MODIFY
src/cachesim/cachesim.cpp
src/cachesim/cachesim.cpp
@@ -196,7 +196,7 @@ void CacheSim::analyzeCacheAccess(CacheTransaction& transaction) const {
}
}
-void CacheSim::updateHitTrace(const CacheTransaction& transaction) {
+void CacheSim::pushAccessTrace(const CacheTransaction& transaction) {
if (m_accessTrace.size() == 0) {
m_accessTrace[0] = CacheAccessTrace(transaction.isHit);
} else {
@@ -206,6 +206,13 @@ void CacheSim::updateHitTrace(const CacheTransaction& transaction) {
emit hitrateChanged();
}
+void CacheSim::popAccessTrace() {
+ Q_ASSERT(m_accessTrace.size() > 0);
+ // The access trace should have an entry
+ m_accessTrace.erase(m_accessTrace.rbegin()->first);
+ emit hitrateChanged();
+}
+
void CacheSim::access(uint32_t address, AccessType type) {
address = address & ~0b11; // Disregard unaligned accesses
CacheTrace trace;
@@ -215,7 +222,7 @@ void CacheSim::access(uint32_t address, AccessType type) {
transaction.type = type;
analyzeCacheAccess(transaction);
- updateHitTrace(transaction);
+ pushAccessTrace(transaction);
if (!transaction.isHit) {
if (type == AccessType::Read ||
@@ -277,6 +284,7 @@ void CacheSim::undo() {
return;
const auto trace = popTrace();
+ popAccessTrace();
const auto& oldWay = trace.oldWay;
const auto& transaction = trace.transaction;

MODIFY
src/cachesim/cachesim.h
src/cachesim/cachesim.h
@@ -163,7 +163,8 @@ private:
CacheWay evictAndUpdate(CacheTransaction& transaction);
void analyzeCacheAccess(CacheTransaction& transaction) const;
void updateConfiguration();
- void updateHitTrace(const CacheTransaction& transaction);
+ void pushAccessTrace(const CacheTransaction& transaction);
+ void popAccessTrace();
ReplPolicy m_replPolicy = ReplPolicy::LRU;
WritePolicy m_wrPolicy = WritePolicy::WriteBack;
@@ -177,6 +178,10 @@ private:
int m_lines = 2; // Some power of 2
int m_ways = 2; // Some power of 2
+ /**
+ * @brief m_cacheLines
+ * The datastructure for storing our cache hierachy, as per the current cache configuration.
+ */
std::map<unsigned, CacheLine> m_cacheLines;
void updateCacheLineReplFields(CacheLine& line, unsigned wayIdx);
@@ -187,24 +192,32 @@ private:
*/
void revertCacheLineReplFields(CacheLine& line, const CacheWay& oldWay, unsigned wayIdx);
+ /**
+ * @brief m_accessTrace
+ * The access trace stack contains cache access statistics for each simulation cycle. Contrary to the TraceStack
+ * (m_traceStack).
+ */
std::map<unsigned, CacheAccessTrace> m_accessTrace;
- // Cache access trace
- // The following information is used to track all most-recent modifications (up to a given set constant) made to the
- // stack. Storing all modifications allows us to rollback any changes performed to the cache, when clock cycles are
- // undone.
+ /**
+ * @brief m_traceStack
+ * The following information is used to track all most-recent modifications made to the stack. The stack is of a
+ * fixed sized which is equal to the undo stack of VSRTL memory elements. Storing all modifications allows us to
+ * rollback any changes performed to the cache, when clock cycles are undone.
+ */
std::deque<CacheTrace> m_traceStack;
+
CacheTrace popTrace();
void pushTrace(const CacheTrace& trace);
};
-static std::map<CacheSim::ReplPolicy, QString> s_cacheReplPolicyStrings{{CacheSim::ReplPolicy::Random, "Random"},
+const static std::map<CacheSim::ReplPolicy, QString> s_cacheReplPolicyStrings{{CacheSim::ReplPolicy::Random, "Random"},
{CacheSim::ReplPolicy::LRU, "LRU"}};
-static std::map<CacheSim::WriteAllocPolicy, QString> s_cacheWriteAllocateStrings{
+const static std::map<CacheSim::WriteAllocPolicy, QString> s_cacheWriteAllocateStrings{
{CacheSim::WriteAllocPolicy::WriteAllocate, "Write allocate"},
{CacheSim::WriteAllocPolicy::NoWriteAllocate, "No write allocate"}};
-static std::map<CacheSim::WritePolicy, QString> s_cacheWritePolicyStrings{
+const static std::map<CacheSim::WritePolicy, QString> s_cacheWritePolicyStrings{
{CacheSim::WritePolicy::WriteThrough, "Write-through"},
{CacheSim::WritePolicy::WriteBack, "Write-back"}};

Also pop access traces when undoing