Update signextend calls in processor models
MODIFY
external/VSRTL
external/VSRTL
-Subproject commit e124e1d2be0b8393704067fc82e5125164ea7a22
+Subproject commit 262dfb1146a4c99f4cb40205bd9be93463935022

MODIFY
src/processors/RISC-V/rv_alu.h
src/processors/RISC-V/rv_alu.h
@@ -132,19 +132,19 @@ public:
return VT_U(0xDEADBEEF);
case ALUOp::ADDW:
- return signextend<VSRTL_VT_U, 32>(op1.uValue() + op2.uValue());
+ return VT_U(signextend<32>(op1.uValue() + op2.uValue()));
case ALUOp::SUBW:
- return signextend<VSRTL_VT_U, 32>(op1.uValue() - op2.uValue());
+ return VT_U(signextend<32>(op1.uValue() - op2.uValue()));
case ALUOp::SLW:
- return signextend<VSRTL_VT_U, 32>(op1.uValue() << (op2.uValue() & generateBitmask(5)));
+ return VT_U(signextend<32>(op1.uValue() << (op2.uValue() & generateBitmask(5))));
case ALUOp::SRAW:
- return signextend<VSRTL_VT_U, 32>(op1.sValue() >> (op2.uValue() & generateBitmask(5)));
+ return VT_U(signextend<32>(op1.sValue() >> (op2.uValue() & generateBitmask(5))));
case ALUOp::SRLW:
- return signextend<VSRTL_VT_U, 32>(op1.uValue() >> (op2.uValue() & generateBitmask(5)));
+ return VT_U(signextend<32>(op1.uValue() >> (op2.uValue() & generateBitmask(5))));
default:
throw std::runtime_error("Invalid ALU opcode");

MODIFY
src/processors/RISC-V/rv_immediate.h
src/processors/RISC-V/rv_immediate.h
@@ -19,11 +19,10 @@ public:
return instr.uValue() & 0xfffff000;
case RVInstr::JAL: {
const auto fields = RVInstrParser::getParser()->decodeJ32Instr(instr.uValue());
- return VT_U(signextend<VSRTL_VT_S, 21>(fields[0] << 20 | fields[1] << 1 | fields[2] << 11 |
- fields[3] << 12));
+ return VT_U(signextend<21>(fields[0] << 20 | fields[1] << 1 | fields[2] << 11 | fields[3] << 12));
}
case RVInstr::JALR: {
- return VT_U(signextend<VSRTL_VT_S, 12>((instr.uValue() >> 20)));
+ return VT_U(signextend<12>((instr.uValue() >> 20)));
}
case RVInstr::BEQ:
case RVInstr::BNE:
@@ -32,8 +31,8 @@ public:
case RVInstr::BLTU:
case RVInstr::BGEU: {
const auto fields = RVInstrParser::getParser()->decodeB32Instr(instr.uValue());
- return VT_U(signextend<VSRTL_VT_S, 13>((fields[0] << 12) | (fields[1] << 5) | (fields[5] << 1) |
- (fields[6] << 11)));
+ return VT_U(
+ signextend<13>((fields[0] << 12) | (fields[1] << 5) | (fields[5] << 1) | (fields[6] << 11)));
}
case RVInstr::LB:
case RVInstr::LH:
@@ -51,12 +50,12 @@ public:
case RVInstr::SLLI:
case RVInstr::SRLI:
case RVInstr::SRAI:
- return VT_U(signextend<VSRTL_VT_S, 12>((instr.uValue() >> 20)));
+ return VT_U(signextend<12>((instr.uValue() >> 20)));
case RVInstr::SB:
case RVInstr::SH:
case RVInstr::SW:
case RVInstr::SD: {
- return VT_U(signextend<VSRTL_VT_S, 12>(((instr.uValue() & 0xfe000000)) >> 20) |
+ return VT_U(signextend<12>(((instr.uValue() & 0xfe000000)) >> 20) |
((instr.uValue() & 0xf80) >> 7));
}
default:

MODIFY
src/processors/RISC-V/rv_memory.h
src/processors/RISC-V/rv_memory.h
@@ -37,17 +37,17 @@ public:
data_out << [=] {
switch (op.uValue()) {
case MemOp::LB:
- return VT_U(signextend<VSRTL_VT_U, 8>(mem->data_out.uValue() & 0xFFUL));
+ return VT_U(signextend<8>(mem->data_out.uValue() & 0xFFUL));
case MemOp::LBU:
return mem->data_out.uValue() & 0xFFUL;
case MemOp::LH:
- return VT_U(signextend<VSRTL_VT_U, 16>(mem->data_out.uValue() & 0xFFFFUL));
+ return VT_U(signextend<16>(mem->data_out.uValue() & 0xFFFFUL));
case MemOp::LHU:
return mem->data_out.uValue() & 0xFFFFUL;
case MemOp::LW:
return mem->data_out.uValue() & 0xFFFFFFFFUL;
case MemOp::LWU:
- return VT_U(signextend<VSRTL_VT_U, 32>(mem->data_out.uValue() & 0xFFFFFFFFUL));
+ return VT_U(signextend<32>(mem->data_out.uValue() & 0xFFFFFFFFUL));
case MemOp::LD:
return mem->data_out.uValue();
default:

Update signextend calls in processor models