Port visibility is no longer a global layout property
MODIFY
external/VSRTL
external/VSRTL
-Subproject commit 1a57c7606ccb13fdc5d19377ea2e5e61f8a4fbfd
+Subproject commit e6cc020a46ce040ef69bbd664eb44076031f9fba

MODIFY
src/processorregistry.h
src/processorregistry.h
@@ -21,7 +21,6 @@ using RegisterInitialization = std::map<unsigned, uint32_t>;
struct Layout {
QString name;
QString file;
- bool showPortWidth;
/**
* @brief stageLabelPositions
* Stage labels are not a part of the VSRTL processor model, and as such are not serialized within the models
@@ -68,8 +67,8 @@ private:
desc.isa = ISAInfo<ISA::RV32IM>::instance();
desc.name = "RISC-V Single Cycle Processor";
desc.description = "A single cycle RISC-V processor";
- desc.layouts = {{"Standard", ":/layouts/RISC-V/rvss/rv_ss_standard_layout.json", false, {0.5}},
- {"Extended", ":/layouts/RISC-V/rvss/rv_ss_extended_layout.json", true, {0.5}}};
+ desc.layouts = {{"Standard", ":/layouts/RISC-V/rvss/rv_ss_standard_layout.json", {0.5}},
+ {"Extended", ":/layouts/RISC-V/rvss/rv_ss_extended_layout.json", {0.5}}};
desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
m_descriptions[desc.id] = desc;
@@ -79,9 +78,8 @@ private:
desc.isa = ISAInfo<ISA::RV32IM>::instance();
desc.name = "RISC-V 5-Stage Processor";
desc.description = "A 5-Stage in-order RISC-V processor with hazard detection and forwarding.";
- desc.layouts = {
- {"Standard", ":/layouts/RISC-V/rv5s/rv5s_standard_layout.json", false, {0.11, 0.31, 0.55, 0.77, 0.92}},
- {"Extended", ":/layouts/RISC-V/rv5s/rv5s_extended_layout.json", true, {0.11, 0.31, 0.58, 0.8, 0.94}}};
+ desc.layouts = {{"Standard", ":/layouts/RISC-V/rv5s/rv5s_standard_layout.json", {0.11, 0.31, 0.55, 0.77, 0.92}},
+ {"Extended", ":/layouts/RISC-V/rv5s/rv5s_extended_layout.json", {0.11, 0.31, 0.58, 0.8, 0.94}}};
desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
m_descriptions[desc.id] = desc;
@@ -95,7 +93,7 @@ private:
"resolve all data hazard through insertions of NOP instructions to correctly schedule the code.";
desc.layouts.push_back({"Standard",
":/layouts/RISC-V/rv5swof/rv5swof_standard_layout.json",
- false,
+
{0.12, 0.35, 0.58, 0.75, 0.92}});
desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
m_descriptions[desc.id] = desc;

MODIFY
src/processortab.cpp
src/processortab.cpp
@@ -86,7 +86,6 @@ void ProcessorTab::loadLayout(const Layout& layout) {
layoutResourceFile.copy(tmpLayoutFilename);
m_vsrtlWidget->getTopLevelComponent()->loadLayoutFile(tmpLayoutFilename);
QFile::remove(tmpLayoutFilename);
- m_vsrtlWidget->setShowPortWidth(layout.showPortWidth);
// Adjust stage label positions
const auto& parent = m_stageInstructionLabels.at(0)->parentItem();

Port visibility is no longer a global layout property