Make implemented ISA statically available for each processor
MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
@@ -309,7 +309,6 @@ public:
SUBCOMPONENT(ecallChecker, EcallChecker);
// Ripes interface compliance
- virtual const ISAInfoBase* implementsISA() const override { return ISAInfo<ISA::RV32IM>::instance(); }
unsigned int stageCount() const override { return STAGECOUNT; }
unsigned int getPcForStage(unsigned int idx) const override {
// clang-format off
@@ -469,6 +468,13 @@ public:
m_syscallExitCycle = -1;
}
+ static const ISAInfoBase* ISA() {
+ static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ return &s_isa;
+ }
+
+ const ISAInfoBase* implementsISA() const override { return ISA(); };
+
private:
/**
* @brief m_syscallExitCycle

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -241,7 +241,6 @@ public:
SUBCOMPONENT(ecallChecker, EcallChecker);
// Ripes interface compliance
- virtual const ISAInfoBase* implementsISA() const override { return ISAInfo<ISA::RV32IM>::instance(); }
unsigned int stageCount() const override { return STAGECOUNT; }
unsigned int getPcForStage(unsigned int idx) const override {
// clang-format off
@@ -394,6 +393,13 @@ public:
m_syscallExitCycle = -1;
}
+ static const ISAInfoBase* ISA() {
+ static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ return &s_isa;
+ }
+
+ const ISAInfoBase* implementsISA() const override { return ISA(); };
+
private:
/**
* @brief m_syscallExitCycle

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -275,7 +275,6 @@ public:
SUBCOMPONENT(ecallChecker, EcallChecker);
// Ripes interface compliance
- virtual const ISAInfoBase* implementsISA() const override { return ISAInfo<ISA::RV32IM>::instance(); }
unsigned int stageCount() const override { return STAGECOUNT; }
unsigned int getPcForStage(unsigned int idx) const override {
// clang-format off
@@ -428,6 +427,13 @@ public:
m_syscallExitCycle = -1;
}
+ static const ISAInfoBase* ISA() {
+ static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ return &s_isa;
+ }
+
+ const ISAInfoBase* implementsISA() const override { return ISA(); };
+
private:
/**
* @brief m_syscallExitCycle

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -145,7 +145,6 @@ public:
SUBCOMPONENT(ecallChecker, EcallChecker);
// Ripes interface compliance
- virtual const ISAInfoBase* implementsISA() const override { return ISAInfo<ISA::RV32IM>::instance(); }
unsigned int stageCount() const override { return 1; }
unsigned int getPcForStage(unsigned int) const override { return pc_reg->out.uValue(); }
unsigned int nextFetchedAddress() const override { return pc_src->out.uValue(); }
@@ -201,6 +200,13 @@ public:
m_finished = false;
}
+ static const ISAInfoBase* ISA() {
+ static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ return &s_isa;
+ }
+
+ const ISAInfoBase* implementsISA() const override { return ISA(); };
+
private:
bool m_finishInNextCycle = false;
bool m_finished = false;

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
@@ -170,6 +170,8 @@ public:
protected:
// Statistics
long long m_instructionsRetired = 0;
+
+ std::shared_ptr<ISAInfoBase> m_isa;
};
} // namespace core

Make implemented ISA statically available for each processor