Initial commit for RV16C support
This commit adds support for a few RV16C instructions in the assembler.
Issues still remain in how these instructions are represented in the disassembled view and instruction model in the processor tab.
MODIFY
src/assembler/rv32i_assembler.cpp
src/assembler/rv32i_assembler.cpp
#include <QByteArray>
#include <algorithm>
+#include "rv_c_ext.h"
#include "rv_i_ext.h"
#include "rv_m_ext.h"
@@ -42,6 +43,9 @@ RV32I_Assembler::initInstructions(const ISAInfo<ISA::RV32I>* isa) const {
case 'M':
RV_M<Reg_T>::enable(isa, instructions, pseudoInstructions);
break;
+ case 'C':
+ RV_C<Reg_T>::enable(isa, instructions, pseudoInstructions);
+ break;
default:
assert(false && "Unhandled ISA extension");
}

MODIFY
src/assembler/rv64i_assembler.cpp
src/assembler/rv64i_assembler.cpp
#include <QByteArray>
#include <algorithm>
+#include "rv_c_ext.h"
#include "rv_i_ext.h"
#include "rv_m_ext.h"
@@ -44,6 +45,9 @@ RV64I_Assembler::initInstructions(const ISAInfo<ISA::RV64I>* isa) const {
case 'M':
enableExtM(isa, instructions, pseudoInstructions);
break;
+ case 'C':
+ RV_C<Reg_T>::enable(isa, instructions, pseudoInstructions);
+ break;
default:
assert(false && "Unhandled ISA extension");
}

ADD
src/assembler/rv_c_ext.h
+#pragma once
+
+#include <QObject>
+#include <functional>
+
+#include "assembler.h"
+#include "rvassembler_common.h"
+
+namespace Ripes {
+namespace Assembler {
+
+#define CAType(name, funct2, funct6) \
+ std::shared_ptr<_Instruction>(new _Instruction( \
+ Opcode<Reg__T>(name, {OpPart(0b01, 0, 1), OpPart(funct2, 5, 6), OpPart(funct6, 10, 15)}), \
+ {std::make_shared<_Reg>(isa, 2, 2, 4, "rs2'"), std::make_shared<_Reg>(isa, 1, 7, 9, "rd'/rs1'")}))
+
+/**
+ * Extension enabler.
+ * Calling an extension enabler will register the appropriate assemblers and pseudo-op expander functors with
+ * the assembler.
+ * The extension enablers are templated to allow for sharing implementations between 32- and 64-bit variants.
+ */
+template <typename Reg__T>
+struct RV_C {
+ ASSEMBLER_TYPES(Reg__T)
+ static void enable(const ISAInfoBase* isa, _InstrVec& instructions, _PseudoInstrVec& /*pseudoInstructions*/) {
+ // Pseudo-op functors
+
+ // Assembler functors
+ instructions.push_back(CAType(Token("c.and"), 0b11, 0b100011));
+ instructions.push_back(CAType(Token("c.subw"), 0b00, 0b100111));
+ instructions.push_back(CAType(Token("c.addw"), 0b01, 0b100111));
+ instructions.push_back(CAType(Token("c.or"), 0b10, 0b100011));
+ instructions.push_back(CAType(Token("c.xor"), 0b01, 0b100011));
+ instructions.push_back(CAType(Token("c.sub"), 0b00, 0b100011));
+ }
+};
+
+} // namespace Assembler
+} // namespace Ripes

MODIFY
src/isa/rv64isainfo.h
src/isa/rv64isainfo.h
@@ -26,7 +26,7 @@ public:
QString march = "rv64i";
// Proceed in canonical order
- for (const auto& ext : {"M", "A", "F", "D"}) {
+ for (const auto& ext : {"M", "A", "F", "D", "C"}) {
if (m_enabledExtensions.contains(ext)) {
march += QString(ext).toLower();
}

MODIFY
src/isa/rvisainfo_common.h
src/isa/rvisainfo_common.h
@@ -120,7 +120,7 @@ public:
protected:
QStringList m_enabledExtensions;
- QStringList m_supportedExtensions = {"M"};
+ QStringList m_supportedExtensions = {"M", "C"};
};
} // namespace Ripes

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -215,7 +215,7 @@ public:
}
static const ISAInfoBase* supportsISA() {
- static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M", "C"});
return &s_isa;
}
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); }

Initial commit for RV16C support

This commit adds support for a few RV16C instructions in the assembler.
Issues still remain in how these instructions are represented in the disassembled view and instruction model in the processor tab.