Allow multiple testdirs and ISA extensions in tst_RISCV::runTests
MODIFY
test/tst_riscv.cpp
test/tst_riscv.cpp
@@ -49,7 +49,7 @@ private:
QString m_currentTest;
- void runTests(const ProcessorID& id, const QString& testdir);
+ void runTests(const ProcessorID& id, const QStringList& extensions, const QStringList& testdirs);
void trapHandler();
@@ -59,15 +59,15 @@ private:
private slots:
- void testRV64_SingleCycle() { runTests(ProcessorID::RV64_SS, RISCV64_TEST_DIR); }
- void testRV64_5StagePipeline() { runTests(ProcessorID::RV64_5S, RISCV64_TEST_DIR); }
- void testRV64_5StagePipelineNOFW() { runTests(ProcessorID::RV64_5S_NO_FW, RISCV64_TEST_DIR); }
- void testRV64_6SDual() { runTests(ProcessorID::RV64_6S_DUAL, RISCV64_TEST_DIR); }
+ void testRV64_SingleCycle() { runTests(ProcessorID::RV64_SS, {"M"}, {RISCV64_TEST_DIR}); }
+ void testRV64_5StagePipeline() { runTests(ProcessorID::RV64_5S, {"M"}, {RISCV64_TEST_DIR}); }
+ void testRV64_5StagePipelineNOFW() { runTests(ProcessorID::RV64_5S_NO_FW, {"M"}, {RISCV64_TEST_DIR}); }
+ void testRV64_6SDual() { runTests(ProcessorID::RV64_6S_DUAL, {"M"}, {RISCV64_TEST_DIR}); }
- void testRV32_SingleCycle() { runTests(ProcessorID::RV32_SS, RISCV32_TEST_DIR); }
- void testRV32_5StagePipeline() { runTests(ProcessorID::RV32_5S, RISCV32_TEST_DIR); }
- void testRV32_5StagePipelineNOFW() { runTests(ProcessorID::RV32_5S_NO_FW, RISCV32_TEST_DIR); }
- void testRV32_6SDual() { runTests(ProcessorID::RV32_6S_DUAL, RISCV32_TEST_DIR); }
+ void testRV32_SingleCycle() { runTests(ProcessorID::RV32_SS, {"M"}, {RISCV32_TEST_DIR}); }
+ void testRV32_5StagePipeline() { runTests(ProcessorID::RV32_5S, {"M"}, {RISCV32_TEST_DIR}); }
+ void testRV32_5StagePipelineNOFW() { runTests(ProcessorID::RV32_5S_NO_FW, {"M"}, {RISCV32_TEST_DIR}); }
+ void testRV32_6SDual() { runTests(ProcessorID::RV32_6S_DUAL, {"M"}, {RISCV32_TEST_DIR}); }
};
bool tst_RISCV::skipTest(const QString& test) {
@@ -138,22 +138,21 @@ QString tst_RISCV::executeSimulator() {
return m_err;
}
-void tst_RISCV::runTests(const ProcessorID& id, const QString& testdir) {
- const auto dir = QDir(testdir);
+void tst_RISCV::runTests(const ProcessorID& id, const QStringList& extensions, const QStringList& testDirs) {
+ for (auto testDir : testDirs) {
+ const auto dir = QDir(testDir);
const auto testFiles = dir.entryList({"*.s"});
- const auto extensions = QStringList("M");
ProcessorHandler::selectProcessor(id, extensions);
for (const auto& test : testFiles) {
m_currentTest = test;
-
if (skipTest(m_currentTest))
continue;
qInfo() << "Running test: " << m_currentTest;
// Assemble test file
- auto f = QFile(testdir + QString(QDir::separator()) + test);
+ auto f = QFile(testDir + QString(QDir::separator()) + test);
if (!f.open(QIODevice::ReadOnly)) {
QFAIL("Could not open test file");
}
@@ -180,6 +179,7 @@ void tst_RISCV::runTests(const ProcessorID& id, const QString& testdir) {
qInfo() << "Test '" << m_currentTest << "' succeeded.";
}
}
+}
QTEST_APPLESS_MAIN(tst_RISCV)
#include "tst_riscv.moc"

Allow multiple testdirs and ISA extensions in tst_RISCV::runTests