Initial commit for stage instruction labels
These labels will contain the currently executing instruction for
each stage in the processor model.
MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
@@ -88,7 +88,7 @@ bool ProcessorHandler::hasBreakpoint(const uint32_t address) const {
}
bool ProcessorHandler::checkBreakpoint() {
- const auto pc = m_currentProcessor->pcForStage(0);
+ const auto pc = m_currentProcessor->getPcForStage(0);
return m_breakpoints.count(pc);
}

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
@@ -23,8 +23,6 @@ enum SysCall {
};
struct StageInfo {
- StageInfo() {}
- StageInfo(uint32_t _pc, bool _valid) : pc(_pc), pc_valid(_valid) {}
unsigned int pc = 0;
bool pc_valid = false;
};
@@ -51,11 +49,11 @@ public:
virtual unsigned int stageCount() const = 0;
/**
- * @brief pcForStage
+ * @brief getPcForStage
* @param stageIndex
* @return Program counter currently present in stage @param stageIndex
*/
- virtual unsigned int pcForStage(unsigned int stageIndex) const = 0;
+ virtual unsigned int getPcForStage(unsigned int stageIndex) const = 0;
/**
* @brief stageName

MODIFY
src/processortab.cpp
src/processortab.cpp
@@ -28,9 +28,8 @@ ProcessorTab::ProcessorTab(QToolBar* toolbar, QWidget* parent) : RipesTab(toolba
m_vsrtlWidget->setShowPortWidth(false);
m_vsrtlWidget->setLocked(true);
- // Load the default processor
- ProcessorHandler::get()->loadProcessorToWidget(m_vsrtlWidget);
- loadLayout(ProcessorRegistry::getDescription(ProcessorHandler::get()->getID()).layouts.at(0));
+ // Load the default constructed processor to the VSRTL widget
+ loadProcessorToWidget(ProcessorRegistry::getDescription(ProcessorHandler::get()->getID()).layouts.at(0));
m_stageModel = new StageTableModel(this);
connect(this, &ProcessorTab::update, m_stageModel, &StageTableModel::processorWasClocked);
@@ -39,6 +38,7 @@ ProcessorTab::ProcessorTab(QToolBar* toolbar, QWidget* parent) : RipesTab(toolba
m_ui->registerWidget->updateModel();
connect(this, &ProcessorTab::update, m_ui->registerWidget, &RegisterWidget::updateView);
connect(this, &ProcessorTab::update, this, &ProcessorTab::updateStatistics);
+ connect(this, &ProcessorTab::update, this, &ProcessorTab::updateInstructionLabels);
setupSimulatorActions();
@@ -172,15 +172,30 @@ void ProcessorTab::pause() {
m_reverseAction->setEnabled(m_vsrtlWidget->isReversible());
}
+void ProcessorTab::loadProcessorToWidget(const Layout& layout) {
+ ProcessorHandler::get()->loadProcessorToWidget(m_vsrtlWidget);
+ loadLayout(layout);
+
+ // Construct stage instruction labels
+ auto* topLevelComponent = m_vsrtlWidget->getTopLevelComponent();
+
+ m_stageInstructionLabels.clear();
+ const auto& proc = ProcessorHandler::get()->getProcessor();
+ for (int i = 0; i < proc->stageCount(); i++) {
+ auto* stagelabel = new vsrtl::Label("Stage" + QString::number(i), topLevelComponent);
+ stagelabel->setPos(topLevelComponent->boundingRect().width() / (proc->stageCount() + 1),
+ stagelabel->boundingRect().height());
+ m_stageInstructionLabels[i] = stagelabel;
+ }
+}
+
void ProcessorTab::processorSelection() {
ProcessorSelectionDialog diag;
if (diag.exec()) {
// New processor model was selected
m_vsrtlWidget->clearDesign();
ProcessorHandler::get()->selectProcessor(diag.getSelectedId(), diag.getRegisterInitialization());
- ProcessorHandler::get()->loadProcessorToWidget(m_vsrtlWidget);
- const Layout layout = diag.getSelectedLayout();
- loadLayout(layout);
+ loadProcessorToWidget(diag.getSelectedLayout());
updateInstructionModel();
m_ui->registerWidget->updateModel();
update();
@@ -243,6 +258,14 @@ void ProcessorTab::enableSimulatorControls() {
m_resetAction->setEnabled(true);
}
+void ProcessorTab::updateInstructionLabels() {
+ const auto& proc = ProcessorHandler::get()->getProcessor();
+ for (unsigned i = 0; i < proc->stageCount(); i++) {
+ const QString instr = ProcessorHandler::get()->parseInstrAt(proc->getPcForStage(i));
+ m_stageInstructionLabels.at(i)->setText(instr);
+ }
+}
+
void ProcessorTab::reset() {
m_autoClockAction->setChecked(false);
m_vsrtlWidget->reset();

MODIFY
src/processortab.h
src/processortab.h
namespace vsrtl {
class VSRTLWidget;
-}
+class Label;
+} // namespace vsrtl
namespace Ripes {
@@ -47,6 +48,7 @@ public slots:
void processorFinished();
void runFinished();
void updateStatistics();
+ void updateInstructionLabels();
void processorSelection();
@@ -62,6 +64,7 @@ private:
void updateInstructionModel();
void updateRegisterModel();
void loadLayout(const Layout&);
+ void loadProcessorToWidget(const Layout&);
Ui::ProcessorTab* m_ui;
InstructionModel* m_instrModel = nullptr;
@@ -69,6 +72,8 @@ private:
vsrtl::VSRTLWidget* m_vsrtlWidget = nullptr;
+ std::map<unsigned, vsrtl::Label*> m_stageInstructionLabels;
+
// Actions
QAction* m_selectProcessorAction = nullptr;
QAction* m_clockAction = nullptr;

MODIFY
test/tst_riscv.cpp
test/tst_riscv.cpp
@@ -94,7 +94,7 @@ bool tst_RISCV::skipTest(const QString& test) {
QString tst_RISCV::dumpRegs() {
QString str = "\n" + m_currentTest + "\nRegister dump:";
- str += "\t PC:" + QString::number(m_design->pcForStage(0), 16) + "\n";
+ str += "\t PC:" + QString::number(m_design->getPcForStage(0), 16) + "\n";
for (int i = 0; i < m_design->implementsISA()->regCnt(); i++) {
str += "\t" + m_design->implementsISA()->regName(i) + ":" + m_design->implementsISA()->regAlias(i) + ":\t" +
QString::number(m_design->registerFile->getRegister(i)) + "\n";

Initial commit for stage instruction labels

These labels will contain the currently executing instruction for
each stage in the processor model.