aneregs from debug
MODIFY
ane/2_compile/compile.mm
ane/2_compile/compile.mm
#include <stdio.h>
#import <CoreFoundation/CoreFoundation.h>
#include <string>
+#include <iostream>
extern "C" {
int ANECCompile(CFDictionaryRef param_1, CFDictionaryRef param_2, unsigned long param_3);
std::string _ZN21ZinIrEnumToStringUtil14OpCodeToStringE22ZinIrOpLayerOpCodeType(int op);
std::string _ZN21ZinIrEnumToStringUtil21NonLinearModeToStringE18ZinIrNonLinearMode(int op);
+
+ void _Z24ZinIrRegBitPrintOutDebugILj7EE11ZinIrStatusjRN11ZinHWTraitsIXT_EE6HwTypeEiRNSt3__113basic_ostreamIcNS5_11char_traitsIcEEEE(
+ unsigned long param_1, void *param_2,int param_3, std::basic_ostream<char> *param_4);
+
+void debugregs(int a1, void *dat, int a2) {
+ _Z24ZinIrRegBitPrintOutDebugILj7EE11ZinIrStatusjRN11ZinHWTraitsIXT_EE6HwTypeEiRNSt3__113basic_ostreamIcNS5_11char_traitsIcEEEE(a1, dat, a2, &std::cout);
+}
+
}
int main(int argc, char* argv[]) {

MODIFY
ane/2_compile/compile.sh
ane/2_compile/compile.sh
-#!/bin/bash
+#!/bin/bash -e
g++ compile.mm -F /System/Library/PrivateFrameworks/ -framework ANECompiler -framework CoreFoundation
rm -f model.hwx
./a.out net.plist debug

ADD
ane/2_compile/dcompile.py
+#!/usr/bin/env python3
+import os
+import sys
+import networkx as nx
+import pylab as plt
+from networkx.drawing.nx_pydot import read_dot
+
+ret = os.system("./a.out "+sys.argv[1]+" debug")
+assert(ret == 0)
+
+df = "debug/model.hwx.zinir_graph_after_reg_spill.dot"
+
+#from graphviz import render
+#render('dot', 'png', df)
+
+#plt = Image(pdot.create_png()
+#display(plt)

ADD
ane/2_compile/simple/doubleneuron.plist
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
+<plist version="1.0">
+<dict>
+ <key>Networks</key>
+ <array>
+ <string>net</string>
+ </array>
+ <key>Version</key>
+ <string>1.0.9</string>
+ <key>net</key>
+ <dict>
+ <!-- This is a one layer network -->
+ <key>Inputs</key>
+ <array>
+ <string>image</string>
+ </array>
+ <key>Units</key>
+ <array>
+ <string>my_layer</string>
+ <string>my_layer_2</string>
+ </array>
+ <key>Outputs</key>
+ <array>
+ <string>probs@output</string>
+ </array>
+
+ <key>image</key>
+ <dict>
+ <!-- default is 1 -->
+ <key>BatchSize</key>
+ <integer>1</integer>
+
+ <key>InputChannels</key>
+ <integer>1</integer>
+ <key>InputHeight</key>
+ <integer>1</integer>
+ <key>InputWidth</key>
+ <integer>77</integer>
+
+ <key>InputType</key>
+ <string>Float16</string>
+ </dict>
+
+ <key>my_layer</key>
+ <dict>
+ <key>Bottom</key>
+ <string>image</string>
+ <key>Name</key>
+ <string>my_layer</string>
+ <key>OutputType</key>
+ <string>Float16</string>
+ <key>Params</key>
+ <dict>
+ <key>Type</key>
+ <string>Sigmoid</string>
+ </dict>
+ <key>Type</key>
+ <string>Neuron</string>
+ </dict>
+
+ <key>my_layer_2</key>
+ <dict>
+ <key>Bottom</key>
+ <string>my_layer</string>
+ <key>Name</key>
+ <string>my_layer_2</string>
+ <key>OutputType</key>
+ <string>Float16</string>
+ <key>Params</key>
+ <dict>
+ <key>Type</key>
+ <string>Sigmoid</string>
+ </dict>
+ <key>Type</key>
+ <string>Neuron</string>
+ </dict>
+
+ <key>probs@output</key>
+ <dict>
+ <key>Bottom</key>
+ <string>my_layer_2</string>
+ </dict>
+
+ </dict>
+</dict>
+</plist>

MODIFY
ane/2_compile/simple/neuron.plist
ane/2_compile/simple/neuron.plist
<key>Params</key>
<dict>
<key>Type</key>
- <string>ReLU</string>
+ <string>Sigmoid</string>
</dict>
<key>Type</key>
<string>Neuron</string>

MODIFY
ane/README
ane/README
@@ -72,9 +72,13 @@ ANECCompileProcedure
0x4 @ 0x240-0x254
0x6 @ 0x258-0x274(end)
AddReloc (this is gold! x4 goes in the hwx)
+ ZinAneTd<7u>::HandleEngineLayer
rbreak ^ZinAneInstruction*
+weeee ZinIrRegBitPrintOutDebug_7u_
+print (void)debugregs(0, 0x0000000100310f30, 0)
+
== min.plist ==
Types: GOC, Conv, Broadcast, ScaledElementWise, Reshape, InputView, Neuron, Concat

ADD
ane/aneregs
+Task_ID: 0
+
+aneTD.Header[0].TID = 0
+aneTD.Header[0].NID = 0
+aneTD.Header[0].LNID = 1
+aneTD.Header[0].EON = 1
+aneTD.Header[1].ExeCycles = 0
+aneTD.Header[1].NextSize = 0
+aneTD.Header[2].LogEvents = 1058
+aneTD.Header[3].Exceptions = 0
+aneTD.Header[4].DebugLogEvents = 16775274
+aneTD.Header[5].DebugExceptions = 0
+aneTD.Header[6].DisallowAbort = 0
+aneTD.Header[6].TDSkip = 0
+aneTD.Header[6].KPC = 0
+aneTD.Header[6].SPL = 0
+aneTD.Header[6].TSR = 0
+aneTD.Header[6].SPC = 0
+aneTD.Header[6].DPC = 0
+aneTD.Header[6].TSE = 0
+aneTD.Header[6].NextPriority = 0
+aneTD.Header[6].TDE = 0
+aneTD.Header[6].SrcLoc = 1
+aneTD.Header[6].DstLoc = 1
+aneTD.Header[6].TQDis = 0
+aneTD.Header[7].NextPointer = 0
+aneTD.Header[8].RBase0 = 5
+aneTD.Header[8].RBE0 = 1
+aneTD.Header[8].RBase1 = 0
+aneTD.Header[8].RBE1 = 0
+aneTD.Header[8].WBase = 4
+aneTD.Header[8].WBE = 1
+aneTD.Header[8].TBase = 0
+aneTD.Header[8].TBE = 0
+aneTD.Header[8].ENE = 1
+aneTD.Header[9].KBase0 = 1
+aneTD.Header[9].KBE0 = 1
+aneTD.Header[9].KBase1 = 0
+aneTD.Header[9].KBE1 = 0
+aneTD.Header[9].KBase2 = 0
+aneTD.Header[9].KBE2 = 0
+aneTD.Header[9].KBase3 = 0
+aneTD.Header[9].KBE3 = 0
+
+aneRegs.KernelDMASrc.CoeffBaseAddr[0].Addr = 0
+aneRegs.KernelDMASrc.CoeffBfrSize[0].MemBfrSize = 2
+aneRegs.KernelDMASrc.CoeffDMAConfig[0].CacheHint = 2
+aneRegs.KernelDMASrc.CoeffDMAConfig[0].CrH = 0
+aneRegs.KernelDMASrc.CoeffDMAConfig[0].En = 1
+aneRegs.KernelDMASrc.CoeffDMAConfig[0].PrefetchParticipateEn = 0
+aneRegs.KernelDMASrc.CoeffBaseAddr[1].Addr = 0
+aneRegs.KernelDMASrc.CoeffBfrSize[1].MemBfrSize = 1
+aneRegs.KernelDMASrc.CoeffDMAConfig[1].CacheHint = 2
+aneRegs.KernelDMASrc.CoeffDMAConfig[1].CrH = 0
+aneRegs.KernelDMASrc.CoeffDMAConfig[1].En = 0
+aneRegs.KernelDMASrc.CoeffDMAConfig[1].PrefetchParticipateEn = 0
+aneRegs.KernelDMASrc.CoeffBaseAddr[2].Addr = 0
+aneRegs.KernelDMASrc.CoeffBfrSize[2].MemBfrSize = 1
+aneRegs.KernelDMASrc.CoeffDMAConfig[2].CacheHint = 2
+aneRegs.KernelDMASrc.CoeffDMAConfig[2].CrH = 0
+aneRegs.KernelDMASrc.CoeffDMAConfig[2].En = 0
+aneRegs.KernelDMASrc.CoeffDMAConfig[2].PrefetchParticipateEn = 0
+aneRegs.KernelDMASrc.Spare0.Spare = 0
+aneRegs.KernelDMASrc.Spare1.Spare = 0
+aneRegs.Common.Cfg.AccDoubleBufEn = 1
+aneRegs.Common.Cfg.ActiveNE = 0
+aneRegs.Common.Cfg.ContextSwitchIn = 0
+aneRegs.Common.Cfg.ContextSwitchOut = 0
+aneRegs.Common.Cfg.ShMax = 1
+aneRegs.Common.Cfg.ShMin = 0
+aneRegs.Common.Cfg.ShPref = 1
+aneRegs.Common.Cfg.SmallSourceMode = 0
+aneRegs.Common.ChCfg.InFmt = 2
+aneRegs.Common.ChCfg.OutFmt = 2
+aneRegs.Common.Cin.Cin = 1
+aneRegs.Common.ConvCfg.Kh = 1
+aneRegs.Common.ConvCfg.Kw = 1
+aneRegs.Common.ConvCfg.OCGSize = 0
+aneRegs.Common.ConvCfg.Ox = 1
+aneRegs.Common.ConvCfg.Oy = 1
+aneRegs.Common.ConvCfg.Px = 0
+aneRegs.Common.ConvCfg.Py = 0
+aneRegs.Common.ConvCfg.Sx = 1
+aneRegs.Common.ConvCfg.Sy = 1
+aneRegs.Common.Cout.Cout = 1
+aneRegs.Common.DPE.Category = 0
+aneRegs.Common.GroupConvCfg.ElemMultMode = 0
+aneRegs.Common.GroupConvCfg.NumGroups = 1
+aneRegs.Common.GroupConvCfg.UnicastCin = 1
+aneRegs.Common.GroupConvCfg.UnicastEn = 1
+aneRegs.Common.InDim.Hin = 1
+aneRegs.Common.InDim.Win = 77
+aneRegs.Common.OutDim.Hout = 1
+aneRegs.Common.OutDim.Wout = 77
+aneRegs.Common.Spare0.Spare = 0
+aneRegs.Common.Spare1.Spare = 0
+aneRegs.Common.TaskInfo.NID = 1
+aneRegs.Common.TaskInfo.TaskID = 0
+aneRegs.Common.TaskInfo.TaskQ = 0
+aneRegs.Common.TileCfg.TileHeight = 1
+aneRegs.TileDMASrc.BaseAddr.Addr = 0
+aneRegs.TileDMASrc.DMAConfig.CacheHint = 2
+aneRegs.TileDMASrc.DMAConfig.CacheHintNoReuse = 12
+aneRegs.TileDMASrc.DMAConfig.CacheHintReuse = 14
+aneRegs.TileDMASrc.DMAConfig.CrH = 0
+aneRegs.TileDMASrc.DMAConfig.DependencyMode = 0
+aneRegs.TileDMASrc.DMAConfig.En = 1
+aneRegs.TileDMASrc.Fmt.CmpVec = 0
+aneRegs.TileDMASrc.DepthStride.Stride = 3
+aneRegs.TileDMASrc.Fmt.FmtMode = 1
+aneRegs.TileDMASrc.Fmt.Interleave = 1
+aneRegs.TileDMASrc.Fmt.MemFmt = 2
+aneRegs.TileDMASrc.Fmt.OffsetCh = 0
+aneRegs.TileDMASrc.Fmt.Shift = 0
+aneRegs.TileDMASrc.Fmt.Truncate = 3
+aneRegs.TileDMASrc.GroupStride.Stride = 0
+aneRegs.TileDMASrc.PixelOffset[0].Offset = 0
+aneRegs.TileDMASrc.PixelOffset[1].Offset = 0
+aneRegs.TileDMASrc.PixelOffset[2].Offset = 0
+aneRegs.TileDMASrc.PixelOffset[3].Offset = 0
+aneRegs.TileDMASrc.PlaneStride.PlaneStride = 3
+aneRegs.TileDMASrc.RowStride.Stride = 3
+aneRegs.TileDMASrc.Spare0.Spare = 0
+aneRegs.TileDMASrc.Spare1.Spare = 0
+aneRegs.L2.ResultBase.Addr = 10
+aneRegs.L2.ResultCfg.AliasConvRslt = 0
+aneRegs.L2.ResultCfg.AliasConvSrc = 0
+aneRegs.L2.ResultCfg.AliasPlanarRslt = 0
+aneRegs.L2.ResultCfg.AliasPlanarSrc = 0
+aneRegs.L2.ResultCfg.ResultType = 2
+aneRegs.L2.ResultCfg.DMACmpVec = 0
+aneRegs.L2.ResultCfg.DMAFmt = 1
+aneRegs.L2.ResultCfg.DMAInterleave = 1
+aneRegs.L2.ResultCfg.DMAOffsetCh = 0
+aneRegs.L2.ResultCfg.L2BfrMode = 1
+aneRegs.L2.ConvResultChannelStride.Stride = 0
+aneRegs.L2.ConvResultRowStride.Stride = 0
+aneRegs.L2.L2Cfg.InputReLU = 0
+aneRegs.L2.L2Cfg.PaddingMode = 0
+aneRegs.L2.Spare0.Spare = 0
+aneRegs.L2.Spare1.Spare = 0
+aneRegs.L2.SourceBase.Addr = 0
+aneRegs.L2.SourceCfg.AliasConvRslt = 0
+aneRegs.L2.SourceCfg.AliasConvSrc = 0
+aneRegs.L2.SourceCfg.AliasPlanarRslt = 0
+aneRegs.L2.SourceCfg.AliasPlanarSrc = 0
+aneRegs.L2.SourceCfg.DMACmpVec = 0
+aneRegs.L2.SourceCfg.DMAFmt = 1
+aneRegs.L2.SourceCfg.DMAInterleave = 1
+aneRegs.L2.SourceCfg.DMAOffsetCh = 0
+aneRegs.L2.SourceCfg.Dependent = 0
+aneRegs.L2.SourceCfg.SourceType = 2
+aneRegs.L2.SourceChannelStride.Stride = 10
+aneRegs.L2.SourceRowStride.Stride = 10
+aneRegs.NE.AccBias.AccBias = 0
+aneRegs.NE.AccBias.AccBiasShift = 0
+aneRegs.NE.KernelCfg.GroupKernelReuse = 0
+aneRegs.NE.KernelCfg.KernelFmt = 0
+aneRegs.NE.KernelCfg.PalettizedBits = 8
+aneRegs.NE.KernelCfg.PalettizedEn = 0
+aneRegs.NE.KernelCfg.SparseFmt = 0
+aneRegs.NE.MACCfg.BiasMode = 0
+aneRegs.NE.MACCfg.BinaryPoint = 0
+aneRegs.NE.MACCfg.KernelMode = 1
+aneRegs.NE.MACCfg.MatrixBiasEn = 0
+aneRegs.NE.MACCfg.NonlinearMode = 2
+aneRegs.NE.MACCfg.OpMode = 4
+aneRegs.NE.MACCfg.PostScaleMode = 0
+aneRegs.NE.MatrixVectorBias.MatrixVectorBias = 0
+aneRegs.NE.PostScale.PostRightShift = 0
+aneRegs.NE.PostScale.PostScale = 15360
+aneRegs.NE.Spare0.Spare = 0
+aneRegs.NE.Spare1.Spare = 0
+aneRegs.TileDMADst.BaseAddr.Addr = 0
+aneRegs.TileDMADst.DepthStride.DepthStride = 3
+aneRegs.TileDMADst.DMAConfig.BypassEOW = 0
+aneRegs.TileDMADst.DMAConfig.CacheHint = 3
+aneRegs.TileDMADst.DMAConfig.CrH = 0
+aneRegs.TileDMADst.DMAConfig.En = 1
+aneRegs.TileDMADst.DMAConfig.L2BfrMode = 1
+aneRegs.TileDMADst.Fmt.CmpVec = 0
+aneRegs.TileDMADst.Fmt.CmpVecFill = 0
+aneRegs.TileDMADst.Fmt.FmtMode = 1
+aneRegs.TileDMADst.Fmt.Interleave = 1
+aneRegs.TileDMADst.Fmt.MemFmt = 2
+aneRegs.TileDMADst.Fmt.OffsetCh = 0
+aneRegs.TileDMADst.Fmt.Shift = 0
+aneRegs.TileDMADst.Fmt.Truncate = 3
+aneRegs.TileDMADst.Fmt.ZeroPadFirst = 1
+aneRegs.TileDMADst.Fmt.ZeroPadLast = 1
+aneRegs.TileDMADst.GroupStride.GroupStride = 0
+aneRegs.TileDMADst.PlaneStride.PlaneStride = 3
+aneRegs.TileDMADst.RowStride.RowStride = 3
+aneRegs.TileDMADst.Spare0.Spare = 0
+aneRegs.TileDMADst.Spare1.Spare = 0
+

MODIFY
ane/lib/ane.py
ane/lib/ane.py
@@ -25,6 +25,8 @@ def init_libane():
libane.ANE_Run.restype = c_int
ANE_Struct = [
+ ("u32", 0x1C, "NextCommandOffset"),
+
# section @ 0x2C len 0xF4
# reloc 0x2c-0x34?? = weights
# u32[16] 0x34-0x74 = 0x80 | 1 if used
@@ -73,13 +75,20 @@ ANE_Struct = [
("u16", 0x246, "NeuronType"), # 0x10 = copy, 0x11 = ReLU, 0x12 = custom
# section @ 0x258 len 0x18
+# HandleTileDmaDstConfig
+ # 0x258 -- *(uint *)(this + 0x334) = *(uint *)(this + 0x334) & 0xfffffc3f | 0xc0;
+ # (GetCacheHintRegisterValue & 0xf) << 6;
("u32", 0x25C, "OutputOffset"), # offset into output buffer to write at?
+ # 0x260 -- *(uint *)(this + 0x33c) = *(uint *)(this + 0x33c) & 0x3f | (int)uVar10 << 6;
("u32", 0x260, "OutputRowStride"),
("u32", 0x264, "OutputPlaneStride"),
("u32", 0x268, "OutputDepthStride"),
("u32", 0x26C, "OutputBatchStride"),
+ # 0x270 -- *(uint *)(this + 0x34c) = *(uint *)(this + 0x34c) & 0xf0ffffff | 0x1000000;
+ # uVar6 = *(uint *)(this + 0x34c) & 0xffffcfcc | 0x2031;
+ # (ZinTensorDescriptorDmaInterleave & 0xf) << 0x18;
("u8", 0x273, "OutputInterleave"), # i also have this at 0x211?
]

MODIFY
ane/ops/concat.hwx
ane/ops/concat.hwx
Binary files a/ane/ops/concat.hwx and b/ane/ops/concat.hwx differ

ADD
ane/ops/sigmoid.hwx
ane/ops/sigmoid.hwx
Binary files /dev/null and b/ane/ops/sigmoid.hwx differ

aneregs from debug