Comply with Ripes processor interface in SSRV32 core
MODIFY
src/processorregistry.h
src/processorregistry.h
@@ -50,8 +50,7 @@ private:
case ProcessorID::RISCV_5S_WOF:
case ProcessorID::RISCV_5S_WF:
case ProcessorID::RISCV_SS:
- break;
- // m_currentProcessor = std::make_unique<vsrtl::RISCV::SingleCycleRISCV>();
+ m_currentProcessor = std::make_unique<vsrtl::RISCV::SingleCycleRISCV>();
}
}

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
@@ -51,7 +51,10 @@ public:
*/
virtual StageInfo stageInfo(unsigned int stageIndex) const = 0;
- virtual void reset() { m_instructionsRetired = 0; }
+ void reset() override {
+ vsrtl::core::Design::reset();
+ m_instructionsRetired = 0;
+ }
private:
// Statistics

MODIFY
src/processors/ss/riscv_ss.h
src/processors/ss/riscv_ss.h
@@ -127,6 +127,13 @@ public:
// Gates
SUBCOMPONENT(br_and, TYPE(And<1, 2>));
SUBCOMPONENT(controlflow_or, TYPE(Or<1, 2>));
+
+ // Ripes interface compliance
+ virtual Ripes::SupportedISA implementsISA() const override { return Ripes::SupportedISA::RISCV; }
+ unsigned int stageCount() const override { return 1; }
+ unsigned int breakpointBreaksStage() const override { return 0; }
+ unsigned int pcForStage(unsigned int) const override { return pc_reg->out.uValue(); }
+ Ripes::StageInfo stageInfo(unsigned int stageIndex) const override { return {}; }
};
} // namespace RISCV
} // namespace vsrtl

Comply with Ripes processor interface in SSRV32 core