Encode register model values using register width of processor
MODIFY
src/radix.h
src/radix.h
@@ -18,7 +18,7 @@ static const auto binRegex = QRegExp("0[bB][0-1]+");
static const auto unsignedRegex = QRegExp("[0-9]+");
static const auto signedRegex = QRegExp("[-]*[0-9]+");
-static inline QString encodeRadixValue(uint32_t value, const Radix type, unsigned width = 32) {
+static inline QString encodeRadixValue(uint64_t value, const Radix type, unsigned width = 32) {
switch (type) {
case Radix::Hex: {
return "0x" + QString::number(value, 16).rightJustified(width / 4, '0');
@@ -35,7 +35,7 @@ static inline QString encodeRadixValue(uint32_t value, const Radix type, unsigne
return QString::number(value, 10);
}
case Radix::Signed: {
- return QString::number(static_cast<int32_t>(value), 10);
+ return QString::number(static_cast<uint64_t>(value), 10);
}
case Radix::ASCII: {
QString str;

MODIFY
src/registermodel.cpp
src/registermodel.cpp
@@ -9,7 +9,9 @@ namespace Ripes {
using namespace vsrtl;
-RegisterModel::RegisterModel(RegisterFileType rft, QObject* parent) : QAbstractTableModel(parent), m_rft(rft) {}
+RegisterModel::RegisterModel(RegisterFileType rft, QObject* parent) : QAbstractTableModel(parent), m_rft(rft) {
+ m_regWidth = ProcessorHandler::getProcessor()->implementsISA()->bits();
+}
std::vector<uint32_t> RegisterModel::gatherRegisterValues() {
std::vector<uint32_t> vals;
@@ -135,7 +137,7 @@ QVariant RegisterModel::tooltipData(unsigned idx) const {
}
QVariant RegisterModel::valueData(unsigned idx) const {
- return encodeRadixValue(ProcessorHandler::getRegisterValue(m_rft, idx), m_radix);
+ return encodeRadixValue(ProcessorHandler::getRegisterValue(m_rft, idx), m_radix, m_regWidth);
}
Qt::ItemFlags RegisterModel::flags(const QModelIndex& index) const {

MODIFY
src/registermodel.h
src/registermodel.h
@@ -47,6 +47,7 @@ private:
QVariant tooltipData(unsigned idx) const;
Radix m_radix = Radix::Hex;
+ unsigned m_regWidth;
RegisterFileType m_rft;
int m_mostRecentlyModifiedReg = -1;

Encode register model values using register width of processor