Enable 'instructions retired' recording in RISCV SS
MODIFY
external/VSRTL
external/VSRTL
-Subproject commit c12f7ac083c6395a85c887df750d9dddad84bd06
+Subproject commit 2c5cff5ad6b8f6a2f482ef817b7a40fccf58b994

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
@@ -140,9 +140,13 @@ public:
*/
virtual bool finished() const = 0;
+ /**
+ * @brief getInstructionsRetired
+ * @returns the number of instructions which has retired (ie. executed and no longer in the pipeline).
+ */
long long getInstructionsRetired() const { return m_instructionsRetired; }
-private:
+protected:
// Statistics
long long m_instructionsRetired = 0;
};

MODIFY
src/processors/ss/riscv_ss.h
src/processors/ss/riscv_ss.h
@@ -167,24 +167,28 @@ public:
void setRegister(unsigned i, uint32_t v) override { setSynchronousValue(registerFile->_wr_mem, i, v); }
void clock() override {
+ // Single cycle processor; 1 instruction retired per cycle!
+ m_instructionsRetired++;
+
// m_finishInNextCycle may be set during Design::clock(). Store the value before clocking the processor, and
// emit finished if this was the final clock cycle.
const bool finishInThisCycle = m_finishInNextCycle;
- Design::clock();
+ RipesProcessor::clock();
if (finishInThisCycle) {
m_finished = true;
}
}
void reverse() override {
- Design::reverse();
+ m_instructionsRetired--;
+ RipesProcessor::reverse();
// Ensure that reverses performed when we expected to finish in the following cycle, clears this expectation.
m_finishInNextCycle = false;
m_finished = false;
}
void reset() override {
- Design::reset();
+ RipesProcessor::reset();
m_finishInNextCycle = false;
m_finished = false;
}

Enable 'instructions retired' recording in RISCV SS