Allow multiple pipeline stages to trigger a breakpoint
This is needed for the dual-issue model, wherein the instruction fetch stage presents itself as 2 stages (IF_1, IF_2) wherein both stages must trigger a breakpoint.
In the future, we should add a notion between stage and way.
MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
@@ -135,8 +135,13 @@ bool ProcessorHandler::hasBreakpoint(const uint32_t address) const {
}
bool ProcessorHandler::checkBreakpoint() {
- const auto pc = m_currentProcessor->getPcForStage(0);
- return m_breakpoints.count(pc);
+ for (const auto& stage : m_currentProcessor->breakpointTriggeringStages()) {
+ const auto it = m_breakpoints.find(m_currentProcessor->getPcForStage(stage));
+ if (it != m_breakpoints.end()) {
+ return true;
+ }
+ }
+ return false;
}
void ProcessorHandler::toggleBreakpoint(const uint32_t address) {

MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
@@ -425,6 +425,7 @@ public:
}
ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
}
+ const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };
const Component* getDataMemory() const override { return data_mem; }
const Component* getInstrMemory() const override { return instr_mem; }

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -352,6 +352,7 @@ public:
}
ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
}
+ const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };
const Component* getDataMemory() const override { return data_mem; }
const Component* getInstrMemory() const override { return instr_mem; }

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -385,6 +385,7 @@ public:
}
ecallChecker->setSysCallExiting(ecallChecker->isSysCallExiting() || fr.exitSyscall);
}
+ const std::vector<unsigned> breakpointTriggeringStages() const override { return {IF}; };
const Component* getDataMemory() const override { return data_mem; }
const Component* getInstrMemory() const override { return instr_mem; }

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -170,6 +170,7 @@ public:
}
}
bool finished() const override { return m_finished; }
+ const std::vector<unsigned> breakpointTriggeringStages() const override { return {0}; };
const Component* getDataMemory() const override { return data_mem; }
const Component* getInstrMemory() const override { return instr_mem; }

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
@@ -93,6 +93,12 @@ public:
*/
virtual StageInfo stageInfo(unsigned int stageIndex) const = 0;
+ /**
+ * @brief breakpointTriggeringStages
+ * @returns the stage indicies for which a breakpoint is triggered when the breakpoint PC address enters the stage.
+ */
+ virtual const std::vector<unsigned> breakpointTriggeringStages() const = 0;
+
/**
* @brief getMemory
* @return reference to the address space utilized by the implementing processor

Allow multiple pipeline stages to trigger a breakpoint

This is needed for the dual-issue model, wherein the instruction fetch stage presents itself as 2 stages (IF_1, IF_2) wherein both stages must trigger a breakpoint.

In the future, we should add a notion between stage and way.