Relax instruction alignment constraint when RVC is enabled
MODIFY
src/assembler/assembler.h
src/assembler/assembler.h
@@ -380,11 +380,11 @@ protected:
/// Check if we're now misaligned wrt. the size of the instruction. Instructions should always be
/// emitted on an aligned boundary wrt. their size.
- unsigned alignmentDiff = addr_offset % assembledWith->size();
+ const unsigned alignmentDiff = addr_offset % (m_isa->instrByteAlignment());
if (alignmentDiff != 0) {
errors.push_back({line.sourceLine, "Instruction misaligned (" + QString::number(alignmentDiff * 8) +
"-bit boundary). This instruction must be aligned on a " +
- QString::number(assembledWith->size() * 8) +
+ QString::number((m_isa->instrByteAlignment()) * 8) +
"-bit boundary."});
break;
}

MODIFY
src/isa/isainfo.h
src/isa/isainfo.h
@@ -47,6 +47,7 @@ public:
unsigned bytes() const { return bits() / CHAR_BIT; } // Register width, in bytes
virtual unsigned instrBits() const = 0; // Instruction width, in bits
unsigned instrBytes() const { return instrBits() / CHAR_BIT; } // Instruction width, in bytes
+ virtual unsigned instrByteAlignment() const { return 0; } // Instruction Alignment, in bytes
virtual int spReg() const { return -1; } // Stack pointer
virtual int gpReg() const { return -1; } // Global pointer
virtual int syscallReg() const { return -1; } // Syscall function register

MODIFY
src/isa/rv32isainfo.h
src/isa/rv32isainfo.h
@@ -36,6 +36,8 @@ public:
return march;
}
QString CCmabi() const override { return "ilp32"; }
+
+ unsigned instrByteAlignment() const override { return extensionEnabled("C") ? 2 : 4; };
};
} // namespace Ripes

MODIFY
src/isa/rv64isainfo.h
src/isa/rv64isainfo.h
@@ -35,6 +35,8 @@ public:
return march;
}
QString CCmabi() const override { return "lp64"; }
+
+ unsigned instrByteAlignment() const override { return extensionEnabled("C") ? 2 : 4; };
};
} // namespace Ripes

MODIFY
test/riscv-tests-c-64/rvc.s
test/riscv-tests-c-64/rvc.s
@@ -18,7 +18,6 @@ test_2:
test_3:
c.addi4spn a0,1020
- c.nop
lui t2,0x1
addi t2,t2,1584
li gp,3
@@ -253,8 +252,8 @@ test_36:
c.j 4
c.j 4
c.j fail
- c.nop
sub ra,ra,t0
+ c.nop
li t2,-2
li gp,36
bne ra,t2,fail

MODIFY
test/riscv-tests-c/rvc.s
test/riscv-tests-c/rvc.s
@@ -18,7 +18,6 @@ test_2:
test_3:
c.addi4spn a0,1020
- c.nop
lui t2,0x1
addi t2,t2,1584
li gp,3
@@ -210,8 +209,8 @@ test_36:
c.j 4
c.j 4
c.j fail
- c.nop
sub ra,ra,t0
+ c.nop
li t2,-2
li gp,36
bne ra,t2,fail
@@ -224,8 +223,8 @@ test_37:
c.j 4
c.j 4
c.j fail
- c.nop
sub ra,ra,t0
+ c.nop
li t2,-2
li gp,37
bne ra,t2,fail

Relax instruction alignment constraint when RVC is enabled (#168)