Add RV5S_NO_FW to tst_cosimulate and apply formatting
MODIFY
src/processorregistry.h
src/processorregistry.h
#include "processors/ripesprocessor.h"
#include "processors/RISC-V/rv5s/rv5s.h"
+#include "processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h"
#include "processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h"
#include "processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h"
-#include "processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h"
#include "processors/RISC-V/rv6s_dual/rv6s_dual.h"
#include "processors/RISC-V/rvss/rvss.h"
@@ -128,7 +128,7 @@ private:
desc.id = ProcessorID::RV5S_NO_FW;
desc.isa = vsrtl::core::RV5S_NO_FW::ISA();
desc.name = "5-Stage Processor w/o forwarding unit";
- desc.description = "A 5-Stage in-order processor with hazard detection/elimination but no forwarding unit.";
+ desc.description = "A 5-stage in-order processor with hazard detection/elimination but no forwarding unit.";
desc.layouts = {{"Standard",
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0}, QPointF{0.75, 0}, QPointF{0.88, 0}}},

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
#include "../rv_registerfile.h"
// Stage separating registers
-#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h"
#include "../rv5s/rv5s_exmem.h"
#include "../rv5s/rv5s_memwb.h"
+#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h"
#include "rv5s_no_fw_idex.h"
// Hazard detection unit

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_hazardunit.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_hazardunit.h
@@ -112,7 +112,8 @@ private:
return false;
}
- return ((writeIdx == idx1) || ((writeIdx == idx2) && (idx2isReg || isBranch || isMemWrite))) && regWrite && !exBranchTaken;
+ return ((writeIdx == idx1) || ((writeIdx == idx2) && (idx2isReg || isBranch || isMemWrite))) && regWrite &&
+ !exBranchTaken;
}
};
} // namespace core

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_idex.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_idex.h
@@ -13,8 +13,8 @@ namespace core {
using namespace Ripes;
/**
- * @brief The RV5S_IDEX class
- * A specialization of the default IDEX stage separating register utilized by the rv5s_no_fw_hz processor.
+ * @brief The RV5S_NO_FW_IDEX class
+ * A specialization of the default IDEX stage separating register utilized by the rv5s_no_fw processor.
*/
class RV5S_NO_FW_IDEX : public IDEX {
public:

MODIFY
test/tst_cosimulate.cpp
test/tst_cosimulate.cpp
@@ -82,6 +82,7 @@ private slots:
*/
void testRV6SDual() { cosimulate(ProcessorID::RV6S_DUAL, {"M"}); }
void testRV5S() { cosimulate(ProcessorID::RV5S, {"M"}); }
+ void testRV5SNoFW() { cosimulate(ProcessorID::RV5S_NO_FW, {"M"}); }
};
void tst_Cosimulate::handleSysCall() {

Add RV5S_NO_FW to tst_cosimulate and apply formatting