ane reg notes
MODIFY
ane/README
ane/README
@@ -77,7 +77,7 @@ ANECCompileProcedure
rbreak ^ZinAneInstruction*
weeee ZinIrRegBitPrintOutDebug_7u_
-print (void)debugregs(0, 0x0000000100310f30, 0)
+print (void)debugregs(0, 0x0000000100211030+8, 3)
== min.plist ==

MODIFY
ane/aneregs
ane/aneregs
+// ZinIrRegBitPrintOutDebug_7u_
+
Task_ID: 0
+header = 10*4 = 0x28
+
aneTD.Header[0].TID = 0
aneTD.Header[0].NID = 0
aneTD.Header[0].LNID = 1
@@ -42,6 +46,8 @@ aneTD.Header[9].KBE2 = 0
aneTD.Header[9].KBase3 = 0
aneTD.Header[9].KBE3 = 0
+0x28 = 00 F8 01 F4 = 0x1F800
++0x30
aneRegs.KernelDMASrc.CoeffBaseAddr[0].Addr = 0
aneRegs.KernelDMASrc.CoeffBfrSize[0].MemBfrSize = 2
aneRegs.KernelDMASrc.CoeffDMAConfig[0].CacheHint = 2
@@ -62,6 +68,9 @@ aneRegs.KernelDMASrc.CoeffDMAConfig[2].En = 0
aneRegs.KernelDMASrc.CoeffDMAConfig[2].PrefetchParticipateEn = 0
aneRegs.KernelDMASrc.Spare0.Spare = 0
aneRegs.KernelDMASrc.Spare1.Spare = 0
+
+0x124 = 00 00 00 3C = 0
++0x1d4
aneRegs.Common.Cfg.AccDoubleBufEn = 1
aneRegs.Common.Cfg.ActiveNE = 0
aneRegs.Common.Cfg.ContextSwitchIn = 0
@@ -98,6 +107,9 @@ aneRegs.Common.TaskInfo.NID = 1
aneRegs.Common.TaskInfo.TaskID = 0
aneRegs.Common.TaskInfo.TaskQ = 0
aneRegs.Common.TileCfg.TileHeight = 1
+
+0x168 = 00 38 01 6C = 0x13800
++0x220
aneRegs.TileDMASrc.BaseAddr.Addr = 0
aneRegs.TileDMASrc.DMAConfig.CacheHint = 2
aneRegs.TileDMASrc.DMAConfig.CacheHintNoReuse = 12
@@ -122,6 +134,9 @@ aneRegs.TileDMASrc.PlaneStride.PlaneStride = 3
aneRegs.TileDMASrc.RowStride.Stride = 3
aneRegs.TileDMASrc.Spare0.Spare = 0
aneRegs.TileDMASrc.Spare1.Spare = 0
+
+0x1dc = 00 48 00 44 = 0x4800
++0x29c
aneRegs.L2.ResultBase.Addr = 10
aneRegs.L2.ResultCfg.AliasConvRslt = 0
aneRegs.L2.ResultCfg.AliasConvSrc = 0
@@ -152,6 +167,11 @@ aneRegs.L2.SourceCfg.Dependent = 0
aneRegs.L2.SourceCfg.SourceType = 2
aneRegs.L2.SourceChannelStride.Stride = 10
aneRegs.L2.SourceRowStride.Stride = 10
+
+0x228 = 00 88 00 0C = 0x8800
++0x2f0
+0x23C = 00 C8 00 10 = 0xC800
++0x30c
aneRegs.NE.AccBias.AccBias = 0
aneRegs.NE.AccBias.AccBiasShift = 0
aneRegs.NE.KernelCfg.GroupKernelReuse = 0
@@ -171,6 +191,9 @@ aneRegs.NE.PostScale.PostRightShift = 0
aneRegs.NE.PostScale.PostScale = 15360
aneRegs.NE.Spare0.Spare = 0
aneRegs.NE.Spare1.Spare = 0
+
+0x254 = 00 78 01 18 = 0x17800
++0x32c
aneRegs.TileDMADst.BaseAddr.Addr = 0
aneRegs.TileDMADst.DepthStride.DepthStride = 3
aneRegs.TileDMADst.DMAConfig.BypassEOW = 0

MODIFY
ane/lib/ane.py
ane/lib/ane.py
@@ -25,15 +25,16 @@ def init_libane():
libane.ANE_Run.restype = c_int
ANE_Struct = [
+# aneTD.Header
("u32", 0x1C, "NextCommandOffset"),
-# section @ 0x2C len 0xF4
+# KernelDMASrc @ section @ 0x2C len 0xF4
# reloc 0x2c-0x34?? = weights
# u32[16] 0x34-0x74 = 0x80 | 1 if used
# u32[16] 0x74-0xB4 = <channel data offset>
# u32[16] 0xB4-0xF4 = <channel data length>
-# section @ 0x128 len 0x3C (conv)
+# Common @ section @ 0x128 len 0x3C (conv)
("u16", 0x128, "InputWidth"),
("u16", 0x12A, "InputHeight"),
("u16", 0x12C, "InputDepth"),
@@ -53,7 +54,7 @@ ANE_Struct = [
("u16", 0x14C, "BatchSize"),
-# section @ 0x16C len 0x6C (input)
+# TileDMASrc @ section @ 0x16C len 0x6C (input)
# reloc 0x16c-0x174 = image
("u32", 0x178, "InputRowStride"),
("u32", 0x17C, "InputPlaneStride"),
@@ -62,19 +63,21 @@ ANE_Struct = [
("u8", 0x1A7, "InputInterleave"),
-# section @ 0x1E0 len 0x44
+# L2 @ section @ 0x1E0 len 0x44
# [0x1ec, 0x1f0, 0x1f4, 0x1f8, 0x214] = number of engines
# [0x1f0, 0x1f4, 0x1f8, 0x214] = engines for inconv?
# [0x21c, 0x220, 0x224] = engines for outconv?
-# section @ 0x22c len 0xC (scaling)
+# NE @ section @ 0x22c len 0xC (scaling)
("u16", 0x230, "BiasScalar"),
("u16", 0x232, "ScaleScalar"),
# section @ 0x240 len 0x10
("u16", 0x246, "NeuronType"), # 0x10 = copy, 0x11 = ReLU, 0x12 = custom
+ ("u32", 0x250, "PostScale"),
+
+# TileDMADst @ section @ 0x258 len 0x18
-# section @ 0x258 len 0x18
# HandleTileDmaDstConfig
# 0x258 -- *(uint *)(this + 0x334) = *(uint *)(this + 0x334) & 0xfffffc3f | 0xc0;
# (GetCacheHintRegisterValue & 0xf) << 6;

ane reg notes