Fix XLEN and RV_INSTR_WIDTH mismatches in processors
MODIFY
src/assembler/rv64i_assembler.cpp
src/assembler/rv64i_assembler.cpp
@@ -66,7 +66,7 @@ void RV64I_Assembler::enableExtI(const ISAInfoBase* isa, InstrVec& instructions,
instructions.push_back(LoadType(Token("lwu"), 0b110));
instructions.push_back(LoadType(Token("ld"), 0b011));
- instructions.push_back(LoadType(Token("sd"), 0b011));
+ instructions.push_back(SType(Token("sd"), 0b011));
}
void RV64I_Assembler::enableExtM(const ISAInfoBase* isa, InstrVec& instructions, PseudoInstrVec& pseudoInstructions) {

MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
@@ -478,7 +478,7 @@ public:
}
static const ISAInfoBase* ISA() {
- static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -453,7 +453,7 @@ public:
}
static const ISAInfoBase* ISA() {
- static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -404,7 +404,7 @@ public:
}
static const ISAInfoBase* ISA() {
- static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h
@@ -20,7 +20,7 @@ public:
}
REGISTERED_CLEN_INPUT(pc4, XLEN);
- REGISTERED_CLEN_INPUT(instr, XLEN);
+ REGISTERED_CLEN_INPUT(instr, RV_INSTR_WIDTH);
REGISTERED_CLEN_INPUT(pc, XLEN);
// Register controls

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -437,7 +437,7 @@ public:
}
static const ISAInfoBase* ISA() {
- static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
@@ -523,14 +523,14 @@ public:
SUBCOMPONENT(data_way_pc, TYPE(EnumMultiplexer<WaySrc, XLEN>));
SUBCOMPONENT(data_way_opcode, TYPE(EnumMultiplexer<WaySrc, RVInstr::width()>));
- SUBCOMPONENT(data_way_instr, TYPE(EnumMultiplexer<WaySrc, XLEN>));
+ SUBCOMPONENT(data_way_instr, TYPE(EnumMultiplexer<WaySrc, RV_INSTR_WIDTH>));
SUBCOMPONENT(data_way_wr_reg_idx, TYPE(EnumMultiplexer<WaySrc, RV_REGS_BITS>));
SUBCOMPONENT(data_way_r1_reg_idx, TYPE(EnumMultiplexer<WaySrc, RV_REGS_BITS>));
SUBCOMPONENT(data_way_r2_reg_idx, TYPE(EnumMultiplexer<WaySrc, RV_REGS_BITS>));
SUBCOMPONENT(exec_way_pc, TYPE(EnumMultiplexer<WaySrc, XLEN>));
SUBCOMPONENT(exec_way_opcode, TYPE(EnumMultiplexer<WaySrc, RVInstr::width()>));
- SUBCOMPONENT(exec_way_instr, TYPE(EnumMultiplexer<WaySrc, XLEN>));
+ SUBCOMPONENT(exec_way_instr, TYPE(EnumMultiplexer<WaySrc, RV_INSTR_WIDTH>));
SUBCOMPONENT(exec_way_wr_reg_idx, TYPE(EnumMultiplexer<WaySrc, RV_REGS_BITS>));
SUBCOMPONENT(exec_way_r1_reg_idx, TYPE(EnumMultiplexer<WaySrc, RV_REGS_BITS>));
SUBCOMPONENT(exec_way_r2_reg_idx, TYPE(EnumMultiplexer<WaySrc, RV_REGS_BITS>));
@@ -795,7 +795,7 @@ public:
}
static const ISAInfoBase* ISA() {
- static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M"});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_idii.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_idii.h
@@ -42,8 +42,8 @@ public:
CONNECT_REGISTERED_CLEN_INPUT(instr_exec, clear, enable);
}
- REGISTERED_CLEN_INPUT(instr_data, XLEN);
- REGISTERED_CLEN_INPUT(instr_exec, XLEN);
+ REGISTERED_CLEN_INPUT(instr_data, RV_INSTR_WIDTH);
+ REGISTERED_CLEN_INPUT(instr_exec, RV_INSTR_WIDTH);
REGISTERED_CLEN_INPUT(pc_data, XLEN);
REGISTERED_CLEN_INPUT(pc_exec, XLEN);

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_ifid.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_ifid.h
@@ -15,7 +15,7 @@ public:
CONNECT_REGISTERED_CLEN_INPUT(instr2, this->clear, this->enable);
}
- REGISTERED_CLEN_INPUT(instr2, XLEN);
+ REGISTERED_CLEN_INPUT(instr2, RV_INSTR_WIDTH);
};
} // namespace core

MODIFY
src/processors/RISC-V/rv_immediate.h
src/processors/RISC-V/rv_immediate.h
@@ -19,11 +19,11 @@ public:
return instr.uValue() & 0xfffff000;
case RVInstr::JAL: {
const auto fields = RVInstrParser::getParser()->decodeJ32Instr(instr.uValue());
- return VT_U(
- signextend<int32_t, 21>(fields[0] << 20 | fields[1] << 1 | fields[2] << 11 | fields[3] << 12));
+ return VT_U(signextend<VSRTL_VT_S, 21>(fields[0] << 20 | fields[1] << 1 | fields[2] << 11 |
+ fields[3] << 12));
}
case RVInstr::JALR: {
- return VT_U(signextend<int32_t, 12>((instr.uValue() >> 20)));
+ return VT_U(signextend<VSRTL_VT_S, 12>((instr.uValue() >> 20)));
}
case RVInstr::BEQ:
case RVInstr::BNE:
@@ -32,7 +32,7 @@ public:
case RVInstr::BLTU:
case RVInstr::BGEU: {
const auto fields = RVInstrParser::getParser()->decodeB32Instr(instr.uValue());
- return VT_U(signextend<int32_t, 13>((fields[0] << 12) | (fields[1] << 5) | (fields[5] << 1) |
+ return VT_U(signextend<VSRTL_VT_S, 13>((fields[0] << 12) | (fields[1] << 5) | (fields[5] << 1) |
(fields[6] << 11)));
}
case RVInstr::LB:
@@ -51,12 +51,12 @@ public:
case RVInstr::SLLI:
case RVInstr::SRLI:
case RVInstr::SRAI:
- return VT_U(signextend<int32_t, 12>((instr.uValue() >> 20)));
+ return VT_U(signextend<VSRTL_VT_S, 12>((instr.uValue() >> 20)));
case RVInstr::SB:
case RVInstr::SH:
case RVInstr::SW:
case RVInstr::SD: {
- return VT_U(signextend<int32_t, 12>(((instr.uValue() & 0xfe000000)) >> 20) |
+ return VT_U(signextend<VSRTL_VT_S, 12>(((instr.uValue() & 0xfe000000)) >> 20) |
((instr.uValue() & 0xf80) >> 7));
}
default:
@@ -66,7 +66,7 @@ public:
}
INPUTPORT_ENUM(opcode, RVInstr);
- INPUTPORT(instr, XLEN);
+ INPUTPORT(instr, RV_INSTR_WIDTH);
OUTPUTPORT(imm, XLEN);
};

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -210,7 +210,7 @@ public:
}
static const ISAInfoBase* ISA() {
- static auto s_isa = ISAInfo<ISA::RV32I>(QStringList{"M" /*, "F" */});
+ static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}

Fix XLEN and RV_INSTR_WIDTH mismatches in processors