Add descriptions to stage separating registers
MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_exmem.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_exmem.h
@@ -13,6 +13,7 @@ template <unsigned XLEN>
class EXMEM : public Component {
public:
EXMEM(const std::string& name, SimComponent* parent) : Component(name, parent) {
+ setDescription("Execute/memory stage separating register");
CONNECT_REGISTERED_CLEN_INPUT(pc, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(pc4, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(alures, clear, enable);

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_idex.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_idex.h
@@ -13,6 +13,7 @@ template <unsigned XLEN>
class IDEX : public Component {
public:
IDEX(const std::string& name, SimComponent* parent) : Component(name, parent) {
+ setDescription("Instruction decode/execute stage separating register");
CONNECT_REGISTERED_CLEN_INPUT(pc4, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(pc, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(r1, clear, enable);

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h
@@ -13,6 +13,7 @@ template <unsigned XLEN>
class IFID : public Component {
public:
IFID(const std::string& name, SimComponent* parent) : Component(name, parent) {
+ setDescription("Instruction fetch/Instruction decode stage separating register");
CONNECT_REGISTERED_CLEN_INPUT(pc4, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(pc, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(instr, clear, enable);

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_memwb.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_memwb.h
@@ -13,6 +13,7 @@ template <unsigned XLEN>
class MEMWB : public Component {
public:
MEMWB(const std::string& name, SimComponent* parent) : Component(name, parent) {
+ setDescription("Memory/write-back stage separating register");
CONNECT_REGISTERED_INPUT(pc);
CONNECT_REGISTERED_INPUT(pc4);
CONNECT_REGISTERED_INPUT(alures);

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_idii.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_idii.h
@@ -16,6 +16,7 @@ template <unsigned XLEN>
class RV5S_IDII_DUAL : public Component {
public:
RV5S_IDII_DUAL(const std::string& name, SimComponent* parent) : Component(name, parent) {
+ setDescription("Instruction decode/instruction issue stage separating register");
CONNECT_REGISTERED_CLEN_INPUT(pc_data, clear, enable);
CONNECT_REGISTERED_CLEN_INPUT(pc_exec, clear, enable);

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_iiex.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_iiex.h
@@ -11,6 +11,7 @@ template <unsigned XLEN>
class RV5S_IIEX_DUAL : public RV5S_IDEX<XLEN> {
public:
RV5S_IIEX_DUAL(const std::string& name, SimComponent* parent) : RV5S_IDEX<XLEN>(name, parent) {
+ SimBase::setDescription("Instruction issue/execute stage separating register");
CONNECT_REGISTERED_CLEN_INPUT(r1_data, this->clear, this->enable);
CONNECT_REGISTERED_CLEN_INPUT(r2_data, this->clear, this->enable);

MODIFY
src/processors/RISC-V/rv_immediate.h
src/processors/RISC-V/rv_immediate.h
@@ -14,6 +14,7 @@ class Immediate : public Component {
public:
Immediate(const std::string& name, SimComponent* parent) : Component(name, parent) {
+ setDescription("Immediate value decoder");
imm << [=] {
Switch(opcode, RVInstr) {
case RVInstr::LUI:

Add descriptions to stage separating registers