Fix incorrect memory indexing in 64-bit processors
MODIFY
external/VSRTL
external/VSRTL
-Subproject commit e41a50e16a47551250b8837e69b08fdd1d75decc
+Subproject commit aa5b63e83adec1797a5b25e453cc8a6235e07649

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_instr_mem.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_instr_mem.h
@@ -14,9 +14,10 @@ class ROM_DUAL : public ROM<addrWidth, dataWidth, byteIndexed> {
public:
ROM_DUAL(std::string name, SimComponent* parent) : ROM<addrWidth, dataWidth, byteIndexed>(name, parent) {
data_out2 << [=] {
- const auto accessAddress = this->addr.uValue() + 4;
- const auto v = this->read(accessAddress);
- return v;
+ auto _addr = this->addr.uValue() + 4;
+ auto val =
+ this->read(_addr, dataWidth / CHAR_BIT, ceillog2((byteIndexed ? addrWidth : dataWidth) / CHAR_BIT));
+ return val;
};
}

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual_registerfile.h
src/processors/RISC-V/rv6s_dual/rv6s_dual_registerfile.h
@@ -63,7 +63,7 @@ public:
INPUTPORT(data_2_in, XLEN);
INPUTPORT(wr_2_en, 1);
- VSRTL_VT_U getRegister(unsigned i) { return m_memory->readMem(i << 2); }
+ VSRTL_VT_U getRegister(unsigned i) { return m_memory->readMem(i << ceillog2(XLEN / CHAR_BIT), XLEN / CHAR_BIT); }
private:
/**

MODIFY
src/processors/RISC-V/rv_registerfile.h
src/processors/RISC-V/rv_registerfile.h
@@ -24,7 +24,7 @@ public:
wr_addr >> _wr_mem->addr;
wr_en_0->out >> _wr_mem->wr_en;
data_in >> _wr_mem->data_in;
- 4 >> _wr_mem->wr_width;
+ (XLEN / CHAR_BIT) >> _wr_mem->wr_width;
// Reads
r1_addr >> _rd1_mem->addr;
@@ -83,7 +83,9 @@ public:
OUTPUTPORT(r1_out, XLEN);
OUTPUTPORT(r2_out, XLEN);
- VSRTL_VT_U getRegister(unsigned i) const { return m_memory->readMemConst(i << 2); }
+ VSRTL_VT_U getRegister(unsigned i) const {
+ return m_memory->readMemConst(i << ceillog2(XLEN / CHAR_BIT), XLEN / CHAR_BIT);
+ }
std::vector<VSRTL_VT_U> getRegisters() {
std::vector<VSRTL_VT_U> regs;

Fix incorrect memory indexing in 64-bit processors