Reduce use of ASSEMBLER_TYPES
MODIFY
src/assembler/assembler.h
src/assembler/assembler.h
@@ -52,7 +52,7 @@ namespace Assembler {
}
// Macro for defining type aliases for register/instruction width specific types of the assembler types
-#define ASSEMBLER_TYPES(_Reg_T) \
+#define AssemblerTypes(_Reg_T) \
using _InstrVec = InstrVec<_Reg_T>; \
using _InstrMap = InstrMap<_Reg_T>; \
using _PseudoInstrVec = PseudoInstrVec<_Reg_T>; \
@@ -76,25 +76,25 @@ namespace Assembler {
template <typename Reg_T>
class Assembler : public AssemblerBase {
static_assert(std::numeric_limits<Reg_T>::is_integer, "Register type must be integer");
- ASSEMBLER_TYPES(Reg_T)
public:
+ AssemblerTypes(Reg_T);
Assembler(const ISAInfoBase* isa) : m_isa(isa) {}
AssembleResult assemble(const QStringList& programLines, const SymbolMap* symbols = nullptr) const override {
AssembleResult result;
- // Per default, emit to .text until otherwise specified
+ /// by default, emit to .text until otherwise specified
setCurrentSegment(".text");
m_symbolMap.clear();
if (symbols) {
m_symbolMap = *symbols;
}
- // Tokenize each source line and separate symbol from remainder of tokens
+ /// Tokenize each source line and separate symbol from remainder of tokens
runPass(tokenizedLines, SourceProgram, pass0, programLines);
- // Pseudo instruction expansion
+ /// Pseudo instruction expansion
runPass(expandedLines, SourceProgram, pass1, tokenizedLines);
/** Assemble. During assembly, we generate:

MODIFY
src/assembler/assemblererror.h
src/assembler/assemblererror.h
namespace Ripes {
namespace Assembler {
-// An error is defined as a reference to a source line index + an error string
+/// An error is defined as a reference to a source line index + an error string
using Error = std::pair<unsigned, QString>;
class Errors : public std::vector<Error> {
public:

MODIFY
src/assembler/directive.h
src/assembler/directive.h
@@ -14,6 +14,8 @@ namespace Assembler {
class AssemblerBase;
+/// A directive argument consists of a tokenized source line as well as the program section of which the directive
+/// handler should work on.
struct DirectiveArg {
const TokenizedSrcLine& line;
const ProgramSection* section;
@@ -27,6 +29,7 @@ public:
Directive(const QString& directive, const DirectiveHandler& handler, bool isEarly = false)
: m_directive(directive), m_handler(handler), m_early(isEarly) {}
+ /// Executes the directive handler.
HandleDirectiveRes handle(const AssemblerBase* assembler, const DirectiveArg& arg) {
return m_handler(assembler, arg);
}

MODIFY
src/assembler/rv32i_assembler.h
src/assembler/rv32i_assembler.h
@@ -14,8 +14,6 @@ class RV32I_Assembler : public QObject, public Assembler<uint32_t> {
public:
using Reg_T = uint32_t;
- ASSEMBLER_TYPES(Reg_T)
-
RV32I_Assembler(const ISAInfo<ISA::RV32I>* isa);
private:

MODIFY
src/assembler/rv64i_assembler.h
src/assembler/rv64i_assembler.h
@@ -10,9 +10,7 @@ namespace Assembler {
class RV64I_Assembler : public QObject, public Assembler<uint64_t> {
Q_OBJECT
-
using Reg_T = uint64_t;
- ASSEMBLER_TYPES(Reg_T)
public:
RV64I_Assembler(const ISAInfo<ISA::RV64I>* isa);

MODIFY
src/assembler/rv_i_ext.h
src/assembler/rv_i_ext.h
@@ -17,12 +17,12 @@ namespace Assembler {
*/
template <typename Reg__T>
struct RV_I {
+ AssemblerTypes(Reg__T);
enum class Options {
shifts64BitVariant, // appends 'w' to 32-bit shift operations, for use in the 64-bit RISC-V ISA
LI64BitVariant // Modifies LI to be able to emit 64-bit constants
};
- ASSEMBLER_TYPES(Reg__T)
static void enable(const ISAInfoBase* isa, _InstrVec& instructions, _PseudoInstrVec& pseudoInstructions,
const std::set<Options>& options = {}) {
// Pseudo-op functors

MODIFY
src/assembler/rv_m_ext.h
src/assembler/rv_m_ext.h
@@ -17,7 +17,7 @@ namespace Assembler {
*/
template <typename Reg__T>
struct RV_M {
- ASSEMBLER_TYPES(Reg__T)
+ AssemblerTypes(Reg__T);
static void enable(const ISAInfoBase* isa, _InstrVec& instructions, _PseudoInstrVec& /*pseudoInstructions*/) {
// Pseudo-op functors

Reduce use of ASSEMBLER_TYPES