Fixed error with store instructions not wait for result of calculating instructions
MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -222,6 +222,7 @@ public:
decode->r2_reg_idx >> hzunit->id_reg2_idx;
control->alu_op2_ctrl >> hzunit->id_alu_op_ctrl_2;
control->do_branch >> hzunit->id_do_branch;
+ control->mem_do_write_ctrl >> hzunit->id_mem_do_write;
idex_reg->mem_do_read_out >> hzunit->ex_do_mem_read_en;
idex_reg->reg_do_write_out >> hzunit->ex_do_reg_write;

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_hazardunit.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_hazardunit.h
@@ -21,6 +21,7 @@ public:
INPUTPORT(id_reg1_idx, RV_REGS_BITS);
INPUTPORT(id_reg2_idx, RV_REGS_BITS);
INPUTPORT(id_do_branch, 1);
+ INPUTPORT(id_mem_do_write, 1);
INPUTPORT_ENUM(id_alu_op_ctrl_2, AluSrc2);
INPUTPORT(ex_reg_wr_idx, RV_REGS_BITS);
@@ -96,6 +97,9 @@ private:
// Get branch information (when branch, idx2isReg must be ignored, because it is IMM)
const bool isBranch = id_do_branch.uValue();
+ // Get mem write information (when write to memory, idx2isReg must be ignored, because it is IMM)
+ const bool isMemWrite = id_mem_do_write.uValue();
+
// Get jump information (when jump, no stall needed because instruction will flushed)
const bool doJump = ex_do_jump.uValue();
@@ -103,8 +107,22 @@ private:
if((writeIdx == 0) || (doJump)){
return false;
}
- return ((writeIdx == idx1) || ((writeIdx == idx2) && (idx2isReg || isBranch))) && regWrite;
+ return ((writeIdx == idx1) || ((writeIdx == idx2) && (idx2isReg || isBranch || isMemWrite))) && regWrite;
}
};
} // namespace core
} // namespace vsrtl
+
+/*
+idx1 = 0x02
+idx2 = 0x07
+idx2isReg = false (IMM)
+isBranch = false
+doJump = false
+exReg = 1
+exWriteReg = 0x07
+memReg = 0
+memWriteReg = 0
+
+
+*/
\ No newline at end of file

Fixed error with store instructions not wait for result of calculating instructions