Adds tests for RVC32 and RVC64
MODIFY
test/CMakeLists.txt
test/CMakeLists.txt
@@ -5,10 +5,12 @@ find_package(Qt5Test REQUIRED)
# Point to bundled tests within source directory
set(RISCV32_TEST_DIR ${CMAKE_CURRENT_SOURCE_DIR}/riscv-tests)
set(RISCV64_TEST_DIR ${CMAKE_CURRENT_SOURCE_DIR}/riscv-tests-64)
-set(RISCV_C_TEST_DIR ${CMAKE_CURRENT_SOURCE_DIR}/riscv-tests-c)
+set(RISCV32_C_TEST_DIR ${CMAKE_CURRENT_SOURCE_DIR}/riscv-tests-c)
+set(RISCV64_C_TEST_DIR ${CMAKE_CURRENT_SOURCE_DIR}/riscv-tests-c-64)
add_definitions(-DRISCV32_TEST_DIR="${RISCV32_TEST_DIR}")
add_definitions(-DRISCV64_TEST_DIR="${RISCV64_TEST_DIR}")
-add_definitions(-DRISCV_C_TEST_DIR="${RISCV_C_TEST_DIR}")
+add_definitions(-DRISCV32_C_TEST_DIR="${RISCV32_C_TEST_DIR}")
+add_definitions(-DRISCV64_C_TEST_DIR="${RISCV64_C_TEST_DIR}")
macro(create_qtest name)
add_executable(${name} ${name}.cpp)

ADD
test/riscv-tests-c-64/rvc.s
+.text
+main:
+ jal zero, test_2
+
+#data
+d1: .word 0x76543210
+d2: .word 0xfedcba98
+d3: .word 0x76543210
+d4: .word 0xfedcba98
+
+test_2:
+ addi a1,a1,1
+ li t2,1
+ li gp,2
+ bne a1,t2,fail
+ lui sp,0x1
+ addi sp,sp,564
+
+test_3:
+ c.addi4spn a0,1020
+ c.nop
+ lui t2,0x1
+ addi t2,t2,1584
+ li gp,3
+ bne a0,t2, fail
+
+test_4:
+# c.addi16sp sp, 496 #not implemented in Ripes assembler https://github.com/mortbopet/Ripes/blob/c229749d39f0f2964d53245fdfe729fcbef2a5ff/src/assembler/rv_c_ext.h#L183
+# c.nop
+ .word 0x0001617d
+ lui t2,0x1
+ addi t2,t2,1060
+ li gp,4
+ bne sp,t2,fail
+
+
+test_5:
+# c.addi16sp sp, -512 #not implemented in Ripes assembler https://github.com/mortbopet/Ripes/blob/c229749d39f0f2964d53245fdfe729fcbef2a5ff/src/assembler/rv_c_ext.h#L183
+# c.nop
+ .word 0x00017101
+ lui t2,0x1
+ addi t2,t2,548
+ li gp,5
+ bne sp,t2, fail
+ li a1,0
+ addi a1,a1, d1
+
+test_6:
+ c.lw a0, a1,4 #c.lw a0, 4(a1) better format ?
+ c.addi a0, 1
+ c.sw a0, a1, 4 #c.sw a0, 4(a1)
+ c.lw a2, a1 ,4 #c.lw a2, 4(a1)
+ lui t2,0xfedcc
+ addi t2,t2,-1383
+ li gp,6
+ bne a2,t2, fail
+
+test_7:
+ c.ld a0,a1,0 #c.ld a0, 0(a1)
+ c.addi a0, 1
+ c.sd a0,a1,0 #c.sd a0, 0(a1)
+ c.ld a2,a1,0 #c.ld a2, 0(a1)
+ lui t2,0xfff6e
+ addiw t2,t2,1493
+ slli t2,t2,0xc
+ addi t2,t2,-837
+ slli t2,t2,0xd
+ addi t2,t2, 1347
+ slli t2,t2,0xc
+ addi t2,t2,529
+ li gp,7
+ bne a2,t2,fail
+
+test_8:
+ ori a0,zero,1
+ c.addi a0,-16
+ c.nop
+ li t2,-15
+ li gp,8
+ bne a0,t2, fail
+
+test_9:
+ ori a5,zero,1
+ c.li a5,-16
+ c.nop
+ li t2,-16
+ li gp,9
+ bne a5,t2, fail
+
+test_10:
+ c.ld a0,a1,0 #c.ld a0, 0(a1)
+ c.addiw a0, -1
+ lui t2,0x76543
+ addiw t2,t2,528
+ li gp,10
+ bne a0,t2,fail
+
+test_11:
+ c.lui s0, -126976
+ c.srai s0,12
+ li t2,-31
+ li gp,11
+ bne s0,t2, fail
+
+test_12:
+ c.lui s0, -126976
+ c.srli s0,12
+ addiw t2,zero,1
+ slli t2,t2,0x34
+ addi t2,t2, -31
+ li gp,12
+ bne s0,t2, fail
+
+test_14:
+ c.li s0,-2
+ c.andi s0,-17
+ li t2,-18
+ li gp,14
+ bne s0,t2, fail
+
+test_15:
+ c.li s1,20
+ c.li a0,6
+ c.sub s1,a0
+ c.nop
+ li t2,14
+ li gp,15
+ bne s1,t2, fail
+
+test_16:
+ c.li s1,20
+ c.li a0,6
+ c.xor s1,a0
+ c.nop
+ li t2,18
+ li gp,16
+ bne s1,t2, fail
+
+test_17:
+ c.li s1,20
+ c.li a0,6
+ c.or s1,a0
+ c.nop
+ li t2,22
+ li gp,17
+ bne s1,t2, fail
+
+test_18:
+ c.li s1,20
+ c.li a0,6
+ c.and s1,a0
+ c.nop
+ li t2,4
+ li gp,18
+ bne s1,t2, fail
+
+test_19:
+ lui s1,0x80000
+ addiw s1,s1,-1
+ c.li a0, -1
+ c.subw s1, a0
+ lui t2,0x80000
+ li gp,19
+ bne s1,t2,fail
+
+test_20:
+ lui s1,0x80000
+ addiw s1,s1,-1
+ c.li a0, 1
+ c.addw s1, a0
+ lui t2,0x80000
+ li gp,20
+ bne s1,t2,fail
+
+test_21:
+ lui s0,0x1
+ addi s0,s0,564
+ c.slli s0,0x4
+ c.nop
+ lui t2,0x12
+ addi t2,t2,832
+ li gp,21
+ bne s0,t2, fail
+
+test_30:
+ c.li ra,0
+ c.j 4
+ c.j 4
+ c.j 4
+ c.j fail
+ c.nop
+ li t2,0
+ li gp,30
+ bne ra,t2, fail
+
+test_31:
+ c.li a0,0
+ c.beqz a0, 4
+ c.j 4
+ c.j 4
+ c.j fail
+ c.nop
+ li t2,0
+ li gp,31
+ bne zero,t2, fail
+
+test_32:
+ c.li a0,1
+ c.bnez a0,4
+ c.j 4
+ c.j 4
+ c.j fail
+ c.nop
+ li t2,0
+ li gp,32
+ bne zero,t2, fail
+
+test_33:
+ c.li a0,1
+ c.beqz a0,4
+ c.j 4
+ c.j fail
+ li t2,0
+ li gp,33
+ bne zero,t2,fail
+
+test_34:
+ c.li a0,0
+ c.bnez a0, 4
+ c.j 4
+ c.j fail
+ li t2,0
+ li gp,34
+ bne zero,t2,fail
+
+test_35:
+ auipc t0,0x0
+ addi t0,t0,14
+ c.li ra,0
+ c.jr t0
+ c.j 4
+ c.j 4
+ c.j fail
+ c.nop
+ nop
+ li t2,0
+ li gp,35
+ bne ra,t2,fail
+
+test_36:
+ auipc t0,0x0
+ addi t0,t0,14
+ c.li ra,0
+ c.jalr t0
+ c.j 4
+ c.j 4
+ c.j fail
+ c.nop
+ sub ra,ra,t0
+ li t2,-2
+ li gp,36
+ bne ra,t2,fail
+
+test_40:
+ li sp,0x0
+ addi sp,sp,d1
+ c.lwsp a0, 12
+ c.addi a0,1
+ c.swsp a0, 12
+ c.lwsp a2, 12
+ lui t2,0xfedcc
+ addi t2,t2,-1383
+ li gp,40
+ bne a2,t2,fail
+
+test_41:
+ c.ldsp a0,8 #c.ldsp a0, 8(sp)
+ c.addi a0, 1
+ c.sdsp a0, 8 #c.sdsp a0, 8(sp)
+ c.ldsp a2, 8 #c.ldsp a2, 8(sp)
+ lui t2,0xfff6e
+ addiw t2,t2,1493
+ slli t2,t2,0xc
+ addi t2,t2,-837
+ slli t2,t2,0xd
+ addi t2,t2,1347
+ slli t2,t2,0xc
+ addi t2,t2,529
+ li gp,41
+ bne a2,t2,fail
+
+test_42:
+ li a0,291
+ c.mv t0,a0
+ c.add t0,a0
+ li t2,582
+ li gp,42
+ bne t0,t2, fail
+
+
+ bne zero,gp, pass
+
+
+pass:
+ li a0, 42
+ li a7, 93
+ ecall
+
+fail:
+ li a0, 0
+ li a7, 93
+ ecall

MODIFY
test/tst_riscv.cpp
test/tst_riscv.cpp
#include "assembler/rv32i_assembler.h"
-#if !defined(RISCV32_TEST_DIR) || !defined(RISCV64_TEST_DIR) || !defined(RISCV_C_TEST_DIR)
+#if !defined(RISCV32_TEST_DIR) || !defined(RISCV64_TEST_DIR) || !defined(RISCV32_C_TEST_DIR) || \
+ !defined(RISCV64_C_TEST_DIR)
static_assert(false, "RISCV test directiories must be defined");
#endif
@@ -63,11 +64,13 @@ private slots:
void testRV64_5StagePipeline() { runTests(ProcessorID::RV64_5S, {"M"}, {RISCV64_TEST_DIR}); }
void testRV64_5StagePipelineNOFW() { runTests(ProcessorID::RV64_5S_NO_FW, {"M"}, {RISCV64_TEST_DIR}); }
void testRV64_6SDual() { runTests(ProcessorID::RV64_6S_DUAL, {"M"}, {RISCV64_TEST_DIR}); }
+ void testRV64C_SingleCycle() { runTests(ProcessorID::RV64_SS, {"M", "C"}, {RISCV64_TEST_DIR, RISCV64_C_TEST_DIR}); }
void testRV32_SingleCycle() { runTests(ProcessorID::RV32_SS, {"M"}, {RISCV32_TEST_DIR}); }
void testRV32_5StagePipeline() { runTests(ProcessorID::RV32_5S, {"M"}, {RISCV32_TEST_DIR}); }
void testRV32_5StagePipelineNOFW() { runTests(ProcessorID::RV32_5S_NO_FW, {"M"}, {RISCV32_TEST_DIR}); }
void testRV32_6SDual() { runTests(ProcessorID::RV32_6S_DUAL, {"M"}, {RISCV32_TEST_DIR}); }
+ void testRV32C_SingleCycle() { runTests(ProcessorID::RV32_SS, {"M", "C"}, {RISCV32_TEST_DIR, RISCV32_C_TEST_DIR}); }
};
bool tst_RISCV::skipTest(const QString& test) {

Adds tests for RVC32 and RVC64  (#155)