Specify address spaces in RV32SS processor
MODIFY
external/VSRTL
external/VSRTL
-Subproject commit 616ba00516d563dd4f152071180467a729fecd70
+Subproject commit a17828564504abbd7d7623734443ac757b38b4d8

MODIFY
src/processors/ripesprocessor.h
src/processors/ripesprocessor.h
#include <QString>
+#include <map>
#include "VSRTL/core/vsrtl_design.h"
namespace Ripes {
@@ -51,6 +52,18 @@ public:
*/
virtual StageInfo stageInfo(unsigned int stageIndex) const = 0;
+ /**
+ * @brief getMemoryPtr
+ * @return pointer to the address space utilized by the implementing processor
+ */
+ virtual std::unordered_map<uint32_t, uint8_t>* getMemoryPtr() = 0;
+
+ /**
+ * @brief setEntryPoint
+ * Sets the program counter of the processor to @param address
+ */
+ virtual void setProgramCounter(uint32_t address) = 0;
+
void reset() override {
vsrtl::core::Design::reset();
m_instructionsRetired = 0;

MODIFY
src/processors/ss/registerfile.h
src/processors/ss/registerfile.h
@@ -14,11 +14,6 @@ class RegisterFile : public Component {
public:
SetGraphicsType(ClockedComponent);
RegisterFile(std::string name, SimComponent* parent) : Component(name, parent) {
- // All memory components must point to the same memory
- _wr_mem->setMemory(&m_memory);
- _rd1_mem->setMemory(&m_memory);
- _rd2_mem->setMemory(&m_memory);
-
// Writes
// Disable writes to register 0
@@ -51,7 +46,7 @@ public:
OUTPUTPORT(r1_out, RV_REG_WIDTH);
OUTPUTPORT(r2_out, RV_REG_WIDTH);
- VSRTL_VT_U getRegister(unsigned i) { return readMem<false>(&m_memory, i); }
+ VSRTL_VT_U getRegister(unsigned i) { return m_memory->readMem<false>(i); }
std::vector<VSRTL_VT_U> getRegisters() {
std::vector<VSRTL_VT_U> regs;
@@ -60,8 +55,16 @@ public:
return regs;
}
+ void setMemory(SparseArray* mem) {
+ m_memory = mem;
+ // All memory components must point to the same memory
+ _wr_mem->setMemory(m_memory);
+ _rd1_mem->setMemory(m_memory);
+ _rd2_mem->setMemory(m_memory);
+ }
+
private:
- std::unordered_map<VSRTL_VT_U, uint8_t> m_memory;
+ SparseArray* m_memory = nullptr;
};
} // namespace RISCV

MODIFY
src/processors/ss/riscv_ss.h
src/processors/ss/riscv_ss.h
@@ -39,6 +39,7 @@ public:
// -----------------------------------------------------------------------
// Instruction memory
pc_reg->out >> instr_mem->addr;
+ instr_mem->setMemory(m_memory);
// -----------------------------------------------------------------------
// Decode
@@ -66,6 +67,8 @@ public:
pc_4->out >> reg_wr_src->get(RegWrSrc::PC4);
control->reg_wr_src_ctrl >> reg_wr_src->select;
+ registerFile->setMemory(m_regMem);
+
// -----------------------------------------------------------------------
// Branch
control->comp_ctrl >> branch->comp_op;
@@ -100,6 +103,7 @@ public:
control->mem_do_write_ctrl >> data_mem->wr_en;
registerFile->r2_out >> data_mem->data_in;
control->mem_ctrl >> data_mem->op;
+ data_mem->mem->setMemory(m_memory);
}
// Design subcomponents
@@ -128,12 +132,21 @@ public:
SUBCOMPONENT(br_and, TYPE(And<1, 2>));
SUBCOMPONENT(controlflow_or, TYPE(Or<1, 2>));
+ // Address spaces
+ ADDRESSSPACE(m_memory);
+ ADDRESSSPACE(m_regMem);
+
// Ripes interface compliance
virtual Ripes::SupportedISA implementsISA() const override { return Ripes::SupportedISA::RISCV; }
unsigned int stageCount() const override { return 1; }
unsigned int breakpointBreaksStage() const override { return 0; }
unsigned int pcForStage(unsigned int) const override { return pc_reg->out.uValue(); }
Ripes::StageInfo stageInfo(unsigned int stageIndex) const override { return {}; }
+ void setProgramCounter(uint32_t address) override {
+ pc_reg->forceValue(0, address);
+ propagateDesign();
+ }
+ std::unordered_map<uint32_t, uint8_t>* getMemoryPtr() override { return &m_memory->data; }
};
} // namespace RISCV
} // namespace vsrtl

MODIFY
test/tst_riscv.cpp
test/tst_riscv.cpp
@@ -101,7 +101,7 @@ void tst_RISCV::loadBinaryToSimulator(const QString& binFile) {
std::vector<unsigned char> program(programByteArray.begin(), programByteArray.end());
// Load program into simulator
- m_design->instr_mem->addInitializationMemory(0x0, program.data(), program.size());
+ m_design->m_memory->addInitializationMemory(0x0, program.data(), program.size());
}
QString tst_RISCV::executeSimulator() {

Specify address spaces in RV32SS processor