Processors now expose their ISA statically
Makes initializing processors a bit simpler
MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
@@ -29,7 +29,7 @@ ProcessorHandler::ProcessorHandler() {
// Some sanity checking
m_currentID = m_currentID >= ProcessorID::NUM_PROCESSORS ? ProcessorID::RV32_5S : m_currentID;
}
- _selectProcessor(m_currentID, ProcessorRegistry::getDescription(m_currentID).isa->supportedExtensions(),
+ _selectProcessor(m_currentID, ProcessorRegistry::getDescription(m_currentID).isa()->supportedExtensions(),
ProcessorRegistry::getDescription(m_currentID).defaultRegisterVals);
// The m_procStateChangeTimer limits maximum frequency of which the procStateChangedNonRun is emitted.
@@ -245,7 +245,7 @@ void ProcessorHandler::_selectProcessor(const ProcessorID& id, const QStringList
// Keep current program if the ISA between the two processors are identical
const bool keepProgram = m_currentProcessor && (m_currentProcessor->implementsISA()->eq(
- ProcessorRegistry::getDescription(id).isa, extensions));
+ ProcessorRegistry::getDescription(id).isa(), extensions));
// Processor initializations
m_currentProcessor = ProcessorRegistry::constructProcessor(m_currentID, extensions);

MODIFY
src/processorregistry.h
src/processorregistry.h
@@ -55,157 +55,148 @@ struct Layout {
bool operator==(const Layout& rhs) const { return this->name == rhs.name; }
};
-struct ProcessorDescription {
+class ProcInfoBase {
+public:
+ ProcInfoBase(ProcessorID _id, const QString& _name, const QString& _desc, const std::vector<Layout>& _layouts,
+ const RegisterInitialization& _defaultRegVals = {})
+ : id(_id), name(_name), description(_desc), defaultRegisterVals(_defaultRegVals), layouts(_layouts) {}
ProcessorID id;
- RegisterInitialization defaultRegisterVals;
- const ISAInfoBase* isa;
QString name;
QString description;
+ RegisterInitialization defaultRegisterVals;
std::vector<Layout> layouts;
+ virtual const ISAInfoBase* isa() const = 0;
+ virtual std::unique_ptr<RipesProcessor> construct(const QStringList& extensions) = 0;
+};
+
+template <typename T>
+class ProcInfo : public ProcInfoBase {
+public:
+ using ProcInfoBase::ProcInfoBase;
+ std::unique_ptr<RipesProcessor> construct(const QStringList& extensions) { return std::make_unique<T>(extensions); }
+ // At this point we force the processor type T to implement a static function identifying its supported ISA.
+ const ISAInfoBase* isa() const { return T::supportsISA(); }
};
class ProcessorRegistry {
public:
- using ProcessorMap = std::map<ProcessorID, ProcessorDescription>;
+ using ProcessorMap = std::map<ProcessorID, std::unique_ptr<ProcInfoBase>>;
static const ProcessorMap& getAvailableProcessors() { return instance().m_descriptions; }
- static const ProcessorDescription& getDescription(ProcessorID id) {
+ static const ProcInfoBase& getDescription(ProcessorID id) {
auto desc = instance().m_descriptions.find(id);
if (desc == instance().m_descriptions.end()) {
- return instance().m_descriptions.begin()->second;
+ return *instance().m_descriptions.begin()->second;
}
- return desc->second;
+ return *desc->second;
}
static std::unique_ptr<RipesProcessor> constructProcessor(ProcessorID id, const QStringList& extensions) {
- switch (id) {
- case ProcessorID::RV32_5S_NO_FW_HZ:
- return std::make_unique<vsrtl::core::RV5S_NO_FW_HZ<uint32_t>>(extensions);
- case ProcessorID::RV32_5S:
- return std::make_unique<vsrtl::core::RV5S<uint32_t>>(extensions);
- case ProcessorID::RV32_6S_DUAL:
- return std::make_unique<vsrtl::core::RV6S_DUAL<uint32_t>>(extensions);
- case ProcessorID::RV32_SS:
- return std::make_unique<vsrtl::core::RVSS<uint32_t>>(extensions);
- case ProcessorID::RV32_5S_NO_HZ:
- return std::make_unique<vsrtl::core::RV5S_NO_HZ<uint32_t>>(extensions);
- case ProcessorID::RV32_5S_NO_FW:
- return std::make_unique<vsrtl::core::RV5S_NO_FW<uint32_t>>(extensions);
- case ProcessorID::RV64_5S_NO_FW_HZ:
- return std::make_unique<vsrtl::core::RV5S_NO_FW_HZ<uint64_t>>(extensions);
- case ProcessorID::RV64_5S:
- return std::make_unique<vsrtl::core::RV5S<uint64_t>>(extensions);
- case ProcessorID::RV64_6S_DUAL:
- return std::make_unique<vsrtl::core::RV6S_DUAL<uint64_t>>(extensions);
- case ProcessorID::RV64_SS:
- return std::make_unique<vsrtl::core::RVSS<uint64_t>>(extensions);
- case ProcessorID::RV64_5S_NO_HZ:
- return std::make_unique<vsrtl::core::RV5S_NO_HZ<uint64_t>>(extensions);
- case ProcessorID::RV64_5S_NO_FW:
- return std::make_unique<vsrtl::core::RV5S_NO_FW<uint64_t>>(extensions);
- case ProcessorID::NUM_PROCESSORS:
- default:
- Q_UNREACHABLE();
- }
+ auto& _this = instance();
+ auto it = _this.m_descriptions.find(id);
+ Q_ASSERT(it != _this.m_descriptions.end());
+ return it->second->construct(extensions);
}
private:
+ template <typename T>
+ void addProcessor(const ProcInfo<T>& pinfo) {
+ Q_ASSERT(m_descriptions.count(pinfo.id) == 0);
+ m_descriptions[pinfo.id] = std::make_unique<ProcInfo<T>>(pinfo);
+ }
+
ProcessorRegistry() {
// Initialize processors
+ std::vector<Layout> layouts;
+ RegisterInitialization defRegVals;
- for (int xlen : {32, 64}) {
// RISC-V single cycle
- ProcessorDescription desc;
- desc.id = xlen == 32 ? ProcessorID::RV32_SS : ProcessorID::RV64_SS;
- desc.isa = xlen == 32 ? vsrtl::core::RVSS<uint32_t>::ISA() : vsrtl::core::RVSS<uint64_t>::ISA();
- desc.name = "Single-cycle processor";
- desc.description = "A single cycle processor";
- desc.layouts = {{"Standard", ":/layouts/RISC-V/rvss/rv_ss_standard_layout.json", {QPointF{0.5, 0}}},
+ layouts = {{"Standard", ":/layouts/RISC-V/rvss/rv_ss_standard_layout.json", {QPointF{0.5, 0}}},
{"Extended", ":/layouts/RISC-V/rvss/rv_ss_extended_layout.json", {QPointF{0.5, 0}}}};
- desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
- m_descriptions[desc.id] = desc;
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo<vsrtl::core::RVSS<uint32_t>>(ProcessorID::RV32_SS, "Single-cycle processor",
+ "A single cycle processor", layouts, defRegVals));
+ addProcessor(ProcInfo<vsrtl::core::RVSS<uint64_t>>(ProcessorID::RV64_SS, "Single-cycle processor",
+ "A single cycle processor", layouts, defRegVals));
// RISC-V 5-stage without forwarding or hazard detection
- desc = ProcessorDescription();
- desc.id = xlen == 32 ? ProcessorID::RV32_5S_NO_FW_HZ : ProcessorID::RV64_5S_NO_FW_HZ;
- desc.isa =
- xlen == 32 ? vsrtl::core::RV5S_NO_FW_HZ<uint32_t>::ISA() : vsrtl::core::RV5S_NO_FW_HZ<uint64_t>::ISA();
- desc.name = "5-stage processor w/o forwarding or hazard detection";
- desc.description = "A 5-stage in-order processor with no forwarding or hazard detection/elimination.";
- desc.layouts = {
+ layouts = {
{"Standard",
":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.54, 0}, QPointF{0.73, 0}, QPointF{0.88, 0}}},
{"Extended",
":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json",
{QPointF{0.08, 0.0}, QPointF{0.31, 0.0}, QPointF{0.56, 0.0}, QPointF{0.76, 0.0}, QPointF{0.9, 0.0}}}};
-
- desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
- m_descriptions[desc.id] = desc;
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW_HZ<uint32_t>>(
+ ProcessorID::RV32_5S_NO_FW_HZ, "5-stage processor w/o forwarding or hazard detection",
+ "A 5-stage in-order processor with no forwarding or hazard detection/elimination.", layouts, defRegVals));
+ addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW_HZ<uint64_t>>(
+ ProcessorID::RV64_5S_NO_FW_HZ, "5-stage processor w/o forwarding or hazard detection",
+ "A 5-stage in-order processor with no forwarding or hazard detection/elimination.", layouts, defRegVals));
// RISC-V 5-stage without hazard detection
- desc = ProcessorDescription();
- desc.id = xlen == 32 ? ProcessorID::RV32_5S_NO_HZ : ProcessorID::RV64_5S_NO_HZ;
- desc.isa = xlen == 32 ? vsrtl::core::RV5S_NO_HZ<uint32_t>::ISA() : vsrtl::core::RV5S_NO_HZ<uint64_t>::ISA();
- desc.name = "5-stage processor w/o hazard detection";
- desc.description = "A 5-stage in-order processor with forwarding but no hazard detection/elimination.";
- desc.layouts = {
- {"Standard",
+ layouts = {{"Standard",
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0}, QPointF{0.75, 0}, QPointF{0.88, 0}}},
{"Extended",
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json",
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.53, 0}, QPointF{0.78, 0}, QPointF{0.9, 0}}}};
- desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
- m_descriptions[desc.id] = desc;
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo<vsrtl::core::RV5S_NO_HZ<uint32_t>>(
+ ProcessorID::RV32_5S_NO_HZ, "5-stage processor w/o hazard detection",
+ "A 5-stage in-order processor with forwarding but no hazard detection/elimination.", layouts, defRegVals));
+ addProcessor(ProcInfo<vsrtl::core::RV5S_NO_HZ<uint64_t>>(
+ ProcessorID::RV64_5S_NO_HZ, "5-stage processor w/o hazard detection",
+ "A 5-stage in-order processor with forwarding but no hazard detection/elimination.", layouts, defRegVals));
// RISC-V 5-stage without forwarding unit
- desc = ProcessorDescription();
- desc.id = xlen == 32 ? ProcessorID::RV32_5S_NO_FW : ProcessorID::RV64_5S_NO_FW;
- desc.isa = xlen == 32 ? vsrtl::core::RV5S_NO_FW<uint32_t>::ISA() : vsrtl::core::RV5S_NO_FW<uint64_t>::ISA();
- desc.name = "5-Stage processor w/o forwarding unit";
- desc.description = "A 5-stage in-order processor with hazard detection/elimination but no forwarding unit.";
- desc.layouts = {
- {"Standard",
+ layouts = {{"Standard",
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0}, QPointF{0.75, 0}, QPointF{0.88, 0}}},
{"Extended",
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_extended_layout.json",
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.53, 0}, QPointF{0.78, 0}, QPointF{0.9, 0}}}};
- desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
- m_descriptions[desc.id] = desc;
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW<uint32_t>>(
+ ProcessorID::RV32_5S_NO_FW, "5-Stage processor w/o forwarding unit",
+ "A 5-stage in-order processor with hazard detection/elimination but no forwarding unit.", layouts,
+ defRegVals));
+ addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW<uint64_t>>(
+ ProcessorID::RV64_5S_NO_FW, "5-Stage processor w/o forwarding unit",
+ "A 5-stage in-order processor with hazard detection/elimination but no forwarding unit.", layouts,
+ defRegVals));
// RISC-V 5-stage
- desc = ProcessorDescription();
- desc.id = xlen == 32 ? ProcessorID::RV32_5S : ProcessorID::RV64_5S;
- desc.isa = xlen == 32 ? vsrtl::core::RV5S<uint32_t>::ISA() : vsrtl::core::RV5S<uint64_t>::ISA();
- desc.name = "5-stage processor";
- desc.description = "A 5-stage in-order processor with hazard detection/elimination and forwarding.";
- desc.layouts = {
- {"Standard",
+ layouts = {{"Standard",
":/layouts/RISC-V/rv5s/rv5s_standard_layout.json",
{QPointF{0.08, 0}, QPointF{0.29, 0}, QPointF{0.55, 0}, QPointF{0.75, 0}, QPointF{0.87, 0}}},
{"Extended",
":/layouts/RISC-V/rv5s/rv5s_extended_layout.json",
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.54, 0}, QPointF{0.78, 0}, QPointF{0.9, 0}}}};
- desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
- m_descriptions[desc.id] = desc;
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo<vsrtl::core::RV5S<uint32_t>>(
+ ProcessorID::RV32_5S, "5-stage processor",
+ "A 5-stage in-order processor with hazard detection/elimination and forwarding.", layouts, defRegVals));
+ addProcessor(ProcInfo<vsrtl::core::RV5S<uint64_t>>(
+ ProcessorID::RV64_5S, "5-stage processor",
+ "A 5-stage in-order processor with hazard detection/elimination and forwarding.", layouts, defRegVals));
// RISC-V 6-stage dual issue
- desc = ProcessorDescription();
- desc.id = xlen == 32 ? ProcessorID::RV32_6S_DUAL : ProcessorID::RV64_6S_DUAL;
- desc.isa = xlen == 32 ? vsrtl::core::RV6S_DUAL<uint32_t>::ISA() : vsrtl::core::RV6S_DUAL<uint64_t>::ISA();
- desc.name = "6-stage dual-issue processor";
- desc.description =
- "A 6-stage dual-issue in-order processor. Each way may execute arithmetic instructions, whereas way 1 "
- "is "
- "reserved for controlflow and ecall instructions, and way 2 for memory accessing instructions.";
- desc.layouts = {{"Extended",
+ layouts = {{"Extended",
":/layouts/RISC-V/rv6s_dual/rv6s_dual_extended_layout.json",
{{QPointF{0.06, 0}, QPointF{0.06, 1}, QPointF{0.22, 0}, QPointF{0.22, 1}, QPointF{0.35, 0},
QPointF{0.35, 1}, QPointF{0.54, 0}, QPointF{0.54, 1}, QPointF{0.78, 0}, QPointF{0.78, 1},
QPointF{0.87, 0}, QPointF{0.87, 1}}}}};
- desc.defaultRegisterVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
- m_descriptions[desc.id] = desc;
- }
+ defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
+ addProcessor(ProcInfo<vsrtl::core::RV6S_DUAL<uint32_t>>(
+ ProcessorID::RV32_6S_DUAL, "6-stage dual-issue processor",
+ "A 6-stage dual-issue in-order processor. Each way may execute arithmetic instructions, whereas way 1 "
+ "is reserved for controlflow and ecall instructions, and way 2 for memory accessing instructions.",
+ layouts, defRegVals));
+ addProcessor(ProcInfo<vsrtl::core::RV6S_DUAL<uint64_t>>(
+ ProcessorID::RV64_6S_DUAL, "6-stage dual-issue processor",
+ "A 6-stage dual-issue in-order processor. Each way may execute arithmetic instructions, whereas way 1 "
+ "is reserved for controlflow and ecall instructions, and way 2 for memory accessing instructions.",
+ layouts, defRegVals));
}
static ProcessorRegistry& instance() {

MODIFY
src/processors/RISC-V/rv5s/rv5s.h
src/processors/RISC-V/rv5s/rv5s.h
@@ -482,12 +482,10 @@ public:
m_syscallExitCycle = -1;
}
- static const ISAInfoBase* ISA() {
+ static const ISAInfoBase* supportsISA() {
static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}
-
- const ISAInfoBase* supportsISA() const override { return ISA(); }
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); }
const std::set<RegisterFileType> registerFiles() const override {

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
@@ -458,12 +458,10 @@ public:
m_syscallExitCycle = -1;
}
- static const ISAInfoBase* ISA() {
+ static const ISAInfoBase* supportsISA() {
static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}
-
- const ISAInfoBase* supportsISA() const override { return ISA(); }
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); }
const std::set<RegisterFileType> registerFiles() const override {

MODIFY
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz.h
@@ -408,12 +408,10 @@ public:
m_syscallExitCycle = -1;
}
- static const ISAInfoBase* ISA() {
+ static const ISAInfoBase* supportsISA() {
static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}
-
- const ISAInfoBase* supportsISA() const override { return ISA(); };
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); };
const std::set<RegisterFileType> registerFiles() const override {

MODIFY
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz.h
@@ -441,12 +441,10 @@ public:
m_syscallExitCycle = -1;
}
- static const ISAInfoBase* ISA() {
+ static const ISAInfoBase* supportsISA() {
static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}
-
- const ISAInfoBase* supportsISA() const override { return ISA(); };
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); };
const std::set<RegisterFileType> registerFiles() const override {

MODIFY
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
src/processors/RISC-V/rv6s_dual/rv6s_dual.h
@@ -799,12 +799,10 @@ public:
m_syscallExitCycle = -1;
}
- static const ISAInfoBase* ISA() {
+ static const ISAInfoBase* supportsISA() {
static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}
-
- const ISAInfoBase* supportsISA() const override { return ISA(); };
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); };
const std::set<RegisterFileType> registerFiles() const override {

MODIFY
src/processors/RISC-V/rvss/rvss.h
src/processors/RISC-V/rvss/rvss.h
@@ -214,12 +214,10 @@ public:
m_finished = false;
}
- static const ISAInfoBase* ISA() {
+ static const ISAInfoBase* supportsISA() {
static auto s_isa = ISAInfo<XLenToRVISA<XLEN>()>(QStringList{"M"});
return &s_isa;
}
-
- const ISAInfoBase* supportsISA() const override { return ISA(); }
const ISAInfoBase* implementsISA() const override { return m_enabledISA.get(); }
const std::set<RegisterFileType> registerFiles() const override {
std::set<RegisterFileType> rfs;

MODIFY
src/processors/interface/ripesprocessor.h
src/processors/interface/ripesprocessor.h
@@ -80,8 +80,10 @@ public:
/**
* @brief supportsISA
* @return ISA alongside all of the supported extensions which this processor implements.
+ * The type inheriting RipesProcessor must implement a static function which provides information about the
+ * supported ISA of the processor.
*/
- virtual const ISAInfoBase* supportsISA() const = 0;
+ // static const ISAInfoBase* T::supportsISA();
/**
* @brief implementsISA

MODIFY
src/processorselectiondialog.cpp
src/processorselectiondialog.cpp
@@ -33,25 +33,25 @@ ProcessorSelectionDialog::ProcessorSelectionDialog(QWidget* parent)
QTreeWidgetItem* selectedItem = nullptr;
for (auto& desc : ProcessorRegistry::getAvailableProcessors()) {
- QTreeWidgetItem* processorItem = new QTreeWidgetItem({desc.second.name});
- processorItem->setData(ProcessorColumn, Qt::UserRole, QVariant::fromValue(desc.second.id));
- if (desc.second.id == ProcessorHandler::getID()) {
+ QTreeWidgetItem* processorItem = new QTreeWidgetItem({desc.second->name});
+ processorItem->setData(ProcessorColumn, Qt::UserRole, QVariant::fromValue(desc.second->id));
+ if (desc.second->id == ProcessorHandler::getID()) {
// Highlight if currently selected processor
auto font = processorItem->font(ProcessorColumn);
font.setBold(true);
processorItem->setFont(ProcessorColumn, font);
selectedItem = processorItem;
}
- const QString& isaFamily = ISAFamilyNames.at(desc.second.isa->isaID());
+ const QString& isaFamily = ISAFamilyNames.at(desc.second->isa()->isaID());
QTreeWidgetItem* familyItem = isaFamilyItems.at(isaFamily);
auto& regWidthItemsForISA = isaFamilyRegWidthItems.at(familyItem);
- auto isaRegWidthItem = regWidthItemsForISA.find(desc.second.isa->bits());
+ auto isaRegWidthItem = regWidthItemsForISA.find(desc.second->isa()->bits());
if (isaRegWidthItem == regWidthItemsForISA.end()) {
// Create reg width item
- auto* widthItem = new QTreeWidgetItem({QString::number(desc.second.isa->bits()) + "-bit"});
+ auto* widthItem = new QTreeWidgetItem({QString::number(desc.second->isa()->bits()) + "-bit"});
widthItem->setFlags(widthItem->flags() & ~(Qt::ItemIsSelectable));
- regWidthItemsForISA[desc.second.isa->bits()] = widthItem;
- isaRegWidthItem = regWidthItemsForISA.find(desc.second.isa->bits());
+ regWidthItemsForISA[desc.second->isa()->bits()] = widthItem;
+ isaRegWidthItem = regWidthItemsForISA.find(desc.second->isa()->bits());
familyItem->insertChild(familyItem->childCount(), widthItem);
}
isaRegWidthItem->second->insertChild(isaRegWidthItem->second->childCount(), processorItem);
@@ -69,7 +69,7 @@ ProcessorSelectionDialog::ProcessorSelectionDialog(QWidget* parent)
// Initialize extensions for processors; default to all available extensions
for (const auto& desc : ProcessorRegistry::getAvailableProcessors()) {
- m_selectedExtensionsForID[desc.second.id] = desc.second.isa->supportedExtensions();
+ m_selectedExtensionsForID[desc.second->id] = desc.second->isa()->supportedExtensions();
}
m_selectedExtensionsForID[ProcessorHandler::getID()] = ProcessorHandler::currentISA()->enabledExtensions();
@@ -122,13 +122,13 @@ void ProcessorSelectionDialog::selectionChanged(QTreeWidgetItem* current, QTreeW
// Update information widgets with the current processor info
m_selectedID = id;
- m_ui->name->setText(desc.name);
- m_ui->ISA->setText(desc.isa->name());
- m_ui->description->setPlainText(desc.description);
+ m_ui->name->setText(desc->name);
+ m_ui->ISA->setText(desc->isa()->name());
+ m_ui->description->setPlainText(desc->description);
m_ui->regInitWidget->processorSelectionChanged(id);
m_ui->layout->clear();
- for (const auto& layout : desc.layouts) {
+ for (const auto& layout : desc->layouts) {
m_ui->layout->addItem(layout.name);
}
@@ -140,10 +140,10 @@ void ProcessorSelectionDialog::selectionChanged(QTreeWidgetItem* current, QTreeW
delete item;
}
- for (const auto& ext : desc.isa->supportedExtensions()) {
+ for (const auto& ext : desc->isa()->supportedExtensions()) {
auto chkbox = new QCheckBox(ext);
m_ui->extensions->addWidget(chkbox);
- if (m_selectedExtensionsForID[desc.id].contains(ext)) {
+ if (m_selectedExtensionsForID[desc->id].contains(ext)) {
chkbox->setChecked(true);
}
connect(chkbox, &QCheckBox::toggled, this, [=](bool toggled) {
@@ -158,7 +158,7 @@ void ProcessorSelectionDialog::selectionChanged(QTreeWidgetItem* current, QTreeW
const Layout* ProcessorSelectionDialog::getSelectedLayout() const {
const auto& desc = ProcessorRegistry::getAvailableProcessors().at(m_selectedID);
- for (const auto& layout : desc.layouts) {
+ for (const auto& layout : desc->layouts) {
if (layout.name == m_ui->layout->currentText()) {
return &layout;
}

MODIFY
src/registerinitializationwidget.cpp
src/registerinitializationwidget.cpp
@@ -22,7 +22,7 @@ void RegisterSelectionComboBox::showPopup() {
if (count())
clear();
- const auto& isa = ProcessorRegistry::getAvailableProcessors().at(m_parent->m_currentID).isa;
+ const auto& isa = ProcessorRegistry::getAvailableProcessors().at(m_parent->m_currentID)->isa();
const auto& initializations = m_parent->m_initializations.at(m_parent->m_currentID);
std::set<unsigned> regOptions;
@@ -58,8 +58,8 @@ RegisterInitializationWidget::RegisterInitializationWidget(QWidget* parent)
for (const auto& desc : ProcessorRegistry::getAvailableProcessors()) {
// Set to initial value if this is the first time the dialog is loaded. Else, keep whatever changes has been
// stored in the static variable, made in previous invokations of the dialog.
- if (!m_initializations.count(desc.second.id)) {
- m_initializations[desc.second.id] = desc.second.defaultRegisterVals;
+ if (!m_initializations.count(desc.second->id)) {
+ m_initializations[desc.second->id] = desc.second->defaultRegisterVals;
}
}
}
@@ -91,7 +91,7 @@ void RegisterInitializationWidget::updateAddButtonState() {
}
int RegisterInitializationWidget::getNonInitializedRegIdx() {
- const auto& currentISA = ProcessorRegistry::getAvailableProcessors().at(m_currentID).isa;
+ const auto& currentISA = ProcessorRegistry::getAvailableProcessors().at(m_currentID)->isa();
const auto& currentInitForProc = m_initializations.at(m_currentID);
unsigned id = 0;
while (currentInitForProc.count(id) || currentISA->regIsReadOnly(id)) {
@@ -109,7 +109,7 @@ RegisterInitializationWidget::RegInitWidgets* RegisterInitializationWidget::addR
}
const auto& regLayout = m_ui->regInitLayout;
- const auto& isa = ProcessorRegistry::getAvailableProcessors().at(m_currentID).isa;
+ const auto& isa = ProcessorRegistry::getAvailableProcessors().at(m_currentID)->isa();
auto& w = m_currentRegInitWidgets.emplace_back(std::make_unique<RegInitWidgets>());
auto* w_ptr = w.get();

Processors now expose their ISA statically

Makes initializing processors a bit simpler