Remove duplicate functions from VSRTL binutils
MODIFY
src/assembler/expreval.cpp
src/assembler/expreval.cpp
@@ -231,7 +231,7 @@ int64_t evaluate(const std::shared_ptr<Expr>& expr, const SymbolMap* variables)
FiExpr;
IfExpr(Or, v) { return evaluate(v->lhs, variables) | evaluate(v->rhs, variables); }
FiExpr;
- IfExpr(SignExtend, v) { return signextend<int>(evaluate(v->lhs, variables), evaluate(v->rhs, variables)); }
+ IfExpr(SignExtend, v) { return vsrtl::signextend<int>(evaluate(v->lhs, variables), evaluate(v->rhs, variables)); }
FiExpr;
IfExpr(Nothing, v) {
Q_UNUSED(v);

MODIFY
src/assembler/instruction.h
src/assembler/instruction.h
@@ -22,7 +22,7 @@ struct BitRange {
}
constexpr unsigned width() const { return stop - start + 1; }
const unsigned start, stop, N;
- const uint32_t mask = generateBitmask(width());
+ const uint32_t mask = vsrtl::generateBitmask(width());
uint32_t apply(uint32_t value) const { return (value & mask) << start; }
uint32_t decode(uint32_t instruction) const { return (instruction >> start) & mask; };
@@ -253,7 +253,7 @@ struct Imm : public Field {
part.decode(reconstructed, instruction);
}
if (repr == Repr::Signed) {
- line.push_back(QString::number(static_cast<int32_t>(signextend<int32_t>(reconstructed, width))));
+ line.push_back(QString::number(vsrtl::signextend(reconstructed, width)));
} else if (repr == Repr::Unsigned) {
line.push_back(QString::number(reconstructed));
} else {
@@ -261,7 +261,7 @@ struct Imm : public Field {
}
if (symbolType != SymbolType::None) {
- const int value = signextend<int32_t>(reconstructed, width);
+ const int value = vsrtl::signextend(reconstructed, width);
const uint32_t symbolAddress = value + (symbolType == SymbolType::Absolute ? 0 : address);
if (symbolMap.count(symbolAddress)) {
line.push_back("<" + symbolMap.at(symbolAddress).v + ">");

MODIFY
src/assembler/rv32i_assembler.cpp
src/assembler/rv32i_assembler.cpp
@@ -226,7 +226,7 @@ void RV32I_Assembler::enableExtI(const ISAInfoBase* isa, InstrVec& instructions,
// go into the terminal case when @p val is either representable as uint32 or int32.
if (isUInt<32>(val) || isInt<32>(val)) {
int64_t Hi20 = ((val + 0x800) >> 12) & 0xFFFFF;
- int64_t Lo12 = signextend<int64_t, 12>(val);
+ int64_t Lo12 = vsrtl::signextend<12>(val);
if (Hi20) {
res.push_back(LineTokens() << Token("lui") << line.tokens.at(1) << QString::number(Hi20));
liveDstReg = true;
@@ -245,10 +245,10 @@ void RV32I_Assembler::enableExtI(const ISAInfoBase* isa, InstrVec& instructions,
line.sourceLine, QString("Invalid immediate '%1'; can't emit >32-bit imm for non-RV64 target")
.arg(line.tokens.at(2)))};
}
- int64_t Lo12 = signextend<int64_t, 12>(val);
+ int64_t Lo12 = vsrtl::signextend<12>(val);
int64_t Hi52 = ((uint64_t)val + 0x800ull) >> 12;
int ShiftAmount = 12 + firstSetBitIdx(Hi52);
- Hi52 = signextend<int64_t>(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
+ Hi52 = vsrtl::signextend<int64_t>(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
genInstrSeq(Hi52, isRV64);
res.push_back(LineTokens() << Token("slli") << line.tokens.at(1) << line.tokens.at(1)
<< QString::number(ShiftAmount));

DELETE
src/binutils.cpp
-#include "binutils.h"
-
-namespace Ripes {
-
-uint32_t accBVec(const std::vector<bool>& v) {
- uint32_t r = 0;
- for (uint32_t i = 0; i < v.size(); i++) {
- r |= v.at(i) << i;
- }
- return r;
-}
-
-void buildVec(std::vector<bool>& v, uint32_t n) {
- for (auto&& i : v) {
- i = n & 0b1;
- n >>= 1;
- }
-}
-} // namespace Ripes

MODIFY
src/binutils.h
src/binutils.h
#include <vector>
#include "limits.h"
-namespace Ripes {
-
-// Sign extension of arbitrary bitfield size.
-// Courtesy of http://graphics.stanford.edu/~seander/bithacks.html#FixedSignExtend
-template <typename T, unsigned B>
-inline T signextend(const T x) {
- struct {
- T x : B;
- } s;
- return s.x = x;
-}
+#include "VSRTL/interface/vsrtl_binutils.h"
-// Runtime signextension
-template <typename T>
-inline T signextend(const T x, unsigned B) {
- int const m = CHAR_BIT * sizeof(T) - B;
- return (x << m) >> m;
-}
+namespace Ripes {
/// Checks if an integer fits into the given bit width.
/// from LLVM MathExtras.h
@@ -85,38 +70,10 @@ constexpr inline bool isInt(unsigned N, int64_t x) {
return N >= 64 || (-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1)));
}
-constexpr uint32_t generateBitmask(int n) {
- return static_cast<uint32_t>((1 << n) - 1);
-}
-
-constexpr uint32_t bitcount(unsigned n) {
- int count = 0;
- while (n > 0) {
- count += 1;
- n = n & (n - 1);
- }
- return count;
-}
-
constexpr bool isPowerOf2(unsigned v) {
return v && ((v & (v - 1)) == 0);
}
-uint32_t accBVec(const std::vector<bool>& v);
-void buildVec(std::vector<bool>& v, uint32_t n);
-
-constexpr inline unsigned floorlog2(unsigned x) {
- return x == 1 ? 0 : 1 + floorlog2(x >> 1);
-}
-
-constexpr inline unsigned ceillog2(unsigned x) {
- return x == 1 || x == 0 ? 1 : floorlog2(x - 1) + 1;
-}
-
-constexpr bool is_powerof2(int v) {
- return v && ((v & (v - 1)) == 0);
-}
-
template <typename T>
unsigned firstSetBitIdx(const T& val) {
for (unsigned i = 0; i < CHAR_BIT * sizeof(T); i++) {

MODIFY
src/cachesim/cachegraphic.cpp
src/cachesim/cachegraphic.cpp
@@ -97,7 +97,7 @@ void CacheGraphic::updateLineReplFields(unsigned lineIdx) {
// If LRU was just initialized, the actual (software) LRU value may be very large. Mask to the
// number of actual LRU bits.
unsigned lruVal = cacheLine->at(way.first).lru;
- lruVal &= generateBitmask(m_cache.getWaysBits());
+ lruVal &= vsrtl::generateBitmask(m_cache.getWaysBits());
const QString lruText = QString::number(lruVal);
way.second.lru->setText(lruText);

MODIFY
src/cachesim/cachesim.cpp
src/cachesim/cachesim.cpp
@@ -88,7 +88,7 @@ CacheSim::CacheSize CacheSim::getCacheSize() const {
}
// Tag bits
- componentBits = bitcount(m_tagMask) * entries;
+ componentBits = vsrtl::bitcount(m_tagMask) * entries;
size.components.push_back("Tag bits: " + QString::number(componentBits));
size.bits += componentBits;
@@ -451,11 +451,11 @@ void CacheSim::reset() {
m_traceStack.clear();
int bitoffset = 2; // 2^2 = 4-byte offset (32-bit words in cache)
- m_blockMask = generateBitmask(getBlockBits()) << bitoffset;
+ m_blockMask = vsrtl::generateBitmask(getBlockBits()) << bitoffset;
bitoffset += getBlockBits();
- m_lineMask = generateBitmask(getLineBits()) << bitoffset;
+ m_lineMask = vsrtl::generateBitmask(getLineBits()) << bitoffset;
bitoffset += getLineBits();
- m_tagMask = generateBitmask(32 - bitoffset) << bitoffset;
+ m_tagMask = vsrtl::generateBitmask(32 - bitoffset) << bitoffset;
m_isResetting = false;
emit hitrateChanged();
@@ -467,11 +467,11 @@ void CacheSim::reset() {
void CacheSim::updateConfiguration() {
// Recalculate masks
int bitoffset = 2; // 2^2 = 4-byte offset (32-bit words in cache)
- m_blockMask = generateBitmask(getBlockBits()) << bitoffset;
+ m_blockMask = vsrtl::generateBitmask(getBlockBits()) << bitoffset;
bitoffset += getBlockBits();
- m_lineMask = generateBitmask(getLineBits()) << bitoffset;
+ m_lineMask = vsrtl::generateBitmask(getLineBits()) << bitoffset;
bitoffset += getLineBits();
- m_tagMask = generateBitmask(32 - bitoffset) << bitoffset;
+ m_tagMask = vsrtl::generateBitmask(32 - bitoffset) << bitoffset;
emit configurationChanged();
}

MODIFY
src/io/ioledmatrix.cpp
src/io/ioledmatrix.cpp
@@ -40,7 +40,7 @@ QString IOLedMatrix::description() const {
}
uint32_t IOLedMatrix::ioRead(uint32_t offset, unsigned size) {
- return (m_ledRegs.at(offset / 4) >> (offset % 4)) & generateBitmask(size * 8);
+ return (m_ledRegs.at(offset / 4) >> (offset % 4)) & vsrtl::generateBitmask(size * 8);
}
void IOLedMatrix::ioWrite(uint32_t offset, uint32_t value, unsigned) {

MODIFY
src/processors/RISC-V/rv_instrparser.h
src/processors/RISC-V/rv_instrparser.h
@@ -13,7 +13,7 @@ using decode_functor = std::function<std::vector<T>(T)>;
template <typename T>
decode_functor<T> generateInstrParser(const std::vector<int>& bitFields) {
constexpr int size_bits = sizeof(T) * CHAR_BIT;
- static_assert(is_powerof2(size_bits) && size_bits >= 32, "Invalid word size parameter");
+ static_assert(isPowerOf2(size_bits) && size_bits >= 32, "Invalid word size parameter");
// Generates functors that can decode a binary number based on the input
// vector which is supplied upon generation
assert(std::accumulate(bitFields.begin(), bitFields.end(), 0) == size_bits &&
@@ -24,7 +24,7 @@ decode_functor<T> generateInstrParser(const std::vector<int>& bitFields) {
// Generate bit masks and fill parse vector
for (const auto& field : bitFields) {
- parseVector.emplace_back(field, generateBitmask(field));
+ parseVector.emplace_back(field, vsrtl::generateBitmask(field));
}
// Create parse functor

Remove duplicate functions from VSRTL binutils