Use CacheShim for managing access to L1 interface
MODIFY
src/cachesim/l1cacheshim.cpp
src/cachesim/l1cacheshim.cpp
@@ -7,6 +7,7 @@ namespace Ripes {
L1CacheShim::L1CacheShim(CacheType type, QObject* parent) : CacheInterface(parent), m_type(type) {
reassociateMemory();
connect(ProcessorHandler::get(), &ProcessorHandler::reqProcessorReset, this, &L1CacheShim::processorReset);
+ processorReset();
}
void L1CacheShim::access(uint32_t, AccessType) {
@@ -24,7 +25,7 @@ void L1CacheShim::processorReset() {
// Propagate a reset through the cache hierarchy
CacheInterface::reset();
- if (m_memory.rw || m_memory.rom) {
+ if ((m_memory.rw || m_memory.rom) && m_nextLevelCache.lock()) {
// Reload the initial (cycle 0) state of the processor. This is necessary to reflect ie. the instruction which
// is loaded from the instruction memory in cycle 0.
processorWasClocked();
@@ -45,8 +46,8 @@ void L1CacheShim::processorWasClocked() {
case MemOp::SW:
if (m_memory.rw->wr_en.uValue() == 1) {
m_nextLevelCache.lock()->access(m_memory.rw->addr.uValue(), AccessType::Write);
- break;
}
+ break;
case MemOp::LB:
case MemOp::LBU:
case MemOp::LH:

MODIFY
src/cachetabwidget.cpp
src/cachetabwidget.cpp
@@ -36,8 +36,11 @@ CacheTabWidget::CacheTabWidget(QWidget* parent) : QWidget(parent), m_ui(new Ui::
m_ui->setupUi(this);
- m_ui->dataCacheWidget->setType(CacheSim::CacheType::DataCache);
- m_ui->instructionCacheWidget->setType(CacheSim::CacheType::InstrCache);
+ m_l1dShim = std::make_unique<L1CacheShim>(L1CacheShim::CacheType::DataCache, this);
+ m_l1iShim = std::make_unique<L1CacheShim>(L1CacheShim::CacheType::InstrCache, this);
+
+ m_l1dShim->setNextLevelCache(m_ui->dataCacheWidget->getCacheSim());
+ m_l1iShim->setNextLevelCache(m_ui->instructionCacheWidget->getCacheSim());
// Make selection changes in the cache trigger the memory viewer to set its central address to the selected address
connectCacheWidget(m_ui->dataCacheWidget);

MODIFY
src/cachetabwidget.h
src/cachetabwidget.h
#pragma once
#include <QWidget>
+#include "cachesim/l1cacheshim.h"
+
namespace Ripes {
class MemoryTab;
class CacheWidget;
@@ -31,6 +33,9 @@ private:
int m_addTabIdx = -1;
int m_nextCacheLevel = 2;
QSize m_defaultTabButtonSize;
+
+ std::unique_ptr<L1CacheShim> m_l1dShim;
+ std::unique_ptr<L1CacheShim> m_l1iShim;
};
} // namespace Ripes

Use CacheShim for managing access to L1 interface