Fix some 32-bit hardcoding in cachesim and cachegraphic
MODIFY
src/binutils.h
src/binutils.h
#pragma once
+#include <math.h>
#include <cstdint>
#include <vector>
-#include "limits.h"
#include "VSRTL/interface/vsrtl_binutils.h"
+#include "limits.h"
#include "ripes_types.h"
+/// Most of the code in this file originates from LLVM MathExtras.h
+
namespace Ripes {
/// Checks if an integer fits into the given bit width.
-/// from LLVM MathExtras.h
template <unsigned N>
constexpr inline bool isInt(VIntS x) {
return N >= 64 || (-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1)));
@@ -75,6 +77,10 @@ constexpr bool isPowerOf2(unsigned v) {
return v && ((v & (v - 1)) == 0);
}
+inline unsigned log2Ceil(double v) {
+ return static_cast<unsigned>(std::ceil(std::log2(v)));
+}
+
template <typename T>
unsigned firstSetBitIdx(const T& val) {
for (unsigned i = 0; i < CHAR_BIT * sizeof(T); i++) {

MODIFY
src/cachesim/cachegraphic.cpp
src/cachesim/cachegraphic.cpp
@@ -132,6 +132,7 @@ void CacheGraphic::updateWay(unsigned lineIdx, unsigned wayIdx) {
simWay = cacheLine->at(wayIdx);
};
+ const unsigned bytes = ProcessorHandler::currentISA()->bytes();
// ======================== Update block text fields ======================
if (simWay.valid) {
for (int i = 0; i < m_cache.getBlocks(); i++) {
@@ -150,7 +151,7 @@ void CacheGraphic::updateWay(unsigned lineIdx, unsigned wayIdx) {
// Update block text
const AInt addressForBlock = m_cache.buildAddress(simWay.tag, lineIdx, i);
- const auto data = ProcessorHandler::getMemory().readMemConst(addressForBlock);
+ const auto data = ProcessorHandler::getMemory().readMemConst(addressForBlock, bytes);
const QString text = encodeRadixValue(data, Radix::Hex, ProcessorHandler::currentISA()->bytes());
blockTextItem->setText(text);
QString tooltip =
@@ -303,7 +304,7 @@ void CacheGraphic::drawIndexingItems() {
drawText(nextBitText, nextBitsPos - QPointF{m_fm.width(nextBitText), smallerFontMetric.height()}, &smallerFont);
};
- drawNextBitPos(2); // Always start 2 bits in due to word-indexing
+ drawNextBitPos(log2Ceil(ProcessorHandler::currentISA()->bytes())); // Account for word indexing
if (m_cache.getBlockBits() > 0) {
m_blockIndexStartPoint = nextBitsPos;
drawNextBitPos(m_cache.getBlockBits());

MODIFY
src/cachesim/cachesim.cpp
src/cachesim/cachesim.cpp
@@ -23,6 +23,8 @@ void CacheInterface::reverse() {
}
CacheSim::CacheSim(QObject* parent) : CacheInterface(parent) {
+ m_byteOffset = log2Ceil(ProcessorHandler::currentISA()->bytes());
+ m_wordBits = ProcessorHandler::currentISA()->bits();
connect(ProcessorHandler::get(), &ProcessorHandler::runFinished, this, [=] {
// Given that we are not updating the graphical state of the cache simulator whilst the processor is running,
// once running is finished, the entirety of the cache view should be reloaded in the graphical view.
@@ -94,7 +96,7 @@ CacheSim::CacheSize CacheSim::getCacheSize() const {
size.bits += componentBits;
// Data bits
- componentBits = 32 * entries * getBlocks();
+ componentBits = m_wordBits * entries * getBlocks();
size.components.push_back("Data bits: " + QString::number(componentBits));
size.bits += componentBits;
@@ -389,27 +391,27 @@ void CacheSim::pushTrace(const CacheTrace& eviction) {
AInt CacheSim::buildAddress(unsigned tag, unsigned lineIdx, unsigned blockIdx) const {
AInt address = 0;
- address |= tag << (2 /*byte offset*/ + getBlockBits() + getLineBits());
- address |= lineIdx << (2 /*byte offset*/ + getBlockBits());
- address |= blockIdx << (2 /*byte offset*/);
+ address |= tag << (m_byteOffset + getBlockBits() + getLineBits());
+ address |= lineIdx << (m_byteOffset + getBlockBits());
+ address |= blockIdx << (m_byteOffset);
return address;
}
unsigned CacheSim::getLineIdx(const AInt address) const {
AInt maskedAddress = address & m_lineMask;
- maskedAddress >>= 2 + getBlockBits();
+ maskedAddress >>= m_byteOffset + getBlockBits();
return maskedAddress;
}
unsigned CacheSim::getTag(const AInt address) const {
AInt maskedAddress = address & m_tagMask;
- maskedAddress >>= 2 + getBlockBits() + getLineBits();
+ maskedAddress >>= m_byteOffset + getBlockBits() + getLineBits();
return maskedAddress;
}
unsigned CacheSim::getBlockIdx(const AInt address) const {
AInt maskedAddress = address & m_blockMask;
- maskedAddress >>= 2;
+ maskedAddress >>= m_byteOffset;
return maskedAddress;
}
@@ -439,6 +441,15 @@ void CacheSim::reverse() {
CacheInterface::reverse();
}
+void CacheSim::recalculateMasks() {
+ unsigned bitOffset = m_byteOffset;
+ m_blockMask = vsrtl::generateBitmask(getBlockBits()) << bitOffset;
+ bitOffset += getBlockBits();
+ m_lineMask = vsrtl::generateBitmask(getLineBits()) << bitOffset;
+ bitOffset += getLineBits();
+ m_tagMask = vsrtl::generateBitmask(m_wordBits - bitOffset) << bitOffset;
+}
+
void CacheSim::reset() {
/** see comment of m_isResetting */
if (m_isResetting) {
@@ -451,12 +462,9 @@ void CacheSim::reset() {
m_accessTrace.clear();
m_traceStack.clear();
- int bitoffset = 2; // 2^2 = 4-byte offset (32-bit words in cache)
- m_blockMask = vsrtl::generateBitmask(getBlockBits()) << bitoffset;
- bitoffset += getBlockBits();
- m_lineMask = vsrtl::generateBitmask(getLineBits()) << bitoffset;
- bitoffset += getLineBits();
- m_tagMask = vsrtl::generateBitmask(32 - bitoffset) << bitoffset;
+ m_wordBits = ProcessorHandler::currentISA()->bits();
+ m_byteOffset = log2Ceil(ProcessorHandler::currentISA()->bytes());
+ recalculateMasks();
m_isResetting = false;
emit hitrateChanged();
@@ -467,12 +475,8 @@ void CacheSim::reset() {
void CacheSim::updateConfiguration() {
// Recalculate masks
- int bitoffset = 2; // 2^2 = 4-byte offset (32-bit words in cache)
- m_blockMask = vsrtl::generateBitmask(getBlockBits()) << bitoffset;
- bitoffset += getBlockBits();
- m_lineMask = vsrtl::generateBitmask(getLineBits()) << bitoffset;
- bitoffset += getLineBits();
- m_tagMask = vsrtl::generateBitmask(32 - bitoffset) << bitoffset;
+ m_byteOffset = log2Ceil(ProcessorHandler::currentISA()->bytes());
+ recalculateMasks();
emit configurationChanged();
}

MODIFY
src/cachesim/cachesim.h
src/cachesim/cachesim.h
@@ -236,6 +236,7 @@ private:
* Called whenever one of the cache parameters changes. Emits signal configurationChanged after updating.
*/
void updateConfiguration();
+ void recalculateMasks();
/**
* @brief reassociateMemory
@@ -254,6 +255,8 @@ private:
int m_blocks = 2; // Some power of 2
int m_lines = 5; // Some power of 2
int m_ways = 0; // Some power of 2
+ unsigned m_byteOffset = -1; // # of bits to represent the # of bytes in a word
+ unsigned m_wordBits = -1;
/**
* @brief m_cacheLines

MODIFY
src/processorhandler.cpp
src/processorhandler.cpp
@@ -329,8 +329,9 @@ AInt ProcessorHandler::_getTextStart() const {
QString ProcessorHandler::_disassembleInstr(const AInt addr) const {
if (m_program) {
+ const unsigned instrBytes = _currentISA()->instrBytes();
return m_currentAssembler
- ->disassemble(m_currentProcessor->getMemory().readMem(addr), m_program.get()->symbols, addr)
+ ->disassemble(m_currentProcessor->getMemory().readMem(addr, instrBytes), m_program.get()->symbols, addr)
.first;
} else {
return QString();

MODIFY
src/syscall/print.h
src/syscall/print.h
@@ -46,7 +46,7 @@ public:
char byte;
AInt address = arg0;
do {
- byte = static_cast<char>(ProcessorHandler::getMemory().readMemConst(address++) & 0xFF);
+ byte = static_cast<char>(ProcessorHandler::getMemory().readMemConst(address++, 1) & 0xFF);
string.append(byte);
} while (byte != '\0');
SystemIO::printString(QString::fromUtf8(string));

Fix some 32-bit hardcoding in cachesim and cachegraphic