Implement SRAI instruction
MODIFY
src/assembler.cpp
src/assembler.cpp
@@ -140,6 +140,8 @@ int Assembler::getImmediate(QString string, bool& canConvert) {
QByteArray Assembler::assembleOpImmInstruction(const QStringList& fields, int row) {
Q_UNUSED(row);
uint32_t funct3 = 0;
+ bool hasFunct7 = false;
+ uint32_t funct7 = 0;
bool canConvert;
int imm = getImmediate(fields[3], canConvert);
if (fields[0] == "addi") {
@@ -164,7 +166,9 @@ QByteArray Assembler::assembleOpImmInstruction(const QStringList& fields, int ro
} else if (fields[0] == "srli") {
funct3 = 0b101;
} else if (fields[0] == "srai") {
+ hasFunct7 = true;
funct3 = 0b101;
+ funct7 = 0b0100000;
} else if (fields[0] == "ori") {
funct3 = 0b110;
} else if (fields[0] == "andi") {
@@ -173,9 +177,15 @@ QByteArray Assembler::assembleOpImmInstruction(const QStringList& fields, int ro
m_error = true;
Q_ASSERT(false);
};
+
+ if (hasFunct7) {
+ return uintToByteArr(OP_IMM | funct3 << 12 | getRegisterNumber(fields[1]) << 7 |
+ getRegisterNumber(fields[2]) << 15 | funct7 << 25 | imm << 20);
+ } else {
return uintToByteArr(OP_IMM | funct3 << 12 | getRegisterNumber(fields[1]) << 7 |
getRegisterNumber(fields[2]) << 15 | imm << 20);
}
+}
QByteArray Assembler::assembleOpInstruction(const QStringList& fields, int row) {
Q_UNUSED(row);

MODIFY
src/pipeline.cpp
src/pipeline.cpp
@@ -151,24 +151,30 @@ Pipeline::Pipeline() {
}
void Pipeline::immGen() {
- uint32_t opcode = (uint32_t)r_instr_IFID & 0b1111111;
+ uint32_t instr = (uint32_t)r_instr_IFID;
+ uint32_t opcode = instr & 0b1111111;
if (opcode == 0b0110111 || opcode == 0b0010111) {
// LUI & AUIPC
- s_imm_ID = Signal<32>((uint32_t)r_instr_IFID & 0xfffff000);
+ s_imm_ID = Signal<32>(instr & 0xfffff000);
} else if (opcode == 0b1101111) {
// JAL
- auto fields = Parser::getParser()->decodeJInstr((uint32_t)r_instr_IFID);
+ auto fields = Parser::getParser()->decodeJInstr(instr);
s_imm_ID = signextend<int32_t, 21>(fields[0] << 20 | fields[1] << 1 | fields[2] << 11 | fields[3] << 12);
} else if (opcode == 0b1100111) {
// JALR
- s_imm_ID = Signal<32>(signextend<int32_t, 12>(((uint32_t)r_instr_IFID >> 20)));
+ s_imm_ID = Signal<32>(signextend<int32_t, 12>((instr >> 20)));
} else {
- // Generates an immediate value on the basis of an instruction opcode
+ auto fields = Parser::getParser()->decodeRInstr(instr);
+ if (opcode == 0b0010011 && (fields[3] == 0b001 || fields[3] == 0b101)) {
+ // SLLI/SRLI/SRAI
+ s_imm_ID = Signal<32>(fields[1]);
+ } else {
+ // Load, store or regular immediate instruction
// Opcode bits 5 and 6 can define the required fields for generating the immediate
- switch (((uint32_t)r_instr_IFID & 0b1100000) >> 5) {
+ switch ((instr & 0b1100000) >> 5) {
case 0b00: {
- // Load instruction, sign extend bits 31:20
- s_imm_ID = Signal<32>(signextend<int32_t, 12>(((uint32_t)r_instr_IFID >> 20)));
+ // Load or regular immediate instruction, sign extend bits 31:20
+ s_imm_ID = Signal<32>(signextend<int32_t, 12>((instr >> 20)));
break;
}
case 0b01: {
@@ -179,7 +185,7 @@ void Pipeline::immGen() {
}
default: {
// Conditional branch instructions
- auto fields = Parser::getParser()->decodeBInstr((uint32_t)r_instr_IFID);
+ auto fields = Parser::getParser()->decodeBInstr(instr);
s_imm_ID = signextend<int32_t, 13>((fields[0] << 12) | (fields[1] << 5) | (fields[5] << 1) |
(fields[6] << 11));
break;
@@ -187,6 +193,7 @@ void Pipeline::immGen() {
}
}
}
+}
void Pipeline::controlGen() {
// Deassert all control lines
@@ -570,7 +577,8 @@ void Pipeline::propagateCombinational() {
mux_alures_PC4_MEM.update();
if (r_MemRead_EXMEM) {
// Store read access for use in GUI
- RVAccess acc{(uint32_t)r_PC_EXMEM, RW::Read, (uint32_t)r_alures_EXMEM, static_cast<uint32_t>(m_pcsCycles.size())};
+ RVAccess acc{(uint32_t)r_PC_EXMEM, RW::Read, (uint32_t)r_alures_EXMEM,
+ static_cast<uint32_t>(m_pcsCycles.size())};
m_RVAccesses.insert(m_RVAccesses.begin(), acc);
switch ((uint32_t)r_MemRead_EXMEM) {
case LB: {
@@ -729,7 +737,8 @@ int Pipeline::step() {
m_reg.clock();
if (r_MemWrite_EXMEM) {
// Store write access for use in GUI
- RVAccess acc{(uint32_t)r_PC_EXMEM, RW::Write, (uint32_t)r_alures_EXMEM, static_cast<uint32_t>(m_pcsCycles.size())};
+ RVAccess acc{(uint32_t)r_PC_EXMEM, RW::Write, (uint32_t)r_alures_EXMEM,
+ static_cast<uint32_t>(m_pcsCycles.size())};
m_RVAccesses.insert(m_RVAccesses.begin(), acc);
switch ((uint32_t)r_MemWrite_EXMEM) {
case SB: {

MODIFY
src/syntaxhighlighter.cpp
src/syntaxhighlighter.cpp
@@ -174,6 +174,7 @@ SyntaxHighlighter::SyntaxHighlighter(QTextDocument* parent) : QSyntaxHighlighter
<< "\\bbgeu\\b"
<< "\\bsrli\\b"
<< "\\bslli\\b"
+ << "\\bsrai\\b"
<< "\\bor\\b"
<< "\\bori\\b"
<< "\\band\\b"

Implement SRAI instruction