Fixed Issue with branches
MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw.h
// Stage separating registers
#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_ifid.h"
-#include "rv5s_no_fw_exmem.h"
+#include "../rv5s/rv5s_exmem.h"
#include "../rv5s/rv5s_memwb.h"
#include "rv5s_no_fw_idex.h"
@@ -195,7 +195,6 @@ public:
idex_reg->mem_do_write_out >> exmem_reg->mem_do_write_in;
idex_reg->mem_do_read_out >> exmem_reg->mem_do_read_in;
idex_reg->mem_op_out >> exmem_reg->mem_op_in;
- idex_reg->alu_op2_ctrl_out >> exmem_reg->alu_op2_ctrl_in;
idex_reg->valid_out >> exmem_reg->valid_in;
@@ -222,6 +221,7 @@ public:
decode->r1_reg_idx >> hzunit->id_reg1_idx;
decode->r2_reg_idx >> hzunit->id_reg2_idx;
control->alu_op2_ctrl >> hzunit->id_alu_op_ctrl_2;
+ control->do_branch >> hzunit->id_do_branch;
idex_reg->mem_do_read_out >> hzunit->ex_do_mem_read_en;
idex_reg->reg_do_write_out >> hzunit->ex_do_reg_write;
@@ -249,7 +249,7 @@ public:
// Stage seperating registers
SUBCOMPONENT(ifid_reg, IFID);
SUBCOMPONENT(idex_reg, RV5S_NO_FW_IDEX);
- SUBCOMPONENT(exmem_reg, RV5S_NO_FW_EXMEM);
+ SUBCOMPONENT(exmem_reg, RV5S_EXMEM);
SUBCOMPONENT(memwb_reg, RV5S_MEMWB);
// Multiplexers

DELETE
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_exmem.h
-#pragma once
-
-#include "VSRTL/core/vsrtl_component.h"
-#include "VSRTL/core/vsrtl_register.h"
-
-#include "../riscv.h"
-
-#include "../rv5s_no_fw_hz/rv5s_no_fw_hz_exmem.h"
-
-namespace vsrtl {
-namespace core {
-using namespace Ripes;
-
-class RV5S_NO_FW_EXMEM : public EXMEM {
-public:
- RV5S_NO_FW_EXMEM(std::string name, SimComponent* parent) : EXMEM(name, parent) {
-
- // Need ctrl-Signal to identify if reg2 is register or immediate
- CONNECT_REGISTERED_CLEN_INPUT(alu_op2_ctrl, clear, enable);
-
- // We want stalling info to persist through clearing of the register, so stalled register is always enabled and
- // never cleared.
- CONNECT_REGISTERED_CLEN_INPUT(stalled, 0, 1);
- }
-
- REGISTERED_CLEN_INPUT(alu_op2_ctrl, AluSrc2::width());
-
- REGISTERED_CLEN_INPUT(stalled, 1);
-};
-
-} // namespace core
-} // namespace vsrtl

MODIFY
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_hazardunit.h
src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_hazardunit.h
@@ -20,6 +20,7 @@ public:
INPUTPORT(id_reg1_idx, RV_REGS_BITS);
INPUTPORT(id_reg2_idx, RV_REGS_BITS);
+ INPUTPORT(id_do_branch, 1);
INPUTPORT_ENUM(id_alu_op_ctrl_2, AluSrc2);
INPUTPORT(ex_reg_wr_idx, RV_REGS_BITS);
@@ -74,30 +75,30 @@ private:
// Check if data Hazard between instruction i+1 and i
bool hasDataHazardEx() const {
- const unsigned idx1 = id_reg1_idx.uValue();
- const unsigned idx2 = id_reg2_idx.uValue();
- const bool idx2isReg = id_alu_op_ctrl_2.uValue() == AluSrc2::REG2;
- const unsigned exidx = ex_reg_wr_idx.uValue();
- const bool regw = ex_do_reg_write.uValue();
- // If destination is x0 ignore hazard
- if(exidx == 0){
- return false;
- }
- return ((exidx == idx1) || ((exidx == idx2) && idx2isReg)) && regw;
+ const unsigned exWriteIdx = ex_reg_wr_idx.uValue();
+ const bool exRegWrite = ex_do_reg_write.uValue();
+ return hasDataHazard(exWriteIdx, exRegWrite);
}
// Check if data Hazard between instruction i+2 and i
bool hasDataHazardMem() const {
+ const unsigned memWriteIdx = mem_reg_wr_idx.uValue();
+ const bool memRegWrite = mem_do_reg_write.uValue();
+ return hasDataHazard(memWriteIdx, memRegWrite);
+ }
+
+ bool hasDataHazard(unsigned writeIdx, bool regWrite) const {
const unsigned idx1 = id_reg1_idx.uValue();
const unsigned idx2 = id_reg2_idx.uValue();
const bool idx2isReg = id_alu_op_ctrl_2.uValue() == AluSrc2::REG2;
- const unsigned memidx = mem_reg_wr_idx.uValue();
- const bool regw = mem_do_reg_write.uValue();
+
+ // Get branch information (when branch, idx2isReg must be ignored, because it is IMM)
+ const bool isBranch = id_do_branch.uValue();
// If destination is x0 ignore hazard
- if(memidx == 0){
+ if(writeIdx == 0){
return false;
}
- return ((memidx == idx1) || ((memidx == idx2) && idx2isReg)) && regw;
+ return ((writeIdx == idx1) || ((writeIdx == idx2) && (idx2isReg || isBranch))) && regWrite;
}
};
} // namespace core

Fixed Issue with branches