RV5S: Add missing load instructions to control signal
MODIFY
src/processors/RISC-V/rv_control.h
src/processors/RISC-V/rv_control.h
@@ -212,7 +212,7 @@ public:
mem_do_read_ctrl << [=] {
switch(opcode.uValue()) {
- case RVInstr::LB: case RVInstr::LH: case RVInstr::LW:
+ case RVInstr::LB: case RVInstr::LH: case RVInstr::LW: case RVInstr::LBU: case RVInstr::LHU:
return 1;
default: return 0;
}

RV5S: Add missing load instructions to control signal