Add missing VInt/AInt conversions
MODIFY
src/assembler/objdump.cpp
src/assembler/objdump.cpp
@@ -13,9 +13,7 @@ void incrementAddressOffsetMap(const QString& text, AddrOffsetMap& map, int& off
}
} // namespace
-QString stringifyProgram(std::weak_ptr<const Program> program,
- std::function<QString(const std::vector<char>&, uint32_t index)> stringifier,
- AddrOffsetMap& addrOffsetMap) {
+QString stringifyProgram(std::weak_ptr<const Program> program, Stringifier stringifier, AddrOffsetMap& addrOffsetMap) {
if (auto sp = program.lock()) {
const auto* textSection = sp->getSection(TEXT_SECTION_NAME);
if (!textSection)

MODIFY
src/assembler/objdump.h
src/assembler/objdump.h
@@ -22,6 +22,13 @@ namespace Assembler {
*/
using AddrOffsetMap = std::map<unsigned, std::pair<unsigned, QString>>;
+/**
+ * Stringifer
+ * A stringifier is a function that takes a vector of bytes (representing an instruction word) alongside a base
+ * address, and returns a string representation of the data.
+ */
+using Stringifier = std::function<QString(const std::vector<char>&, AInt)>;
+
QString objdump(const std::shared_ptr<const Program>& program, AddrOffsetMap& addrOffsetMap);
QString binobjdump(const std::shared_ptr<const Program>& program, AddrOffsetMap& addrOffsetMap);

MODIFY
src/cachetab.h
src/cachetab.h
#include <QWidget>
#include "ripestab.h"
+#include "ripes_types.h"
+
namespace Ripes {
namespace Ui {
@@ -19,7 +21,7 @@ public:
void tabVisibilityChanged(bool visible) override;
signals:
- void focusAddressChanged(uint32_t address);
+ void focusAddressChanged(AInt address);
private:
Ui::CacheTab* m_ui;

MODIFY
src/instructionmodel.cpp
src/instructionmodel.cpp
@@ -45,7 +45,7 @@ void InstructionModel::updateStageInfo() {
}
}
const auto stageInfo = ProcessorHandler::getProcessor()->stageInfo(i);
- const uint32_t oldAddress = oldStageInfo.pc;
+ const AInt oldAddress = oldStageInfo.pc;
const bool stageInfoChanged = oldStageInfo != stageInfo;
oldStageInfo = stageInfo;
if (stageInfoChanged) {
@@ -65,7 +65,7 @@ void InstructionModel::updateStageInfo() {
}
bool InstructionModel::setData(const QModelIndex& index, const QVariant& value, int role) {
- const uint32_t addr = indexToAddress(index);
+ const AInt addr = indexToAddress(index);
if ((index.column() == Column::Breakpoint) && role == Qt::CheckStateRole) {
if (static_cast<Qt::CheckState>(value.toInt()) == Qt::Checked) {
ProcessorHandler::setBreakpoint(addr, !ProcessorHandler::hasBreakpoint(addr));
@@ -93,13 +93,13 @@ QVariant InstructionModel::headerData(int section, Qt::Orientation orientation,
return QVariant();
}
-QVariant InstructionModel::BPData(uint32_t addr) const {
+QVariant InstructionModel::BPData(AInt addr) const {
return ProcessorHandler::hasBreakpoint(addr);
}
-QVariant InstructionModel::PCData(uint32_t addr) const {
+QVariant InstructionModel::PCData(AInt addr) const {
return "0x" + QString::number(addr, 16);
}
-QVariant InstructionModel::stageData(uint32_t addr) const {
+QVariant InstructionModel::stageData(AInt addr) const {
QStringList stagesForAddr;
for (const auto& si : m_stageInfos) {
if ((si.second.pc == addr) && si.second.stage_valid) {
@@ -113,7 +113,7 @@ QVariant InstructionModel::stageData(uint32_t addr) const {
}
}
-QVariant InstructionModel::instructionData(uint32_t addr) const {
+QVariant InstructionModel::instructionData(AInt addr) const {
return ProcessorHandler::disassembleInstr(addr);
}
@@ -121,7 +121,7 @@ QVariant InstructionModel::data(const QModelIndex& index, int role) const {
if (!index.isValid()) {
return QVariant();
}
- const uint32_t addr = indexToAddress(index);
+ const AInt addr = indexToAddress(index);
switch (index.column()) {
case Column::Breakpoint: {
if (role == Qt::CheckStateRole) {

MODIFY
src/instructionmodel.h
src/instructionmodel.h
@@ -11,14 +11,14 @@ namespace Ripes {
class Parser;
class Pipeline;
-static inline uint32_t indexToAddress(const QModelIndex& index) {
+static inline AInt indexToAddress(const QModelIndex& index) {
if (auto prog_spt = ProcessorHandler::getProgram()) {
return (index.row() * 4) + prog_spt->getSection(TEXT_SECTION_NAME)->address;
}
return 0;
}
-static inline int addressToRow(uint32_t addr) {
+static inline int addressToRow(AInt addr) {
if (auto prog_spt = ProcessorHandler::getProgram()) {
if (prog_spt->getSection(TEXT_SECTION_NAME) != nullptr) {
return (addr - prog_spt->getSection(TEXT_SECTION_NAME)->address) / 4;
@@ -48,15 +48,15 @@ signals:
* Emitted whenever the PC of the first stage, changed. Argument is the address of the instruction now present in
* the first stage.
*/
- void firstStageInstrChanged(uint32_t);
+ void firstStageInstrChanged(AInt);
private:
void updateStageInfo();
- QVariant BPData(uint32_t addr) const;
- QVariant PCData(uint32_t addr) const;
- QVariant stageData(uint32_t addr) const;
- QVariant instructionData(uint32_t addr) const;
+ QVariant BPData(AInt addr) const;
+ QVariant PCData(AInt addr) const;
+ QVariant stageData(AInt addr) const;
+ QVariant instructionData(AInt addr) const;
void updateRowCount();
void onProcessorReset();

MODIFY
src/io/iomanager.cpp
src/io/iomanager.cpp
@@ -27,8 +27,8 @@ QString IOManager::cSymbolsHeaderpath() const {
}
}
-uint32_t IOManager::nextPeripheralAddress() const {
- uint32_t base = 0;
+AInt IOManager::nextPeripheralAddress() const {
+ AInt base = 0;
if (m_periphMMappings.empty()) {
base = RipesSettings::value(RIPES_SETTING_PERIPHERALS_START).toUInt();
} else {
@@ -41,9 +41,9 @@ uint32_t IOManager::nextPeripheralAddress() const {
return base;
}
-uint32_t IOManager::assignBaseAddress(IOBase* peripheral) {
+AInt IOManager::assignBaseAddress(IOBase* peripheral) {
unregisterPeripheralWithProcessor(peripheral);
- const uint32_t base = nextPeripheralAddress();
+ const AInt base = nextPeripheralAddress();
m_periphMMappings[peripheral] = {base, peripheral->byteSize(), peripheral->name()};
registerPeripheralWithProcessor(peripheral);
return base;
@@ -69,13 +69,13 @@ void IOManager::registerPeripheralWithProcessor(IOBase* peripheral) {
ProcessorHandler::getMemory().addIORegion(
m_periphMMappings.at(peripheral).startAddr, peripheral->byteSize(),
vsrtl::core::IOFunctors{
- [peripheral](uint32_t offset, uint32_t value, uint32_t size) { peripheral->ioWrite(offset, value, size); },
- [peripheral](uint32_t offset, uint32_t size) { return peripheral->ioRead(offset, size); }});
+ [peripheral](AInt offset, VInt value, unsigned size) { peripheral->ioWrite(offset, value, size); },
+ [peripheral](AInt offset, unsigned size) { return peripheral->ioRead(offset, size); }});
- peripheral->memWrite = [](uint32_t address, uint32_t value, uint32_t size) {
+ peripheral->memWrite = [](AInt address, VInt value, unsigned size) {
ProcessorHandler::getMemory().writeMem(address, value, size);
};
- peripheral->memRead = [](uint32_t address, uint32_t size) {
+ peripheral->memRead = [](AInt address, unsigned size) {
return ProcessorHandler::getMemory().readMem(address, size);
};
}
@@ -132,9 +132,8 @@ void IOManager::refreshMemoryMap() {
const auto& program = ProcessorHandler::getProgram();
if (program) {
for (const auto& section : program.get()->sections) {
- m_memoryMap[section.second.address] =
- MemoryMapEntry{static_cast<uint32_t>(section.second.address),
- static_cast<unsigned>(section.second.data.size()), section.second.name};
+ m_memoryMap[section.second.address] = MemoryMapEntry{
+ section.second.address, static_cast<unsigned>(section.second.data.size()), section.second.name};
}
}
@@ -142,9 +141,9 @@ void IOManager::refreshMemoryMap() {
emit memoryMapChanged();
}
-std::vector<std::pair<Symbol, uint32_t>> IOManager::assemblerSymbolsForPeriph(IOBase* peripheral) const {
+std::vector<std::pair<Symbol, AInt>> IOManager::assemblerSymbolsForPeriph(IOBase* peripheral) const {
const QString& periphName = cName(peripheral->name());
- std::vector<std::pair<Symbol, uint32_t>> symbols;
+ std::vector<std::pair<Symbol, AInt>> symbols;
const auto& periphInfo = m_periphMMappings.at(peripheral);
symbols.push_back({{periphName + "_BASE", Symbol::Type::Address}, periphInfo.startAddr});
symbols.push_back({periphName + "_SIZE", periphInfo.size});

MODIFY
src/io/iomanager.h
src/io/iomanager.h
@@ -20,13 +20,13 @@ struct PeripheralID {
using PeriphIDs = std::vector<PeripheralID>;
struct MemoryMapEntry {
- uint32_t startAddr;
+ AInt startAddr;
unsigned size;
QString name;
- uint32_t end() const { return startAddr + size; }
+ AInt end() const { return startAddr + size; }
};
-using MemoryMap = std::map<uint32_t, MemoryMapEntry>;
+using MemoryMap = std::map<AInt, MemoryMapEntry>;
class IOManager : public QObject {
Q_OBJECT
@@ -53,7 +53,7 @@ public:
* @returns as cSymbols, but as a map which can be directly loaded into the assembler.
*/
const Assembler::SymbolMap& assemblerSymbols() const { return m_assemblerSymbols; }
- std::vector<std::pair<Symbol, uint32_t>> assemblerSymbolsForPeriph(IOBase* peripheral) const;
+ std::vector<std::pair<Symbol, AInt>> assemblerSymbolsForPeriph(IOBase* peripheral) const;
signals:
void memoryMapChanged();
@@ -91,9 +91,9 @@ private:
* @brief nextPeripheralAddress
* @returns a valid base address for a new peripheral
*/
- uint32_t nextPeripheralAddress() const;
+ AInt nextPeripheralAddress() const;
- uint32_t assignBaseAddress(IOBase* peripheral);
+ AInt assignBaseAddress(IOBase* peripheral);
void assignBaseAddresses();
MemoryMap m_memoryMap;

MODIFY
src/pipelinediagrammodel.cpp
src/pipelinediagrammodel.cpp
namespace Ripes {
-static inline uint32_t indexToAddress(unsigned index) {
+static inline AInt indexToAddress(unsigned index) {
if (auto spt = ProcessorHandler::getProgram()) {
return (index * ProcessorHandler::currentISA()->bytes()) + spt->getSection(TEXT_SECTION_NAME)->address;
}
@@ -87,7 +87,7 @@ QVariant PipelineDiagramModel::data(const QModelIndex& index, int role) const {
if (!m_cycleStageInfos.count(index.column()))
return QVariant();
- const uint32_t addr = indexToAddress(index.row());
+ const AInt addr = indexToAddress(index.row());
const auto& stageInfo = m_cycleStageInfos.at(index.column());
QStringList stagesForAddr;

MODIFY
src/processors/interface/ripesprocessor.h
src/processors/interface/ripesprocessor.h
@@ -18,7 +18,7 @@ namespace Ripes {
*/
struct StageInfo {
enum class State { None, Stalled, Flushed, WayHazard, Unused };
- vsrtl::VSRTL_VT_U pc = 0;
+ AInt pc = 0;
bool stage_valid = false;
State state;
bool operator==(const StageInfo& other) const {

MODIFY
src/processortab.cpp
src/processortab.cpp
@@ -449,7 +449,7 @@ void ProcessorTab::reset() {
printToLog("\n");
}
-void ProcessorTab::setInstructionViewCenterAddr(uint32_t address) {
+void ProcessorTab::setInstructionViewCenterAddr(AInt address) {
const auto index = addressToRow(address);
const auto view = m_ui->instructionView;
const auto rect = view->rect();

MODIFY
src/processortab.h
src/processortab.h
#include <QToolBar>
#include <QWidget>
+#include "ripes_types.h"
#include "ripestab.h"
namespace vsrtl {
@@ -52,7 +53,7 @@ public slots:
private slots:
void run(bool state);
void clock();
- void setInstructionViewCenterAddr(uint32_t address);
+ void setInstructionViewCenterAddr(AInt address);
void showPipelineDiagram();
private:

MODIFY
src/programviewer.cpp
src/programviewer.cpp
@@ -199,9 +199,7 @@ void ProgramViewer::breakpointAreaPaintEvent(QPaintEvent* event) {
}
}
-namespace {}
-
-QTextBlock ProgramViewer::blockForAddress(unsigned long addr) const {
+QTextBlock ProgramViewer::blockForAddress(AInt addr) const {
const uint64_t adjustedLineNumber =
(addr - ProcessorHandler::get()->getTextStart()) / ProcessorHandler::currentISA()->instrBytes();
@@ -209,7 +207,7 @@ QTextBlock ProgramViewer::blockForAddress(unsigned long addr) const {
return document()->findBlockByNumber(adjustedLineNumber);
}
- unsigned long lineNumber = adjustedLineNumber;
+ uint64_t lineNumber = adjustedLineNumber;
auto low = m_labelAddrOffsetMap.lower_bound(lineNumber);
if (low == m_labelAddrOffsetMap.begin() && lineNumber < low->first) {
// The line number is less that the position of the first offset block; block is directly inferred from

MODIFY
src/radix.h
src/radix.h
@@ -64,7 +64,7 @@ static inline QString encodeRadixValue(VInt value, const Radix type, unsigned by
Q_UNREACHABLE();
}
-static inline uint32_t decodeRadixValue(QString value, const Radix type, bool* ok = nullptr) {
+static inline VInt decodeRadixValue(QString value, const Radix type, bool* ok = nullptr) {
switch (type) {
case Radix::Hex: {
return value.toUInt(ok, 16);

MODIFY
src/ripes_types.h
src/ripes_types.h
namespace Ripes {
// Data types representing simulator memory addresses and simulator values. The type should be wide enough to represent
-// all ISAs supported by Ripes.
-using AInt = uint64_t;
-using VInt = uint64_t;
-using AIntS = typename std::make_signed<AInt>::type;
-using VIntS = typename std::make_signed<VInt>::type;
+// all ISAs supported by Ripes. AInt and VInt are equal, but we discern between the two for code readability.
+using AInt = uint64_t; // Address type
+using VInt = uint64_t; // Value type
+using AIntS = typename std::make_signed<AInt>::type; // Signed address type
+using VIntS = typename std::make_signed<VInt>::type; // Signed value type
} // namespace Ripes

MODIFY
src/syscall/file.h
src/syscall/file.h
@@ -18,8 +18,8 @@ public:
{{0, "Pointer to null terminated string for the path"}, {1, "flags"}},
{{0, "the file decriptor or -1 if an error occurred"}}) {}
void execute() {
- const uint32_t arg0 = BaseSyscall::getArg(RegisterFileType::GPR, 0);
- const uint32_t arg1 = BaseSyscall::getArg(RegisterFileType::GPR, 1);
+ const AInt arg0 = BaseSyscall::getArg(RegisterFileType::GPR, 0);
+ const AInt arg1 = BaseSyscall::getArg(RegisterFileType::GPR, 1);
QByteArray string;
char byte;
unsigned int address = arg0;
@@ -41,7 +41,7 @@ class CloseSyscall : public BaseSyscall {
public:
CloseSyscall() : BaseSyscall("Close", "Close a file", {{0, "the file descriptor to close"}}) {}
void execute() {
- const uint32_t arg0 = BaseSyscall::getArg(RegisterFileType::GPR, 0);
+ const VInt arg0 = BaseSyscall::getArg(RegisterFileType::GPR, 0);
SystemIO::closeFile(arg0);
}
};

Add missing VInt/AInt conversions