Fix various processor issues relating to RV64 instructions
MODIFY
src/processors/RISC-V/rv_alu.h
src/processors/RISC-V/rv_alu.h
@@ -141,10 +141,12 @@ public:
return VT_U(signextend<32>(op1.uValue() << (op2.uValue() & generateBitmask<5>())));
case ALUOp::SRAW:
- return VT_U(signextend<32>(op1.sValue() >> (op2.uValue() & generateBitmask<5>())));
+ return VT_U(
+ signextend<32>(static_cast<int32_t>(op1.uValue()) >> (op2.uValue() & generateBitmask<5>())));
case ALUOp::SRLW:
- return VT_U(signextend<32>(op1.uValue() >> (op2.uValue() & generateBitmask<5>())));
+ return VT_U(
+ signextend<32>(static_cast<uint32_t>(op1.uValue()) >> (op2.uValue() & generateBitmask<5>())));
default:
throw std::runtime_error("Invalid ALU opcode");

MODIFY
src/processors/RISC-V/rv_memory.h
src/processors/RISC-V/rv_memory.h
@@ -35,23 +35,24 @@ public:
wr_width->out >> mem->wr_width;
data_out << [=] {
+ const auto& value = mem->data_out.uValue();
switch (op.uValue()) {
case MemOp::LB:
- return VT_U(signextend<8>(mem->data_out.uValue() & 0xFFUL));
+ return VT_U(signextend<8>(value & 0xFFUL));
case MemOp::LBU:
- return mem->data_out.uValue() & 0xFFUL;
+ return value & 0xFFUL;
case MemOp::LH:
- return VT_U(signextend<16>(mem->data_out.uValue() & 0xFFFFUL));
+ return VT_U(signextend<16>(value & 0xFFFFUL));
case MemOp::LHU:
- return mem->data_out.uValue() & 0xFFFFUL;
- case MemOp::LW:
- return mem->data_out.uValue() & 0xFFFFFFFFUL;
+ return value & 0xFFFFUL;
case MemOp::LWU:
- return VT_U(signextend<32>(mem->data_out.uValue() & 0xFFFFFFFFUL));
+ return value & 0xFFFFFFFFUL;
+ case MemOp::LW:
+ return VT_U(signextend<32>(value));
case MemOp::LD:
- return mem->data_out.uValue();
+ return value;
default:
- return mem->data_out.uValue();
+ return value;
}
};
}

Fix various processor issues relating to RV64 instructions