text: Egad, working with chips is an unfamiliar hassle. It's all OK so long as it's just verilog, but when you finally decide you're done you have to take all of your work off of the unix box, run it through donglified software on NT box A to generate a weird binary file, then run it through software on NT box B to actually download it into the FPGA. That's messed up.
  On the other hand, once the scope is actually attached to the FPGA, it's pretty neat to see all the electrons dance. "See that piece of rock? Today I made it count to 16." Also, any productive hassle is preferable to the non- productivity of sysadminning.
  More perl:
  # nthmost 3, (1, 5, 2, 4, 3) ==> 2
  # (indexed from 0)
  sub nthmost ($@) { my ($n) = shift; return ((sort {$b <=> $a} @_)[$n]); }
  Unfortunately it's O(n log n) even if $n is 0, but oneliners are nice anyway.