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jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_012_test_input.fixed_align_left_true_indent_step_2.vhd | 1 | 3982 |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin
proc_label : process
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
begin end process;
end architecture rtl;
architecture rtl of fifo is
constant avmm_master_null : avmm_master_t := (
(others => '0'),
(others => '0'),
'0',
'0'
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := (
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
constant cons1 : t_type := (1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(G_GENERIC3))
))
);
constant cons1 : t_type := (1 => func1(G_GENERIC1, G_GENERIC2),
2 => func2(func3(func4(
func5(G_GENERIC3))
)));
constant cons1 : t_type :=
(
1 => func1(
G_GENERIC1, G_GENERIC2),
2 => func2(
func3(func4(
func5(
G_GENERIC3
)
)
)
)
);
begin end architecture rtl;
architecture rtl of fifo is
constant cons1 : t_type := '0';
constant cons2 : t_type := '0' and '1'
and '0' or '1';
constant cons2 : t_type := func1(G_GENERIC1, G_GENERIC_2,
func2(G_GENERIC3));
begin end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_020_test_input.fixed.vhd | 1 | 421 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
CASE_LABEL : case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE ;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_003_test_input.fixed_align_left_yes_align_paren_no__smart_tabs.vhd | 1 | 553 |
architecture RTL of ENT is
begin
-- These should pass the check
O_FOO <= (1 => q_foo(63 downto 32),
0 => q_foo(31 downto 0));
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
-- These should fail the check
O_FOO <= (1 => q_foo(63 downto 32),
0 => q_foo(31 downto 0));
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
O_FOO <=
(
1 => func1(std_logic_vector(G_GEN1), G_GEN2),
2 => func2(func3(G_GEN3), G_GEN3),
3 => func4(G_GEN4)
);
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_generate_statement/rule_500_test_input.vhd | 1 | 167 |
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
end generate;
-- Violations below
IF_LABEL : IF a = '1' generate
end generate;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_015_test_input.fixed.vhd | 1 | 599 |
architecture RTL of FIFO is
function func_1 (a : integer) return integer is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
begin
end function func1;
function func_1 (a : integer) return integer is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
begin
end function func1;
procedure proc_1 (a : integer) is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
begin
end procedure proc_1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/loop_statement/rule_300_test_input.fixed.vhd | 2 | 152 |
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop
end loop;
end process;
end;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/sim/wr_data_gen.vhd | 20 | 18946 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_100_test_input.vhd | 1 | 186 |
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end package body;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case_generate_statement/rule_500_test_input.vhd | 1 | 169 |
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
end generate;
GEN_LABEL : CASE expression generate
end generate;
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_100_test_input.vhd | 1 | 815 |
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
-- Fixes follow
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_no_align_paren_yes_align_when_yes_wrap_at_when_yes.vhd | 1 | 2256 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_024_test_input.vhd | 1 | 101 |
entity FIFO is
end entity FIFO;
entity --Comment
--Comment
--Comment
FIFO is
end entity
FIFO;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/record_type_definition/rule_004_test_input.fixed.vhd | 1 | 292 |
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record;
type t_record is record
a : std_logic;
b : std_logic;
end record
;
type t_record is record a : std_logic; b : std_logic; end record
;
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_003_test_input.vhd | 1 | 132 |
package body fifo_pkg is
end package body fifo_pkg;
package body fifo_pkg is
end package body;
package body fifo_pkg is
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package/rule_013_test_input.fixed_upper.vhd | 1 | 71 |
package fifo_pkg IS
end package;
package fifo_pkg IS
end package;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/kintex7/ddr3k7-core/ddr3_read_core.vhd | 1 | 18277 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: ddr3k7-core
-- Module Name: ddr3_read_core - Behavioral
-- Project Name: YARR
-- Target Devices: xc7k160t
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ddr3_read_core is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
Port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
wb_clk_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_stall_o : out STD_LOGIC;
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_req_o : out std_logic;
ddr_gnt_i : in std_logic
);
end ddr3_read_core;
architecture Behavioral of ddr3_read_core is
--------------------------------------
-- Components
--------------------------------------
COMPONENT fifo_29x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(28 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_8x32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_256x16
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(511 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(511 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
--------------------------------------
-- Constants
--------------------------------------
constant c_read_wait_time : unsigned(7 downto 0) := TO_UNSIGNED(15, 8);
constant c_register_shift_size : integer := 8;
--------------------------------------
-- Types
--------------------------------------
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal wb_sel_s : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal wb_cyc_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_we_s : std_logic;
signal wb_adr_s : std_logic_vector(32 - 1 downto 0);
signal wb_dat_s : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal wb_ack_s : std_logic;
signal wb_stall_s : std_logic;
signal wb_rd_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_data_shift_a : data_array;
signal wb_ack_shift_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_addr_shift_a : addr_array;
signal wb_rd_addr_shift_next_a : addr_array;
signal wb_rd_addr_ref_a : addr_array;
signal wb_rd_shifting_s : std_logic;
signal wb_rd_aligned_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_row_a : row_array;
signal wb_rd_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_several_row_s : std_logic;
signal wb_rd_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal wb_rd_shift_flush_s : std_logic;
signal wb_rd_shift_flush_1_s : std_logic;
signal fifo_wb_rd_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_wr_s : std_logic;
signal fifo_wb_rd_addr_rd_s : std_logic;
signal fifo_wb_rd_addr_dout_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal fifo_wb_rd_addr_full_s : std_logic;
signal fifo_wb_rd_addr_almost_full_s : std_logic;
signal fifo_wb_rd_addr_empty_s : std_logic;
signal fifo_wb_rd_mask_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_din_s : std_logic_vector(g_BYTE_ADDR_WIDTH + c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_wr_s : std_logic;
signal fifo_wb_rd_mask_rd_s : std_logic;
signal fifo_wb_rd_mask_dout_s : std_logic_vector(c_register_shift_size-1 downto 0);
signal fifo_wb_rd_mask_full_s : std_logic;
signal fifo_wb_rd_mask_almost_full_s : std_logic;
signal fifo_wb_rd_mask_empty_s : std_logic;
signal fifo_wb_rd_mask_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal fifo_wb_rd_data_din_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_wr_s : std_logic;
signal fifo_wb_rd_data_rd_s : std_logic;
signal fifo_wb_rd_data_dout_s : std_logic_vector(511 downto 0);
signal fifo_wb_rd_data_dout_a : data_array;
signal fifo_wb_rd_data_full_s : std_logic;
signal fifo_wb_rd_data_almost_full_s : std_logic;
signal fifo_wb_rd_data_empty_s : std_logic;
signal fifo_wb_rd_data_rd_data_count_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
--------------------------------------
-- Counter
--------------------------------------
signal wb_read_wait_cnt : unsigned(7 downto 0);
begin
rst_s <= not rst_n_i;
--------------------------------------
-- Wishbone input delay
--------------------------------------
p_wb_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_sel_s <= (others =>'0');
wb_cyc_s <= '0';
wb_stb_s <= '0';
wb_we_s <= '0';
wb_adr_s <= (others =>'0');
wb_dat_s <= (others =>'0');
elsif rising_edge(wb_clk_i) then
wb_sel_s <= wb_sel_i;
wb_cyc_s <= wb_cyc_i;
wb_stb_s <= wb_stb_i;
wb_we_s <= wb_we_i;
wb_adr_s <= wb_adr_i;
wb_dat_s <= wb_dat_i;
end if;
end process p_wb_in;
--------------------------------------
-- Wishbone ouput
--------------------------------------
wb_ack_o <= wb_ack_s;
detection_gen : if (g_NOT_CONSECUTIVE_DETECTION = true) generate
wb_stall_s <= fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s or wb_rd_several_row_s;
end generate;
no_dectection_gen : if (g_NOT_CONSECUTIVE_DETECTION = false) generate
wb_stall_s <= fifo_wb_rd_addr_almost_full_s or fifo_wb_rd_mask_almost_full_s;
end generate;
wb_stall_o <= wb_stall_s;
--------------------------------------
-- Wishbone read
--------------------------------------
p_wb_read : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
wb_read_wait_cnt <= c_read_wait_time;
wb_rd_valid_shift_s <= (others => '0');
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_a(i) <= (others => '0');
end loop;
elsif rising_edge(wb_clk_i) then
wb_rd_shift_flush_1_s <= wb_rd_shift_flush_s;
if (wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '0') then
wb_read_wait_cnt <= c_read_wait_time;
else
if(wb_rd_valid_shift_s /= (wb_rd_valid_shift_s'range => '0')) then
if (wb_read_wait_cnt /= 0) then
wb_read_wait_cnt <= wb_read_wait_cnt - 1;
end if;
end if;
end if;
if(wb_rd_shift_flush_s = '1') then
wb_read_wait_cnt <= c_read_wait_time;
end if;
wb_rd_addr_shift_a <= wb_rd_addr_shift_next_a;
wb_rd_valid_shift_s <= wb_rd_valid_shift_next_s;
end if;
end process p_wb_read;
p_wb_read_rtl : process (wb_read_wait_cnt,wb_rd_addr_shift_a,wb_rd_addr_ref_a,wb_rd_valid_shift_s,wb_rd_shift_flush_s,wb_rd_global_row_s,wb_rd_addr_shift_a,wb_rd_row_a,wb_rd_first_row_s)
begin
fifo_wb_rd_addr_s <= (others => '0');
wb_rd_first_row_s <= (others => '0');
for i in (c_register_shift_size-1) downto 0 loop
if wb_rd_global_row_s(i) = '1' then
fifo_wb_rd_addr_s <= wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ;
wb_rd_first_row_s <= wb_rd_row_a(i);
end if;
end loop;
if((wb_rd_global_row_s /= wb_rd_first_row_s) and (wb_rd_global_row_s /= (wb_rd_global_row_s'range => '0'))) then
wb_rd_several_row_s <= '1';
else
wb_rd_several_row_s <= '0';
end if;
end process p_wb_read_rtl;
wb_rd_shifting_s <= --'0' when wb_rd_several_row_s = '1' else
'1' when wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '0' else--and wb_stall_s = '0' else
'1' when wb_read_wait_cnt = 0 else
'0';
wb_rd_global_row_s <= wb_rd_aligned_s and wb_rd_valid_shift_s;
wb_rd_flush_v_s <= wb_rd_first_row_s;
rd_match_g:for i in 0 to c_register_shift_size-1 generate
wb_rd_aligned_s(i) <= '1' when wb_rd_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else
'0';
rd_row_g:for j in 0 to c_register_shift_size-1 generate
wb_rd_row_a(i)(j) <= '1' when wb_rd_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_rd_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_rd_aligned_s(i) = '1' and wb_rd_aligned_s(j) = '1' and wb_rd_valid_shift_s(i) = '1' and wb_rd_valid_shift_s(j) = '1' else
'0';
end generate;
end generate;
p_wb_read_shift: process (wb_rd_shifting_s,wb_rd_addr_shift_a,wb_rd_valid_shift_s,wb_adr_s,wb_dat_s,wb_sel_s,wb_rd_flush_v_s)
begin
if(wb_rd_shifting_s = '1') then
wb_rd_addr_shift_next_a(c_register_shift_size-1) <= wb_adr_s(g_BYTE_ADDR_WIDTH-1 downto 0);
wb_rd_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_s and wb_stb_s and not wb_we_s;
for i in 1 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i-1) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i-1) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i-1) <= '0';
end if;
end loop;
else
for i in 0 to c_register_shift_size-1 loop
wb_rd_addr_shift_next_a(i) <= wb_rd_addr_shift_a(i);
if wb_rd_flush_v_s(i) = '0' then
wb_rd_valid_shift_next_s(i) <= wb_rd_valid_shift_s(i);
else
wb_rd_valid_shift_next_s(i) <= '0';
end if;
end loop;
end if;
end process p_wb_read_shift;
p_wb_read_data : process(wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= (others => '0');
wb_ack_shift_s(i) <= '0';
end loop;
elsif rising_edge(wb_clk_i) then
if(fifo_wb_rd_data_rd_s = '1') then
for i in 0 to c_register_shift_size-1 loop
wb_rd_data_shift_a(i) <= fifo_wb_rd_data_dout_s(63+(i*64) downto 0+(i*64));
wb_ack_shift_s(i) <= fifo_wb_rd_mask_dout_s(i); -- The data are reversed
end loop;
else
wb_rd_data_shift_a(c_register_shift_size-1) <= (others => '0');
wb_ack_shift_s(c_register_shift_size-1) <= '0';
for i in 0 to c_register_shift_size-2 loop
wb_rd_data_shift_a(i) <= wb_rd_data_shift_a(i+1);
wb_ack_shift_s(i) <= wb_ack_shift_s(i+1);
end loop;
end if;
end if;
end process p_wb_read_data;
fifo_rd_data_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fifo_wb_rd_addr_din_s <= (others => '0');
fifo_wb_rd_mask_din_s <= (others => '0');
fifo_wb_rd_addr_wr_s <= '0';
fifo_wb_rd_mask_wr_s <= '0';
elsif rising_edge(wb_clk_i) then
fifo_wb_rd_addr_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_mask_wr_s <= wb_rd_shift_flush_s;
fifo_wb_rd_addr_din_s <= fifo_wb_rd_addr_s;
fifo_wb_rd_mask_din_s <= fifo_wb_rd_addr_s & wb_rd_valid_shift_s;
end if;
end process;
fifo_wb_rd_data_rd_s <= '1' when wb_ack_shift_s(c_register_shift_size-1 downto 1) = "0000000" and fifo_wb_rd_mask_empty_s = '0' and fifo_wb_rd_data_empty_s = '0' else
'0';
fifo_wb_rd_mask_rd_s <= fifo_wb_rd_data_rd_s;
wb_dat_o <= wb_rd_data_shift_a(0);
wb_ack_s <= wb_ack_shift_s(0);
wb_rd_shift_flush_s <= '1' when wb_rd_flush_v_s /= (wb_rd_flush_v_s'range => '0') else
'0';
fifo_wb_read_addr : fifo_29x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => ddr_ui_clk_i,
din => fifo_wb_rd_addr_din_s,
wr_en => fifo_wb_rd_addr_wr_s,
rd_en => fifo_wb_rd_addr_rd_s,
dout => fifo_wb_rd_addr_dout_s,
full => fifo_wb_rd_addr_full_s,
almost_full => fifo_wb_rd_addr_almost_full_s,
empty => fifo_wb_rd_addr_empty_s
);
fifo_wb_read_mask : fifo_8x32
PORT MAP (
rst => rst_s,
wr_clk => wb_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_mask_din_s(7 downto 0),
wr_en => fifo_wb_rd_mask_wr_s,
rd_en => fifo_wb_rd_mask_rd_s,
dout => fifo_wb_rd_mask_dout_s,
--dout(7 downto 0) => fifo_wb_rd_mask_dout_s,
--dout(36 downto 8) => open,--ddr_wb_rd_mask_addr_dout_do,
full => fifo_wb_rd_mask_full_s,
almost_full => fifo_wb_rd_mask_almost_full_s,
empty => fifo_wb_rd_mask_empty_s,
rd_data_count => fifo_wb_rd_mask_rd_data_count_s
);
fifo_wb_read_data : fifo_256x16
PORT MAP (
rst => rst_s,
wr_clk => ddr_ui_clk_i,
rd_clk => wb_clk_i,
din => fifo_wb_rd_data_din_s,
wr_en => fifo_wb_rd_data_wr_s,
rd_en => fifo_wb_rd_data_rd_s,
dout => fifo_wb_rd_data_dout_s,
full => fifo_wb_rd_data_full_s,
almost_full => fifo_wb_rd_data_almost_full_s,
empty => fifo_wb_rd_data_empty_s,
rd_data_count => fifo_wb_rd_data_rd_data_count_s
);
--------------------------------------
-- DDR CMD
--------------------------------------
ddr_addr_o <= fifo_wb_rd_addr_dout_s;
ddr_cmd_o <= "001";
ddr_cmd_en_o<= fifo_wb_rd_addr_rd_s;
ddr_req_o <= not fifo_wb_rd_addr_empty_s;
--------------------------------------
-- DDR Data in
--------------------------------------
fifo_wb_rd_addr_rd_s <= ddr_rdy_i and (not fifo_wb_rd_addr_empty_s) and (not fifo_wb_rd_data_almost_full_s) and ddr_gnt_i; -- and (not fifo_wb_rd_mask_full_s);
fifo_wb_rd_data_wr_s <= ddr_rd_data_valid_i and ddr_rd_data_end_i;
fifo_wb_rd_data_din_s <= ddr_rd_data_i;
end Behavioral;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/configuration/architecture_012/configuration_test_input.fixed_spaces_gte2.vhd | 2 | 371 | architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en:std_logic;
signal wr_en:std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/use_clause/rule_500_test_input.fixed_upper.vhd | 1 | 108 |
use IEEE.std_logic_1164.all;
use MY_LIB, OTHERLIB.my_math_stuff.multiply;
use YETANOTHERLIB.std_logic;
| gpl-3.0 |
rjarzmik/mips_processor | MIPS_CPU_Syn.vhd | 1 | 3551 | -------------------------------------------------------------------------------
-- Title : MIPS CPU synthesis entity
-- Project : Cache implementations
-------------------------------------------------------------------------------
-- File : MIPS_CPU_Syn.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2017-01-04
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Entity to test the MIPS CPU Synthesis
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-01-04 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
use work.cache_defs.all;
use work.instruction_defs.instr_tag_t;
use work.instruction_defs.INSTR_TAG_FIRST_VALID;
use work.instruction_prediction.prediction_t;
entity MIPS_CPU_Syn is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
NB_REGISTERS_GP : positive := 32; -- r0 to r31
NB_REGISTERS_SPECIAL : positive := 2; -- mflo and mfhi
DEBUG : boolean := false
);
port (
clk : in std_logic;
rst : in std_logic;
-- outer mem interface
o_memory_req : out std_logic;
o_memory_we : out std_logic;
o_memory_addr : out addr_t;
i_memory_rdata : in data_t;
o_memory_wdata : out data_t;
i_memory_done : in std_logic;
-- Temprorary Data Memory interface
o_mem_addr : out addr_t;
i_mem_rd_valid : in std_logic;
i_mem_rd_data : in data_t;
o_mem_wr_en : out std_logic;
o_mem_word_width : out std_logic;
o_mem_wr_data : out data_t;
i_mem_wr_ack : in std_logic
);
end entity MIPS_CPU_Syn;
architecture str of MIPS_CPU_Syn is
signal cls_creq : cache_request_t;
signal cls_cresp : cache_response_t;
begin -- architecture str
MIPS_CPU_1 : entity work.MIPS_CPU
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
NB_REGISTERS_GP => NB_REGISTERS_GP,
NB_REGISTERS_SPECIAL => NB_REGISTERS_SPECIAL)
port map (
clk => clk,
rst => rst,
o_creq => cls_creq,
i_cresp => cls_cresp,
o_mem_addr => o_mem_addr,
i_mem_rd_valid => i_mem_rd_valid,
i_mem_rd_data => i_mem_rd_data,
o_mem_wr_en => o_mem_wr_en,
o_mem_word_width => o_mem_word_width,
o_mem_wr_data => o_mem_wr_data,
i_mem_wr_ack => i_mem_wr_ack);
cls : entity work.cache_line_streamer
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATAS_PER_LINE_WIDTH => DATAS_PER_LINE_WIDTH)
port map (
clk => clk,
rst => rst,
i_creq => cls_creq,
o_cresp => cls_cresp,
o_memory_req => o_memory_req,
o_memory_we => o_memory_we,
o_memory_addr => o_memory_addr,
o_memory_wdata => o_memory_wdata,
i_memory_rdata => i_memory_rdata,
i_memory_done => i_memory_done);
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_035_test_input_smart_tabs.fixed_indent_4.vhd | 1 | 449 |
architecture RTL of FIFO is
begin
process
begin
a <= b; -- level 2
ab <= xy; -- level 2
-- level 2
if (a = b) then -- level 2
z <= y; -- level 3
-- level 2
elsif (a + b -c = z) then -- level 2
z <= x; -- level 3
end if; -- level 2
end process; -- level 1
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable/rule_005_test_input.fixed.vhd | 2 | 413 |
architecture RTL of FIFO is
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
begin
end process;
end architecture RTL;
-- Violations below
architecture RTL of FIFO is
shared variable shar_var1 : integer;
shared variable shar_var1 : integer;
begin
process
variable var1 : integer;
variable var1 : integer;
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/iteration_scheme/rule_101_test_input.vhd | 1 | 172 |
architecture rtl of fifo is
begin
process begin
for x in (11 downto 0) loop end loop;
for x in (11 downto 0) loop end loop;
end process;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_018_test_input.fixed_add.vhd | 1 | 274 |
architecture RTL of FIFO is
begin
process is begin end process;
PROC_LABEL : process is
begin
end process PROC_LABEL;
-- Violations below
PROC_LABEL : process is
begin
end process PROC_LABEL;
process is
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_021_test_input.fixed_require_blank.vhd | 1 | 329 |
architecture RTL of FIFO is
begin
process
begin
end process;
process (a, b)
begin
end process;
process (a, b) is
begin
end process;
-- Violations below
process
begin
end process;
process (a, b)
begin
end process;
process (a, b) is
begin
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/package_body/rule_601_test_input.vhd | 1 | 101 |
package body pkg_fifo is
end package body pkg_fifo;
package body fifo is
end package body fifo;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_020_test_input.vhd | 2 | 719 |
architecture RTl of FIFO is
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
-- Failures below
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_014_test_input.vhd | 1 | 562 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_028_test_input.vhd | 1 | 247 |
architecture RTL of ENT is
begin
end ARCHITECTURE RTL;
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end architecture Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end Architecture;
| gpl-3.0 |
lvd2/zxevo | fpga/base_trdemu/sd_iface_contention_test/sim_models/T80_MCode.vhd | 12 | 53716 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0235 : Added IM 2 fix by Mike Johnson
--
-- 0238 : Added NoRead signal
--
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
--
-- 0242 : Fixed I/O instruction timing, cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(7) = '0'; -- NZ
when "001" => return F(7) = '1'; -- Z
when "010" => return F(4) = '0'; -- NC
when "011" => return F(4) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then
I_DJNZ <= '1';
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RLD <= '1';
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RRD <= '1';
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI, RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
-- note B is decremented AFTER being put on the bus
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
--IncDec_16 <= "0010";
IncDec_16 <= "0110";
else
--IncDec_16 <= "1010";
IncDec_16 <= "1110";
end if;
TStates <= "100";
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
-- note B is decremented BEFORE being put on the bus.
-- mikej fix for hl inc
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110"; -- mikej
else
IncDec_16 <= "1110"; -- mikej
end if;
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
| gpl-3.0 |
rjarzmik/mips_processor | instruction_tag.vhd | 1 | 4598 | -------------------------------------------------------------------------------
-- Title : Instruction tagging
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : instruction_tag.vhd.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-07
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-07 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
package instruction_defs is
-- Smallest 2 power with at least : None, Fetch, Decode/Issue, Execute, Memory, Writeback
constant NB_PIPELINE_STAGES : natural := 16;
type instr_tag_t is record
valid : boolean;
tag : natural range 0 to NB_PIPELINE_STAGES - 1;
is_branch : boolean;
is_ja : boolean;
is_jr : boolean;
is_branch_taken : boolean;
end record;
constant INSTR_TAG_NONE : instr_tag_t := (
tag => 0, valid => false,
is_branch => false, is_ja => false, is_jr => false,
is_branch_taken => false);
constant INSTR_TAG_FIRST_VALID : instr_tag_t := (
tag => 0, valid => true,
is_branch => false, is_ja => false, is_jr => false,
is_branch_taken => false);
function get_instr_change_is_branch(itag : instr_tag_t;
new_is_branch : boolean)
return instr_tag_t;
function get_instr_change_is_ja(itag : instr_tag_t;
new_is_ja : boolean)
return instr_tag_t;
function get_instr_change_is_jr(itag : instr_tag_t;
new_is_jr : boolean)
return instr_tag_t;
function get_instr_change_tag(itag : instr_tag_t;
new_tag : natural) return instr_tag_t;
function get_next_instr_tag(itag : in instr_tag_t;
step : positive) return instr_tag_t;
function get_instr_change_is_branch_taken(itag : instr_tag_t;
new_is_branch_taken : boolean)
return instr_tag_t;
end package instruction_defs;
package body instruction_defs is
function get_instr_change_is_branch(itag : instr_tag_t;
new_is_branch : boolean)
return instr_tag_t is
variable o : instr_tag_t;
begin
o := itag;
o.is_branch := new_is_branch;
return o;
end function get_instr_change_is_branch;
function get_instr_change_is_ja(itag : instr_tag_t;
new_is_ja : boolean)
return instr_tag_t is
variable o : instr_tag_t;
begin
o := itag;
o.is_ja := new_is_ja;
return o;
end function get_instr_change_is_ja;
function get_instr_change_is_jr(itag : instr_tag_t;
new_is_jr : boolean)
return instr_tag_t is
variable o : instr_tag_t;
begin
o := itag;
o.is_jr := new_is_jr;
return o;
end function get_instr_change_is_jr;
function get_instr_change_is_branch_taken(itag : instr_tag_t;
new_is_branch_taken : boolean)
return instr_tag_t is
variable o : instr_tag_t;
begin
o := itag;
o.is_branch_taken := new_is_branch_taken;
return o;
end function get_instr_change_is_branch_taken;
function get_instr_change_tag(itag : instr_tag_t;
new_tag : natural) return instr_tag_t is
variable o : instr_tag_t;
begin
o := itag;
o.tag := new_tag;
return o;
end function get_instr_change_tag;
function get_next_instr_tag(itag : in instr_tag_t;
step : positive) return instr_tag_t is
variable o : instr_tag_t;
begin
o := itag;
o.tag := (o.tag + step) mod NB_PIPELINE_STAGES;
return o;
end function get_next_instr_tag;
end package body instruction_defs;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_expressions/rule_500_test_input.vhd | 2 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' WHEN rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' WHEN rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_002_test_input.fixed.vhd | 4 | 662 |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_505_test_input.fixed_upper.vhd | 1 | 169 |
architecture RTL of FIFO is
begin
block_label : block is begin end BLOCK block_label;
BLOCK_LABEL : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure/rule_004_test_input.vhd | 1 | 660 |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/rule_group/test_input.config_3.actual.vhd | 2 | 1053 |
library ieee;
use IEEE.STD_LOGIC_1164.all;
entity BLAH is
generic (
G_BLAH : std_logic
);
port (
I_INPUT : in std_logic;
O_OUTPUT : out std_logic;
IO_INOUT : inout std_logic
);
end entity BLAH;
ARCHITECTURE RTL of BLAH is
constant CON_A : std_logic;
signal SIG_A : std_logic;
component COMP_1 is
generic (
G_GEN_1 : integer
);
port (
I_INPUT : in integer;
O_OUTPUT : out std_logic;
IO_INOUT : inout integer
);
end component COMP_1;
begin
proc_label : process (Ab, Cd, Ef) is
variable VAR_A : std_logic_vector(7 downto 0);
begin
a <= b or c and d xor e;
end process proc_label;
u_inst : component MY_COMP
generic map (
G_GEN_1 => 1
)
port map (
I_INPUT => W_sig_1
);
end architecture RTL;
package SOME_PKG is
procedure PROC_1;
function FUNC_1 Return integer;
end package SOME_PKG;
package body SOME_PKG_BODY is
procedure PROC_1 is
begin
end procedure PROC_1;
end package body SOME_PKG_BODY;
| gpl-3.0 |
Yarr/Yarr-fw | syn/spec/octa_fei4_revA/board_pkg.vhd | 5 | 193 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
| gpl-3.0 |
Yarr/Yarr-fw | syn/spec/quad_fei4_revA/board_pkg.vhd | 5 | 193 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package board_pkg is
constant c_TX_CHANNELS : integer := 8;
constant c_RX_CHANNELS : integer := 8;
end board_pkg;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure_call/rule_301_test_input.vhd | 3 | 637 |
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
postponed wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
wr_en(a, b);
end process;
-- Violations below
procedure_call_label : postponed wr_en(a, b);
procedure_call_label : postponed wr_en(a, b);
postponed wr_en(a, b);
postponed wr_en(a, b);
wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
procedure_call_label : wr_en(a, b);
wr_en(a, b);
wr_en(a, b);
end process;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure_call/rule_300_test_input.vhd | 3 | 637 |
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
postponed wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
wr_en(a, b);
end process;
-- Violations below
procedure_call_label : postponed wr_en(a, b);
procedure_call_label : postponed wr_en(a, b);
postponed wr_en(a, b);
postponed wr_en(a, b);
wr_en(a, b);
wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
procedure_call_label : wr_en(a, b);
wr_en(a, b);
wr_en(a, b);
end process;
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case_generate_alternative/rule_500_test_input.vhd | 1 | 207 |
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
when choice =>
end generate;
GEN_LABEL : case expression generate
WHEN choice =>
end generate;
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/Debouncer.vhd | 1 | 974 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Debouncer is
Port ( Clk : in STD_LOGIC;
Button : in STD_LOGIC;
Dout : out STD_LOGIC);
end Debouncer;
architecture Behavioral of Debouncer is
signal Counter,nCounter : STD_LOGIC_VECTOR (23 downto 0) := x"000000";
signal ButtonHistory,nButtonHistory : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal nextHistory : STD_LOGIC := '0';
begin
nCounter <= x"FFFFFF" when Counter=x"FFFFFF" and Button='1' else
x"000000" when Counter=x"000000" and Button='0' else
Counter+1 when Button='1' else Counter-1;
nextHistory <= '0' when Counter=x"000000" else '1';
nButtonHistory <= nextHistory & ButtonHistory(1);
Dout <= '1' when ButtonHistory="01" else '0';
process (Clk) begin
if (rising_edge(Clk)) then
Counter <= nCounter;
ButtonHistory <= nButtonHistory;
end if;
end process;
end Behavioral;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_017_test_input.fixed.vhd | 1 | 681 |
architecture RTl of FIFO is
component fifo is
generic (
gen1 : integer := 0; -- Comment
gen2 : integer := 1; -- Comment
gen3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
-- Failures below
component fifo is
generic (
gen1 : integer := 0; -- Comment
gen2 : integer := 1; -- Comment
gen3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/function/rule_100_test_input.fixed.vhd | 1 | 1549 |
architecture RTL of FIFO is
function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
pure function func1 (a : integer) return integer is
begin
end;
impure function func1 (a : integer) return integer is
begin
end;
-- Fixes follow
function func1 return integer is
begin
end;
function func1 return integer is
begin
end;
function func1 return integer is
begin
end;
function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
pure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
impure function func1 return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
function func1 (a : integer) return integer is
begin
end;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_005_test_input.fixed.vhd | 1 | 279 |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
COMPONENT fifo is --Some Comemnt
-- Some COmment
end component fifo;
Component fifo is--Other comment
-- Some Comment
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/ranges/rule_002_test_input.vhd | 2 | 1049 |
-- Nothing should fail in this entity
entity ENT1 is
generic (
G_GENERIC1 : std_logic_vector(3 downto 0);
G_GENERIC2 : std_logic_vector(0 to 256)
);
port (
P_PORT1 : std_logic_vector(15 downto 6); -- DOWNTO
P_PORT2 : std_logic_vector(56 to 132)
);
end entity ENT1;
-- Everything should fail in this entity
entity ENT1 is
generic (
G_GENERIC1 : std_logic_vector(3 downTo 0);
G_GENERIC2 : std_logic_vector(0 TO 256)
);
port (
P_PORT1 : std_logic_vector(15 Downto 6);
P_PORT2 : std_logic_vector(56 tO 132)
);
end entity ENT1;
architecture ARCH of ENT1 is
constant c_const1 : std_logic_vector(3 DOWNTO 0); -- downto
constant c_const2 : std_logic_vector(3 downto 0);
constant c_const3 : std_logic_vector(345 To 670);
constant c_const4 : std_logic_vector(345 to 670);
signal w_sig1 : std_logic_vector(50 dOWnto 45);
signal w_sig2 : std_logic_vector(50 downto 45);
signal w_sig3 : std_logic_vector(46 TO 345);
signal w_sig4 : std_logic_vector(46 to 345);
begin
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_021_test_input.fixed_lower.vhd | 4 | 221 |
architecture RTL of ENT is
begin
end RTL;
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_002_test_input.fixed.vhd | 1 | 255 |
library ieee;
library ieee;
library ieee;
library ieee;
library ieee;
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
-- Comment with tab
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/block/rule_205_test_input.fixed.vhd | 1 | 175 |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
end block;
a <= b;
BLOCK_LABEL : block is
begin
end block;
a <= b;
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/architecture/rule_020_test_input.fixed_upper.vhd | 1 | 221 |
architecture RTL of ENT IS
begin
end RTL;
architecture RTL of ent IS
begin
end rtl;
architecture RTL of Ent IS
begin
end Rtl;
architecture RTL of ENT IS
begin
end;
architecture RTL of ENT IS
begin
end architecture;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/attribute_declaration/rule_100_test_input.fixed.vhd | 1 | 174 |
architecture RTL of FIFO is
attribute max_delay : time;
-- Violations below
attribute max_delay : time;
attribute max_delay : time;
begin
end architecture RTL;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/signal/rule_015_test_input.vhd | 1 | 1262 |
architecture ARCH of ENTITY is
signal sig1, sig2, sig3,
sig4, sig5, sig6 : std_logic;
signal siga, sigb,
sigc,
sigd,
sige,
sigf
: std_logic; -- This is a comment
-- Test variations of a single signal declaration
signal sig1 : std_logic;
signal sig1 : std_logic
;
signal sig1 :
std_logic
;
signal sig1
:
std_logic
;
signal
sig1
:
std_logic
;
-- Test variations of a two signal declarations
signal sig1, sig2 : std_logic;
signal sig1, sig2 : std_logic
;
signal sig1, sig2 :
std_logic
;
signal sig1, sig2
:
std_logic
;
signal sig1,
sig2
:
std_logic
;
signal sig1
,
sig2
:
std_logic
;
signal
sig1
,
sig2
:
std_logic
;
signal sig1, sig2 : std_logic; -- Comma, should not induce a failure
-- This should pass
signal foo : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);
signal foo, bar, mine : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);
signal ar,ai,ar3,ai3: STD_LOGIC_VECTOR (width-1 downto 0);
signal br1,bi1,br,bi,br2,bi2: STD_LOGIC_VECTOR (width-1 downto 0);
begin
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_013_test_input.fixed.vhd | 1 | 397 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
| gpl-3.0 |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd | 2 | 35790 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : ddr3_ctrl_spec_bank3_64b_32b.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr3_ctrl_spec_bank3_64b_32b is
generic
(
C3_P0_MASK_SIZE : integer := 8;
C3_P0_DATA_PORT_SIZE : integer := 64;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end ddr3_ctrl_spec_bank3_64b_32b;
architecture arc of ddr3_ctrl_spec_bank3_64b_32b is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"20";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"02";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"20";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 1;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(191 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_p1_cmd_clk,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_p1_wr_clk,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_p1_rd_clk,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_002_test_input.fixed.vhd | 11 | 212 |
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
| gpl-3.0 |
Yarr/Yarr-fw | ip-cores/spartan6/clk_gen.vhd | 1 | 6925 | -- file: clk_gen.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
-- CLK_OUT3____80.000______0.000______50.0______263.295____213.982
-- CLK_OUT4____40.000______0.000______50.0______306.416____213.982
-- CLK_OUT5____40.000_____90.000______50.0______306.416____213.982
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________40____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_gen is
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLK_40_90 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clk_gen;
architecture xilinx of clk_gen is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_gen,clk_wiz_v3_6,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=PLL_BASE,num_out_clk=5,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4 : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_40_IN;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 16,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DIVIDE => 16,
CLKOUT4_PHASE => 90.000,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 25.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => RESET,
-- Input clock control
CLKFBIN => CLKFB_IN,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLKFB_OUT <= clkfbout;
CLK_640 <= clkout0;
CLK_160 <= clkout1;
CLK_80 <= clkout2;
CLK_40 <= clkout3;
CLK_40_90 <= clkout4;
end xilinx;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_601_test_input.vhd | 1 | 492 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
W_GEN_1 => 3,
GEN_2 => 4,
WR_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_test_input.fixed_align_left_no_align_paren_yes_align_when_yes_wrap_at_when_yes_align_else_yes.vhd | 1 | 2531 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_generate_statement/rule_502_test_input.vhd | 1 | 253 |
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
elsif b = '1' generate
else generate
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
ELSIF b = '1' generate
else generate
end generate;
end;
| gpl-3.0 |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_006_test_input.vhd | 1 | 88 |
entity FIFO is
end entity;
entity FIFO IS
end entity;
entity FIFO Is
end entity;
| gpl-3.0 |
rjarzmik/mips_processor | instruction_prediction.vhd | 1 | 2641 | -------------------------------------------------------------------------------
-- Title : Instruction predicting
-- Project :
-------------------------------------------------------------------------------
-- File : Instruction_prediction.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-07
-- Last update: 2016-12-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-07 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
package instruction_prediction is
constant NB_PREDICTIONS : positive := 4;
constant ADDR_WIDTH : integer := 32;
subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0);
type prediction_t is record
valid : boolean;
pc : addr_t;
next_pc : addr_t;
is_ja_jr : boolean;
is_branch : boolean;
take_branch : natural range 0 to 3; -- 0:never, 1:no, 2:yes, 3:always
end record;
type predictions_t is array(0 to NB_PREDICTIONS - 1) of prediction_t;
function is_prediction_hit(i_address : addr_t;
predictions : predictions_t) return boolean;
function get_prediction(i_address : addr_t;
predictions : predictions_t) return prediction_t;
end package instruction_prediction;
package body instruction_prediction is
function is_prediction_hit(i_address : addr_t;
predictions : predictions_t)
return boolean is
variable found : boolean := false;
begin
for i in predictions'range loop
found := found or (predictions(i).valid and predictions(i).pc = i_address);
end loop;
return found;
end function is_prediction_hit;
function get_prediction(i_address : addr_t;
predictions : predictions_t)
return prediction_t is
variable found : prediction_t;
begin
for i in predictions'range loop
if predictions(i).valid and predictions(i).pc = i_address then
found := predictions(i);
end if;
end loop;
return found;
end function get_prediction;
end package body instruction_prediction;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/async_fifo/vhdl_source/gray_code_pkg.vhd | 4 | 3209 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : gray_code_pkg
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: gray code package, only the functions needed for the
-- asynchronous fifo
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gray_code_pkg is
---------------------------------------------------------------------------
-- type
---------------------------------------------------------------------------
type t_gray is array (natural range <>) of std_logic;
---------------------------------------------------------------------------
-- conversion function
---------------------------------------------------------------------------
function to_unsigned (arg : t_gray) return unsigned;
---------------------------------------------------------------------------
-- arithmetic function
---------------------------------------------------------------------------
function increment (arg : t_gray) return t_gray;
end gray_code_pkg;
-------------------------------------------------------------------------------
-- package body
-------------------------------------------------------------------------------
package body gray_code_pkg is
function to_unsigned (arg : t_gray) return unsigned is
variable mybin : unsigned(arg'range);
variable temp : std_logic;
begin
for i in arg'low to arg'high-1 loop
temp := '0';
for j in i+1 to arg'high loop
temp := temp xor arg(j);
end loop;
mybin(i) := arg(i) xor temp;
end loop;
mybin(mybin'high) := arg(arg'high);
return mybin;
end to_unsigned;
function increment (arg : t_gray) return t_gray is
alias xarg : t_gray((arg'length-1) downto 0) is arg;
variable grayinc : t_gray(xarg'range);
variable temp : std_logic;
begin
for i in xarg'range loop
-- rule: high downto i: xnor
-- i-1: and
-- i-2 downto 0: and not
temp := '0';
if i = xarg'high then
temp := xarg(i) xor xarg(i-1);
else
for j in i to arg'high loop
temp := temp xor xarg(j);
end loop;
temp := not(temp);
if i >= 1 then
temp := temp and xarg(i-1);
end if;
end if;
if i >= 2 then
for j in 0 to i-2 loop
temp := temp and not(xarg(j));
end loop;
end if;
grayinc(i) := xarg(i) xor temp;
end loop;
return grayinc;
end increment;
end;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/busses/vhdl_source/mem_bus_pkg.vhd | 3 | 4603 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mem_bus_pkg is
type t_mem_req is record
tag : std_logic_vector(7 downto 0);
request : std_logic;
read_writen : std_logic;
size : unsigned(1 downto 0); -- +1 for reads only
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_mem_resp is record
data : std_logic_vector(7 downto 0);
rack : std_logic;
rack_tag : std_logic_vector(7 downto 0);
dack_tag : std_logic_vector(7 downto 0);
count : unsigned(1 downto 0);
end record;
constant c_mem_req_init : t_mem_req := (
tag => X"00",
request => '0',
read_writen => '1',
size => "00",
address => (others => '0'),
data => X"00" );
constant c_mem_resp_init : t_mem_resp := (
data => X"00",
rack => '0',
rack_tag => X"00",
dack_tag => X"00",
count => "00" );
type t_mem_req_array is array(natural range <>) of t_mem_req;
type t_mem_resp_array is array(natural range <>) of t_mem_resp;
-- 8 bits memory bus with burst --
type t_mem_burst_req is record
request : std_logic;
read_writen : std_logic;
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
data_push : std_logic;
data_pop : std_logic;
byte_en : std_logic;
end record;
type t_mem_burst_resp is record
data : std_logic_vector(7 downto 0);
ready : std_logic; -- can accept requests
rdata_av : std_logic; -- indicates if there is data in read fifo
wdata_full : std_logic; -- indicates if there is space in write fifo
end record;
constant c_mem_burst_req_init : t_mem_burst_req := (
request => '0',
read_writen => '1',
address => (others => '0'),
data => X"00",
data_push => '0',
data_pop => '0',
byte_en => '1' );
constant c_mem_burst_resp_init : t_mem_burst_resp := (
data => X"00",
ready => '0',
rdata_av => '0',
wdata_full => '0' );
-- 16 bits memory bus with burst --
type t_mem_burst_16_req is record
request : std_logic;
request_tag : std_logic_vector(7 downto 0);
read_writen : std_logic;
address : unsigned(25 downto 0);
data : std_logic_vector(15 downto 0);
byte_en : std_logic_vector(1 downto 0);
data_push : std_logic;
data_pop : std_logic;
end record;
type t_mem_burst_16_resp is record
data : std_logic_vector(15 downto 0);
data_tag : std_logic_vector(7 downto 0);
ready : std_logic;
rdata_av : std_logic;
wdata_full : std_logic;
end record;
constant c_mem_burst_16_req_init : t_mem_burst_16_req := (
request => '0',
request_tag => X"00",
read_writen => '1',
address => (others => '0'),
data => X"0000",
data_push => '0',
data_pop => '0',
byte_en => "11" );
-- 32 bits memory bus --
type t_mem_burst_32_req is record
request : std_logic;
request_tag : std_logic_vector(7 downto 0);
read_writen : std_logic;
address : unsigned(25 downto 0);
data : std_logic_vector(31 downto 0);
byte_en : std_logic_vector(3 downto 0);
data_push : std_logic;
data_pop : std_logic;
end record;
type t_mem_burst_32_resp is record
data : std_logic_vector(31 downto 0);
data_tag : std_logic_vector(7 downto 0);
ready : std_logic;
rdata_av : std_logic;
wdata_full : std_logic;
end record;
constant c_mem_burst_32_req_init : t_mem_burst_32_req := (
request => '0',
request_tag => X"00",
read_writen => '1',
address => (others => '0'),
data => X"00000000",
data_push => '0',
data_pop => '0',
byte_en => "1111" );
end package;
package body mem_bus_pkg is
end package body;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/cart_slot/vhdl_source/slot_server_v4.vhd | 3 | 27534 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.cart_slot_pkg.all;
entity slot_server_v4 is
generic (
g_tag_slot : std_logic_vector(7 downto 0) := X"08";
g_tag_reu : std_logic_vector(7 downto 0) := X"10";
g_ram_base_reu : unsigned(27 downto 0) := X"1000000"; -- should be on 16M boundary, or should be limited in size
g_ram_base_cart : unsigned(27 downto 0) := X"0F70000"; -- should be on a 64K boundary
g_rom_base_cart : unsigned(27 downto 0) := X"0F80000"; -- should be on a 512K boundary
g_control_read : boolean := true;
g_command_intf : boolean := true;
g_ram_expansion : boolean := true;
g_extended_reu : boolean := false;
g_sampler : boolean := false;
g_implement_sid : boolean := true;
g_sid_voices : natural := 3;
g_vic_copper : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : inout std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
PHI2 : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
DMAn : out std_logic := '1';
BA : in std_logic := '0';
ROMLn : in std_logic;
ROMHn : in std_logic;
GAMEn : inout std_logic;
EXROMn : inout std_logic;
RWn : inout std_logic;
ADDRESS : inout std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
-- other hardware pins
BUFFER_ENn : out std_logic;
buttons : in std_logic_vector(2 downto 0);
cart_led_n : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
-- debug
freezer_state : out std_logic_vector(1 downto 0);
-- audio output
sid_pwm_left : out std_logic := '0';
sid_pwm_right : out std_logic := '0';
samp_pwm_left : out std_logic := '0';
samp_pwm_right : out std_logic := '0';
-- timing output
phi2_tick : out std_logic;
c64_stopped : out std_logic;
-- master on memory bus
memctrl_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- slave on io bus
io_req : in t_io_req;
io_resp : out t_io_resp );
end slot_server_v4;
architecture structural of slot_server_v4 is
signal phi2_tick_i : std_logic;
signal phi2_recovered : std_logic;
signal vic_cycle : std_logic;
signal do_sample_addr : std_logic;
signal do_sample_io : std_logic;
signal do_io_event : std_logic;
signal do_probe_end : std_logic;
signal timing_inhibit : std_logic;
signal slave_dout : std_logic_vector(7 downto 0);
signal slave_dtri : std_logic := '0';
signal master_dout : std_logic_vector(7 downto 0);
signal master_dtri : std_logic := '0';
signal address_tri_l : std_logic;
signal address_tri_h : std_logic;
signal address_out : std_logic_vector(15 downto 0);
signal rwn_tri : std_logic;
signal rwn_out : std_logic;
signal control : t_cart_control;
signal status : t_cart_status;
signal allow_serve : std_logic;
-- interface with freezer (cartridge) logic
signal serve_enable : std_logic := '0'; -- from cartridge emulation logic
signal serve_vic : std_logic := '0';
signal serve_rom : std_logic := '0'; -- ROML or ROMH
signal serve_io1 : std_logic := '0'; -- IO1n
signal serve_io2 : std_logic := '0'; -- IO2n
signal allow_write : std_logic := '0';
-- kernal replacement logic
signal kernal_area : std_logic := '0';
signal kernal_probe : std_logic := '0';
signal kernal_addr_out : std_logic := '0';
signal force_ultimax : std_logic := '0';
signal cpu_write : std_logic;
signal epyx_timeout : std_logic;
signal reu_dma_n : std_logic := '1'; -- direct from REC
signal cmd_if_freeze : std_logic := '0'; -- same function as reu_dma_n, but then from CI
signal mask_buttons : std_logic := '0';
signal reset_button : std_logic;
signal freeze_button : std_logic;
signal actual_c64_reset : std_logic;
signal dma_n : std_logic := '1';
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal exrom_n : std_logic := '1';
signal game_n : std_logic := '1';
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal unfreeze : std_logic;
signal freeze_trig : std_logic;
signal freeze_act : std_logic;
signal io_req_dma : t_io_req;
signal io_resp_dma : t_io_resp := c_io_resp_init;
signal io_req_peri : t_io_req;
signal io_resp_peri : t_io_resp := c_io_resp_init;
signal io_req_sid : t_io_req;
signal io_resp_sid : t_io_resp := c_io_resp_init;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_req_cmd : t_io_req;
signal io_resp_cmd : t_io_resp := c_io_resp_init;
signal io_req_copper : t_io_req;
signal io_resp_copper : t_io_resp := c_io_resp_init;
signal io_req_samp_cpu : t_io_req;
signal io_resp_samp_cpu : t_io_resp := c_io_resp_init;
signal dma_req_io : t_dma_req;
signal dma_resp_io : t_dma_resp := c_dma_resp_init;
signal dma_req_reu : t_dma_req;
signal dma_resp_reu : t_dma_resp := c_dma_resp_init;
signal dma_req_copper : t_dma_req;
signal dma_resp_copper : t_dma_resp := c_dma_resp_init;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp := c_dma_resp_init;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp := c_slot_resp_init;
signal slot_resp_reu : t_slot_resp := c_slot_resp_init;
signal slot_resp_cart : t_slot_resp := c_slot_resp_init;
signal slot_resp_sid : t_slot_resp := c_slot_resp_init;
signal slot_resp_cmd : t_slot_resp := c_slot_resp_init;
signal slot_resp_samp : t_slot_resp := c_slot_resp_init;
signal mem_req_slot : t_mem_req := c_mem_req_init;
signal mem_resp_slot : t_mem_resp := c_mem_resp_init;
signal mem_req_reu : t_mem_req := c_mem_req_init;
signal mem_resp_reu : t_mem_resp := c_mem_resp_init;
signal mem_req_samp : t_mem_req := c_mem_req_init;
signal mem_resp_samp : t_mem_resp := c_mem_resp_init;
-- signal mem_req_trace : t_mem_req;
-- signal mem_resp_trace : t_mem_resp;
signal mem_rack_slot : std_logic;
signal mem_dack_slot : std_logic;
signal sid_sample_left : signed(17 downto 0);
signal sid_sample_right : signed(17 downto 0);
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
begin
reset_button <= buttons(0) when control.swap_buttons='0' else buttons(2);
freeze_button <= buttons(2) when control.swap_buttons='0' else buttons(0);
i_split_64K: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_peri, -- 4040000
reqs(1) => io_req_dma, -- 4050000
resps(0) => io_resp_peri,
resps(1) => io_resp_dma );
i_bridge: entity work.io_to_dma_bridge
port map (
clock => clock,
reset => reset,
c64_stopped => status.c64_stopped,
io_req => io_req_dma,
io_resp => io_resp_dma,
dma_req => dma_req_io,
dma_resp => dma_resp_io );
i_split_8K: entity work.io_bus_splitter
generic map (
g_range_lo => 13,
g_range_hi => 15,
g_ports => 5 )
port map (
clock => clock,
req => io_req_peri,
resp => io_resp_peri,
reqs(0) => io_req_regs, -- 4040000
reqs(1) => io_req_sid, -- 4042000
reqs(2) => io_req_cmd, -- 4044000
reqs(3) => io_req_copper, -- 4046000
reqs(4) => io_req_samp_cpu, -- 4048000
resps(0) => io_resp_regs,
resps(1) => io_resp_sid,
resps(2) => io_resp_cmd,
resps(3) => io_resp_copper,
resps(4) => io_resp_samp_cpu );
i_registers: entity work.cart_slot_registers
generic map (
g_rom_base => g_rom_base_cart,
g_ram_base => g_ram_base_cart,
-- g_control_read => g_control_read,
g_ram_expansion => g_ram_expansion )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_timing: entity work.slot_timing
port map (
clock => clock,
reset => reset,
-- Cartridge pins
PHI2 => PHI2,
BA => BA,
serve_vic => serve_vic,
serve_enable => serve_enable,
serve_inhibit => status.c64_stopped,
allow_serve => allow_serve,
timing_addr => control.timing_addr_valid,
edge_recover => control.phi2_edge_recover,
phi2_tick => phi2_tick_i,
phi2_recovered => phi2_recovered,
clock_det => status.clock_detect,
vic_cycle => vic_cycle,
inhibit => timing_inhibit,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_probe_end => do_probe_end,
do_io_event => do_io_event );
mem_req_slot.tag <= g_tag_slot;
mem_rack_slot <= '1' when mem_resp_slot.rack_tag = g_tag_slot else '0';
mem_dack_slot <= '1' when mem_resp_slot.dack_tag = g_tag_slot else '0';
i_slave: entity work.slot_slave
port map (
clock => clock,
reset => reset,
-- Cartridge pins
RSTn => RSTn,
IO1n => IO1n,
IO2n => IO2n,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
BA => BA,
ADDRESS => ADDRESS,
DATA_in => DATA,
DATA_out => slave_dout,
DATA_tri => slave_dtri,
-- interface with memory controller
mem_req => mem_req_slot.request,
mem_rwn => mem_req_slot.read_writen,
mem_wdata => mem_req_slot.data,
mem_size => mem_req_slot.size,
mem_rack => mem_rack_slot,
mem_dack => mem_dack_slot,
mem_rdata => mem_resp_slot.data,
mem_count => mem_resp.count,
-- mem_addr comes from cartridge logic
-- synchronized outputs
reset_out => actual_c64_reset,
-- timing inputs
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
do_probe_end => do_probe_end,
-- interface with freezer (cartridge) logic
allow_serve => allow_serve,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
-- kernal emulation
kernal_enable => control.kernal_enable,
kernal_probe => kernal_probe,
kernal_area => kernal_area,
force_ultimax => force_ultimax,
cpu_write => cpu_write,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp,
-- interface with hardware
BUFFER_ENn => BUFFER_ENn );
i_master: entity work.slot_master_v4
port map (
clock => clock,
reset => reset,
-- Cartridge pins
DMAn => dma_n,
BA => BA,
RWn_in => RWn,
RWn_out => rwn_out,
RWn_tri => rwn_tri,
ADDRESS_out => address_out,
ADDRESS_tri_h => address_tri_h,
ADDRESS_tri_l => address_tri_l,
DATA_in => DATA,
DATA_out => master_dout,
DATA_tri => master_dtri,
-- timing inputs
vic_cycle => vic_cycle,
phi2_recovered => phi2_recovered,
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
reu_dma_n => reu_dma_n,
cmd_if_freeze => cmd_if_freeze,
-- request from the cpu to do a cycle on the cart bus
dma_req => dma_req,
dma_resp => dma_resp,
-- system control
stop_cond => control.c64_stop_mode,
c64_stop => control.c64_stop,
c64_stopped => status.c64_stopped );
i_freeze: entity work.freezer
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
button_freeze => freeze_button,
cpu_cycle_done => do_io_event,
cpu_write => cpu_write,
freezer_state => freezer_state,
unfreeze => unfreeze,
freeze_trig => freeze_trig,
freeze_act => freeze_act );
i_cart_logic: entity work.all_carts_v4
generic map (
g_rom_base => std_logic_vector(g_rom_base_cart),
g_ram_base => std_logic_vector(g_ram_base_cart) )
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
c64_reset => control.c64_reset,
ethernet_enable => control.eth_enable,
freeze_trig => freeze_trig,
freeze_act => freeze_act,
unfreeze => unfreeze,
cart_logic => control.cartridge_type,
cart_kill => control.cartridge_kill,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp_cart,
mem_addr => mem_req_slot.address,
serve_enable => serve_enable,
serve_vic => serve_vic,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
kernal_area => kernal_area,
kernal_enable => control.kernal_enable,
irq_n => irq_n,
nmi_n => nmi_n,
exrom_n => exrom_n,
game_n => game_n,
CART_LEDn => cart_led_n );
r_sid: if g_implement_sid generate
begin
-- i_trce: entity work.sid_trace
-- generic map (
-- g_mem_tag => X"CE" )
-- port map (
-- clock => clock,
-- reset => actual_c64_reset,
--
-- addr => unsigned(slot_addr(6 downto 0)),
-- wren => sid_write,
-- wdata => io_wdata,
--
-- phi2_tick => phi2_tick_i,
--
-- io_req => io_req_trace,
-- io_resp => io_resp_trace,
--
-- mem_req => mem_req_trace,
-- mem_resp => mem_resp_trace );
i_sid: entity work.sid_peripheral
generic map (
g_num_voices => g_sid_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_sid,
io_resp => io_resp_sid,
slot_req => slot_req,
slot_resp => slot_resp_sid,
start_iter => phi2_tick_i,
sample_left => sid_sample_left,
sample_right => sid_sample_right );
i_pdm_sid_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_left'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_left,
dac_out => sid_pwm_left );
i_pdm_sid_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_right'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_right,
dac_out => sid_pwm_right );
end generate;
g_cmd: if g_command_intf generate
i_cmd: entity work.command_interface
port map (
clock => clock,
reset => reset,
-- C64 side interface
slot_req => slot_req,
slot_resp => slot_resp_cmd,
freeze => cmd_if_freeze,
-- io interface for local cpu
io_req => io_req_cmd, -- we get an 8K range
io_resp => io_resp_cmd );
end generate;
g_reu: if g_ram_expansion generate
begin
i_reu: entity work.reu
generic map (
g_extended => g_extended_reu,
g_ram_base => g_ram_base_reu,
g_ram_tag => g_tag_reu )
port map (
clock => clock,
reset => actual_c64_reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp_reu,
-- system interface
phi2_tick => do_io_event,
reu_dma_n => reu_dma_n,
size_ctrl => control.reu_size,
enable => control.reu_enable,
-- memory interface
mem_req => mem_req_reu,
mem_resp => mem_resp_reu,
dma_req => dma_req_reu,
dma_resp => dma_resp_reu );
end generate;
r_copper: if g_vic_copper generate
i_copper: entity work.copper
port map (
clock => clock,
reset => reset,
irq_n => IRQn,
phi2_tick => phi2_tick_i,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
io_req => io_req_copper,
io_resp => io_resp_copper,
dma_req => dma_req_copper,
dma_resp => dma_resp_copper,
slot_req => slot_req,
slot_resp => open ); -- never required, just snoop!
end generate;
r_sampler: if g_sampler generate
signal local_io_req : t_io_req := c_io_req_init;
signal local_io_resp : t_io_resp;
signal io_req_samp : t_io_req;
signal io_resp_samp : t_io_resp;
signal irq_samp : std_logic;
begin
i_io_bridge: entity work.slot_to_io_bridge
generic map (
g_io_base => X"48000", -- dont care in this context
g_slot_start => "100100000",
g_slot_stop => "111111111" )
port map (
clock => clock,
reset => reset,
enable => control.sampler_enable,
irq_in => irq_samp,
slot_req => slot_req,
slot_resp => slot_resp_samp,
io_req => local_io_req,
io_resp => local_io_resp );
i_io_arb_sampler: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => io_req_samp_cpu,
reqs(1) => local_io_req,
resps(0) => io_resp_samp_cpu,
resps(1) => local_io_resp,
req => io_req_samp,
resp => io_resp_samp );
i_sampler: entity work.sampler
generic map (
g_num_voices => 8 )
port map (
clock => clock,
reset => actual_c64_reset,
io_req => io_req_samp,
io_resp => io_resp_samp,
mem_req => mem_req_samp,
mem_resp => mem_resp_samp,
irq => irq_samp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => open );
i_pdm_samp_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_L,
dac_out => samp_pwm_left );
i_pdm_samp_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_R,
dac_out => samp_pwm_right );
end generate;
slot_resp <= or_reduce(slot_resp_reu & slot_resp_cart & slot_resp_sid & slot_resp_cmd & slot_resp_samp);
p_probe_address_delay: process(clock)
variable kernal_probe_d : std_logic_vector(2 downto 0) := (others => '0');
begin
if rising_edge(clock) then
kernal_addr_out <= kernal_probe_d(0);
kernal_probe_d := kernal_probe & kernal_probe_d(kernal_probe_d'high downto 1);
end if;
end process;
ADDRESS(7 downto 0) <= address_out(7 downto 0) when address_tri_l='1' else (others => 'Z');
ADDRESS(12 downto 8) <= address_out(12 downto 8) when address_tri_h='1' else (others => 'Z');
ADDRESS(15 downto 13) <= "101" when (kernal_addr_out='1' and kernal_probe='1') else
address_out(15 downto 13) when address_tri_h='1' else (others => 'Z');
RWn <= rwn_out when rwn_tri='1' else 'Z';
DATA <= slave_dout when (slave_dtri='1') else
master_dout when (master_dtri='1') else (others => 'Z');
-- open drain outputs
irq_oc <= '0' when irq_n='0' or slot_resp.irq='1' else '1';
nmi_oc <= '0' when (control.c64_nmi='1') or (nmi_n='0') else '1';
rst_oc <= '0' when (reset_button='1' and status.c64_stopped='0' and mask_buttons='0') or
(control.c64_reset='1') else '1';
dma_oc <= '0' when (dma_n='0' or kernal_probe='1') else '1';
-- dma_oc <= '0' when (dma_n='0') else '1';
process(control, serve_enable, exrom_n, game_n, force_ultimax, kernal_probe)
begin
exrom_oc <= '1';
game_oc <= '1';
if (force_ultimax = '1') or (control.c64_ultimax = '1') then
game_oc <= '0';
elsif kernal_probe = '1' then
game_oc <= '0';
exrom_oc <= '0';
else
if (serve_enable='1' and exrom_n='0') then
exrom_oc <= '0';
end if;
if (serve_enable='1' and game_n='0') then
game_oc <= '0';
end if;
end if;
end process;
irq_push: entity work.oc_pusher port map(clock => clock, sig_in => irq_oc, oc_out => IRQn);
nmi_push: entity work.oc_pusher port map(clock => clock, sig_in => nmi_oc, oc_out => NMIn);
rst_push: entity work.oc_pusher port map(clock => clock, sig_in => rst_oc, oc_out => RSTn);
dma_push: entity work.oc_pusher port map(clock => clock, sig_in => dma_oc, oc_out => DMAn);
exr_push: entity work.oc_pusher port map(clock => clock, sig_in => exrom_oc, oc_out => EXROMn);
gam_push: entity work.oc_pusher port map(clock => clock, sig_in => game_oc, oc_out => GAMEn);
-- arbitration
i_dma_arb: entity work.dma_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => dma_req_io,
reqs(1) => dma_req_reu,
reqs(2) => dma_req_copper,
resps(0) => dma_resp_io,
resps(1) => dma_resp_reu,
resps(2) => dma_resp_copper,
req => dma_req,
resp => dma_resp );
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_slot,
reqs(1) => mem_req_reu,
reqs(2) => mem_req_samp,
-- reqs(3) => mem_req_trace,
resps(0) => mem_resp_slot,
resps(1) => mem_resp_reu,
resps(2) => mem_resp_samp,
-- resps(3) => mem_resp_trace,
req => mem_req,
resp => mem_resp );
-- Delay the inhibit one clock cycle, because our
-- arbited introduces one clock cycle delay as well.
process(clock)
begin
if rising_edge(clock) then
memctrl_inhibit <= timing_inhibit;
end if;
end process;
phi2_tick <= phi2_tick_i;
c64_stopped <= status.c64_stopped;
end structural;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/iec_interface/vhdl_source/iec_processor_io.vhd | 3 | 12997 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 260/111/136/1
library work;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity iec_processor_io is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
end iec_processor_io;
architecture structural of iec_processor_io is
signal proc_reset : std_logic;
signal enable : std_logic;
-- irq
signal irq_event : std_logic;
signal irq_enable : std_logic;
signal irq_status : std_logic;
-- instruction ram interface
signal instr_addr : unsigned(8 downto 0);
signal instr_en : std_logic;
signal instr_data : std_logic_vector(31 downto 0);
-- software fifo interface
signal up_fifo_get : std_logic;
signal up_fifo_put : std_logic;
signal up_fifo_din : std_logic_vector(8 downto 0);
signal up_fifo_dout : std_logic_vector(8 downto 0);
signal up_fifo_empty : std_logic;
signal up_fifo_full : std_logic;
signal up_dav : std_logic;
signal up_space : std_logic;
signal down_fifo_flush : std_logic;
signal down_fifo_empty : std_logic;
signal down_fifo_full : std_logic;
signal down_fifo_get : std_logic;
signal down_fifo_put : std_logic;
signal down_fifo_din : std_logic_vector(8 downto 0);
signal down_fifo_dout : std_logic_vector(8 downto 0);
signal down_dav : std_logic;
signal down_space : std_logic;
signal ram_en : std_logic;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_sel : std_logic;
signal reg_rdata : std_logic_vector(7 downto 0);
begin
i_proc: entity work.iec_processor
generic map (
g_mhz => g_mhz )
port map (
clock => clock,
reset => proc_reset,
-- instruction ram interface
instr_addr => instr_addr,
instr_en => instr_en,
instr_data => instr_data(29 downto 0),
-- software fifo interface
up_fifo_put => up_fifo_put,
up_fifo_din => up_fifo_din,
up_fifo_full => up_fifo_full,
down_fifo_empty => down_fifo_empty,
down_fifo_get => down_fifo_get,
down_fifo_dout => down_fifo_dout,
down_fifo_flush => down_fifo_flush,
irq_event => irq_event,
clk_o => clk_o,
clk_i => clk_i,
data_o => data_o,
data_i => data_i,
atn_o => atn_o,
atn_i => atn_i,
srq_o => srq_o,
srq_i => srq_i );
-- i_inst_ram: entity work.dpram
-- generic map (
-- g_width_bits => 32,
-- g_depth_bits => 11,
-- g_read_first_a => false,
-- g_read_first_b => false,
-- g_storage => "block" )
-- port map (
-- a_clock => clock,
-- a_address => instr_addr,
-- a_rdata => instr_data,
-- a_wdata => X"00",
-- a_en => instr_en,
-- a_we => '0',
--
-- b_clock => clock,
-- b_address => req.address(10 downto 0),
-- b_rdata => ram_rdata,
-- b_wdata => req.data,
-- b_en => ram_en,
-- b_we => req.write );
i_ram: RAMB16_S9_S36
generic map (
INIT_00 => X"00406F0019C00011002000000000004119C000101E5000111F5000101F80B200",
INIT_01 => X"098012000A8012000040A10000409C002A800D001F800D0000409C0029800B00",
INIT_02 => X"2A80690009801E0000200000000000423680060039C000501F50001119C04601",
INIT_03 => X"1B80AF0019C0C8111F80690019C046012C80180000409C0000406F0019C00011",
INIT_04 => X"004029001E50000C00200000000000431E50000C19C050011F5000111E500010",
INIT_05 => X"2C80290000403100001000001F50000C188030103D802E00001000001F806900",
INIT_06 => X"1E5000101B80AF0019C3E82019C064012C80390019C000221F50001000700000",
INIT_07 => X"1E50001019C050011F50001019C05001005000111E50001019C0280119C00022",
INIT_08 => X"1F50001019C05001025000111E50001019C050011F50001019C0500101500011",
INIT_09 => X"045000111E50001019C050011F50001019C05001035000111E50001019C05001",
INIT_0A => X"19C050011F50001019C05001055000111E50001019C050011F50001019C05001",
INIT_0B => X"19C05001075000111E50001019C050011F50001019C05001065000111E500010",
INIT_0C => X"19C05A011B80AF0019C3E82019C002011E5000101F50001119C050011F500010",
INIT_0D => X"1A806F001F80B2001F5000111F5000101F50001200200000000000DD00700000",
INIT_0E => X"19C3E8101F50001119C046011E5000112C8079001B50000C19C0C8101F500011",
INIT_0F => X"1B80AF001550000119C0C81119C0C8101B80AF001550000019C0C8111B80AF00",
INIT_10 => X"1B80AF001550000319C0C81119C0C8101B80AF001550000219C0C81119C0C810",
INIT_11 => X"1B80AF001550000519C0C81119C0C8101B80AF001550000419C0C81119C0C810",
INIT_12 => X"1B80AF001550000719C0C81119C0C8101B80AF001550000619C0C81119C0C810",
INIT_13 => X"00200000000000452C80A00000300000007000001E50001119C0140119C0C810",
INIT_14 => X"007000001E50000A1F5000093880A84A007000001E5000093880A45F00700000",
INIT_15 => X"000000EE007000001E5000091F50000A3880AE2A007000001E50000A3880AB3F",
INIT_16 => X"1880B94D1880D7573D80B200001000001F500008009000001F80690000200000",
INIT_17 => X"1B80D40019C3E82019C014011F5000111E5000101E5000121E5000081F80B200",
INIT_18 => X"1880694B1880CB4C1880B94D1F80C000004031001E50000C1D80C50000100000",
INIT_19 => X"1F5000121F80C00019C06401004029001F50001200200000000000E51880CF4A",
INIT_1A => X"002000001F80690000200000000000E61F80180019C005011F50001019C01E01",
INIT_1B => X"00300000000000550010000000200000000000DA3480EE0039C000331E500008",
INIT_1C => X"0040F900004120000040F900004120000040F9001F50001019C000221E500010",
INIT_1D => X"00200000000000DE1F80D7000060000019C0003300200000000000AD00412500",
INIT_1E => X"2780B2000060000019C00033004102000040F9001F50001119C000111E500011",
INIT_1F => X"0060000000200000000000AE0070000019C0040119C3E83019C000331F80D700",
INIT_20 => X"1F50001319C0080135500001345000031E50001319C015011F80B20019C00033",
INIT_21 => X"355000043450000619C00801355000053450000719C008013550000034500002",
INIT_22 => X"0041120000700000004102000041020000410200004102000070000000300000",
INIT_23 => X"0070000000411200004112000041120000411200004112000041120000411200",
INIT_24 => X"0041120000411700004117000070000000411700004117000041170000411700",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000700000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST" )
port map (
DOA => ram_rdata,
ADDRA => std_logic_vector(req.address(10 downto 0)),
CLKA => clock,
DIA => req.data,
DIPA => "0",
ENA => ram_en,
SSRA => '0',
WEA => req.write,
DOB => instr_data,
ADDRB => std_logic_vector(instr_addr),
CLKB => clock,
DIB => X"00000000",
DIPB => X"0",
ENB => instr_en,
SSRB => '0',
WEB => '0' );
-- i_up_fifo: entity work.srl_fifo
-- generic map (
-- Width => 9,
-- Depth => 15, -- 15 is the maximum
-- Threshold => 13 )
-- port map (
-- clock => clock,
-- reset => reset,
-- GetElement => up_fifo_get,
-- PutElement => up_fifo_put,
-- FlushFifo => '0',
-- DataIn => up_fifo_din,
-- DataOut => up_fifo_dout,
-- SpaceInFifo => up_space,
-- AlmostFull => open,
-- DataInFifo => up_dav);
--
-- up_fifo_empty <= not up_dav;
-- up_fifo_full <= not up_space;
i_up_fifo: entity work.sync_fifo
generic map (
g_depth => 2048,
g_data_width => 9,
g_threshold => 500,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => up_fifo_get,
wr_en => up_fifo_put,
din => up_fifo_din,
dout => up_fifo_dout,
flush => '0',
full => up_fifo_full,
almost_full => open,
empty => up_fifo_empty,
count => open );
i_down_fifo: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15, -- 15 is the maximum
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => down_fifo_get,
PutElement => down_fifo_put,
FlushFifo => down_fifo_flush,
DataIn => down_fifo_din,
DataOut => down_fifo_dout,
SpaceInFifo => down_space,
AlmostFull => open,
DataInFifo => down_dav);
down_fifo_empty <= not down_dav;
down_fifo_full <= not down_space;
process(clock)
begin
if rising_edge(clock) then
ram_sel <= '0';
reg_rdata <= (others => '0');
proc_reset <= not enable;
resp.ack <= '0';
if req.read='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
ram_sel <= req.address(11);
case req.address(3 downto 0) is
when X"0" =>
reg_rdata <= X"23"; -- version
when X"1" =>
reg_rdata(0) <= down_fifo_empty;
reg_rdata(1) <= down_fifo_full;
when X"2" =>
reg_rdata(0) <= up_fifo_empty;
reg_rdata(1) <= up_fifo_full;
reg_rdata(7) <= up_fifo_dout(8);
when X"6"|X"8"|X"9"|X"A"|X"B" =>
reg_rdata <= up_fifo_dout(7 downto 0);
when X"7" =>
reg_rdata <= "0000000" & up_fifo_dout(8);
when X"C" =>
reg_rdata <= "0000000" & irq_status;
when others => null;
end case;
elsif req.write='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
if req.address(11)='0' then
case req.address(3 downto 0) is
when X"3" =>
proc_reset <= '1';
enable <= req.data(0);
when X"C" =>
irq_status <= '0';
irq_enable <= req.data(0);
when others =>
null;
end case;
end if;
end if;
if irq_event='1' then
irq_status <= '1';
end if;
resp.irq <= irq_enable and irq_status;
if reset='1' then
proc_reset <= '1';
enable <= '0';
end if;
end if;
end process;
resp.data <= ram_rdata when ram_sel='1' else reg_rdata;
down_fifo_put <= '1' when req.write='1' and req.address(11)='0' and req.address(3 downto 1) = "10" else '0';
up_fifo_get <= '1' when req.read='1' and req.address(11)='0' and ((req.address(3 downto 0) = "0110") or (req.address(3 downto 2) = "10")) else '0';
down_fifo_din <= req.address(0) & req.data;
ram_en <= (req.write or req.read) and req.address(11);
end structural;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/cs8900a/vhdl_source/cs8900a_bus.vhd | 3 | 7543 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
| gpl-3.0 |
J-Rios/VHDL_Modules | 3.Peripherals/UART/UART_Tx.vhd | 1 | 2603 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity UART_TX is
Generic
(
DBIT : integer := 8; -- # Data BITS
SB_TICK : integer := 16 -- # Stop BITS Tick (1 -> 16, 1.5 -> 24, 2 -> 32)
);
Port
(
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TX_START : in STD_LOGIC;
S_TICK : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR (7 downto 0);
TX_DONE_TICK : out STD_LOGIC;
TX : out STD_LOGIC
);
end UART_TX;
-------------------------------------------------------------------------
architecture Behavioral of UART_TX is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type;
signal s_reg, s_next: unsigned(3 downto 0);
signal n_reg, n_next: unsigned(2 downto 0);
signal b_reg, b_next: std_logic_vector(7 downto 0);
signal TX_reg, TX_next: std_logic;
begin
-- FSMD state & data registers
process(CLK,RESET)
begin
if RESET='1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
TX_reg <= '1';
elsif (CLK'event and CLK='1') then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
TX_reg <= TX_next;
end if;
end process;
-- Next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,S_TICK, TX_reg,TX_START,DIN)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
TX_next <= TX_reg;
TX_DONE_TICK <= '0';
case state_reg is
when idle =>
TX_next <= '1';
if TX_START='1' then
state_next <= start;
s_next <= (others=>'0');
b_next <= DIN;
end if;
when start =>
TX_next <= '0';
if (S_TICK = '1') then
if s_reg=15 then
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
TX_next <= b_reg(0);
if (S_TICK = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= '0' & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
state_next <= stop;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
TX_next <= '1';
if (S_TICK = '1') then
if s_reg=(SB_TICK-1) then
state_next <= idle;
TX_DONE_TICK <= '1';
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
TX <= TX_reg;
end Behavioral;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/usb2/vhdl_sim/ulpi_phy_bfm.vhd | 10 | 10740 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end ulpi_phy_bfm;
architecture gideon of ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : integer := 0;
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_nxt_d : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
type t_data8 is array(natural range <>) of std_logic_vector(7 downto 0);
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
signal irq_status : std_logic_vector(7 downto 0) := X"00";
signal func_select : std_logic_vector(7 downto 0) := X"00";
signal intf_control : std_logic_vector(7 downto 0) := X"00";
signal otg_control : std_logic_vector(7 downto 0) := X"00";
signal scratch : std_logic_vector(7 downto 0) := X"00";
signal power : std_logic := '0';
signal power_level : std_logic_vector(1 downto 0) := "00";
signal pid : std_logic_vector(3 downto 0) := X"F";
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
function to_std(a : boolean) return std_logic is
begin
if (a) then
return '1';
else
return '0';
end if;
end function;
begin
crc_sync <= '1' when (state = idle) else '0';
irq_status(3) <= to_std(status_in(3 downto 2) = "01");
irq_status(2) <= status_in(3);
irq_status(1) <= to_std(status_in(3 downto 2) = "11");
status_in(3 downto 2) <= power_level;
process(power)
begin
if power'event then
if power = '1' then
power_level <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
elsif power = '0' then
power_level <= transport "11",
"10" after 3 us,
"01" after 6 us,
"00" after 10 us;
else
power_level <= "00";
end if;
end if;
end process;
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
variable a : integer;
begin
a := to_integer(unsigned(addr));
case a is
when 4 =>
func_select <= data;
if data(4 downto 0) = "10000" then -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
elsif data(4 downto 3) ="00" then -- normal operation
status_in(1 downto 0) <= data(1 downto 0); -- for the time being
end if;
when 7 =>
intf_control <= data;
when 8 =>
intf_control <= intf_control or data;
when 9 =>
intf_control <= intf_control and not data;
when 10 =>
otg_control <= data;
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
power <= '1';
else -- power off
report "Power Off";
power <= '0';
end if;
when 22 =>
scratch <= data;
when 23 =>
scratch <= scratch or data;
when 24 =>
scratch <= scratch and not data;
when others =>
null;
end case;
end procedure;
variable receive_buffer : t_data8(0 to 127);
variable transmit_buffer : t_data8(0 to 127);
variable receive_length : integer := 0;
variable transmit_length : integer := 0;
procedure determine_response is
begin
if receive_buffer(0) = X"43" then -- data0 packet
transmit_buffer(0) := X"D2";
transmit_length := 1;
do_send <= '1';
end if;
end procedure;
impure function read_ulpi_register(addr: std_logic_vector(5 downto 0)) return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
variable a : integer;
begin
a := to_integer(unsigned(addr));
ret := X"00";
case a is
when 19 | 20 =>
ret := irq_status;
when 0 =>
ret := X"24";
when 1|2 =>
ret := X"04";
when 4|5|6 =>
ret := func_select;
when 7|8|9 =>
ret := intf_control;
when 10|11|12 =>
ret := otg_control;
when 22|23|24 =>
ret := scratch;
when others =>
null;
end case;
return ret;
end function;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
counter <= 0;
byte_count := transmit_length;
elsif ulpi_dir_i = '0' then
pid <= ULPI_DATA(3 downto 0);
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
receive_length := 0;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
address := ULPI_DATA(5 downto 0);
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= transmit_buffer(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
report "Received packet with length = " & integer'image(receive_length);
determine_response;
else
if (ulpi_nxt_i = '1') and (pid /= X"0") then
receive_buffer(receive_length) := ULPI_DATA;
receive_length := receive_length + 1;
end if;
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= read_ulpi_register(address);
state <= idle;
when others =>
state <= idle;
end case;
ulpi_nxt_d <= ulpi_nxt_i;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => ulpi_nxt_d,
data_in => ULPI_DATA,
crc => data_crc );
end gideon;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/io/iec_interface/vhdl_sim/iec_processor_tb.vhd | 5 | 5679 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
| gpl-3.0 |
shaolinbertrand/Processador_N.I.N.A | somador.vhd | 1 | 293 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity somador is port(
x,y : in std_logic_vector(15 downto 0);
result : out std_logic_vector(15 downto 0)
);
end somador;
architecture hardware of somador is begin
result <= x + y;
end hardware;
| gpl-3.0 |
timofonic/1541UltimateII | fpga/ip/busses/vhdl_bfm/io_bus_bfm_pkg.vhd | 4 | 3912 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.io_bus_pkg.all;
package io_bus_bfm_pkg is
type t_io_bus_bfm_object;
type p_io_bus_bfm_object is access t_io_bus_bfm_object;
type t_io_bfm_command is ( e_io_none, e_io_read, e_io_write );
type t_io_bus_bfm_object is record
next_bfm : p_io_bus_bfm_object;
name : string(1 to 256);
command : t_io_bfm_command;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable io_bus_bfms : p_io_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
------------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
end io_bus_bfm_pkg;
package body io_bus_bfm_pkg is
procedure register_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_io_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if io_bus_bfms = null then -- first entry
io_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := io_bus_bfms;
io_bus_bfms := pntr;
end if;
end register_io_bus_bfm;
procedure bind_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
variable p : p_io_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := io_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_io_bus_bfm;
------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_read;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
data := io.data;
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_write;
io.data := data;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
| gpl-3.0 |
J-Rios/VHDL_Modules | 1.Combinational/Gate_OR.vhd | 1 | 427 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
entity Gate_OR is
Port
(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end Gate_OR;
----------------------------------------------------------------------------------
architecture Behavioral of Gate_OR is
begin
Z <= A or B;
end Behavioral;
| gpl-3.0 |
rogerioag/gcg | samples/unidade_a2/templates/decl_signals.vhd | 5 | 101 | -- Signals declaration.\n
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;\n
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/Fault_injector.vhd | 13 | 1277 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity fault_injector is
generic(DATA_WIDTH : integer := 32);
port(
data_in: in std_logic_vector (DATA_WIDTH-1 downto 0);
address: in std_logic_vector(integer(ceil(log2(real(DATA_WIDTH))))-1 downto 0);
sta_0: in std_logic;
sta_1: in std_logic;
data_out: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end fault_injector;
architecture behavior of fault_injector is
signal mask: std_logic_vector (DATA_WIDTH-1 downto 0);
begin
-- data_in | sta_0 | sta_1 | data_out
-- --------|--------|--------|----------
-- 0 | 0 | 0 | 0
-- 1 | 0 | 0 | 1
-- X | 0 | 1 | 1
-- X | 1 | 0 | 0
process (address) begin
mask <= (others => '0');
mask(to_integer(unsigned(address))) <= '1';
end process;
Gen_faulty:
for i in 0 to DATA_WIDTH-1 generate
data_out(i) <= (not mask(i) and data_in(i)) or (mask(i) and not sta_0 and not sta_1 and data_in(i)) or (mask(i) and sta_1 and not sta_0) ;
--data_out(i) <= data_in(i);
end generate;
end; | gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/Testbenches/immortal_slack_monitor_tb.vhd | 3 | 4459 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/21/2017 05:18:09 PM
-- Design Name:
-- Module Name: immortal_slack_monitor_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity immortal_slack_monitor_tb is
end immortal_slack_monitor_tb;
architecture Behavioral of immortal_slack_monitor_tb is
constant tck_period : time := 10 ns;
constant HALF_SEPARATOR : time := 2*tck_period;
constant FULL_SEPARATOR : time := 8*tck_period;
signal toSI : STD_LOGIC;
signal fromSO : STD_LOGIC;
signal SE : STD_LOGIC;
signal CE : STD_LOGIC;
signal UE : STD_LOGIC;
signal TCK : STD_LOGIC;
signal RST : STD_LOGIC;
signal SEL : STD_LOGIC;
signal toF : STD_LOGIC;
signal toC : STD_LOGIC;
signal slack_control : std_logic_vector (2 downto 0);
signal slack_data : std_logic_vector (31 downto 0);
component immortal_slack_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end component;
begin
slack_monitor : immortal_slack_monitor_instrument
port map (
-- IJTAG connection
TCK => TCK,
RST => RST,
SEL => SEL,
SI => toSI,
SE => SE,
UE => UE,
CE => CE,
SO => fromSO,
toF => toF,
toC => toC,
-- Monitor connections
control => slack_control,
data => slack_data
);
ijtag_shift_proc: process
-- Generate a number of TCK ticks
procedure tck_tick (number_of_tick : in positive) is
begin
for i in 1 to number_of_tick loop
TCK <= '0';
wait for TCK_period/2;
TCK <= '1';
wait for TCK_period/2;
end loop;
end procedure tck_tick;
procedure tck_halftick_high is
begin
TCK <= '1';
wait for TCK_period/2;
end procedure tck_halftick_high;
procedure tck_halftick_low is
begin
TCK <= '0';
wait for TCK_period/2;
end procedure tck_halftick_low;
-- Shifts in specified data (Capture -> Shift -> Update)
procedure shift_data (data : in std_logic_vector) is
begin
--Capture phase
CE <= '1';
tck_tick(1);
CE <= '0';
--Shift phase
SE <= '1';
for i in data'range loop
toSI <= data(i);
tck_tick(1);
end loop;
SE <= '0';
-- Update phase
--tck_tick(1);
tck_halftick_low;
UE <= '1';
tck_halftick_high;
tck_halftick_low;
UE <= '0';
tck_halftick_high;
end procedure shift_data;
-- Returns all zeroes std_logic_vector of specified size
function all_zeroes (number_of_zeroes : in positive) return std_logic_vector is
variable zero_array : std_logic_vector(0 to number_of_zeroes-1);
begin
for i in zero_array'range loop
zero_array(i) := '0';
end loop;
return zero_array;
end function all_zeroes;
begin
slack_data <= "01010101010101010101010101001010";
UE <= '0';
CE <= '0';
SE <= '0';
toSI <= '0';
-- Reset iJTAG chain and Instruments
RST <= '1';
wait for tck_period;
RST <= '0';
SEL <= '1';
tck_tick(4);
shift_data("11100"&"00000"&"0"&"1"&"1"&"0000000000000001111"); -- shift in threshold H without update
tck_tick(4);
slack_data <= "00101010101010101010101010101010";
tck_tick(4);
wait;
end process;
end Behavioral;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/mlite_pack.vhd | 3 | 26281 | ---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/Arbiter_in_one_hot_checkers.vhd | 10 | 23865 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_in_one_hot_checkers is
port (
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic;
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
X_N, X_E, X_W, X_S, X_L :in std_logic;
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in_one_hot_checkers;
architecture behavior of Arbiter_in_one_hot_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= X_N & X_E & X_W & X_S & X_L;
-- Checkers
--checked
process (state, Requests, state_in)
begin
--if ( (state = North or state = East or state = West or state = South or state = Local or state = IDLE) and Requests = "00000" and state_in /= state ) then
if (Requests = "00000" and state_in /= state ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_Req_N <= '1';
else
err_IDLE_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = IDLE and req_X_N = '1' and X_N = '0' ) then
err_IDLE_grant_N <= '1';
else
err_IDLE_grant_N <= '0';
end if;
end process;
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_Req_N <= '1';
else
err_North_Req_N <= '0';
end if;
end process;
process (state, req_X_N, X_N)
begin
if ( state = North and req_X_N = '1' and X_N = '0' ) then
err_North_grant_N <= '1';
else
err_North_grant_N <= '0';
end if;
end process;
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_Req_E <= '1';
else
err_East_Req_E <= '0';
end if;
end process;
process (state, req_X_E, X_E)
begin
if ( state = East and req_X_E = '1' and X_E = '0' ) then
err_East_grant_E <= '1';
else
err_East_grant_E <= '0';
end if;
end process;
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_Req_W <= '1';
else
err_West_Req_W <= '0';
end if;
end process;
process (state, req_X_W, X_W)
begin
if ( state = West and req_X_W = '1' and X_W = '0' ) then
err_West_grant_W <= '1';
else
err_West_grant_W <= '0';
end if;
end process;
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_Req_S <= '1';
else
err_South_Req_S <= '0';
end if;
end process;
process (state, req_X_S, X_S)
begin
if ( state = South and req_X_S = '1' and X_S = '0' ) then
err_South_grant_S <= '1';
else
err_South_grant_S <= '0';
end if;
end process;
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_Req_L <= '1';
else
err_Local_Req_L <= '0';
end if;
end process;
process (state, req_X_L, X_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and X_L = '0' ) then
err_Local_grant_L <= '1';
else
err_Local_grant_L <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_Req_E <= '1';
else
err_IDLE_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_IDLE_grant_E <= '1';
else
err_IDLE_grant_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_Req_E <= '1';
else
err_North_Req_E <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, X_E)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_North_grant_E <= '1';
else
err_North_grant_E <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_Req_W <= '1';
else
err_East_Req_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, X_W)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_East_grant_W <= '1';
else
err_East_grant_W <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_Req_S <= '1';
else
err_West_Req_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, X_S)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_West_grant_S <= '1';
else
err_West_grant_S <= '0';
end if;
end process;
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_Req_L <= '1';
else
err_South_Req_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, X_L)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_South_grant_L <= '1';
else
err_South_grant_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_Req_N <= '1';
else
err_Local_Req_N <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, X_N)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_Local_grant_N <= '1';
else
err_Local_grant_N <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_Req_W <= '1';
else
err_IDLE_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_IDLE_grant_W <= '1';
else
err_IDLE_grant_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_Req_W <= '1';
else
err_North_Req_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and X_W = '0' ) then
err_North_grant_W <= '1';
else
err_North_grant_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_Req_S <= '1';
else
err_East_Req_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and X_S = '0' ) then
err_East_grant_S <= '1';
else
err_East_grant_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_Req_L <= '1';
else
err_West_Req_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and X_L = '0' ) then
err_West_grant_L <= '1';
else
err_West_grant_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_Req_N <= '1';
else
err_South_Req_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and X_N = '0' ) then
err_South_grant_N <= '1';
else
err_South_grant_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_Req_E <= '1';
else
err_Local_Req_E <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and X_E = '0' ) then
err_Local_grant_E <= '1';
else
err_Local_grant_E <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_Req_S <= '1';
else
err_IDLE_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_IDLE_grant_S <= '1';
else
err_IDLE_grant_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_Req_S <= '1';
else
err_North_Req_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0') then
err_North_grant_S <= '1';
else
err_North_grant_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_Req_L <= '1';
else
err_East_Req_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0') then
err_East_grant_L <= '1';
else
err_East_grant_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_Req_N <= '1';
else
err_West_Req_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0') then
err_West_grant_N <= '1';
else
err_West_grant_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_Req_E <= '1';
else
err_South_Req_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0') then
err_South_grant_E <= '1';
else
err_South_grant_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_Req_W <= '1';
else
err_Local_Req_W <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0') then
err_Local_grant_W <= '1';
else
err_Local_grant_W <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_Req_L <= '1';
else
err_IDLE_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_IDLE_grant_L <= '1';
else
err_IDLE_grant_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_Req_L <= '1';
else
err_North_Req_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, X_L)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
X_L = '0' ) then
err_North_grant_L <= '1';
else
err_North_grant_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_Req_N <= '1';
else
err_East_Req_N <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, X_N)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
X_N = '0' ) then
err_East_grant_N <= '1';
else
err_East_grant_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_Req_E <= '1';
else
err_West_Req_E <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, X_E)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
X_E = '0' ) then
err_West_grant_E <= '1';
else
err_West_grant_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_Req_W <= '1';
else
err_South_Req_W <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, X_W)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
X_W = '0' ) then
err_South_grant_W <= '1';
else
err_South_grant_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_Req_S <= '1';
else
err_Local_Req_S <= '0';
end if;
end process;
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, X_S)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
X_S = '0' ) then
err_Local_grant_S <= '1';
else
err_Local_grant_S <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
process (Requests, Grants)
begin
if ( Requests /= "00000" and Grants = "00000") then
err_request_no_grants <= '1';
else
err_request_no_grants <= '0';
end if;
end process;
process (req_X_N, X_N)
begin
if (req_X_N = '0' and X_N = '1') then
err_no_Req_N_grant_N <= '1';
else
err_no_Req_N_grant_N <= '0';
end if;
end process;
process (req_X_E, X_E)
begin
if (req_X_E = '0' and X_E = '1') then
err_no_Req_E_grant_E <= '1';
else
err_no_Req_E_grant_E <= '0';
end if;
end process;
process (req_X_W, X_W)
begin
if (req_X_W = '0' and X_W = '1') then
err_no_Req_W_grant_W <= '1';
else
err_no_Req_W_grant_W <= '0';
end if;
end process;
process (req_X_S, X_S)
begin
if (req_X_S = '0' and X_S = '1') then
err_no_Req_S_grant_S <= '1';
else
err_no_Req_S_grant_S <= '0';
end if;
end process;
process (req_X_L, X_L)
begin
if (req_X_L = '0' and X_L = '1') then
err_no_Req_L_grant_L <= '1';
else
err_no_Req_L_grant_L <= '0';
end if;
end process;
end behavior; | gpl-3.0 |
os-cillation/easyfpga-soc | infrastructure/receive_frame_buffer_tb.vhd | 1 | 4757 | -- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity receive_frame_buffer_tb is
end receive_frame_buffer_tb;
architecture write_sequence of receive_frame_buffer_tb is
constant CLK_PERIOD : time := 10 ns;
constant UUT_WORD_COUNT_MAX : natural := 11;
constant UUT_WIDTH : natural := 8;
signal clk, clr, store : std_logic;
signal complete, full : std_logic;
signal word : std_logic_vector(UUT_WIDTH -1 downto 0);
signal frame : std_logic_vector(UUT_WORD_COUNT_MAX*UUT_WIDTH -1 downto 0);
procedure clear (signal clr : out std_logic;
signal store : out std_logic
) is
begin
clr <= '1';
store <= '1';
wait for CLK_PERIOD;
end clear;
procedure send_word (constant word_arg : in std_logic_vector(UUT_WIDTH -1 downto 0);
signal word : out std_logic_vector(UUT_WIDTH -1 downto 0);
signal clr : out std_logic;
signal store : out std_logic
) is
begin
clr <= '0';
store <= '1';
word <= word_arg;
wait for CLK_PERIOD;
end send_word;
begin
--**************************************
-- instantiation of unit under test
--**************************************
UUT : entity work.receive_frame_buffer
generic map (
WIDTH => UUT_WIDTH ,
WORD_COUNT_MAX => UUT_WORD_COUNT_MAX
) port map (
clk_i => clk,
clear_i => clr,
store_i => store,
frame_complete_o => complete,
full_o => full,
word_i => word,
frame_o => frame
);
--*****************************
-- clock generator process
--*****************************
CLOCK_GEN_PROC : process is
begin
clk <= '0';
wait for CLK_PERIOD/2;
clk <= '1';
wait for CLK_PERIOD/2;
end process CLOCK_GEN_PROC;
--*******************************
-- stimuli generator process
--*******************************
STIMULI_GEN_PROC : process is
begin
-- hold in reset for 100 ns
clr <= '1';
store <= '0';
word <= x"00";
wait for 100 ns;
--******************
-- send MCU_SEL
--******************
assert false report "will now send MCU_SEL" severity note;
send_word(word_arg => x"8A", word => word, clr => clr, store => store);
send_word(word_arg => x"55", word => word, clr => clr, store => store);
clear(clr => clr, store => store);
--**********************
-- send REGISTER_WR
--**********************
assert false report "will now send REGISTER_WR" severity note;
send_word(word_arg => x"8A", word => word, clr => clr, store => store);
send_word(word_arg => x"66", word => word, clr => clr, store => store);
-- data
send_word(word_arg => x"00", word => word, clr => clr, store => store);
send_word(word_arg => x"11", word => word, clr => clr, store => store);
send_word(word_arg => x"22", word => word, clr => clr, store => store);
send_word(word_arg => x"33", word => word, clr => clr, store => store);
-- address
send_word(word_arg => x"44", word => word, clr => clr, store => store);
send_word(word_arg => x"AA", word => word, clr => clr, store => store);
send_word(word_arg => x"BB", word => word, clr => clr, store => store);
send_word(word_arg => x"CC", word => word, clr => clr, store => store);
-- parity (correct)
send_word(word_arg => x"99", word => word, clr => clr, store => store);
-- clear
clear(clr => clr, store => store);
wait; -- forever
end process STIMULI_GEN_PROC;
end write_sequence;
| gpl-3.0 |
os-cillation/easyfpga-soc | templates/standalone_application/hello_world.vhd | 1 | 2373 | -- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- H E L L O W O R L D S T A N D A L O N E A P P L I C A T I O N
-- (hello_world.vhd)
--
-- Simple 1 Hz LED blinker
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------------------------
ENTITY hello_world is
--------------------------------------------------------------------------------
port (
-- 8 MHz clock input
clk_i : in std_logic;
-- LED output
gpio_b0_00 : out std_logic
);
end hello_world;
--------------------------------------------------------------------------------
ARCHITECTURE behavioral of hello_world is
--------------------------------------------------------------------------------
constant counter_max : natural := 8000000;
-------------------------------------------------------------------------------
begin -- architecture behavioral
-------------------------------------------------------------------------------
counter : process(clk_i)
variable count : natural range 0 to counter_max := 0;
begin
if (rising_edge(clk_i)) then
-- LED on
if (count < counter_max/2) then
gpio_b0_00 <= '1';
count := count + 1;
-- LED off
elsif (count < counter_max) then
gpio_b0_00 <= '0';
count := count + 1;
-- counter reset
else
count := 0;
end if;
end if;
end process counter;
end behavioral;
| gpl-3.0 |
rogerioag/gcg | tutorial/ula/src/unidadeLogica.vhd | 1 | 844 | -- Projeto gerado via script.
-- Data: Sáb,31/12/2011-01:39:29
-- Autor: rogerio
-- Comentario: Descrição da Entidade: unidadeLogica.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity unidadeLogica is
port (A, B, OpAND, OpOR, OpNAND, OpNOR, OpXOR, OpXNOR, OpNOT: in <<type>>; S: out <<type>>);
end unidadeLogica;
architecture estrutural of unidadeLogica is
-- Declaração dos componentes.
component <<COMPONENT_NAME>>
port(<<ports_in>>: in <<type>>; <<ports_out>>: out <<type>>);
end component;
-- Declaração dos sinais.
signal <<s_sinal_1>>, <<s_sinal_2>>, <<s_sinal_N>>: <<type>> <<length>>;
begin
-- Comandos.
-- Instanciação dos componentes e o mapeamento de portas.
<<instance_name>>: <<COMPONENT_NAME>> port map(<<port1>>=><<portX>>, <<port2>>=><<portY>>);
end estrutural;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx_1.vhd | 3 | 181455 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram_1 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_1 is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c",
INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c",
INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042",
INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042",
INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000",
INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000",
INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808",
INIT_06 => X"fc002e000000003300fc00fffffc0000f90203fc00aea8000000143000140000",
INIT_07 => X"00100000f90203fc00980a0005250a251000aecc00001a011c1c009118180000",
INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_wrapper.vhd | 3 | 6136 | ---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component TS1N40LPB4096X32M4S is
--generic (cdeFileInit : string);
port (
PD : in std_logic; --Power down mode
CLK : in std_logic; --CLK input
CEB : in std_logic; --Chip enable, active low for SRAM operation; active high for fuse data setting
WEB : in std_logic; --Write enable, active low
CEBM : in std_logic; --Chip enable for BIST, active low for SRAM operation; active high for fuse data setting
WEBM : in std_logic; --Write enable for BIST, active low
AWT : in std_logic; --Asynchronous write through
A: in std_logic_vector(11 downto 0); --Address input
D: in std_logic_vector(31 downto 0); --Data input
BWEB: in std_logic_vector(31 downto 0); --Bit write enable, active low
AM: in std_logic_vector(9 downto 0); --Address input for BIST
DM: in std_logic_vector(31 downto 0); --Data input for BIST
BWEBM: in std_logic_vector(31 downto 0); --Bit write enable, active low
BIST: in std_logic; --BIST enable
RTSEL:in std_logic_vector(1 downto 0); --Read margin setting pins
WTSEL:in std_logic_vector(1 downto 0); --Write margin setting pins
Q: out std_logic_vector(31 downto 0) --Data output
);
end component;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
signal write_enable: std_logic;
signal write_BWEB: std_logic_vector(31 downto 0);
signal not_clock: std_logic;
signal delayed_data_out, Q: std_logic_vector(31 downto 0);
begin
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
end case;
end process;
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
-- the following process is not actually tested!
process(Mem_write_byte_enable)
begin
write_BWEB <= (others => '1');
if Mem_write_byte_enable(0) = '1' then
write_BWEB(7 downto 0) <= "00000000";
end if;
if Mem_write_byte_enable(1) = '1' then
write_BWEB(15 downto 8) <= "00000000";
end if;
if Mem_write_byte_enable(2) = '1' then
write_BWEB(23 downto 16) <= "00000000";
end if;
if Mem_write_byte_enable(3) = '1' then
write_BWEB(31 downto 24) <= "00000000";
end if;
end process;
-- Plasma wants the data in the next clock cycle!
process(Mem_clk, Mem_reset)begin
if Mem_reset = '1' then
delayed_data_out <= (others=> '0');
elsif rising_edge(Mem_clk) then
delayed_data_out <= Q;
end if;
end process;
RAM_unit: TS1N40LPB4096X32M4S
generic map (cdeFileInit => stim_file)
port map(
PD => '0',
CLK => not_clock, -- this is the part that we changed. there was some serious timing issues with setup and hold times!
CEB => '0',
WEB => write_enable,
CEBM => '0',
WEBM => '1',
AWT => '0',
A => Mem_address(13 downto 2),
D => Mem_data_write,
BWEB => write_BWEB,
AM => (others =>'0'),
DM => (others =>'0'),
BWEBM => (others =>'1'),
BIST => '0',
RTSEL => "01", -- they said and i qoute: "Please use this setting"
WTSEL => "01", -- they said and i qoute: "Please use this setting"
Q => Q
);
Mem_data_read <= delayed_data_out;
end; --architecture logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/Checkers/Control_Part_Checkers/Allocator_checkers/Allocator_credit_counter_logic_checkers/allocator_credit_counter_logic_pseudo.vhd | 3 | 3136 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : out std_logic_vector(1 downto 0)
);
end allocator_credit_counter_logic_pseudo;
architecture behavior of allocator_credit_counter_logic_pseudo is
begin
-- The combionational part
-- this process handels the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
END;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/pc_next.vhd | 14 | 2101 | ---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Processor_NI/pc_next.vhd | 14 | 2101 | ---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity pc_next is
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end; --pc_next
architecture logic of pc_next is
signal pc_reg : std_logic_vector(31 downto 2);
begin
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_reg)
variable pc_inc : std_logic_vector(31 downto 2);
variable pc_next : std_logic_vector(31 downto 2);
begin
pc_inc := bv_increment(pc_reg); --pc_reg+1
case pc_source is
when FROM_INC4 =>
pc_next := pc_inc;
when FROM_OPCODE25_0 =>
pc_next := pc_reg(31 downto 28) & opcode25_0;
when FROM_BRANCH | FROM_LBRANCH =>
if take_branch = '1' then
pc_next := pc_new;
else
pc_next := pc_inc;
end if;
when others =>
pc_next := pc_inc;
end case;
if pause_in = '1' then
pc_next := pc_reg;
end if;
if reset_in = '1' then
pc_reg <= ZERO(31 downto 2);
pc_next := pc_reg;
elsif rising_edge(clk) then
pc_reg <= pc_next;
end if;
pc_future <= pc_next;
pc_current <= pc_reg;
pc_plus4 <= pc_inc;
end process;
end; --logic
| gpl-3.0 |
os-cillation/easyfpga-soc | infrastructure/fifo_adapter.vhd | 1 | 2448 | -- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- F I F O A D A P T E R
-- Asynchronous entity to tristate external pins if disabled
-- and invert control signals to be high active
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity fifo_adapter is
port (
-- external fifo pins
data_pins : inout std_logic_vector(7 downto 0);
rxf_pin : in std_logic;
txd_pin : in std_logic;
wr_pin : out std_logic;
rd_pin : out std_logic;
-- internal fifo signals
enable_i : in std_logic; -- async enable
direction_i : in std_logic; -- data direction (0:receive, 1:send)
data_transmit_i : in std_logic_vector(7 downto 0);
data_receive_o : out std_logic_vector(7 downto 0);
rxf_o : out std_logic;
txd_o : out std_logic;
wr_i : in std_logic;
rd_i : in std_logic
);
end fifo_adapter;
architecture async of fifo_adapter is
begin
-- receive data (dir=0)
data_receive_o <= data_pins when (enable_i='1' and direction_i='0')
else (others => '0');
-- send data (dir=1)
data_pins <= data_transmit_i when (enable_i='1' and direction_i='1')
else (others => 'Z');
-- control pins: connect when enabled
rxf_o <= not rxf_pin when enable_i = '1' else '0';
txd_o <= not txd_pin when enable_i = '1' else '0';
wr_pin <= wr_i when enable_i = '1' else 'Z';
rd_pin <= not rd_i when enable_i = '1' else 'Z';
end async;
| gpl-3.0 |
adelapie/noekeon_inner_round | noekeon_pipelining_inner_k_3/pi_1.vhd | 5 | 1312 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end pi_1;
architecture Behavioral of pi_1 is
begin
a_1_out <= a_1_in(30 downto 0) & a_1_in(31);
a_2_out <= a_2_in(26 downto 0) & a_2_in(31 downto 27);
a_3_out <= a_3_in(29 downto 0) & a_3_in(31 downto 30);
end Behavioral;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/control.vhd | 9 | 16953 | ---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/counter_threshold.vhd | 9 | 3773 | --Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Healthy_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when others =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre_FCX.vhd | 3 | 4775 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= CE;
toSE <= SE;
toUE <= UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch; | gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/xbar.vhd | 20 | 1004 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end; | gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/TB_Package_32_bit_credit_based.vhd | 9 | 15781 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1', '0' after 26 us;
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Processor_NI/TB_Package_32_bit_credit_based.vhd | 9 | 15781 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1', '0' after 26 us;
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/TB_Package_32_bit_credit_based.vhd | 9 | 15781 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integer ) return std_logic_vector ;
function Body_gen(Packet_length, Data: integer ) return std_logic_vector ;
function Tail_gen(Packet_length, Data: integer ) return std_logic_vector ;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0));
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector);
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector);
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer);
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function Header_gen(Packet_length, source, destination, packet_id: integer)
return std_logic_vector is
variable Header_flit: std_logic_vector (31 downto 0);
begin
Header_flit := Header_type & std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)) & XOR_REDUCE(Header_type &
std_logic_vector(to_unsigned(Packet_length, 12)) & std_logic_vector(to_unsigned(destination, 4)) &
std_logic_vector(to_unsigned(source, 4)) & std_logic_vector(to_unsigned(packet_id, 8)));
return Header_flit;
end Header_gen;
function Body_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Body_flit: std_logic_vector (31 downto 0);
begin
Body_flit := Body_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Body_type & std_logic_vector(to_unsigned(Data, 28)));
return Body_flit;
end Body_gen;
function Tail_gen(Packet_length, Data: integer)
return std_logic_vector is
variable Tail_flit: std_logic_vector (31 downto 0);
begin
Tail_flit := Tail_type & std_logic_vector(to_unsigned(Data, 28)) & XOR_REDUCE(Tail_type & std_logic_vector(to_unsigned(Data, 28)));
return Tail_flit;
end Tail_gen;
procedure credit_counter_control(signal clk: in std_logic;
signal credit_in: in std_logic; signal valid_out: in std_logic;
signal credit_counter_out: out std_logic_vector(1 downto 0)) is
variable credit_counter: std_logic_vector (1 downto 0);
begin
credit_counter := "11";
while true loop
credit_counter_out<= credit_counter;
wait until clk'event and clk ='1';
if valid_out = '1' and credit_in ='1' then
credit_counter := credit_counter;
elsif credit_in = '1' then
credit_counter := credit_counter + 1;
elsif valid_out = '1' and credit_counter > 0 then
credit_counter := credit_counter - 1;
else
credit_counter := credit_counter;
end if;
end loop;
end credit_counter_control;
procedure gen_random_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_random_packet;
procedure gen_bit_reversed_packet(network_size, frame_length, source, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time; signal clk: in std_logic;
signal credit_counter_in: in std_logic_vector(1 downto 0); signal valid_out: out std_logic;
signal port_in: out std_logic_vector) is
variable seed1 :positive ;
variable seed2 :positive ;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
variable rand : real ;
variable destination_id: integer;
variable id_counter, frame_starting_delay, Packet_length, frame_ending_delay : integer:= 0;
variable credit_counter: std_logic_vector (1 downto 0);
begin
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
valid_out <= '0';
port_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
wait until clk'event and clk ='1';
for i in 0 to initial_delay loop
wait until clk'event and clk ='1';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
while true loop
--generating the frame initial delay
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - 3*Packet_length)))/100);
--generating the frame ending delay
frame_ending_delay := frame_length - (3*Packet_length+frame_starting_delay);
for k in 0 to frame_starting_delay-1 loop
wait until clk'event and clk ='0';
end loop;
valid_out <= '0';
while credit_counter_in = 0 loop
wait until clk'event and clk ='0';
end loop;
-- generating the packet
id_counter := id_counter + 1;
if id_counter = 256 then
id_counter := 0;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
Packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (Packet_length < min_packet_size) then
Packet_length:=min_packet_size;
end if;
if (Packet_length > max_packet_size) then
Packet_length:=max_packet_size;
end if;
--------------------------------------
uniform(seed1, seed2, rand);
destination_id := integer(rand*real((network_size**2)-1));
while (destination_id = source) loop
uniform(seed1, seed2, rand);
destination_id := integer(rand*3.0);
end loop;
--------------------------------------
write(LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(source) & " to " & integer'image(destination_id) & " with length: " & integer'image(Packet_length) & " id: " & integer'image(id_counter));
writeline(VEC_FILE, LINEVARIABLE);
wait until clk'event and clk ='0';
port_in <= Header_gen(Packet_length, source, destination_id, id_counter);
valid_out <= '1';
wait until clk'event and clk ='0';
for I in 0 to Packet_length-3 loop
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Body_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
end loop;
if credit_counter_in = "00" then
valid_out <= '0';
wait until credit_counter_in'event and credit_counter_in >0;
wait until clk'event and clk ='0';
end if;
uniform(seed1, seed2, rand);
port_in <= Tail_gen(Packet_length, integer(rand*1000.0));
valid_out <= '1';
wait until clk'event and clk ='0';
valid_out <= '0';
port_in <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" ;
for l in 0 to frame_ending_delay-1 loop
wait until clk'event and clk ='0';
end loop;
port_in <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" ;
if now > finish_time then
wait;
end if;
end loop;
end gen_bit_reversed_packet;
procedure get_packet(DATA_WIDTH, initial_delay, Node_ID: in integer; signal clk: in std_logic;
signal credit_out: out std_logic; signal valid_in: in std_logic; signal port_in: in std_logic_vector) is
-- initial_delay: waits for this number of clock cycles before sending the packet!
variable source_node, destination_node, P_length, packet_id, counter: integer;
variable LINEVARIABLE : line;
file VEC_FILE : text is out "received.txt";
begin
credit_out <= '1', '0' after 26 us;
counter := 0;
while true loop
wait until clk'event and clk ='1';
if valid_in = '1' then
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then
counter := 1;
P_length := to_integer(unsigned(port_in(28 downto 17)));
destination_node := to_integer(unsigned(port_in(16 downto 13)));
source_node := to_integer(unsigned(port_in(12 downto 9)));
packet_id := to_integer(unsigned(port_in(8 downto 1)));
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then
--report "flit type: " &integer'image(to_integer(unsigned(port_in(DATA_WIDTH-1 downto DATA_WIDTH-3)))) ;
--report "counter: " & integer'image(counter);
counter := counter+1;
end if;
if (port_in(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then
counter := counter+1;
report "Packet received at " & time'image(now) & " From " & integer'image(source_node) & " to " & integer'image(destination_node) & " with length: "& integer'image(P_length) & " counter: "& integer'image(counter);
assert (P_length=counter) report "wrong packet size" severity warning;
assert (Node_ID=destination_node) report "wrong packet destination " severity warning;
write(LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(source_node) & " to: " & integer'image(destination_node) & " length: "& integer'image(P_length) & " actual length: "& integer'image(counter) & " id: "& integer'image(packet_id));
writeline(VEC_FILE, LINEVARIABLE);
counter := 0;
end if;
end if;
end loop;
end get_packet;
procedure gen_fault(signal sta_0, sta_1: out std_logic; signal address: out std_logic_vector; delay, seed_1, seed_2: in integer) is
variable seed1 :positive := seed_1;
variable seed2 :positive := seed_2;
variable rand : real;
variable stuck: integer;
begin
sta_0 <= '0';
sta_1 <= '0';
while true loop
sta_0 <= '0';
sta_1 <= '0';
for I in 0 to delay loop
wait for 1 ns;
end loop;
uniform(seed1, seed2, rand);
address <= std_logic_vector(to_unsigned(integer(rand*31.0), 5));
uniform(seed1, seed2, rand);
stuck := integer(rand*11.0);
if stuck > 5 then
sta_0 <= '1';
sta_1 <= '0';
else
sta_0 <= '0';
sta_1 <= '1';
end if;
wait for 1 ns;
end loop;
end gen_fault;
end TB_Package;
| gpl-3.0 |
adelapie/noekeon_inner_round | noekeon_pipelining_inner_k_1/tb_pi_2.vhd | 5 | 2708 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_2 IS
END tb_pi_2;
ARCHITECTURE behavior OF tb_pi_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_2
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_2 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"43575679";
a_2_in <= X"465647e0";
a_3_in <= X"c002aeef";
wait for clk_period;
assert a_1_out = X"a1abab3c"
report "PI1 ERROR (a_0)" severity FAILURE;
assert a_2_out = X"0232b23f"
report "PI1 ERROR (a_1)" severity FAILURE;
assert a_3_out = X"f000abbb"
report "PI1 ERROR (a_2)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 |
rogerioag/gcg | tutorial/ula/testbench/and3_tb.vhd | 1 | 2050 | -- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Teste da entidade and3.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and3_tb is
end and3_tb;
architecture logica of and3_tb is
-- Declaração do componente.
component and3
port (a,b,c: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for and3_0: and3 use entity work.and3;
signal s_t_a, s_t_b, s_t_c, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
and3_0: and3 port map (a=>s_t_a,b=>s_t_b,c=>s_t_c,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a, vi_b, vi_c: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0', '0'),
('0', '0', '1', '0'),
('0', '1', '0', '0'),
('0', '1', '1', '0'),
('1', '0', '0', '0'),
('1', '0', '1', '0'),
('1', '1', '0', '0'),
('1', '1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
s_t_c <= patterns(i).vi_c;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
| gpl-3.0 |
adelapie/noekeon_inner_round | noekeon_pipelining_inner_k_3/noekeon_pipe/tb_reg_128_s.vhd | 8 | 1067 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/eth_dma.vhd | 12 | 6966 | ---------------------------------------------------------------------
-- TITLE: Ethernet DMA
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/27/07
-- FILENAME: eth_dma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Ethernet DMA (Direct Memory Access) controller.
-- Reads four bits and writes four bits from/to the Ethernet PHY each
-- 2.5 MHz clock cycle. Received data is DMAed starting at 0x13ff0000
-- transmit data is read from 0x13fd0000.
-- To send a packet write bytes/4 to Ethernet send register.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity eth_dma is port(
clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic; --enable receive DMA
select_eth : in std_logic;
rec_isr : out std_logic; --data received
send_isr : out std_logic; --transmit done
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end; --entity eth_dma
architecture logic of eth_dma is
signal rec_clk : std_logic_vector(1 downto 0); --receive
signal rec_store : std_logic_vector(31 downto 0); --to DDR
signal rec_data : std_logic_vector(27 downto 0);
signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
signal rec_words : std_logic_vector(13 downto 0);
signal rec_dma : std_logic_vector(1 downto 0); --active & request
signal rec_done : std_logic;
signal send_clk : std_logic_vector(1 downto 0); --transmit
signal send_read : std_logic_vector(31 downto 0); --from DDR
signal send_data : std_logic_vector(31 downto 0);
signal send_cnt : std_logic_vector(2 downto 0); --nibbles
signal send_words : std_logic_vector(8 downto 0);
signal send_level : std_logic_vector(8 downto 0);
signal send_dma : std_logic_vector(1 downto 0); --active & request
signal send_enable: std_logic;
begin --architecture
dma_proc: process(clk, reset, enable_eth, select_eth,
data_read, pause_in, mem_address, mem_byte_we, data_w,
E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
rec_clk, rec_store, rec_data,
rec_cnt, rec_words, rec_dma, rec_done,
send_clk, send_read, send_data, send_cnt, send_words,
send_level, send_dma, send_enable)
begin
if reset = '1' then
rec_clk <= "00";
rec_cnt <= "000";
rec_words <= ZERO(13 downto 0);
rec_dma <= "00";
rec_done <= '0';
send_clk <= "00";
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= ZERO(8 downto 0);
send_dma <= "00";
send_enable <= '0';
elsif rising_edge(clk) then
--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
rec_clk <= rec_clk(0) & E_RX_CLK;
if rec_clk = "01" and enable_eth = '1' then
if E_RX_DV = '1' or rec_cnt /= "000" then
if rec_cnt = "111" then
rec_store <= rec_data & E_RXD;
rec_dma(0) <= '1'; --request DMA
end if;
rec_data <= rec_data(23 downto 0) & E_RXD;
rec_cnt <= rec_cnt + 1;
end if;
end if;
--Set transmit count or clear receive interrupt
if select_eth = '1' then
if mem_byte_we /= "0000" then
send_cnt <= "000";
send_words <= ZERO(8 downto 0);
send_level <= data_w(8 downto 0);
send_dma(0) <= '1';
else
rec_done <= '0';
end if;
end if;
--Transmit nibble on low->high E_TX_CLK. Get 32 bits from DDR.
send_clk <= send_clk(0) & E_TX_CLK;
if send_clk = "01" then
if send_cnt = "111" then
if send_words /= send_level then
send_data <= send_read;
send_dma(0) <= '1';
send_enable <= '1';
else
send_enable <= '0';
end if;
else
send_data(31 downto 4) <= send_data(27 downto 0);
end if;
send_cnt <= send_cnt + 1;
end if;
--Pick which type of DMA operation: bit0 = request; bit1 = active
if pause_in = '0' then
if rec_dma(1) = '1' then
rec_dma <= "00"; --DMA done
rec_words <= rec_words + 1;
if E_RX_DV = '0' then
rec_done <= '1';
end if;
elsif send_dma(1) = '1' then
send_dma <= "00";
send_words <= send_words + 1;
send_read <= data_read;
elsif rec_dma(0) = '1' then
rec_dma(1) <= '1'; --start DMA
elsif send_dma(0) = '1' then
send_dma(1) <= '1'; --start DMA
end if;
end if;
end if; --rising_edge(clk)
E_TXD <= send_data(31 downto 28);
E_TX_EN <= send_enable;
rec_isr <= rec_done;
if send_words = send_level then
send_isr <= '1';
else
send_isr <= '0';
end if;
if rec_dma(1) = '1' then
address <= "0001001111111111" & rec_words; --0x13ff0000
byte_we <= "1111";
data_write <= rec_store;
pause_out <= '1'; --to CPU
elsif send_dma(1) = '1' then
address <= "000100111111111000000" & send_words; --0x13fe0000
byte_we <= "0000";
data_write <= data_w;
pause_out <= '1';
else
address <= mem_address; --Send request from CPU to DDR
byte_we <= mem_byte_we;
data_write <= data_w;
pause_out <= '0';
end if;
end process;
end; --architecture logic
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/Router_32_bit_credit_based_packet_drop_classifier_SHMU_will_full_set_of_checkers.vhd | 3 | 585940 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT checkers_counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
data_input: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N,
N_err_IDLE_grant_N,
N_err_North_Req_N,
N_err_North_grant_N,
N_err_East_Req_E,
N_err_East_grant_E,
N_err_West_Req_W,
N_err_West_grant_W,
N_err_South_Req_S,
N_err_South_grant_S,
N_err_Local_Req_L,
N_err_Local_grant_L,
N_err_IDLE_Req_E,
N_err_IDLE_grant_E,
N_err_North_Req_E,
N_err_North_grant_E,
N_err_East_Req_W,
N_err_East_grant_W,
N_err_West_Req_S,
N_err_West_grant_S,
N_err_South_Req_L,
N_err_South_grant_L,
N_err_Local_Req_N,
N_err_Local_grant_N,
N_err_IDLE_Req_W,
N_err_IDLE_grant_W,
N_err_North_Req_W,
N_err_North_grant_W,
N_err_East_Req_S,
N_err_East_grant_S,
N_err_West_Req_L,
N_err_West_grant_L,
N_err_South_Req_N,
N_err_South_grant_N,
N_err_Local_Req_E,
N_err_Local_grant_E,
N_err_IDLE_Req_S,
N_err_IDLE_grant_S,
N_err_North_Req_S,
N_err_North_grant_S,
N_err_East_Req_L,
N_err_East_grant_L,
N_err_West_Req_N,
N_err_West_grant_N,
N_err_South_Req_E,
N_err_South_grant_E,
N_err_Local_Req_W,
N_err_Local_grant_W,
N_err_IDLE_Req_L,
N_err_IDLE_grant_L,
N_err_North_Req_L,
N_err_North_grant_L,
N_err_East_Req_N,
N_err_East_grant_N,
N_err_West_Req_E,
N_err_West_grant_E,
N_err_South_Req_W,
N_err_South_grant_W,
N_err_Local_Req_S,
N_err_Local_grant_S,
N_err_state_in_onehot,
N_err_no_request_grants,
N_err_request_no_grants,
N_err_no_Req_N_grant_N,
N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W,
N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N,
E_err_IDLE_grant_N,
E_err_North_Req_N,
E_err_North_grant_N,
E_err_East_Req_E,
E_err_East_grant_E,
E_err_West_Req_W,
E_err_West_grant_W,
E_err_South_Req_S,
E_err_South_grant_S,
E_err_Local_Req_L,
E_err_Local_grant_L,
E_err_IDLE_Req_E,
E_err_IDLE_grant_E,
E_err_North_Req_E,
E_err_North_grant_E,
E_err_East_Req_W,
E_err_East_grant_W,
E_err_West_Req_S,
E_err_West_grant_S,
E_err_South_Req_L,
E_err_South_grant_L,
E_err_Local_Req_N,
E_err_Local_grant_N,
E_err_IDLE_Req_W,
E_err_IDLE_grant_W,
E_err_North_Req_W,
E_err_North_grant_W,
E_err_East_Req_S,
E_err_East_grant_S,
E_err_West_Req_L,
E_err_West_grant_L,
E_err_South_Req_N,
E_err_South_grant_N,
E_err_Local_Req_E,
E_err_Local_grant_E,
E_err_IDLE_Req_S,
E_err_IDLE_grant_S,
E_err_North_Req_S,
E_err_North_grant_S,
E_err_East_Req_L,
E_err_East_grant_L,
E_err_West_Req_N,
E_err_West_grant_N,
E_err_South_Req_E,
E_err_South_grant_E,
E_err_Local_Req_W,
E_err_Local_grant_W,
E_err_IDLE_Req_L,
E_err_IDLE_grant_L,
E_err_North_Req_L,
E_err_North_grant_L,
E_err_East_Req_N,
E_err_East_grant_N,
E_err_West_Req_E,
E_err_West_grant_E,
E_err_South_Req_W,
E_err_South_grant_W,
E_err_Local_Req_S,
E_err_Local_grant_S,
E_err_state_in_onehot,
E_err_no_request_grants,
E_err_request_no_grants,
E_err_no_Req_N_grant_N,
E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W,
E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N,
W_err_IDLE_grant_N,
W_err_North_Req_N,
W_err_North_grant_N,
W_err_East_Req_E,
W_err_East_grant_E,
W_err_West_Req_W,
W_err_West_grant_W,
W_err_South_Req_S,
W_err_South_grant_S,
W_err_Local_Req_L,
W_err_Local_grant_L,
W_err_IDLE_Req_E,
W_err_IDLE_grant_E,
W_err_North_Req_E,
W_err_North_grant_E,
W_err_East_Req_W,
W_err_East_grant_W,
W_err_West_Req_S,
W_err_West_grant_S,
W_err_South_Req_L,
W_err_South_grant_L,
W_err_Local_Req_N,
W_err_Local_grant_N,
W_err_IDLE_Req_W,
W_err_IDLE_grant_W,
W_err_North_Req_W,
W_err_North_grant_W,
W_err_East_Req_S,
W_err_East_grant_S,
W_err_West_Req_L,
W_err_West_grant_L,
W_err_South_Req_N,
W_err_South_grant_N,
W_err_Local_Req_E,
W_err_Local_grant_E,
W_err_IDLE_Req_S,
W_err_IDLE_grant_S,
W_err_North_Req_S,
W_err_North_grant_S,
W_err_East_Req_L,
W_err_East_grant_L,
W_err_West_Req_N,
W_err_West_grant_N,
W_err_South_Req_E,
W_err_South_grant_E,
W_err_Local_Req_W,
W_err_Local_grant_W,
W_err_IDLE_Req_L,
W_err_IDLE_grant_L,
W_err_North_Req_L,
W_err_North_grant_L,
W_err_East_Req_N,
W_err_East_grant_N,
W_err_West_Req_E,
W_err_West_grant_E,
W_err_South_Req_W,
W_err_South_grant_W,
W_err_Local_Req_S,
W_err_Local_grant_S,
W_err_state_in_onehot,
W_err_no_request_grants,
W_err_request_no_grants,
W_err_no_Req_N_grant_N,
W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W,
W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N,
S_err_IDLE_grant_N,
S_err_North_Req_N,
S_err_North_grant_N,
S_err_East_Req_E,
S_err_East_grant_E,
S_err_West_Req_W,
S_err_West_grant_W,
S_err_South_Req_S,
S_err_South_grant_S,
S_err_Local_Req_L,
S_err_Local_grant_L,
S_err_IDLE_Req_E,
S_err_IDLE_grant_E,
S_err_North_Req_E,
S_err_North_grant_E,
S_err_East_Req_W,
S_err_East_grant_W,
S_err_West_Req_S,
S_err_West_grant_S,
S_err_South_Req_L,
S_err_South_grant_L,
S_err_Local_Req_N,
S_err_Local_grant_N,
S_err_IDLE_Req_W,
S_err_IDLE_grant_W,
S_err_North_Req_W,
S_err_North_grant_W,
S_err_East_Req_S,
S_err_East_grant_S,
S_err_West_Req_L,
S_err_West_grant_L,
S_err_South_Req_N,
S_err_South_grant_N,
S_err_Local_Req_E,
S_err_Local_grant_E,
S_err_IDLE_Req_S,
S_err_IDLE_grant_S,
S_err_North_Req_S,
S_err_North_grant_S,
S_err_East_Req_L,
S_err_East_grant_L,
S_err_West_Req_N,
S_err_West_grant_N,
S_err_South_Req_E,
S_err_South_grant_E,
S_err_Local_Req_W,
S_err_Local_grant_W,
S_err_IDLE_Req_L,
S_err_IDLE_grant_L,
S_err_North_Req_L,
S_err_North_grant_L,
S_err_East_Req_N,
S_err_East_grant_N,
S_err_West_Req_E,
S_err_West_grant_E,
S_err_South_Req_W,
S_err_South_grant_W,
S_err_Local_Req_S,
S_err_Local_grant_S,
S_err_state_in_onehot,
S_err_no_request_grants,
S_err_request_no_grants,
S_err_no_Req_N_grant_N,
S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W,
S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N,
L_err_IDLE_grant_N,
L_err_North_Req_N,
L_err_North_grant_N,
L_err_East_Req_E,
L_err_East_grant_E,
L_err_West_Req_W,
L_err_West_grant_W,
L_err_South_Req_S,
L_err_South_grant_S,
L_err_Local_Req_L,
L_err_Local_grant_L,
L_err_IDLE_Req_E,
L_err_IDLE_grant_E,
L_err_North_Req_E,
L_err_North_grant_E,
L_err_East_Req_W,
L_err_East_grant_W,
L_err_West_Req_S,
L_err_West_grant_S,
L_err_South_Req_L,
L_err_South_grant_L,
L_err_Local_Req_N,
L_err_Local_grant_N,
L_err_IDLE_Req_W,
L_err_IDLE_grant_W,
L_err_North_Req_W,
L_err_North_grant_W,
L_err_East_Req_S,
L_err_East_grant_S,
L_err_West_Req_L,
L_err_West_grant_L,
L_err_South_Req_N,
L_err_South_grant_N,
L_err_Local_Req_E,
L_err_Local_grant_E,
L_err_IDLE_Req_S,
L_err_IDLE_grant_S,
L_err_North_Req_S,
L_err_North_grant_S,
L_err_East_Req_L,
L_err_East_grant_L,
L_err_West_Req_N,
L_err_West_grant_N,
L_err_South_Req_E,
L_err_South_grant_E,
L_err_Local_Req_W,
L_err_Local_grant_W,
L_err_IDLE_Req_L,
L_err_IDLE_grant_L,
L_err_North_Req_L,
L_err_North_grant_L,
L_err_East_Req_N,
L_err_East_grant_N,
L_err_West_Req_E,
L_err_West_grant_E,
L_err_South_Req_W,
L_err_South_grant_W,
L_err_Local_Req_S,
L_err_Local_grant_S,
L_err_state_in_onehot,
L_err_no_request_grants,
L_err_request_no_grants,
L_err_no_Req_N_grant_N,
L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W,
L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E,
N_err_North_req_X_E,
N_err_East_req_X_W,
N_err_West_req_X_S,
N_err_South_req_X_L,
N_err_Local_req_X_N,
N_err_IDLE_req_X_W,
N_err_North_req_X_W,
N_err_East_req_X_S,
N_err_West_req_X_L,
N_err_South_req_X_N,
N_err_Local_req_X_E,
N_err_IDLE_req_X_S,
N_err_North_req_X_S,
N_err_East_req_X_L,
N_err_West_req_X_N,
N_err_South_req_X_E,
N_err_Local_req_X_W,
N_err_IDLE_req_X_L,
N_err_North_req_X_L,
N_err_East_req_X_N,
N_err_West_req_X_E,
N_err_South_req_X_W,
N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E,
E_err_North_req_X_E,
E_err_East_req_X_W,
E_err_West_req_X_S,
E_err_South_req_X_L,
E_err_Local_req_X_N,
E_err_IDLE_req_X_W,
E_err_North_req_X_W,
E_err_East_req_X_S,
E_err_West_req_X_L,
E_err_South_req_X_N,
E_err_Local_req_X_E,
E_err_IDLE_req_X_S,
E_err_North_req_X_S,
E_err_East_req_X_L,
E_err_West_req_X_N,
E_err_South_req_X_E,
E_err_Local_req_X_W,
E_err_IDLE_req_X_L,
E_err_North_req_X_L,
E_err_East_req_X_N,
E_err_West_req_X_E,
E_err_South_req_X_W,
E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N,
W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E,
W_err_North_req_X_E,
W_err_East_req_X_W,
W_err_West_req_X_S,
W_err_South_req_X_L,
W_err_Local_req_X_N,
W_err_IDLE_req_X_W,
W_err_North_req_X_W,
W_err_East_req_X_S,
W_err_West_req_X_L,
W_err_South_req_X_N,
W_err_Local_req_X_E,
W_err_IDLE_req_X_S,
W_err_North_req_X_S,
W_err_East_req_X_L,
W_err_West_req_X_N,
W_err_South_req_X_E,
W_err_Local_req_X_W,
W_err_IDLE_req_X_L,
W_err_North_req_X_L,
W_err_East_req_X_N,
W_err_West_req_X_E,
W_err_South_req_X_W,
W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants,
W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant,
W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N,
S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E,
S_err_North_req_X_E,
S_err_East_req_X_W,
S_err_West_req_X_S,
S_err_South_req_X_L,
S_err_Local_req_X_N,
S_err_IDLE_req_X_W,
S_err_North_req_X_W,
S_err_East_req_X_S,
S_err_West_req_X_L,
S_err_South_req_X_N,
S_err_Local_req_X_E,
S_err_IDLE_req_X_S,
S_err_North_req_X_S,
S_err_East_req_X_L,
S_err_West_req_X_N,
S_err_South_req_X_E,
S_err_Local_req_X_W,
S_err_IDLE_req_X_L,
S_err_North_req_X_L,
S_err_East_req_X_N,
S_err_West_req_X_E,
S_err_South_req_X_W,
S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants,
S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant,
S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant,
S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N,
L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E,
L_err_North_req_X_E,
L_err_East_req_X_W,
L_err_West_req_X_S,
L_err_South_req_X_L,
L_err_Local_req_X_N,
L_err_IDLE_req_X_W,
L_err_North_req_X_W,
L_err_East_req_X_S,
L_err_West_req_X_L,
L_err_South_req_X_N,
L_err_Local_req_X_E,
L_err_IDLE_req_X_S,
L_err_North_req_X_S,
L_err_East_req_X_L,
L_err_West_req_X_N,
L_err_South_req_X_E,
L_err_Local_req_X_W,
L_err_IDLE_req_X_L,
L_err_North_req_X_L,
L_err_East_req_X_N,
L_err_West_req_X_E,
L_err_South_req_X_W,
L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- Checker outputs
-- Routing part checkers
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order,
-- Cx_Reconf checkers
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
-- Rxy_Reconf checkers
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
-- Signals related to link fault classification modules
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
-- Signals related to Control part checkers fault classification modules
signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic;
signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic;
signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic;
signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic;
signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic;
signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic;
signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic;
signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic;
signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic;
signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic;
signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic;
signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic;
signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic;
signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic;
signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic;
signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic;
signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic;
signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic;
signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic;
signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic;
-- Signals needed for control part checkers
-- Signals needed for LBDR packet drop checkers
-- North
signal N_err_header_empty_Requests_FF_Requests_in,
N_err_tail_Requests_in_all_zero,
N_err_tail_empty_Requests_FF_Requests_in,
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
N_err_grants_onehot,
N_err_grants_mismatch,
N_err_header_tail_Requests_FF_Requests_in,
N_err_dst_addr_cur_addr_N1,
N_err_dst_addr_cur_addr_not_N1,
N_err_dst_addr_cur_addr_E1,
N_err_dst_addr_cur_addr_not_E1,
N_err_dst_addr_cur_addr_W1,
N_err_dst_addr_cur_addr_not_W1,
N_err_dst_addr_cur_addr_S1,
N_err_dst_addr_cur_addr_not_S1,
N_err_dst_addr_cur_addr_Req_L_in,
N_err_dst_addr_cur_addr_not_Req_L_in,
N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--N_err_header_not_empty_Req_L_in, -- added according to new design
N_err_header_not_empty_Req_N_in,
N_err_header_not_empty_Req_E_in,
N_err_header_not_empty_Req_W_in,
N_err_header_not_empty_Req_S_in,
N_err_header_empty_packet_drop_in_packet_drop_equal,
N_err_tail_not_empty_packet_drop_not_packet_drop_in,
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
N_err_packet_drop_order,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- East
E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_tail_empty_Requests_FF_Requests_in,
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
E_err_grants_onehot,
E_err_grants_mismatch,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--E_err_header_not_empty_Req_L_in, -- added according to new design
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in,
E_err_header_empty_packet_drop_in_packet_drop_equal,
E_err_tail_not_empty_packet_drop_not_packet_drop_in,
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
E_err_packet_drop_order,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- West
W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_tail_empty_Requests_FF_Requests_in,
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
W_err_grants_onehot,
W_err_grants_mismatch,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1,
W_err_dst_addr_cur_addr_not_N1,
W_err_dst_addr_cur_addr_E1,
W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1,
W_err_dst_addr_cur_addr_not_W1,
W_err_dst_addr_cur_addr_S1,
W_err_dst_addr_cur_addr_not_S1,
W_err_dst_addr_cur_addr_Req_L_in,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--W_err_header_not_empty_Req_L_in, -- added according to new design
W_err_header_not_empty_Req_N_in,
W_err_header_not_empty_Req_E_in,
W_err_header_not_empty_Req_W_in,
W_err_header_not_empty_Req_S_in,
W_err_header_empty_packet_drop_in_packet_drop_equal,
W_err_tail_not_empty_packet_drop_not_packet_drop_in,
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
W_err_packet_drop_order,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- South
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_tail_empty_Requests_FF_Requests_in,
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
S_err_grants_onehot,
S_err_grants_mismatch,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--S_err_header_not_empty_Req_L_in, -- added according to new design
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in,
S_err_header_empty_packet_drop_in_packet_drop_equal,
S_err_tail_not_empty_packet_drop_not_packet_drop_in,
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
S_err_packet_drop_order,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- Local
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_tail_empty_Requests_FF_Requests_in,
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
L_err_grants_onehot,
L_err_grants_mismatch,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--L_err_header_not_empty_Req_L_in, -- added according to new design
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in,
L_err_header_empty_packet_drop_in_packet_drop_equal,
L_err_tail_not_empty_packet_drop_not_packet_drop_in,
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
L_err_packet_drop_order,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- Signals needed for FIFO packet drop with fault classifier support checkers
-- North
-- Functional checkers
signal N_err_empty_full,
N_err_empty_read_en,
N_err_full_write_en,
N_err_state_in_onehot,
N_err_read_pointer_in_onehot,
N_err_write_pointer_in_onehot,
-- Structural checkers
N_err_write_en_write_pointer,
N_err_not_write_en_write_pointer,
N_err_read_pointer_write_pointer_not_empty,
N_err_read_pointer_write_pointer_empty,
N_err_read_pointer_write_pointer_not_full,
N_err_read_pointer_write_pointer_full,
N_err_read_pointer_increment,
N_err_read_pointer_not_increment,
N_err_write_en,
N_err_not_write_en,
N_err_not_write_en1,
N_err_not_write_en2,
N_err_read_en_mismatch,
N_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
N_err_fake_credit_read_en_fake_credit_counter_in_increment,
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
N_err_fake_credit_read_en_credit_out,
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
N_err_state_out_Idle_not_fault_out_not_fake_credit,
N_err_state_out_Idle_not_fault_out_not_fault_info_in,
N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
N_err_state_out_Idle_fault_out_fake_credit,
N_err_state_out_Idle_fault_out_state_in_Packet_drop,
N_err_state_out_Idle_fault_out_fault_info_in,
N_err_state_out_Idle_fault_out_faulty_packet_in,
N_err_state_out_Idle_not_health_info,
N_err_state_out_Idle_not_write_fake_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
N_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
N_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
N_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
N_err_state_out_Body_flit_valid_in_not_health_info,
N_err_state_out_Body_flit_not_fake_credit,
N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
N_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
N_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
N_err_state_out_Tail_flit_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
N_err_fault_info_fault_info_out_equal,
N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- East
-- Functional checkers
E_err_empty_full,
E_err_empty_read_en,
E_err_full_write_en,
E_err_state_in_onehot,
E_err_read_pointer_in_onehot,
E_err_write_pointer_in_onehot,
-- Structural checkers
E_err_write_en_write_pointer,
E_err_not_write_en_write_pointer,
E_err_read_pointer_write_pointer_not_empty,
E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full,
E_err_read_pointer_write_pointer_full,
E_err_read_pointer_increment,
E_err_read_pointer_not_increment,
E_err_write_en,
E_err_not_write_en,
E_err_not_write_en1,
E_err_not_write_en2,
E_err_read_en_mismatch,
E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
E_err_fake_credit_read_en_fake_credit_counter_in_increment,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
E_err_fake_credit_read_en_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
E_err_state_out_Idle_not_fault_out_not_fake_credit,
E_err_state_out_Idle_not_fault_out_not_fault_info_in,
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Idle_fault_out_fake_credit,
E_err_state_out_Idle_fault_out_state_in_Packet_drop,
E_err_state_out_Idle_fault_out_fault_info_in,
E_err_state_out_Idle_fault_out_faulty_packet_in,
E_err_state_out_Idle_not_health_info,
E_err_state_out_Idle_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
E_err_state_out_Body_flit_valid_in_not_health_info,
E_err_state_out_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
E_err_state_out_Tail_flit_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
E_err_fault_info_fault_info_out_equal,
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- West
-- Functional checkers
W_err_empty_full,
W_err_empty_read_en,
W_err_full_write_en,
W_err_state_in_onehot,
W_err_read_pointer_in_onehot,
W_err_write_pointer_in_onehot,
-- Structural checkers
W_err_write_en_write_pointer,
W_err_not_write_en_write_pointer,
W_err_read_pointer_write_pointer_not_empty,
W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full,
W_err_read_pointer_write_pointer_full,
W_err_read_pointer_increment,
W_err_read_pointer_not_increment,
W_err_write_en,
W_err_not_write_en,
W_err_not_write_en1,
W_err_not_write_en2,
W_err_read_en_mismatch,
W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
W_err_fake_credit_read_en_fake_credit_counter_in_increment,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
W_err_fake_credit_read_en_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
W_err_state_out_Idle_not_fault_out_not_fake_credit,
W_err_state_out_Idle_not_fault_out_not_fault_info_in,
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Idle_fault_out_fake_credit,
W_err_state_out_Idle_fault_out_state_in_Packet_drop,
W_err_state_out_Idle_fault_out_fault_info_in,
W_err_state_out_Idle_fault_out_faulty_packet_in,
W_err_state_out_Idle_not_health_info,
W_err_state_out_Idle_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
W_err_state_out_Body_flit_valid_in_not_health_info,
W_err_state_out_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
W_err_state_out_Tail_flit_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
W_err_fault_info_fault_info_out_equal,
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- South
-- Functional checkers
S_err_empty_full,
S_err_empty_read_en,
S_err_full_write_en,
S_err_state_in_onehot,
S_err_read_pointer_in_onehot,
S_err_write_pointer_in_onehot,
-- Structural checkers
S_err_write_en_write_pointer,
S_err_not_write_en_write_pointer,
S_err_read_pointer_write_pointer_not_empty,
S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full,
S_err_read_pointer_write_pointer_full,
S_err_read_pointer_increment,
S_err_read_pointer_not_increment,
S_err_write_en,
S_err_not_write_en,
S_err_not_write_en1,
S_err_not_write_en2,
S_err_read_en_mismatch,
S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
S_err_fake_credit_read_en_fake_credit_counter_in_increment,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
S_err_fake_credit_read_en_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
S_err_state_out_Idle_not_fault_out_not_fake_credit,
S_err_state_out_Idle_not_fault_out_not_fault_info_in,
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Idle_fault_out_fake_credit,
S_err_state_out_Idle_fault_out_state_in_Packet_drop,
S_err_state_out_Idle_fault_out_fault_info_in,
S_err_state_out_Idle_fault_out_faulty_packet_in,
S_err_state_out_Idle_not_health_info,
S_err_state_out_Idle_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
S_err_state_out_Body_flit_valid_in_not_health_info,
S_err_state_out_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
S_err_state_out_Tail_flit_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
S_err_fault_info_fault_info_out_equal,
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- Local
-- Functional checkers
L_err_empty_full,
L_err_empty_read_en,
L_err_full_write_en,
L_err_state_in_onehot,
L_err_read_pointer_in_onehot,
L_err_write_pointer_in_onehot,
-- Structural checkers
L_err_write_en_write_pointer,
L_err_not_write_en_write_pointer,
L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty,
L_err_read_pointer_write_pointer_not_full,
L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment,
L_err_read_pointer_not_increment,
L_err_write_en,
L_err_not_write_en,
L_err_not_write_en1,
L_err_not_write_en2,
L_err_read_en_mismatch,
L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
L_err_fake_credit_read_en_fake_credit_counter_in_increment,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
L_err_fake_credit_read_en_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
L_err_state_out_Idle_not_fault_out_not_fake_credit,
L_err_state_out_Idle_not_fault_out_not_fault_info_in,
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Idle_fault_out_fake_credit,
L_err_state_out_Idle_fault_out_state_in_Packet_drop,
L_err_state_out_Idle_fault_out_fault_info_in,
L_err_state_out_Idle_fault_out_faulty_packet_in,
L_err_state_out_Idle_not_health_info,
L_err_state_out_Idle_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
L_err_state_out_Body_flit_valid_in_not_health_info,
L_err_state_out_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
L_err_state_out_Tail_flit_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
L_err_fault_info_fault_info_out_equal,
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for Allocator unit
-- Allocator logic checker outputs
signal err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match: std_logic;
-- Allocator credit_counter logic checker outputs
signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_in Checker signals (part of allocator unit)
-- North Arbiter_in checker outputs
signal N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N,
N_err_IDLE_grant_N,
N_err_North_Req_N,
N_err_North_grant_N,
N_err_East_Req_E,
N_err_East_grant_E,
N_err_West_Req_W,
N_err_West_grant_W,
N_err_South_Req_S,
N_err_South_grant_S,
N_err_Local_Req_L,
N_err_Local_grant_L,
N_err_IDLE_Req_E,
N_err_IDLE_grant_E,
N_err_North_Req_E,
N_err_North_grant_E,
N_err_East_Req_W,
N_err_East_grant_W,
N_err_West_Req_S,
N_err_West_grant_S,
N_err_South_Req_L,
N_err_South_grant_L,
N_err_Local_Req_N,
N_err_Local_grant_N,
N_err_IDLE_Req_W,
N_err_IDLE_grant_W,
N_err_North_Req_W,
N_err_North_grant_W,
N_err_East_Req_S,
N_err_East_grant_S,
N_err_West_Req_L,
N_err_West_grant_L,
N_err_South_Req_N,
N_err_South_grant_N,
N_err_Local_Req_E,
N_err_Local_grant_E,
N_err_IDLE_Req_S,
N_err_IDLE_grant_S,
N_err_North_Req_S,
N_err_North_grant_S,
N_err_East_Req_L,
N_err_East_grant_L,
N_err_West_Req_N,
N_err_West_grant_N,
N_err_South_Req_E,
N_err_South_grant_E,
N_err_Local_Req_W,
N_err_Local_grant_W,
N_err_IDLE_Req_L,
N_err_IDLE_grant_L,
N_err_North_Req_L,
N_err_North_grant_L,
N_err_East_Req_N,
N_err_East_grant_N,
N_err_West_Req_E,
N_err_West_grant_E,
N_err_South_Req_W,
N_err_South_grant_W,
N_err_Local_Req_S,
N_err_Local_grant_S,
N_err_arbiter_state_in_onehot,
N_err_no_request_grants,
N_err_request_no_grants,
N_err_no_Req_N_grant_N,
N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W,
N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N,
E_err_IDLE_grant_N,
E_err_North_Req_N,
E_err_North_grant_N,
E_err_East_Req_E,
E_err_East_grant_E,
E_err_West_Req_W,
E_err_West_grant_W,
E_err_South_Req_S,
E_err_South_grant_S,
E_err_Local_Req_L,
E_err_Local_grant_L,
E_err_IDLE_Req_E,
E_err_IDLE_grant_E,
E_err_North_Req_E,
E_err_North_grant_E,
E_err_East_Req_W,
E_err_East_grant_W,
E_err_West_Req_S,
E_err_West_grant_S,
E_err_South_Req_L,
E_err_South_grant_L,
E_err_Local_Req_N,
E_err_Local_grant_N,
E_err_IDLE_Req_W,
E_err_IDLE_grant_W,
E_err_North_Req_W,
E_err_North_grant_W,
E_err_East_Req_S,
E_err_East_grant_S,
E_err_West_Req_L,
E_err_West_grant_L,
E_err_South_Req_N,
E_err_South_grant_N,
E_err_Local_Req_E,
E_err_Local_grant_E,
E_err_IDLE_Req_S,
E_err_IDLE_grant_S,
E_err_North_Req_S,
E_err_North_grant_S,
E_err_East_Req_L,
E_err_East_grant_L,
E_err_West_Req_N,
E_err_West_grant_N,
E_err_South_Req_E,
E_err_South_grant_E,
E_err_Local_Req_W,
E_err_Local_grant_W,
E_err_IDLE_Req_L,
E_err_IDLE_grant_L,
E_err_North_Req_L,
E_err_North_grant_L,
E_err_East_Req_N,
E_err_East_grant_N,
E_err_West_Req_E,
E_err_West_grant_E,
E_err_South_Req_W,
E_err_South_grant_W,
E_err_Local_Req_S,
E_err_Local_grant_S,
E_err_arbiter_state_in_onehot,
E_err_no_request_grants,
E_err_request_no_grants,
E_err_no_Req_N_grant_N,
E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W,
E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N,
W_err_IDLE_grant_N,
W_err_North_Req_N,
W_err_North_grant_N,
W_err_East_Req_E,
W_err_East_grant_E,
W_err_West_Req_W,
W_err_West_grant_W,
W_err_South_Req_S,
W_err_South_grant_S,
W_err_Local_Req_L,
W_err_Local_grant_L,
W_err_IDLE_Req_E,
W_err_IDLE_grant_E,
W_err_North_Req_E,
W_err_North_grant_E,
W_err_East_Req_W,
W_err_East_grant_W,
W_err_West_Req_S,
W_err_West_grant_S,
W_err_South_Req_L,
W_err_South_grant_L,
W_err_Local_Req_N,
W_err_Local_grant_N,
W_err_IDLE_Req_W,
W_err_IDLE_grant_W,
W_err_North_Req_W,
W_err_North_grant_W,
W_err_East_Req_S,
W_err_East_grant_S,
W_err_West_Req_L,
W_err_West_grant_L,
W_err_South_Req_N,
W_err_South_grant_N,
W_err_Local_Req_E,
W_err_Local_grant_E,
W_err_IDLE_Req_S,
W_err_IDLE_grant_S,
W_err_North_Req_S,
W_err_North_grant_S,
W_err_East_Req_L,
W_err_East_grant_L,
W_err_West_Req_N,
W_err_West_grant_N,
W_err_South_Req_E,
W_err_South_grant_E,
W_err_Local_Req_W,
W_err_Local_grant_W,
W_err_IDLE_Req_L,
W_err_IDLE_grant_L,
W_err_North_Req_L,
W_err_North_grant_L,
W_err_East_Req_N,
W_err_East_grant_N,
W_err_West_Req_E,
W_err_West_grant_E,
W_err_South_Req_W,
W_err_South_grant_W,
W_err_Local_Req_S,
W_err_Local_grant_S,
W_err_arbiter_state_in_onehot,
W_err_no_request_grants,
W_err_request_no_grants,
W_err_no_Req_N_grant_N,
W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W,
W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N,
S_err_IDLE_grant_N,
S_err_North_Req_N,
S_err_North_grant_N,
S_err_East_Req_E,
S_err_East_grant_E,
S_err_West_Req_W,
S_err_West_grant_W,
S_err_South_Req_S,
S_err_South_grant_S,
S_err_Local_Req_L,
S_err_Local_grant_L,
S_err_IDLE_Req_E,
S_err_IDLE_grant_E,
S_err_North_Req_E,
S_err_North_grant_E,
S_err_East_Req_W,
S_err_East_grant_W,
S_err_West_Req_S,
S_err_West_grant_S,
S_err_South_Req_L,
S_err_South_grant_L,
S_err_Local_Req_N,
S_err_Local_grant_N,
S_err_IDLE_Req_W,
S_err_IDLE_grant_W,
S_err_North_Req_W,
S_err_North_grant_W,
S_err_East_Req_S,
S_err_East_grant_S,
S_err_West_Req_L,
S_err_West_grant_L,
S_err_South_Req_N,
S_err_South_grant_N,
S_err_Local_Req_E,
S_err_Local_grant_E,
S_err_IDLE_Req_S,
S_err_IDLE_grant_S,
S_err_North_Req_S,
S_err_North_grant_S,
S_err_East_Req_L,
S_err_East_grant_L,
S_err_West_Req_N,
S_err_West_grant_N,
S_err_South_Req_E,
S_err_South_grant_E,
S_err_Local_Req_W,
S_err_Local_grant_W,
S_err_IDLE_Req_L,
S_err_IDLE_grant_L,
S_err_North_Req_L,
S_err_North_grant_L,
S_err_East_Req_N,
S_err_East_grant_N,
S_err_West_Req_E,
S_err_West_grant_E,
S_err_South_Req_W,
S_err_South_grant_W,
S_err_Local_Req_S,
S_err_Local_grant_S,
S_err_arbiter_state_in_onehot,
S_err_no_request_grants,
S_err_request_no_grants,
S_err_no_Req_N_grant_N,
S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W,
S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N,
L_err_IDLE_grant_N,
L_err_North_Req_N,
L_err_North_grant_N,
L_err_East_Req_E,
L_err_East_grant_E,
L_err_West_Req_W,
L_err_West_grant_W,
L_err_South_Req_S,
L_err_South_grant_S,
L_err_Local_Req_L,
L_err_Local_grant_L,
L_err_IDLE_Req_E,
L_err_IDLE_grant_E,
L_err_North_Req_E,
L_err_North_grant_E,
L_err_East_Req_W,
L_err_East_grant_W,
L_err_West_Req_S,
L_err_West_grant_S,
L_err_South_Req_L,
L_err_South_grant_L,
L_err_Local_Req_N,
L_err_Local_grant_N,
L_err_IDLE_Req_W,
L_err_IDLE_grant_W,
L_err_North_Req_W,
L_err_North_grant_W,
L_err_East_Req_S,
L_err_East_grant_S,
L_err_West_Req_L,
L_err_West_grant_L,
L_err_South_Req_N,
L_err_South_grant_N,
L_err_Local_Req_E,
L_err_Local_grant_E,
L_err_IDLE_Req_S,
L_err_IDLE_grant_S,
L_err_North_Req_S,
L_err_North_grant_S,
L_err_East_Req_L,
L_err_East_grant_L,
L_err_West_Req_N,
L_err_West_grant_N,
L_err_South_Req_E,
L_err_South_grant_E,
L_err_Local_Req_W,
L_err_Local_grant_W,
L_err_IDLE_Req_L,
L_err_IDLE_grant_L,
L_err_North_Req_L,
L_err_North_grant_L,
L_err_East_Req_N,
L_err_East_grant_N,
L_err_West_Req_E,
L_err_West_grant_E,
L_err_South_Req_W,
L_err_South_grant_W,
L_err_Local_Req_S,
L_err_Local_grant_S,
L_err_arbiter_state_in_onehot,
L_err_no_request_grants,
L_err_request_no_grants,
L_err_no_Req_N_grant_N,
L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W,
L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_out Checker signals (part of allocator unit)
-- North Arbiter_out checker outputs
signal N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E,
N_err_North_req_X_E,
N_err_East_req_X_W,
N_err_West_req_X_S,
N_err_South_req_X_L,
N_err_Local_req_X_N,
N_err_IDLE_req_X_W,
N_err_North_req_X_W,
N_err_East_req_X_S,
N_err_West_req_X_L,
N_err_South_req_X_N,
N_err_Local_req_X_E,
N_err_IDLE_req_X_S,
N_err_North_req_X_S,
N_err_East_req_X_L,
N_err_West_req_X_N,
N_err_South_req_X_E,
N_err_Local_req_X_W,
N_err_IDLE_req_X_L,
N_err_North_req_X_L,
N_err_East_req_X_N,
N_err_West_req_X_E,
N_err_South_req_X_W,
N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E,
E_err_North_req_X_E,
E_err_East_req_X_W,
E_err_West_req_X_S,
E_err_South_req_X_L,
E_err_Local_req_X_N,
E_err_IDLE_req_X_W,
E_err_North_req_X_W,
E_err_East_req_X_S,
E_err_West_req_X_L,
E_err_South_req_X_N,
E_err_Local_req_X_E,
E_err_IDLE_req_X_S,
E_err_North_req_X_S,
E_err_East_req_X_L,
E_err_West_req_X_N,
E_err_South_req_X_E,
E_err_Local_req_X_W,
E_err_IDLE_req_X_L,
E_err_North_req_X_L,
E_err_East_req_X_N,
E_err_West_req_X_E,
E_err_South_req_X_W,
E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N,
W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E,
W_err_North_req_X_E,
W_err_East_req_X_W,
W_err_West_req_X_S,
W_err_South_req_X_L,
W_err_Local_req_X_N,
W_err_IDLE_req_X_W,
W_err_North_req_X_W,
W_err_East_req_X_S,
W_err_West_req_X_L,
W_err_South_req_X_N,
W_err_Local_req_X_E,
W_err_IDLE_req_X_S,
W_err_North_req_X_S,
W_err_East_req_X_L,
W_err_West_req_X_N,
W_err_South_req_X_E,
W_err_Local_req_X_W,
W_err_IDLE_req_X_L,
W_err_North_req_X_L,
W_err_East_req_X_N,
W_err_West_req_X_E,
W_err_South_req_X_W,
W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants,
W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant,
W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N,
S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E,
S_err_North_req_X_E,
S_err_East_req_X_W,
S_err_West_req_X_S,
S_err_South_req_X_L,
S_err_Local_req_X_N,
S_err_IDLE_req_X_W,
S_err_North_req_X_W,
S_err_East_req_X_S,
S_err_West_req_X_L,
S_err_South_req_X_N,
S_err_Local_req_X_E,
S_err_IDLE_req_X_S,
S_err_North_req_X_S,
S_err_East_req_X_L,
S_err_West_req_X_N,
S_err_South_req_X_E,
S_err_Local_req_X_W,
S_err_IDLE_req_X_L,
S_err_North_req_X_L,
S_err_East_req_X_N,
S_err_West_req_X_E,
S_err_South_req_X_W,
S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants,
S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant,
S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant,
S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N,
L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E,
L_err_North_req_X_E,
L_err_East_req_X_W,
L_err_West_req_X_S,
L_err_South_req_X_L,
L_err_Local_req_X_N,
L_err_IDLE_req_X_W,
L_err_North_req_X_W,
L_err_East_req_X_S,
L_err_West_req_X_L,
L_err_South_req_X_N,
L_err_Local_req_X_E,
L_err_IDLE_req_X_S,
L_err_North_req_X_S,
L_err_East_req_X_L,
L_err_West_req_X_N,
L_err_South_req_X_E,
L_err_Local_req_X_W,
L_err_IDLE_req_X_L,
L_err_North_req_X_L,
L_err_East_req_X_N,
L_err_West_req_X_E,
L_err_South_req_X_W,
L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for grouping checkers to model turn/path faults
signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic;
signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic;
signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic;
signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic;
-- Just used temporarily for debugging purposes!
signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic;
signal Allocator_checkers_ORed : std_logic;
--signal turn_faults_sig : std_logic_vector(19 downto 0);
begin
-- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers
-- corresponding to that input are ORed together.
N_FIFO_checkers_ORed <= N_err_empty_full or
N_err_empty_read_en or
N_err_full_write_en or
N_err_state_in_onehot or
N_err_read_pointer_in_onehot or
N_err_write_pointer_in_onehot or
N_err_write_en_write_pointer or
N_err_not_write_en_write_pointer or
N_err_read_pointer_write_pointer_not_empty or
N_err_read_pointer_write_pointer_empty or
N_err_read_pointer_write_pointer_not_full or
N_err_read_pointer_write_pointer_full or
N_err_read_pointer_increment or
N_err_read_pointer_not_increment or
N_err_write_en or
N_err_not_write_en or
N_err_not_write_en1 or
N_err_not_write_en2 or
N_err_read_en_mismatch or
N_err_read_en_mismatch1 or
N_err_fake_credit_read_en_fake_credit_counter_in_increment or
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
N_err_fake_credit_read_en_credit_out or
N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
N_err_state_out_Idle_not_fault_out_not_fake_credit or
N_err_state_out_Idle_not_fault_out_not_fault_info_in or
N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
N_err_state_out_Idle_fault_out_fake_credit or
N_err_state_out_Idle_fault_out_state_in_Packet_drop or
N_err_state_out_Idle_fault_out_fault_info_in or
N_err_state_out_Idle_fault_out_faulty_packet_in or
N_err_state_out_Idle_not_health_info or
N_err_state_out_Idle_not_write_fake_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
N_err_state_out_Body_flit_valid_in_not_health_info or
N_err_state_out_Body_flit_not_fake_credit or
N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
N_err_state_out_Tail_flit_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
N_err_fault_info_fault_info_out_equal or
N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- East
E_FIFO_checkers_ORed <= E_err_empty_full or
E_err_empty_read_en or
E_err_full_write_en or
E_err_state_in_onehot or
E_err_read_pointer_in_onehot or
E_err_write_pointer_in_onehot or
E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_write_en or
E_err_not_write_en or
E_err_not_write_en1 or
E_err_not_write_en2 or
E_err_read_en_mismatch or
E_err_read_en_mismatch1 or
E_err_fake_credit_read_en_fake_credit_counter_in_increment or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
E_err_fake_credit_read_en_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
E_err_state_out_Idle_not_fault_out_not_fake_credit or
E_err_state_out_Idle_not_fault_out_not_fault_info_in or
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Idle_fault_out_fake_credit or
E_err_state_out_Idle_fault_out_state_in_Packet_drop or
E_err_state_out_Idle_fault_out_fault_info_in or
E_err_state_out_Idle_fault_out_faulty_packet_in or
E_err_state_out_Idle_not_health_info or
E_err_state_out_Idle_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
E_err_state_out_Body_flit_valid_in_not_health_info or
E_err_state_out_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
E_err_state_out_Tail_flit_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
E_err_fault_info_fault_info_out_equal or
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- West
W_FIFO_checkers_ORed <= W_err_empty_full or
W_err_empty_read_en or
W_err_full_write_en or
W_err_state_in_onehot or
W_err_read_pointer_in_onehot or
W_err_write_pointer_in_onehot or
W_err_write_en_write_pointer or
W_err_not_write_en_write_pointer or
W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or
W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or
W_err_read_pointer_increment or
W_err_read_pointer_not_increment or
W_err_write_en or
W_err_not_write_en or
W_err_not_write_en1 or
W_err_not_write_en2 or
W_err_read_en_mismatch or
W_err_read_en_mismatch1 or
W_err_fake_credit_read_en_fake_credit_counter_in_increment or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
W_err_fake_credit_read_en_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
W_err_state_out_Idle_not_fault_out_not_fake_credit or
W_err_state_out_Idle_not_fault_out_not_fault_info_in or
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Idle_fault_out_fake_credit or
W_err_state_out_Idle_fault_out_state_in_Packet_drop or
W_err_state_out_Idle_fault_out_fault_info_in or
W_err_state_out_Idle_fault_out_faulty_packet_in or
W_err_state_out_Idle_not_health_info or
W_err_state_out_Idle_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
W_err_state_out_Body_flit_valid_in_not_health_info or
W_err_state_out_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
W_err_state_out_Tail_flit_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
W_err_fault_info_fault_info_out_equal or
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- South
S_FIFO_checkers_ORed <= S_err_empty_full or
S_err_empty_read_en or
S_err_full_write_en or
S_err_state_in_onehot or
S_err_read_pointer_in_onehot or
S_err_write_pointer_in_onehot or
S_err_write_en_write_pointer or
S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or
S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or
S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or
S_err_read_pointer_not_increment or
S_err_write_en or
S_err_not_write_en or
S_err_not_write_en1 or
S_err_not_write_en2 or
S_err_read_en_mismatch or
S_err_read_en_mismatch1 or
S_err_fake_credit_read_en_fake_credit_counter_in_increment or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
S_err_fake_credit_read_en_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
S_err_state_out_Idle_not_fault_out_not_fake_credit or
S_err_state_out_Idle_not_fault_out_not_fault_info_in or
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Idle_fault_out_fake_credit or
S_err_state_out_Idle_fault_out_state_in_Packet_drop or
S_err_state_out_Idle_fault_out_fault_info_in or
S_err_state_out_Idle_fault_out_faulty_packet_in or
S_err_state_out_Idle_not_health_info or
S_err_state_out_Idle_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
S_err_state_out_Body_flit_valid_in_not_health_info or
S_err_state_out_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
S_err_state_out_Tail_flit_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
S_err_fault_info_fault_info_out_equal or
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- Local
L_FIFO_checkers_ORed <= L_err_empty_full or
L_err_empty_read_en or
L_err_full_write_en or
L_err_state_in_onehot or
L_err_read_pointer_in_onehot or
L_err_write_pointer_in_onehot or
L_err_write_en_write_pointer or
L_err_not_write_en_write_pointer or
L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or
L_err_read_pointer_write_pointer_not_full or
L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or
L_err_read_pointer_not_increment or
L_err_write_en or
L_err_not_write_en or
L_err_not_write_en1 or
L_err_not_write_en2 or
L_err_read_en_mismatch or
L_err_read_en_mismatch1 or
L_err_fake_credit_read_en_fake_credit_counter_in_increment or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
L_err_fake_credit_read_en_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
L_err_state_out_Idle_not_fault_out_not_fake_credit or
L_err_state_out_Idle_not_fault_out_not_fault_info_in or
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Idle_fault_out_fake_credit or
L_err_state_out_Idle_fault_out_state_in_Packet_drop or
L_err_state_out_Idle_fault_out_fault_info_in or
L_err_state_out_Idle_fault_out_faulty_packet_in or
L_err_state_out_Idle_not_health_info or
L_err_state_out_Idle_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
L_err_state_out_Body_flit_valid_in_not_health_info or
L_err_state_out_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
L_err_state_out_Tail_flit_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
L_err_fault_info_fault_info_out_equal or
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
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-- Just for debugging purposes of the checkers!
-- LBDR checker outputs ORed
-- North
-- Routing part checkers
N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_N1 or
N_err_dst_addr_cur_addr_not_N1 or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--N_err_header_not_empty_Req_L_in or -- added according to new design
N_err_header_not_empty_Req_N_in or
N_err_header_not_empty_Req_E_in or
N_err_header_not_empty_Req_W_in or
N_err_header_not_empty_Req_S_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
-- Cx_Reconf checkers
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- East
-- Routing part checkers
E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_dst_addr_cur_addr_E1 or
E_err_dst_addr_cur_addr_not_E1 or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--E_err_header_not_empty_Req_L_in or -- added according to new design
E_err_header_not_empty_Req_N_in or
E_err_header_not_empty_Req_E_in or
E_err_header_not_empty_Req_W_in or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
-- Cx_Reconf checkers
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- West
-- Routing part checkers
W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
W_err_dst_addr_cur_addr_E1 or
W_err_dst_addr_cur_addr_not_E1 or
W_err_dst_addr_cur_addr_W1 or
W_err_dst_addr_cur_addr_not_W1 or
W_err_dst_addr_cur_addr_S1 or
W_err_dst_addr_cur_addr_not_S1 or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--W_err_header_not_empty_Req_L_in or -- added according to new design
W_err_header_not_empty_Req_N_in or
W_err_header_not_empty_Req_E_in or
W_err_header_not_empty_Req_W_in or
W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
-- Cx_Reconf checkers
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- South
-- Routing part checkers
S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_dst_addr_cur_addr_S1 or
S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--S_err_header_not_empty_Req_L_in or -- added according to new design
S_err_header_not_empty_Req_N_in or
S_err_header_not_empty_Req_E_in or
S_err_header_not_empty_Req_W_in or
S_err_header_not_empty_Req_S_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
-- Cx_Reconf checkers
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- Local
-- Routing part checkers
L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
L_err_dst_addr_cur_addr_Req_L_in or
L_err_dst_addr_cur_addr_not_Req_L_in or
L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--L_err_header_not_empty_Req_L_in or -- added according to new design
L_err_header_not_empty_Req_N_in or
L_err_header_not_empty_Req_E_in or
L_err_header_not_empty_Req_W_in or
L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
-- Cx_Reconf checkers
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
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-- Allocator checker outputs ORed !
-- Allocator logic checker outputs
Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or
err_grant_N_E_sig_not_empty_E_grant_N_E or
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or
err_grant_N_W_sig_not_empty_W_grant_N_W or
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or
err_grant_N_S_sig_not_empty_S_grant_N_S or
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or
err_grant_N_L_sig_not_empty_L_grant_N_L or
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or
err_grant_E_N_sig_not_empty_N_grant_E_N or
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or
err_grant_E_E_sig_not_empty_E_grant_E_E or
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or
err_grant_E_W_sig_not_empty_W_grant_E_W or
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_E_S_sig_not_empty_S_grant_E_S or
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or
err_grant_E_L_sig_not_empty_L_grant_E_L or
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or
err_grant_W_N_sig_not_empty_N_grant_W_N or
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_W_E_sig_not_empty_E_grant_W_E or
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or
err_grant_W_W_sig_not_empty_W_grant_W_W or
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or
err_grant_W_S_sig_not_empty_S_grant_W_S or
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or
err_grant_W_L_sig_not_empty_L_grant_W_L or
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or
err_grant_S_N_sig_not_empty_N_grant_S_N or
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or
err_grant_S_E_sig_not_empty_E_grant_S_E or
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or
err_grant_S_W_sig_not_empty_W_grant_S_W or
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or
err_grant_S_S_sig_not_empty_S_grant_S_S or
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or
err_grant_S_L_sig_not_empty_L_grant_S_L or
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or
err_grant_L_N_sig_not_empty_N_grant_L_N or
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_L_E_sig_not_empty_E_grant_L_E or
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or
err_grant_L_W_sig_not_empty_W_grant_L_W or
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_grant_L_S_sig_not_empty_S_grant_L_S or
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or
err_grant_L_L_sig_not_empty_L_grant_L_L or
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or
err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or
err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or
err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal or
N_err_IDLE_Req_N or
N_err_IDLE_grant_N or
N_err_North_Req_N or
N_err_North_grant_N or
N_err_East_Req_E or
N_err_East_grant_E or
N_err_West_Req_W or
N_err_West_grant_W or
N_err_South_Req_S or
N_err_South_grant_S or
N_err_Local_Req_L or
N_err_Local_grant_L or
N_err_IDLE_Req_E or
N_err_IDLE_grant_E or
N_err_North_Req_E or
N_err_North_grant_E or
N_err_East_Req_W or
N_err_East_grant_W or
N_err_West_Req_S or
N_err_West_grant_S or
N_err_South_Req_L or
N_err_South_grant_L or
N_err_Local_Req_N or
N_err_Local_grant_N or
N_err_IDLE_Req_W or
N_err_IDLE_grant_W or
N_err_North_Req_W or
N_err_North_grant_W or
N_err_East_Req_S or
N_err_East_grant_S or
N_err_West_Req_L or
N_err_West_grant_L or
N_err_South_Req_N or
N_err_South_grant_N or
N_err_Local_Req_E or
N_err_Local_grant_E or
N_err_IDLE_Req_S or
N_err_IDLE_grant_S or
N_err_North_Req_S or
N_err_North_grant_S or
N_err_East_Req_L or
N_err_East_grant_L or
N_err_West_Req_N or
N_err_West_grant_N or
N_err_South_Req_E or
N_err_South_grant_E or
N_err_Local_Req_W or
N_err_Local_grant_W or
N_err_IDLE_Req_L or
N_err_IDLE_grant_L or
N_err_North_Req_L or
N_err_North_grant_L or
N_err_East_Req_N or
N_err_East_grant_N or
N_err_West_Req_E or
N_err_West_grant_E or
N_err_South_Req_W or
N_err_South_grant_W or
N_err_Local_Req_S or
N_err_Local_grant_S or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_N_grant_N or
N_err_no_Req_E_grant_E or
N_err_no_Req_W_grant_W or
N_err_no_Req_S_grant_S or
N_err_no_Req_L_grant_L or
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal or
E_err_IDLE_Req_N or
E_err_IDLE_grant_N or
E_err_North_Req_N or
E_err_North_grant_N or
E_err_East_Req_E or
E_err_East_grant_E or
E_err_West_Req_W or
E_err_West_grant_W or
E_err_South_Req_S or
E_err_South_grant_S or
E_err_Local_Req_L or
E_err_Local_grant_L or
E_err_IDLE_Req_E or
E_err_IDLE_grant_E or
E_err_North_Req_E or
E_err_North_grant_E or
E_err_East_Req_W or
E_err_East_grant_W or
E_err_West_Req_S or
E_err_West_grant_S or
E_err_South_Req_L or
E_err_South_grant_L or
E_err_Local_Req_N or
E_err_Local_grant_N or
E_err_IDLE_Req_W or
E_err_IDLE_grant_W or
E_err_North_Req_W or
E_err_North_grant_W or
E_err_East_Req_S or
E_err_East_grant_S or
E_err_West_Req_L or
E_err_West_grant_L or
E_err_South_Req_N or
E_err_South_grant_N or
E_err_Local_Req_E or
E_err_Local_grant_E or
E_err_IDLE_Req_S or
E_err_IDLE_grant_S or
E_err_North_Req_S or
E_err_North_grant_S or
E_err_East_Req_L or
E_err_East_grant_L or
E_err_West_Req_N or
E_err_West_grant_N or
E_err_South_Req_E or
E_err_South_grant_E or
E_err_Local_Req_W or
E_err_Local_grant_W or
E_err_IDLE_Req_L or
E_err_IDLE_grant_L or
E_err_North_Req_L or
E_err_North_grant_L or
E_err_East_Req_N or
E_err_East_grant_N or
E_err_West_Req_E or
E_err_West_grant_E or
E_err_South_Req_W or
E_err_South_grant_W or
E_err_Local_Req_S or
E_err_Local_grant_S or
E_err_state_in_onehot or
E_err_no_request_grants or
E_err_request_no_grants or
E_err_no_Req_N_grant_N or
E_err_no_Req_E_grant_E or
E_err_no_Req_W_grant_W or
E_err_no_Req_S_grant_S or
E_err_no_Req_L_grant_L or
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal or
W_err_IDLE_Req_N or
W_err_IDLE_grant_N or
W_err_North_Req_N or
W_err_North_grant_N or
W_err_East_Req_E or
W_err_East_grant_E or
W_err_West_Req_W or
W_err_West_grant_W or
W_err_South_Req_S or
W_err_South_grant_S or
W_err_Local_Req_L or
W_err_Local_grant_L or
W_err_IDLE_Req_E or
W_err_IDLE_grant_E or
W_err_North_Req_E or
W_err_North_grant_E or
W_err_East_Req_W or
W_err_East_grant_W or
W_err_West_Req_S or
W_err_West_grant_S or
W_err_South_Req_L or
W_err_South_grant_L or
W_err_Local_Req_N or
W_err_Local_grant_N or
W_err_IDLE_Req_W or
W_err_IDLE_grant_W or
W_err_North_Req_W or
W_err_North_grant_W or
W_err_East_Req_S or
W_err_East_grant_S or
W_err_West_Req_L or
W_err_West_grant_L or
W_err_South_Req_N or
W_err_South_grant_N or
W_err_Local_Req_E or
W_err_Local_grant_E or
W_err_IDLE_Req_S or
W_err_IDLE_grant_S or
W_err_North_Req_S or
W_err_North_grant_S or
W_err_East_Req_L or
W_err_East_grant_L or
W_err_West_Req_N or
W_err_West_grant_N or
W_err_South_Req_E or
W_err_South_grant_E or
W_err_Local_Req_W or
W_err_Local_grant_W or
W_err_IDLE_Req_L or
W_err_IDLE_grant_L or
W_err_North_Req_L or
W_err_North_grant_L or
W_err_East_Req_N or
W_err_East_grant_N or
W_err_West_Req_E or
W_err_West_grant_E or
W_err_South_Req_W or
W_err_South_grant_W or
W_err_Local_Req_S or
W_err_Local_grant_S or
W_err_state_in_onehot or
W_err_no_request_grants or
W_err_request_no_grants or
W_err_no_Req_N_grant_N or
W_err_no_Req_E_grant_E or
W_err_no_Req_W_grant_W or
W_err_no_Req_S_grant_S or
W_err_no_Req_L_grant_L or
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal or
S_err_IDLE_Req_N or
S_err_IDLE_grant_N or
S_err_North_Req_N or
S_err_North_grant_N or
S_err_East_Req_E or
S_err_East_grant_E or
S_err_West_Req_W or
S_err_West_grant_W or
S_err_South_Req_S or
S_err_South_grant_S or
S_err_Local_Req_L or
S_err_Local_grant_L or
S_err_IDLE_Req_E or
S_err_IDLE_grant_E or
S_err_North_Req_E or
S_err_North_grant_E or
S_err_East_Req_W or
S_err_East_grant_W or
S_err_West_Req_S or
S_err_West_grant_S or
S_err_South_Req_L or
S_err_South_grant_L or
S_err_Local_Req_N or
S_err_Local_grant_N or
S_err_IDLE_Req_W or
S_err_IDLE_grant_W or
S_err_North_Req_W or
S_err_North_grant_W or
S_err_East_Req_S or
S_err_East_grant_S or
S_err_West_Req_L or
S_err_West_grant_L or
S_err_South_Req_N or
S_err_South_grant_N or
S_err_Local_Req_E or
S_err_Local_grant_E or
S_err_IDLE_Req_S or
S_err_IDLE_grant_S or
S_err_North_Req_S or
S_err_North_grant_S or
S_err_East_Req_L or
S_err_East_grant_L or
S_err_West_Req_N or
S_err_West_grant_N or
S_err_South_Req_E or
S_err_South_grant_E or
S_err_Local_Req_W or
S_err_Local_grant_W or
S_err_IDLE_Req_L or
S_err_IDLE_grant_L or
S_err_North_Req_L or
S_err_North_grant_L or
S_err_East_Req_N or
S_err_East_grant_N or
S_err_West_Req_E or
S_err_West_grant_E or
S_err_South_Req_W or
S_err_South_grant_W or
S_err_Local_Req_S or
S_err_Local_grant_S or
S_err_state_in_onehot or
S_err_no_request_grants or
S_err_request_no_grants or
S_err_no_Req_N_grant_N or
S_err_no_Req_E_grant_E or
S_err_no_Req_W_grant_W or
S_err_no_Req_S_grant_S or
S_err_no_Req_L_grant_L or
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal or
L_err_IDLE_Req_N or
L_err_IDLE_grant_N or
L_err_North_Req_N or
L_err_North_grant_N or
L_err_East_Req_E or
L_err_East_grant_E or
L_err_West_Req_W or
L_err_West_grant_W or
L_err_South_Req_S or
L_err_South_grant_S or
L_err_Local_Req_L or
L_err_Local_grant_L or
L_err_IDLE_Req_E or
L_err_IDLE_grant_E or
L_err_North_Req_E or
L_err_North_grant_E or
L_err_East_Req_W or
L_err_East_grant_W or
L_err_West_Req_S or
L_err_West_grant_S or
L_err_South_Req_L or
L_err_South_grant_L or
L_err_Local_Req_N or
L_err_Local_grant_N or
L_err_IDLE_Req_W or
L_err_IDLE_grant_W or
L_err_North_Req_W or
L_err_North_grant_W or
L_err_East_Req_S or
L_err_East_grant_S or
L_err_West_Req_L or
L_err_West_grant_L or
L_err_South_Req_N or
L_err_South_grant_N or
L_err_Local_Req_E or
L_err_Local_grant_E or
L_err_IDLE_Req_S or
L_err_IDLE_grant_S or
L_err_North_Req_S or
L_err_North_grant_S or
L_err_East_Req_L or
L_err_East_grant_L or
L_err_West_Req_N or
L_err_West_grant_N or
L_err_South_Req_E or
L_err_South_grant_E or
L_err_Local_Req_W or
L_err_Local_grant_W or
L_err_IDLE_Req_L or
L_err_IDLE_grant_L or
L_err_North_Req_L or
L_err_North_grant_L or
L_err_East_Req_N or
L_err_East_grant_N or
L_err_West_Req_E or
L_err_West_grant_E or
L_err_South_Req_W or
L_err_South_grant_W or
L_err_Local_Req_S or
L_err_Local_grant_S or
L_err_state_in_onehot or
L_err_no_request_grants or
L_err_request_no_grants or
L_err_no_Req_N_grant_N or
L_err_no_Req_E_grant_E or
L_err_no_Req_W_grant_W or
L_err_no_Req_S_grant_S or
L_err_no_Req_L_grant_L or
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_IDLE_req_X_N or
N_err_North_req_X_N or
N_err_North_credit_not_zero_req_X_N_grant_N or
N_err_North_credit_zero_or_not_req_X_N_not_grant_N or
N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or
N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or
N_err_West_credit_zero_or_not_req_X_W_not_grant_W or
N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or
N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
N_err_IDLE_req_X_E or
N_err_North_req_X_E or
N_err_East_req_X_W or
N_err_West_req_X_S or
N_err_South_req_X_L or
N_err_Local_req_X_N or
N_err_IDLE_req_X_W or
N_err_North_req_X_W or
N_err_East_req_X_S or
N_err_West_req_X_L or
N_err_South_req_X_N or
N_err_Local_req_X_E or
N_err_IDLE_req_X_S or
N_err_North_req_X_S or
N_err_East_req_X_L or
N_err_West_req_X_N or
N_err_South_req_X_E or
N_err_Local_req_X_W or
N_err_IDLE_req_X_L or
N_err_North_req_X_L or
N_err_East_req_X_N or
N_err_West_req_X_E or
N_err_South_req_X_W or
N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_state_North_Invalid_Grant or
N_err_state_East_Invalid_Grant or
N_err_state_West_Invalid_Grant or
N_err_state_South_Invalid_Grant or
N_err_state_Local_Invalid_Grant or
N_err_Grants_onehot_or_all_zero or
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_IDLE_req_X_N or
E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or
E_err_North_credit_zero_or_not_req_X_N_not_grant_N or
E_err_East_req_X_E or
E_err_East_credit_not_zero_req_X_E_grant_E or
E_err_East_credit_zero_or_not_req_X_E_not_grant_E or
E_err_West_req_X_W or
E_err_West_credit_not_zero_req_X_W_grant_W or
E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or
E_err_South_credit_zero_or_not_req_X_S_not_grant_S or
E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
E_err_IDLE_req_X_E or
E_err_North_req_X_E or
E_err_East_req_X_W or
E_err_West_req_X_S or
E_err_South_req_X_L or
E_err_Local_req_X_N or
E_err_IDLE_req_X_W or
E_err_North_req_X_W or
E_err_East_req_X_S or
E_err_West_req_X_L or
E_err_South_req_X_N or
E_err_Local_req_X_E or
E_err_IDLE_req_X_S or
E_err_North_req_X_S or
E_err_East_req_X_L or
E_err_West_req_X_N or
E_err_South_req_X_E or
E_err_Local_req_X_W or
E_err_IDLE_req_X_L or
E_err_North_req_X_L or
E_err_East_req_X_N or
E_err_West_req_X_E or
E_err_South_req_X_W or
E_err_Local_req_X_S or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or
E_err_state_North_Invalid_Grant or
E_err_state_East_Invalid_Grant or
E_err_state_West_Invalid_Grant or
E_err_state_South_Invalid_Grant or
E_err_state_Local_Invalid_Grant or
E_err_Grants_onehot_or_all_zero or
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or
W_err_East_credit_zero_or_not_req_X_E_not_grant_E or
W_err_West_req_X_W or
W_err_West_credit_not_zero_req_X_W_grant_W or
W_err_West_credit_zero_or_not_req_X_W_not_grant_W or
W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or
W_err_South_credit_zero_or_not_req_X_S_not_grant_S or
W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
W_err_IDLE_req_X_E or
W_err_North_req_X_E or
W_err_East_req_X_W or
W_err_West_req_X_S or
W_err_South_req_X_L or
W_err_Local_req_X_N or
W_err_IDLE_req_X_W or
W_err_North_req_X_W or
W_err_East_req_X_S or
W_err_West_req_X_L or
W_err_South_req_X_N or
W_err_Local_req_X_E or
W_err_IDLE_req_X_S or
W_err_North_req_X_S or
W_err_East_req_X_L or
W_err_West_req_X_N or
W_err_South_req_X_E or
W_err_Local_req_X_W or
W_err_IDLE_req_X_L or
W_err_North_req_X_L or
W_err_East_req_X_N or
W_err_West_req_X_E or
W_err_South_req_X_W or
W_err_Local_req_X_S or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_state_North_Invalid_Grant or
W_err_state_East_Invalid_Grant or
W_err_state_West_Invalid_Grant or
W_err_state_South_Invalid_Grant or
W_err_state_Local_Invalid_Grant or
W_err_Grants_onehot_or_all_zero or
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_IDLE_req_X_N or
S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or
S_err_North_credit_zero_or_not_req_X_N_not_grant_N or
S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or
S_err_East_credit_zero_or_not_req_X_E_not_grant_E or
S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or
S_err_West_credit_zero_or_not_req_X_W_not_grant_W or
S_err_South_req_X_S or
S_err_South_credit_not_zero_req_X_S_grant_S or
S_err_South_credit_zero_or_not_req_X_S_not_grant_S or
S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
S_err_IDLE_req_X_E or
S_err_North_req_X_E or
S_err_East_req_X_W or
S_err_West_req_X_S or
S_err_South_req_X_L or
S_err_Local_req_X_N or
S_err_IDLE_req_X_W or
S_err_North_req_X_W or
S_err_East_req_X_S or
S_err_West_req_X_L or
S_err_South_req_X_N or
S_err_Local_req_X_E or
S_err_IDLE_req_X_S or
S_err_North_req_X_S or
S_err_East_req_X_L or
S_err_West_req_X_N or
S_err_South_req_X_E or
S_err_Local_req_X_W or
S_err_IDLE_req_X_L or
S_err_North_req_X_L or
S_err_East_req_X_N or
S_err_West_req_X_E or
S_err_South_req_X_W or
S_err_Local_req_X_S or
S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or
S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or
S_err_state_North_Invalid_Grant or
S_err_state_East_Invalid_Grant or
S_err_state_West_Invalid_Grant or
S_err_state_South_Invalid_Grant or
S_err_state_Local_Invalid_Grant or
S_err_Grants_onehot_or_all_zero or
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_IDLE_req_X_N or
L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or
L_err_North_credit_zero_or_not_req_X_N_not_grant_N or
L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or
L_err_East_credit_zero_or_not_req_X_E_not_grant_E or
L_err_West_req_X_W or
L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or
L_err_South_req_X_S or
L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or
L_err_Local_req_X_L or
L_err_Local_credit_not_zero_req_X_L_grant_L or
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
L_err_IDLE_req_X_E or
L_err_North_req_X_E or
L_err_East_req_X_W or
L_err_West_req_X_S or
L_err_South_req_X_L or
L_err_Local_req_X_N or
L_err_IDLE_req_X_W or
L_err_North_req_X_W or
L_err_East_req_X_S or
L_err_West_req_X_L or
L_err_South_req_X_N or
L_err_Local_req_X_E or
L_err_IDLE_req_X_S or
L_err_North_req_X_S or
L_err_East_req_X_L or
L_err_West_req_X_N or
L_err_South_req_X_E or
L_err_Local_req_X_W or
L_err_IDLE_req_X_L or
L_err_North_req_X_L or
L_err_East_req_X_N or
L_err_West_req_X_E or
L_err_South_req_X_W or
L_err_Local_req_X_S or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_state_North_Invalid_Grant or
L_err_state_East_Invalid_Grant or
L_err_state_West_Invalid_Grant or
L_err_state_South_Invalid_Grant or
L_err_state_Local_Invalid_Grant or
L_err_Grants_onehot_or_all_zero;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Turn fault checkers
-- FIFO
N2E_turn_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_E1 or
N_err_dst_addr_cur_addr_not_E1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_E_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or
N_err_East_Req_E or
N_err_East_grant_E or
N_err_IDLE_Req_E or
N_err_IDLE_grant_E or
N_err_North_Req_E or
N_err_North_grant_E or
N_err_Local_Req_E or
N_err_Local_grant_E or
N_err_South_Req_E or
N_err_South_grant_E or
N_err_West_Req_E or
N_err_West_grant_E or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_E_grant_E or
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_IDLE_req_X_N or
E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or
E_err_North_credit_zero_or_not_req_X_N_not_grant_N or
E_err_Local_req_X_N or
E_err_South_req_X_N or
E_err_West_req_X_N or
E_err_East_req_X_N or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or
E_err_Grants_onehot_or_all_zero or
W_err_South_req_X_N or
W_err_West_req_X_N or
W_err_East_req_X_N or
err_grant_E_N_sig_not_empty_N_grant_E_N or
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or
err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
N2W_turn_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_W1 or
N_err_dst_addr_cur_addr_not_W1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_W_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or
N_err_West_Req_W or
N_err_West_grant_W or
N_err_East_Req_W or
N_err_East_grant_W or
N_err_IDLE_Req_W or
N_err_IDLE_grant_W or
N_err_North_Req_W or
N_err_North_grant_W or
N_err_Local_Req_W or
N_err_Local_grant_W or
N_err_South_Req_W or
N_err_South_grant_W or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_W_grant_W or
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_Local_req_X_N or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_Grants_onehot_or_all_zero or
err_grant_W_N_sig_not_empty_N_grant_W_N or
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
E2N_turn_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_N_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or
E_err_IDLE_Req_N or
E_err_IDLE_grant_N or
E_err_North_Req_N or
E_err_North_grant_N or
E_err_Local_Req_N or
E_err_Local_grant_N or
E_err_South_Req_N or
E_err_South_grant_N or
E_err_West_Req_N or
E_err_West_grant_N or
E_err_East_Req_N or
E_err_East_grant_N or
E_err_state_in_onehot or
E_err_no_request_grants or
E_err_request_no_grants or
E_err_no_Req_N_grant_N or
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or
N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_IDLE_req_X_E or
N_err_North_req_X_E or
N_err_Local_req_X_E or
N_err_South_req_X_E or
N_err_West_req_X_E or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_Grants_onehot_or_all_zero or
err_grant_N_E_sig_not_empty_E_grant_N_E or
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or
err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or
err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
E2S_turn_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or
E_err_South_Req_S or
E_err_South_grant_S or
E_err_West_Req_S or
E_err_West_grant_S or
E_err_East_Req_S or
E_err_East_grant_S or
E_err_IDLE_Req_S or
E_err_IDLE_grant_S or
E_err_North_Req_S or
E_err_North_grant_S or
E_err_Local_Req_S or
E_err_Local_grant_S or
E_err_state_in_onehot or
E_err_no_request_grants or
E_err_request_no_grants or
E_err_no_Req_S_grant_S or
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or
S_err_East_credit_zero_or_not_req_X_E_not_grant_E or
S_err_IDLE_req_X_E or
S_err_North_req_X_E or
S_err_Local_req_X_E or
S_err_South_req_X_E or
S_err_West_req_X_E or
S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or
S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or
S_err_Grants_onehot_or_all_zero or
err_grant_S_E_sig_not_empty_E_grant_S_E or
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or
err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or
err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
W2N_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or
W_err_dst_addr_cur_addr_not_N1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
W_err_header_not_empty_Req_N_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or
W_err_IDLE_Req_N or
W_err_IDLE_grant_N or
W_err_North_Req_N or
W_err_North_grant_N or
W_err_Local_Req_N or
W_err_Local_grant_N or
W_err_South_Req_N or
W_err_South_grant_N or
W_err_West_Req_N or
W_err_West_grant_N or
W_err_East_Req_N or
W_err_East_grant_N or
W_err_state_in_onehot or
W_err_no_request_grants or
W_err_request_no_grants or
W_err_no_Req_N_grant_N or
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or
N_err_West_credit_zero_or_not_req_X_W_not_grant_W or
N_err_East_req_X_W or
N_err_IDLE_req_X_W or
N_err_North_req_X_W or
N_err_Local_req_X_W or
N_err_South_req_X_W or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_Grants_onehot_or_all_zero or
err_grant_N_W_sig_not_empty_W_grant_N_W or
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or
err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or
err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
W2S_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_S1 or
W_err_dst_addr_cur_addr_not_S1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or
W_err_South_Req_S or
W_err_South_grant_S or
W_err_West_Req_S or
W_err_West_grant_S or
W_err_East_Req_S or
W_err_East_grant_S or
W_err_IDLE_Req_S or
W_err_IDLE_grant_S or
W_err_North_Req_S or
W_err_North_grant_S or
W_err_Local_Req_S or
W_err_Local_grant_S or
W_err_state_in_onehot or
W_err_no_request_grants or
W_err_request_no_grants or
W_err_no_Req_S_grant_S or
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or
S_err_West_credit_zero_or_not_req_X_W_not_grant_W or
S_err_East_req_X_W or
S_err_IDLE_req_X_W or
S_err_North_req_X_W or
S_err_Local_req_X_W or
S_err_South_req_X_W or
S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or
S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or
S_err_Grants_onehot_or_all_zero or
err_grant_S_W_sig_not_empty_W_grant_S_W or
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or
err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or
err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2E_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
S_err_header_not_empty_Req_E_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or
S_err_East_Req_E or
S_err_East_grant_E or
S_err_IDLE_Req_E or
S_err_IDLE_grant_E or
S_err_North_Req_E or
S_err_North_grant_E or
S_err_Local_Req_E or
S_err_Local_grant_E or
S_err_South_Req_E or
S_err_South_grant_E or
S_err_West_Req_E or
S_err_West_grant_E or
S_err_state_in_onehot or
S_err_no_request_grants or
S_err_request_no_grants or
S_err_no_Req_E_grant_E or
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or
E_err_South_credit_zero_or_not_req_X_S_not_grant_S or
E_err_West_req_X_S or
E_err_East_req_X_S or
E_err_IDLE_req_X_S or
E_err_North_req_X_S or
E_err_Local_req_X_S or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or
E_err_Grants_onehot_or_all_zero or
err_grant_E_S_sig_not_empty_S_grant_E_S or
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or
err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or
err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
S2W_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
S_err_header_not_empty_Req_W_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or
S_err_West_Req_W or
S_err_West_grant_W or
S_err_East_Req_W or
S_err_East_grant_W or
S_err_IDLE_Req_W or
S_err_IDLE_grant_W or
S_err_North_Req_W or
S_err_North_grant_W or
S_err_Local_Req_W or
S_err_Local_grant_W or
S_err_South_Req_W or
S_err_South_grant_W or
S_err_state_in_onehot or
S_err_no_request_grants or
S_err_request_no_grants or
S_err_no_Req_W_grant_W or
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or
W_err_South_credit_zero_or_not_req_X_S_not_grant_S or
W_err_West_req_X_S or
W_err_East_req_X_S or
W_err_IDLE_req_X_S or
W_err_North_req_X_S or
W_err_Local_req_X_S or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_Grants_onehot_or_all_zero or
err_grant_W_S_sig_not_empty_S_grant_W_S or
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- Path fault checkers
-- FIFO
N2S_path_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_S1 or
N_err_dst_addr_cur_addr_not_S1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
N_err_header_not_empty_Req_S_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or
N_err_South_Req_S or
N_err_South_grant_S or
N_err_West_Req_S or
N_err_West_grant_S or
N_err_East_Req_S or
N_err_East_grant_S or
N_err_IDLE_Req_S or
N_err_IDLE_grant_S or
N_err_North_Req_S or
N_err_North_grant_S or
N_err_Local_Req_S or
N_err_Local_grant_S or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_S_grant_S or
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_IDLE_req_X_N or
S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or
S_err_North_credit_zero_or_not_req_X_N_not_grant_N or
S_err_Local_req_X_N or
S_err_South_req_X_N or
S_err_West_req_X_N or
S_err_East_req_X_N or
S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or
S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or
S_err_Grants_onehot_or_all_zero or
err_grant_S_N_sig_not_empty_N_grant_S_N or
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or
err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or
err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2N_path_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
S_err_header_not_empty_Req_N_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or
S_err_IDLE_Req_N or
S_err_IDLE_grant_N or
S_err_North_Req_N or
S_err_North_grant_N or
S_err_Local_Req_N or
S_err_Local_grant_N or
S_err_South_Req_N or
S_err_South_grant_N or
S_err_West_Req_N or
S_err_West_grant_N or
S_err_East_Req_N or
S_err_East_grant_N or
S_err_state_in_onehot or
S_err_no_request_grants or
S_err_request_no_grants or
S_err_no_Req_N_grant_N or
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or
N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_West_req_X_S or
N_err_East_req_X_S or
N_err_IDLE_req_X_S or
N_err_North_req_X_S or
N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_Grants_onehot_or_all_zero or
err_grant_N_S_sig_not_empty_S_grant_N_S or
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or
err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or
err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
E2W_path_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_W_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or
E_err_West_Req_W or
E_err_West_grant_W or
E_err_East_Req_W or
E_err_East_grant_W or
E_err_IDLE_Req_W or
E_err_IDLE_grant_W or
E_err_North_Req_W or
E_err_North_grant_W or
E_err_Local_Req_W or
E_err_Local_grant_W or
E_err_South_Req_W or
E_err_South_grant_W or
E_err_state_in_onehot or
E_err_no_request_grants or
E_err_request_no_grants or
E_err_no_Req_W_grant_W or
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or
W_err_East_credit_zero_or_not_req_X_E_not_grant_E or
W_err_IDLE_req_X_E or
W_err_North_req_X_E or
W_err_Local_req_X_E or
W_err_South_req_X_E or
W_err_West_req_X_E or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_Grants_onehot_or_all_zero or
err_grant_W_E_sig_not_empty_E_grant_W_E or
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
W2E_path_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_E1 or
W_err_dst_addr_cur_addr_not_E1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
W_err_header_not_empty_Req_E_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or
W_err_East_Req_E or
W_err_East_grant_E or
W_err_IDLE_Req_E or
W_err_IDLE_grant_E or
W_err_North_Req_E or
W_err_North_grant_E or
W_err_Local_Req_E or
W_err_Local_grant_E or
W_err_South_Req_E or
W_err_South_grant_E or
W_err_West_Req_E or
W_err_West_grant_E or
W_err_state_in_onehot or
W_err_no_request_grants or
W_err_request_no_grants or
W_err_no_Req_E_grant_E or
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_West_req_X_W or
E_err_West_credit_not_zero_req_X_W_grant_W or
E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_East_req_X_W or
E_err_IDLE_req_X_W or
E_err_North_req_X_W or
E_err_Local_req_X_W or
E_err_South_req_X_W or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or
E_err_Grants_onehot_or_all_zero or
err_grant_E_W_sig_not_empty_W_grant_E_W or
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- Checkers for Paths/turns from/to Local port
-- FIFO
L2N_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
L_err_header_not_empty_Req_N_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or
L_err_IDLE_Req_N or
L_err_IDLE_grant_N or
L_err_North_Req_N or
L_err_North_grant_N or
L_err_Local_Req_N or
L_err_Local_grant_N or
L_err_South_Req_N or
L_err_South_grant_N or
L_err_West_Req_N or
L_err_West_grant_N or
L_err_East_Req_N or
L_err_East_grant_N or
L_err_state_in_onehot or
L_err_no_request_grants or
L_err_request_no_grants or
L_err_no_Req_N_grant_N or
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
N_err_South_req_X_L or
N_err_West_req_X_L or
N_err_East_req_X_L or
N_err_IDLE_req_X_L or
N_err_North_req_X_L or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_Grants_onehot_or_all_zero or
err_grant_N_L_sig_not_empty_L_grant_N_L or
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or
err_grant_signals_not_empty_grant_N or
err_not_grant_signals_empty_not_grant_N or
err_grants_valid_not_match or
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal;
-- FIFO
L2E_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
L_err_header_not_empty_Req_E_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or
L_err_East_Req_E or
L_err_East_grant_E or
L_err_IDLE_Req_E or
L_err_IDLE_grant_E or
L_err_North_Req_E or
L_err_North_grant_E or
L_err_Local_Req_E or
L_err_Local_grant_E or
L_err_South_Req_E or
L_err_South_grant_E or
L_err_West_Req_E or
L_err_West_grant_E or
L_err_state_in_onehot or
L_err_no_request_grants or
L_err_request_no_grants or
L_err_no_Req_E_grant_E or
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
E_err_South_req_X_L or
E_err_West_req_X_L or
E_err_East_req_X_L or
E_err_IDLE_req_X_L or
E_err_North_req_X_L or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or
E_err_Grants_onehot_or_all_zero or
err_grant_E_L_sig_not_empty_L_grant_E_L or
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or
err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or
err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
L2W_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
L_err_header_not_empty_Req_W_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or
L_err_West_Req_W or
L_err_West_grant_W or
L_err_East_Req_W or
L_err_East_grant_W or
L_err_IDLE_Req_W or
L_err_IDLE_grant_W or
L_err_North_Req_W or
L_err_North_grant_W or
L_err_Local_Req_W or
L_err_Local_grant_W or
L_err_South_Req_W or
L_err_South_grant_W or
L_err_state_in_onehot or
L_err_no_request_grants or
L_err_request_no_grants or
L_err_no_Req_W_grant_W or
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
W_err_South_req_X_L or
W_err_West_req_X_L or
W_err_East_req_X_L or
W_err_IDLE_req_X_L or
W_err_North_req_X_L or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or
W_err_Grants_onehot_or_all_zero or
err_grant_W_L_sig_not_empty_L_grant_W_L or
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or
err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or
err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
L2S_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or
L_err_South_Req_S or
L_err_South_grant_S or
L_err_West_Req_S or
L_err_West_grant_S or
L_err_East_Req_S or
L_err_East_grant_S or
L_err_IDLE_Req_S or
L_err_IDLE_grant_S or
L_err_North_Req_S or
L_err_North_grant_S or
L_err_Local_Req_S or
L_err_Local_grant_S or
L_err_state_in_onehot or
L_err_no_request_grants or
L_err_request_no_grants or
L_err_no_Req_S_grant_S or
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
S_err_South_req_X_L or
S_err_West_req_X_L or
S_err_East_req_X_L or
S_err_IDLE_req_X_L or
S_err_North_req_X_L or
S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or
S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or
S_err_Grants_onehot_or_all_zero or
err_grant_S_L_sig_not_empty_L_grant_S_L or
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or
err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or
err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
N2L_fault <= N_FIFO_checkers_ORed or
-- LBDR
N_err_header_empty_Requests_FF_Requests_in or
N_err_tail_Requests_in_all_zero or
N_err_tail_empty_Requests_FF_Requests_in or
N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
N_err_grants_onehot or
N_err_grants_mismatch or
N_err_header_tail_Requests_FF_Requests_in or
N_err_dst_addr_cur_addr_Req_L_in or
N_err_dst_addr_cur_addr_not_Req_L_in or
N_err_header_not_empty_faulty_drop_packet_in or
N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
N_err_header_not_empty_faulty_Req_in_all_zero or
--N_err_header_not_empty_Req_L_in or
N_err_header_empty_packet_drop_in_packet_drop_equal or
N_err_tail_not_empty_packet_drop_not_packet_drop_in or
N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
N_err_packet_drop_order or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
N_err_Requests_state_in_state_not_equal or
N_err_Local_Req_L or
N_err_Local_grant_L or
N_err_South_Req_L or
N_err_South_grant_L or
N_err_West_Req_L or
N_err_West_grant_L or
N_err_East_Req_L or
N_err_East_grant_L or
N_err_IDLE_Req_L or
N_err_IDLE_grant_L or
N_err_North_Req_L or
N_err_North_grant_L or
N_err_state_in_onehot or
N_err_no_request_grants or
N_err_request_no_grants or
N_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_IDLE_req_X_N or
L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or
L_err_North_credit_zero_or_not_req_X_N_not_grant_N or
L_err_Local_req_X_N or
L_err_South_req_X_N or
L_err_West_req_X_N or
L_err_East_req_X_N or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_Grants_onehot_or_all_zero or
err_grant_L_N_sig_not_empty_N_grant_L_N or
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
E2L_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
--E_err_header_not_empty_Req_L_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or
E_err_Local_Req_L or
E_err_Local_grant_L or
E_err_South_Req_L or
E_err_South_grant_L or
E_err_West_Req_L or
E_err_West_grant_L or
E_err_East_Req_L or
E_err_East_grant_L or
E_err_IDLE_Req_L or
E_err_IDLE_grant_L or
E_err_North_Req_L or
E_err_North_grant_L or
E_err_state_in_onehot or
E_err_no_request_grants or
E_err_request_no_grants or
E_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or
L_err_East_credit_zero_or_not_req_X_E_not_grant_E or
L_err_IDLE_req_X_E or
L_err_North_req_X_E or
L_err_Local_req_X_E or
L_err_South_req_X_E or
L_err_West_req_X_E or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_Grants_onehot_or_all_zero or
err_grant_L_E_sig_not_empty_E_grant_L_E or
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or
err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
W2L_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or
--W_err_header_not_empty_Req_L_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or
W_err_Local_Req_L or
W_err_Local_grant_L or
W_err_South_Req_L or
W_err_South_grant_L or
W_err_West_Req_L or
W_err_West_grant_L or
W_err_East_Req_L or
W_err_East_grant_L or
W_err_IDLE_Req_L or
W_err_IDLE_grant_L or
W_err_North_Req_L or
W_err_North_grant_L or
W_err_state_in_onehot or
W_err_no_request_grants or
W_err_request_no_grants or
W_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_West_req_X_W or
L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or
L_err_East_req_X_W or
L_err_IDLE_req_X_W or
L_err_North_req_X_W or
L_err_Local_req_X_W or
L_err_South_req_X_W or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_Grants_onehot_or_all_zero or
err_grant_L_W_sig_not_empty_W_grant_L_W or
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
S2L_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
--S_err_header_not_empty_Req_L_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or
S_err_Local_Req_L or
S_err_Local_grant_L or
S_err_South_Req_L or
S_err_South_grant_L or
S_err_West_Req_L or
S_err_West_grant_L or
S_err_East_Req_L or
S_err_East_grant_L or
S_err_IDLE_Req_L or
S_err_IDLE_grant_L or
S_err_North_Req_L or
S_err_North_grant_L or
S_err_state_in_onehot or
S_err_no_request_grants or
S_err_request_no_grants or
S_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_South_req_X_S or
L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or
L_err_West_req_X_S or
L_err_East_req_X_S or
L_err_IDLE_req_X_S or
L_err_North_req_X_S or
L_err_Local_req_X_S or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or
L_err_Grants_onehot_or_all_zero or
err_grant_L_S_sig_not_empty_S_grant_L_S or
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or
err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
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-- Link faults and turn faults
-- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits
-- N2E, N2W, E2N, E2S,
-- W2N, W2S, S2E, S2W,
-- N2S, S2N, E2W, W2E,
-- L2N, L2E, L2W, L2S,
-- N2L, E2L, W2L, S2L
--turn_faults <= "00000000000000000000";
turn_faults <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault &
W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault &
N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault &
L2N_fault & L2E_fault & L2W_fault & L2S_fault &
N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults
link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
--link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
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-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
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-- all the Checker Counter Threshold modules
-- Turn faults
CHK_CT_N2E_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => N2E_turn_fault, Healthy => Healthy_N2E_turn_fault,
Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault);
CHK_CT_N2W_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => N2W_turn_fault, Healthy => Healthy_N2W_turn_fault,
Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault);
CHK_CT_E2N_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => E2N_turn_fault, Healthy => Healthy_E2N_turn_fault,
Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault);
CHK_CT_E2S_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => E2S_turn_fault, Healthy => Healthy_E2S_turn_fault,
Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault);
CHK_CT_W2N_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => W2N_turn_fault, Healthy => Healthy_W2N_turn_fault,
Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault);
CHK_CT_W2S_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => W2S_turn_fault, Healthy => Healthy_W2S_turn_fault,
Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault);
CHK_CT_S2E_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => S2E_turn_fault, Healthy => Healthy_S2E_turn_fault,
Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault);
CHK_CT_S2W_turn_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => S2W_turn_fault, Healthy => Healthy_S2W_turn_fault,
Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault);
--Path faults
CHK_CT_N2S_path_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => N2S_path_fault, Healthy => Healthy_N2S_path_fault,
Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault);
CHK_CT_S2N_path_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => S2N_path_fault, Healthy => Healthy_S2N_path_fault,
Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault);
CHK_CT_E2W_path_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => E2W_path_fault, Healthy => Healthy_E2W_path_fault,
Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault);
CHK_CT_W2E_path_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => W2E_path_fault, Healthy => Healthy_W2E_path_fault,
Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault);
-- Local port related faults (to/from local port)
CHK_CT_L2N_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => L2N_fault, Healthy => Healthy_L2N_fault,
Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault);
CHK_CT_L2E_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => L2E_fault, Healthy => Healthy_L2E_fault,
Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault);
CHK_CT_L2W_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => L2W_fault, Healthy => Healthy_L2W_fault,
Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault);
CHK_CT_L2S_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => L2S_fault, Healthy => Healthy_L2S_fault,
Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault);
CHK_CT_N2L_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => N2L_fault, Healthy => Healthy_N2L_fault,
Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault);
CHK_CT_E2L_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => E2L_fault, Healthy => Healthy_E2L_fault,
Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault);
CHK_CT_W2L_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => W2L_fault, Healthy => Healthy_W2L_fault,
Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault);
CHK_CT_S2L_fault: checkers_counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, data_input => S2L_fault, Healthy => Healthy_S2L_fault,
Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault);
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-- All the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N,
-- Checker outputs
-- Functional checkers
err_empty_full => N_err_empty_full,
err_empty_read_en => N_err_empty_read_en,
err_full_write_en => N_err_full_write_en,
err_state_in_onehot => N_err_state_in_onehot,
err_read_pointer_in_onehot => N_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => N_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => N_err_write_en_write_pointer,
err_not_write_en_write_pointer => N_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full,
err_read_pointer_increment => N_err_read_pointer_increment,
err_read_pointer_not_increment => N_err_read_pointer_not_increment,
err_write_en => N_err_write_en,
err_not_write_en => N_err_not_write_en,
err_not_write_en1 => N_err_not_write_en1,
err_not_write_en2 => N_err_not_write_en2,
err_read_en_mismatch => N_err_read_en_mismatch,
err_read_en_mismatch1 => N_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E,
-- Checker outputs
-- Functional checkers
err_empty_full => E_err_empty_full,
err_empty_read_en => E_err_empty_read_en,
err_full_write_en => E_err_full_write_en,
err_state_in_onehot => E_err_state_in_onehot,
err_read_pointer_in_onehot => E_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => E_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_write_en => E_err_write_en,
err_not_write_en => E_err_not_write_en,
err_not_write_en1 => E_err_not_write_en1,
err_not_write_en2 => E_err_not_write_en2,
err_read_en_mismatch => E_err_read_en_mismatch,
err_read_en_mismatch1 => E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W,
-- Checker outputs
-- Functional checkers
err_empty_full => W_err_empty_full,
err_empty_read_en => W_err_empty_read_en,
err_full_write_en => W_err_full_write_en,
err_state_in_onehot => W_err_state_in_onehot,
err_read_pointer_in_onehot => W_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => W_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_write_en => W_err_write_en,
err_not_write_en => W_err_not_write_en,
err_not_write_en1 => W_err_not_write_en1,
err_not_write_en2 => W_err_not_write_en2,
err_read_en_mismatch => W_err_read_en_mismatch,
err_read_en_mismatch1 => W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S,
-- Checker outputs
-- Functional checkers
err_empty_full => S_err_empty_full,
err_empty_read_en => S_err_empty_read_en,
err_full_write_en => S_err_full_write_en,
err_state_in_onehot => S_err_state_in_onehot,
err_read_pointer_in_onehot => S_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => S_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_write_en => S_err_not_write_en,
err_not_write_en1 => S_err_not_write_en1,
err_not_write_en2 => S_err_not_write_en2,
err_read_en_mismatch => S_err_read_en_mismatch,
err_read_en_mismatch1 => S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L,
-- Checker outputs
-- Functional checkers
err_empty_full => L_err_empty_full,
err_empty_read_en => L_err_empty_read_en,
err_full_write_en => L_err_full_write_en,
err_state_in_onehot => L_err_state_in_onehot,
err_read_pointer_in_onehot => L_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => L_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_write_en => L_err_not_write_en,
err_not_write_en1 => L_err_not_write_en1,
err_not_write_en2 => L_err_not_write_en2,
err_read_en_mismatch => L_err_read_en_mismatch,
err_read_en_mismatch1 => L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
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parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N);
parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
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--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => N_err_grants_onehot,
err_grants_mismatch => N_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => N_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => E_err_grants_onehot,
err_grants_mismatch => E_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => E_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => W_err_grants_onehot,
err_grants_mismatch => W_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => W_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => S_err_grants_onehot,
err_grants_mismatch => S_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => S_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => L_err_grants_onehot,
err_grants_mismatch => L_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => L_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
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-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL,
-- Checker outputs
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N ,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N ,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E ,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E ,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W ,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W ,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S ,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S ,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L ,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L ,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N ,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N ,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E ,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E ,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W ,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W ,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S ,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S ,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L ,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L ,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N ,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N ,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E ,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E ,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W ,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W ,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S ,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S ,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L ,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L ,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N ,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N ,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E ,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E ,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W ,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W ,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S ,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S ,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L ,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L ,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N ,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N ,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E ,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E ,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W ,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W ,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S ,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S ,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L ,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L ,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match ,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment ,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change ,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement ,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change ,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment ,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change ,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement ,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change ,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment ,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change ,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement ,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change ,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment ,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change ,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement ,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change ,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment ,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change ,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement ,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change ,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
-- North Arbiter_in Checker outputs
N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N => N_err_IDLE_Req_N,
N_err_IDLE_grant_N => N_err_IDLE_grant_N,
N_err_North_Req_N => N_err_North_Req_N,
N_err_North_grant_N => N_err_North_grant_N,
N_err_East_Req_E => N_err_East_Req_E,
N_err_East_grant_E => N_err_East_grant_E,
N_err_West_Req_W => N_err_West_Req_W,
N_err_West_grant_W => N_err_West_grant_W,
N_err_South_Req_S => N_err_South_Req_S,
N_err_South_grant_S => N_err_South_grant_S,
N_err_Local_Req_L => N_err_Local_Req_L,
N_err_Local_grant_L => N_err_Local_grant_L,
N_err_IDLE_Req_E => N_err_IDLE_Req_E,
N_err_IDLE_grant_E => N_err_IDLE_grant_E,
N_err_North_Req_E => N_err_North_Req_E,
N_err_North_grant_E => N_err_North_grant_E,
N_err_East_Req_W => N_err_East_Req_W,
N_err_East_grant_W => N_err_East_grant_W,
N_err_West_Req_S => N_err_West_Req_S,
N_err_West_grant_S => N_err_West_grant_S,
N_err_South_Req_L => N_err_South_Req_L,
N_err_South_grant_L => N_err_South_grant_L,
N_err_Local_Req_N => N_err_Local_Req_N,
N_err_Local_grant_N => N_err_Local_grant_N,
N_err_IDLE_Req_W => N_err_IDLE_Req_W,
N_err_IDLE_grant_W => N_err_IDLE_grant_W,
N_err_North_Req_W => N_err_North_Req_W,
N_err_North_grant_W => N_err_North_grant_W,
N_err_East_Req_S => N_err_East_Req_S,
N_err_East_grant_S => N_err_East_grant_S,
N_err_West_Req_L => N_err_West_Req_L,
N_err_West_grant_L => N_err_West_grant_L,
N_err_South_Req_N => N_err_South_Req_N,
N_err_South_grant_N => N_err_South_grant_N,
N_err_Local_Req_E => N_err_Local_Req_E,
N_err_Local_grant_E => N_err_Local_grant_E,
N_err_IDLE_Req_S => N_err_IDLE_Req_S,
N_err_IDLE_grant_S => N_err_IDLE_grant_S,
N_err_North_Req_S => N_err_North_Req_S,
N_err_North_grant_S => N_err_North_grant_S,
N_err_East_Req_L => N_err_East_Req_L,
N_err_East_grant_L => N_err_East_grant_L,
N_err_West_Req_N => N_err_West_Req_N,
N_err_West_grant_N => N_err_West_grant_N,
N_err_South_Req_E => N_err_South_Req_E,
N_err_South_grant_E => N_err_South_grant_E,
N_err_Local_Req_W => N_err_Local_Req_W,
N_err_Local_grant_W => N_err_Local_grant_W,
N_err_IDLE_Req_L => N_err_IDLE_Req_L,
N_err_IDLE_grant_L => N_err_IDLE_grant_L,
N_err_North_Req_L => N_err_North_Req_L,
N_err_North_grant_L => N_err_North_grant_L,
N_err_East_Req_N => N_err_East_Req_N,
N_err_East_grant_N => N_err_East_grant_N,
N_err_West_Req_E => N_err_West_Req_E,
N_err_West_grant_E => N_err_West_grant_E,
N_err_South_Req_W => N_err_South_Req_W,
N_err_South_grant_W => N_err_South_grant_W,
N_err_Local_Req_S => N_err_Local_Req_S,
N_err_Local_grant_S => N_err_Local_grant_S,
N_err_state_in_onehot => N_err_arbiter_state_in_onehot,
N_err_no_request_grants => N_err_no_request_grants,
N_err_request_no_grants => N_err_request_no_grants,
N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N,
N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W,
N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L,
-- East Arbiter_in Checker outputs
E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N => E_err_IDLE_Req_N,
E_err_IDLE_grant_N => E_err_IDLE_grant_N,
E_err_North_Req_N => E_err_North_Req_N,
E_err_North_grant_N => E_err_North_grant_N,
E_err_East_Req_E => E_err_East_Req_E,
E_err_East_grant_E => E_err_East_grant_E,
E_err_West_Req_W => E_err_West_Req_W,
E_err_West_grant_W => E_err_West_grant_W,
E_err_South_Req_S => E_err_South_Req_S,
E_err_South_grant_S => E_err_South_grant_S,
E_err_Local_Req_L => E_err_Local_Req_L,
E_err_Local_grant_L => E_err_Local_grant_L,
E_err_IDLE_Req_E => E_err_IDLE_Req_E,
E_err_IDLE_grant_E => E_err_IDLE_grant_E,
E_err_North_Req_E => E_err_North_Req_E,
E_err_North_grant_E => E_err_North_grant_E,
E_err_East_Req_W => E_err_East_Req_W,
E_err_East_grant_W => E_err_East_grant_W,
E_err_West_Req_S => E_err_West_Req_S,
E_err_West_grant_S => E_err_West_grant_S,
E_err_South_Req_L => E_err_South_Req_L,
E_err_South_grant_L => E_err_South_grant_L,
E_err_Local_Req_N => E_err_Local_Req_N,
E_err_Local_grant_N => E_err_Local_grant_N,
E_err_IDLE_Req_W => E_err_IDLE_Req_W,
E_err_IDLE_grant_W => E_err_IDLE_grant_W,
E_err_North_Req_W => E_err_North_Req_W,
E_err_North_grant_W => E_err_North_grant_W,
E_err_East_Req_S => E_err_East_Req_S,
E_err_East_grant_S => E_err_East_grant_S,
E_err_West_Req_L => E_err_West_Req_L,
E_err_West_grant_L => E_err_West_grant_L,
E_err_South_Req_N => E_err_South_Req_N,
E_err_South_grant_N => E_err_South_grant_N,
E_err_Local_Req_E => E_err_Local_Req_E,
E_err_Local_grant_E => E_err_Local_grant_E,
E_err_IDLE_Req_S => E_err_IDLE_Req_S,
E_err_IDLE_grant_S => E_err_IDLE_grant_S,
E_err_North_Req_S => E_err_North_Req_S,
E_err_North_grant_S => E_err_North_grant_S,
E_err_East_Req_L => E_err_East_Req_L,
E_err_East_grant_L => E_err_East_grant_L,
E_err_West_Req_N => E_err_West_Req_N,
E_err_West_grant_N => E_err_West_grant_N,
E_err_South_Req_E => E_err_South_Req_E,
E_err_South_grant_E => E_err_South_grant_E,
E_err_Local_Req_W => E_err_Local_Req_W,
E_err_Local_grant_W => E_err_Local_grant_W,
E_err_IDLE_Req_L => E_err_IDLE_Req_L,
E_err_IDLE_grant_L => E_err_IDLE_grant_L,
E_err_North_Req_L => E_err_North_Req_L,
E_err_North_grant_L => E_err_North_grant_L,
E_err_East_Req_N => E_err_East_Req_N,
E_err_East_grant_N => E_err_East_grant_N,
E_err_West_Req_E => E_err_West_Req_E,
E_err_West_grant_E => E_err_West_grant_E,
E_err_South_Req_W => E_err_South_Req_W,
E_err_South_grant_W => E_err_South_grant_W,
E_err_Local_Req_S => E_err_Local_Req_S,
E_err_Local_grant_S => E_err_Local_grant_S,
E_err_state_in_onehot => E_err_arbiter_state_in_onehot,
E_err_no_request_grants => E_err_no_request_grants,
E_err_request_no_grants => E_err_request_no_grants,
E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N,
E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W,
E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L,
-- West Arbiter_in Checker outputs
W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N => W_err_IDLE_Req_N,
W_err_IDLE_grant_N => W_err_IDLE_grant_N,
W_err_North_Req_N => W_err_North_Req_N,
W_err_North_grant_N => W_err_North_grant_N,
W_err_East_Req_E => W_err_East_Req_E,
W_err_East_grant_E => W_err_East_grant_E,
W_err_West_Req_W => W_err_West_Req_W,
W_err_West_grant_W => W_err_West_grant_W,
W_err_South_Req_S => W_err_South_Req_S,
W_err_South_grant_S => W_err_South_grant_S,
W_err_Local_Req_L => W_err_Local_Req_L,
W_err_Local_grant_L => W_err_Local_grant_L,
W_err_IDLE_Req_E => W_err_IDLE_Req_E,
W_err_IDLE_grant_E => W_err_IDLE_grant_E,
W_err_North_Req_E => W_err_North_Req_E,
W_err_North_grant_E => W_err_North_grant_E,
W_err_East_Req_W => W_err_East_Req_W,
W_err_East_grant_W => W_err_East_grant_W,
W_err_West_Req_S => W_err_West_Req_S,
W_err_West_grant_S => W_err_West_grant_S,
W_err_South_Req_L => W_err_South_Req_L,
W_err_South_grant_L => W_err_South_grant_L,
W_err_Local_Req_N => W_err_Local_Req_N,
W_err_Local_grant_N => W_err_Local_grant_N,
W_err_IDLE_Req_W => W_err_IDLE_Req_W,
W_err_IDLE_grant_W => W_err_IDLE_grant_W,
W_err_North_Req_W => W_err_North_Req_W,
W_err_North_grant_W => W_err_North_grant_W,
W_err_East_Req_S => W_err_East_Req_S,
W_err_East_grant_S => W_err_East_grant_S,
W_err_West_Req_L => W_err_West_Req_L,
W_err_West_grant_L => W_err_West_grant_L,
W_err_South_Req_N => W_err_South_Req_N,
W_err_South_grant_N => W_err_South_grant_N,
W_err_Local_Req_E => W_err_Local_Req_E,
W_err_Local_grant_E => W_err_Local_grant_E,
W_err_IDLE_Req_S => W_err_IDLE_Req_S,
W_err_IDLE_grant_S => W_err_IDLE_grant_S,
W_err_North_Req_S => W_err_North_Req_S,
W_err_North_grant_S => W_err_North_grant_S,
W_err_East_Req_L => W_err_East_Req_L,
W_err_East_grant_L => W_err_East_grant_L,
W_err_West_Req_N => W_err_West_Req_N,
W_err_West_grant_N => W_err_West_grant_N,
W_err_South_Req_E => W_err_South_Req_E,
W_err_South_grant_E => W_err_South_grant_E,
W_err_Local_Req_W => W_err_Local_Req_W,
W_err_Local_grant_W => W_err_Local_grant_W,
W_err_IDLE_Req_L => W_err_IDLE_Req_L,
W_err_IDLE_grant_L => W_err_IDLE_grant_L,
W_err_North_Req_L => W_err_North_Req_L,
W_err_North_grant_L => W_err_North_grant_L,
W_err_East_Req_N => W_err_East_Req_N,
W_err_East_grant_N => W_err_East_grant_N,
W_err_West_Req_E => W_err_West_Req_E,
W_err_West_grant_E => W_err_West_grant_E,
W_err_South_Req_W => W_err_South_Req_W,
W_err_South_grant_W => W_err_South_grant_W,
W_err_Local_Req_S => W_err_Local_Req_S,
W_err_Local_grant_S => W_err_Local_grant_S,
W_err_state_in_onehot => W_err_arbiter_state_in_onehot,
W_err_no_request_grants => W_err_no_request_grants,
W_err_request_no_grants => W_err_request_no_grants,
W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N,
W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W,
W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L,
-- South Arbiter_in Checker outputs
S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N => S_err_IDLE_Req_N,
S_err_IDLE_grant_N => S_err_IDLE_grant_N,
S_err_North_Req_N => S_err_North_Req_N,
S_err_North_grant_N => S_err_North_grant_N,
S_err_East_Req_E => S_err_East_Req_E,
S_err_East_grant_E => S_err_East_grant_E,
S_err_West_Req_W => S_err_West_Req_W,
S_err_West_grant_W => S_err_West_grant_W,
S_err_South_Req_S => S_err_South_Req_S,
S_err_South_grant_S => S_err_South_grant_S,
S_err_Local_Req_L => S_err_Local_Req_L,
S_err_Local_grant_L => S_err_Local_grant_L,
S_err_IDLE_Req_E => S_err_IDLE_Req_E,
S_err_IDLE_grant_E => S_err_IDLE_grant_E,
S_err_North_Req_E => S_err_North_Req_E,
S_err_North_grant_E => S_err_North_grant_E,
S_err_East_Req_W => S_err_East_Req_W,
S_err_East_grant_W => S_err_East_grant_W,
S_err_West_Req_S => S_err_West_Req_S,
S_err_West_grant_S => S_err_West_grant_S,
S_err_South_Req_L => S_err_South_Req_L,
S_err_South_grant_L => S_err_South_grant_L,
S_err_Local_Req_N => S_err_Local_Req_N,
S_err_Local_grant_N => S_err_Local_grant_N,
S_err_IDLE_Req_W => S_err_IDLE_Req_W,
S_err_IDLE_grant_W => S_err_IDLE_grant_W,
S_err_North_Req_W => S_err_North_Req_W,
S_err_North_grant_W => S_err_North_grant_W,
S_err_East_Req_S => S_err_East_Req_S,
S_err_East_grant_S => S_err_East_grant_S,
S_err_West_Req_L => S_err_West_Req_L,
S_err_West_grant_L => S_err_West_grant_L,
S_err_South_Req_N => S_err_South_Req_N,
S_err_South_grant_N => S_err_South_grant_N,
S_err_Local_Req_E => S_err_Local_Req_E,
S_err_Local_grant_E => S_err_Local_grant_E,
S_err_IDLE_Req_S => S_err_IDLE_Req_S,
S_err_IDLE_grant_S => S_err_IDLE_grant_S,
S_err_North_Req_S => S_err_North_Req_S,
S_err_North_grant_S => S_err_North_grant_S,
S_err_East_Req_L => S_err_East_Req_L,
S_err_East_grant_L => S_err_East_grant_L,
S_err_West_Req_N => S_err_West_Req_N,
S_err_West_grant_N => S_err_West_grant_N,
S_err_South_Req_E => S_err_South_Req_E,
S_err_South_grant_E => S_err_South_grant_E,
S_err_Local_Req_W => S_err_Local_Req_W,
S_err_Local_grant_W => S_err_Local_grant_W,
S_err_IDLE_Req_L => S_err_IDLE_Req_L,
S_err_IDLE_grant_L => S_err_IDLE_grant_L,
S_err_North_Req_L => S_err_North_Req_L,
S_err_North_grant_L => S_err_North_grant_L,
S_err_East_Req_N => S_err_East_Req_N,
S_err_East_grant_N => S_err_East_grant_N,
S_err_West_Req_E => S_err_West_Req_E,
S_err_West_grant_E => S_err_West_grant_E,
S_err_South_Req_W => S_err_South_Req_W,
S_err_South_grant_W => S_err_South_grant_W,
S_err_Local_Req_S => S_err_Local_Req_S,
S_err_Local_grant_S => S_err_Local_grant_S,
S_err_state_in_onehot => S_err_arbiter_state_in_onehot,
S_err_no_request_grants => S_err_no_request_grants,
S_err_request_no_grants => S_err_request_no_grants,
S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N,
S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W,
S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L,
-- Local Arbiter_in Checker outputs
L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N => L_err_IDLE_Req_N,
L_err_IDLE_grant_N => L_err_IDLE_grant_N,
L_err_North_Req_N => L_err_North_Req_N,
L_err_North_grant_N => L_err_North_grant_N,
L_err_East_Req_E => L_err_East_Req_E,
L_err_East_grant_E => L_err_East_grant_E,
L_err_West_Req_W => L_err_West_Req_W,
L_err_West_grant_W => L_err_West_grant_W,
L_err_South_Req_S => L_err_South_Req_S,
L_err_South_grant_S => L_err_South_grant_S,
L_err_Local_Req_L => L_err_Local_Req_L,
L_err_Local_grant_L => L_err_Local_grant_L,
L_err_IDLE_Req_E => L_err_IDLE_Req_E,
L_err_IDLE_grant_E => L_err_IDLE_grant_E,
L_err_North_Req_E => L_err_North_Req_E,
L_err_North_grant_E => L_err_North_grant_E,
L_err_East_Req_W => L_err_East_Req_W,
L_err_East_grant_W => L_err_East_grant_W,
L_err_West_Req_S => L_err_West_Req_S,
L_err_West_grant_S => L_err_West_grant_S,
L_err_South_Req_L => L_err_South_Req_L,
L_err_South_grant_L => L_err_South_grant_L,
L_err_Local_Req_N => L_err_Local_Req_N,
L_err_Local_grant_N => L_err_Local_grant_N,
L_err_IDLE_Req_W => L_err_IDLE_Req_W,
L_err_IDLE_grant_W => L_err_IDLE_grant_W,
L_err_North_Req_W => L_err_North_Req_W,
L_err_North_grant_W => L_err_North_grant_W,
L_err_East_Req_S => L_err_East_Req_S,
L_err_East_grant_S => L_err_East_grant_S,
L_err_West_Req_L => L_err_West_Req_L,
L_err_West_grant_L => L_err_West_grant_L,
L_err_South_Req_N => L_err_South_Req_N,
L_err_South_grant_N => L_err_South_grant_N,
L_err_Local_Req_E => L_err_Local_Req_E,
L_err_Local_grant_E => L_err_Local_grant_E,
L_err_IDLE_Req_S => L_err_IDLE_Req_S,
L_err_IDLE_grant_S => L_err_IDLE_grant_S,
L_err_North_Req_S => L_err_North_Req_S,
L_err_North_grant_S => L_err_North_grant_S,
L_err_East_Req_L => L_err_East_Req_L,
L_err_East_grant_L => L_err_East_grant_L,
L_err_West_Req_N => L_err_West_Req_N,
L_err_West_grant_N => L_err_West_grant_N,
L_err_South_Req_E => L_err_South_Req_E,
L_err_South_grant_E => L_err_South_grant_E,
L_err_Local_Req_W => L_err_Local_Req_W,
L_err_Local_grant_W => L_err_Local_grant_W,
L_err_IDLE_Req_L => L_err_IDLE_Req_L,
L_err_IDLE_grant_L => L_err_IDLE_grant_L,
L_err_North_Req_L => L_err_North_Req_L,
L_err_North_grant_L => L_err_North_grant_L,
L_err_East_Req_N => L_err_East_Req_N,
L_err_East_grant_N => L_err_East_grant_N,
L_err_West_Req_E => L_err_West_Req_E,
L_err_West_grant_E => L_err_West_grant_E,
L_err_South_Req_W => L_err_South_Req_W,
L_err_South_grant_W => L_err_South_grant_W,
L_err_Local_Req_S => L_err_Local_Req_S,
L_err_Local_grant_S => L_err_Local_grant_S,
L_err_state_in_onehot => L_err_arbiter_state_in_onehot,
L_err_no_request_grants => L_err_no_request_grants,
L_err_request_no_grants => L_err_request_no_grants,
L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N,
L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W,
L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N => N_err_IDLE_req_X_N,
N_err_North_req_X_N => N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E => N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W => N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S => N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L => N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E => N_err_IDLE_req_X_E,
N_err_North_req_X_E => N_err_North_req_X_E,
N_err_East_req_X_W => N_err_East_req_X_W,
N_err_West_req_X_S => N_err_West_req_X_S,
N_err_South_req_X_L => N_err_South_req_X_L,
N_err_Local_req_X_N => N_err_Local_req_X_N,
N_err_IDLE_req_X_W => N_err_IDLE_req_X_W,
N_err_North_req_X_W => N_err_North_req_X_W,
N_err_East_req_X_S => N_err_East_req_X_S,
N_err_West_req_X_L => N_err_West_req_X_L,
N_err_South_req_X_N => N_err_South_req_X_N,
N_err_Local_req_X_E => N_err_Local_req_X_E,
N_err_IDLE_req_X_S => N_err_IDLE_req_X_S,
N_err_North_req_X_S => N_err_North_req_X_S,
N_err_East_req_X_L => N_err_East_req_X_L,
N_err_West_req_X_N => N_err_West_req_X_N,
N_err_South_req_X_E => N_err_South_req_X_E,
N_err_Local_req_X_W => N_err_Local_req_X_W,
N_err_IDLE_req_X_L => N_err_IDLE_req_X_L,
N_err_North_req_X_L => N_err_North_req_X_L,
N_err_East_req_X_N => N_err_East_req_X_N,
N_err_West_req_X_E => N_err_West_req_X_E,
N_err_South_req_X_W => N_err_South_req_X_W,
N_err_Local_req_X_S => N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state => N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N => E_err_IDLE_req_X_N,
E_err_North_req_X_N => E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E => E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W => E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S => E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L => E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E => E_err_IDLE_req_X_E,
E_err_North_req_X_E => E_err_North_req_X_E,
E_err_East_req_X_W => E_err_East_req_X_W,
E_err_West_req_X_S => E_err_West_req_X_S,
E_err_South_req_X_L => E_err_South_req_X_L,
E_err_Local_req_X_N => E_err_Local_req_X_N,
E_err_IDLE_req_X_W => E_err_IDLE_req_X_W,
E_err_North_req_X_W => E_err_North_req_X_W,
E_err_East_req_X_S => E_err_East_req_X_S,
E_err_West_req_X_L => E_err_West_req_X_L,
E_err_South_req_X_N => E_err_South_req_X_N,
E_err_Local_req_X_E => E_err_Local_req_X_E,
E_err_IDLE_req_X_S => E_err_IDLE_req_X_S,
E_err_North_req_X_S => E_err_North_req_X_S,
E_err_East_req_X_L => E_err_East_req_X_L,
E_err_West_req_X_N => E_err_West_req_X_N,
E_err_South_req_X_E => E_err_South_req_X_E,
E_err_Local_req_X_W => E_err_Local_req_X_W,
E_err_IDLE_req_X_L => E_err_IDLE_req_X_L,
E_err_North_req_X_L => E_err_North_req_X_L,
E_err_East_req_X_N => E_err_East_req_X_N,
E_err_West_req_X_E => E_err_West_req_X_E,
E_err_South_req_X_W => E_err_South_req_X_W,
E_err_Local_req_X_S => E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state => E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N => W_err_IDLE_req_X_N,
W_err_North_req_X_N => W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E => W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W => W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S => W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L => W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E => W_err_IDLE_req_X_E,
W_err_North_req_X_E => W_err_North_req_X_E,
W_err_East_req_X_W => W_err_East_req_X_W,
W_err_West_req_X_S => W_err_West_req_X_S,
W_err_South_req_X_L => W_err_South_req_X_L,
W_err_Local_req_X_N => W_err_Local_req_X_N,
W_err_IDLE_req_X_W => W_err_IDLE_req_X_W,
W_err_North_req_X_W => W_err_North_req_X_W,
W_err_East_req_X_S => W_err_East_req_X_S,
W_err_West_req_X_L => W_err_West_req_X_L,
W_err_South_req_X_N => W_err_South_req_X_N,
W_err_Local_req_X_E => W_err_Local_req_X_E,
W_err_IDLE_req_X_S => W_err_IDLE_req_X_S,
W_err_North_req_X_S => W_err_North_req_X_S,
W_err_East_req_X_L => W_err_East_req_X_L,
W_err_West_req_X_N => W_err_West_req_X_N,
W_err_South_req_X_E => W_err_South_req_X_E,
W_err_Local_req_X_W => W_err_Local_req_X_W,
W_err_IDLE_req_X_L => W_err_IDLE_req_X_L,
W_err_North_req_X_L => W_err_North_req_X_L,
W_err_East_req_X_N => W_err_East_req_X_N,
W_err_West_req_X_E => W_err_West_req_X_E,
W_err_South_req_X_W => W_err_South_req_X_W,
W_err_Local_req_X_S => W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state => W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants,
W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant,
W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N => S_err_IDLE_req_X_N,
S_err_North_req_X_N => S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E => S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W => S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S => S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L => S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E => S_err_IDLE_req_X_E,
S_err_North_req_X_E => S_err_North_req_X_E,
S_err_East_req_X_W => S_err_East_req_X_W,
S_err_West_req_X_S => S_err_West_req_X_S,
S_err_South_req_X_L => S_err_South_req_X_L,
S_err_Local_req_X_N => S_err_Local_req_X_N,
S_err_IDLE_req_X_W => S_err_IDLE_req_X_W,
S_err_North_req_X_W => S_err_North_req_X_W,
S_err_East_req_X_S => S_err_East_req_X_S,
S_err_West_req_X_L => S_err_West_req_X_L,
S_err_South_req_X_N => S_err_South_req_X_N,
S_err_Local_req_X_E => S_err_Local_req_X_E,
S_err_IDLE_req_X_S => S_err_IDLE_req_X_S,
S_err_North_req_X_S => S_err_North_req_X_S,
S_err_East_req_X_L => S_err_East_req_X_L,
S_err_West_req_X_N => S_err_West_req_X_N,
S_err_South_req_X_E => S_err_South_req_X_E,
S_err_Local_req_X_W => S_err_Local_req_X_W,
S_err_IDLE_req_X_L => S_err_IDLE_req_X_L,
S_err_North_req_X_L => S_err_North_req_X_L,
S_err_East_req_X_N => S_err_East_req_X_N,
S_err_West_req_X_E => S_err_West_req_X_E,
S_err_South_req_X_W => S_err_South_req_X_W,
S_err_Local_req_X_S => S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state => S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants,
S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant,
S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant,
S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N => L_err_IDLE_req_X_N,
L_err_North_req_X_N => L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E => L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W => L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S => L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L => L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E => L_err_IDLE_req_X_E,
L_err_North_req_X_E => L_err_North_req_X_E,
L_err_East_req_X_W => L_err_East_req_X_W,
L_err_West_req_X_S => L_err_West_req_X_S,
L_err_South_req_X_L => L_err_South_req_X_L,
L_err_Local_req_X_N => L_err_Local_req_X_N,
L_err_IDLE_req_X_W => L_err_IDLE_req_X_W,
L_err_North_req_X_W => L_err_North_req_X_W,
L_err_East_req_X_S => L_err_East_req_X_S,
L_err_West_req_X_L => L_err_West_req_X_L,
L_err_South_req_X_N => L_err_South_req_X_N,
L_err_Local_req_X_E => L_err_Local_req_X_E,
L_err_IDLE_req_X_S => L_err_IDLE_req_X_S,
L_err_North_req_X_S => L_err_North_req_X_S,
L_err_East_req_X_L => L_err_East_req_X_L,
L_err_West_req_X_N => L_err_West_req_X_N,
L_err_South_req_X_E => L_err_South_req_X_E,
L_err_Local_req_X_W => L_err_Local_req_X_W,
L_err_IDLE_req_X_L => L_err_IDLE_req_X_L,
L_err_North_req_X_L => L_err_North_req_X_L,
L_err_East_req_X_N => L_err_East_req_X_N,
L_err_West_req_X_E => L_err_West_req_X_E,
L_err_South_req_X_W => L_err_South_req_X_W,
L_err_Local_req_X_S => L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state => L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
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-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/Allocator_with_checkers/allocator_with_checkers.vhd | 6 | 128714 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N,
N_err_IDLE_grant_N,
N_err_North_Req_N,
N_err_North_grant_N,
N_err_East_Req_E,
N_err_East_grant_E,
N_err_West_Req_W,
N_err_West_grant_W,
N_err_South_Req_S,
N_err_South_grant_S,
N_err_Local_Req_L,
N_err_Local_grant_L,
N_err_IDLE_Req_E,
N_err_IDLE_grant_E,
N_err_North_Req_E,
N_err_North_grant_E,
N_err_East_Req_W,
N_err_East_grant_W,
N_err_West_Req_S,
N_err_West_grant_S,
N_err_South_Req_L,
N_err_South_grant_L,
N_err_Local_Req_N,
N_err_Local_grant_N,
N_err_IDLE_Req_W,
N_err_IDLE_grant_W,
N_err_North_Req_W,
N_err_North_grant_W,
N_err_East_Req_S,
N_err_East_grant_S,
N_err_West_Req_L,
N_err_West_grant_L,
N_err_South_Req_N,
N_err_South_grant_N,
N_err_Local_Req_E,
N_err_Local_grant_E,
N_err_IDLE_Req_S,
N_err_IDLE_grant_S,
N_err_North_Req_S,
N_err_North_grant_S,
N_err_East_Req_L,
N_err_East_grant_L,
N_err_West_Req_N,
N_err_West_grant_N,
N_err_South_Req_E,
N_err_South_grant_E,
N_err_Local_Req_W,
N_err_Local_grant_W,
N_err_IDLE_Req_L,
N_err_IDLE_grant_L,
N_err_North_Req_L,
N_err_North_grant_L,
N_err_East_Req_N,
N_err_East_grant_N,
N_err_West_Req_E,
N_err_West_grant_E,
N_err_South_Req_W,
N_err_South_grant_W,
N_err_Local_Req_S,
N_err_Local_grant_S,
N_err_state_in_onehot,
N_err_no_request_grants,
N_err_request_no_grants,
N_err_no_Req_N_grant_N,
N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W,
N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N,
E_err_IDLE_grant_N,
E_err_North_Req_N,
E_err_North_grant_N,
E_err_East_Req_E,
E_err_East_grant_E,
E_err_West_Req_W,
E_err_West_grant_W,
E_err_South_Req_S,
E_err_South_grant_S,
E_err_Local_Req_L,
E_err_Local_grant_L,
E_err_IDLE_Req_E,
E_err_IDLE_grant_E,
E_err_North_Req_E,
E_err_North_grant_E,
E_err_East_Req_W,
E_err_East_grant_W,
E_err_West_Req_S,
E_err_West_grant_S,
E_err_South_Req_L,
E_err_South_grant_L,
E_err_Local_Req_N,
E_err_Local_grant_N,
E_err_IDLE_Req_W,
E_err_IDLE_grant_W,
E_err_North_Req_W,
E_err_North_grant_W,
E_err_East_Req_S,
E_err_East_grant_S,
E_err_West_Req_L,
E_err_West_grant_L,
E_err_South_Req_N,
E_err_South_grant_N,
E_err_Local_Req_E,
E_err_Local_grant_E,
E_err_IDLE_Req_S,
E_err_IDLE_grant_S,
E_err_North_Req_S,
E_err_North_grant_S,
E_err_East_Req_L,
E_err_East_grant_L,
E_err_West_Req_N,
E_err_West_grant_N,
E_err_South_Req_E,
E_err_South_grant_E,
E_err_Local_Req_W,
E_err_Local_grant_W,
E_err_IDLE_Req_L,
E_err_IDLE_grant_L,
E_err_North_Req_L,
E_err_North_grant_L,
E_err_East_Req_N,
E_err_East_grant_N,
E_err_West_Req_E,
E_err_West_grant_E,
E_err_South_Req_W,
E_err_South_grant_W,
E_err_Local_Req_S,
E_err_Local_grant_S,
E_err_state_in_onehot,
E_err_no_request_grants,
E_err_request_no_grants,
E_err_no_Req_N_grant_N,
E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W,
E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N,
W_err_IDLE_grant_N,
W_err_North_Req_N,
W_err_North_grant_N,
W_err_East_Req_E,
W_err_East_grant_E,
W_err_West_Req_W,
W_err_West_grant_W,
W_err_South_Req_S,
W_err_South_grant_S,
W_err_Local_Req_L,
W_err_Local_grant_L,
W_err_IDLE_Req_E,
W_err_IDLE_grant_E,
W_err_North_Req_E,
W_err_North_grant_E,
W_err_East_Req_W,
W_err_East_grant_W,
W_err_West_Req_S,
W_err_West_grant_S,
W_err_South_Req_L,
W_err_South_grant_L,
W_err_Local_Req_N,
W_err_Local_grant_N,
W_err_IDLE_Req_W,
W_err_IDLE_grant_W,
W_err_North_Req_W,
W_err_North_grant_W,
W_err_East_Req_S,
W_err_East_grant_S,
W_err_West_Req_L,
W_err_West_grant_L,
W_err_South_Req_N,
W_err_South_grant_N,
W_err_Local_Req_E,
W_err_Local_grant_E,
W_err_IDLE_Req_S,
W_err_IDLE_grant_S,
W_err_North_Req_S,
W_err_North_grant_S,
W_err_East_Req_L,
W_err_East_grant_L,
W_err_West_Req_N,
W_err_West_grant_N,
W_err_South_Req_E,
W_err_South_grant_E,
W_err_Local_Req_W,
W_err_Local_grant_W,
W_err_IDLE_Req_L,
W_err_IDLE_grant_L,
W_err_North_Req_L,
W_err_North_grant_L,
W_err_East_Req_N,
W_err_East_grant_N,
W_err_West_Req_E,
W_err_West_grant_E,
W_err_South_Req_W,
W_err_South_grant_W,
W_err_Local_Req_S,
W_err_Local_grant_S,
W_err_state_in_onehot,
W_err_no_request_grants,
W_err_request_no_grants,
W_err_no_Req_N_grant_N,
W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W,
W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N,
S_err_IDLE_grant_N,
S_err_North_Req_N,
S_err_North_grant_N,
S_err_East_Req_E,
S_err_East_grant_E,
S_err_West_Req_W,
S_err_West_grant_W,
S_err_South_Req_S,
S_err_South_grant_S,
S_err_Local_Req_L,
S_err_Local_grant_L,
S_err_IDLE_Req_E,
S_err_IDLE_grant_E,
S_err_North_Req_E,
S_err_North_grant_E,
S_err_East_Req_W,
S_err_East_grant_W,
S_err_West_Req_S,
S_err_West_grant_S,
S_err_South_Req_L,
S_err_South_grant_L,
S_err_Local_Req_N,
S_err_Local_grant_N,
S_err_IDLE_Req_W,
S_err_IDLE_grant_W,
S_err_North_Req_W,
S_err_North_grant_W,
S_err_East_Req_S,
S_err_East_grant_S,
S_err_West_Req_L,
S_err_West_grant_L,
S_err_South_Req_N,
S_err_South_grant_N,
S_err_Local_Req_E,
S_err_Local_grant_E,
S_err_IDLE_Req_S,
S_err_IDLE_grant_S,
S_err_North_Req_S,
S_err_North_grant_S,
S_err_East_Req_L,
S_err_East_grant_L,
S_err_West_Req_N,
S_err_West_grant_N,
S_err_South_Req_E,
S_err_South_grant_E,
S_err_Local_Req_W,
S_err_Local_grant_W,
S_err_IDLE_Req_L,
S_err_IDLE_grant_L,
S_err_North_Req_L,
S_err_North_grant_L,
S_err_East_Req_N,
S_err_East_grant_N,
S_err_West_Req_E,
S_err_West_grant_E,
S_err_South_Req_W,
S_err_South_grant_W,
S_err_Local_Req_S,
S_err_Local_grant_S,
S_err_state_in_onehot,
S_err_no_request_grants,
S_err_request_no_grants,
S_err_no_Req_N_grant_N,
S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W,
S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N,
L_err_IDLE_grant_N,
L_err_North_Req_N,
L_err_North_grant_N,
L_err_East_Req_E,
L_err_East_grant_E,
L_err_West_Req_W,
L_err_West_grant_W,
L_err_South_Req_S,
L_err_South_grant_S,
L_err_Local_Req_L,
L_err_Local_grant_L,
L_err_IDLE_Req_E,
L_err_IDLE_grant_E,
L_err_North_Req_E,
L_err_North_grant_E,
L_err_East_Req_W,
L_err_East_grant_W,
L_err_West_Req_S,
L_err_West_grant_S,
L_err_South_Req_L,
L_err_South_grant_L,
L_err_Local_Req_N,
L_err_Local_grant_N,
L_err_IDLE_Req_W,
L_err_IDLE_grant_W,
L_err_North_Req_W,
L_err_North_grant_W,
L_err_East_Req_S,
L_err_East_grant_S,
L_err_West_Req_L,
L_err_West_grant_L,
L_err_South_Req_N,
L_err_South_grant_N,
L_err_Local_Req_E,
L_err_Local_grant_E,
L_err_IDLE_Req_S,
L_err_IDLE_grant_S,
L_err_North_Req_S,
L_err_North_grant_S,
L_err_East_Req_L,
L_err_East_grant_L,
L_err_West_Req_N,
L_err_West_grant_N,
L_err_South_Req_E,
L_err_South_grant_E,
L_err_Local_Req_W,
L_err_Local_grant_W,
L_err_IDLE_Req_L,
L_err_IDLE_grant_L,
L_err_North_Req_L,
L_err_North_grant_L,
L_err_East_Req_N,
L_err_East_grant_N,
L_err_West_Req_E,
L_err_West_grant_E,
L_err_South_Req_W,
L_err_South_grant_W,
L_err_Local_Req_S,
L_err_Local_grant_S,
L_err_state_in_onehot,
L_err_no_request_grants,
L_err_request_no_grants,
L_err_no_Req_N_grant_N,
L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W,
L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E,
N_err_North_req_X_E,
N_err_East_req_X_W,
N_err_West_req_X_S,
N_err_South_req_X_L,
N_err_Local_req_X_N,
N_err_IDLE_req_X_W,
N_err_North_req_X_W,
N_err_East_req_X_S,
N_err_West_req_X_L,
N_err_South_req_X_N,
N_err_Local_req_X_E,
N_err_IDLE_req_X_S,
N_err_North_req_X_S,
N_err_East_req_X_L,
N_err_West_req_X_N,
N_err_South_req_X_E,
N_err_Local_req_X_W,
N_err_IDLE_req_X_L,
N_err_North_req_X_L,
N_err_East_req_X_N,
N_err_West_req_X_E,
N_err_South_req_X_W,
N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E,
E_err_North_req_X_E,
E_err_East_req_X_W,
E_err_West_req_X_S,
E_err_South_req_X_L,
E_err_Local_req_X_N,
E_err_IDLE_req_X_W,
E_err_North_req_X_W,
E_err_East_req_X_S,
E_err_West_req_X_L,
E_err_South_req_X_N,
E_err_Local_req_X_E,
E_err_IDLE_req_X_S,
E_err_North_req_X_S,
E_err_East_req_X_L,
E_err_West_req_X_N,
E_err_South_req_X_E,
E_err_Local_req_X_W,
E_err_IDLE_req_X_L,
E_err_North_req_X_L,
E_err_East_req_X_N,
E_err_West_req_X_E,
E_err_South_req_X_W,
E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N,
W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E,
W_err_North_req_X_E,
W_err_East_req_X_W,
W_err_West_req_X_S,
W_err_South_req_X_L,
W_err_Local_req_X_N,
W_err_IDLE_req_X_W,
W_err_North_req_X_W,
W_err_East_req_X_S,
W_err_West_req_X_L,
W_err_South_req_X_N,
W_err_Local_req_X_E,
W_err_IDLE_req_X_S,
W_err_North_req_X_S,
W_err_East_req_X_L,
W_err_West_req_X_N,
W_err_South_req_X_E,
W_err_Local_req_X_W,
W_err_IDLE_req_X_L,
W_err_North_req_X_L,
W_err_East_req_X_N,
W_err_West_req_X_E,
W_err_South_req_X_W,
W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants,
W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant,
W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N,
S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E,
S_err_North_req_X_E,
S_err_East_req_X_W,
S_err_West_req_X_S,
S_err_South_req_X_L,
S_err_Local_req_X_N,
S_err_IDLE_req_X_W,
S_err_North_req_X_W,
S_err_East_req_X_S,
S_err_West_req_X_L,
S_err_South_req_X_N,
S_err_Local_req_X_E,
S_err_IDLE_req_X_S,
S_err_North_req_X_S,
S_err_East_req_X_L,
S_err_West_req_X_N,
S_err_South_req_X_E,
S_err_Local_req_X_W,
S_err_IDLE_req_X_L,
S_err_North_req_X_L,
S_err_East_req_X_N,
S_err_West_req_X_E,
S_err_South_req_X_W,
S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants,
S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant,
S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant,
S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N,
L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E,
L_err_North_req_X_E,
L_err_East_req_X_W,
L_err_West_req_X_S,
L_err_South_req_X_L,
L_err_Local_req_X_N,
L_err_IDLE_req_X_W,
L_err_North_req_X_W,
L_err_East_req_X_S,
L_err_West_req_X_L,
L_err_South_req_X_N,
L_err_Local_req_X_E,
L_err_IDLE_req_X_S,
L_err_North_req_X_S,
L_err_East_req_X_L,
L_err_West_req_X_N,
L_err_South_req_X_E,
L_err_Local_req_X_W,
L_err_IDLE_req_X_L,
L_err_North_req_X_L,
L_err_East_req_X_N,
L_err_West_req_X_E,
L_err_South_req_X_W,
L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : out std_logic
);
end allocator;
architecture behavior of allocator is
-- so the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic;
signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic;
signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic;
signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic;
signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic;
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
signal valid_N_sig, valid_E_sig, valid_W_sig, valid_S_sig, valid_L_sig : std_logic;
signal grant_N_N_signal, grant_N_E_signal, grant_N_W_signal, grant_N_S_signal, grant_N_L_signal: std_logic;
signal grant_E_N_signal, grant_E_E_signal, grant_E_W_signal, grant_E_S_signal, grant_E_L_signal: std_logic;
signal grant_W_N_signal, grant_W_E_signal, grant_W_W_signal, grant_W_S_signal, grant_W_L_signal: std_logic;
signal grant_S_N_signal, grant_S_E_signal, grant_S_W_signal, grant_S_S_signal, grant_S_L_signal: std_logic;
signal grant_L_N_signal, grant_L_E_signal, grant_L_W_signal, grant_L_S_signal, grant_L_L_signal: std_logic;
-- Allocator logic checker outputs and allocator credit counter logic checker outputs go directly to the output interface of Allocator
component Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
component arbiter_out is
port ( reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y:in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L :out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
-- Checker modules
component allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
component allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
-- Not complete yet !
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end component;
begin
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= (others=>'1');
credit_counter_E_out <= (others=>'1');
credit_counter_W_out <= (others=>'1');
credit_counter_S_out <= (others=>'1');
credit_counter_L_out <= (others=>'1');
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
end if;
end process;
-- The combionational part
-- We did this because of the checkers
valid_N <= valid_N_sig;
valid_E <= valid_E_sig;
valid_W <= valid_W_sig;
valid_S <= valid_S_sig;
valid_L <= valid_L_sig;
grant_N_N <= grant_N_N_signal;
grant_E_N <= grant_E_N_signal;
grant_W_N <= grant_W_N_signal;
grant_S_N <= grant_S_N_signal;
grant_L_N <= grant_L_N_signal;
grant_N_E <= grant_N_E_signal;
grant_E_E <= grant_E_E_signal;
grant_W_E <= grant_W_E_signal;
grant_S_E <= grant_S_E_signal;
grant_L_E <= grant_L_E_signal;
grant_N_W <= grant_N_W_signal;
grant_E_W <= grant_E_W_signal;
grant_W_W <= grant_W_W_signal;
grant_S_W <= grant_S_W_signal;
grant_L_W <= grant_L_W_signal;
grant_N_S <= grant_N_S_signal;
grant_E_S <= grant_E_S_signal;
grant_W_S <= grant_W_S_signal;
grant_S_S <= grant_S_S_signal;
grant_L_S <= grant_L_S_signal;
grant_N_L <= grant_N_L_signal;
grant_E_L <= grant_E_L_signal;
grant_W_L <= grant_W_L_signal;
grant_S_L <= grant_S_L_signal;
grant_L_L <= grant_L_L_signal;
-- Taking Arbiter_in checker outputs to outputs of Allocator
grant_N_N_signal <= grant_N_N_sig and not empty_N;
grant_N_E_signal <= grant_N_E_sig and not empty_E;
grant_N_W_signal <= grant_N_W_sig and not empty_W;
grant_N_S_signal <= grant_N_S_sig and not empty_S;
grant_N_L_signal <= grant_N_L_sig and not empty_L;
grant_E_N_signal <= grant_E_N_sig and not empty_N;
grant_E_E_signal <= grant_E_E_sig and not empty_E;
grant_E_W_signal <= grant_E_W_sig and not empty_W;
grant_E_S_signal <= grant_E_S_sig and not empty_S;
grant_E_L_signal <= grant_E_L_sig and not empty_L;
grant_W_N_signal <= grant_W_N_sig and not empty_N;
grant_W_E_signal <= grant_W_E_sig and not empty_E;
grant_W_W_signal <= grant_W_W_sig and not empty_W;
grant_W_S_signal <= grant_W_S_sig and not empty_S;
grant_W_L_signal <= grant_W_L_sig and not empty_L;
grant_S_N_signal <= grant_S_N_sig and not empty_N;
grant_S_E_signal <= grant_S_E_sig and not empty_E;
grant_S_W_signal <= grant_S_W_sig and not empty_W;
grant_S_S_signal <= grant_S_S_sig and not empty_S;
grant_S_L_signal <= grant_S_L_sig and not empty_L;
grant_L_N_signal <= grant_L_N_sig and not empty_N;
grant_L_E_signal <= grant_L_E_sig and not empty_E;
grant_L_W_signal <= grant_L_W_sig and not empty_W;
grant_L_S_signal <= grant_L_S_sig and not empty_S;
grant_L_L_signal <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
-- this process handles the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Allocator logic checkers module instantiation
ALLOCATOR_LOGIC_CHECKERS: allocator_logic_pseudo_checkers PORT MAP (
empty_N => empty_N,
empty_E => empty_E,
empty_W => empty_W,
empty_S => empty_S,
empty_L => empty_L,
grant_N_N_sig => grant_N_N_sig, grant_N_E_sig => grant_N_E_sig, grant_N_W_sig => grant_N_W_sig, grant_N_S_sig => grant_N_S_sig, grant_N_L_sig => grant_N_L_sig,
grant_E_N_sig => grant_E_N_sig, grant_E_E_sig => grant_E_E_sig, grant_E_W_sig => grant_E_W_sig, grant_E_S_sig => grant_E_S_sig, grant_E_L_sig => grant_E_L_sig,
grant_W_N_sig => grant_W_N_sig, grant_W_E_sig => grant_W_E_sig, grant_W_W_sig => grant_W_W_sig, grant_W_S_sig => grant_W_S_sig, grant_W_L_sig => grant_W_L_sig,
grant_S_N_sig => grant_S_N_sig, grant_S_E_sig => grant_S_E_sig, grant_S_W_sig => grant_S_W_sig, grant_S_S_sig => grant_S_S_sig, grant_S_L_sig => grant_S_L_sig,
grant_L_N_sig => grant_L_N_sig, grant_L_E_sig => grant_L_E_sig, grant_L_W_sig => grant_L_W_sig, grant_L_S_sig => grant_L_S_sig, grant_L_L_sig => grant_L_L_sig,
valid_N => valid_N_sig,
valid_E => valid_E_sig,
valid_W => valid_W_sig,
valid_S => valid_S_sig,
valid_L => valid_L_sig,
grant_N_N => grant_N_N_signal,
grant_N_E => grant_N_E_signal,
grant_N_W => grant_N_W_signal,
grant_N_S => grant_N_S_signal,
grant_N_L => grant_N_L_signal,
grant_E_N => grant_E_N_signal,
grant_E_E => grant_E_E_signal,
grant_E_W => grant_E_W_signal,
grant_E_S => grant_E_S_signal,
grant_E_L => grant_E_L_signal,
grant_W_N => grant_W_N_signal,
grant_W_E => grant_W_E_signal,
grant_W_W => grant_W_W_signal,
grant_W_S => grant_W_S_signal,
grant_W_L => grant_W_L_signal,
grant_S_N => grant_S_N_signal,
grant_S_E => grant_S_E_signal,
grant_S_W => grant_S_W_signal,
grant_S_S => grant_S_S_signal,
grant_S_L => grant_S_L_signal,
grant_L_N => grant_L_N_signal,
grant_L_E => grant_L_E_signal,
grant_L_W => grant_L_W_signal,
grant_L_S => grant_L_S_signal,
grant_L_L => grant_L_L_signal,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
-- Checker Outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match
);
-- Allocator credit counter logic checkers module instantiation
ALLOCATOR_CREDIT_COUNTER_LOGIC_CHECKERS: allocator_credit_counter_logic_pseudo_checkers PORT MAP (
credit_in_N => credit_in_N,
credit_in_E => credit_in_E,
credit_in_W => credit_in_W,
credit_in_S => credit_in_S,
credit_in_L => credit_in_L,
credit_counter_N_out => credit_counter_N_out, credit_counter_E_out => credit_counter_E_out, credit_counter_W_out => credit_counter_W_out, credit_counter_S_out => credit_counter_S_out, credit_counter_L_out => credit_counter_L_out,
valid_N => grant_N, -- Must be connected to grant signals!
valid_E => grant_E, -- Must be connected to grant signals!
valid_W => grant_W, -- Must be connected to grant signals!
valid_S => grant_S, -- Must be connected to grant signals!
valid_L => grant_L, -- Must be connected to grant signals!
credit_counter_N_in => credit_counter_N_in,
credit_counter_E_in => credit_counter_E_in,
credit_counter_W_in => credit_counter_W_in,
credit_counter_S_in => credit_counter_S_in,
credit_counter_L_in => credit_counter_L_in,
-- Checker Outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter In
-- North Arbiter_in with checkers integrated (module instantiation)
arb_N_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N, Req_X_E=> req_N_E, Req_X_W=>req_N_W, Req_X_S=>req_N_S, Req_X_L=>req_N_L,
X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L,
-- North Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => N_err_IDLE_Req_N,
err_IDLE_grant_N => N_err_IDLE_grant_N,
err_North_Req_N => N_err_North_Req_N,
err_North_grant_N => N_err_North_grant_N,
err_East_Req_E => N_err_East_Req_E,
err_East_grant_E => N_err_East_grant_E,
err_West_Req_W => N_err_West_Req_W,
err_West_grant_W => N_err_West_grant_W,
err_South_Req_S => N_err_South_Req_S,
err_South_grant_S => N_err_South_grant_S,
err_Local_Req_L => N_err_Local_Req_L,
err_Local_grant_L => N_err_Local_grant_L,
err_IDLE_Req_E => N_err_IDLE_Req_E,
err_IDLE_grant_E => N_err_IDLE_grant_E,
err_North_Req_E => N_err_North_Req_E,
err_North_grant_E => N_err_North_grant_E,
err_East_Req_W => N_err_East_Req_W,
err_East_grant_W => N_err_East_grant_W,
err_West_Req_S => N_err_West_Req_S,
err_West_grant_S => N_err_West_grant_S,
err_South_Req_L => N_err_South_Req_L,
err_South_grant_L => N_err_South_grant_L,
err_Local_Req_N => N_err_Local_Req_N,
err_Local_grant_N => N_err_Local_grant_N,
err_IDLE_Req_W => N_err_IDLE_Req_W,
err_IDLE_grant_W => N_err_IDLE_grant_W,
err_North_Req_W => N_err_North_Req_W,
err_North_grant_W => N_err_North_grant_W,
err_East_Req_S => N_err_East_Req_S,
err_East_grant_S => N_err_East_grant_S,
err_West_Req_L => N_err_West_Req_L,
err_West_grant_L => N_err_West_grant_L,
err_South_Req_N => N_err_South_Req_N,
err_South_grant_N => N_err_South_grant_N,
err_Local_Req_E => N_err_Local_Req_E,
err_Local_grant_E => N_err_Local_grant_E,
err_IDLE_Req_S => N_err_IDLE_Req_S,
err_IDLE_grant_S => N_err_IDLE_grant_S,
err_North_Req_S => N_err_North_Req_S,
err_North_grant_S => N_err_North_grant_S,
err_East_Req_L => N_err_East_Req_L,
err_East_grant_L => N_err_East_grant_L,
err_West_Req_N => N_err_West_Req_N,
err_West_grant_N => N_err_West_grant_N,
err_South_Req_E => N_err_South_Req_E,
err_South_grant_E => N_err_South_grant_E,
err_Local_Req_W => N_err_Local_Req_W,
err_Local_grant_W => N_err_Local_grant_W,
err_IDLE_Req_L => N_err_IDLE_Req_L,
err_IDLE_grant_L => N_err_IDLE_grant_L,
err_North_Req_L => N_err_North_Req_L,
err_North_grant_L => N_err_North_grant_L,
err_East_Req_N => N_err_East_Req_N,
err_East_grant_N => N_err_East_grant_N,
err_West_Req_E => N_err_West_Req_E,
err_West_grant_E => N_err_West_grant_E,
err_South_Req_W => N_err_South_Req_W,
err_South_grant_W => N_err_South_grant_W,
err_Local_Req_S => N_err_Local_Req_S,
err_Local_grant_S => N_err_Local_grant_S,
err_state_in_onehot => N_err_state_in_onehot,
err_no_request_grants => N_err_no_request_grants,
err_request_no_grants => N_err_request_no_grants,
err_no_Req_N_grant_N => N_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => N_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => N_err_no_Req_L_grant_L
);
arb_E_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N, Req_X_E=> req_E_E, Req_X_W=>req_E_W, Req_X_S=>req_E_S, Req_X_L=>req_E_L,
X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L,
-- East Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => E_err_IDLE_Req_N,
err_IDLE_grant_N => E_err_IDLE_grant_N,
err_North_Req_N => E_err_North_Req_N,
err_North_grant_N => E_err_North_grant_N,
err_East_Req_E => E_err_East_Req_E,
err_East_grant_E => E_err_East_grant_E,
err_West_Req_W => E_err_West_Req_W,
err_West_grant_W => E_err_West_grant_W,
err_South_Req_S => E_err_South_Req_S,
err_South_grant_S => E_err_South_grant_S,
err_Local_Req_L => E_err_Local_Req_L,
err_Local_grant_L => E_err_Local_grant_L,
err_IDLE_Req_E => E_err_IDLE_Req_E,
err_IDLE_grant_E => E_err_IDLE_grant_E,
err_North_Req_E => E_err_North_Req_E,
err_North_grant_E => E_err_North_grant_E,
err_East_Req_W => E_err_East_Req_W,
err_East_grant_W => E_err_East_grant_W,
err_West_Req_S => E_err_West_Req_S,
err_West_grant_S => E_err_West_grant_S,
err_South_Req_L => E_err_South_Req_L,
err_South_grant_L => E_err_South_grant_L,
err_Local_Req_N => E_err_Local_Req_N,
err_Local_grant_N => E_err_Local_grant_N,
err_IDLE_Req_W => E_err_IDLE_Req_W,
err_IDLE_grant_W => E_err_IDLE_grant_W,
err_North_Req_W => E_err_North_Req_W,
err_North_grant_W => E_err_North_grant_W,
err_East_Req_S => E_err_East_Req_S,
err_East_grant_S => E_err_East_grant_S,
err_West_Req_L => E_err_West_Req_L,
err_West_grant_L => E_err_West_grant_L,
err_South_Req_N => E_err_South_Req_N,
err_South_grant_N => E_err_South_grant_N,
err_Local_Req_E => E_err_Local_Req_E,
err_Local_grant_E => E_err_Local_grant_E,
err_IDLE_Req_S => E_err_IDLE_Req_S,
err_IDLE_grant_S => E_err_IDLE_grant_S,
err_North_Req_S => E_err_North_Req_S,
err_North_grant_S => E_err_North_grant_S,
err_East_Req_L => E_err_East_Req_L,
err_East_grant_L => E_err_East_grant_L,
err_West_Req_N => E_err_West_Req_N,
err_West_grant_N => E_err_West_grant_N,
err_South_Req_E => E_err_South_Req_E,
err_South_grant_E => E_err_South_grant_E,
err_Local_Req_W => E_err_Local_Req_W,
err_Local_grant_W => E_err_Local_grant_W,
err_IDLE_Req_L => E_err_IDLE_Req_L,
err_IDLE_grant_L => E_err_IDLE_grant_L,
err_North_Req_L => E_err_North_Req_L,
err_North_grant_L => E_err_North_grant_L,
err_East_Req_N => E_err_East_Req_N,
err_East_grant_N => E_err_East_grant_N,
err_West_Req_E => E_err_West_Req_E,
err_West_grant_E => E_err_West_grant_E,
err_South_Req_W => E_err_South_Req_W,
err_South_grant_W => E_err_South_grant_W,
err_Local_Req_S => E_err_Local_Req_S,
err_Local_grant_S => E_err_Local_grant_S,
err_state_in_onehot => E_err_state_in_onehot,
err_no_request_grants => E_err_no_request_grants,
err_request_no_grants => E_err_request_no_grants,
err_no_Req_N_grant_N => E_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => E_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => E_err_no_Req_L_grant_L
);
arb_W_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N, Req_X_E=> req_W_E, Req_X_W=>req_W_W, Req_X_S=>req_W_S, Req_X_L=>req_W_L,
X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L,
-- West Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => W_err_IDLE_Req_N,
err_IDLE_grant_N => W_err_IDLE_grant_N,
err_North_Req_N => W_err_North_Req_N,
err_North_grant_N => W_err_North_grant_N,
err_East_Req_E => W_err_East_Req_E,
err_East_grant_E => W_err_East_grant_E,
err_West_Req_W => W_err_West_Req_W,
err_West_grant_W => W_err_West_grant_W,
err_South_Req_S => W_err_South_Req_S,
err_South_grant_S => W_err_South_grant_S,
err_Local_Req_L => W_err_Local_Req_L,
err_Local_grant_L => W_err_Local_grant_L,
err_IDLE_Req_E => W_err_IDLE_Req_E,
err_IDLE_grant_E => W_err_IDLE_grant_E,
err_North_Req_E => W_err_North_Req_E,
err_North_grant_E => W_err_North_grant_E,
err_East_Req_W => W_err_East_Req_W,
err_East_grant_W => W_err_East_grant_W,
err_West_Req_S => W_err_West_Req_S,
err_West_grant_S => W_err_West_grant_S,
err_South_Req_L => W_err_South_Req_L,
err_South_grant_L => W_err_South_grant_L,
err_Local_Req_N => W_err_Local_Req_N,
err_Local_grant_N => W_err_Local_grant_N,
err_IDLE_Req_W => W_err_IDLE_Req_W,
err_IDLE_grant_W => W_err_IDLE_grant_W,
err_North_Req_W => W_err_North_Req_W,
err_North_grant_W => W_err_North_grant_W,
err_East_Req_S => W_err_East_Req_S,
err_East_grant_S => W_err_East_grant_S,
err_West_Req_L => W_err_West_Req_L,
err_West_grant_L => W_err_West_grant_L,
err_South_Req_N => W_err_South_Req_N,
err_South_grant_N => W_err_South_grant_N,
err_Local_Req_E => W_err_Local_Req_E,
err_Local_grant_E => W_err_Local_grant_E,
err_IDLE_Req_S => W_err_IDLE_Req_S,
err_IDLE_grant_S => W_err_IDLE_grant_S,
err_North_Req_S => W_err_North_Req_S,
err_North_grant_S => W_err_North_grant_S,
err_East_Req_L => W_err_East_Req_L,
err_East_grant_L => W_err_East_grant_L,
err_West_Req_N => W_err_West_Req_N,
err_West_grant_N => W_err_West_grant_N,
err_South_Req_E => W_err_South_Req_E,
err_South_grant_E => W_err_South_grant_E,
err_Local_Req_W => W_err_Local_Req_W,
err_Local_grant_W => W_err_Local_grant_W,
err_IDLE_Req_L => W_err_IDLE_Req_L,
err_IDLE_grant_L => W_err_IDLE_grant_L,
err_North_Req_L => W_err_North_Req_L,
err_North_grant_L => W_err_North_grant_L,
err_East_Req_N => W_err_East_Req_N,
err_East_grant_N => W_err_East_grant_N,
err_West_Req_E => W_err_West_Req_E,
err_West_grant_E => W_err_West_grant_E,
err_South_Req_W => W_err_South_Req_W,
err_South_grant_W => W_err_South_grant_W,
err_Local_Req_S => W_err_Local_Req_S,
err_Local_grant_S => W_err_Local_grant_S,
err_state_in_onehot => W_err_state_in_onehot,
err_no_request_grants => W_err_no_request_grants,
err_request_no_grants => W_err_request_no_grants,
err_no_Req_N_grant_N => W_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => W_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => W_err_no_Req_L_grant_L
);
arb_S_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N, Req_X_E=> req_S_E, Req_X_W=>req_S_W, Req_X_S=>req_S_S, Req_X_L=>req_S_L,
X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L,
-- South Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => S_err_IDLE_Req_N,
err_IDLE_grant_N => S_err_IDLE_grant_N,
err_North_Req_N => S_err_North_Req_N,
err_North_grant_N => S_err_North_grant_N,
err_East_Req_E => S_err_East_Req_E,
err_East_grant_E => S_err_East_grant_E,
err_West_Req_W => S_err_West_Req_W,
err_West_grant_W => S_err_West_grant_W,
err_South_Req_S => S_err_South_Req_S,
err_South_grant_S => S_err_South_grant_S,
err_Local_Req_L => S_err_Local_Req_L,
err_Local_grant_L => S_err_Local_grant_L,
err_IDLE_Req_E => S_err_IDLE_Req_E,
err_IDLE_grant_E => S_err_IDLE_grant_E,
err_North_Req_E => S_err_North_Req_E,
err_North_grant_E => S_err_North_grant_E,
err_East_Req_W => S_err_East_Req_W,
err_East_grant_W => S_err_East_grant_W,
err_West_Req_S => S_err_West_Req_S,
err_West_grant_S => S_err_West_grant_S,
err_South_Req_L => S_err_South_Req_L,
err_South_grant_L => S_err_South_grant_L,
err_Local_Req_N => S_err_Local_Req_N,
err_Local_grant_N => S_err_Local_grant_N,
err_IDLE_Req_W => S_err_IDLE_Req_W,
err_IDLE_grant_W => S_err_IDLE_grant_W,
err_North_Req_W => S_err_North_Req_W,
err_North_grant_W => S_err_North_grant_W,
err_East_Req_S => S_err_East_Req_S,
err_East_grant_S => S_err_East_grant_S,
err_West_Req_L => S_err_West_Req_L,
err_West_grant_L => S_err_West_grant_L,
err_South_Req_N => S_err_South_Req_N,
err_South_grant_N => S_err_South_grant_N,
err_Local_Req_E => S_err_Local_Req_E,
err_Local_grant_E => S_err_Local_grant_E,
err_IDLE_Req_S => S_err_IDLE_Req_S,
err_IDLE_grant_S => S_err_IDLE_grant_S,
err_North_Req_S => S_err_North_Req_S,
err_North_grant_S => S_err_North_grant_S,
err_East_Req_L => S_err_East_Req_L,
err_East_grant_L => S_err_East_grant_L,
err_West_Req_N => S_err_West_Req_N,
err_West_grant_N => S_err_West_grant_N,
err_South_Req_E => S_err_South_Req_E,
err_South_grant_E => S_err_South_grant_E,
err_Local_Req_W => S_err_Local_Req_W,
err_Local_grant_W => S_err_Local_grant_W,
err_IDLE_Req_L => S_err_IDLE_Req_L,
err_IDLE_grant_L => S_err_IDLE_grant_L,
err_North_Req_L => S_err_North_Req_L,
err_North_grant_L => S_err_North_grant_L,
err_East_Req_N => S_err_East_Req_N,
err_East_grant_N => S_err_East_grant_N,
err_West_Req_E => S_err_West_Req_E,
err_West_grant_E => S_err_West_grant_E,
err_South_Req_W => S_err_South_Req_W,
err_South_grant_W => S_err_South_grant_W,
err_Local_Req_S => S_err_Local_Req_S,
err_Local_grant_S => S_err_Local_grant_S,
err_state_in_onehot => S_err_state_in_onehot,
err_no_request_grants => S_err_no_request_grants,
err_request_no_grants => S_err_request_no_grants,
err_no_Req_N_grant_N => S_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => S_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => S_err_no_Req_L_grant_L
);
arb_L_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N, Req_X_E=> req_L_E, Req_X_W=>req_L_W, Req_X_S=>req_L_S, Req_X_L=>req_L_L,
X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L,
-- Local Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => L_err_IDLE_Req_N,
err_IDLE_grant_N => L_err_IDLE_grant_N,
err_North_Req_N => L_err_North_Req_N,
err_North_grant_N => L_err_North_grant_N,
err_East_Req_E => L_err_East_Req_E,
err_East_grant_E => L_err_East_grant_E,
err_West_Req_W => L_err_West_Req_W,
err_West_grant_W => L_err_West_grant_W,
err_South_Req_S => L_err_South_Req_S,
err_South_grant_S => L_err_South_grant_S,
err_Local_Req_L => L_err_Local_Req_L,
err_Local_grant_L => L_err_Local_grant_L,
err_IDLE_Req_E => L_err_IDLE_Req_E,
err_IDLE_grant_E => L_err_IDLE_grant_E,
err_North_Req_E => L_err_North_Req_E,
err_North_grant_E => L_err_North_grant_E,
err_East_Req_W => L_err_East_Req_W,
err_East_grant_W => L_err_East_grant_W,
err_West_Req_S => L_err_West_Req_S,
err_West_grant_S => L_err_West_grant_S,
err_South_Req_L => L_err_South_Req_L,
err_South_grant_L => L_err_South_grant_L,
err_Local_Req_N => L_err_Local_Req_N,
err_Local_grant_N => L_err_Local_grant_N,
err_IDLE_Req_W => L_err_IDLE_Req_W,
err_IDLE_grant_W => L_err_IDLE_grant_W,
err_North_Req_W => L_err_North_Req_W,
err_North_grant_W => L_err_North_grant_W,
err_East_Req_S => L_err_East_Req_S,
err_East_grant_S => L_err_East_grant_S,
err_West_Req_L => L_err_West_Req_L,
err_West_grant_L => L_err_West_grant_L,
err_South_Req_N => L_err_South_Req_N,
err_South_grant_N => L_err_South_grant_N,
err_Local_Req_E => L_err_Local_Req_E,
err_Local_grant_E => L_err_Local_grant_E,
err_IDLE_Req_S => L_err_IDLE_Req_S,
err_IDLE_grant_S => L_err_IDLE_grant_S,
err_North_Req_S => L_err_North_Req_S,
err_North_grant_S => L_err_North_grant_S,
err_East_Req_L => L_err_East_Req_L,
err_East_grant_L => L_err_East_grant_L,
err_West_Req_N => L_err_West_Req_N,
err_West_grant_N => L_err_West_grant_N,
err_South_Req_E => L_err_South_Req_E,
err_South_grant_E => L_err_South_grant_E,
err_Local_Req_W => L_err_Local_Req_W,
err_Local_grant_W => L_err_Local_grant_W,
err_IDLE_Req_L => L_err_IDLE_Req_L,
err_IDLE_grant_L => L_err_IDLE_grant_L,
err_North_Req_L => L_err_North_Req_L,
err_North_grant_L => L_err_North_grant_L,
err_East_Req_N => L_err_East_Req_N,
err_East_grant_N => L_err_East_grant_N,
err_West_Req_E => L_err_West_Req_E,
err_West_grant_E => L_err_West_grant_E,
err_South_Req_W => L_err_South_Req_W,
err_South_grant_W => L_err_South_grant_W,
err_Local_Req_S => L_err_Local_Req_S,
err_Local_grant_S => L_err_Local_grant_S,
err_state_in_onehot => L_err_state_in_onehot,
err_no_request_grants => L_err_no_request_grants,
err_request_no_grants => L_err_request_no_grants,
err_no_Req_N_grant_N => L_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => L_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => L_err_no_Req_L_grant_L
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter Out mobuldes instantiation(s)
-- Y is N now
-- North Arbiter_out with checkers integrated
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig,
grant_Y_E => grant_N_E_sig,
grant_Y_W => grant_N_W_sig,
grant_Y_S => grant_N_S_sig,
grant_Y_L => grant_N_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => N_err_IDLE_req_X_N,
err_North_req_X_N => N_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => N_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => N_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => N_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => N_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => N_err_IDLE_req_X_E,
err_North_req_X_E => N_err_North_req_X_E,
err_East_req_X_W => N_err_East_req_X_W,
err_West_req_X_S => N_err_West_req_X_S,
err_South_req_X_L => N_err_South_req_X_L,
err_Local_req_X_N => N_err_Local_req_X_N,
err_IDLE_req_X_W => N_err_IDLE_req_X_W,
err_North_req_X_W => N_err_North_req_X_W,
err_East_req_X_S => N_err_East_req_X_S,
err_West_req_X_L => N_err_West_req_X_L,
err_South_req_X_N => N_err_South_req_X_N,
err_Local_req_X_E => N_err_Local_req_X_E,
err_IDLE_req_X_S => N_err_IDLE_req_X_S,
err_North_req_X_S => N_err_North_req_X_S,
err_East_req_X_L => N_err_East_req_X_L,
err_West_req_X_N => N_err_West_req_X_N,
err_South_req_X_E => N_err_South_req_X_E,
err_Local_req_X_W => N_err_Local_req_X_W,
err_IDLE_req_X_L => N_err_IDLE_req_X_L,
err_North_req_X_L => N_err_North_req_X_L,
err_East_req_X_N => N_err_East_req_X_N,
err_West_req_X_E => N_err_West_req_X_E,
err_South_req_X_W => N_err_South_req_X_W,
err_Local_req_X_S => N_err_Local_req_X_S,
err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
err_no_request_grants => N_arbiter_out_err_no_request_grants,
err_request_IDLE_state => N_err_request_IDLE_state,
err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero
);
-- Y is E now
-- East Arbiter_out with checkers integrated
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig,
grant_Y_E => grant_E_E_sig,
grant_Y_W => grant_E_W_sig,
grant_Y_S => grant_E_S_sig,
grant_Y_L => grant_E_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => E_err_IDLE_req_X_N,
err_North_req_X_N => E_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => E_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => E_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => E_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => E_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => E_err_IDLE_req_X_E,
err_North_req_X_E => E_err_North_req_X_E,
err_East_req_X_W => E_err_East_req_X_W,
err_West_req_X_S => E_err_West_req_X_S,
err_South_req_X_L => E_err_South_req_X_L,
err_Local_req_X_N => E_err_Local_req_X_N,
err_IDLE_req_X_W => E_err_IDLE_req_X_W,
err_North_req_X_W => E_err_North_req_X_W,
err_East_req_X_S => E_err_East_req_X_S,
err_West_req_X_L => E_err_West_req_X_L,
err_South_req_X_N => E_err_South_req_X_N,
err_Local_req_X_E => E_err_Local_req_X_E,
err_IDLE_req_X_S => E_err_IDLE_req_X_S,
err_North_req_X_S => E_err_North_req_X_S,
err_East_req_X_L => E_err_East_req_X_L,
err_West_req_X_N => E_err_West_req_X_N,
err_South_req_X_E => E_err_South_req_X_E,
err_Local_req_X_W => E_err_Local_req_X_W,
err_IDLE_req_X_L => E_err_IDLE_req_X_L,
err_North_req_X_L => E_err_North_req_X_L,
err_East_req_X_N => E_err_East_req_X_N,
err_West_req_X_E => E_err_West_req_X_E,
err_South_req_X_W => E_err_South_req_X_W,
err_Local_req_X_S => E_err_Local_req_X_S,
err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
err_no_request_grants => E_arbiter_out_err_no_request_grants,
err_request_IDLE_state => E_err_request_IDLE_state,
err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero
);
-- Y is W now
-- West Arbiter_out with checkers integrated
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig,
grant_Y_E => grant_W_E_sig,
grant_Y_W => grant_W_W_sig,
grant_Y_S => grant_W_S_sig,
grant_Y_L => grant_W_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => W_err_IDLE_req_X_N,
err_North_req_X_N => W_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => W_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => W_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => W_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => W_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => W_err_IDLE_req_X_E,
err_North_req_X_E => W_err_North_req_X_E,
err_East_req_X_W => W_err_East_req_X_W,
err_West_req_X_S => W_err_West_req_X_S,
err_South_req_X_L => W_err_South_req_X_L,
err_Local_req_X_N => W_err_Local_req_X_N,
err_IDLE_req_X_W => W_err_IDLE_req_X_W,
err_North_req_X_W => W_err_North_req_X_W,
err_East_req_X_S => W_err_East_req_X_S,
err_West_req_X_L => W_err_West_req_X_L,
err_South_req_X_N => W_err_South_req_X_N,
err_Local_req_X_E => W_err_Local_req_X_E,
err_IDLE_req_X_S => W_err_IDLE_req_X_S,
err_North_req_X_S => W_err_North_req_X_S,
err_East_req_X_L => W_err_East_req_X_L,
err_West_req_X_N => W_err_West_req_X_N,
err_South_req_X_E => W_err_South_req_X_E,
err_Local_req_X_W => W_err_Local_req_X_W,
err_IDLE_req_X_L => W_err_IDLE_req_X_L,
err_North_req_X_L => W_err_North_req_X_L,
err_East_req_X_N => W_err_East_req_X_N,
err_West_req_X_E => W_err_West_req_X_E,
err_South_req_X_W => W_err_South_req_X_W,
err_Local_req_X_S => W_err_Local_req_X_S,
err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
err_no_request_grants => W_arbiter_out_err_no_request_grants,
err_request_IDLE_state => W_err_request_IDLE_state,
err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero
);
-- Y is S now
-- South Arbiter_out with checkers integrated
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig,
grant_Y_E => grant_S_E_sig,
grant_Y_W => grant_S_W_sig,
grant_Y_S => grant_S_S_sig,
grant_Y_L => grant_S_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => S_err_IDLE_req_X_N,
err_North_req_X_N => S_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => S_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => S_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => S_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => S_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => S_err_IDLE_req_X_E,
err_North_req_X_E => S_err_North_req_X_E,
err_East_req_X_W => S_err_East_req_X_W,
err_West_req_X_S => S_err_West_req_X_S,
err_South_req_X_L => S_err_South_req_X_L,
err_Local_req_X_N => S_err_Local_req_X_N,
err_IDLE_req_X_W => S_err_IDLE_req_X_W,
err_North_req_X_W => S_err_North_req_X_W,
err_East_req_X_S => S_err_East_req_X_S,
err_West_req_X_L => S_err_West_req_X_L,
err_South_req_X_N => S_err_South_req_X_N,
err_Local_req_X_E => S_err_Local_req_X_E,
err_IDLE_req_X_S => S_err_IDLE_req_X_S,
err_North_req_X_S => S_err_North_req_X_S,
err_East_req_X_L => S_err_East_req_X_L,
err_West_req_X_N => S_err_West_req_X_N,
err_South_req_X_E => S_err_South_req_X_E,
err_Local_req_X_W => S_err_Local_req_X_W,
err_IDLE_req_X_L => S_err_IDLE_req_X_L,
err_North_req_X_L => S_err_North_req_X_L,
err_East_req_X_N => S_err_East_req_X_N,
err_West_req_X_E => S_err_West_req_X_E,
err_South_req_X_W => S_err_South_req_X_W,
err_Local_req_X_S => S_err_Local_req_X_S,
err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
err_no_request_grants => S_arbiter_out_err_no_request_grants,
err_request_IDLE_state => S_err_request_IDLE_state,
err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero
);
-- Y is L now
-- Local Arbiter_out with checkers integrated
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig,
grant_Y_E => grant_L_E_sig,
grant_Y_W => grant_L_W_sig,
grant_Y_S => grant_L_S_sig,
grant_Y_L => grant_L_L_sig,
err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => L_err_IDLE_req_X_N,
err_North_req_X_N => L_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => L_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => L_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => L_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => L_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => L_err_IDLE_req_X_E,
err_North_req_X_E => L_err_North_req_X_E,
err_East_req_X_W => L_err_East_req_X_W,
err_West_req_X_S => L_err_West_req_X_S,
err_South_req_X_L => L_err_South_req_X_L,
err_Local_req_X_N => L_err_Local_req_X_N,
err_IDLE_req_X_W => L_err_IDLE_req_X_W,
err_North_req_X_W => L_err_North_req_X_W,
err_East_req_X_S => L_err_East_req_X_S,
err_West_req_X_L => L_err_West_req_X_L,
err_South_req_X_N => L_err_South_req_X_N,
err_Local_req_X_E => L_err_Local_req_X_E,
err_IDLE_req_X_S => L_err_IDLE_req_X_S,
err_North_req_X_S => L_err_North_req_X_S,
err_East_req_X_L => L_err_East_req_X_L,
err_West_req_X_N => L_err_West_req_X_N,
err_South_req_X_E => L_err_South_req_X_E,
err_Local_req_X_W => L_err_Local_req_X_W,
err_IDLE_req_X_L => L_err_IDLE_req_X_L,
err_North_req_X_L => L_err_North_req_X_L,
err_East_req_X_N => L_err_East_req_X_N,
err_West_req_X_E => L_err_West_req_X_E,
err_South_req_X_W => L_err_South_req_X_W,
err_Local_req_X_S => L_err_Local_req_X_S,
err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
err_no_request_grants => L_arbiter_out_err_no_request_grants,
err_request_IDLE_state => L_err_request_IDLE_state,
err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
valid_N_sig <= grant_N;
valid_E_sig <= grant_E;
valid_W_sig <= grant_W;
valid_S_sig <= grant_S;
valid_L_sig <= grant_L;
END;
| gpl-3.0 |
Project-Bonfire/KOIT | RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Cx_Reconf/RTL/Cx_Reconf_pseudo_with_checkers_top.vhd | 3 | 7867 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_with_checkers_top is
port ( reconfig_cx: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Temp_Cx: in std_logic_vector(3 downto 0);
Faulty_C_N: in std_logic;
Faulty_C_E: in std_logic;
Faulty_C_W: in std_logic;
Faulty_C_S: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Cx_in_out: out std_logic_vector(3 downto 0);
reconfig_cx_in_out: out std_logic;
Temp_Cx_in_out: out std_logic_vector(3 downto 0);
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_with_checkers_top;
architecture behavior of Cx_Reconf_pseudo_with_checkers_top is
component Cx_Reconf_pseudo is
port ( reconfig_cx: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Temp_Cx: in std_logic_vector(3 downto 0);
Faulty_C_N: in std_logic;
Faulty_C_E: in std_logic;
Faulty_C_W: in std_logic;
Faulty_C_S: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Cx_in: out std_logic_vector(3 downto 0);
reconfig_cx_in: out std_logic;
Temp_Cx_in: out std_logic_vector(3 downto 0)
);
end component;
component Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: out std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end component;
signal Cx_in_sig: std_logic_vector (3 downto 0);
signal reconfig_cx_in_sig: std_logic;
signal Temp_Cx_in_sig: std_logic_vector(3 downto 0);
begin
Cx_in_out <= Cx_in_sig;
reconfig_cx_in_out <= reconfig_cx_in_sig;
Temp_Cx_in_out <= Temp_Cx_in_sig;
-- Cx Reconfiguration module instantiation
Cx_Reconf: Cx_Reconf_pseudo port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Temp_Cx => Temp_Cx,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Cx => Cx,
Cx_in => Cx_in_sig,
reconfig_cx_in => reconfig_cx_in_sig,
Temp_Cx_in => Temp_Cx_in_sig
);
-- Cx Reconfiguration module checkers instantiation
CHECKERS: Cx_Reconf_pseudo_checkers port map (
reconfig_cx => reconfig_cx,
flit_type => flit_type,
empty => empty,
grants => grants,
Cx_in => Cx_in_sig,
Temp_Cx => Temp_Cx,
reconfig_cx_in => reconfig_cx_in_sig,
Cx => Cx,
Faulty_C_N => Faulty_C_N,
Faulty_C_E => Faulty_C_E,
Faulty_C_W => Faulty_C_W,
Faulty_C_S => Faulty_C_S,
Temp_Cx_in => Temp_Cx_in_sig,
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal
);
end behavior; | gpl-3.0 |
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