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stringlengths 1
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stringlengths 0
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lepton-eda/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/bjt_transistor_simple_arc.vhdl | 15 | 1525 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE simple_arc OF BJT_transistor_simple IS
terminal unnamed_net8 : electrical;
terminal unnamed_net7 : electrical;
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
SP1 : ENTITY SP_DIODE(SPICE_Diode_Model)
GENERIC MAP (
VT => VT,
AF => AF,
KF => KF,
PT => PT,
EG => EG,
M => ME,
PB => PE,
TT => TF,
CJ0 => CJE,
ISS => ISS)
PORT MAP ( ANODE => unnamed_net8,
KATHODE => unnamed_net5);
CS2 : ENTITY SPICE_cs(current_controlled)
GENERIC MAP (
N => BF,
VT => VT,
ISS => ISS)
PORT MAP ( urt => unnamed_net4,
lrt => unnamed_net5,
ult => unnamed_net1,
llt => unnamed_net8);
CAP2 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net5,
RT => unnamed_net1);
CAP1 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net1,
RT => unnamed_net4);
GND1 : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net7);
CAP3 : ENTITY CAPACITOR
GENERIC MAP (
c => CCS)
PORT MAP ( LT => unnamed_net7,
RT => unnamed_net4);
RES_emitter : ENTITY RESISTOR
GENERIC MAP (
r => RE)
PORT MAP ( RT => unnamed_net5,
LT => emitter);
RES_collector : ENTITY RESISTOR
GENERIC MAP (
r => RC)
PORT MAP ( RT => collector,
LT => unnamed_net4);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => RB)
PORT MAP ( RT => unnamed_net1,
LT => base);
END ARCHITECTURE simple_arc;
| gpl-2.0 |
Diego-HR/HL-Object-Oriented | QAMDemodulator/src/solution1/impl/sysgen/vhdl_sim/qam_dem_top_mounstrito.vhd | 4 | 63258 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity qam_dem_top_mounstrito is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
din_i_V : IN STD_LOGIC_VECTOR (15 downto 0);
din_q_V : IN STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V_ap_vld : OUT STD_LOGIC;
dout_mix_q_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_q_V_ap_vld : OUT STD_LOGIC;
ph_in_i_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_in_q_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V_ap_vld : OUT STD_LOGIC;
ph_out_q_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_q_V_ap_vld : OUT STD_LOGIC;
loop_integ_V : OUT STD_LOGIC_VECTOR (27 downto 0);
loop_integ_V_ap_vld : OUT STD_LOGIC;
control_lf_p : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_i : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_out_gain : IN STD_LOGIC_VECTOR (7 downto 0);
control_reg_clr : IN STD_LOGIC_VECTOR (0 downto 0);
control_reg_init_V : IN STD_LOGIC_VECTOR (27 downto 0) );
end;
architecture behav of qam_dem_top_mounstrito is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv28_0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv14_1FFF : STD_LOGIC_VECTOR (13 downto 0) := "01111111111111";
constant ap_const_lv14_2000 : STD_LOGIC_VECTOR (13 downto 0) := "10000000000000";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv9_9 : STD_LOGIC_VECTOR (8 downto 0) := "000001001";
constant ap_const_lv9_1F7 : STD_LOGIC_VECTOR (8 downto 0) := "111110111";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv28_7FFFFFF : STD_LOGIC_VECTOR (27 downto 0) := "0111111111111111111111111111";
constant ap_const_lv28_8000000 : STD_LOGIC_VECTOR (27 downto 0) := "1000000000000000000000000000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv10_3FF : STD_LOGIC_VECTOR (9 downto 0) := "1111111111";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_34 : BOOLEAN;
signal i_reg_V : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
signal phase_angle_V : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal cos_lut_address0 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_lut_ce0 : STD_LOGIC;
signal cos_lut_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal cos_lut_address1 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_lut_ce1 : STD_LOGIC;
signal cos_lut_q1 : STD_LOGIC_VECTOR (14 downto 0);
signal reg_312 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_82 : BOOLEAN;
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_89 : BOOLEAN;
signal grp_fu_276_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal reg_316 : STD_LOGIC_VECTOR (26 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_99 : BOOLEAN;
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_106 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal OP1_V_i_cast_fu_320_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP1_V_i_cast_reg_1471 : STD_LOGIC_VECTOR (26 downto 0);
signal ap_sig_bdd_122 : BOOLEAN;
signal OP2_V_i_cast_fu_325_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_i_cast_reg_1476 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_1_i_cast_fu_330_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_1_i_cast_reg_1481 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_1_fu_335_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_1_reg_1486 : STD_LOGIC_VECTOR (26 downto 0);
signal sd_out_i_V_reg_1491 : STD_LOGIC_VECTOR (15 downto 0);
signal newsignbit_fu_372_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_reg_1497 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_fu_408_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_reg_1503 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_fu_432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_reg_1509 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_467_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_1516 : STD_LOGIC_VECTOR (0 downto 0);
signal sd_out_q_V_reg_1521 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_148 : BOOLEAN;
signal isneg_1_reg_1527 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_1_reg_1533 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_1_i_reg_1541 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_6_fu_620_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1547 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_163 : BOOLEAN;
signal OP1_V_fu_628_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal OP2_V_fu_633_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal isneg_2_reg_1562 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_176 : BOOLEAN;
signal p_Val2_9_reg_1568 : STD_LOGIC_VECTOR (13 downto 0);
signal newsignbit_2_reg_1574 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_i8_reg_1580 : STD_LOGIC_VECTOR (1 downto 0);
signal OP1_V_1_fu_692_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal OP2_V_1_fu_697_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal tmp_9_fu_775_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_9_reg_1596 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_24_reg_1601 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_197 : BOOLEAN;
signal overflow_3_fu_854_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_3_reg_1607 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_3_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_3_reg_1613 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_26_fu_977_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_26_reg_1620 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_210 : BOOLEAN;
signal p_Val2_4_fu_1041_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_4_reg_1625 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_16_i_fu_1137_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_16_i_reg_1630 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_221 : BOOLEAN;
signal isNeg_2_fu_1160_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal isNeg_2_reg_1636 : STD_LOGIC_VECTOR (0 downto 0);
signal sh_assign_3_fu_1174_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sh_assign_3_reg_1641 : STD_LOGIC_VECTOR (7 downto 0);
signal msb_V_reg_1647 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_234 : BOOLEAN;
signal tmp_26_reg_1654 : STD_LOGIC_VECTOR (0 downto 0);
signal sin_adr_V_reg_1660 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_247 : BOOLEAN;
signal tmp_23_i_fu_1300_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_i_fu_1305_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Val2_41_fu_1145_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal loop_integ_V_preg : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_275 : BOOLEAN;
signal grp_fu_276_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_276_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_6_i_fu_340_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_1_fu_348_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Result_i_fu_380_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal p_not_i1_i_fu_390_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_fu_364_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i1_i_fu_396_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_i_fu_402_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i1_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i1_i_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_not_i_fu_442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_i_fu_438_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_brmerge_i_i1_i_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge8_i_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_458_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_463_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_i_fu_475_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_3_fu_483_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_not_i_i_fu_525_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_fu_530_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_i_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i_fu_546_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_1_fu_540_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_1_not_i_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i2_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal brmerge_i_i_i_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_brmerge_i_i_i_fu_604_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge9_i_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_615_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_s_fu_592_p5 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_i3_fu_637_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal isneg_2_fu_656_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_9_fu_664_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal newsignbit_2_fu_674_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Result_i8_fu_682_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Result_2_fu_644_p5 : STD_LOGIC_VECTOR (4 downto 0);
signal p_not_i_i9_fu_701_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_fu_706_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i_fu_711_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i1_fu_727_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i1_fu_722_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i1_fu_732_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_2_fu_738_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_2_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_not_i1_fu_749_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i1_fu_743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_fu_755_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_21_mux_i_fu_761_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_i1_fu_768_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_1_i1_fu_783_p3 : STD_LOGIC_VECTOR (18 downto 0);
signal tmp_10_cast_i_fu_790_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_23_fu_794_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_23_fu_794_p2 : STD_LOGIC_VECTOR (20 downto 0);
signal tmp_7_fu_826_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal newsignbit_3_fu_818_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not_i_i_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_3_fu_800_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i4_i_fu_842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_i1_fu_848_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i_i_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i_i_fu_860_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_4_not_i_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i_i_fu_884_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge1_i_fu_893_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ssdm_int_V_write_assign_fu_898_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_1_i_fu_905_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_10_fu_911_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal isNeg_fu_927_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_fu_935_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal sh_assign_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_i1_fu_919_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_5_i1_fu_957_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast_i_fu_953_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast6_i_fu_949_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_6_i2_fu_961_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_973_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_7_i1_fu_967_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_cast_i_fu_985_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_1_fu_989_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal isNeg_1_fu_995_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i1_fu_1003_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_2_fu_1009_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_3_cast_i_fu_1021_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_3_cast5_i_fu_1017_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_10_i_fu_1025_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_1037_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_11_i_fu_1031_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_5_fu_1053_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_12_i_fu_1058_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_13_i_fu_1062_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_27_fu_1065_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal newsignbit_4_fu_1083_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_4_fu_1071_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_i_fu_1091_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_not_i_fu_1109_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i2_fu_1103_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_29_fu_1079_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal underflow_4_fu_1097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i1_fu_1115_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_28_mux_i_fu_1121_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_i2_fu_1129_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_17_i_fu_1168_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_i_fu_1188_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_5_cast_i_fu_1185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_5_cast3_i_fu_1182_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_i_fu_1191_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_1202_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_20_i_fu_1197_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_i2_15_fu_1217_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_33_fu_1206_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_35_cast_i_fu_1225_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_21_i_fu_1229_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_34_fu_1233_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal cos_adr_V_3_fu_1283_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_adr_V_fu_1288_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal sin_adr_V_1_fu_1294_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal p_Val2_31_cast_i_fu_1314_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal p_Val2_32_cast_i_fu_1310_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_25_i_fu_1318_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_i_fu_1323_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_demorgan_i_fu_1345_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_i_fu_1328_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_i_fu_1351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_i_fu_1363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_i_fu_1369_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_i_fu_1357_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_1381_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal sel_tmp_i_fu_1339_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_12_fu_1391_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_27_fu_1395_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_28_fu_1405_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_29_fu_1422_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal sin_out_V_fu_1333_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_30_fu_1432_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_31_fu_1436_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal or_cond_fu_1375_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_1446_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_33_fu_1454_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_276_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component qam_dem_top_mul_16s_12s_27_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (11 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (26 downto 0) );
end component;
component qam_dem_top_mounstrito_cos_lut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (9 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0);
address1 : IN STD_LOGIC_VECTOR (9 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
begin
cos_lut_U : component qam_dem_top_mounstrito_cos_lut
generic map (
DataWidth => 15,
AddressRange => 1024,
AddressWidth => 10)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => cos_lut_address0,
ce0 => cos_lut_ce0,
q0 => cos_lut_q0,
address1 => cos_lut_address1,
ce1 => cos_lut_ce1,
q1 => cos_lut_q1);
qam_dem_top_mul_16s_12s_27_2_U1 : component qam_dem_top_mul_16s_12s_27_2
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 16,
din1_WIDTH => 12,
dout_WIDTH => 27)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_276_p0,
din1 => grp_fu_276_p1,
ce => grp_fu_276_ce,
dout => grp_fu_276_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- loop_integ_V_preg assign process. --
loop_integ_V_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
loop_integ_V_preg <= ap_const_lv28_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V_preg <= p_Val2_41_fu_1145_p3;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_122))) then
OP1_V_i_cast_reg_1471 <= OP1_V_i_cast_fu_320_p1;
OP2_V_i_cast_reg_1476 <= OP2_V_i_cast_fu_325_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
OP2_V_1_i_cast_reg_1481 <= OP2_V_1_i_cast_fu_330_p1;
tmp_1_reg_1486 <= tmp_1_fu_335_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
i_reg_V <= p_Val2_41_fu_1145_p3;
isNeg_2_reg_1636 <= control_lf_out_gain(7 downto 7);
sh_assign_3_reg_1641 <= sh_assign_3_fu_1174_p3;
tmp_16_i_reg_1630 <= tmp_16_i_fu_1137_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
isneg_1_reg_1527 <= p_Val2_3_fu_483_p2(26 downto 26);
newsignbit_1_reg_1533 <= p_Val2_3_fu_483_p2(24 downto 24);
p_Result_1_i_reg_1541 <= p_Val2_3_fu_483_p2(26 downto 25);
sd_out_q_V_reg_1521 <= p_Val2_3_fu_483_p2(26 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
isneg_2_reg_1562 <= isneg_2_fu_656_p1(20 downto 20);
newsignbit_2_reg_1574 <= newsignbit_2_fu_674_p1(18 downto 18);
p_Result_i8_reg_1580 <= p_Result_i8_fu_682_p1(20 downto 19);
p_Val2_9_reg_1568 <= p_Val2_9_fu_664_p1(18 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
msb_V_reg_1647 <= p_Val2_34_fu_1233_p2(26 downto 25);
phase_angle_V <= p_Val2_34_fu_1233_p2(26 downto 11);
sin_adr_V_reg_1660 <= p_Val2_34_fu_1233_p2(24 downto 15);
tmp_26_reg_1654 <= p_Val2_34_fu_1233_p2(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
newsignbit_reg_1497 <= p_Val2_1_fu_348_p2(24 downto 24);
overflow_reg_1503 <= overflow_fu_408_p2;
sd_out_i_V_reg_1491 <= p_Val2_1_fu_348_p2(26 downto 11);
underflow_reg_1509 <= underflow_fu_432_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
overflow_3_reg_1607 <= overflow_3_fu_854_p2;
p_Val2_24_reg_1601 <= p_Val2_23_fu_794_p2(18 downto 5);
underflow_3_reg_1613 <= underflow_3_fu_878_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
p_Val2_26_reg_1620 <= p_Val2_26_fu_977_p3;
p_Val2_4_reg_1625 <= p_Val2_4_fu_1041_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
reg_312 <= grp_fu_276_p2(26 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8))) then
reg_316 <= grp_fu_276_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_3_reg_1516 <= tmp_3_fu_467_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
tmp_6_reg_1547 <= tmp_6_fu_620_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_9_reg_1596 <= tmp_9_fu_775_p3;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_122)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_122)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
OP1_V_1_fu_692_p1 <= std_logic_vector(resize(signed(p_Result_2_fu_644_p5),21));
OP1_V_fu_628_p1 <= std_logic_vector(resize(signed(p_Result_s_fu_592_p5),21));
OP1_V_i_cast_fu_320_p1 <= std_logic_vector(resize(signed(din_i_V),27));
OP2_V_1_fu_697_p1 <= std_logic_vector(resize(signed(sd_out_i_V_reg_1491),21));
OP2_V_1_i_cast_fu_330_p1 <= std_logic_vector(resize(signed(ph_in_q_V),27));
OP2_V_fu_633_p1 <= std_logic_vector(resize(signed(sd_out_q_V_reg_1521),21));
OP2_V_i_cast_fu_325_p1 <= std_logic_vector(resize(signed(ph_in_i_V),27));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st15_fsm_14)
begin
if (((ap_const_logic_1 = ap_done_reg) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_106 assign process. --
ap_sig_bdd_106_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_106 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_122 assign process. --
ap_sig_bdd_122_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_122 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_148 assign process. --
ap_sig_bdd_148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_148 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_163 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_176 assign process. --
ap_sig_bdd_176_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_176 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_197 assign process. --
ap_sig_bdd_197_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_197 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_210 assign process. --
ap_sig_bdd_210_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_210 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_221 assign process. --
ap_sig_bdd_221_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_221 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_234 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_247 assign process. --
ap_sig_bdd_247_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_247 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_275 assign process. --
ap_sig_bdd_275_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_275 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_34 assign process. --
ap_sig_bdd_34_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_34 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_82 assign process. --
ap_sig_bdd_82_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_82 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_89 assign process. --
ap_sig_bdd_89_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_99 assign process. --
ap_sig_bdd_99_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_99 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_197)
begin
if (ap_sig_bdd_197) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_210)
begin
if (ap_sig_bdd_210) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_221)
begin
if (ap_sig_bdd_221) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_234)
begin
if (ap_sig_bdd_234) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_247)
begin
if (ap_sig_bdd_247) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_34)
begin
if (ap_sig_bdd_34) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_82)
begin
if (ap_sig_bdd_82) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_99)
begin
if (ap_sig_bdd_99) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_89)
begin
if (ap_sig_bdd_89) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_106)
begin
if (ap_sig_bdd_106) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_148)
begin
if (ap_sig_bdd_148) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_163)
begin
if (ap_sig_bdd_163) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_176)
begin
if (ap_sig_bdd_176) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
brmerge1_i_fu_893_p2 <= (overflow_3_reg_1607 or underflow_4_not_i_fu_888_p2);
brmerge39_i1_i_fu_426_p2 <= (p_not38_i1_i_fu_420_p2 or newsignbit_0_not_i1_i_fu_414_p2);
brmerge39_i_i1_fu_732_p2 <= (p_not38_i_i1_fu_727_p2 or newsignbit_0_not_i_i1_fu_722_p2);
brmerge39_i_i_fu_556_p2 <= (p_not38_i_i_fu_551_p2 or newsignbit_0_not_i_i_fu_546_p2);
brmerge39_i_i_i_fu_872_p2 <= (p_not38_i_i_i_fu_866_p2 or newsignbit_0_not_i_i_i_fu_860_p2);
brmerge8_i_fu_447_p2 <= (overflow_reg_1503 or underflow_not_i_fu_442_p2);
brmerge9_i_fu_579_p2 <= (overflow_1_fu_540_p2 or underflow_1_not_i_fu_573_p2);
brmerge_i1_fu_1115_p2 <= (newsignbit_4_fu_1083_p3 or isneg_not_i_fu_1109_p2);
brmerge_i1_i_fu_396_p2 <= (newsignbit_fu_372_p3 or p_not_i1_i_fu_390_p2);
brmerge_i_fu_755_p2 <= (overflow_2_fu_716_p2 or underflow_not_i1_fu_749_p2);
brmerge_i_i1_fu_706_p2 <= (newsignbit_2_reg_1574 or p_not_i_i9_fu_701_p2);
brmerge_i_i1_i_fu_438_p2 <= (underflow_reg_1509 or overflow_reg_1503);
brmerge_i_i4_i_fu_842_p2 <= (newsignbit_3_fu_818_p3 or p_not_i_i_i_fu_836_p2);
brmerge_i_i_fu_530_p2 <= (newsignbit_1_reg_1533 or p_not_i_i_fu_525_p2);
brmerge_i_i_i1_fu_743_p2 <= (underflow_2_fu_738_p2 or overflow_2_fu_716_p2);
brmerge_i_i_i2_fu_1103_p2 <= (isneg_4_fu_1071_p3 xor newsignbit_4_fu_1083_p3);
brmerge_i_i_i_fu_567_p2 <= (underflow_1_fu_562_p2 or overflow_1_fu_540_p2);
brmerge_i_i_i_i_fu_884_p2 <= (underflow_3_reg_1613 or overflow_3_reg_1607);
cos_adr_V_3_fu_1283_p2 <= (sin_adr_V_reg_1660 xor ap_const_lv10_3FF);
cos_adr_V_fu_1288_p3 <=
cos_adr_V_3_fu_1283_p2 when (tmp_26_reg_1654(0) = '1') else
sin_adr_V_reg_1660;
cos_lut_address0 <= tmp_23_i_fu_1300_p1(10 - 1 downto 0);
cos_lut_address1 <= tmp_24_i_fu_1305_p1(10 - 1 downto 0);
-- cos_lut_ce0 assign process. --
cos_lut_ce0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
cos_lut_ce0 <= ap_const_logic_1;
else
cos_lut_ce0 <= ap_const_logic_0;
end if;
end process;
-- cos_lut_ce1 assign process. --
cos_lut_ce1_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
cos_lut_ce1 <= ap_const_logic_1;
else
cos_lut_ce1 <= ap_const_logic_0;
end if;
end process;
dout_mix_i_V <= sd_out_i_V_reg_1491;
-- dout_mix_i_V_ap_vld assign process. --
dout_mix_i_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
dout_mix_i_V_ap_vld <= ap_const_logic_1;
else
dout_mix_i_V_ap_vld <= ap_const_logic_0;
end if;
end process;
dout_mix_q_V <= sd_out_q_V_reg_1521;
-- dout_mix_q_V_ap_vld assign process. --
dout_mix_q_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
dout_mix_q_V_ap_vld <= ap_const_logic_1;
else
dout_mix_q_V_ap_vld <= ap_const_logic_0;
end if;
end process;
-- grp_fu_276_ce assign process. --
grp_fu_276_ce_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st9_fsm_8, ap_sig_bdd_122, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_122)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then
grp_fu_276_ce <= ap_const_logic_1;
else
grp_fu_276_ce <= ap_const_logic_0;
end if;
end process;
-- grp_fu_276_p0 assign process. --
grp_fu_276_p0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, OP1_V_i_cast_fu_320_p1, OP1_V_i_cast_reg_1471, tmp_1_fu_335_p1, tmp_1_reg_1486, ap_sig_cseq_ST_st7_fsm_6, OP2_V_fu_633_p1, ap_sig_cseq_ST_st8_fsm_7, OP2_V_1_fu_697_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
grp_fu_276_p0 <= OP2_V_1_fu_697_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
grp_fu_276_p0 <= OP2_V_fu_633_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
grp_fu_276_p0 <= tmp_1_reg_1486(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
grp_fu_276_p0 <= OP1_V_i_cast_reg_1471(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_276_p0 <= tmp_1_fu_335_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_276_p0 <= OP1_V_i_cast_fu_320_p1(16 - 1 downto 0);
else
grp_fu_276_p0 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_276_p1 assign process. --
grp_fu_276_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, OP2_V_i_cast_fu_325_p1, OP2_V_i_cast_reg_1476, OP2_V_1_i_cast_fu_330_p1, OP2_V_1_i_cast_reg_1481, ap_sig_cseq_ST_st7_fsm_6, OP1_V_fu_628_p1, ap_sig_cseq_ST_st8_fsm_7, OP1_V_1_fu_692_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
grp_fu_276_p1 <= OP1_V_1_fu_692_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
grp_fu_276_p1 <= OP1_V_fu_628_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
grp_fu_276_p1 <= OP2_V_i_cast_reg_1476(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
grp_fu_276_p1 <= OP2_V_1_i_cast_reg_1481(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_276_p1 <= OP2_V_1_i_cast_fu_330_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_276_p1 <= OP2_V_i_cast_fu_325_p1(12 - 1 downto 0);
else
grp_fu_276_p1 <= "XXXXXXXXXXXX";
end if;
end process;
isNeg_1_fu_995_p3 <= sh_assign_1_fu_989_p2(8 downto 8);
isNeg_2_fu_1160_p3 <= control_lf_out_gain(7 downto 7);
isNeg_fu_927_p3 <= control_lf_p(7 downto 7);
isneg_2_fu_656_p1 <= grp_fu_276_p2(21 - 1 downto 0);
isneg_3_fu_800_p3 <= p_Val2_23_fu_794_p2(20 downto 20);
isneg_4_fu_1071_p3 <= p_Val2_27_fu_1065_p2(28 downto 28);
isneg_fu_364_p3 <= p_Val2_1_fu_348_p2(26 downto 26);
isneg_not_i_fu_1109_p2 <= (isneg_4_fu_1071_p3 xor ap_const_lv1_1);
-- loop_integ_V assign process. --
loop_integ_V_assign_proc : process(ap_sig_cseq_ST_st12_fsm_11, p_Val2_41_fu_1145_p3, loop_integ_V_preg)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V <= p_Val2_41_fu_1145_p3;
else
loop_integ_V <= loop_integ_V_preg;
end if;
end process;
-- loop_integ_V_ap_vld assign process. --
loop_integ_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st12_fsm_11)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V_ap_vld <= ap_const_logic_1;
else
loop_integ_V_ap_vld <= ap_const_logic_0;
end if;
end process;
newsignbit_0_not_i1_i_fu_414_p2 <= (newsignbit_fu_372_p3 xor ap_const_lv1_1);
newsignbit_0_not_i_i1_fu_722_p2 <= (newsignbit_2_reg_1574 xor ap_const_lv1_1);
newsignbit_0_not_i_i_fu_546_p2 <= (newsignbit_1_reg_1533 xor ap_const_lv1_1);
newsignbit_0_not_i_i_i_fu_860_p2 <= (newsignbit_3_fu_818_p3 xor ap_const_lv1_1);
newsignbit_2_fu_674_p1 <= grp_fu_276_p2(21 - 1 downto 0);
newsignbit_3_fu_818_p3 <= p_Val2_23_fu_794_p2(18 downto 18);
newsignbit_4_fu_1083_p3 <= p_Val2_27_fu_1065_p2(27 downto 27);
newsignbit_fu_372_p3 <= p_Val2_1_fu_348_p2(24 downto 24);
not_brmerge_i_i1_i_fu_452_p2 <= (brmerge_i_i1_i_fu_438_p2 xor ap_const_lv1_1);
not_brmerge_i_i_i_fu_604_p2 <= (brmerge_i_i_i_fu_567_p2 xor ap_const_lv1_1);
or_cond_fu_1375_p2 <= (sel_tmp7_i_fu_1369_p2 or sel_tmp4_i_fu_1357_p2);
overflow_1_fu_540_p2 <= (brmerge_i_i_fu_530_p2 and tmp_7_i_fu_535_p2);
overflow_2_fu_716_p2 <= (brmerge_i_i1_fu_706_p2 and tmp_8_i_fu_711_p2);
overflow_3_fu_854_p2 <= (brmerge_i_i4_i_fu_842_p2 and tmp_3_i1_fu_848_p2);
overflow_fu_408_p2 <= (brmerge_i1_i_fu_396_p2 and tmp_5_i_fu_402_p2);
p_Result_2_fu_644_p5 <= (tmp_1_i3_fu_637_p3 & ap_const_lv5_0(2 downto 0));
p_Result_i8_fu_682_p1 <= grp_fu_276_p2(21 - 1 downto 0);
p_Result_i_fu_380_p4 <= p_Val2_1_fu_348_p2(26 downto 25);
p_Result_s_fu_592_p5 <= (tmp_i2_fu_585_p3 & ap_const_lv5_0(2 downto 0));
p_Val2_1_fu_348_p2 <= std_logic_vector(unsigned(tmp_6_i_fu_340_p3) - unsigned(reg_316));
p_Val2_1_i_fu_905_p3 <=
ap_const_lv14_2000 when (underflow_3_reg_1613(0) = '1') else
p_Val2_24_reg_1601;
p_Val2_21_mux_i_fu_761_p3 <=
ap_const_lv14_1FFF when (brmerge_i_i_i1_fu_743_p2(0) = '1') else
p_Val2_9_reg_1568;
p_Val2_23_fu_794_p1 <= reg_316(21 - 1 downto 0);
p_Val2_23_fu_794_p2 <= std_logic_vector(signed(tmp_10_cast_i_fu_790_p1) - signed(p_Val2_23_fu_794_p1));
p_Val2_26_fu_977_p3 <=
tmp_16_fu_973_p1 when (isNeg_fu_927_p3(0) = '1') else
tmp_7_i1_fu_967_p2;
p_Val2_27_fu_1065_p2 <= std_logic_vector(signed(tmp_12_i_fu_1058_p1) + signed(tmp_13_i_fu_1062_p1));
p_Val2_28_mux_i_fu_1121_p3 <=
ap_const_lv28_7FFFFFF when (brmerge_i_i_i2_fu_1103_p2(0) = '1') else
p_Val2_29_fu_1079_p1;
p_Val2_29_fu_1079_p1 <= p_Val2_27_fu_1065_p2(28 - 1 downto 0);
p_Val2_31_cast_i_fu_1314_p1 <= std_logic_vector(resize(unsigned(cos_lut_q1),16));
p_Val2_32_cast_i_fu_1310_p1 <= std_logic_vector(resize(unsigned(cos_lut_q0),16));
p_Val2_33_fu_1206_p3 <=
tmp_25_fu_1202_p1 when (isNeg_2_reg_1636(0) = '1') else
tmp_20_i_fu_1197_p2;
p_Val2_34_fu_1233_p2 <= std_logic_vector(signed(tmp_35_cast_i_fu_1225_p1) - signed(tmp_21_i_fu_1229_p1));
p_Val2_3_fu_483_p2 <= std_logic_vector(unsigned(tmp_3_i_fu_475_p3) + unsigned(reg_316));
p_Val2_41_fu_1145_p3 <=
control_reg_init_V when (control_reg_clr(0) = '1') else
p_Val2_5_fu_1053_p2;
p_Val2_4_fu_1041_p3 <=
tmp_18_fu_1037_p1 when (isNeg_1_fu_995_p3(0) = '1') else
tmp_11_i_fu_1031_p2;
p_Val2_5_fu_1053_p2 <= std_logic_vector(unsigned(i_reg_V) + unsigned(p_Val2_4_reg_1625));
p_Val2_9_fu_664_p1 <= grp_fu_276_p2(21 - 1 downto 0);
p_Val2_i1_fu_768_p3 <=
ap_const_lv14_2000 when (underflow_2_fu_738_p2(0) = '1') else
p_Val2_9_reg_1568;
p_Val2_i2_fu_1129_p3 <=
ap_const_lv28_8000000 when (underflow_4_fu_1097_p2(0) = '1') else
p_Val2_29_fu_1079_p1;
p_not38_i1_i_fu_420_p2 <= "0" when (p_Result_i_fu_380_p4 = ap_const_lv2_3) else "1";
p_not38_i_i1_fu_727_p2 <= "0" when (p_Result_i8_reg_1580 = ap_const_lv2_3) else "1";
p_not38_i_i_fu_551_p2 <= "0" when (p_Result_1_i_reg_1541 = ap_const_lv2_3) else "1";
p_not38_i_i_i_fu_866_p2 <= "0" when (tmp_7_fu_826_p4 = ap_const_lv2_3) else "1";
p_not_i1_i_fu_390_p2 <= "0" when (p_Result_i_fu_380_p4 = ap_const_lv2_0) else "1";
p_not_i_i9_fu_701_p2 <= "0" when (p_Result_i8_reg_1580 = ap_const_lv2_0) else "1";
p_not_i_i_fu_525_p2 <= "0" when (p_Result_1_i_reg_1541 = ap_const_lv2_0) else "1";
p_not_i_i_i_fu_836_p2 <= "0" when (tmp_7_fu_826_p4 = ap_const_lv2_0) else "1";
ph_out_i_V <=
tmp_12_fu_1391_p1 when (sel_tmp7_i_fu_1369_p2(0) = '1') else
tmp_28_fu_1405_p3;
-- ph_out_i_V_ap_vld assign process. --
ph_out_i_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ph_out_i_V_ap_vld <= ap_const_logic_1;
else
ph_out_i_V_ap_vld <= ap_const_logic_0;
end if;
end process;
ph_out_q_V <=
tmp_32_fu_1446_p3 when (or_cond_fu_1375_p2(0) = '1') else
tmp_33_fu_1454_p3;
-- ph_out_q_V_ap_vld assign process. --
ph_out_q_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ph_out_q_V_ap_vld <= ap_const_logic_1;
else
ph_out_q_V_ap_vld <= ap_const_logic_0;
end if;
end process;
sel_tmp3_demorgan_i_fu_1345_p2 <= (tmp_25_i_fu_1318_p2 or tmp_26_i_fu_1323_p2);
sel_tmp3_i_fu_1351_p2 <= (sel_tmp3_demorgan_i_fu_1345_p2 xor ap_const_lv1_1);
sel_tmp4_i_fu_1357_p2 <= (tmp_27_i_fu_1328_p2 and sel_tmp3_i_fu_1351_p2);
sel_tmp6_i_fu_1363_p2 <= (tmp_25_i_fu_1318_p2 xor ap_const_lv1_1);
sel_tmp7_i_fu_1369_p2 <= (tmp_26_i_fu_1323_p2 and sel_tmp6_i_fu_1363_p2);
sel_tmp_i_fu_1339_p2 <= std_logic_vector(unsigned(ap_const_lv16_0) - unsigned(p_Val2_32_cast_i_fu_1310_p1));
sh_assign_1_cast6_i_fu_949_p1 <= std_logic_vector(resize(unsigned(sh_assign_fu_941_p3),28));
sh_assign_1_cast_i_fu_953_p1 <= std_logic_vector(resize(unsigned(sh_assign_fu_941_p3),32));
sh_assign_1_fu_989_p2 <= std_logic_vector(signed(tmp_19_cast_i_fu_985_p1) + signed(ap_const_lv9_9));
sh_assign_2_fu_1009_p3 <=
tmp_8_i1_fu_1003_p2 when (isNeg_1_fu_995_p3(0) = '1') else
sh_assign_1_fu_989_p2;
sh_assign_3_cast5_i_fu_1017_p1 <= std_logic_vector(resize(signed(sh_assign_2_fu_1009_p3),28));
sh_assign_3_cast_i_fu_1021_p1 <= std_logic_vector(resize(signed(sh_assign_2_fu_1009_p3),32));
sh_assign_3_fu_1174_p3 <=
tmp_17_i_fu_1168_p2 when (isNeg_2_fu_1160_p3(0) = '1') else
control_lf_out_gain;
sh_assign_5_cast3_i_fu_1182_p1 <= std_logic_vector(resize(unsigned(sh_assign_3_reg_1641),28));
sh_assign_5_cast_i_fu_1185_p1 <= std_logic_vector(resize(unsigned(sh_assign_3_reg_1641),32));
sh_assign_fu_941_p3 <=
tmp_4_i_fu_935_p2 when (isNeg_fu_927_p3(0) = '1') else
control_lf_p;
sin_adr_V_1_fu_1294_p3 <=
sin_adr_V_reg_1660 when (tmp_26_reg_1654(0) = '1') else
cos_adr_V_3_fu_1283_p2;
sin_out_V_fu_1333_p2 <= std_logic_vector(unsigned(ap_const_lv16_0) - unsigned(p_Val2_31_cast_i_fu_1314_p1));
ssdm_int_V_write_assign_fu_898_p3 <=
ap_const_lv14_1FFF when (brmerge_i_i_i_i_fu_884_p2(0) = '1') else
p_Val2_24_reg_1601;
tmp_10_cast_i_fu_790_p1 <= std_logic_vector(resize(signed(tmp_1_i1_fu_783_p3),21));
tmp_10_fu_911_p3 <=
ssdm_int_V_write_assign_fu_898_p3 when (brmerge1_i_fu_893_p2(0) = '1') else
p_Val2_1_i_fu_905_p3;
tmp_10_i_fu_1025_p2 <= std_logic_vector(shift_left(unsigned(tmp_5_i1_fu_957_p1),to_integer(unsigned('0' & sh_assign_3_cast_i_fu_1021_p1(31-1 downto 0)))));
tmp_11_fu_1381_p4 <= cos_lut_q0(14 downto 4);
tmp_11_i_fu_1031_p2 <= std_logic_vector(shift_right(signed(tmp_i1_fu_919_p3),to_integer(unsigned('0' & sh_assign_3_cast5_i_fu_1017_p1(28-1 downto 0)))));
tmp_12_fu_1391_p1 <= std_logic_vector(resize(unsigned(tmp_11_fu_1381_p4),12));
tmp_12_i_fu_1058_p1 <= std_logic_vector(resize(signed(p_Val2_5_fu_1053_p2),29));
tmp_13_i_fu_1062_p1 <= std_logic_vector(resize(signed(p_Val2_26_reg_1620),29));
tmp_15_i_fu_1091_p2 <= (newsignbit_4_fu_1083_p3 xor ap_const_lv1_1);
tmp_16_fu_973_p1 <= tmp_6_i2_fu_961_p2(28 - 1 downto 0);
tmp_16_i_fu_1137_p3 <=
p_Val2_28_mux_i_fu_1121_p3 when (brmerge_i1_fu_1115_p2(0) = '1') else
p_Val2_i2_fu_1129_p3;
tmp_17_i_fu_1168_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(control_lf_out_gain));
tmp_18_fu_1037_p1 <= tmp_10_i_fu_1025_p2(28 - 1 downto 0);
tmp_18_i_fu_1188_p1 <= std_logic_vector(resize(signed(tmp_16_i_reg_1630),32));
tmp_19_cast_i_fu_985_p1 <= std_logic_vector(resize(signed(control_lf_i),9));
tmp_19_i_fu_1191_p2 <= std_logic_vector(shift_left(unsigned(tmp_18_i_fu_1188_p1),to_integer(unsigned('0' & sh_assign_5_cast_i_fu_1185_p1(31-1 downto 0)))));
tmp_1_fu_335_p1 <= std_logic_vector(resize(signed(din_q_V),27));
tmp_1_i1_fu_783_p3 <= (tmp_9_reg_1596 & ap_const_lv5_0);
tmp_1_i3_fu_637_p3 <= (tmp_6_reg_1547 & ap_const_lv1_1);
tmp_20_i_fu_1197_p2 <= std_logic_vector(shift_right(signed(tmp_16_i_reg_1630),to_integer(unsigned('0' & sh_assign_5_cast3_i_fu_1182_p1(28-1 downto 0)))));
tmp_21_i_fu_1229_p1 <= std_logic_vector(resize(unsigned(p_Val2_33_fu_1206_p3),29));
tmp_23_i_fu_1300_p1 <= std_logic_vector(resize(unsigned(cos_adr_V_fu_1288_p3),64));
tmp_24_i_fu_1305_p1 <= std_logic_vector(resize(unsigned(sin_adr_V_1_fu_1294_p3),64));
tmp_25_fu_1202_p1 <= tmp_19_i_fu_1191_p2(28 - 1 downto 0);
tmp_25_i_fu_1318_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_1) else "0";
tmp_26_i_fu_1323_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_0) else "0";
tmp_27_fu_1395_p4 <= sel_tmp_i_fu_1339_p2(15 downto 4);
tmp_27_i_fu_1328_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_3) else "0";
tmp_28_fu_1405_p3 <=
tmp_12_fu_1391_p1 when (sel_tmp4_i_fu_1357_p2(0) = '1') else
tmp_27_fu_1395_p4;
tmp_29_fu_1422_p4 <= cos_lut_q1(14 downto 4);
tmp_30_fu_1432_p1 <= std_logic_vector(resize(unsigned(tmp_29_fu_1422_p4),12));
tmp_31_fu_1436_p4 <= sin_out_V_fu_1333_p2(15 downto 4);
tmp_32_fu_1446_p3 <=
tmp_30_fu_1432_p1 when (sel_tmp7_i_fu_1369_p2(0) = '1') else
tmp_31_fu_1436_p4;
tmp_33_fu_1454_p3 <=
tmp_30_fu_1432_p1 when (tmp_25_i_fu_1318_p2(0) = '1') else
tmp_31_fu_1436_p4;
tmp_35_cast_i_fu_1225_p1 <= std_logic_vector(resize(signed(tmp_i2_15_fu_1217_p3),29));
tmp_3_fu_467_p3 <=
tmp_5_fu_458_p2 when (brmerge8_i_fu_447_p2(0) = '1') else
tmp_s_fu_463_p2;
tmp_3_i1_fu_848_p2 <= (isneg_3_fu_800_p3 xor ap_const_lv1_1);
tmp_3_i_fu_475_p3 <= (reg_312 & ap_const_lv11_0);
tmp_4_fu_610_p2 <= (newsignbit_1_reg_1533 and not_brmerge_i_i_i_fu_604_p2);
tmp_4_i_fu_935_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(control_lf_p));
tmp_5_fu_458_p2 <= (newsignbit_reg_1497 and not_brmerge_i_i1_i_fu_452_p2);
tmp_5_i1_fu_957_p1 <= std_logic_vector(resize(signed(tmp_i1_fu_919_p3),32));
tmp_5_i_fu_402_p2 <= (isneg_fu_364_p3 xor ap_const_lv1_1);
tmp_6_fu_620_p3 <=
tmp_4_fu_610_p2 when (brmerge9_i_fu_579_p2(0) = '1') else
tmp_8_fu_615_p2;
tmp_6_i2_fu_961_p2 <= std_logic_vector(shift_left(unsigned(tmp_5_i1_fu_957_p1),to_integer(unsigned('0' & sh_assign_1_cast_i_fu_953_p1(31-1 downto 0)))));
tmp_6_i_fu_340_p3 <= (reg_312 & ap_const_lv11_0);
tmp_7_fu_826_p4 <= p_Val2_23_fu_794_p2(20 downto 19);
tmp_7_i1_fu_967_p2 <= std_logic_vector(shift_right(signed(tmp_i1_fu_919_p3),to_integer(unsigned('0' & sh_assign_1_cast6_i_fu_949_p1(28-1 downto 0)))));
tmp_7_i_fu_535_p2 <= (isneg_1_reg_1527 xor ap_const_lv1_1);
tmp_8_fu_615_p2 <= (underflow_1_fu_562_p2 or newsignbit_1_reg_1533);
tmp_8_i1_fu_1003_p2 <= std_logic_vector(signed(ap_const_lv9_1F7) - signed(tmp_19_cast_i_fu_985_p1));
tmp_8_i_fu_711_p2 <= (isneg_2_reg_1562 xor ap_const_lv1_1);
tmp_9_fu_775_p3 <=
p_Val2_21_mux_i_fu_761_p3 when (brmerge_i_fu_755_p2(0) = '1') else
p_Val2_i1_fu_768_p3;
tmp_i1_fu_919_p3 <= (tmp_10_fu_911_p3 & ap_const_lv14_0);
tmp_i2_15_fu_1217_p3 <= (phase_angle_V & ap_const_lv11_0);
tmp_i2_fu_585_p3 <= (tmp_3_reg_1516 & ap_const_lv1_1);
tmp_s_fu_463_p2 <= (underflow_reg_1509 or newsignbit_reg_1497);
underflow_1_fu_562_p2 <= (brmerge39_i_i_fu_556_p2 and isneg_1_reg_1527);
underflow_1_not_i_fu_573_p2 <= (underflow_1_fu_562_p2 xor ap_const_lv1_1);
underflow_2_fu_738_p2 <= (brmerge39_i_i1_fu_732_p2 and isneg_2_reg_1562);
underflow_3_fu_878_p2 <= (brmerge39_i_i_i_fu_872_p2 and isneg_3_fu_800_p3);
underflow_4_fu_1097_p2 <= (isneg_4_fu_1071_p3 and tmp_15_i_fu_1091_p2);
underflow_4_not_i_fu_888_p2 <= (underflow_3_reg_1613 xor ap_const_lv1_1);
underflow_fu_432_p2 <= (brmerge39_i1_i_fu_426_p2 and isneg_fu_364_p3);
underflow_not_i1_fu_749_p2 <= (underflow_2_fu_738_p2 xor ap_const_lv1_1);
underflow_not_i_fu_442_p2 <= (underflow_reg_1509 xor ap_const_lv1_1);
end behav;
| gpl-2.0 |
Diego-HR/HL-Object-Oriented | QAMDemodulator/src/solution1/syn/vhdl/qam_dem_top_mounstrito.vhd | 4 | 63258 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity qam_dem_top_mounstrito is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
din_i_V : IN STD_LOGIC_VECTOR (15 downto 0);
din_q_V : IN STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V_ap_vld : OUT STD_LOGIC;
dout_mix_q_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_q_V_ap_vld : OUT STD_LOGIC;
ph_in_i_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_in_q_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V_ap_vld : OUT STD_LOGIC;
ph_out_q_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_q_V_ap_vld : OUT STD_LOGIC;
loop_integ_V : OUT STD_LOGIC_VECTOR (27 downto 0);
loop_integ_V_ap_vld : OUT STD_LOGIC;
control_lf_p : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_i : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_out_gain : IN STD_LOGIC_VECTOR (7 downto 0);
control_reg_clr : IN STD_LOGIC_VECTOR (0 downto 0);
control_reg_init_V : IN STD_LOGIC_VECTOR (27 downto 0) );
end;
architecture behav of qam_dem_top_mounstrito is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv28_0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv14_1FFF : STD_LOGIC_VECTOR (13 downto 0) := "01111111111111";
constant ap_const_lv14_2000 : STD_LOGIC_VECTOR (13 downto 0) := "10000000000000";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv9_9 : STD_LOGIC_VECTOR (8 downto 0) := "000001001";
constant ap_const_lv9_1F7 : STD_LOGIC_VECTOR (8 downto 0) := "111110111";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv28_7FFFFFF : STD_LOGIC_VECTOR (27 downto 0) := "0111111111111111111111111111";
constant ap_const_lv28_8000000 : STD_LOGIC_VECTOR (27 downto 0) := "1000000000000000000000000000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv10_3FF : STD_LOGIC_VECTOR (9 downto 0) := "1111111111";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_34 : BOOLEAN;
signal i_reg_V : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
signal phase_angle_V : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal cos_lut_address0 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_lut_ce0 : STD_LOGIC;
signal cos_lut_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal cos_lut_address1 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_lut_ce1 : STD_LOGIC;
signal cos_lut_q1 : STD_LOGIC_VECTOR (14 downto 0);
signal reg_312 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_82 : BOOLEAN;
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_89 : BOOLEAN;
signal grp_fu_276_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal reg_316 : STD_LOGIC_VECTOR (26 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_99 : BOOLEAN;
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_106 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal OP1_V_i_cast_fu_320_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP1_V_i_cast_reg_1471 : STD_LOGIC_VECTOR (26 downto 0);
signal ap_sig_bdd_122 : BOOLEAN;
signal OP2_V_i_cast_fu_325_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_i_cast_reg_1476 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_1_i_cast_fu_330_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_1_i_cast_reg_1481 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_1_fu_335_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_1_reg_1486 : STD_LOGIC_VECTOR (26 downto 0);
signal sd_out_i_V_reg_1491 : STD_LOGIC_VECTOR (15 downto 0);
signal newsignbit_fu_372_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_reg_1497 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_fu_408_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_reg_1503 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_fu_432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_reg_1509 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_467_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_1516 : STD_LOGIC_VECTOR (0 downto 0);
signal sd_out_q_V_reg_1521 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_148 : BOOLEAN;
signal isneg_1_reg_1527 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_1_reg_1533 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_1_i_reg_1541 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_6_fu_620_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1547 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_163 : BOOLEAN;
signal OP1_V_fu_628_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal OP2_V_fu_633_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal isneg_2_reg_1562 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_176 : BOOLEAN;
signal p_Val2_9_reg_1568 : STD_LOGIC_VECTOR (13 downto 0);
signal newsignbit_2_reg_1574 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_i8_reg_1580 : STD_LOGIC_VECTOR (1 downto 0);
signal OP1_V_1_fu_692_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal OP2_V_1_fu_697_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal tmp_9_fu_775_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_9_reg_1596 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_24_reg_1601 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_197 : BOOLEAN;
signal overflow_3_fu_854_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_3_reg_1607 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_3_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_3_reg_1613 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_26_fu_977_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_26_reg_1620 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_210 : BOOLEAN;
signal p_Val2_4_fu_1041_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_4_reg_1625 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_16_i_fu_1137_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_16_i_reg_1630 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_221 : BOOLEAN;
signal isNeg_2_fu_1160_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal isNeg_2_reg_1636 : STD_LOGIC_VECTOR (0 downto 0);
signal sh_assign_3_fu_1174_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sh_assign_3_reg_1641 : STD_LOGIC_VECTOR (7 downto 0);
signal msb_V_reg_1647 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_234 : BOOLEAN;
signal tmp_26_reg_1654 : STD_LOGIC_VECTOR (0 downto 0);
signal sin_adr_V_reg_1660 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_247 : BOOLEAN;
signal tmp_23_i_fu_1300_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_i_fu_1305_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Val2_41_fu_1145_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal loop_integ_V_preg : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_275 : BOOLEAN;
signal grp_fu_276_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_276_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_6_i_fu_340_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_1_fu_348_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Result_i_fu_380_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal p_not_i1_i_fu_390_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_fu_364_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i1_i_fu_396_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_i_fu_402_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i1_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i1_i_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_not_i_fu_442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_i_fu_438_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_brmerge_i_i1_i_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge8_i_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_458_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_463_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_i_fu_475_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_3_fu_483_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_not_i_i_fu_525_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_fu_530_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_i_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i_fu_546_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_1_fu_540_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_1_not_i_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i2_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal brmerge_i_i_i_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_brmerge_i_i_i_fu_604_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge9_i_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_615_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_s_fu_592_p5 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_i3_fu_637_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal isneg_2_fu_656_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_9_fu_664_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal newsignbit_2_fu_674_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Result_i8_fu_682_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Result_2_fu_644_p5 : STD_LOGIC_VECTOR (4 downto 0);
signal p_not_i_i9_fu_701_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_fu_706_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i_fu_711_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i1_fu_727_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i1_fu_722_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i1_fu_732_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_2_fu_738_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_2_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_not_i1_fu_749_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i1_fu_743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_fu_755_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_21_mux_i_fu_761_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_i1_fu_768_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_1_i1_fu_783_p3 : STD_LOGIC_VECTOR (18 downto 0);
signal tmp_10_cast_i_fu_790_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_23_fu_794_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_23_fu_794_p2 : STD_LOGIC_VECTOR (20 downto 0);
signal tmp_7_fu_826_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal newsignbit_3_fu_818_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not_i_i_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_3_fu_800_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i4_i_fu_842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_i1_fu_848_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i_i_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i_i_fu_860_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_4_not_i_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i_i_fu_884_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge1_i_fu_893_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ssdm_int_V_write_assign_fu_898_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_1_i_fu_905_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_10_fu_911_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal isNeg_fu_927_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_fu_935_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal sh_assign_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_i1_fu_919_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_5_i1_fu_957_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast_i_fu_953_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast6_i_fu_949_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_6_i2_fu_961_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_973_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_7_i1_fu_967_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_cast_i_fu_985_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_1_fu_989_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal isNeg_1_fu_995_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i1_fu_1003_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_2_fu_1009_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_3_cast_i_fu_1021_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_3_cast5_i_fu_1017_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_10_i_fu_1025_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_1037_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_11_i_fu_1031_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_5_fu_1053_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_12_i_fu_1058_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_13_i_fu_1062_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_27_fu_1065_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal newsignbit_4_fu_1083_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_4_fu_1071_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_i_fu_1091_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_not_i_fu_1109_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i2_fu_1103_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_29_fu_1079_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal underflow_4_fu_1097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i1_fu_1115_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_28_mux_i_fu_1121_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_i2_fu_1129_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_17_i_fu_1168_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_i_fu_1188_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_5_cast_i_fu_1185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_5_cast3_i_fu_1182_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_i_fu_1191_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_1202_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_20_i_fu_1197_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_i2_15_fu_1217_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_33_fu_1206_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_35_cast_i_fu_1225_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_21_i_fu_1229_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_34_fu_1233_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal cos_adr_V_3_fu_1283_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_adr_V_fu_1288_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal sin_adr_V_1_fu_1294_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal p_Val2_31_cast_i_fu_1314_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal p_Val2_32_cast_i_fu_1310_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_25_i_fu_1318_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_i_fu_1323_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_demorgan_i_fu_1345_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_i_fu_1328_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_i_fu_1351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_i_fu_1363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_i_fu_1369_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_i_fu_1357_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_1381_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal sel_tmp_i_fu_1339_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_12_fu_1391_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_27_fu_1395_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_28_fu_1405_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_29_fu_1422_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal sin_out_V_fu_1333_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_30_fu_1432_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_31_fu_1436_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal or_cond_fu_1375_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_1446_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_33_fu_1454_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_276_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component qam_dem_top_mul_16s_12s_27_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (11 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (26 downto 0) );
end component;
component qam_dem_top_mounstrito_cos_lut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (9 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0);
address1 : IN STD_LOGIC_VECTOR (9 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
begin
cos_lut_U : component qam_dem_top_mounstrito_cos_lut
generic map (
DataWidth => 15,
AddressRange => 1024,
AddressWidth => 10)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => cos_lut_address0,
ce0 => cos_lut_ce0,
q0 => cos_lut_q0,
address1 => cos_lut_address1,
ce1 => cos_lut_ce1,
q1 => cos_lut_q1);
qam_dem_top_mul_16s_12s_27_2_U1 : component qam_dem_top_mul_16s_12s_27_2
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 16,
din1_WIDTH => 12,
dout_WIDTH => 27)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_276_p0,
din1 => grp_fu_276_p1,
ce => grp_fu_276_ce,
dout => grp_fu_276_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- loop_integ_V_preg assign process. --
loop_integ_V_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
loop_integ_V_preg <= ap_const_lv28_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V_preg <= p_Val2_41_fu_1145_p3;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_122))) then
OP1_V_i_cast_reg_1471 <= OP1_V_i_cast_fu_320_p1;
OP2_V_i_cast_reg_1476 <= OP2_V_i_cast_fu_325_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
OP2_V_1_i_cast_reg_1481 <= OP2_V_1_i_cast_fu_330_p1;
tmp_1_reg_1486 <= tmp_1_fu_335_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
i_reg_V <= p_Val2_41_fu_1145_p3;
isNeg_2_reg_1636 <= control_lf_out_gain(7 downto 7);
sh_assign_3_reg_1641 <= sh_assign_3_fu_1174_p3;
tmp_16_i_reg_1630 <= tmp_16_i_fu_1137_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
isneg_1_reg_1527 <= p_Val2_3_fu_483_p2(26 downto 26);
newsignbit_1_reg_1533 <= p_Val2_3_fu_483_p2(24 downto 24);
p_Result_1_i_reg_1541 <= p_Val2_3_fu_483_p2(26 downto 25);
sd_out_q_V_reg_1521 <= p_Val2_3_fu_483_p2(26 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
isneg_2_reg_1562 <= isneg_2_fu_656_p1(20 downto 20);
newsignbit_2_reg_1574 <= newsignbit_2_fu_674_p1(18 downto 18);
p_Result_i8_reg_1580 <= p_Result_i8_fu_682_p1(20 downto 19);
p_Val2_9_reg_1568 <= p_Val2_9_fu_664_p1(18 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
msb_V_reg_1647 <= p_Val2_34_fu_1233_p2(26 downto 25);
phase_angle_V <= p_Val2_34_fu_1233_p2(26 downto 11);
sin_adr_V_reg_1660 <= p_Val2_34_fu_1233_p2(24 downto 15);
tmp_26_reg_1654 <= p_Val2_34_fu_1233_p2(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
newsignbit_reg_1497 <= p_Val2_1_fu_348_p2(24 downto 24);
overflow_reg_1503 <= overflow_fu_408_p2;
sd_out_i_V_reg_1491 <= p_Val2_1_fu_348_p2(26 downto 11);
underflow_reg_1509 <= underflow_fu_432_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
overflow_3_reg_1607 <= overflow_3_fu_854_p2;
p_Val2_24_reg_1601 <= p_Val2_23_fu_794_p2(18 downto 5);
underflow_3_reg_1613 <= underflow_3_fu_878_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
p_Val2_26_reg_1620 <= p_Val2_26_fu_977_p3;
p_Val2_4_reg_1625 <= p_Val2_4_fu_1041_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
reg_312 <= grp_fu_276_p2(26 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8))) then
reg_316 <= grp_fu_276_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_3_reg_1516 <= tmp_3_fu_467_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
tmp_6_reg_1547 <= tmp_6_fu_620_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_9_reg_1596 <= tmp_9_fu_775_p3;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_122)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_122)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
OP1_V_1_fu_692_p1 <= std_logic_vector(resize(signed(p_Result_2_fu_644_p5),21));
OP1_V_fu_628_p1 <= std_logic_vector(resize(signed(p_Result_s_fu_592_p5),21));
OP1_V_i_cast_fu_320_p1 <= std_logic_vector(resize(signed(din_i_V),27));
OP2_V_1_fu_697_p1 <= std_logic_vector(resize(signed(sd_out_i_V_reg_1491),21));
OP2_V_1_i_cast_fu_330_p1 <= std_logic_vector(resize(signed(ph_in_q_V),27));
OP2_V_fu_633_p1 <= std_logic_vector(resize(signed(sd_out_q_V_reg_1521),21));
OP2_V_i_cast_fu_325_p1 <= std_logic_vector(resize(signed(ph_in_i_V),27));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st15_fsm_14)
begin
if (((ap_const_logic_1 = ap_done_reg) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_106 assign process. --
ap_sig_bdd_106_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_106 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_122 assign process. --
ap_sig_bdd_122_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_122 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_148 assign process. --
ap_sig_bdd_148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_148 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_163 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_176 assign process. --
ap_sig_bdd_176_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_176 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_197 assign process. --
ap_sig_bdd_197_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_197 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_210 assign process. --
ap_sig_bdd_210_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_210 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_221 assign process. --
ap_sig_bdd_221_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_221 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_234 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_247 assign process. --
ap_sig_bdd_247_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_247 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_275 assign process. --
ap_sig_bdd_275_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_275 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_34 assign process. --
ap_sig_bdd_34_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_34 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_82 assign process. --
ap_sig_bdd_82_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_82 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_89 assign process. --
ap_sig_bdd_89_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_99 assign process. --
ap_sig_bdd_99_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_99 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_197)
begin
if (ap_sig_bdd_197) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_210)
begin
if (ap_sig_bdd_210) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_221)
begin
if (ap_sig_bdd_221) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_234)
begin
if (ap_sig_bdd_234) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_247)
begin
if (ap_sig_bdd_247) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_34)
begin
if (ap_sig_bdd_34) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_82)
begin
if (ap_sig_bdd_82) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_99)
begin
if (ap_sig_bdd_99) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_89)
begin
if (ap_sig_bdd_89) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_106)
begin
if (ap_sig_bdd_106) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_148)
begin
if (ap_sig_bdd_148) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_163)
begin
if (ap_sig_bdd_163) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_176)
begin
if (ap_sig_bdd_176) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
brmerge1_i_fu_893_p2 <= (overflow_3_reg_1607 or underflow_4_not_i_fu_888_p2);
brmerge39_i1_i_fu_426_p2 <= (p_not38_i1_i_fu_420_p2 or newsignbit_0_not_i1_i_fu_414_p2);
brmerge39_i_i1_fu_732_p2 <= (p_not38_i_i1_fu_727_p2 or newsignbit_0_not_i_i1_fu_722_p2);
brmerge39_i_i_fu_556_p2 <= (p_not38_i_i_fu_551_p2 or newsignbit_0_not_i_i_fu_546_p2);
brmerge39_i_i_i_fu_872_p2 <= (p_not38_i_i_i_fu_866_p2 or newsignbit_0_not_i_i_i_fu_860_p2);
brmerge8_i_fu_447_p2 <= (overflow_reg_1503 or underflow_not_i_fu_442_p2);
brmerge9_i_fu_579_p2 <= (overflow_1_fu_540_p2 or underflow_1_not_i_fu_573_p2);
brmerge_i1_fu_1115_p2 <= (newsignbit_4_fu_1083_p3 or isneg_not_i_fu_1109_p2);
brmerge_i1_i_fu_396_p2 <= (newsignbit_fu_372_p3 or p_not_i1_i_fu_390_p2);
brmerge_i_fu_755_p2 <= (overflow_2_fu_716_p2 or underflow_not_i1_fu_749_p2);
brmerge_i_i1_fu_706_p2 <= (newsignbit_2_reg_1574 or p_not_i_i9_fu_701_p2);
brmerge_i_i1_i_fu_438_p2 <= (underflow_reg_1509 or overflow_reg_1503);
brmerge_i_i4_i_fu_842_p2 <= (newsignbit_3_fu_818_p3 or p_not_i_i_i_fu_836_p2);
brmerge_i_i_fu_530_p2 <= (newsignbit_1_reg_1533 or p_not_i_i_fu_525_p2);
brmerge_i_i_i1_fu_743_p2 <= (underflow_2_fu_738_p2 or overflow_2_fu_716_p2);
brmerge_i_i_i2_fu_1103_p2 <= (isneg_4_fu_1071_p3 xor newsignbit_4_fu_1083_p3);
brmerge_i_i_i_fu_567_p2 <= (underflow_1_fu_562_p2 or overflow_1_fu_540_p2);
brmerge_i_i_i_i_fu_884_p2 <= (underflow_3_reg_1613 or overflow_3_reg_1607);
cos_adr_V_3_fu_1283_p2 <= (sin_adr_V_reg_1660 xor ap_const_lv10_3FF);
cos_adr_V_fu_1288_p3 <=
cos_adr_V_3_fu_1283_p2 when (tmp_26_reg_1654(0) = '1') else
sin_adr_V_reg_1660;
cos_lut_address0 <= tmp_23_i_fu_1300_p1(10 - 1 downto 0);
cos_lut_address1 <= tmp_24_i_fu_1305_p1(10 - 1 downto 0);
-- cos_lut_ce0 assign process. --
cos_lut_ce0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
cos_lut_ce0 <= ap_const_logic_1;
else
cos_lut_ce0 <= ap_const_logic_0;
end if;
end process;
-- cos_lut_ce1 assign process. --
cos_lut_ce1_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
cos_lut_ce1 <= ap_const_logic_1;
else
cos_lut_ce1 <= ap_const_logic_0;
end if;
end process;
dout_mix_i_V <= sd_out_i_V_reg_1491;
-- dout_mix_i_V_ap_vld assign process. --
dout_mix_i_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
dout_mix_i_V_ap_vld <= ap_const_logic_1;
else
dout_mix_i_V_ap_vld <= ap_const_logic_0;
end if;
end process;
dout_mix_q_V <= sd_out_q_V_reg_1521;
-- dout_mix_q_V_ap_vld assign process. --
dout_mix_q_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
dout_mix_q_V_ap_vld <= ap_const_logic_1;
else
dout_mix_q_V_ap_vld <= ap_const_logic_0;
end if;
end process;
-- grp_fu_276_ce assign process. --
grp_fu_276_ce_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st9_fsm_8, ap_sig_bdd_122, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_122)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then
grp_fu_276_ce <= ap_const_logic_1;
else
grp_fu_276_ce <= ap_const_logic_0;
end if;
end process;
-- grp_fu_276_p0 assign process. --
grp_fu_276_p0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, OP1_V_i_cast_fu_320_p1, OP1_V_i_cast_reg_1471, tmp_1_fu_335_p1, tmp_1_reg_1486, ap_sig_cseq_ST_st7_fsm_6, OP2_V_fu_633_p1, ap_sig_cseq_ST_st8_fsm_7, OP2_V_1_fu_697_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
grp_fu_276_p0 <= OP2_V_1_fu_697_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
grp_fu_276_p0 <= OP2_V_fu_633_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
grp_fu_276_p0 <= tmp_1_reg_1486(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
grp_fu_276_p0 <= OP1_V_i_cast_reg_1471(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_276_p0 <= tmp_1_fu_335_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_276_p0 <= OP1_V_i_cast_fu_320_p1(16 - 1 downto 0);
else
grp_fu_276_p0 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_276_p1 assign process. --
grp_fu_276_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, OP2_V_i_cast_fu_325_p1, OP2_V_i_cast_reg_1476, OP2_V_1_i_cast_fu_330_p1, OP2_V_1_i_cast_reg_1481, ap_sig_cseq_ST_st7_fsm_6, OP1_V_fu_628_p1, ap_sig_cseq_ST_st8_fsm_7, OP1_V_1_fu_692_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
grp_fu_276_p1 <= OP1_V_1_fu_692_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
grp_fu_276_p1 <= OP1_V_fu_628_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
grp_fu_276_p1 <= OP2_V_i_cast_reg_1476(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
grp_fu_276_p1 <= OP2_V_1_i_cast_reg_1481(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_276_p1 <= OP2_V_1_i_cast_fu_330_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_276_p1 <= OP2_V_i_cast_fu_325_p1(12 - 1 downto 0);
else
grp_fu_276_p1 <= "XXXXXXXXXXXX";
end if;
end process;
isNeg_1_fu_995_p3 <= sh_assign_1_fu_989_p2(8 downto 8);
isNeg_2_fu_1160_p3 <= control_lf_out_gain(7 downto 7);
isNeg_fu_927_p3 <= control_lf_p(7 downto 7);
isneg_2_fu_656_p1 <= grp_fu_276_p2(21 - 1 downto 0);
isneg_3_fu_800_p3 <= p_Val2_23_fu_794_p2(20 downto 20);
isneg_4_fu_1071_p3 <= p_Val2_27_fu_1065_p2(28 downto 28);
isneg_fu_364_p3 <= p_Val2_1_fu_348_p2(26 downto 26);
isneg_not_i_fu_1109_p2 <= (isneg_4_fu_1071_p3 xor ap_const_lv1_1);
-- loop_integ_V assign process. --
loop_integ_V_assign_proc : process(ap_sig_cseq_ST_st12_fsm_11, p_Val2_41_fu_1145_p3, loop_integ_V_preg)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V <= p_Val2_41_fu_1145_p3;
else
loop_integ_V <= loop_integ_V_preg;
end if;
end process;
-- loop_integ_V_ap_vld assign process. --
loop_integ_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st12_fsm_11)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V_ap_vld <= ap_const_logic_1;
else
loop_integ_V_ap_vld <= ap_const_logic_0;
end if;
end process;
newsignbit_0_not_i1_i_fu_414_p2 <= (newsignbit_fu_372_p3 xor ap_const_lv1_1);
newsignbit_0_not_i_i1_fu_722_p2 <= (newsignbit_2_reg_1574 xor ap_const_lv1_1);
newsignbit_0_not_i_i_fu_546_p2 <= (newsignbit_1_reg_1533 xor ap_const_lv1_1);
newsignbit_0_not_i_i_i_fu_860_p2 <= (newsignbit_3_fu_818_p3 xor ap_const_lv1_1);
newsignbit_2_fu_674_p1 <= grp_fu_276_p2(21 - 1 downto 0);
newsignbit_3_fu_818_p3 <= p_Val2_23_fu_794_p2(18 downto 18);
newsignbit_4_fu_1083_p3 <= p_Val2_27_fu_1065_p2(27 downto 27);
newsignbit_fu_372_p3 <= p_Val2_1_fu_348_p2(24 downto 24);
not_brmerge_i_i1_i_fu_452_p2 <= (brmerge_i_i1_i_fu_438_p2 xor ap_const_lv1_1);
not_brmerge_i_i_i_fu_604_p2 <= (brmerge_i_i_i_fu_567_p2 xor ap_const_lv1_1);
or_cond_fu_1375_p2 <= (sel_tmp7_i_fu_1369_p2 or sel_tmp4_i_fu_1357_p2);
overflow_1_fu_540_p2 <= (brmerge_i_i_fu_530_p2 and tmp_7_i_fu_535_p2);
overflow_2_fu_716_p2 <= (brmerge_i_i1_fu_706_p2 and tmp_8_i_fu_711_p2);
overflow_3_fu_854_p2 <= (brmerge_i_i4_i_fu_842_p2 and tmp_3_i1_fu_848_p2);
overflow_fu_408_p2 <= (brmerge_i1_i_fu_396_p2 and tmp_5_i_fu_402_p2);
p_Result_2_fu_644_p5 <= (tmp_1_i3_fu_637_p3 & ap_const_lv5_0(2 downto 0));
p_Result_i8_fu_682_p1 <= grp_fu_276_p2(21 - 1 downto 0);
p_Result_i_fu_380_p4 <= p_Val2_1_fu_348_p2(26 downto 25);
p_Result_s_fu_592_p5 <= (tmp_i2_fu_585_p3 & ap_const_lv5_0(2 downto 0));
p_Val2_1_fu_348_p2 <= std_logic_vector(unsigned(tmp_6_i_fu_340_p3) - unsigned(reg_316));
p_Val2_1_i_fu_905_p3 <=
ap_const_lv14_2000 when (underflow_3_reg_1613(0) = '1') else
p_Val2_24_reg_1601;
p_Val2_21_mux_i_fu_761_p3 <=
ap_const_lv14_1FFF when (brmerge_i_i_i1_fu_743_p2(0) = '1') else
p_Val2_9_reg_1568;
p_Val2_23_fu_794_p1 <= reg_316(21 - 1 downto 0);
p_Val2_23_fu_794_p2 <= std_logic_vector(signed(tmp_10_cast_i_fu_790_p1) - signed(p_Val2_23_fu_794_p1));
p_Val2_26_fu_977_p3 <=
tmp_16_fu_973_p1 when (isNeg_fu_927_p3(0) = '1') else
tmp_7_i1_fu_967_p2;
p_Val2_27_fu_1065_p2 <= std_logic_vector(signed(tmp_12_i_fu_1058_p1) + signed(tmp_13_i_fu_1062_p1));
p_Val2_28_mux_i_fu_1121_p3 <=
ap_const_lv28_7FFFFFF when (brmerge_i_i_i2_fu_1103_p2(0) = '1') else
p_Val2_29_fu_1079_p1;
p_Val2_29_fu_1079_p1 <= p_Val2_27_fu_1065_p2(28 - 1 downto 0);
p_Val2_31_cast_i_fu_1314_p1 <= std_logic_vector(resize(unsigned(cos_lut_q1),16));
p_Val2_32_cast_i_fu_1310_p1 <= std_logic_vector(resize(unsigned(cos_lut_q0),16));
p_Val2_33_fu_1206_p3 <=
tmp_25_fu_1202_p1 when (isNeg_2_reg_1636(0) = '1') else
tmp_20_i_fu_1197_p2;
p_Val2_34_fu_1233_p2 <= std_logic_vector(signed(tmp_35_cast_i_fu_1225_p1) - signed(tmp_21_i_fu_1229_p1));
p_Val2_3_fu_483_p2 <= std_logic_vector(unsigned(tmp_3_i_fu_475_p3) + unsigned(reg_316));
p_Val2_41_fu_1145_p3 <=
control_reg_init_V when (control_reg_clr(0) = '1') else
p_Val2_5_fu_1053_p2;
p_Val2_4_fu_1041_p3 <=
tmp_18_fu_1037_p1 when (isNeg_1_fu_995_p3(0) = '1') else
tmp_11_i_fu_1031_p2;
p_Val2_5_fu_1053_p2 <= std_logic_vector(unsigned(i_reg_V) + unsigned(p_Val2_4_reg_1625));
p_Val2_9_fu_664_p1 <= grp_fu_276_p2(21 - 1 downto 0);
p_Val2_i1_fu_768_p3 <=
ap_const_lv14_2000 when (underflow_2_fu_738_p2(0) = '1') else
p_Val2_9_reg_1568;
p_Val2_i2_fu_1129_p3 <=
ap_const_lv28_8000000 when (underflow_4_fu_1097_p2(0) = '1') else
p_Val2_29_fu_1079_p1;
p_not38_i1_i_fu_420_p2 <= "0" when (p_Result_i_fu_380_p4 = ap_const_lv2_3) else "1";
p_not38_i_i1_fu_727_p2 <= "0" when (p_Result_i8_reg_1580 = ap_const_lv2_3) else "1";
p_not38_i_i_fu_551_p2 <= "0" when (p_Result_1_i_reg_1541 = ap_const_lv2_3) else "1";
p_not38_i_i_i_fu_866_p2 <= "0" when (tmp_7_fu_826_p4 = ap_const_lv2_3) else "1";
p_not_i1_i_fu_390_p2 <= "0" when (p_Result_i_fu_380_p4 = ap_const_lv2_0) else "1";
p_not_i_i9_fu_701_p2 <= "0" when (p_Result_i8_reg_1580 = ap_const_lv2_0) else "1";
p_not_i_i_fu_525_p2 <= "0" when (p_Result_1_i_reg_1541 = ap_const_lv2_0) else "1";
p_not_i_i_i_fu_836_p2 <= "0" when (tmp_7_fu_826_p4 = ap_const_lv2_0) else "1";
ph_out_i_V <=
tmp_12_fu_1391_p1 when (sel_tmp7_i_fu_1369_p2(0) = '1') else
tmp_28_fu_1405_p3;
-- ph_out_i_V_ap_vld assign process. --
ph_out_i_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ph_out_i_V_ap_vld <= ap_const_logic_1;
else
ph_out_i_V_ap_vld <= ap_const_logic_0;
end if;
end process;
ph_out_q_V <=
tmp_32_fu_1446_p3 when (or_cond_fu_1375_p2(0) = '1') else
tmp_33_fu_1454_p3;
-- ph_out_q_V_ap_vld assign process. --
ph_out_q_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ph_out_q_V_ap_vld <= ap_const_logic_1;
else
ph_out_q_V_ap_vld <= ap_const_logic_0;
end if;
end process;
sel_tmp3_demorgan_i_fu_1345_p2 <= (tmp_25_i_fu_1318_p2 or tmp_26_i_fu_1323_p2);
sel_tmp3_i_fu_1351_p2 <= (sel_tmp3_demorgan_i_fu_1345_p2 xor ap_const_lv1_1);
sel_tmp4_i_fu_1357_p2 <= (tmp_27_i_fu_1328_p2 and sel_tmp3_i_fu_1351_p2);
sel_tmp6_i_fu_1363_p2 <= (tmp_25_i_fu_1318_p2 xor ap_const_lv1_1);
sel_tmp7_i_fu_1369_p2 <= (tmp_26_i_fu_1323_p2 and sel_tmp6_i_fu_1363_p2);
sel_tmp_i_fu_1339_p2 <= std_logic_vector(unsigned(ap_const_lv16_0) - unsigned(p_Val2_32_cast_i_fu_1310_p1));
sh_assign_1_cast6_i_fu_949_p1 <= std_logic_vector(resize(unsigned(sh_assign_fu_941_p3),28));
sh_assign_1_cast_i_fu_953_p1 <= std_logic_vector(resize(unsigned(sh_assign_fu_941_p3),32));
sh_assign_1_fu_989_p2 <= std_logic_vector(signed(tmp_19_cast_i_fu_985_p1) + signed(ap_const_lv9_9));
sh_assign_2_fu_1009_p3 <=
tmp_8_i1_fu_1003_p2 when (isNeg_1_fu_995_p3(0) = '1') else
sh_assign_1_fu_989_p2;
sh_assign_3_cast5_i_fu_1017_p1 <= std_logic_vector(resize(signed(sh_assign_2_fu_1009_p3),28));
sh_assign_3_cast_i_fu_1021_p1 <= std_logic_vector(resize(signed(sh_assign_2_fu_1009_p3),32));
sh_assign_3_fu_1174_p3 <=
tmp_17_i_fu_1168_p2 when (isNeg_2_fu_1160_p3(0) = '1') else
control_lf_out_gain;
sh_assign_5_cast3_i_fu_1182_p1 <= std_logic_vector(resize(unsigned(sh_assign_3_reg_1641),28));
sh_assign_5_cast_i_fu_1185_p1 <= std_logic_vector(resize(unsigned(sh_assign_3_reg_1641),32));
sh_assign_fu_941_p3 <=
tmp_4_i_fu_935_p2 when (isNeg_fu_927_p3(0) = '1') else
control_lf_p;
sin_adr_V_1_fu_1294_p3 <=
sin_adr_V_reg_1660 when (tmp_26_reg_1654(0) = '1') else
cos_adr_V_3_fu_1283_p2;
sin_out_V_fu_1333_p2 <= std_logic_vector(unsigned(ap_const_lv16_0) - unsigned(p_Val2_31_cast_i_fu_1314_p1));
ssdm_int_V_write_assign_fu_898_p3 <=
ap_const_lv14_1FFF when (brmerge_i_i_i_i_fu_884_p2(0) = '1') else
p_Val2_24_reg_1601;
tmp_10_cast_i_fu_790_p1 <= std_logic_vector(resize(signed(tmp_1_i1_fu_783_p3),21));
tmp_10_fu_911_p3 <=
ssdm_int_V_write_assign_fu_898_p3 when (brmerge1_i_fu_893_p2(0) = '1') else
p_Val2_1_i_fu_905_p3;
tmp_10_i_fu_1025_p2 <= std_logic_vector(shift_left(unsigned(tmp_5_i1_fu_957_p1),to_integer(unsigned('0' & sh_assign_3_cast_i_fu_1021_p1(31-1 downto 0)))));
tmp_11_fu_1381_p4 <= cos_lut_q0(14 downto 4);
tmp_11_i_fu_1031_p2 <= std_logic_vector(shift_right(signed(tmp_i1_fu_919_p3),to_integer(unsigned('0' & sh_assign_3_cast5_i_fu_1017_p1(28-1 downto 0)))));
tmp_12_fu_1391_p1 <= std_logic_vector(resize(unsigned(tmp_11_fu_1381_p4),12));
tmp_12_i_fu_1058_p1 <= std_logic_vector(resize(signed(p_Val2_5_fu_1053_p2),29));
tmp_13_i_fu_1062_p1 <= std_logic_vector(resize(signed(p_Val2_26_reg_1620),29));
tmp_15_i_fu_1091_p2 <= (newsignbit_4_fu_1083_p3 xor ap_const_lv1_1);
tmp_16_fu_973_p1 <= tmp_6_i2_fu_961_p2(28 - 1 downto 0);
tmp_16_i_fu_1137_p3 <=
p_Val2_28_mux_i_fu_1121_p3 when (brmerge_i1_fu_1115_p2(0) = '1') else
p_Val2_i2_fu_1129_p3;
tmp_17_i_fu_1168_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(control_lf_out_gain));
tmp_18_fu_1037_p1 <= tmp_10_i_fu_1025_p2(28 - 1 downto 0);
tmp_18_i_fu_1188_p1 <= std_logic_vector(resize(signed(tmp_16_i_reg_1630),32));
tmp_19_cast_i_fu_985_p1 <= std_logic_vector(resize(signed(control_lf_i),9));
tmp_19_i_fu_1191_p2 <= std_logic_vector(shift_left(unsigned(tmp_18_i_fu_1188_p1),to_integer(unsigned('0' & sh_assign_5_cast_i_fu_1185_p1(31-1 downto 0)))));
tmp_1_fu_335_p1 <= std_logic_vector(resize(signed(din_q_V),27));
tmp_1_i1_fu_783_p3 <= (tmp_9_reg_1596 & ap_const_lv5_0);
tmp_1_i3_fu_637_p3 <= (tmp_6_reg_1547 & ap_const_lv1_1);
tmp_20_i_fu_1197_p2 <= std_logic_vector(shift_right(signed(tmp_16_i_reg_1630),to_integer(unsigned('0' & sh_assign_5_cast3_i_fu_1182_p1(28-1 downto 0)))));
tmp_21_i_fu_1229_p1 <= std_logic_vector(resize(unsigned(p_Val2_33_fu_1206_p3),29));
tmp_23_i_fu_1300_p1 <= std_logic_vector(resize(unsigned(cos_adr_V_fu_1288_p3),64));
tmp_24_i_fu_1305_p1 <= std_logic_vector(resize(unsigned(sin_adr_V_1_fu_1294_p3),64));
tmp_25_fu_1202_p1 <= tmp_19_i_fu_1191_p2(28 - 1 downto 0);
tmp_25_i_fu_1318_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_1) else "0";
tmp_26_i_fu_1323_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_0) else "0";
tmp_27_fu_1395_p4 <= sel_tmp_i_fu_1339_p2(15 downto 4);
tmp_27_i_fu_1328_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_3) else "0";
tmp_28_fu_1405_p3 <=
tmp_12_fu_1391_p1 when (sel_tmp4_i_fu_1357_p2(0) = '1') else
tmp_27_fu_1395_p4;
tmp_29_fu_1422_p4 <= cos_lut_q1(14 downto 4);
tmp_30_fu_1432_p1 <= std_logic_vector(resize(unsigned(tmp_29_fu_1422_p4),12));
tmp_31_fu_1436_p4 <= sin_out_V_fu_1333_p2(15 downto 4);
tmp_32_fu_1446_p3 <=
tmp_30_fu_1432_p1 when (sel_tmp7_i_fu_1369_p2(0) = '1') else
tmp_31_fu_1436_p4;
tmp_33_fu_1454_p3 <=
tmp_30_fu_1432_p1 when (tmp_25_i_fu_1318_p2(0) = '1') else
tmp_31_fu_1436_p4;
tmp_35_cast_i_fu_1225_p1 <= std_logic_vector(resize(signed(tmp_i2_15_fu_1217_p3),29));
tmp_3_fu_467_p3 <=
tmp_5_fu_458_p2 when (brmerge8_i_fu_447_p2(0) = '1') else
tmp_s_fu_463_p2;
tmp_3_i1_fu_848_p2 <= (isneg_3_fu_800_p3 xor ap_const_lv1_1);
tmp_3_i_fu_475_p3 <= (reg_312 & ap_const_lv11_0);
tmp_4_fu_610_p2 <= (newsignbit_1_reg_1533 and not_brmerge_i_i_i_fu_604_p2);
tmp_4_i_fu_935_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(control_lf_p));
tmp_5_fu_458_p2 <= (newsignbit_reg_1497 and not_brmerge_i_i1_i_fu_452_p2);
tmp_5_i1_fu_957_p1 <= std_logic_vector(resize(signed(tmp_i1_fu_919_p3),32));
tmp_5_i_fu_402_p2 <= (isneg_fu_364_p3 xor ap_const_lv1_1);
tmp_6_fu_620_p3 <=
tmp_4_fu_610_p2 when (brmerge9_i_fu_579_p2(0) = '1') else
tmp_8_fu_615_p2;
tmp_6_i2_fu_961_p2 <= std_logic_vector(shift_left(unsigned(tmp_5_i1_fu_957_p1),to_integer(unsigned('0' & sh_assign_1_cast_i_fu_953_p1(31-1 downto 0)))));
tmp_6_i_fu_340_p3 <= (reg_312 & ap_const_lv11_0);
tmp_7_fu_826_p4 <= p_Val2_23_fu_794_p2(20 downto 19);
tmp_7_i1_fu_967_p2 <= std_logic_vector(shift_right(signed(tmp_i1_fu_919_p3),to_integer(unsigned('0' & sh_assign_1_cast6_i_fu_949_p1(28-1 downto 0)))));
tmp_7_i_fu_535_p2 <= (isneg_1_reg_1527 xor ap_const_lv1_1);
tmp_8_fu_615_p2 <= (underflow_1_fu_562_p2 or newsignbit_1_reg_1533);
tmp_8_i1_fu_1003_p2 <= std_logic_vector(signed(ap_const_lv9_1F7) - signed(tmp_19_cast_i_fu_985_p1));
tmp_8_i_fu_711_p2 <= (isneg_2_reg_1562 xor ap_const_lv1_1);
tmp_9_fu_775_p3 <=
p_Val2_21_mux_i_fu_761_p3 when (brmerge_i_fu_755_p2(0) = '1') else
p_Val2_i1_fu_768_p3;
tmp_i1_fu_919_p3 <= (tmp_10_fu_911_p3 & ap_const_lv14_0);
tmp_i2_15_fu_1217_p3 <= (phase_angle_V & ap_const_lv11_0);
tmp_i2_fu_585_p3 <= (tmp_3_reg_1516 & ap_const_lv1_1);
tmp_s_fu_463_p2 <= (underflow_reg_1509 or newsignbit_reg_1497);
underflow_1_fu_562_p2 <= (brmerge39_i_i_fu_556_p2 and isneg_1_reg_1527);
underflow_1_not_i_fu_573_p2 <= (underflow_1_fu_562_p2 xor ap_const_lv1_1);
underflow_2_fu_738_p2 <= (brmerge39_i_i1_fu_732_p2 and isneg_2_reg_1562);
underflow_3_fu_878_p2 <= (brmerge39_i_i_i_fu_872_p2 and isneg_3_fu_800_p3);
underflow_4_fu_1097_p2 <= (isneg_4_fu_1071_p3 and tmp_15_i_fu_1091_p2);
underflow_4_not_i_fu_888_p2 <= (underflow_3_reg_1613 xor ap_const_lv1_1);
underflow_fu_432_p2 <= (brmerge39_i1_i_fu_426_p2 and isneg_fu_364_p3);
underflow_not_i1_fu_749_p2 <= (underflow_2_fu_738_p2 xor ap_const_lv1_1);
underflow_not_i_fu_442_p2 <= (underflow_reg_1509 xor ap_const_lv1_1);
end behav;
| gpl-2.0 |
lepton-eda/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/spice_cs.vhdl | 15 | 406 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY SPICE_cs IS
GENERIC ( N : REAL := 10.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal llt : electrical;
terminal ult : electrical;
terminal lrt : electrical;
terminal urt : electrical );
END ENTITY SPICE_cs;
| gpl-2.0 |
elahejalalpour/CoDesign | Phase-1/hem/hem_tb.vhd | 1 | 2197 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:23:35 06/27/2015
-- Design Name:
-- Module Name: C:/projectxilinx/hem/multiplier/hem_tb.vhd
-- Project Name: multiplier
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: hem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hem_tb IS
END hem_tb;
ARCHITECTURE behavior OF hem_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hem
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
r : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal r : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hem PORT MAP (
a => a,
b => b,
r => r
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
a<="0111";
b<="1100";
wait for 10ns;
a<="0101";
b<="1101";
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 |
znuh/open-nexys | bscan_la/bscan_la.vhd | 1 | 4874 | ----------------------------------------------------------------------------------
-- la.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Logic Analyzer top level module. It connects the core with the hardware
-- dependend IO modules and defines all inputs and outputs that represent
-- phyisical pins of the fpga.
--
-- It defines two constants FREQ and RATE. The first is the clock frequency
-- used for receiver and transmitter for generating the proper baud rate.
-- The second defines the speed at which to operate the serial port.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bscan_la is
Port(
clock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
reset : in std_logic;
CAPTURE : in std_logic;
DRCK : in std_logic;
SEL : in std_logic;
SHIFT : in std_logic;
UPDATE : in std_logic;
TDO : out std_logic;
TDI : in std_logic
);
end bscan_la;
architecture Behavioral of bscan_la is
COMPONENT core
PORT(
clock : IN std_logic;
extReset : IN std_logic;
cmd : IN std_logic_vector(39 downto 0);
execute : IN std_logic;
input : IN std_logic_vector(31 downto 0);
inputClock : IN std_logic;
sampleReady50 : OUT std_logic;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : IN std_logic_vector(31 downto 0);
memoryOut : OUT std_logic_vector(31 downto 0);
memoryRead : OUT std_logic;
memoryWrite : OUT std_logic
);
END COMPONENT;
COMPONENT sram_bram
PORT(
clock : IN std_logic;
input : IN std_logic_vector(31 downto 0);
output : OUT std_logic_vector(31 downto 0);
read : IN std_logic;
write : IN std_logic
);
END COMPONENT;
component bscan_sreg is
GENERIC (
SREG_LEN : integer := 40
);
Port (
CAPTURE_i : in std_logic;
DRCK_i : in std_logic;
SEL_i : in std_logic;
SHIFT_i : in std_logic;
UPDATE_i : in std_logic;
TDI_i : in std_logic;
TDO_o: out std_logic;
clk_i : in std_logic;
Data_i : in std_logic_vector((SREG_LEN - 1) downto 0);
Data_o : out std_logic_vector((SREG_LEN - 1) downto 0);
strobe_o : out std_logic
);
end component;
signal cmd : std_logic_vector (39 downto 0);
signal memoryIn, memoryOut : std_logic_vector (31 downto 0);
signal output : std_logic_vector (31 downto 0);
signal read, write, execute, send, busy : std_logic;
signal din, dout : std_logic_vector(39 downto 0);
signal strobe : std_logic;
begin
-- JTAG
process(clock)
begin
if rising_edge(clock) then
execute <= '0';
-- update from jtag
if strobe = '1' then
busy <= '0';
cmd <= dout;
din(39) <= '0';
if dout(7 downto 0) = x"02" then
din <= x"80534c4131";
else
execute <= '1';
end if;
end if;
-- TODO: this isn't safe yet!
-- TODO: output -> din on strobe = '1'
if send = '1' then
busy <= '1';
din <= x"80" & output;
end if;
end if;
end process;
Inst_core: core PORT MAP(
clock => clock,
extReset => reset,
cmd => cmd,
execute => execute,
input => input,
inputClock => exClock,
--sampleReady50 => ready50,
output => output,
outputSend => send,
outputBusy => busy,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => read,
memoryWrite => write
);
bscan_sreg_inst : bscan_sreg
Port map (
CAPTURE_i => CAPTURE,
DRCK_i => DRCK,
SEL_i => SEL,
SHIFT_i => SHIFT,
UPDATE_i => UPDATE,
TDI_i => TDI,
TDO_o => TDO,
clk_i => clock,
Data_i => din,
Data_o => dout,
strobe_o => strobe
);
Inst_sram: sram_bram PORT MAP(
clock => clock,
input => memoryOut,
output => memoryIn,
read => read,
write => write
);
end Behavioral;
| gpl-2.0 |
znuh/open-nexys | bscan_la/sram_bram.vhd | 4 | 2555 | ----------------------------------------------------------------------------------
-- sram_bram.vhd
--
-- Copyright (C) 2007 Jonas Diemer
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Simple BlockRAM interface.
--
-- This module should be used instead of sram.vhd if no external SRAM is present.
-- Instead, it will use internal BlockRAM (16 Blocks).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_bram is
GENERIC
(
ADDRESS_WIDTH : integer := 13
);
Port (
clock : in STD_LOGIC;
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
read : in std_logic;
write : in std_logic
);
end sram_bram;
architecture Behavioral of sram_bram is
signal address : std_logic_vector (ADDRESS_WIDTH - 1 downto 0);
signal bramIn, bramOut : std_logic_vector (31 downto 0);
COMPONENT BRAM8k32bit--SampleRAM
PORT(
WE : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
ADDR : IN std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
DOUT : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic
);
END COMPONENT;
begin
-- assign signals
output <= bramOut;
-- memory io interface state controller
bramIn <= input;
-- memory address controller
process(clock)
begin
if rising_edge(clock) then
if write = '1' then
address <= address + 1;
elsif read = '1' then
address <= address - 1;
end if;
end if;
end process;
-- sample block ram
Inst_SampleRAM: BRAM8k32bit PORT MAP(
ADDR => address,
DIN => bramIn,
WE => write,
CLK => clock,
DOUT => bramOut
);
end Behavioral;
| gpl-2.0 |
6769/VHDL | Lab_5/Controller.vhd | 1 | 1090 | entity Controller is
port(
Rb,Reset, Eq,D7,D711,D2312,CLK:in bit;
State_debug:out integer range 0 to 3;
Sp,Roll,Win,Lose,Clear:out bit:='0');
end entity Controller;
architecture Behavior of Controller is
signal State,NextState:integer range 0 to 3:=0;
begin
State_debug<=State;
process(Rb,Reset,State)
begin
if( Rb='1' or Reset='1' ) then
--Roll<=Rb;
case State is
when 0 =>
if(D711='1')then Win<='1';NextState<=2;
elsif(D2312='1') then Lose<='1';NextState<=3;
else NextState<=1;Sp<='1';
end if;
when 2=>
if(Reset='1') then Win<='0';Lose<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 3=>
if(Reset='1') then Lose<='0';Win<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 1=>
if(Eq='1')then Win<='1' ;NextState<=2;
elsif(D7='1')then Lose<='1';NextState<=3;
end if;
end case;
end if;
end process;
Roll<=Rb;
Clear<='1' when Reset='1' and (State=2 or State=3) else '0';
process(CLK)
begin
if CLK'event and CLK = '1' then
State <= NextState;
end if;
end process;
end architecture Behavior;
| gpl-2.0 |
6769/VHDL | Lab_5/__FromSaru/lab50/control.vhd | 1 | 811 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end control;
architecture con of control is
signal count:std_logic_vector(3 downto 0):="0000";
signal w,l:bit;
begin
process(reset,rb)
begin
if reset='0' then
sp<='1';
count<="0000";
elsif rb'event and rb='1' then
count<=count+1;
elsif rb'event and rb='0' and count="0001" then
sp<='0';
end if;
roll<=not rb;
end process;
process(count,eq,d7,d711,d2312)
begin
--if w='0' and l='0' then
if count="0000" then
w <='0';l <='0';
elsif count="0001" then
w <=d711;l <=d2312;
else
w <=eq;l <=d7;
end if;
--end if;
end process;
win<=w;
lose<=l;
end con; | gpl-2.0 |
6769/VHDL | Lab_2_part2/simulation/qsim/work/cyclic_reg_with_clock_vlg_check_tst/_primary.vhd | 1 | 685 | library verilog;
use verilog.vl_types.all;
entity cyclic_reg_with_clock_vlg_check_tst is
port(
hex0 : in vl_logic_vector(7 downto 0);
hex1 : in vl_logic_vector(7 downto 0);
hex2 : in vl_logic_vector(7 downto 0);
hex3 : in vl_logic_vector(7 downto 0);
hex4 : in vl_logic_vector(7 downto 0);
hex5 : in vl_logic_vector(7 downto 0);
hex6 : in vl_logic_vector(7 downto 0);
hex7 : in vl_logic_vector(7 downto 0);
sampler_rx : in vl_logic
);
end cyclic_reg_with_clock_vlg_check_tst;
| gpl-2.0 |
zzhou007/161lab | newlab5/cpu_component_library.vhd | 1 | 3012 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package cpu_component_library is
component alu_control is
port (
alu_op : in std_logic_vector(1 downto 0);
instruction_5_0 : in std_logic_vector(5 downto 0);
alu_out : out std_logic_vector(3 downto 0)
);
end component;
component control_unit is
port (
instr_op : in std_logic_vector(5 downto 0);
reg_dst : out std_logic;
branch : out std_logic;
mem_read : out std_logic;
mem_to_reg : out std_logic;
alu_op : out std_logic_vector(1 downto 0);
mem_write : out std_logic;
alu_src : out std_logic;
reg_write : out std_logic
);
end component;
component generic_register is
generic (
SIZE : natural := 4
);
port (
clk : in std_logic;
rst : in std_logic;
write_en : in std_logic;
data_in : in std_logic_vector(SIZE-1 downto 0);
data_out : out std_logic_vector(SIZE-1 downto 0)
);
end component;
component mux_2_1 is
generic(
SIZE : natural := 4
);
port (
select_in : in std_logic;
data_0_in : in std_logic_vector(SIZE-1 downto 0);
data_1_in : in std_logic_vector(SIZE-1 downto 0);
data_out : out std_logic_vector(SIZE-1 downto 0)
);
end component;
component cpu_registers is
port (
clk : in std_logic;
rst : in std_logic;
reg_write : in std_logic;
read_register_1 : in std_logic_vector(4 downto 0);
read_register_2 : in std_logic_vector(4 downto 0);
write_register : in std_logic_vector(4 downto 0);
write_data : in std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0)
);
end component;
component alu is
port (
alu_control_in : in std_logic_vector(3 downto 0);
channel_a_in : in std_logic_vector(31 downto 0);
channel_b_in : in std_logic_vector(31 downto 0);
zero_out : out std_logic;
alu_result_out : out std_logic_vector(31 downto 0)
);
end component;
-- Instruction/Data memory Unit
component memory is
generic (
COE_FILE_NAME : string := "init.coe"
);
port (
clk : in std_logic;
rst : in std_logic;
instr_read_address : in std_logic_vector(7 downto 0);
instr_instruction : out std_logic_vector(31 downto 0);
data_mem_write : in std_logic;
data_address : in std_logic_vector(7 downto 0);
data_write_data : in std_logic_vector(31 downto 0);
data_read_data : out std_logic_vector(31 downto 0)
);
end component;
end cpu_component_library;
package body cpu_component_library is
end cpu_component_library;
| gpl-2.0 |
6769/VHDL | Lab_5/__FromTextBook/simulation/qsim/work/@game_vlg_sample_tst/_primary.vhd | 1 | 286 | library verilog;
use verilog.vl_types.all;
entity Game_vlg_sample_tst is
port(
Clk : in vl_logic;
Rb : in vl_logic;
Reset : in vl_logic;
sampler_tx : out vl_logic
);
end Game_vlg_sample_tst;
| gpl-2.0 |
6769/VHDL | Lab_1_partC/simulation/qsim/work/@input_@display_vlg_check_tst/_primary.vhd | 1 | 366 | library verilog;
use verilog.vl_types.all;
entity Input_Display_vlg_check_tst is
port(
adder1_hex_display: in vl_logic_vector(15 downto 0);
adder2_hex_display: in vl_logic_vector(15 downto 0);
sum : in vl_logic_vector(23 downto 0);
sampler_rx : in vl_logic
);
end Input_Display_vlg_check_tst;
| gpl-2.0 |
6769/VHDL | Lab_6/TheFinalCodeVersion/multiplexers.vhd | 2 | 1349 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity multiplexers is
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end entity multiplexers;
architecture choice of multiplexers is
signal mid_choice:std_logic_vector(N+2-1 downto 0);
begin
mid_choice<=control_reg&control_GDi;--0~7|G|Din--
-- out_to_bus<= DataIn when control_GDi(0)='1'
-- else reg_G when control_GDi(1)='1'
-- else reg0 when control_reg(0)='1'
-- else reg1 when control_reg(1)='1'
-- ;--else (others=>'Z');
process(mid_choice,reg0,reg1,reg_G,DataIn)
begin
case mid_choice is
when "1000"=>
out_to_bus<=reg0;
when "0100"=>
out_to_bus<=reg1;
when "0010"=>
out_to_bus<=reg_G;
when others=>
--when "0001"=>
out_to_bus<=DataIn;
--when others=>
end case;
end process;
end architecture choice;
| gpl-2.0 |
zzhou007/161lab | lab6/CAM_Array.vhd | 1 | 1387 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CAM_Array is
Generic (CAM_WIDTH : integer := 8 ;
CAM_DEPTH : integer := 4 ) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we_decoded_row_address : in STD_LOGIC_VECTOR(CAM_DEPTH-1 downto 0) ;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
decoded_match_address : out STD_LOGIC_VECTOR (CAM_DEPTH-1 downto 0));
end CAM_Array;
architecture Behavioral of CAM_Array is
component CAM_Row is
Generic (CAM_WIDTH : integer := 8) ;
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
search_word : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
dont_care_mask : in STD_LOGIC_VECTOR (CAM_WIDTH-1 downto 0);
row_match : out STD_LOGIC);
end component ;
begin
GEN_REG:
for i in 0 to (CAM_DEPTH-1) generate
cam_array : cam_row
generic map
(
CAM_WIDTH => CAM_WIDTH
)
port map
(
clk => clk,
rst => rst,
we => we_decoded_row_address(i),
search_word => search_word,
dont_care_mask => dont_care_mask,
row_match => decoded_match_address(i)
);
end generate GEN_REG;
end Behavioral;
| gpl-2.0 |
6769/VHDL | Lab_2_part2/clock/simulation/qsim/work/counter741_vlg_check_tst/_primary.vhd | 1 | 272 | library verilog;
use verilog.vl_types.all;
entity counter741_vlg_check_tst is
port(
Qout : in vl_logic_vector(7 downto 0);
second : in vl_logic;
sampler_rx : in vl_logic
);
end counter741_vlg_check_tst;
| gpl-2.0 |
6769/VHDL | Lab_3/Part2/View_input.vhd | 3 | 750 | entity View_input is
port (reset:in bit;
w: in bit;
clk:in bit;
z: out bit;
state8_0:out bit_vector(8 downto 0));--LED Red for showing State table
end entity View_input;
architecture match of View_input is
component FSM_core
port(
X: in bit;
CLK: in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z: out bit);
end component;
signal stateout:integer range 0 to 8;
begin
lable_1:fsm_core port map(w,clk,reset,stateout,z);
with stateout select --mux choice
state8_0 <= "000000001" when 0,
"000000010" when 1,
"000000100" when 2,
"000001000" when 3,
"000010000" when 4,
"000100000" when 5,
"001000000" when 6,
"010000000" when 7,
"100000000" when 8;
end architecture match;
| gpl-2.0 |
6769/VHDL | Lab_2_part1/T_flip_flop.vhd | 1 | 335 | entity T_flip_flop is
port(T,clk,clear:in bit;
Q,QN:buffer bit
);
end T_flip_flop;
architecture internal of T_flip_flop is
begin
QN<=not Q;
process(clk,clear)
begin
if(clear='0') then Q<='0';
elsif(clk'event and clk='1') then
if T='1' then Q<= QN;
end if;
end if ;
end process;
end architecture internal; | gpl-2.0 |
zzhou007/161lab | lab6/tb.vhd | 1 | 2822 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY system_tb IS
END system_tb;
ARCHITECTURE behavior OF system_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CAM_Wrapper
GENERIC
(
CAM_WIDTH : integer := 4 ;
CAM_DEPTH : integer := 4
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
we_decoded_row_address: IN std_logic_vector(3 downto 0);
search_word : IN std_logic_vector(3 downto 0);
dont_care_mask : IN std_logic_vector(3 downto 0);
decoded_match_address : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal we_decoded_row_address : std_logic_vector(3 downto 0) := (others => '0');
signal search_word : std_logic_vector(3 downto 0) := (others => '0');
signal dont_care_mask : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal decoded_match_address : std_logic_vector(3 downto 0);
-- Temps for verification
signal temp_addr : std_logic_vector(3 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CAM_Wrapper GENERIC MAP
(
CAM_WIDTH => 4,
CAM_DEPTH => 4
)
PORT MAP
(
clk => clk,
rst => rst,
we_decoded_row_address => we_decoded_row_address,
search_word => search_word,
dont_care_mask => dont_care_mask,
decoded_match_address => decoded_match_address
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for clk_period/2;
rst <= '1';
wait for clk_period*2;
rst <= '0';
-- insert stimulus here
for i in 3 downto 0 loop
we_decoded_row_address <= (OTHERS => '0');
we_decoded_row_address(i) <= '1';
search_word <= conv_std_logic_vector((i+1)*2, 4);
wait for clk_period;
end loop;
we_decoded_row_address <= (OTHERS => '0');
wait for clk_period;
for i in 8 downto 1 loop
search_word <= conv_std_logic_vector(i, 4);
wait for clk_period;
temp_addr <= (others => '0');
if( i mod(2) = 0 ) then
temp_addr( (i/2) - 1) <= '1';
end if;
wait for 10 ns;
assert temp_addr = decoded_match_address report "Case did not match, you have a bug in your code" severity Warning;
end loop;
wait;
end process;
END; | gpl-2.0 |
sorgelig/SAMCoupe_MIST | sid/mult_acc.vhd | 6 | 7965 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity mult_acc is
port (
clock : in std_logic;
reset : in std_logic;
voice_i : in unsigned(3 downto 0);
enable_i : in std_logic;
voice3_off_l : in std_logic;
voice3_off_r : in std_logic;
filter_en : in std_logic := '0';
enveloppe : in unsigned(7 downto 0);
waveform : in unsigned(11 downto 0);
--
osc3 : out std_logic_vector(7 downto 0);
env3 : out std_logic_vector(7 downto 0);
--
valid_out : out std_logic;
direct_out_L : out signed(17 downto 0);
direct_out_R : out signed(17 downto 0);
filter_out_L : out signed(17 downto 0);
filter_out_R : out signed(17 downto 0) );
end mult_acc;
-- architecture unsigned_wave of mult_acc is
-- signal filter_m : std_logic;
-- signal voice_m : unsigned(3 downto 0);
-- signal mult_m : unsigned(19 downto 0);
-- signal accu_f : unsigned(17 downto 0);
-- signal accu_u : unsigned(17 downto 0);
-- signal enable_d : std_logic;
-- signal direct_i : unsigned(17 downto 0);
-- signal filter_i : unsigned(17 downto 0);
-- begin
-- process(clock)
-- variable mult_ext : unsigned(21 downto 0);
-- variable mult_trunc : unsigned(21 downto 4);
-- begin
-- if rising_edge(clock) then
-- -- latch outputs
-- if reset='1' then
-- osc3 <= (others => '0');
-- env3 <= (others => '0');
-- elsif voice_i = X"2" then
-- osc3 <= std_logic_vector(waveform(11 downto 4));
-- env3 <= std_logic_vector(enveloppe);
-- end if;
--
-- mult_ext := extend(mult_m, mult_ext'length);
-- mult_trunc := mult_ext(mult_trunc'range);
-- filter_m <= filter_en;
-- voice_m <= voice_i;
-- mult_m <= enveloppe * waveform;
-- valid_out <= '0';
-- enable_d <= enable_i;
--
-- if enable_d='1' then
-- if voice_m = 0 then
-- valid_out <= '1';
-- direct_i <= accu_u;
-- filter_i <= accu_f;
-- if filter_m='1' then
-- accu_f <= mult_trunc;
-- accu_u <= (others => '0');
-- else
-- accu_f <= (others => '0');
-- accu_u <= mult_trunc;
-- end if;
-- else
-- valid_out <= '0';
-- if filter_m='1' then
-- accu_f <= sum_limit(accu_f, mult_trunc);
-- else
-- if (voice_m /= 2) or (voice3_off = '0') then
-- accu_u <= sum_limit(accu_u, mult_trunc);
-- end if;
-- end if;
-- end if;
-- end if;
--
-- if reset = '1' then
-- valid_out <= '0';
-- accu_u <= (others => '0');
-- accu_f <= (others => '0');
-- direct_i <= (others => '0');
-- filter_i <= (others => '0');
-- end if;
-- end if;
-- end process;
--
-- direct_out <= '0' & signed(direct_i(17 downto 1));
-- filter_out <= '0' & signed(filter_i(17 downto 1));
-- end unsigned_wave;
--
architecture signed_wave of mult_acc is
signal filter_m : std_logic;
signal voice_m : unsigned(3 downto 0);
signal mult_m : signed(20 downto 0);
signal accu_fl : signed(17 downto 0);
signal accu_fr : signed(17 downto 0);
signal accu_ul : signed(17 downto 0);
signal accu_ur : signed(17 downto 0);
signal enable_d : std_logic;
begin
process(clock)
variable mult_ext : signed(21 downto 0);
variable mult_trunc : signed(21 downto 4);
variable env_signed : signed(8 downto 0);
variable wave_signed: signed(11 downto 0);
begin
if rising_edge(clock) then
-- latch outputs
if reset='1' then
osc3 <= (others => '0');
env3 <= (others => '0');
elsif voice_i = X"2" then
osc3 <= std_logic_vector(waveform(11 downto 4));
env3 <= std_logic_vector(enveloppe);
end if;
env_signed := '0' & signed(enveloppe);
wave_signed := not waveform(11) & signed(waveform(10 downto 0));
mult_ext := extend(mult_m, mult_ext'length);
mult_trunc := mult_ext(mult_trunc'range);
filter_m <= filter_en;
voice_m <= voice_i;
mult_m <= env_signed * wave_signed;
valid_out <= '0';
enable_d <= enable_i;
if enable_d='1' then
if voice_m = 0 then
valid_out <= '1';
direct_out_l <= accu_ul;
direct_out_r <= accu_ur;
filter_out_l <= accu_fl;
filter_out_r <= accu_fr;
accu_fr <= (others => '0');
accu_ur <= (others => '0');
if filter_m='1' then
accu_fl <= mult_trunc;
accu_ul <= (others => '0');
else
accu_fl <= (others => '0');
accu_ul <= mult_trunc;
end if;
elsif voice_m(3)='0' then
valid_out <= '0';
if filter_m='1' then
accu_fl <= sum_limit(accu_fl, mult_trunc);
else
if (voice_m /= 2) or (voice3_off_l = '0') then
accu_ul <= sum_limit(accu_ul, mult_trunc);
end if;
end if;
else -- upper 8 voices go to right
valid_out <= '0';
if filter_m='1' then
accu_fr <= sum_limit(accu_fr, mult_trunc);
else
if (voice_m /= 10) or (voice3_off_r = '0') then
accu_ur <= sum_limit(accu_ur, mult_trunc);
end if;
end if;
end if;
end if;
if reset = '1' then
valid_out <= '0';
accu_ul <= (others => '0');
accu_fl <= (others => '0');
accu_ur <= (others => '0');
accu_fr <= (others => '0');
direct_out_l <= (others => '0');
direct_out_r <= (others => '0');
filter_out_l <= (others => '0');
filter_out_r <= (others => '0');
end if;
end if;
end process;
end signed_wave;
| gpl-2.0 |
6769/VHDL | Lab_5/__FromSaru/lab50/lab50.vhd | 1 | 1971 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab50 is
port(reset,rb,clk_50m,clk_28m:in bit;
win,lose:out bit;
led1,led2:out bit_vector(7 downto 0));
end lab50;
architecture allmap of lab50 is
component counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end component;
component decoder_1_6 IS
PORT(m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
end component;
component adder is
port(addend1,addend2:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0));
end component;
component point_register is
port(sp:in bit;
point:out std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0));
end component;
component comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end component;
component test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end component;
component control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end component;
signal roll,eq,d7,d711,d2312,sp:bit;
signal count1,count2,sum,point:std_logic_vector(3 downto 0);
begin
decoder1:decoder_1_6 port map(m=>count1,led_vector=>led1);
decoder2:decoder_1_6 port map(m=>count2,led_vector=>led2);
counter1:counter_1_6 port map(clk_50m=>clk_50m,roll=>roll,out_count=>count1);
counter2:counter_1_6 port map(clk_50m=>clk_28m,roll=>roll,out_count=>count2);
add:adder port map(addend1=>count1,addend2=>count2,sum=>sum);
pr:point_register port map(sp=>sp,point=>point,sum=>sum);
compare:comparator port map(point=>point,sum=>sum,eq=>eq);
test:test_logic port map(sum=>sum,d7=>d7,d711=>d711,d2312=>d2312);
con:control port map(reset=>reset,rb=>rb,
eq=>eq,d7=>d7,d711=>d711,d2312=>d2312,
roll=>roll,win=>win,lose=>lose,sp=>sp);
end allmap; | gpl-2.0 |
6769/VHDL | Lab_5/Modelsim/clock_signal_per_second.vhd | 1 | 645 | library ieee;
use ieee.numeric_bit.all;
entity clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end entity clock_signal_per_second;
architecture behavior of clock_signal_per_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
constant Terminator:integer:=25000;--25*1000*1000
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal<Terminator then counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second_output<=not second_output;
end if;
end process;
end architecture behavior; | gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/voltage_source.vhdl | 15 | 415 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY VOLTAGE_SOURCE IS
GENERIC ( amplitude : REAL := 2.0;
offset : REAL := 1.2;
width : REAL := 0.002;
period : REAL := 0.005;
k : REAL := 100.0 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY VOLTAGE_SOURCE;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/voltage_dependend_capacitor_arc.vhdl | 15 | 362 | ARCHITECTURE spice_beh OF voltage_dependend_capacitor IS
QUANTITY v ACROSS i THROUGH lt TO rt;
QUANTITY c : real;
BEGIN
-- c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (always_positive(1.0 - v/PB))**(-M);
c == ((TT * ISS)/(N * VT)) * exp(v/(N*VT)) + CJ0 * (1.0 - v/PB)**(-M);
v'dot == i / always_positive(c);
END ARCHITECTURE spice_beh;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/spice_cs_arc.vhdl | 15 | 244 | ARCHITECTURE current_controlled OF spice_cs IS
QUANTITY v ACROSS i THROUGH urt TO lrt;
QUANTITY vc ACROSS ic THROUGH ult TO llt;
BEGIN
vc == 0.0;
i == N * ic;
-- i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE current_controlled;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc177.vhd | 4 | 1782 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc177.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n02i00177ent IS
END c04s03b03x01p03n02i00177ent;
ARCHITECTURE c04s03b03x01p03n02i00177arch OF c04s03b03x01p03n02i00177ent IS
type array1 is array (positive range <>, natural range <>) of integer;
signal c1 : array1(1 to 8, 0 to 7);
alias one_bit : array1 is c1; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert FALSE
report "***FAILED TEST: c04s03b03x01p03n02i00177 - Multi-dimensional arrays not allowed in alias declarations."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n02i00177arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1455.vhd | 4 | 1703 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1455.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01455ent IS
END c08s07b00x00p01n01i01455ent;
ARCHITECTURE c08s07b00x00p01n01i01455arch OF c08s07b00x00p01n01i01455ent IS
begin
TESTING: process
variable i1, i2 : integer := 0;
begin
if 1 then -- failure_here condition not boolean.
i1 := 1;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p01n01i01455 - Expression of IF statement is not of type BOOLEAN"
severity ERROR;
wait;
end process TESTING;
END c08s07b00x00p01n01i01455arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd | 4 | 1730 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library device_lib;
configuration last_pass_spice of carry_chain is
for device_level
for bit_array ( 0 to n - 1 )
for bit_0
for all : nmos
use entity device_lib.nmos(ideal);
end for;
for all : pmos
use entity device_lib.pmos(ideal);
end for;
end for;
for middle_bit
for all : nmos
use entity device_lib.nmos(ideal);
end for;
for all : pmos
use entity device_lib.pmos(ideal);
end for;
end for;
end for;
for bit_array ( n )
for bit_n
for p_pass : nmos
use entity device_lib.nmos(spice_equivalent);
end for;
for others : nmos
use entity device_lib.nmos(ideal);
end for;
for all : pmos
use entity device_lib.pmos(ideal);
end for;
end for;
end for;
end for;
end configuration last_pass_spice;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/cmp_800.vhd | 2 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_800 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_800;
architecture augh of cmp_800 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc999.vhd | 4 | 1824 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc999.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i00999pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i00999pkg;
use work.c06s03b00x00p09n01i00999pkg.all;
ENTITY c06s03b00x00p09n01i00999ent IS
END c06s03b00x00p09n01i00999ent;
ARCHITECTURE c06s03b00x00p09n01i00999arch OF c06s03b00x00p09n01i00999ent IS
BEGIN
TESTING: PROCESS
subtype ST3 is c06s03b00x00p09n01i00999pkg.c06s03b00x00p09n01i00999ent.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i00999 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i00999arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd | 4 | 3149 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc415.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00415ent IS
END c03s02b01x01p19n01i00415ent;
ARCHITECTURE c03s02b01x01p19n01i00415arch OF c03s02b01x01p19n01i00415ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
constant C1 : boolean_cons_vector := (others => true);
function complex_scalar(s : boolean_cons_vector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_cons_vector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_cons_vector;
signal S2 : boolean_cons_vector;
signal S3 : boolean_cons_vector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00415"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00415 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00415arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket14/test_case.vhd | 3 | 821 | library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity scrambler is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
port (
clk, en, reset, seed : in std_logic;
d_in : in std_logic;
d_out : out std_logic);
end entity scrambler;
architecture behavioural of scrambler is
type test_array_type is array (ARRAY_WIDTH-1 downto 0) of
std_logic_vector (BUS_WIDTH-1 downto 0);
signal test_array : test_array_type := (others => (others => '0'));
signal test_vec : std_logic_vector (BUS_WIDTH-1 downto 0)
:= (others => '0');
begin
failing_process : process (clk) begin
if clk'event and clk = '1' then
test_array <= test_array (ARRAY_WIDTH-2 downto 0) & test_vec;
end if;
end process failing_process;
end architecture behavioural;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug0100/nochoice2.vhdl | 1 | 179 | entity nochoice2 is
end;
architecture behav of nochoice2 is
constant n : string (1 to 2) := "ab";
begin
process
begin
case n is
end case;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1253/repro1.vhdl | 1 | 506 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity repro1 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end repro1;
architecture archi of repro1 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= std_logic_vector'(1 + signed(tmp));
end if;
end process;
Q <= tmp;
end archi;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug096/reader.vhdl | 1 | 266 | entity reader is
end reader;
use std.textio.all;
architecture behav of reader is
begin
process
file f : text is in "input.txt";
variable l : line;
begin
for i in 1 to 5 loop
readline (f, l);
end loop;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2544.vhd | 4 | 1998 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2544.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p14n01i02544ent IS
END c07s03b05x00p14n01i02544ent;
ARCHITECTURE c07s03b05x00p14n01i02544arch OF c07s03b05x00p14n01i02544ent IS
BEGIN
TESTING: PROCESS
type X1 is range 1.0 to 100.0 ;
type X2 is range 1.0 to 100.0 ;
type I1 is range 1 to 1000000;
type I2 is range 1 to 10000000 ;
variable RE1 : X1 ;
variable RE2 : X2 ;
variable IN1 : I1 ;
variable IN2 : I2 ;
BEGIN
IN2 := IN2 - IN1; -- Failure_here
-- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
-- UNIVERSAL INTEGER OR UNIVERSAL REAL.
assert FALSE
report "***FAILED TEST: c07s03b05x00p14n01i02544 - Type conversion can only occur on operand of universal real or integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p14n01i02544arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd | 4 | 3290 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1907.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p11n01i01907ent IS
END c07s01b00x00p11n01i01907ent;
ARCHITECTURE c07s01b00x00p11n01i01907arch OF c07s01b00x00p11n01i01907ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable b1a, b2a, b3a, b4a : BOOLEAN;
variable b1o, b2o, b3o, b4o : BOOLEAN;
variable b1x, b2x, b3x, b4x : BOOLEAN;
BEGIN
-- Test that the following operators can be used associatively.
-- 1. AND.
b1a := TRUE;
b2a := TRUE;
b3a := FALSE;
assert (NOT (b1a AND b2a AND b3a))
report "AND operator cannot be used associatively.";
b4a := TRUE;
assert (b1a AND b2a AND b4a)
report "AND operator cannot be used associatively.";
-- 2. OR.
b1o := FALSE;
b2o := FALSE;
b3o := TRUE;
assert (b1o OR b2o OR b3o)
report "OR operator cannot be used associatively.";
b4o := FALSE;
assert (NOT (b1o OR b2o OR b4o))
report "OR operator cannot be used associatively.";
-- 3. XOR.
b1x := TRUE;
b2x := TRUE;
b3x := FALSE;
assert (NOT (b1x XOR b2x XOR b3x))
report "XOR operator cannot be used associatively.";
b4x := TRUE;
assert (b1x XOR b2x XOR b4x)
report "XOR operator cannot be used associatively.";
wait for 5 ns;
assert NOT( (NOT (b1a AND b2a AND b3a)) and
(b1a AND b2a AND b4a) and
(b1o OR b2o OR b3o) and
(NOT (b1o OR b2o OR b4o)) and
(NOT (b1x XOR b2x XOR b3x)) and
(b1x XOR b2x XOR b4x) )
report "***PASSED TEST: /src/ch07/sc01/p012/s010101.vhd"
severity NOTE;
assert ( (NOT (b1a AND b2a AND b3a)) and
(b1a AND b2a AND b4a) and
(b1o OR b2o OR b3o) and
(NOT (b1o OR b2o OR b4o)) and
(NOT (b1x XOR b2x XOR b3x)) and
(b1x XOR b2x XOR b4x) )
report "***FAILED TEST: c07s01b00x00p11n01i01907 - Associative test for and or and xor failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p11n01i01907arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd | 4 | 2142 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
begin
process_3_a : process is
-- code from book:
subtype pixel_row is bit_vector (0 to 15);
variable current_row, mask : pixel_row;
-- end of code from book
begin
current_row := "0000000011111111";
mask := "0000111111110000";
-- code from book:
current_row := current_row and not mask;
current_row := current_row xor X"FFFF";
-- end of code from book
-- code from book (conditions only):
assert B"10001010" sll 3 = B"01010000";
assert B"10001010" sll -2 = B"00100010";
assert B"10010111" srl 2 = B"00100101";
assert B"10010111" srl -6 = B"11000000";
assert B"01001011" sra 3 = B"00001001";
assert B"10010111" sra 3 = B"11110010";
assert B"00001100" sla 2 = B"00110000";
assert B"00010001" sla 2 = B"01000111";
assert B"00010001" sra -2 = B"01000111";
assert B"00110000" sla -2 = B"00001100";
assert B"10010011" rol 1 = B"00100111";
assert B"10010011" ror 1 = B"11001001";
assert "abc" & 'd' = "abcd";
assert 'w' & "xyz" = "wxyz";
assert 'a' & 'b' = "ab";
-- end of code from book
wait;
end process process_3_a;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd | 4 | 2669 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01073ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
SUBTYPE A8 IS A (1 TO 8);
SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
ELSE
IF (a=3) THEN
RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
ELSE
RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
END IF;
END IF;
END;
END c06s04b00x00p03n01i01073ent;
ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,0)(1,1,1);
q(2) := func1(0,3)(2,2,2);
q(3) := func1(0,0)(3,3,3);
q(4) := func1(4,4,4); -- Indexed name - function params defaulted
q(5) := func1(5,5,5);
q(6) := func1(6,6,6);
q(7) := func1(3,3,3);
q(8) := func1(1,1,1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***PASSED TEST: c06s04b00x00p03n01i01073"
severity NOTE;
assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01073arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2895.vhd | 4 | 1775 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2895.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p05n02i02895ent IS
END c02s01b01x00p05n02i02895ent;
ARCHITECTURE c02s01b01x00p05n02i02895arch OF c02s01b01x00p05n02i02895ent IS
function exp_type_check (variable c1: in integer) return integer is
-- Failure_here
begin
null;
end exp_type_check;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p05n02i02895 - The object class for formal parameters of a function cannot be of object class variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p05n02i02895arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/mul_556.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_556 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_556;
architecture augh of mul_556 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue610/repro3.vhdl | 1 | 290 | entity repro3 is
end repro3;
architecture behav of repro3 is
procedure set (v : out string) is
begin
v := (others => ' ');
end set;
begin
process
variable s : string (1 to 4);
begin
set (s);
assert s = " " severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd | 4 | 4493 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_17_fg_17_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package body bounded_buffer_adt is
function new_bounded_buffer ( size : in positive ) return bounded_buffer is
begin
return new bounded_buffer_object'(
byte_count => 0, head_index => 0, tail_index => 0,
store => new store_array(0 to size - 1) );
end function new_bounded_buffer;
procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
is_empty : out boolean ) is
begin
is_empty := the_bounded_buffer.byte_count = 0;
end procedure test_empty;
procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
is_full : out boolean ) is
begin
is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
end procedure test_full;
procedure write ( the_bounded_buffer : inout bounded_buffer; data : in byte ) is
variable buffer_full : boolean;
begin
test_full(the_bounded_buffer, buffer_full);
if buffer_full then
report "write to full bounded buffer" severity failure;
else
the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
mod the_bounded_buffer.store'length;
the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
end if;
end procedure write;
procedure read ( the_bounded_buffer : inout bounded_buffer; data : out byte ) is
variable buffer_empty : boolean;
begin
test_empty(the_bounded_buffer, buffer_empty);
if buffer_empty then
report "read from empty bounded buffer" severity failure;
else
data := the_bounded_buffer.store(the_bounded_buffer.head_index);
the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
mod the_bounded_buffer.store'length;
the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
end if;
end procedure read;
end package body bounded_buffer_adt;
-- not in book
entity fg_17_11 is
end entity fg_17_11;
architecture test of fg_17_11 is
begin
process is
use work.bounded_buffer_adt.all;
variable buf : bounded_buffer := new_bounded_buffer(4);
variable empty, full : boolean;
variable d : byte;
begin
test_empty(buf, empty);
assert empty;
test_full(buf, full);
assert not full;
write(buf, X"01");
write(buf, X"02");
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert not full;
write(buf, X"03");
write(buf, X"04");
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert full;
write(buf, X"05");
read(buf, d);
read(buf, d);
test_empty(buf, empty);
assert not empty;
test_full(buf, full);
assert not full;
read(buf, d);
read(buf, d);
test_empty(buf, empty);
assert empty;
test_full(buf, full);
assert not full;
read(buf, d);
write(buf, X"06");
write(buf, X"07");
write(buf, X"08");
read(buf, d);
read(buf, d);
write(buf, X"09");
read(buf, d);
write(buf, X"0A");
read(buf, d);
write(buf, X"0B");
read(buf, d);
write(buf, X"0C");
read(buf, d);
write(buf, X"0D");
read(buf, d);
write(buf, X"0E");
read(buf, d);
write(buf, X"0F");
read(buf, d);
wait;
end process;
end architecture test;
-- end not in book
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue243/test.vhdl | 2 | 469 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_pkg IS
SUBTYPE test_t IS std_ulogic_vector(7 DOWNTO 0);
TYPE test_array_t IS ARRAY (natural RANGE <>) OF test_t;
END PACKAGE test_pkg;
LIBRARY work;
USE work.test_pkg.ALL;
ENTITY test IS
PORT (
a : IN test_array_t(0 TO 4) := (OTHERS => (OTHERS => '0'));
b : IN test_array_t(0 TO 4) := ((OTHERS => (OTHERS => '0'))));
END ENTITY test;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1564.vhd | 4 | 1612 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1564.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01564ent IS
END c08s10b00x00p03n01i01564ent;
ARCHITECTURE c08s10b00x00p03n01i01564arch OF c08s10b00x00p03n01i01564ent IS
BEGIN
TESTING: PROCESS
BEGIN
for i in 1 to 10 loop
end loop;
next;
assert FALSE
report "***FAILED TEST: c08s10b00x00p03n01i01564 - A NEXT statement must be inside a loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01564arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/uassoc01/uassoc02.vhdl | 1 | 821 | library ieee;
use ieee.std_logic_1164.all;
entity uassoc02_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end uassoc02_sub;
architecture behav of uassoc02_sub is
begin
o <= not i;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity uassoc02 is
port (i1 : std_logic_vector(3 downto 0);
i2 : std_logic_vector(7 downto 0);
o : out std_logic_vector(3 downto 0));
end uassoc02;
architecture rtl of uassoc02 is
component uassoc02_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end component;
signal o1: std_logic_vector(3 downto 0);
signal o2: std_logic_vector(7 downto 0);
begin
dut1: uassoc02_sub
port map (i => i1, o => o1);
dut2: uassoc02_sub
port map (i => i2, o => o2);
o <= o1 xor o2 (3 downto 0);
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd | 4 | 4306 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_verify of mac_test is
signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
behavioral_s_real, behavioral_s_imag,
rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut_behavioral : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
behavioral_s_real, behavioral_s_imag, behavioral_ovf );
dut_rtl : entity work.mac(rtl)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag,
rtl_s_real, rtl_s_imag, rtl_ovf );
behavioral_s_real_converter :
entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
behavioral_s_imag_converter :
entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
rtl_s_real_converter :
entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
rtl_s_imag_converter :
entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
verifier : process
constant epsilon : real := 4.0E-5; -- 1-bit error in 15-bit mantissa
begin
wait until clk = '0';
assert behavioral_ovf = rtl_ovf
report "Overflow flags differ" severity error;
if behavioral_ovf = '0' and rtl_ovf = '0' then
assert abs (behavioral_s.re - rtl_s.re) < epsilon
report "Real sums differ" severity error;
assert abs (behavioral_s.im - rtl_s.im) < epsilon
report "Imag sums differ" severity error;
end if;
end process verifier;
end architecture bench_verify;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd | 4 | 1965 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc884.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s01b00x00p09n01i00884ent IS
END c10s01b00x00p09n01i00884ent;
ARCHITECTURE c10s01b00x00p09n01i00884arch OF c10s01b00x00p09n01i00884ent IS
constant GS1: INTEGER := 105;
constant GS2: INTEGER := 785;
signal PS1: INTEGER := 356;
signal PS2: INTEGER := 123;
BEGIN
TESTING: PROCESS
constant GS1: INTEGER := 3;
constant GS2: INTEGER := 9;
BEGIN
PS1 <= GS1 + 1;
PS2 <= GS2 + 2;
wait on PS1, PS2;
assert NOT( PS1=4 and PS2=11 )
report "***PASSED TEST: c10s01b00x00p09n01i00884"
severity NOTE;
assert ( PS1=4 and PS2=11 )
report "***FAILED TEST: c10s01b00x00p09n01i00884 - A declaration region is formed by the text of a process statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p09n01i00884arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd | 4 | 3023 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3032.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03032ent IS
END c12s02b01x00p01n02i03032ent;
ARCHITECTURE c12s02b01x00p01n02i03032arch OF c12s02b01x00p01n02i03032ent IS
subtype subi is integer range 1 to 10;
subtype subr is real range 1.0 to 10.0;
subtype subb is bit range '1' to '1';
type c_a is array(integer range <>) of subi;
signal s1, s2, s3 : c_a(1 to 3);
BEGIN
-- test array generics
bl1: block
generic(gi : c_a(1 to 3));
generic map (gi => (1,1,1));
port (s11 : OUT c_a(1 to 3));
port map (s11 => s1);
begin
assert ((gi(1)=1) and (gi(2)=1) and (gi(3)=1))
report "Generic array GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic(gi : c_a(1 to 3));
generic map (gi => (5,5,5));
port (s22 : OUT c_a(1 to 3));
port map (s22 => s2);
begin
assert ((gi(1)=5) and (gi(2)=5) and (gi(3)=5))
report "Generic array GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic(gi : c_a(1 to 3));
generic map (gi => (10,10,10));
port (s33 : OUT c_a(1 to 3));
port map (s33 => s3);
begin
assert ((gi(1)=10) and (gi(2)=10) and (gi(3)=10))
report "Generic array GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
report "***PASSED TEST: c12s02b01x00p01n02i03032"
severity NOTE;
assert ( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
report "***FAILED TEST: c12s02b01x00p01n02i03032 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03032arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd | 4 | 16578 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1948.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01948pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01948pkg.all;
ENTITY c07s02b01x00p01n02i01948ent IS
END c07s02b01x00p01n02i01948ent;
ARCHITECTURE c07s02b01x00p01n02i01948arch OF c07s02b01x00p01n02i01948ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT NOR_C_csa1_1 : t_csa1_1 := ( '0', '0', '0', '1' );
CONSTANT NOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NOR_C_csa1_2 : t_csa1_2 := ( FALSE, FALSE, FALSE, TRUE );
CONSTANT NOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE, TRUE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT NOR_C_csa1_3 : t_csa1_3 := ( '0', '0', '0', '1' );
CONSTANT NOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT NOR_C_csa1_4 : t_csa1_4 := ( FALSE, FALSE, FALSE, TRUE );
CONSTANT NOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE, TRUE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL NOR_S_csa1_1 : t_csa1_1 := ( '0', '0', '0', '1' );
SIGNAL NOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NOR_S_csa1_2 : t_csa1_2 := ( FALSE, FALSE, FALSE, TRUE );
SIGNAL NOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE, TRUE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL NOR_S_csa1_3 : t_csa1_3 := ( '0', '0', '0', '1' );
SIGNAL NOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL NOR_S_csa1_4 : t_csa1_4 := ( FALSE, FALSE, FALSE, TRUE );
SIGNAL NOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE, TRUE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE NOR_V_csa1_1 : t_csa1_1 := ( '0', '0', '0', '1' );
VARIABLE NOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NOR_V_csa1_2 : t_csa1_2 := ( FALSE, FALSE, FALSE, TRUE );
VARIABLE NOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE, TRUE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE NOR_V_csa1_3 : t_csa1_3 := ( '0', '0', '0', '1' );
VARIABLE NOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE NOR_V_csa1_4 : t_csa1_4 := ( FALSE, FALSE, FALSE, TRUE );
VARIABLE NOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE, TRUE );
BEGIN
--
-- Test NOR operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 NOR ARGB_C_csa1_1 ) = NOR_C_csa1_1
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 NOR ARGB_C_csa1_2 ) = NOR_C_csa1_2
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 NOR ARGB_C_csa1_3 ) = NOR_C_csa1_3
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 NOR ARGB_C_csa1_4 ) = NOR_C_csa1_4
REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 NOR ARGB_C_usa1_1 ) = NOR_C_usa1_1
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 NOR ARGB_C_usa1_2 ) = NOR_C_usa1_2
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 NOR ARGB_C_usa1_3 ) = NOR_C_usa1_3
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 NOR ARGB_C_usa1_4 ) = NOR_C_usa1_4
REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test NOR operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 NOR ARGB_S_csa1_1 ) = NOR_S_csa1_1
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 NOR ARGB_S_csa1_2 ) = NOR_S_csa1_2
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 NOR ARGB_S_csa1_3 ) = NOR_S_csa1_3
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 NOR ARGB_S_csa1_4 ) = NOR_S_csa1_4
REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 NOR ARGB_S_usa1_1 ) = NOR_S_usa1_1
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 NOR ARGB_S_usa1_2 ) = NOR_S_usa1_2
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 NOR ARGB_S_usa1_3 ) = NOR_S_usa1_3
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 NOR ARGB_S_usa1_4 ) = NOR_S_usa1_4
REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test NOR operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 NOR ARGB_V_csa1_1 ) = NOR_V_csa1_1
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 NOR ARGB_V_csa1_2 ) = NOR_V_csa1_2
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 NOR ARGB_V_csa1_3 ) = NOR_V_csa1_3
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 NOR ARGB_V_csa1_4 ) = NOR_V_csa1_4
REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 NOR ARGB_V_usa1_1 ) = NOR_V_usa1_1
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 NOR ARGB_V_usa1_2 ) = NOR_V_usa1_2
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 NOR ARGB_V_usa1_3 ) = NOR_V_usa1_3
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 NOR ARGB_V_usa1_4 ) = NOR_V_usa1_4
REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 NOR ARGB_C_csa1_1 ) = NOR_C_csa1_1 and
( ARGA_C_csa1_2 NOR ARGB_C_csa1_2 ) = NOR_C_csa1_2 and
( ARGA_C_csa1_3 NOR ARGB_C_csa1_3 ) = NOR_C_csa1_3 and
( ARGA_C_csa1_4 NOR ARGB_C_csa1_4 ) = NOR_C_csa1_4 and
( ARGA_C_usa1_1 NOR ARGB_C_usa1_1 ) = NOR_C_usa1_1 and
( ARGA_C_usa1_2 NOR ARGB_C_usa1_2 ) = NOR_C_usa1_2 and
( ARGA_C_usa1_3 NOR ARGB_C_usa1_3 ) = NOR_C_usa1_3 and
( ARGA_C_usa1_4 NOR ARGB_C_usa1_4 ) = NOR_C_usa1_4 and
( ARGA_S_csa1_1 NOR ARGB_S_csa1_1 ) = NOR_S_csa1_1 and
( ARGA_S_csa1_2 NOR ARGB_S_csa1_2 ) = NOR_S_csa1_2 and
( ARGA_S_csa1_3 NOR ARGB_S_csa1_3 ) = NOR_S_csa1_3 and
( ARGA_S_csa1_4 NOR ARGB_S_csa1_4 ) = NOR_S_csa1_4 and
( ARGA_S_usa1_1 NOR ARGB_S_usa1_1 ) = NOR_S_usa1_1 and
( ARGA_S_usa1_2 NOR ARGB_S_usa1_2 ) = NOR_S_usa1_2 and
( ARGA_S_usa1_3 NOR ARGB_S_usa1_3 ) = NOR_S_usa1_3 and
( ARGA_S_usa1_4 NOR ARGB_S_usa1_4 ) = NOR_S_usa1_4 and
( ARGA_V_csa1_1 NOR ARGB_V_csa1_1 ) = NOR_V_csa1_1 and
( ARGA_V_csa1_2 NOR ARGB_V_csa1_2 ) = NOR_V_csa1_2 and
( ARGA_V_csa1_3 NOR ARGB_V_csa1_3 ) = NOR_V_csa1_3 and
( ARGA_V_csa1_4 NOR ARGB_V_csa1_4 ) = NOR_V_csa1_4 and
( ARGA_V_usa1_1 NOR ARGB_V_usa1_1 ) = NOR_V_usa1_1 and
( ARGA_V_usa1_2 NOR ARGB_V_usa1_2 ) = NOR_V_usa1_2 and
( ARGA_V_usa1_3 NOR ARGB_V_usa1_3 ) = NOR_V_usa1_3 and
( ARGA_V_usa1_4 NOR ARGB_V_usa1_4 ) = NOR_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01948"
severity NOTE;
assert ( ( ARGA_C_csa1_1 NOR ARGB_C_csa1_1 ) = NOR_C_csa1_1 and
( ARGA_C_csa1_2 NOR ARGB_C_csa1_2 ) = NOR_C_csa1_2 and
( ARGA_C_csa1_3 NOR ARGB_C_csa1_3 ) = NOR_C_csa1_3 and
( ARGA_C_csa1_4 NOR ARGB_C_csa1_4 ) = NOR_C_csa1_4 and
( ARGA_C_usa1_1 NOR ARGB_C_usa1_1 ) = NOR_C_usa1_1 and
( ARGA_C_usa1_2 NOR ARGB_C_usa1_2 ) = NOR_C_usa1_2 and
( ARGA_C_usa1_3 NOR ARGB_C_usa1_3 ) = NOR_C_usa1_3 and
( ARGA_C_usa1_4 NOR ARGB_C_usa1_4 ) = NOR_C_usa1_4 and
( ARGA_S_csa1_1 NOR ARGB_S_csa1_1 ) = NOR_S_csa1_1 and
( ARGA_S_csa1_2 NOR ARGB_S_csa1_2 ) = NOR_S_csa1_2 and
( ARGA_S_csa1_3 NOR ARGB_S_csa1_3 ) = NOR_S_csa1_3 and
( ARGA_S_csa1_4 NOR ARGB_S_csa1_4 ) = NOR_S_csa1_4 and
( ARGA_S_usa1_1 NOR ARGB_S_usa1_1 ) = NOR_S_usa1_1 and
( ARGA_S_usa1_2 NOR ARGB_S_usa1_2 ) = NOR_S_usa1_2 and
( ARGA_S_usa1_3 NOR ARGB_S_usa1_3 ) = NOR_S_usa1_3 and
( ARGA_S_usa1_4 NOR ARGB_S_usa1_4 ) = NOR_S_usa1_4 and
( ARGA_V_csa1_1 NOR ARGB_V_csa1_1 ) = NOR_V_csa1_1 and
( ARGA_V_csa1_2 NOR ARGB_V_csa1_2 ) = NOR_V_csa1_2 and
( ARGA_V_csa1_3 NOR ARGB_V_csa1_3 ) = NOR_V_csa1_3 and
( ARGA_V_csa1_4 NOR ARGB_V_csa1_4 ) = NOR_V_csa1_4 and
( ARGA_V_usa1_1 NOR ARGB_V_usa1_1 ) = NOR_V_usa1_1 and
( ARGA_V_usa1_2 NOR ARGB_V_usa1_2 ) = NOR_V_usa1_2 and
( ARGA_V_usa1_3 NOR ARGB_V_usa1_3 ) = NOR_V_usa1_3 and
( ARGA_V_usa1_4 NOR ARGB_V_usa1_4 ) = NOR_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01948 - Logical operator NOR for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01948arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd | 4 | 2628 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc570.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:32 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00570ent IS
END c03s04b01x00p01n01i00570ent;
ARCHITECTURE c03s04b01x00p01n01i00570arch OF c03s04b01x00p01n01i00570ent IS
type real_file is file of real;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_file open read_mode is "iofile.19";
variable v : real;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3.0) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00570"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00570 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00570arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc156.vhd | 4 | 2366 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc156.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p17n01i00156ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p17n01i00156ent;
ARCHITECTURE c04s03b02x02p17n01i00156arch OF c04s03b02x02p17n01i00156ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>conv1(a2),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
assert FALSE
report "***FAILED TEST: c04s03b02x02p17n01i00156 - Type coversion return wrong type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p17n01i00156arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd | 4 | 1869 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02061ent IS
END c07s02b04x00p01n02i02061ent;
ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
signal S1 : Integer;
signal S2 : Integer;
signal S3 : BIT_VECTOR(0 to 7);
BEGIN
TESTING: PROCESS
variable V1,V2 : Integer := 10;
variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
BEGIN
S1 <= V1 + V2;
wait for 1 ns;
assert NOT(S1 = 20)
report "***PASSED TEST: c07s02b04x00p01n02i02061"
severity NOTE;
assert (S1 = 20)
report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02061arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd | 4 | 1867 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1447.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01447ent IS
END c08s07b00x00p02n01i01447ent;
ARCHITECTURE c08s07b00x00p02n01i01447arch OF c08s07b00x00p02n01i01447ent IS
begin
transmit: process
procedure ARITH(z : out integer) is
begin
z := 5;
end ARITH;
variable k : integer ;
variable m : integer := 6;
begin
if m > 5 then
ARITH(k);
end if;
assert (k = 5)
report "***FAILED TEST: c08s07b00x00p02n01i01447 - Procedure Call statement to be sequence statements of IF statement"
severity ERROR;
assert NOT(k = 5)
report "***PASSED TEST: c08s07b00x00p02n01i01447"
severity NOTE;
wait;
end process;
END c08s07b00x00p02n01i01447arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1069/tdp_ram_single.vhdl | 1 | 2793 | library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 12;
WIDTH_A : positive := 8;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
byteen_a : in std_logic_vector(WIDTH_A/COL_WIDTH - 1 downto 0);
addr_a : in std_logic_vector(ADDRWIDTH_A - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH_A - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH_A - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
function log2(val : INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
function eq_assert(x : integer; y : integer) return integer is
begin
assert x = y;
return x;
end function eq_assert;
constant COLS_A : positive := WIDTH_A / COL_WIDTH;
constant COLS_B : positive := WIDTH_B / COL_WIDTH;
constant TOTAL_COLS : positive := eq_assert(COLS_A * 2 ** ADDRWIDTH_A, COLS_B * 2 ** ADDRWIDTH_B);
constant EXTRA_ADDR_BITS_A : positive := log2(COLS_A);
constant EXTRA_ADDR_BITS_B : positive := log2(COLS_B);
type ram_t is array(0 to TOTAL_COLS - 1) of std_logic_vector(COL_WIDTH - 1 downto 0);
shared variable store : ram_t := (others => (others => '0'));
signal reg_a : std_logic_vector(WIDTH_A - 1 downto 0);
begin
assert WIDTH_A mod COL_WIDTH = 0 and
WIDTH_B mod COL_WIDTH = 0 and
2 ** (ADDRWIDTH_A + EXTRA_ADDR_BITS_A) = TOTAL_COLS and
2 ** (ADDRWIDTH_B + EXTRA_ADDR_BITS_B) = TOTAL_COLS
report "Both WIDTH_A and WIDTH_B have to be a power-of-two multiple of COL_WIDTH"
severity failure;
process(clk_a)
begin
if rising_edge(clk_a) then
for i in 0 to COLS_A - 1 loop
if write_a = '1' and byteen_a(i) = '1' then
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A))) :=
data_write_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_a = '1' then
reg_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A)));
end if;
end loop;
data_read_a <= reg_a;
end if;
end process;
end behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd | 4 | 2553 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of multiplier_test is
signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
signal p : std_ulogic_vector(31 downto 0);
begin
dut : entity work.multiplier(behavioral)
port map (a, b, p);
stimulus : process is
begin
a <= X"8000"; b <= X"8000"; -- -1 * -1
wait for 50 ns;
a <= X"0001"; b <= X"0001"; -- 2**-15 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"0000"; -- 2**-15 * 0
wait for 50 ns;
a <= X"0000"; b <= X"0001"; -- 0 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"8000"; -- 2**-15 * -1
wait for 50 ns;
a <= X"8000"; b <= X"0001"; -- -1 * 2**-15
wait for 50 ns;
a <= X"4000"; b <= X"4000"; -- 0.5 * 0.5
wait for 50 ns;
a <= X"C000"; b <= X"4000"; -- -0.5 * 0.5
wait for 50 ns;
a <= X"4000"; b <= X"C000"; -- 0.5 * -0.5
wait for 50 ns;
a <= X"C000"; b <= X"C000"; -- -0.5 * -0.5
wait for 50 ns;
wait;
end process stimulus;
end architecture bench;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd | 4 | 1346 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
clk, reset : in bit );
end entity reg;
--------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk, reset) is
constant zero : bit_vector(0 to width - 1) := (others => '0');
begin
if reset = '1' then
q <= zero;
elsif clk'event and clk = '1' then
q <= d;
end if;
end process behavior;
end architecture behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1241/tb_top.vhdl | 1 | 668 | entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_top is
signal sel : unsigned(1 downto 0);
signal data : std_logic_vector(3 downto 0);
signal q : std_logic;
begin
dut: entity work.top
port map (sel, data, q);
process
begin
data <= "1001";
sel <= "10";
wait for 1 ns;
assert q = '0' severity failure;
sel <= "11";
wait for 1 ns;
assert q = '1' severity failure;
sel <= "00";
wait for 1 ns;
assert q = '1' severity failure;
sel <= "01";
wait for 1 ns;
assert q = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1310/issue.vhdl | 1 | 727 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (sig_gt, sig_ge, sig_lt, sig_le : out boolean;
uns_gt, uns_ge, uns_lt, uns_le : out boolean);
end issue;
architecture beh of issue is
begin
-- all of those works
uns_gt <= (unsigned'("1111") > unsigned'("0111"));
uns_ge <= (unsigned'("1111") >= unsigned'("0111"));
uns_lt <= (unsigned'("1111") < unsigned'("0111"));
uns_le <= (unsigned'("1111") <= unsigned'("0111"));
sig_gt <= (signed'("1111") > signed'("0111"));
sig_ge <= (signed'("1111") >= signed'("0111"));
sig_lt <= (signed'("1111") < signed'("0111"));
sig_le <= (signed'("1111") <= signed'("0111"));
end architecture beh;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc845.vhd | 4 | 2502 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc845.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b01x00p07n01i00845ent_a is
end c01s03b01x00p07n01i00845ent_a;
architecture c01s03b01x00p07n01i00845arch_a of c01s03b01x00p07n01i00845ent_a is
begin
AC_BLK : block
signal B : BIT;
begin
B <= '1';
end block;
end;
ENTITY c01s03b01x00p07n01i00845ent IS
END c01s03b01x00p07n01i00845ent;
ARCHITECTURE c01s03b01x00p07n01i00845arch OF c01s03b01x00p07n01i00845ent IS
BEGIN
A_BLK : block
component C
end component;
begin
L1 : C;
L2 : C;
L3 : C;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b01x00p07n01i00845 - Block configuration must be an architecture name."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p07n01i00845arch;
configuration c01s03b01x00p07n01i00845cfg of c01s03b01x00p07n01i00845ent is
for PQ -- Failure_here
for A_BLK
for L1 : C
use entity work.c01s03b01x00p07n01i00845ent_a (c01s03b01x00p07n01i00845arch_a) ;
end for;
for L2 : C
use entity work.c01s03b01x00p07n01i00845ent_a (c01s03b01x00p07n01i00845arch_a) ;
end for;
for L3 : C
use entity work.c01s03b01x00p07n01i00845ent_a (c01s03b01x00p07n01i00845arch_a) ;
end for;
end for;
end for ;
end c01s03b01x00p07n01i00845cfg ;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2942.vhd | 4 | 1903 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2942.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n04i02942pkg is
procedure proc1 (x:integer; y : integer);
end c02s02b00x00p07n04i02942pkg;
package body c02s02b00x00p07n04i02942pkg is
procedure proc1 (x, y :in integer) is --Failure_here
begin
end proc1;
end c02s02b00x00p07n04i02942pkg;
ENTITY c02s02b00x00p07n04i02942ent IS
END c02s02b00x00p07n04i02942ent;
ARCHITECTURE c02s02b00x00p07n04i02942arch OF c02s02b00x00p07n04i02942ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02942 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02942arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2844.vhd | 4 | 1605 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2844.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity UNTIL is
end UNTIL;
ENTITY c13s09b00x00p99n01i02844ent IS
END c13s09b00x00p99n01i02844ent;
ARCHITECTURE c13s09b00x00p99n01i02844arch OF c13s09b00x00p99n01i02844ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02844 - Reserved word UNTIL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02844arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_563.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_563;
architecture augh of sub_563 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue212/test.vhdl | 2 | 858 | PACKAGE test_pkg IS
TYPE test_record_t IS RECORD
number : integer;
END RECORD test_record_t;
FUNCTION set_test_record_default
RETURN test_record_t;
FUNCTION set_test_record (
CONSTANT C_TEST : test_record_t := set_test_record_default)
RETURN test_record_t;
END PACKAGE test_pkg;
PACKAGE BODY test_pkg IS
FUNCTION set_test_record_default
RETURN test_record_t IS
VARIABLE result : test_record_t;
BEGIN
result.number := 0;
RETURN result;
END set_test_record_default;
FUNCTION set_test_record (
CONSTANT C_TEST : test_record_t := set_test_record_default)
RETURN test_record_t IS
BEGIN
RETURN C_TEST;
END set_test_record;
END PACKAGE BODY test_pkg;
ENTITY test IS
END ENTITY test;
LIBRARY work;
USE work.test_pkg.set_test_record;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1861.vhd | 4 | 1927 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1861.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01861ent IS
END c07s01b00x00p08n01i01861ent;
ARCHITECTURE c07s01b00x00p08n01i01861arch OF c07s01b00x00p08n01i01861ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal obus : cmd_bus(small_int);
signal bool : boolean;
BEGIN
sig : bool <= true after 5 ns;
obus(sig) <= 5 after 5 ns; --signal assignment label illegal here
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01861 - Signal assignment labels are not permitted as primaries in an index expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01861arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd | 4 | 2987 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc408.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00408ent IS
END c03s02b01x01p19n01i00408ent;
ARCHITECTURE c03s02b01x01p19n01i00408arch OF c03s02b01x01p19n01i00408ent IS
constant C1 : character := 's';
function complex_scalar(s : character) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return character is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : character;
signal S2 : character;
signal S3 : character := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00408"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00408 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00408arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd | 4 | 2589 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-- File : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\Default\genhdl\vhdl\tb_pll.vhd
-- CDB : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\default\default.cdb
-- By : CDB2VHDL Netlister version 16.1.0.2
-- Time : Fri Apr 05 12:08:46 2002
-- Entity/architecture declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_pll is
end tb_pll;
architecture tb_pll of tb_pll is
-- Component declarations
-- Signal declarations
signal f_ref : real;
terminal lf_out : electrical;
terminal v_ref : electrical;
signal vco_f : real;
terminal vco_out : electrical;
begin
-- Signal assignments
-- Component instances
PLL6 : entity work.PLL(behavioral)
generic map(
Fp => 20.0e3,
Fz => 1.0e6,
Kv => 100.0e3,
Fc => 1.0e6
)
port map(
input => v_ref,
lf_out => lf_out,
vco_out => vco_out
);
v1 : entity work.v_SweptSine(bhv)
generic map(
StartFreq => 900.0e3,
SweepRate => 2000.0e6,
FinishFreq => 1.1e6,
InitDelay => 80.0e-6,
PeakAmp => 5.0
)
port map(
pos => v_ref,
neg => ELECTRICAL_REF
);
MeasFreq9 : entity work.MeasFreq(ThresDetect)
port map(
input => v_ref,
f_out => f_ref
);
MeasFreq10 : entity work.MeasFreq(ThresDetect)
port map(
input => vco_out,
f_out => vco_f
);
end tb_pll;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug052/tb.vhdl | 2 | 228 | entity tb is
package pkg1 is
constant c : natural := 5;
end pkg1;
end tb;
architecture behav of tb is
begin
assert pkg1.c = 5 severity failure;
assert pkg1.c /= 5 report "value is correct" severity note;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug077/repro6.vhdl | 1 | 545 | entity repro6 is
end repro6;
architecture behav of repro6 is
type my_rec is record
a : bit;
w : bit_vector (1 to 3);
end record;
procedure check (signal v : my_rec) is
begin
assert v.a = '0' and v.w = "001";
end check;
procedure pack (signal a : bit; signal w : bit_vector) is
begin
check (v.a => a,
v.w => w);
end pack;
signal sa : bit;
signal sw : bit_vector (1 to 2);
begin
process
begin
sa <= '0';
sw <= "01";
wait for 0 ns;
pack (sa, sw);
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd | 4 | 2007 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1081.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01081ent IS
END c06s05b00x00p01n02i01081ent;
ARCHITECTURE c06s05b00x00p01n02i01081arch OF c06s05b00x00p01n02i01081ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
BEGIN
TESTING: PROCESS
VARIABLE var : bit_vector_8 := B"1110_0010";
VARIABLE v1 : bit_vector_4 := B"0011";
VARIABLE v2 : bit_vector_4 := B"1111";
BEGIN
var (0 to 3) := v1;
var (4 to 7) := v2;
assert NOT( var = B"0011_1111" )
report "***PASSED TEST: c06s05b00x00p01n02i01081"
severity NOTE;
assert ( var = B"0011_1111" )
report "***FAILED TEST: c06s05b00x00p01n02i01081 - Slices of a variable may be the target of a variable assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01081arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/block-statements/simple-grouping-block.vhdl | 3 | 621 | entity test is
end test;
architecture only of test is
signal delay_line_in : bit := '0';
signal delay_line_out : bit := '0';
begin -- only
delay: block
begin -- block delay
delay_line_out <= delay_line_in after 1 ns;
end block delay;
start: process
begin -- process
delay_line_in <= '1';
wait;
end process;
check: process( delay_line_out )
begin
if delay_line_out = '1' then
assert now = 1 ns report "TEST FAILED - delay did not happen as expected!" severity FAILURE;
assert not(now = 1 ns) report "TEST PASSED" severity WARNING;
end if;
end process;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd | 4 | 3267 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_mixer is
end tb_mixer;
architecture TB_mixer of tb_mixer is
-- Component declarations
-- Signal declarations
terminal mix_in : electrical_vector(1 to 8);
terminal pseudo_gnd : electrical;
begin
-- Signal assignments
-- Component instances
v3 : entity work.v_sine(ideal)
generic map(
amplitude => 5.0,
freq => 1.0e3
)
port map(
pos => mix_in(7),
neg => ELECTRICAL_REF
);
v4 : entity work.v_sine(ideal)
generic map(
amplitude => 4.0,
freq => 2.0e3
)
port map(
pos => mix_in(8),
neg => ELECTRICAL_REF
);
v9 : entity work.v_sine(ideal)
generic map(
freq => 1.0e3,
amplitude => 5.0
)
port map(
pos => mix_in(5),
neg => ELECTRICAL_REF
);
v10 : entity work.v_sine(ideal)
generic map(
freq => 2.0e3,
amplitude => 4.0
)
port map(
pos => mix_in(6),
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => pseudo_gnd,
p2 => ELECTRICAL_REF
);
mixer1 : entity work.mixer_wa(weighted)
port map(
inputs => mix_in,
output => pseudo_gnd
);
v14 : entity work.v_sine(ideal)
generic map(
amplitude => 4.0,
freq => 2.0e3
)
port map(
pos => mix_in(2),
neg => ELECTRICAL_REF
);
v15 : entity work.v_sine(ideal)
generic map(
amplitude => 5.0,
freq => 1.0e3
)
port map(
pos => mix_in(1),
neg => ELECTRICAL_REF
);
v16 : entity work.v_sine(ideal)
generic map(
freq => 2.0e3,
amplitude => 4.0
)
port map(
pos => mix_in(4),
neg => ELECTRICAL_REF
);
v17 : entity work.v_sine(ideal)
generic map(
freq => 1.0e3,
amplitude => 5.0
)
port map(
pos => mix_in(3),
neg => ELECTRICAL_REF
);
end TB_mixer;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket32/arith_prefix_and.vhdl | 3 | 2968 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- =============================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
entity arith_prefix_and is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_and;
architecture rtl of arith_prefix_and is
type T_VENDOR is (VENDOR_XILINX, VENDOR_ALTERA);
constant VENDOR : T_VENDOR := VENDOR_XILINX;
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) and x(1);
gen2: if N > 2 generate
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
s <= std_logic_vector(('0' & p) + 1);
y(N-1 downto 2) <= s(N downto 3) xor ('0' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
-- component MUXCY
-- port (
-- S : in std_logic;
-- DI : in std_logic;
-- CI : in std_logic;
-- O : out std_logic
-- );
-- end component;
signal c : std_logic_vector(N-1 downto 0);
begin
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : entity unisim.MUXCY
port map (
S => p(i),
DI => '0',
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2965.vhd | 4 | 1870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2965.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p03n01i02965pkg is
procedure proc1 (x:integer);
procedure proc1 (x:integer); -- Failure_here
end c02s03b00x00p03n01i02965pkg;
package body c02s03b00x00p03n01i02965pkg is
procedure proc1 (x:integer) is
begin
end proc1;
end c02s03b00x00p03n01i02965pkg;
ENTITY c02s03b00x00p03n01i02965ent IS
END c02s03b00x00p03n01i02965ent;
ARCHITECTURE c02s03b00x00p03n01i02965arch OF c02s03b00x00p03n01i02965ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s03b00x00p03n01i02965 - A call to an overloaded subprogram is ambiguous."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p03n01i02965
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd | 4 | 1885 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc272.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p06n01i00272ent IS
END c03s01b03x00p06n01i00272ent;
ARCHITECTURE c03s01b03x00p06n01i00272arch OF c03s01b03x00p06n01i00272ent IS
type small is range 0 to 2_000_000_000 -- < 2**31-1
units
lu;
end units;
BEGIN
TESTING: PROCESS
variable smaller : small;
BEGIN
smaller := 2000000000 lu;
wait for 5 ns;
assert NOT( smaller = 2000000000 lu )
report "***PASSED TEST: c03s01b03x00p06n01i00272"
severity NOTE;
assert ( smaller = 2000000000 lu )
report "***FAILED TEST: c03s01b03x00p06n01i00272 - Large physical type declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p06n01i00272arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1023.vhd | 4 | 1810 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1023.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n02i01023ent IS
END c06s03b00x00p10n02i01023ent;
ARCHITECTURE c06s03b00x00p10n02i01023arch OF c06s03b00x00p10n02i01023ent IS
BEGIN
TESTING: PROCESS
variable j : integer;
BEGIN
L1: for i in 1 to 10 loop
e.j := L1.i;
end loop;
j := L1.i; -- illegal as reference to L1.i is allowed within the
-- loop L1 only.
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01023 - An expanded name denoting an entity declared within a named construct is allowed only within the construct."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n02i01023arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1696.vhd | 4 | 1642 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1696.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p05n01i01696ent IS
END c09s02b00x00p05n01i01696ent;
ARCHITECTURE c09s02b00x00p05n01i01696arch OF c09s02b00x00p05n01i01696ent IS
BEGIN
TESTING: PROCESS
BEGIN
process -- ERROR:
begin
wait;
end process;
assert FALSE
report "***FAILED TEST: c09s02b00x00p05n01i01696 - Process statements are illegal inside the body a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p05n01i01696arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_337.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_337 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_337;
architecture augh of sub_337 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue956/ent.vhdl | 1 | 323 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
i : in bit;
o : out bit
);
end;
architecture a of ent is
signal test : std_logic_vector(0 to 7);
begin
process(i)
begin
for x in test'low to test'high loop
end loop;
o <= i;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue458/repro2.vhdl | 1 | 575 | entity repro is
end entity;
architecture A of repro is
signal S1 : bit := '0';
signal S2_transport : bit;
signal S2_delayed : bit;
begin
S1 <= '1' after 10 ns, '0' after 20 ns;
S2_transport <= transport S1 after 100 ns;
S2_delayed <= S1'delayed(100 ns);
process (S1) is
begin
assert false report "S1 = " & bit'image(S1) severity note;
end process;
process (S2_delayed) is
begin
assert false report "S1'delayed = " & bit'image(S2_delayed) severity note;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug20255/test.vhd | 3 | 369 | entity e is
end entity e;
architecture test of e is
begin
test : process is
type frequency is range -2147483647 to 2147483647 units KHz;
MHz = 1000 KHz;
GHz = 1000 MHz;
end units;
begin
assert frequency'image(2 MHz) = "2000 khz"; -- this should work, but GHDL produces an error
wait;
end process;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd | 4 | 2034 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2945.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean;
end c02s02b00x00p07n05i02945pkg;
package body c02s02b00x00p07n05i02945pkg is
function F1 (i : integer) return Boolean is
begin
return TRUE;
end F1;
end c02s02b00x00p07n05i02945pkg;
use work.c02s02b00x00p07n05i02945pkg.all;
ENTITY c02s02b00x00p07n05i02945ent IS
END c02s02b00x00p07n05i02945ent;
ARCHITECTURE c02s02b00x00p07n05i02945arch OF c02s02b00x00p07n05i02945ent IS
BEGIN
TESTING: PROCESS
variable k : boolean;
BEGIN
k := F1(2);
assert NOT( k=TRUE )
report "***PASSED TEST: c02s02b00x00p07n05i02945"
severity NOTE;
assert ( k=TRUE )
report "***FAILED TEST: c02s02b00x00p07n05i02945 - Subprogram Function declaration test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n05i02945arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_213.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_213 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_213;
architecture augh of sub_213 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd | 4 | 1363 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity analog_switch is
port ( terminal n1, n2 : electrical;
signal control : in std_ulogic );
end entity analog_switch;
----------------------------------------------------------------
architecture ideal of analog_switch is
quantity v across i through n1 to n2;
begin
if control = '1' or control = 'H' use
v == 0.0;
else
i == 0.0;
end use;
break on control;
end architecture ideal;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2076.vhd | 4 | 1818 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2076.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02076ent IS
END c07s02b04x00p01n02i02076ent;
ARCHITECTURE c07s02b04x00p01n02i02076arch OF c07s02b04x00p01n02i02076ent IS
BEGIN
TESTING: PROCESS
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- Local declarations.
variable TIMEV : TIME := 1 ns;
variable POSRV : POSITIVE_R := 0.0;
BEGIN
TIMEV := TIMEV + POSRV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02076 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02076arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/oper01/uns01.vhdl | 1 | 426 | entity uns01 is
port (ok : out boolean);
end uns01;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of uns01 is
-- add uns uns
constant a : unsigned (7 downto 0) := x"1e";
constant b : unsigned (3 downto 0) := x"2";
constant r1 : unsigned (7 downto 0) := a - b;
signal er1 : unsigned (7 downto 0);
begin
er1 <= x"1c";
-- ok <= r1 = x"20";
ok <= r1 = er1;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1161/issue1.vhdl | 1 | 210 | library ieee;
use ieee.std_logic_1164.all;
entity issue1 is
port (foo : out std_logic_vector(4-1 downto 0));
end issue1;
architecture rtl of issue1 is
begin
foo <= ("0",others=>'1');
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd | 4 | 2370 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity misc_logic is
end entity misc_logic;
-- end not in book
use work.MVL4.all;
architecture gate_level of misc_logic is
signal src1, src1_enable : MVL4_ulogic;
signal src2, src2_enable : MVL4_ulogic;
signal selected_val : MVL4_logic;
-- . . .
begin
src1_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src1, enable => src1_enable, y => selected_val );
src2_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src2, enable => src2_enable, y => selected_val );
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
src1 <= '0'; src2 <= '1'; wait for 10 ns;
src1_enable <= '1'; wait for 10 ns;
src1 <= 'Z'; wait for 10 ns;
src1 <= '1'; wait for 10 ns;
src1_enable <= '0'; wait for 10 ns;
src2_enable <= '1'; wait for 10 ns;
src2 <= 'Z'; wait for 10 ns;
src2 <= '0'; wait for 10 ns;
src2_enable <= '0'; wait for 10 ns;
src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
src1 <= '0'; wait for 10 ns;
src1 <= 'X'; wait for 10 ns;
src1 <= '1'; src2 <= '1'; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture gate_level;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd | 4 | 1831 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1991.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01991ent IS
END c07s02b02x00p07n01i01991ent;
ARCHITECTURE c07s02b02x00p07n01i01991arch OF c07s02b02x00p07n01i01991ent IS
BEGIN
TESTING: PROCESS
type ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
variable k : integer := 0;
BEGIN
if (ONE /= TWO) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01991"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01991 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01991arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc195.vhd | 4 | 1845 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc195.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s00b00x00p11n01i00195ent IS
END c03s00b00x00p11n01i00195ent;
ARCHITECTURE c03s00b00x00p11n01i00195arch OF c03s00b00x00p11n01i00195ent IS
type T1 is array (0 to 31) of BIT;
subtype T2 is integer range 2 to 20;
signal S1 : T2 ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= 25 after 10 ns;
wait for 20 ns;
assert NOT(S1 = 25)
report "***PASSED TEST: c03s00b00x00p11n01i00195"
severity NOTE;
assert ( S1 = 25 )
report "***FAILED TEST: c03s00b00x00p11n01i00195 - Value doesn't belong to the range of the subtype of the object."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s00b00x00p11n01i00195arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue610/repro4.vhdl | 1 | 310 | entity repro4 is
end repro4;
architecture behav of repro4 is
procedure set (signal v : out string) is
begin
v <= (others => ' ');
end set;
signal s : string (1 to 3);
begin
set (s);
process
begin
wait for 0 ns;
assert s = " " severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue238/cst.vhdl | 2 | 154 | package cst is
function four return natural;
end cst;
package body cst is
function four return natural is
begin
return 4;
end four;
end cst;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_160.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_160 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_160;
architecture augh of cmp_160 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue99/bug2.vhdl | 2 | 185 | package bug2 is
generic ( gen: natural );
constant test: natural:=gen;
function get_val return natural;
end package;
package mygbug2 is new work.bug2 generic map ( gen => 17 );
| gpl-2.0 |
tgingold/ghdl | libraries/vital2000/memory_b.vhdl | 6 | 275738 | -- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
-- : Jose De Castro, Consultant
-- : Prakash Bare, GDA Technologies
-- : William Yam, LSI Logic Corporation
-- : Dennis Brophy, Model Technology
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC memory models.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Ver:|Auth:| Date:| Changes Made:
-- 0.1 | eb |071796| First prototye as part of VITAL memory proposal
-- 0.2 | jdc |012897| Initial prototyping with proposed MTM scheme
-- 0.3 | jdc |090297| Extensive updates for TAG review (functional)
-- 0.4 | eb |091597| Changed naming conventions for VitalMemoryTable
-- | | | Added interface of VitalMemoryCrossPorts() &
-- | | | VitalMemoryViolation().
-- 0.5 | jdc |092997| Completed naming changes thoughout package body.
-- | | | Testing with simgle port test model looks ok.
-- 0.6 | jdc |121797| Major updates to the packages:
-- | | | - Implement VitalMemoryCrossPorts()
-- | | | - Use new VitalAddressValueType
-- | | | - Use new VitalCrossPortModeType enum
-- | | | - Overloading without SamePort args
-- | | | - Honor erroneous address values
-- | | | - Honor ports disabled with 'Z'
-- | | | - Implement implicit read 'M' table symbol
-- | | | - Cleanup buses to use (H DOWNTO L)
-- | | | - Message control via MsgOn,HeaderMsg,PortName
-- | | | - Tested with 1P1RW,2P2RW,4P2R2W,4P4RW cases
-- 0.7 | jdc |052698| Bug fixes to the packages:
-- | | | - Fix failure with negative Address values
-- | | | - Added debug messages for VMT table search
-- | | | - Remove 'S' for action column (only 's')
-- | | | - Remove 's' for response column (only 'S')
-- | | | - Remove 'X' for action and response columns
-- 0.8 | jdc |061298| Implemented VitalMemoryViolation()
-- | | | - Minimal functionality violation tables
-- | | | - Missing:
-- | | | - Cannot handle wide violation variables
-- | | | - Cannot handle sub-word cases
-- | | | Fixed IIC version of MemoryMatch
-- | | | Fixed 'M' vs 'm' switched on debug output
-- | | | TO BE DONE:
-- | | | - Implement 'd' corrupting a single bit
-- | | | - Implement 'D' corrupting a single bit
-- 0.9 |eb/sc|080498| Added UNDEF value for VitalPortFlagType
-- 0.10|eb/sc|080798| Added CORRUPT value for VitalPortFlagType
-- 0.11|eb/sc|081798| Added overloaded function interface for
-- | | | VitalDeclareMemory
-- 0.14| jdc |113198| Merging of memory functionality and version
-- | | | 1.4 9/17/98 of timing package from Prakash
-- 0.15| jdc |120198| Major development of VMV functionality
-- 0.16| jdc |120298| Complete VMV functionlality for initial testing
-- | | | - New ViolationTableCorruptMask() procedure
-- | | | - New MemoryTableCorruptMask() procedure
-- | | | - HandleMemoryAction():
-- | | | - Removed DataOutBus bogus output
-- | | | - Replaced DataOutTmp with DataInTmp
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'c','l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'c','l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'C','L','D','E' to use HighBit, LowBit
-- | | | - HandleDataAction():
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'L','D','E' to use HighBit, LowBit
-- | | | - MemoryTableLookUp():
-- | | | - Added MsgOn table debug output
-- | | | - Uses new MemoryTableCorruptMask()
-- | | | - ViolationTableLookUp():
-- | | | - Uses new ViolationTableCorruptMask()
-- 0.17| jdc |120898| - Added VitalMemoryViolationSymbolType,
-- | | | VitalMemoryViolationTableType data
-- | | | types but not used yet (need to discuss)
-- | | | - Added overload for VitalMemoryViolation()
-- | | | which does not have array flags
-- | | | - Bug fixes for VMV functionality:
-- | | | - ViolationTableLookUp() not handling '-' in
-- | | | scalar violation matching
-- | | | - VitalMemoryViolation() now normalizes
-- | | | VFlagArrayTmp'LEFT as LSB before calling
-- | | | ViolationTableLookUp() for proper scanning
-- | | | - ViolationTableCorruptMask() had to remove
-- | | | normalization of CorruptMaskTmp and
-- | | | ViolMaskTmp for proper MSB:LSB corruption
-- | | | - HandleMemoryAction(), HandleDataAction()
-- | | | - Removed 'D','E' since not being used
-- | | | - Use XOR instead of OR for corrupt masks
-- | | | - Now 'd' is sensitive to HighBit, LowBit
-- | | | - Fixed LowBit overflow in bit writeable case
-- | | | - MemoryTableCorruptMask()
-- | | | - ViolationTableCorruptMask()
-- | | | - VitalMemoryTable()
-- | | | - VitalMemoryCrossPorts()
-- | | | - Fixed VitalMemoryViolation() failing on
-- | | | error AddressValue from earlier VMT()
-- | | | - Minor cleanup of code formatting
-- 0.18| jdc |032599| - In VitalDeclareMemory()
-- | | | - Added BinaryLoadFile formal arg and
-- | | | modified LoadMemory() to handle bin
-- | | | - Added NOCHANGE to VitalPortFlagType
-- | | | - For VitalCrossPortModeType
-- | | | - Added CpContention enum
-- | | | - In HandleDataAction()
-- | | | - Set PortFlag := NOCHANGE for 'S'
-- | | | - In HandleMemoryAction()
-- | | | - Set PortFlag := NOCHANGE for 's'
-- | | | - In VitalMemoryTable() and
-- | | | VitalMemoryViolation()
-- | | | - Honor PortFlag = NOCHANGE returned
-- | | | from HandleMemoryAction()
-- | | | - In VitalMemoryCrossPorts()
-- | | | - Fixed Address = AddressJ for all
-- | | | conditions of DoWrCont & DoCpRead
-- | | | - Handle CpContention like WrContOnly
-- | | | under CpReadOnly conditions, with
-- | | | associated memory message changes
-- | | | - Handle PortFlag = NOCHANGE like
-- | | | PortFlag = READ for actions
-- | | | - Modeling change:
-- | | | - Need to init PortFlag every delta
-- | | | PortFlag_A := (OTHES => UNDEF);
-- | | | - Updated InternalTimingCheck code
-- 0.19| jdc |042599| - Fixes for bit-writeable cases
-- | | | - Check PortFlag after HandleDataAction
-- | | | in VitalMemoryViolation()
-- 0.20| jdc |042599| - Merge PortFlag changes from Prakash
-- | | | and Willian:
-- | | | VitalMemorySchedulePathDelay()
-- | | | VitalMemoryExpandPortFlag()
-- 0.21| jdc |072199| - Changed VitalCrossPortModeType enums,
-- | | | added new CpReadAndReadContention.
-- | | | - Fixed VitalMemoryCrossPorts() parameter
-- | | | SamePortFlag to INOUT so that it can
-- | | | set CORRUPT or READ value.
-- | | | - Fixed VitalMemoryTable() where PortFlag
-- | | | setting by HandleDataAction() is being
-- | | | ignored when HandleMemoryAction() sets
-- | | | PortFlagTmp to NOCHANGE.
-- | | | - Fixed VitalMemoryViolation() to set
-- | | | all bits of PortFlag when violating.
-- 0.22| jdc |072399| - Added HIGHZ to PortFlagType. HandleData
-- | | | checks whether the previous state is HIGHZ.
-- | | | If yes then portFlag should be NOCHANGE
-- | | | for VMPD to ignore IORetain corruption.
-- | | | The idea is that the first Z should be
-- | | | propagated but later ones should be ignored.
-- | | |
-- 0.23| jdc |100499| - Took code checked in by Dennis 09/28/99
-- | | | - Changed VitalPortFlagType to record of
-- | | | new VitalPortStateType to hold current,
-- | | | previous values and separate disable.
-- | | | Also created VitalDefaultPortFlag const.
-- | | | Removed usage of PortFlag NOCHANGE
-- | | | - VitalMemoryTable() changes:
-- | | | Optimized return when all curr = prev
-- | | | AddressValue is now INOUT to optimize
-- | | | Transfer PF.MemoryCurrent to MemoryPrevious
-- | | | Transfer PF.DataCurrent to DataPrevious
-- | | | Reset PF.OutputDisable to FALSE
-- | | | Expects PortFlag init in declaration
-- | | | No need to init PortFlag every delta
-- | | | - VitalMemorySchedulePathDelay() changes:
-- | | | Initialize with VitalDefaultPortFlag
-- | | | Check PortFlag.OutputDisable
-- | | | - HandleMemoryAction() changes:
-- | | | Set value of PortFlag.MemoryCurrent
-- | | | Never set PortFlag.OutputDisable
-- | | | - HandleDataAction() changes:
-- | | | Set value of PortFlag.DataCurrent
-- | | | Set PortFlag.DataCurrent for HIGHZ
-- | | | - VitalMemoryCrossPorts() changes:
-- | | | Check/set value of PF.MemoryCurrent
-- | | | Check value of PF.OutputDisable
-- | | | - VitalMemoryViolation() changes:
-- | | | Fixed bug - not reading inout PF value
-- | | | Clean up setting of PortFlag
-- 0.24| jdc |100899| - Modified update of PF.OutputDisable
-- | | | to correctly accomodate 2P1W1R case:
-- | | | the read port should not exhibit
-- | | | IO retain corrupt when reading
-- | | | addr unrelated to addr being written.
-- 0.25| jdc |100999| - VitalMemoryViolation() change:
-- | | | Fixed bug with RDNWR mode incorrectly
-- | | | updating the PF.OutputDisable
-- 0.26| jdc |100999| - VitalMemoryCrossPorts() change:
-- | | | Fixed bugs with update of PF
-- 0.27| jdc |101499| - VitalMemoryCrossPorts() change:
-- | | | Added DoRdWrCont message (ErrMcpRdWrCo,
-- | | | Memory cross port read/write data only
-- | | | contention)
-- | | | - VitalMemoryTable() change:
-- | | | Set PF.OutputDisable := TRUE for the
-- | | | optimized cases.
-- 0.28| pb |112399| - Added 8 VMPD procedures for vector
-- | | | PathCondition support. Now the total
-- | | | number of overloadings for VMPD is 24.
-- | | | - Number of overloadings for SetupHold
-- | | | procedures increased to 5. Scalar violations
-- | | | are not supported anymore. Vector checkEnabled
-- | | | support is provided through the new overloading
-- 0.29| jdc |120999| - HandleMemoryAction() HandleDataAction()
-- | | | Reinstated 'D' and 'E' actions but
-- | | | with new PortFlagType
-- | | | - Updated file handling syntax, must compile
-- | | | with -93 syntax now.
-- 0.30| jdc |022300| - Formated for 80 column max width
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.Vital_Timing.all;
USE IEEE.Vital_Primitives.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
-- ----------------------------------------------------------------------------
PACKAGE BODY Vital_Memory IS
-- ----------------------------------------------------------------------------
-- Timing Section
-- ----------------------------------------------------------------------------
FILE LogFile : TEXT OPEN write_mode IS "delayLog";
FILE Output : TEXT OPEN write_mode IS "STD_OUTPUT";
-- Added for turning off the debug msg..
CONSTANT PrintDebugMsg : STD_ULOGIC := '0';
-- '0' - don't print in STD OUTPUT
-- '1' - print in STD OUTPUT
-- Type and constant definitions for type conversion.
TYPE MVL9_TO_CHAR_TBL IS ARRAY (STD_ULOGIC) OF character;
--constant MVL9_to_char: MVL9_TO_CHAR_TBL := "UX01ZWLH-";
CONSTANT MVL9_to_char: MVL9_TO_CHAR_TBL := "XX01ZX010";
-- ----------------------------------------------------------------------------
-- STD_LOGIC WRITE UTILITIES
-- ----------------------------------------------------------------------------
PROCEDURE WRITE(
l : INOUT line;
val : IN std_logic_vector;
justify : IN side := right;
field : IN width := 0
) IS
VARIABLE invect : std_logic_vector(val'LENGTH DOWNTO 1);
VARIABLE ins : STRING(val'LENGTH DOWNTO 1);
BEGIN
invect := val;
FOR I IN invect'length DOWNTO 1 LOOP
ins(I) := MVL9_to_char(invect(I));
END LOOP;
WRITE(L, ins, justify, field);
END;
PROCEDURE WRITE(
l : INOUT line;
val : IN std_ulogic;
justify : IN side := right;
field : in width := 0
) IS
VARIABLE ins : CHARACTER;
BEGIN
ins := MVL9_to_char(val);
WRITE(L, ins, justify, field);
END;
-- ----------------------------------------------------------------------------
PROCEDURE DelayValue(
InputTime : IN TIME ;
outline : INOUT LINE
) IS
CONSTANT header : STRING := "TIME'HIGH";
BEGIN
IF(InputTime = TIME'HIGH) THEN
WRITE(outline, header);
ELSE
WRITE(outline, InputTime);
END IF;
END DelayValue;
-- ----------------------------------------------------------------------------
PROCEDURE PrintScheduleDataArray (
ScheduleDataArray : IN VitalMemoryScheduleDataVectorType
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
VARIABLE value : TIME;
CONSTANT empty : STRING := " ";
CONSTANT header1 : STRING := "i Age PropDly RetainDly";
CONSTANT header2 : STRING := "i Sc.Value Output Lastvalue Sc.Time";
BEGIN
WRITE (outline1, empty);
WRITE (outline1, NOW);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITE (outline1, header1);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
FOR i IN ScheduleDataArray'RANGE LOOP
WRITE (outline1, i );
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).InputAge, outline1);
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).PropDelay, outline1);
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).OutputRetainDelay, outline1);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
END LOOP;
WRITE (outline1, header2);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
FOR i IN ScheduleDataArray'RANGE LOOP
WRITE (outline1, i );
WRITE (outline1, empty);
WRITE (outline1, ScheduleDataArray(i).ScheduleValue);
WRITE (outline1, empty);
WRITE (outline1, ScheduleDataArray(i).OutputData);
WRITE (outline1, empty);
WRITE (outline1, ScheduleDataArray(i).LastOutputValue );
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).ScheduleTime, outline1);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
END LOOP;
WRITE (outline1, empty);
WRITE (outline2, empty);
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (Output, outline2);
END IF;
END PrintScheduleDataArray;
-- ----------------------------------------------------------------------------
PROCEDURE PrintArcType (
ArcType : IN VitalMemoryArcType
) IS
VARIABLE outline1, outline2 : LINE;
CONSTANT empty : STRING := " ";
CONSTANT cross : STRING := "CrossArc";
CONSTANT para : STRING := "ParallelArc";
CONSTANT sub : STRING := "SubWordArc";
CONSTANT Header1 : STRING := "Path considered @ ";
CONSTANT Header2 : STRING := " is ";
BEGIN
WRITELINE (LogFile, outline1);
WRITE (outline1, header1);
WRITE (outline1, NOW);
WRITE (outline1, empty);
WRITE (outline1, header2);
WRITE (outline1, empty);
case ArcType is
WHEN CrossArc =>
WRITE (outline1, cross);
WHEN ParallelArc =>
WRITE (outline1, para);
WHEN SubwordArc =>
WRITE (outline1, sub);
END CASE;
outline2 := outline1 ;
-- Appears on STD OUT
IF (PrintDebugMsg = '1') THEN
WRITELINE (Output, outline1);
END IF;
WRITELINE (LogFile, outline2);
END PrintArcType;
-- ----------------------------------------------------------------------------
-- This returns the value picked from the delay array
-- ----------------------------------------------------------------------------
PROCEDURE PrintDelay (
outbitpos : IN INTEGER;
InputArrayLow : IN INTEGER;
InputArrayHigh : IN INTEGER;
debugprop : IN VitalTimeArrayT;
debugretain : IN VitalTimeArrayT
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
VARIABLE outline3 : LINE;
VARIABLE outline4 : LINE;
VARIABLE outline5 : LINE;
VARIABLE outline6 : LINE;
CONSTANT empty : STRING := " ";
CONSTANT empty5 : STRING := " ";
CONSTANT header1 : STRING := "Prop. delays : ";
CONSTANT header2 : STRING := "Retain delays : ";
CONSTANT header3 : STRING := "output bit : ";
BEGIN
WRITE(outline1, header3);
WRITE(outline1, outbitpos);
outline2 := outline1;
WRITELINE(LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE(output, outline2);
END IF;
WRITE(outline1, header1);
WRITE (outline1, empty5);
FOR i IN InputArrayHigh DOWNTO InputArrayLow LOOP
DelayValue(debugprop(i), outline1);
WRITE(outline1, empty);
END LOOP;
outline2 := outline1;
WRITELINE(LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE(output, outline2);
END IF;
WRITE(outline1, header2);
WRITE (outline1, empty5);
FOR i in InputArrayHigh DOWNTO InputArrayLow LOOP
DelayValue(debugretain(i), outline1);
WRITE(outline1, empty);
END LOOP;
outline2 := outline1;
WRITELINE(LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE(output, outline2);
END IF;
END PrintDelay;
-- ----------------------------------------------------------------------------
PROCEDURE DebugMsg1 IS
CONSTANT header1:STRING:= "******************************************";
CONSTANT header2 :STRING:="Entering the process because of an i/p change";
variable outline1, outline2 : LINE;
BEGIN
WRITE(outline1, header1);
outline2 := outline1;
WRITELINE (Logfile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITE(outline1, header2);
outline2 := outline1;
WRITELINE (Logfile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITE(outline1, header1);
outline2 := outline1;
WRITELINE (Logfile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
END DebugMsg1;
-- ----------------------------------------------------------------------------
PROCEDURE ScheduleDebugMsg IS
CONSTANT header1 : STRING := "******************************************";
CONSTANT header2 : STRING := "Finished executing all the procedures";
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
BEGIN
WRITE(outline1, header1);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header2);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header1);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
END ScheduleDebugMsg;
-- ----------------------------------------------------------------------------
PROCEDURE PrintInputName(
InputSignalName : IN STRING
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
CONSTANT header1 : STRING := "***Changing input is ";
CONSTANT header2 : STRING := "(";
CONSTANT header3 : STRING := ")";
CONSTANT header4 : STRING := "****";
CONSTANT header5 : STRING := "******************************************";
CONSTANT header6 : STRING:="Entering the process because of an i/p change";
CONSTANT empty : STRING := " ";
BEGIN
WRITE(outline1, header5);
outline2 := outline1;
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
WRITE(outline1, header6);
outline2 := outline1;
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
WRITE(outline1, header5);
outline2 := outline1;
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
WRITE(outline1, header1);
WRITE(outline1, InputSignalName);
WRITE(outline1, empty);
WRITE(outline1, now);
WRITE(outline1, empty);
WRITE(outline1, header4);
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
END PrintInputName;
-- ----------------------------------------------------------------------------
PROCEDURE PrintInputChangeTime(
ChangeTimeArray : IN VitalTimeArrayT
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
CONSTANT header5 : STRING := "*************************************";
CONSTANT header6 : STRING:="ChangeTime Array : ";
CONSTANT empty : STRING := " ";
BEGIN
WRITE(outline1, header5);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header6);
FOR i in ChangeTimeArray'range LOOP
WRITE(outline1, ChangeTimeArray(i));
WRITE(outline1, empty);
END LOOP;
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header5);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
END PrintInputChangeTime;
-- ----------------------------------------------------------------------------
PROCEDURE PrintInputChangeTime(
ChangeTime : IN Time
) IS
VARIABLE ChangeTimeArray : VitalTimeArrayT(0 DOWNTO 0);
BEGIN
ChangeTimeArray(0) := ChangeTime;
PrintInputChangeTime(ChangeTimeArray);
END PrintInputChangeTime;
-- ----------------------------------------------------------------------------
-- for debug purpose
CONSTANT MaxNoInputBits : INTEGER := 1000;
TYPE VitalMemoryDelayType IS RECORD
PropDelay : TIME;
OutputRetainDelay : TIME;
END RECORD;
-- ----------------------------------------------------------------------------
-- PROCEDURE: IntToStr
--
-- PARAMETERS: InputInt - Integer to be converted to String.
-- ResultStr - String buffer for converted Integer
-- AppendPos - Position in buffer to place result
--
-- DESCRIPTION: This procedure is used to convert an input integer
-- into a string representation. The converted string
-- may be placed at a specific position in the result
-- buffer.
--
-- ----------------------------------------------------------------------------
PROCEDURE IntToStr (
InputInt : IN INTEGER ;
ResultStr : INOUT STRING ( 1 TO 256) ;
AppendPos : INOUT NATURAL
) IS
-- Look-up table. Given an int, we can get the character.
TYPE integer_table_type IS ARRAY (0 TO 9) OF CHARACTER ;
CONSTANT integer_table : integer_table_type :=
('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ;
-- Local variables used in this function.
VARIABLE inpVal : INTEGER := inputInt ;
VARIABLE divisor : INTEGER := 10 ;
VARIABLE tmpStrIndex : INTEGER := 1 ;
VARIABLE tmpStr : STRING ( 1 TO 256 ) ;
BEGIN
IF ( inpVal = 0 ) THEN
tmpStr(tmpStrIndex) := integer_table ( 0 ) ;
tmpStrIndex := tmpStrIndex + 1 ;
ELSE
WHILE ( inpVal > 0 ) LOOP
tmpStr(tmpStrIndex) := integer_table (inpVal mod divisor);
tmpStrIndex := tmpStrIndex + 1 ;
inpVal := inpVal / divisor ;
END LOOP ;
END IF ;
IF (appendPos /= 1 ) THEN
resultStr(appendPos) := ',' ;
appendPos := appendPos + 1 ;
END IF ;
FOR i IN tmpStrIndex-1 DOWNTO 1 LOOP
resultStr(appendPos) := tmpStr(i) ;
appendPos := appendPos + 1 ;
END LOOP ;
END IntToStr ;
-- ----------------------------------------------------------------------------
TYPE CheckType IS (
SetupCheck,
HoldCheck,
RecoveryCheck,
RemovalCheck,
PulseWidCheck,
PeriodCheck
);
TYPE CheckInfoType IS RECORD
Violation : BOOLEAN;
CheckKind : CheckType;
ObsTime : TIME;
ExpTime : TIME;
DetTime : TIME;
State : X01;
END RECORD;
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
TYPE HiLoStrType IS ARRAY (std_ulogic RANGE 'X' TO '1') OF STRING(1 TO 4);
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
CONSTANT HiLoStr : HiLoStrType := (" X ", " Low", "High" );
TYPE EdgeSymbolMatchType IS ARRAY (X01,X01,VitalEdgeSymbolType) OF BOOLEAN;
-- last value, present value, edge symbol
CONSTANT EdgeSymbolMatch : EdgeSymbolMatchType :=
(
'X' =>
( 'X'=>( OTHERS => FALSE),
'0'=>('N'|'F'|'v'|'E'|'D'|'*' => TRUE, OTHERS => FALSE ),
'1'=>('P'|'R'|'^'|'E'|'A'|'*' => TRUE, OTHERS => FALSE )
),
'0' =>
( 'X'=>( 'r'|'p'|'R'|'A'|'*' => TRUE, OTHERS => FALSE ),
'0'=>( OTHERS => FALSE ),
'1'=>( '/'|'P'|'p'|'R'|'*' => TRUE, OTHERS => FALSE )
),
'1' =>
( 'X'=>( 'f'|'n'|'F'|'D'|'*' => TRUE, OTHERS => FALSE ),
'0'=>( '\'|'N'|'n'|'F'|'*' => TRUE, OTHERS => FALSE ),
'1'=>( OTHERS => FALSE )
)
);
-- ----------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1, t2 : IN TIME
) RETURN TIME IS
BEGIN
IF (t1 < t2) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ----------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1, t2 : IN TIME
) RETURN TIME IS
BEGIN
IF (t1 < t2) THEN RETURN (t2); ELSE RETURN (t1); END IF;
END Maximum;
-- ----------------------------------------------------------------------------
-- FUNCTION: VitalMemoryCalcDelay
-- Description: Select Transition dependent Delay.
-- Used internally by VitalMemorySelectDelay.
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryCalcDelay (
CONSTANT NewVal : IN STD_ULOGIC := 'X';
CONSTANT OldVal : IN STD_ULOGIC := 'X';
CONSTANT Delay : IN VitalDelayType01ZX
) RETURN VitalMemoryDelayType IS
VARIABLE Result : VitalMemoryDelayType;
BEGIN
CASE Oldval IS
WHEN '0' | 'L' =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' =>
Result.PropDelay := Delay(tr01);
WHEN 'Z' =>
Result.PropDelay := Delay(tr0Z);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr01), Delay(tr0Z));
END CASE;
Result.OutputRetainDelay := Delay(tr0X);
WHEN '1' | 'H' =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' =>
Result.PropDelay := Delay(tr01);
WHEN 'Z' =>
Result.PropDelay := Delay(tr1Z);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr10), Delay(tr1Z));
END CASE;
Result.OutputRetainDelay := Delay(tr1X);
WHEN 'Z' =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Delay(trZ0);
WHEN '1' | 'H' =>
Result.PropDelay := Delay(trZ1);
WHEN 'Z' =>
Result.PropDelay := Maximum(Delay(tr1Z), Delay(tr0Z));
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(trZ1), Delay(trZ0));
END CASE;
Result.OutputRetainDelay := Delay(trZX);
WHEN OTHERS =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Maximum(Delay(tr10), Delay(trZ0));
WHEN '1' | 'H' =>
Result.PropDelay := Maximum(Delay(tr01), Delay(trZ1));
WHEN 'Z' =>
Result.PropDelay := Maximum(Delay(tr1Z), Delay(tr0Z));
WHEN OTHERS =>
Result.PropDelay := Maximum(Delay(tr10), Delay(tr01));
END CASE;
Result.OutputRetainDelay := Minimum(Delay(tr1X), Delay(tr0X));
END CASE;
RETURN Result;
END VitalMemoryCalcDelay;
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryCalcDelay (
CONSTANT NewVal : IN STD_ULOGIC := 'X';
CONSTANT OldVal : IN STD_ULOGIC := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalMemoryDelayType IS
VARIABLE Result : VitalMemoryDelayType;
BEGIN
CASE Oldval IS
WHEN '0' | 'L' =>
CASE Newval IS
WHEN '0' | 'L' => Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' => Result.PropDelay := Delay(tr01);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr01), Delay(tr10));
END CASE;
Result.OutputRetainDelay := Delay(tr0Z);
WHEN '1' | 'H' =>
CASE Newval IS
WHEN '0' | 'L' => Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' => Result.PropDelay := Delay(tr01);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr10), Delay(tr01));
END CASE;
Result.OutputRetainDelay := Delay(tr1Z);
WHEN OTHERS =>
Result.PropDelay := Maximum(Delay(tr10),Delay(tr01));
Result.OutputRetainDelay := Minimum(Delay(tr1Z),Delay(tr0Z));
END CASE;
RETURN Result;
END VitalMemoryCalcDelay;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryUpdateInputChangeTime (
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
VARIABLE NumBitsPerSubword : INTEGER
) IS
VARIABLE LastInputValue : STD_LOGIC_VECTOR(InputSignal'LENGTH-1 downto 0);
VARIABLE InSignalNorm : STD_LOGIC_VECTOR(InputSignal'LENGTH-1 downto 0);
VARIABLE ChangeTimeNorm : VitalTimeArrayT(InputSignal'LENGTH-1 downto 0);
VARIABLE BitsPerWord : INTEGER;
BEGIN
LastInputValue := InputSignal'LAST_VALUE;
IF NumBitsPerSubword = DefaultNumBitsPerSubword THEN
BitsPerWord := InputSignal'LENGTH;
ELSE
BitsPerWord := NumBitsPerSubword;
END IF;
FOR i IN InSignalNorm'RANGE LOOP
IF (InSignalNorm(i) /= LastInputValue(i)) THEN
ChangeTimeNorm(i/BitsPerWord) := NOW - InputSignal'LAST_EVENT;
ELSE
ChangeTimeNorm(i/BitsPerWord) := InputChangeTimeArray(i);
END IF;
END LOOP;
FOR i IN ChangeTimeNorm'RANGE LOOP
ChangeTimeNorm(i) := ChangeTimeNorm(i/BitsPerword);
END LOOP;
InputChangeTimeArray := ChangeTimeNorm;
-- for debug purpose only
PrintInputChangeTime(InputChangeTimeArray);
END VitalMemoryUpdateInputChangeTime;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryUpdateInputChangeTime
-- Description: Time since previous event for each bit of the input
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryUpdateInputChangeTime (
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR
) IS
VARIABLE LastInputValue : STD_LOGIC_VECTOR(InputSignal'RANGE) ;
BEGIN
LastInputValue := InputSignal'LAST_VALUE;
FOR i IN InputSignal'RANGE LOOP
IF (InputSignal(i) /= LastInputValue(i)) THEN
InputChangeTimeArray(i) := NOW - InputSignal'LAST_EVENT;
END IF;
END LOOP;
-- for debug purpose only
PrintInputChangeTime(InputChangeTimeArray);
END VitalMemoryUpdateInputChangeTime;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryUpdateInputChangeTime (
VARIABLE InputChangeTime : INOUT TIME;
SIGNAL InputSignal : IN STD_ULOGIC
) IS
BEGIN
InputChangeTime := NOW - InputSignal'LAST_EVENT;
-- for debug purpose only
PrintInputChangeTime(InputChangeTime);
END VitalMemoryUpdateInputChangeTime;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryExpandPortFlag (
CONSTANT PortFlag : IN VitalPortFlagVectorType;
CONSTANT NumBitsPerSubword : IN INTEGER;
VARIABLE ExpandedPortFlag : OUT VitalPortFlagVectorType
) IS
VARIABLE PortFlagNorm : VitalPortFlagVectorType(
PortFlag'LENGTH-1 downto 0) := PortFlag;
VARIABLE ExpandedPortFlagNorm : VitalPortFlagVectorType(
ExpandedPortFlag'LENGTH-1 downto 0);
VARIABLE SubwordIndex : INTEGER;
BEGIN
FOR Index IN INTEGER RANGE 0 to ExpandedPortFlag'LENGTH-1 LOOP
IF NumBitsPerSubword = DefaultNumBitsPerSubword THEN
SubwordIndex := 0;
ELSE
SubwordIndex := Index / NumBitsPerSubword;
END IF;
ExpandedPortFlagNorm(Index) := PortFlagNorm(SubWordIndex);
END LOOP;
ExpandedPortFlag := ExpandedPortFlagNorm;
END VitalMemoryExpandPortFlag;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemorySelectDelay
-- Description : Select Propagation Delay. Used internally by
-- VitalMemoryAddPathDelay.
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType01ZX
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN
) IS
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE CurRetainDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0):=InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType01ZX(
PathDelayArray'LENGTH-1 downto 0):= PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0):= ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW) AND
(OutputRetainFlag = FALSE ));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
RetainDelay:=ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH - 1 ;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
(CurPropDelay,CurRetainDelay) :=
VitalMemoryCalcDelay (
NewValue, OldValue, DelayArrayNorm(DelayArrayIndex)
);
IF (OutputRetainFlag = FALSE) THEN
CurRetainDelay := TIME'HIGH;
END IF;
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := CurRetainDelay;
IF ArcType = CrossArc THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns)THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge)THEN
PropDelay := CurPropDelay;
RetainDelay := CurRetainDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge)THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
IF (OutputRetainFlag = TRUE) THEN
IF (CurRetainDelay < RetainDelay) THEN
RetainDelay := CurRetainDelay;
END IF;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay:= RetainDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos,InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType01Z
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN
) IS
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE CurRetainDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0):=InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType01Z(
PathDelayArray'LENGTH-1 downto 0):= PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0):=ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW) AND
(OutputRetainFlag = FALSE));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
RetainDelay:=ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH-1;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
(CurPropDelay, CurRetainDelay) :=
VitalMemoryCalcDelay (
NewValue, OldValue, DelayArrayNorm(DelayArrayIndex)
);
IF (OutputRetainFlag = FALSE) THEN
CurRetainDelay := TIME'HIGH;
END IF;
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := CurRetainDelay;
IF (ArcType = CrossArc) THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns) THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge) THEN
PropDelay := CurPropDelay;
RetainDelay := CurRetainDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge) THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
IF (OutputRetainFlag = TRUE) THEN
IF (CurRetainDelay < RetainDelay) THEN
RetainDelay := CurRetainDelay;
END IF;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay:= RetainDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos, InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType01
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE CurPathDelay : VitalMemoryDelayType;
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0):= InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType01(
PathDelayArray'LENGTH-1 downto 0):= PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0):=ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH-1;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
CurPropDelay:= VitalCalcDelay (NewValue,
OldValue, DelayArrayNorm(DelayArrayIndex));
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := TIME'HIGH;
IF (ArcType = CrossArc) THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns) THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge) THEN
PropDelay := CurPropDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge) THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos, InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0) := InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType(
PathDelayArray'LENGTH-1 downto 0) := PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0) := ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH-1;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
CurPropDelay := VitalCalcDelay (NewValue,
OldValue, DelayArrayNorm(DelayArrayIndex));
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := TIME'HIGH;
IF (ArcType = CrossArc) THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns) THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge) THEN
PropDelay := CurPropDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge) THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos, InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryInitPathDelay
-- Description: To initialize Schedule Data structure for an
-- output.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE OutputDataArray : IN STD_LOGIC_VECTOR;
CONSTANT NumBitsPerSubWord : IN INTEGER := DefaultNumBitsPerSubword
) IS
BEGIN
-- Initialize the ScheduleData Structure.
FOR i IN OutputDataArray'RANGE LOOP
ScheduleDataArray(i).OutputData := OutputDataArray(i);
ScheduleDataArray(i).PropDelay := TIME'HIGH;
ScheduleDataArray(i).OutputRetainDelay := TIME'HIGH;
ScheduleDataArray(i).InputAge := TIME'HIGH;
ScheduleDataArray(i).NumBitsPerSubWord := NumBitsPerSubWord;
-- Update LastOutputValue of Output if the Output has
-- already been scheduled.
IF ((ScheduleDataArray(i).ScheduleValue /= OutputDataArray(i)) AND
(ScheduleDataArray(i).ScheduleTime <= NOW)) THEN
ScheduleDataArray(i).LastOutputValue
:= ScheduleDataArray(i).ScheduleValue;
END IF;
END LOOP;
-- for debug purpose
DebugMsg1;
PrintScheduleDataArray(ScheduleDataArray);
END VitalMemoryInitPathDelay;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
VARIABLE OutputData : IN STD_ULOGIC
) IS
VARIABLE ScheduledataArray: VitalMemoryScheduleDataVectorType
(0 downto 0);
VARIABLE OutputDataArray : STD_LOGIC_VECTOR(0 downto 0);
BEGIN
ScheduledataArray(0) := ScheduleData;
OutputDataArray(0) := OutputData;
VitalMemoryInitPathDelay (
ScheduleDataArray => ScheduleDataArray,
OutputDataArray => OutputDataArray,
NumBitsPerSubWord => DefaultNumBitsPerSubword
);
-- for debug purpose
DebugMsg1;
PrintScheduleDataArray( ScheduleDataArray);
END VitalMemoryInitPathDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryAddPathDelay
-- Description: Declare a path for one scalar/vector input to
-- the output for which Schedule Data has been
-- initialized previously.
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- #1
-- DelayType - VitalMemoryDelayType
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #2
-- DelayType - VitalMemoryDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray
);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #3
-- DelayType - VitalMemoryDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR Mem400
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #4
-- DelayType - VitalMemoryDelayType
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE ScheduleDataArray : VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #5
-- DelayType - VitalMemoryDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #6
-- DelayType - VitalMemoryDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #7
-- DelayType - VitalMemoryDelayType01
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType01(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #8
-- DelayType - VitalMemoryDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #9
-- DelayType - VitalMemoryDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #10
-- DelayType - VitalMemoryDelayType01
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray: INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
)IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #11
-- DelayType - VitalMemoryDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #12
-- DelayType - VitalMemoryDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #13
-- DelayType - VitalMemoryDelayType01Z
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType01Z(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #14
-- DelayType - VitalMemoryDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #15
-- DelayType - VitalMemoryDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm : VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0);
VARIABLE PathConditionArrayExp : VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword := ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #16
-- DelayType - VitalMemoryDelayType01Z
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
NumBitsPerSubword := ScheduleDataArray(0).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray,
InputSignal,
NumBitsPerSubword
);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #17
-- DelayType - VitalMemoryDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray,
InputSignal,
NumBitsPerSubword
);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #18
-- DelayType - VitalMemoryDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0);
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword := ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #19
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType01ZX(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #20
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray :INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #21
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray :INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #22
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #23
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #24
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemorySchedulePathDelay
-- Description: Schedule Output after Propagation Delay selected
-- by checking all the paths added thru'
-- VitalMemoryAddPathDelay.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType:= VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
) IS
VARIABLE Age : TIME;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE Data : STD_ULOGIC;
BEGIN
IF (PortFlag.OutputDisable /= TRUE) THEN
FOR i IN ScheduleDataArray'RANGE LOOP
PropDelay := ScheduleDataArray(i).PropDelay;
RetainDelay := ScheduleDataArray(i).OutputRetainDelay;
NEXT WHEN PropDelay = TIME'HIGH;
Age := ScheduleDataArray(i).InputAge;
Data := ScheduleDataArray(i).OutputData;
IF (Age < RetainDelay and RetainDelay < PropDelay) THEN
OutSignal(i) <= TRANSPORT 'X' AFTER (RetainDelay - Age);
END IF;
IF (Age <= PropDelay) THEN
OutSignal(i)<= TRANSPORT OutputMap(Data)AFTER (PropDelay-Age);
ScheduleDataArray(i).ScheduleValue := Data;
ScheduleDataArray(i).ScheduleTime := NOW + PropDelay - Age;
END IF;
END LOOP;
END IF;
-- for debug purpose
PrintScheduleDataArray(ScheduleDataArray);
-- for debug purpose
ScheduleDebugMsg;
END VitalMemorySchedulePathDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemorySchedulePathDelay
-- Description: Schedule Output after Propagation Delay selected
-- by checking all the paths added thru'
-- VitalMemoryAddPathDelay.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PortFlag : IN VitalPortFlagVectorType;
CONSTANT OutputMap : IN VitalOutputMapType:= VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
) IS
VARIABLE Age : TIME;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE Data : STD_ULOGIC;
VARIABLE ExpandedPortFlag :
VitalPortFlagVectorType(ScheduleDataArray'RANGE);
VARIABLE NumBitsPerSubword : INTEGER;
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
VitalMemoryExpandPortFlag( PortFlag, NumBitsPerSubword, ExpandedPortFlag );
FOR i IN ScheduleDataArray'RANGE LOOP
NEXT WHEN ExpandedPortFlag(i).OutputDisable = TRUE;
PropDelay := ScheduleDataArray(i).PropDelay;
RetainDelay := ScheduleDataArray(i).OutputRetainDelay;
NEXT WHEN PropDelay = TIME'HIGH;
Age := ScheduleDataArray(i).InputAge;
Data := ScheduleDataArray(i).OutputData;
IF (Age < RetainDelay and RetainDelay < PropDelay) THEN
OutSignal(i) <= TRANSPORT 'X' AFTER (RetainDelay - Age);
END IF;
IF (Age <= PropDelay) THEN
OutSignal(i)<= TRANSPORT OutputMap(Data)AFTER (PropDelay-Age);
ScheduleDataArray(i).ScheduleValue := Data;
ScheduleDataArray(i).ScheduleTime := NOW + PropDelay - Age;
END IF;
END LOOP;
-- for debug purpose
PrintScheduleDataArray(ScheduleDataArray);
-- for debug purpose
ScheduleDebugMsg;
END VitalMemorySchedulePathDelay;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT STD_ULOGIC;
CONSTANT OutputSignalName: IN STRING :="";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType
) IS
VARIABLE Age : TIME;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE Data : STD_ULOGIC;
VARIABLE ScheduleDataArray : VitalMemoryScheduleDataVectorType (0 downto 0);
BEGIN
IF (PortFlag.OutputDisable /= TRUE) THEN
ScheduledataArray(0) := ScheduleData;
PropDelay := ScheduleDataArray(0).PropDelay;
RetainDelay := ScheduleDataArray(0).OutputRetainDelay;
Age := ScheduleDataArray(0).InputAge;
Data := ScheduleDataArray(0).OutputData;
IF (Age < RetainDelay and RetainDelay < PropDelay) THEN
OutSignal <= TRANSPORT 'X' AFTER (RetainDelay - Age);
END IF;
IF (Age <= PropDelay and PropDelay /= TIME'HIGH) THEN
OutSignal <= TRANSPORT OutputMap(Data) AFTER (PropDelay - Age);
ScheduleDataArray(0).ScheduleValue := Data;
ScheduleDataArray(0).ScheduleTime := NOW + PropDelay - Age;
END IF;
END IF;
-- for debug purpose
PrintScheduleDataArray(ScheduleDataArray);
-- for debug purpose
ScheduleDebugMsg;
END VitalMemorySchedulePathDelay;
-- ----------------------------------------------------------------------------
-- Procedure : InternalTimingCheck
-- ----------------------------------------------------------------------------
PROCEDURE InternalTimingCheck (
CONSTANT TestSignal : IN std_ulogic;
CONSTANT RefSignal : IN std_ulogic;
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
VARIABLE RefTime : IN TIME;
VARIABLE RefEdge : IN BOOLEAN;
VARIABLE TestTime : IN TIME;
VARIABLE TestEvent : IN BOOLEAN;
VARIABLE SetupEn : INOUT BOOLEAN;
VARIABLE HoldEn : INOUT BOOLEAN;
VARIABLE CheckInfo : INOUT CheckInfoType;
CONSTANT MsgOn : IN BOOLEAN
) IS
VARIABLE bias : TIME;
VARIABLE actualObsTime : TIME;
VARIABLE BC : TIME;
VARIABLE Message :LINE;
BEGIN
-- Check SETUP constraint
IF (RefEdge) THEN
IF (SetupEn) THEN
CheckInfo.ObsTime := RefTime - TestTime;
CheckInfo.State := To_X01(TestSignal);
CASE CheckInfo.State IS
WHEN '0' =>
CheckInfo.ExpTime := SetupLow;
-- start of new code IR245-246
BC := HoldHigh;
-- end of new code IR245-246
WHEN '1' =>
CheckInfo.ExpTime := SetupHigh;
-- start of new code IR245-246
BC := HoldLow;
-- end of new code IR245-246
WHEN 'X' =>
CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow);
-- start of new code IR245-246
BC := Maximum(HoldHigh,HoldLow);
-- end of new code IR245-246
END CASE;
-- added the second condition for IR 245-246
CheckInfo.Violation :=
((CheckInfo.ObsTime < CheckInfo.ExpTime)
AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns))));
-- start of new code IR245-246
IF (CheckInfo.ExpTime = 0 ns) THEN
CheckInfo.CheckKind := HoldCheck;
ELSE
CheckInfo.CheckKind := SetupCheck;
END IF;
-- end of new code IR245-246
SetupEn := FALSE;
ELSE
CheckInfo.Violation := FALSE;
END IF;
-- Check HOLD constraint
ELSIF (TestEvent) THEN
IF HoldEn THEN
CheckInfo.ObsTime := TestTime - RefTime;
CheckInfo.State := To_X01(TestSignal);
CASE CheckInfo.State IS
WHEN '0' =>
CheckInfo.ExpTime := HoldHigh;
-- new code for unnamed IR
CheckInfo.State := '1';
-- start of new code IR245-246
BC := SetupLow;
-- end of new code IR245-246
WHEN '1' =>
CheckInfo.ExpTime := HoldLow;
-- new code for unnamed IR
CheckInfo.State := '0';
-- start of new code IR245-246
BC := SetupHigh;
-- end of new code IR245-246
WHEN 'X' =>
CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow);
-- start of new code IR245-246
BC := Maximum(SetupHigh,SetupLow);
-- end of new code IR245-246
END CASE;
-- added the second condition for IR 245-246
CheckInfo.Violation :=
((CheckInfo.ObsTime < CheckInfo.ExpTime)
AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns))));
-- start of new code IR245-246
IF (CheckInfo.ExpTime = 0 ns) THEN
CheckInfo.CheckKind := SetupCheck;
ELSE
CheckInfo.CheckKind := HoldCheck;
END IF;
-- end of new code IR245-246
HoldEn := NOT CheckInfo.Violation;
ELSE
CheckInfo.Violation := FALSE;
END IF;
ELSE
CheckInfo.Violation := FALSE;
END IF;
-- Adjust report values to account for internal model delays
-- Note: TestDelay, RefDelay, TestTime, RefTime are non-negative
-- Note: bias may be negative or positive
IF MsgOn AND CheckInfo.Violation THEN
-- modified the code for correct reporting of violation in case of
-- order of signals being reversed because of internal delays
-- new variable
actualObsTime := (TestTime-TestDelay)-(RefTime-RefDelay);
bias := TestDelay - RefDelay;
IF (actualObsTime < 0 ns) THEN -- It should be a setup check
IF ( CheckInfo.CheckKind = HoldCheck) THEN
CheckInfo.CheckKind := SetupCheck;
CASE CheckInfo.State IS
WHEN '0' => CheckInfo.ExpTime := SetupLow;
WHEN '1' => CheckInfo.ExpTime := SetupHigh;
WHEN 'X' => CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow);
END CASE;
END IF;
CheckInfo.ObsTime := -actualObsTime;
CheckInfo.ExpTime := CheckInfo.ExpTime + bias;
CheckInfo.DetTime := RefTime - RefDelay;
ELSE -- It should be a hold check
IF (CheckInfo.CheckKind = SetupCheck) THEN
CheckInfo.CheckKind := HoldCheck;
CASE CheckInfo.State IS
WHEN '0' =>
CheckInfo.ExpTime := HoldHigh;
CheckInfo.State := '1';
WHEN '1' =>
CheckInfo.ExpTime := HoldLow;
CheckInfo.State := '0';
WHEN 'X' =>
CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow);
END CASE;
END IF;
CheckInfo.ObsTime := actualObsTime;
CheckInfo.ExpTime := CheckInfo.ExpTime - bias;
CheckInfo.DetTime := TestTime - TestDelay;
END IF;
END IF;
END InternalTimingCheck;
-- ----------------------------------------------------------------------------
-- Setup and Hold Time Check Routine
-- ----------------------------------------------------------------------------
PROCEDURE TimingArrayIndex (
SIGNAL InputSignal : IN Std_logic_vector;
CONSTANT ArrayIndexNorm : IN INTEGER;
VARIABLE Index : OUT INTEGER
) IS
BEGIN
IF (InputSignal'LEFT > InputSignal'RIGHT) THEN
Index := ArrayIndexNorm + InputSignal'RIGHT;
ELSE
Index := InputSignal'RIGHT - ArrayIndexNorm;
END IF;
END TimingArrayIndex;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
IF (NOT CheckInfo.Violation) THEN
RETURN;
END IF;
Write ( Message, HeaderMsg );
CASE CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN RecoveryCheck => Write ( Message, STRING'(" RECOVERY ") );
WHEN RemovalCheck => Write ( Message, STRING'(" REMOVAL ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END VitalMemoryReportViolation;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT TestArrayIndex : IN INTEGER;
CONSTANT RefArrayIndex : IN INTEGER;
SIGNAL TestSignal : IN std_logic_vector;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
VARIABLE i, j : INTEGER;
BEGIN
IF (NOT CheckInfo.Violation) THEN
RETURN;
END IF;
Write ( Message, HeaderMsg );
CASE CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
WHEN OTHERS => Write ( Message, STRING'(" UNKNOWN ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
TimingArrayIndex(TestSignal, TestArrayIndex, i);
CASE MsgFormat IS
WHEN Scalar =>
NULL;
WHEN VectorEnum =>
Write ( Message, '_');
Write ( Message, i);
WHEN Vector =>
Write ( Message, '(');
Write ( Message, i);
Write ( Message, ')');
END CASE;
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
IF(RefSignal'LENGTH > 0) THEN
TimingArrayIndex(RefSignal, RefArrayIndex, j);
CASE MsgFormat IS
WHEN Scalar =>
NULL;
WHEN VectorEnum =>
Write ( Message, '_');
Write ( Message, j);
WHEN Vector =>
Write ( Message, '(');
Write ( Message, j);
Write ( Message, ')');
END CASE;
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END VitalMemoryReportViolation;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT TestArrayIndex : IN INTEGER;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
IF (NOT CheckInfo.Violation) THEN
RETURN;
END IF;
Write ( Message, HeaderMsg );
CASE CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
WHEN OTHERS => Write ( Message, STRING'(" UNKNOWN ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
CASE MsgFormat IS
WHEN Scalar =>
NULL;
WHEN VectorEnum =>
Write ( Message, '_');
Write ( Message, TestArrayIndex);
WHEN Vector =>
Write ( Message, '(');
Write ( Message, TestArrayIndex);
Write ( Message, ')');
END CASE;
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END VitalMemoryReportViolation;
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryTimingDataInit
RETURN VitalMemoryTimingDataType IS
BEGIN
RETURN (FALSE, 'X', 0 ns, FALSE, 'X', 0 ns, FALSE,
NULL, NULL, NULL, NULL, NULL, NULL);
END;
-- ----------------------------------------------------------------------------
-- Procedure: VitalSetupHoldCheck
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayType;
CONSTANT SetupLow : IN VitalDelayType;
CONSTANT HoldHigh : IN VitalDelayType;
CONSTANT HoldLow : IN VitalDelayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE CheckEnScalar : BOOLEAN := FALSE;
VARIABLE ViolationInt : X01ArrayT(CheckEnabled'RANGE);
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : BOOLEAN;
VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay);
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLast := To_X01(TestSignal);
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF (RefEdge) THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
TimingData.SetupEn := TimingData.SetupEn AND EnableSetupOnRef;
TimingData.HoldEn := EnableHoldOnRef;
END IF;
-- Detect test (data) changes and record the time of the last change
TestEvent := TimingData.TestLast /= To_X01Z(TestSignal);
TimingData.TestLast := To_X01Z(TestSignal);
IF TestEvent THEN
TimingData.SetupEn := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEn := TimingData.HoldEn AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTime := NOW;
END IF;
FOR i IN CheckEnabled'RANGE LOOP
IF CheckEnabled(i) = TRUE THEN
CheckEnScalar := TRUE;
END IF;
ViolationInt(i) := '0';
END LOOP;
IF (CheckEnScalar) THEN
InternalTimingCheck (
TestSignal => TestSignal,
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh,
SetupLow => SetupLow,
HoldHigh => HoldHigh,
HoldLow => HoldLow,
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTime,
TestEvent => TestEvent,
SetupEn => TimingData.SetupEn,
HoldEn => TimingData.HoldEn,
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName,
HeaderMsg, CheckInfo, MsgSeverity );
END IF;
IF (XOn) THEN
FOR i IN CheckEnabled'RANGE LOOP
IF CheckEnabled(i) = TRUE THEN
ViolationInt(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END IF;
Violation := ViolationInt;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF (RefEdge) THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
FOR i IN TestSignal'RANGE LOOP
TimingData.SetupEnA(i)
:= TimingData.SetupEnA(i) AND EnableSetupOnRef;
TimingData.HoldEnA(i) := EnableHoldOnRef;
END LOOP;
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTimeA(i) := NOW;
--TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
FOR i IN TestSignal'RANGE LOOP
Violation(i) := '0';
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelay(i));
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh(i),
SetupLow => SetupLow(i),
HoldHigh => HoldHigh(i),
HoldLow => HoldLow(i),
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i ,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
Violation(i) := 'X';
END IF;
END IF;
END IF;
END LOOP;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE ViolationInt : X01ArrayT(TestSignal'RANGE);
VARIABLE ViolationIntNorm: X01ArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE ViolationNorm : X01ArrayT(Violation'LENGTH-1 downto 0);
VARIABLE CheckEnInt : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE CheckEnIntNorm : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE CheckEnScalar : BOOLEAN := FALSE; --Mem IR 401
VARIABLE CheckEnabledNorm: VitalBoolArrayT(CheckEnabled'LENGTH-1 downto 0);
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF RefEdge THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
FOR i IN TestSignal'RANGE LOOP
TimingData.SetupEnA(i)
:= TimingData.SetupEnA(i) AND EnableSetupOnRef;
TimingData.HoldEnA(i) := EnableHoldOnRef;
END LOOP;
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTimeA(i) := NOW;
--TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
IF ArcType = CrossArc THEN
CheckEnScalar := FALSE;
FOR i IN CheckEnabled'RANGE LOOP
IF CheckEnabled(i) = TRUE THEN
CheckEnScalar := TRUE;
END IF;
END LOOP;
FOR i IN CheckEnInt'RANGE LOOP
CheckEnInt(i) := CheckEnScalar;
END LOOP;
ELSE
FOR i IN CheckEnIntNorm'RANGE LOOP
CheckEnIntNorm(i) := CheckEnabledNorm(i / NumBitsPerSubWord );
END LOOP;
CheckEnInt := CheckEnIntNorm;
END IF;
FOR i IN TestSignal'RANGE LOOP
ViolationInt(i) := '0';
IF (CheckEnInt(i)) THEN
TestDly := Maximum(0 ns, TestDelay(i));
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh(i),
SetupLow => SetupLow(i),
HoldHigh => HoldHigh(i),
HoldLow => HoldLow(i),
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i ,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
ViolationInt(i) := 'X';
END IF;
END IF;
END IF;
END LOOP;
IF (ViolationInt'LENGTH = Violation'LENGTH) THEN
Violation := ViolationInt;
ELSE
ViolationIntNorm := ViolationInt;
FOR i IN ViolationNorm'RANGE LOOP
ViolationNorm(i) := '0';
END LOOP;
FOR i IN ViolationIntNorm'RANGE LOOP
IF (ViolationIntNorm(i) = 'X') THEN
ViolationNorm(i / NumBitsPerSubWord) := 'X';
END IF;
END LOOP;
Violation := ViolationNorm;
END IF;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArraytype;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0);
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME;
VARIABLE bias : TIME;
VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH;
VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH;
VARIABLE NumChecks : NATURAL;
VARIABLE ViolationTest : X01ArrayT(NumTestBits-1 downto 0);
VARIABLE ViolationRef : X01ArrayT(NumRefBits-1 downto 0);
VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0)
:= TestSignal;
VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0)
:= TestDelay;
VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0)
:= RefSignal;
VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0)
:= RefDelay;
VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0)
:= SetupHigh;
VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0)
:= SetupLow;
VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0)
:= HoldHigh;
VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0)
:= HoldLow;
VARIABLE RefBitLow : NATURAL;
VARIABLE RefBitHigh : NATURAL;
VARIABLE EnArrayIndex : NATURAL;
VARIABLE TimingArrayIndex: NATURAL;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0);
TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0);
TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0);
TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0);
IF (ArcType = CrossArc) THEN
NumChecks := RefSignal'LENGTH * TestSignal'LENGTH;
ELSE
NumChecks := TestSignal'LENGTH;
END IF;
TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
FOR i IN TestSignalNorm'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignalNorm(i));
END LOOP;
FOR i IN RefSignalNorm'RANGE LOOP
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
END LOOP;
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
FOR i IN RefSignalNorm'RANGE LOOP
RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i),
To_X01(RefSignalNorm(i)), RefTransition);
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
IF (RefEdge(i)) THEN
TimingData.RefTimeA(i) := NOW;
END IF;
END LOOP;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignalNorm'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i));
TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i));
IF (TestEvent(i)) THEN
TimingData.TestTimeA(i) := NOW;
END IF;
END LOOP;
FOR i IN ViolationTest'RANGE LOOP
ViolationTest(i) := '0';
END LOOP;
FOR i IN ViolationRef'RANGE LOOP
ViolationRef(i) := '0';
END LOOP;
FOR i IN TestSignalNorm'RANGE LOOP
IF (ArcType = CrossArc) THEN
FOR j IN RefSignalNorm'RANGE LOOP
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest;
TimingData.HoldEnA(i*NumRefBits+j)
:= TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest;
END IF;
IF (RefEdge(j)) THEN
--TimingData.HoldEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef;
TimingData.SetupEnA(i*NumRefBits+j)
:= TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef;
END IF;
END LOOP;
RefBitLow := 0;
RefBitHigh := NumRefBits-1;
TimingArrayIndex := i;
ELSE
IF ArcType = SubwordArc THEN
RefBitLow := i / NumBitsPerSubWord;
TimingArrayIndex := i + NumTestBits * RefBitLow;
ELSE
RefBitLow := i;
TimingArrayIndex := i;
END IF;
RefBitHigh := RefBitLow;
IF TestEvent(i) THEN
--TimingData.SetupEnA(i) := TRUE;
--IR252
TimingData.SetupEnA(i) := EnableSetupOnTest;
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest;
END IF;
IF RefEdge(RefBitLow) THEN
--TimingData.HoldEnA(i) := TRUE;
--IR252
TimingData.HoldEnA(i) := EnableHoldOnRef;
TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef;
END IF;
END IF;
EnArrayIndex := i;
FOR j IN RefBitLow to RefBitHigh LOOP
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelayNorm(i));
RefDly := Maximum(0 ns, RefDelayNorm(j));
InternalTimingCheck (
TestSignal => TestSignalNorm(i),
RefSignal => RefSignalNorm(j),
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHighNorm(TimingArrayIndex),
SetupLow => SetupLowNorm(TimingArrayIndex),
HoldHigh => HoldHighNorm(TimingArrayIndex),
HoldLow => HoldLowNorm(TimingArrayIndex),
RefTime => TimingData.RefTimeA(j),
RefEdge => RefEdge(j),
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(EnArrayIndex),
HoldEn => TimingData.HoldEnA(EnArrayIndex),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF (CheckInfo.Violation) THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j,
TestSignal, RefSignal, HeaderMsg, CheckInfo,
MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
ViolationTest(i) := 'X';
ViolationRef(j) := 'X';
END IF;
END IF;
END IF;
TimingArrayIndex := TimingArrayIndex + NumRefBits;
EnArrayIndex := EnArrayIndex + NumRefBits;
END LOOP;
END LOOP;
IF (ArcType = CrossArc) THEN
Violation := ViolationRef;
ELSE
IF (Violation'LENGTH = ViolationRef'LENGTH) THEN
Violation := ViolationRef;
ELSE
Violation := ViolationTest;
END IF;
END IF;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArraytype;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0);
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME;
VARIABLE bias : TIME;
VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH;
VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH;
VARIABLE NumChecks : NATURAL;
VARIABLE ViolationTest : X01ArrayT(NumTestBits-1 downto 0);
VARIABLE ViolationRef : X01ArrayT(NumRefBits-1 downto 0);
VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0)
:= TestSignal;
VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0)
:= TestDelay;
VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0)
:= RefSignal;
VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0)
:= RefDelay;
VARIABLE CheckEnNorm : VitalBoolArrayT(NumRefBits-1 downto 0)
:= CheckEnabled;
VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0)
:= SetupHigh;
VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0)
:= SetupLow;
VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0)
:= HoldHigh;
VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0)
:= HoldLow;
VARIABLE RefBitLow : NATURAL;
VARIABLE RefBitHigh : NATURAL;
VARIABLE EnArrayIndex : NATURAL;
VARIABLE TimingArrayIndex: NATURAL;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0);
TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0);
TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0);
TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0);
IF ArcType = CrossArc THEN
NumChecks := RefSignal'LENGTH * TestSignal'LENGTH;
ELSE
NumChecks := TestSignal'LENGTH;
END IF;
TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
FOR i IN TestSignalNorm'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignalNorm(i));
END LOOP;
FOR i IN RefSignalNorm'RANGE LOOP
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
END LOOP;
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
FOR i IN RefSignalNorm'RANGE LOOP
RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i),
To_X01(RefSignalNorm(i)), RefTransition);
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
IF RefEdge(i) THEN
TimingData.RefTimeA(i) := NOW;
END IF;
END LOOP;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignalNorm'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i));
TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i));
IF TestEvent(i) THEN
TimingData.TestTimeA(i) := NOW;
END IF;
END LOOP;
FOR i IN ViolationTest'RANGE LOOP
ViolationTest(i) := '0';
END LOOP;
FOR i IN ViolationRef'RANGE LOOP
ViolationRef(i) := '0';
END LOOP;
FOR i IN TestSignalNorm'RANGE LOOP
IF (ArcType = CrossArc) THEN
FOR j IN RefSignalNorm'RANGE LOOP
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest;
TimingData.HoldEnA(i*NumRefBits+j)
:= TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest;
END IF;
IF (RefEdge(j)) THEN
--TimingData.HoldEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef;
TimingData.SetupEnA(i*NumRefBits+j)
:= TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef;
END IF;
END LOOP;
RefBitLow := 0;
RefBitHigh := NumRefBits-1;
TimingArrayIndex := i;
ELSE
IF (ArcType = SubwordArc) THEN
RefBitLow := i / NumBitsPerSubWord;
TimingArrayIndex := i + NumTestBits * RefBitLow;
ELSE
RefBitLow := i;
TimingArrayIndex := i;
END IF;
RefBitHigh := RefBitLow;
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i) := TRUE;
--IR252
TimingData.SetupEnA(i) := EnableSetupOnTest;
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest;
END IF;
IF (RefEdge(RefBitLow)) THEN
--TimingData.HoldEnA(i) := TRUE;
--IR252
TimingData.HoldEnA(i) := EnableHoldOnRef;
TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef;
END IF;
END IF;
EnArrayIndex := i;
FOR j IN RefBitLow to RefBitHigh LOOP
IF (CheckEnNorm(j)) THEN
TestDly := Maximum(0 ns, TestDelayNorm(i));
RefDly := Maximum(0 ns, RefDelayNorm(j));
InternalTimingCheck (
TestSignal => TestSignalNorm(i),
RefSignal => RefSignalNorm(j),
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHighNorm(TimingArrayIndex),
SetupLow => SetupLowNorm(TimingArrayIndex),
HoldHigh => HoldHighNorm(TimingArrayIndex),
HoldLow => HoldLowNorm(TimingArrayIndex),
RefTime => TimingData.RefTimeA(j),
RefEdge => RefEdge(j),
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(EnArrayIndex),
HoldEn => TimingData.HoldEnA(EnArrayIndex),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF (CheckInfo.Violation) THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j,
TestSignal, RefSignal, HeaderMsg, CheckInfo,
MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
ViolationTest(i) := 'X';
ViolationRef(j) := 'X';
END IF;
END IF;
END IF;
TimingArrayIndex := TimingArrayIndex + NumRefBits;
EnArrayIndex := EnArrayIndex + NumRefBits;
END LOOP;
END LOOP;
IF (ArcType = CrossArc) THEN
Violation := ViolationRef;
ELSE
IF (Violation'LENGTH = ViolationRef'LENGTH) THEN
Violation := ViolationRef;
ELSE
Violation := ViolationTest;
END IF;
END IF;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
-- scalar violations not needed
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF (RefEdge) THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
FOR i IN TestSignal'RANGE LOOP
TimingData.SetupEnA(i)
:= TimingData.SetupEnA(i) AND EnableSetupOnRef;
TimingData.HoldEnA(i) := EnableHoldOnRef;
END LOOP;
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTimeA(i) := NOW;
--TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
Violation := '0';
FOR i IN TestSignal'RANGE LOOP
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelay(i));
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh(i),
SetupLow => SetupLow(i),
HoldHigh => HoldHigh(i),
HoldLow => HoldLow(i),
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i ,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
Violation := 'X';
END IF;
END IF;
END IF;
END LOOP;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArraytype;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0);
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME;
VARIABLE bias : TIME;
VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH;
VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH;
VARIABLE NumChecks : NATURAL;
VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0)
:= TestSignal;
VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0)
:= TestDelay;
VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0)
:= RefSignal;
VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0)
:= RefDelay;
VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0)
:= SetupHigh;
VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0)
:= SetupLow;
VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0)
:= HoldHigh;
VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0)
:= HoldLow;
VARIABLE RefBitLow : NATURAL;
VARIABLE RefBitHigh : NATURAL;
VARIABLE EnArrayIndex : NATURAL;
VARIABLE TimingArrayIndex: NATURAL;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0);
TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0);
TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0);
TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0);
IF (ArcType = CrossArc) THEN
NumChecks := RefSignal'LENGTH * TestSignal'LENGTH;
ELSE
NumChecks := TestSignal'LENGTH;
END IF;
TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
FOR i IN TestSignalNorm'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignalNorm(i));
END LOOP;
FOR i IN RefSignalNorm'RANGE LOOP
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
END LOOP;
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
FOR i IN RefSignalNorm'RANGE LOOP
RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i),
To_X01(RefSignalNorm(i)), RefTransition);
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
IF (RefEdge(i)) THEN
TimingData.RefTimeA(i) := NOW;
END IF;
END LOOP;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignalNorm'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i));
TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i));
IF (TestEvent(i)) THEN
TimingData.TestTimeA(i) := NOW;
END IF;
END LOOP;
FOR i IN TestSignalNorm'RANGE LOOP
IF (ArcType = CrossArc) THEN
FOR j IN RefSignalNorm'RANGE LOOP
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest;
TimingData.HoldEnA(i*NumRefBits+j)
:= TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest;
END IF;
IF (RefEdge(j)) THEN
--TimingData.HoldEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef;
TimingData.SetupEnA(i*NumRefBits+j)
:= TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef;
END IF;
END LOOP;
RefBitLow := 0;
RefBitHigh := NumRefBits-1;
TimingArrayIndex := i;
ELSE
IF (ArcType = SubwordArc) THEN
RefBitLow := i / NumBitsPerSubWord;
TimingArrayIndex := i + NumTestBits * RefBitLow;
ELSE
RefBitLow := i;
TimingArrayIndex := i;
END IF;
RefBitHigh := RefBitLow;
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i) := TRUE;
--IR252
TimingData.SetupEnA(i) := EnableSetupOnTest;
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest;
END IF;
IF (RefEdge(RefBitLow)) THEN
--TimingData.HoldEnA(i) := TRUE;
--IR252
TimingData.HoldEnA(i) := EnableHoldOnRef;
TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef;
END IF;
END IF;
EnArrayIndex := i;
Violation := '0';
FOR j IN RefBitLow to RefBitHigh LOOP
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelayNorm(i));
RefDly := Maximum(0 ns, RefDelayNorm(j));
InternalTimingCheck (
TestSignal => TestSignalNorm(i),
RefSignal => RefSignalNorm(j),
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHighNorm(TimingArrayIndex),
SetupLow => SetupLowNorm(TimingArrayIndex),
HoldHigh => HoldHighNorm(TimingArrayIndex),
HoldLow => HoldLowNorm(TimingArrayIndex),
RefTime => TimingData.RefTimeA(j),
RefEdge => RefEdge(j),
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(EnArrayIndex),
HoldEn => TimingData.HoldEnA(EnArrayIndex),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF (CheckInfo.Violation) THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j,
TestSignal, RefSignal, HeaderMsg, CheckInfo,
MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
Violation := 'X';
END IF;
END IF;
END IF;
TimingArrayIndex := TimingArrayIndex + NumRefBits;
EnArrayIndex := EnArrayIndex + NumRefBits;
END LOOP;
END LOOP;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
CONSTANT Period : IN VitalDelayArraytype;
CONSTANT PulseWidthHigh : IN VitalDelayArraytype;
CONSTANT PulseWidthLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
) IS
VARIABLE TestDly : VitalDelayType;
VARIABLE CheckInfo : CheckInfoType;
VARIABLE PeriodObs : VitalDelayType;
VARIABLE PulseTest : BOOLEAN;
VARIABLE PeriodTest: BOOLEAN;
VARIABLE TestValue : X01;
BEGIN
-- Initialize for no violation
Violation := '0'; --MEM IR 402
FOR i IN TestSignal'RANGE LOOP
TestDly := Maximum(0 ns, TestDelay(i));
TestValue := To_X01(TestSignal(i));
IF (PeriodData(i).NotFirstFlag = FALSE) THEN
PeriodData(i).Rise := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Fall := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Last := TestValue;
PeriodData(i).NotFirstFlag := TRUE;
END IF;
-- Initialize for no violation
-- Violation := '0'; --Mem IR 402
-- No violation possible if no test signal change
NEXT WHEN (PeriodData(i).Last = TestValue);
-- record starting pulse times
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'P')) THEN
-- Compute period times, then record the High Rise Time
PeriodObs := NOW - PeriodData(i).Rise;
PeriodData(i).Rise := NOW;
PeriodTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'N')) THEN
-- Compute period times, then record the Low Fall Time
PeriodObs := NOW - PeriodData(i).Fall;
PeriodData(i).Fall := NOW;
PeriodTest := TRUE;
ELSE
PeriodTest := FALSE;
END IF;
-- do checks on pulse ends
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'p')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Fall;
CheckInfo.ExpTime := PulseWidthLow(i);
PulseTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'n')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Rise;
CheckInfo.ExpTime := PulseWidthHigh(i);
PulseTest := TRUE;
ELSE
PulseTest := FALSE;
END IF;
IF (PulseTest AND CheckEnabled) THEN
-- Verify Pulse Width [ignore 1st edge]
IF (CheckInfo.ObsTime < CheckInfo.ExpTime) THEN
IF (XOn) THEN
Violation := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PulseWidCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := PeriodData(i).Last;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
IF (PeriodTest AND CheckEnabled) THEN
-- Verify the Period [ignore 1st edge]
CheckInfo.ObsTime := PeriodObs;
CheckInfo.ExpTime := Period(i);
IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN
IF (XOn) THEN
Violation := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PeriodCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := TestValue;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
PeriodData(i).Last := TestValue;
END LOOP;
END VitalMemoryPeriodPulseCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
CONSTANT Period : IN VitalDelayArraytype;
CONSTANT PulseWidthHigh : IN VitalDelayArraytype;
CONSTANT PulseWidthLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
)IS
VARIABLE TestDly : VitalDelayType;
VARIABLE CheckInfo : CheckInfoType;
VARIABLE PeriodObs : VitalDelayType;
VARIABLE PulseTest : BOOLEAN;
VARIABLE PeriodTest: BOOLEAN;
VARIABLE TestValue : X01;
BEGIN
FOR i IN TestSignal'RANGE LOOP
TestDly := Maximum(0 ns, TestDelay(i));
TestValue := To_X01(TestSignal(i));
IF (PeriodData(i).NotFirstFlag = FALSE) THEN
PeriodData(i).Rise := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Fall := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Last := TestValue;
PeriodData(i).NotFirstFlag := TRUE;
END IF;
-- Initialize for no violation
Violation(i) := '0';
-- No violation possible if no test signal change
NEXT WHEN (PeriodData(i).Last = TestValue);
-- record starting pulse times
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'P')) THEN
-- Compute period times, then record the High Rise Time
PeriodObs := NOW - PeriodData(i).Rise;
PeriodData(i).Rise := NOW;
PeriodTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'N')) THEN
-- Compute period times, then record the Low Fall Time
PeriodObs := NOW - PeriodData(i).Fall;
PeriodData(i).Fall := NOW;
PeriodTest := TRUE;
ELSE
PeriodTest := FALSE;
END IF;
-- do checks on pulse ends
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'p')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Fall;
CheckInfo.ExpTime := PulseWidthLow(i);
PulseTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'n')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Rise;
CheckInfo.ExpTime := PulseWidthHigh(i);
PulseTest := TRUE;
ELSE
PulseTest := FALSE;
END IF;
IF (PulseTest AND CheckEnabled) THEN
-- Verify Pulse Width [ignore 1st edge]
IF (CheckInfo.ObsTime < CheckInfo.ExpTime) THEN
IF (XOn) THEN
Violation(i) := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PulseWidCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := PeriodData(i).Last;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
IF (PeriodTest AND CheckEnabled) THEN
-- Verify the Period [ignore 1st edge]
CheckInfo.ObsTime := PeriodObs;
CheckInfo.ExpTime := Period(i);
IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN
IF (XOn) THEN
Violation(i) := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PeriodCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := TestValue;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFOrmat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
PeriodData(i).Last := TestValue;
END LOOP;
END VitalMemoryPeriodPulseCheck;
-- ----------------------------------------------------------------------------
-- Functionality Section
-- ----------------------------------------------------------------------------
-- Look-up table. Given an int, we can get the 4-bit bit_vector.
TYPE HexToBitvTableType IS ARRAY (NATURAL RANGE <>) OF
std_logic_vector(3 DOWNTO 0) ;
CONSTANT HexToBitvTable : HexToBitvTableType (0 TO 15) :=
(
"0000", "0001", "0010", "0011",
"0100", "0101", "0110", "0111",
"1000", "1001", "1010", "1011",
"1100", "1101", "1110", "1111"
) ;
-- ----------------------------------------------------------------------------
-- Misc Utilities Local Utilities
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Procedure: IsSpace
-- Parameters: ch -- input character
-- Description: Returns TRUE or FALSE depending on the input character
-- being white space or not.
-- ----------------------------------------------------------------------------
FUNCTION IsSpace (ch : character)
RETURN boolean IS
BEGIN
RETURN ((ch = ' ') OR (ch = CR) OR (ch = HT) OR (ch = NUL));
END IsSpace;
-- ----------------------------------------------------------------------------
-- Procedure: LenOfString
-- Parameters: Str -- input string
-- Description: Returns the NATURAL length of the input string.
-- as terminated by the first NUL character.
-- ----------------------------------------------------------------------------
FUNCTION LenOfString (Str : STRING)
RETURN NATURAL IS
VARIABLE StrRight : NATURAL;
BEGIN
StrRight := Str'RIGHT;
FOR i IN Str'RANGE LOOP
IF (Str(i) = NUL) THEN
StrRight := i - 1;
EXIT;
END IF;
END LOOP;
RETURN (StrRight);
END LenOfString;
-- ----------------------------------------------------------------------------
-- Procedure: HexToInt
-- Parameters: Hex -- input character or string
-- Description: Converts input character or string interpreted as a
-- hexadecimal representation to integer value.
-- ----------------------------------------------------------------------------
FUNCTION HexToInt(Hex : CHARACTER) RETURN INTEGER IS
CONSTANT HexChars : STRING := "0123456789ABCDEFabcdef";
CONSTANT XHiChar : CHARACTER := 'X';
CONSTANT XLoChar : CHARACTER := 'x';
BEGIN
IF (Hex = XLoChar OR Hex = XHiChar) THEN
RETURN (23);
END IF;
FOR i IN 1 TO 16 LOOP
IF(Hex = HexChars(i)) THEN
RETURN (i-1);
END IF;
END LOOP;
FOR i IN 17 TO 22 LOOP
IF (Hex = HexChars(i)) THEN
RETURN (i-7);
END IF;
END LOOP;
ASSERT FALSE REPORT
"Invalid character received by HexToInt function"
SEVERITY WARNING;
RETURN (0);
END HexToInt;
-- ----------------------------------------------------------------------------
FUNCTION HexToInt (Hex : STRING) RETURN INTEGER IS
VARIABLE Value : INTEGER := 0;
VARIABLE Length : INTEGER;
BEGIN
Length := LenOfString(hex);
IF (Length > 8) THEN
ASSERT FALSE REPORT
"Invalid string length received by HexToInt function"
SEVERITY WARNING;
ELSE
FOR i IN 1 TO Length LOOP
Value := Value + HexToInt(Hex(i)) * 16 ** (Length - i);
END LOOP;
END IF;
RETURN (Value);
END HexToInt;
-- ----------------------------------------------------------------------------
-- Procedure: HexToBitv
-- Parameters: Hex -- Input hex string
-- Description: Converts input hex string to a std_logic_vector
-- ----------------------------------------------------------------------------
FUNCTION HexToBitv(
Hex : STRING
) RETURN std_logic_vector is
VARIABLE Index : INTEGER := 0 ;
VARIABLE ValHexToInt : INTEGER ;
VARIABLE BitsPerHex : INTEGER := 4 ; -- Denotes no. of bits per hex char.
VARIABLE HexLen : NATURAL := (BitsPerHex * LenOfString(Hex)) ;
VARIABLE TableVal : std_logic_vector(3 DOWNTO 0) ;
VARIABLE Result : std_logic_vector(HexLen-1 DOWNTO 0) ;
BEGIN
-- Assign 4-bit wide bit vector to result directly from a look-up table.
Index := 0 ;
WHILE ( Index < HexLen ) LOOP
ValHexToInt := HexToInt( Hex((HexLen - Index)/BitsPerHex ) );
IF ( ValHexToInt = 23 ) THEN
TableVal := "XXXX";
ELSE
-- Look up from the table.
TableVal := HexToBitvTable( ValHexToInt ) ;
END IF;
-- Assign now.
Result(Index+3 DOWNTO Index) := TableVal ;
-- Get ready for next block of 4-bits.
Index := Index + 4 ;
END LOOP ;
RETURN Result ;
END HexToBitv ;
-- ----------------------------------------------------------------------------
-- Procedure: BinToBitv
-- Parameters: Bin -- Input bin string
-- Description: Converts input bin string to a std_logic_vector
-- ----------------------------------------------------------------------------
FUNCTION BinToBitv(
Bin : STRING
) RETURN std_logic_vector is
VARIABLE Index : INTEGER := 0 ;
VARIABLE Length : NATURAL := LenOfString(Bin);
VARIABLE BitVal : std_ulogic;
VARIABLE Result : std_logic_vector(Length-1 DOWNTO 0) ;
BEGIN
Index := 0 ;
WHILE ( Index < Length ) LOOP
IF (Bin(Length-Index) = '0') THEN
BitVal := '0';
ELSIF (Bin(Length-Index) = '1') THEN
BitVal := '1';
ELSE
BitVal := 'X';
END IF ;
-- Assign now.
Result(Index) := BitVal ;
Index := Index + 1 ;
END LOOP ;
RETURN Result ;
END BinToBitv ;
-- ----------------------------------------------------------------------------
-- For Memory Table Modeling
-- ----------------------------------------------------------------------------
TYPE To_MemoryCharType IS ARRAY (VitalMemorySymbolType) OF CHARACTER;
CONSTANT To_MemoryChar : To_MemoryCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S',
'g', 'u', 'i', 'G', 'U', 'I',
'w', 's',
'c', 'l', 'd', 'e', 'C', 'L',
'M', 'm', 't' );
TYPE ValidMemoryTableInputType IS ARRAY (VitalMemorySymbolType) OF BOOLEAN;
CONSTANT ValidMemoryTableInput : ValidMemoryTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S',
TRUE,
-- 'g', 'u', 'i', 'G', 'U', 'I',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'w', 's',
FALSE, FALSE,
-- 'c', 'l', 'd', 'e', 'C', 'L',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'M', 'm', 't'
FALSE, FALSE, FALSE);
TYPE MemoryTableMatchType IS ARRAY (X01,X01,VitalMemorySymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT MemoryTableMatch : MemoryTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
-- g u i G U I
-- w s
-- c l d e, C L
-- m t
( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
-- g u i G U I
-- w s
-- c l d e, C L
-- m t
( FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
-- g u i G U I
-- w s
-- c l d e, C L
-- m t
( FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE)
)
);
-- ----------------------------------------------------------------------------
-- Error Message Types and Tables
-- ----------------------------------------------------------------------------
TYPE VitalMemoryErrorType IS (
ErrGoodAddr, -- 'g' Good address (no transition)
ErrUnknAddr, -- 'u' 'X' levels in address (no transition)
ErrInvaAddr, -- 'i' Invalid address (no transition)
ErrGoodTrAddr, -- 'G' Good address (with transition)
ErrUnknTrAddr, -- 'U' 'X' levels in address (with transition)
ErrInvaTrAddr, -- 'I' Invalid address (with transition)
ErrWrDatMem, -- 'w' Writing data to memory
ErrNoChgMem, -- 's' Retaining previous memory contents
ErrCrAllMem, -- 'c' Corrupting entire memory with 'X'
ErrCrWrdMem, -- 'l' Corrupting a word in memory with 'X'
ErrCrBitMem, -- 'd' Corrupting a single bit in memory with 'X'
ErrCrDatMem, -- 'e' Corrupting a word with 'X' based on data in
ErrCrAllSubMem,-- 'C' Corrupting a sub-word entire memory with 'X'
ErrCrWrdSubMem,-- 'L' Corrupting a sub-word in memory with 'X'
ErrCrBitSubMem,-- 'D' Corrupting a single bit of a memory sub-word with 'X'
ErrCrDatSubMem,-- 'E' Corrupting a sub-word with 'X' based on data in
ErrCrWrdOut, -- 'l' Corrupting data out with 'X'
ErrCrBitOut, -- 'd' Corrupting a single bit of data out with 'X'
ErrCrDatOut, -- 'e' Corrupting data out with 'X' based on data in
ErrCrWrdSubOut,-- 'L' Corrupting data out sub-word with 'X'
ErrCrBitSubOut,-- 'D' Corrupting a single bit of data out sub-word with 'X'
ErrCrDatSubOut,-- 'E' Corrupting data out sub-word with 'X' based on data in
ErrImplOut, -- 'M' Implicit read from memory to data out
ErrReadOut, -- 'm' Reading data from memory to data out
ErrAssgOut, -- 't' Transferring from data in to data out
ErrAsgXOut, -- 'X' Assigning unknown level to data out
ErrAsg0Out, -- '0' Assigning low level to data out
ErrAsg1Out, -- '1' Assigning high level to data out
ErrAsgZOut, -- 'Z' Assigning high impedence to data out
ErrAsgSOut, -- 'S' Keeping data out at steady value
ErrAsgXMem, -- 'X' Assigning unknown level to memory location
ErrAsg0Mem, -- '0' Assigning low level to memory location
ErrAsg1Mem, -- '1' Assigning high level to memory location
ErrAsgZMem, -- 'Z' Assigning high impedence to memory location
ErrDefMemAct, -- No memory table match, using default action
ErrInitMem, -- Initialize memory contents
ErrMcpWrCont, -- Memory cross port to same port write contention
ErrMcpCpCont, -- Memory cross port read/write data/memory contention
ErrMcpCpRead, -- Memory cross port read to same port
ErrMcpRdWrCo, -- Memory cross port read/write data only contention
ErrMcpCpWrCont,-- Memory cross port to cross port write contention
ErrUnknMemDo, -- Unknown memory action
ErrUnknDatDo, -- Unknown data action
ErrUnknSymbol, -- Illegal memory symbol
ErrLdIlgArg,
ErrLdAddrRng,
ErrLdMemInfo,
ErrLdFileEmpty,
ErrPrintString
);
TYPE VitalMemoryErrorSeverityType IS
ARRAY (VitalMemoryErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalMemoryErrorSeverity :
VitalMemoryErrorSeverityType := (
ErrGoodAddr => NOTE,
ErrUnknAddr => WARNING,
ErrInvaAddr => WARNING,
ErrGoodTrAddr => NOTE,
ErrUnknTrAddr => WARNING,
ErrInvaTrAddr => WARNING,
ErrWrDatMem => NOTE,
ErrNoChgMem => NOTE,
ErrCrAllMem => WARNING,
ErrCrWrdMem => WARNING,
ErrCrBitMem => WARNING,
ErrCrDatMem => WARNING,
ErrCrAllSubMem => WARNING,
ErrCrWrdSubMem => WARNING,
ErrCrBitSubMem => WARNING,
ErrCrDatSubMem => WARNING,
ErrCrWrdOut => WARNING,
ErrCrBitOut => WARNING,
ErrCrDatOut => WARNING,
ErrCrWrdSubOut => WARNING,
ErrCrBitSubOut => WARNING,
ErrCrDatSubOut => WARNING,
ErrImplOut => NOTE,
ErrReadOut => NOTE,
ErrAssgOut => NOTE,
ErrAsgXOut => NOTE,
ErrAsg0Out => NOTE,
ErrAsg1Out => NOTE,
ErrAsgZOut => NOTE,
ErrAsgSOut => NOTE,
ErrAsgXMem => NOTE,
ErrAsg0Mem => NOTE,
ErrAsg1Mem => NOTE,
ErrAsgZMem => NOTE,
ErrDefMemAct => NOTE,
ErrInitMem => NOTE,
ErrMcpWrCont => WARNING,
ErrMcpCpCont => WARNING,
ErrMcpCpRead => WARNING,
ErrMcpRdWrCo => WARNING,
ErrMcpCpWrCont => WARNING,
ErrUnknMemDo => ERROR,
ErrUnknDatDo => ERROR,
ErrUnknSymbol => ERROR,
ErrLdIlgArg => ERROR,
ErrLdAddrRng => WARNING,
ErrLdMemInfo => NOTE,
ErrLdFileEmpty => ERROR,
ErrPrintString => WARNING
);
-- ----------------------------------------------------------------------------
CONSTANT MsgGoodAddr : STRING
:= "Good address (no transition)";
CONSTANT MsgUnknAddr : STRING
:= "Unknown address (no transition)";
CONSTANT MsgInvaAddr : STRING
:= "Invalid address (no transition)";
CONSTANT MsgGoodTrAddr : STRING
:= "Good address (with transition)";
CONSTANT MsgUnknTrAddr : STRING
:= "Unknown address (with transition)";
CONSTANT MsgInvaTrAddr : STRING
:= "Invalid address (with transition)";
CONSTANT MsgNoChgMem : STRING
:= "Retaining previous memory contents";
CONSTANT MsgWrDatMem : STRING
:= "Writing data to memory";
CONSTANT MsgCrAllMem : STRING
:= "Corrupting entire memory with 'X'";
CONSTANT MsgCrWrdMem : STRING
:= "Corrupting a word in memory with 'X'";
CONSTANT MsgCrBitMem : STRING
:= "Corrupting a single bit in memory with 'X'";
CONSTANT MsgCrDatMem : STRING
:= "Corrupting a word with 'X' based on data in";
CONSTANT MsgCrAllSubMem : STRING
:= "Corrupting a sub-word entire memory with 'X'";
CONSTANT MsgCrWrdSubMem : STRING
:= "Corrupting a sub-word in memory with 'X'";
CONSTANT MsgCrBitSubMem : STRING
:= "Corrupting a single bit of a sub-word with 'X'";
CONSTANT MsgCrDatSubMem : STRING
:= "Corrupting a sub-word with 'X' based on data in";
CONSTANT MsgCrWrdOut : STRING
:= "Corrupting data out with 'X'";
CONSTANT MsgCrBitOut : STRING
:= "Corrupting a single bit of data out with 'X'";
CONSTANT MsgCrDatOut : STRING
:= "Corrupting data out with 'X' based on data in";
CONSTANT MsgCrWrdSubOut : STRING
:= "Corrupting data out sub-word with 'X'";
CONSTANT MsgCrBitSubOut : STRING
:= "Corrupting a single bit of data out sub-word with 'X'";
CONSTANT MsgCrDatSubOut : STRING
:= "Corrupting data out sub-word with 'X' based on data in";
CONSTANT MsgImplOut : STRING
:= "Implicit read from memory to data out";
CONSTANT MsgReadOut : STRING
:= "Reading data from memory to data out";
CONSTANT MsgAssgOut : STRING
:= "Transferring from data in to data out";
CONSTANT MsgAsgXOut : STRING
:= "Assigning unknown level to data out";
CONSTANT MsgAsg0Out : STRING
:= "Assigning low level to data out";
CONSTANT MsgAsg1Out : STRING
:= "Assigning high level to data out";
CONSTANT MsgAsgZOut : STRING
:= "Assigning high impedance to data out";
CONSTANT MsgAsgSOut : STRING
:= "Keeping data out at steady value";
CONSTANT MsgAsgXMem : STRING
:= "Assigning unknown level to memory location";
CONSTANT MsgAsg0Mem : STRING
:= "Assigning low level to memory location";
CONSTANT MsgAsg1Mem : STRING
:= "Assigning high level to memory location";
CONSTANT MsgAsgZMem : STRING
:= "Assigning high impedance to memory location";
CONSTANT MsgDefMemAct : STRING
:= "No memory table match, using default action";
CONSTANT MsgInitMem : STRING
:= "Initializing memory contents";
CONSTANT MsgMcpWrCont : STRING
:= "Same port write contention";
CONSTANT MsgMcpCpCont : STRING
:= "Cross port read/write data/memory contention";
CONSTANT MsgMcpCpRead : STRING
:= "Cross port read to same port";
CONSTANT MsgMcpRdWrCo : STRING
:= "Cross port read/write data only contention";
CONSTANT MsgMcpCpWrCont : STRING
:= "Cross port write contention";
CONSTANT MsgUnknMemDo : STRING
:= "Unknown memory action";
CONSTANT MsgUnknDatDo : STRING
:= "Unknown data action";
CONSTANT MsgUnknSymbol : STRING
:= "Illegal memory symbol";
CONSTANT MsgLdIlgArg : STRING
:= "Illegal bit arguments while loading memory.";
CONSTANT MsgLdMemInfo : STRING
:= "Loading data from the file into memory.";
CONSTANT MsgLdAddrRng : STRING
:= "Address out of range while loading memory.";
CONSTANT MsgLdFileEmpty : STRING
:= "Memory load file is empty.";
CONSTANT MsgPrintString : STRING
:= "";
CONSTANT MsgUnknown : STRING
:= "Unknown error message.";
CONSTANT MsgVMT : STRING
:= "VitalMemoryTable";
CONSTANT MsgVMV : STRING
:= "VitalMemoryViolation";
CONSTANT MsgVDM : STRING
:= "VitalDeclareMemory";
CONSTANT MsgVMCP : STRING
:= "VitalMemoryCrossPorts";
-- ----------------------------------------------------------------------------
-- LOCAL Utilities
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Procedure: MemoryMessage
-- Parameters: ErrorId -- Input error code
-- Description: This function looks up the input error code and returns
-- the string value of the associated message.
-- ----------------------------------------------------------------------------
FUNCTION MemoryMessage (
CONSTANT ErrorId : IN VitalMemoryErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrGoodAddr => RETURN MsgGoodAddr ;
WHEN ErrUnknAddr => RETURN MsgUnknAddr ;
WHEN ErrInvaAddr => RETURN MsgInvaAddr ;
WHEN ErrGoodTrAddr => RETURN MsgGoodTrAddr ;
WHEN ErrUnknTrAddr => RETURN MsgUnknTrAddr ;
WHEN ErrInvaTrAddr => RETURN MsgInvaTrAddr ;
WHEN ErrWrDatMem => RETURN MsgWrDatMem ;
WHEN ErrNoChgMem => RETURN MsgNoChgMem ;
WHEN ErrCrAllMem => RETURN MsgCrAllMem ;
WHEN ErrCrWrdMem => RETURN MsgCrWrdMem ;
WHEN ErrCrBitMem => RETURN MsgCrBitMem ;
WHEN ErrCrDatMem => RETURN MsgCrDatMem ;
WHEN ErrCrAllSubMem => RETURN MsgCrAllSubMem;
WHEN ErrCrWrdSubMem => RETURN MsgCrWrdSubMem;
WHEN ErrCrBitSubMem => RETURN MsgCrBitSubMem;
WHEN ErrCrDatSubMem => RETURN MsgCrDatSubMem;
WHEN ErrCrWrdOut => RETURN MsgCrWrdOut ;
WHEN ErrCrBitOut => RETURN MsgCrBitOut ;
WHEN ErrCrDatOut => RETURN MsgCrDatOut ;
WHEN ErrCrWrdSubOut => RETURN MsgCrWrdSubOut;
WHEN ErrCrBitSubOut => RETURN MsgCrBitSubOut;
WHEN ErrCrDatSubOut => RETURN MsgCrDatSubOut;
WHEN ErrImplOut => RETURN MsgImplOut ;
WHEN ErrReadOut => RETURN MsgReadOut ;
WHEN ErrAssgOut => RETURN MsgAssgOut ;
WHEN ErrAsgXOut => RETURN MsgAsgXOut ;
WHEN ErrAsg0Out => RETURN MsgAsg0Out ;
WHEN ErrAsg1Out => RETURN MsgAsg1Out ;
WHEN ErrAsgZOut => RETURN MsgAsgZOut ;
WHEN ErrAsgSOut => RETURN MsgAsgSOut ;
WHEN ErrAsgXMem => RETURN MsgAsgXMem ;
WHEN ErrAsg0Mem => RETURN MsgAsg0Mem ;
WHEN ErrAsg1Mem => RETURN MsgAsg1Mem ;
WHEN ErrAsgZMem => RETURN MsgAsgZMem ;
WHEN ErrDefMemAct => RETURN MsgDefMemAct ;
WHEN ErrInitMem => RETURN MsgInitMem ;
WHEN ErrMcpWrCont => RETURN MsgMcpWrCont ;
WHEN ErrMcpCpCont => RETURN MsgMcpCpCont ;
WHEN ErrMcpCpRead => RETURN MsgMcpCpRead ;
WHEN ErrMcpRdWrCo => RETURN MsgMcpRdWrCo ;
WHEN ErrMcpCpWrCont => RETURN MsgMcpCpWrCont;
WHEN ErrUnknMemDo => RETURN MsgUnknMemDo ;
WHEN ErrUnknDatDo => RETURN MsgUnknDatDo ;
WHEN ErrUnknSymbol => RETURN MsgUnknSymbol ;
WHEN ErrLdIlgArg => RETURN MsgLdIlgArg ;
WHEN ErrLdAddrRng => RETURN MsgLdAddrRng ;
WHEN ErrLdMemInfo => RETURN MsgLdMemInfo ;
WHEN ErrLdFileEmpty => RETURN MsgLdFileEmpty;
WHEN ErrPrintString => RETURN MsgPrintString;
WHEN OTHERS => RETURN MsgUnknown ;
END CASE;
END;
-- ----------------------------------------------------------------------------
-- Procedure: PrintMemoryMessage
-- Parameters: Routine -- String identifying the calling routine
-- ErrorId -- Input error code for message lookup
-- Info -- Output string or character
-- InfoStr -- Additional output string
-- Info1 -- Additional output integer
-- Info2 -- Additional output integer
-- Info3 -- Additional output integer
-- Description: This procedure prints out a memory status message
-- given the input error id and other status information.
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId)
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT Info1 : IN STRING;
CONSTANT Info2 : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info1 & " " & Info2
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT InfoStr : IN STRING;
CONSTANT Info1 : IN NATURAL
) IS
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IntToStr(Info1,TmpStr,TmpInt);
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT InfoStr : IN STRING;
CONSTANT Info1 : IN NATURAL;
CONSTANT Info2 : IN NATURAL
) IS
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IntToStr(Info1,TmpStr,TmpInt);
IntToStr(Info2,TmpStr,TmpInt);
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT InfoStr : IN STRING;
CONSTANT Info1 : IN NATURAL;
CONSTANT Info2 : IN NATURAL;
CONSTANT Info3 : IN NATURAL
) IS
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IntToStr(Info1,TmpStr,TmpInt);
IntToStr(Info2,TmpStr,TmpInt);
IntToStr(Info3,TmpStr,TmpInt);
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT Table : IN VitalMemoryTableType;
CONSTANT Index : IN INTEGER;
CONSTANT InfoStr : IN STRING
) IS
CONSTANT TableEntries : INTEGER := Table'LENGTH(1);
CONSTANT TableWidth : INTEGER := Table'LENGTH(2);
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IF (Index < 0 AND Index > TableEntries-1) THEN
ASSERT FALSE
REPORT Routine & ": Memory table search failure"
SEVERITY ERROR;
END IF;
ColLoop:
FOR i IN 0 TO TableWidth-1 LOOP
IF (i >= 64) THEN
TmpStr(TmpInt) := '.';
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := '.';
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := '.';
TmpInt := TmpInt + 1;
EXIT ColLoop;
END IF;
TmpStr(TmpInt) := ''';
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := To_MemoryChar(Table(Index,i));
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := ''';
TmpInt := TmpInt + 1;
IF (i < TableWidth-1) THEN
TmpStr(TmpInt) := ',';
TmpInt := TmpInt + 1;
END IF;
END LOOP;
ASSERT FALSE
REPORT Routine & ": Port=" & InfoStr & " TableRow=" & TmpStr
SEVERITY NOTE;
END;
-- ----------------------------------------------------------------------------
-- Procedure: DecodeAddress
-- Parameters: Address - Converted address.
-- AddrFlag - Flag to indicte address match
-- MemoryData - Information about memory characteristics
-- PrevAddressBus - Previous input address value
-- AddressBus - Input address value.
-- Description: This procedure is used for transforming a valid
-- address value to an integer in order to access memory.
-- It performs address bound checking as well.
-- Sets Address to -1 for unknowns
-- Sets Address to -2 for out of range
-- ----------------------------------------------------------------------------
PROCEDURE DecodeAddress (
VARIABLE Address : INOUT INTEGER;
VARIABLE AddrFlag : INOUT VitalMemorySymbolType;
VARIABLE MemoryData : IN VitalMemoryDataType;
CONSTANT PrevAddressBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector
) IS
VARIABLE Power : NATURAL;
VARIABLE AddrUnkn : BOOLEAN;
BEGIN
Power := 0;
AddrUnkn := FALSE;
-- It is assumed that always Address'LEFT represents the Most significant bit.
FOR i IN AddressBus'RANGE LOOP
Power := Power * 2;
IF (AddressBus(i) /= '1' AND AddressBus(i) /= '0') THEN
AddrUnkn := TRUE;
Power := 0;
EXIT;
ELSIF (AddressBus(i) = '1') THEN
Power := Power + 1;
END IF;
END LOOP;
Address := Power;
AddrFlag := 'g';
IF (AddrUnkn) THEN
AddrFlag := 'u'; -- unknown addr
Address := -1;
END IF;
IF ( Power > (MemoryData.NoOfWords - 1)) THEN
AddrFlag := 'i'; -- invalid addr
Address := -2;
END IF;
IF (PrevAddressBus /= AddressBus) THEN
CASE AddrFlag IS
WHEN 'g' => AddrFlag := 'G';
WHEN 'u' => AddrFlag := 'U';
WHEN 'i' => AddrFlag := 'I';
WHEN OTHERS =>
ASSERT FALSE REPORT
"DecodeAddress: Internal error. [AddrFlag]="
& To_MemoryChar(AddrFlag)
SEVERITY ERROR;
END CASE;
END IF;
END DecodeAddress;
-- ----------------------------------------------------------------------------
-- Procedure: DecodeData
-- Parameters: DataFlag - Flag to indicte data match
-- PrevDataInBus - Previous input data value
-- DataInBus - Input data value.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used for interpreting the input data
-- as a data flag for subsequent table matching.
-- ----------------------------------------------------------------------------
PROCEDURE DecodeData (
VARIABLE DataFlag : INOUT VitalMemorySymbolType;
CONSTANT PrevDataInBus : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL
) IS
VARIABLE DataUnkn : BOOLEAN := FALSE;
BEGIN
FOR i IN LowBit TO HighBit LOOP
IF DataInBus(i) /= '1' AND DataInBus(i) /= '0' THEN
DataUnkn := TRUE;
EXIT;
END IF;
END LOOP;
DataFlag := 'g';
IF (DataUnkn) THEN
DataFlag := 'u'; -- unknown addr
END IF;
IF (PrevDataInBus(HighBit DOWNTO LowBit) /=
DataInBus(HighBit DOWNTO LowBit)) THEN
CASE DataFlag IS
WHEN 'g' => DataFlag := 'G';
WHEN 'u' => DataFlag := 'U';
WHEN OTHERS =>
ASSERT FALSE REPORT
"DecodeData: Internal error. [DataFlag]="
& To_MemoryChar(DataFlag)
SEVERITY ERROR;
END CASE;
END IF;
END DecodeData;
-- ----------------------------------------------------------------------------
-- Procedure: WriteMemory
-- Parameters: MemoryPtr - Pointer to the memory array.
-- DataInBus - Input Data to be written.
-- Address - Address of the memory location.
-- BitPosition - Position of bit in memory location.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used to write to a memory location
-- on a bit/byte/word basis.
-- The high bit and low bit offset are used for byte write
-- operations.These parameters specify the data byte for write.
-- In the case of word write the complete memory word is used.
-- This procedure is overloaded for bit,byte and word write
-- memory operations.The number of parameters may vary.
-- ----------------------------------------------------------------------------
PROCEDURE WriteMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL
) IS
VARIABLE TmpData : std_logic_vector(DataInBus'LENGTH - 1 DOWNTO 0);
BEGIN
-- Address bound checking.
IF ( Address < 0 OR Address > (MemoryPtr.NoOfWords - 1)) THEN
PrintMemoryMessage ( "WriteMemory", ErrPrintString,
"Aborting write operation as address is out of range.") ;
RETURN;
END IF;
TmpData := To_UX01(DataInBus);
FOR i in LowBit to HighBit LOOP
MemoryPtr.MemoryArrayPtr(Address).all(i) := TmpData(i);
END LOOP;
END WriteMemory;
-- ----------------------------------------------------------------------------
PROCEDURE WriteMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT BitPosition : IN NATURAL
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := BitPosition;
LowBit := BitPosition;
WriteMemory (MemoryPtr, DataInBus, Address, HighBit, LowBit);
END WriteMemory;
-- ----------------------------------------------------------------------------
PROCEDURE WriteMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := MemoryPtr.NoOfBitsPerWord - 1;
LowBit := 0;
WriteMemory (MemoryPtr, DataInBus, Address, HighBit, LowBit);
END WriteMemory;
-- ----------------------------------------------------------------------------
-- Procedure: ReadMemory
-- Parameters: MemoryPtr - Pointer to the memory array.
-- DataOut - Output Data to be read in this.
-- Address - Address of the memory location.
-- BitPosition - Position of bit in memory location.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used to read from a memory location
-- on a bit/byte/word basis.
-- The high bit and low bit offset are used for byte write
-- operations.These parameters specify the data byte for
-- read.In the case of word write the complete memory word
-- is used.This procedure is overloaded for bit,byte and
-- word write memory operations.The number of parameters
-- may vary.
-- ----------------------------------------------------------------------------
PROCEDURE ReadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
VARIABLE DataOut : OUT std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL
) IS
VARIABLE DataOutTmp : std_logic_vector(MemoryPtr.NoOfBitsPerWord-1 DOWNTO 0);
VARIABLE length : NATURAL := (HighBit - LowBit + 1);
BEGIN
-- Address bound checking.
IF ( Address > (MemoryPtr.NoOfWords - 1)) THEN
PrintMemoryMessage (
"ReadMemory",ErrInvaAddr,
"[Address,NoOfWords]=",Address,MemoryPtr.NoOfWords
);
FOR i in LowBit to HighBit LOOP
DataOutTmp(i) := 'X';
END LOOP;
ELSE
FOR i in LowBit to HighBit LOOP
DataOutTmp(i) := MemoryPtr.MemoryArrayPtr (Address).all(i);
END LOOP;
END IF;
DataOut := DataOutTmp;
END ReadMemory;
-- ----------------------------------------------------------------------------
PROCEDURE ReadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
VARIABLE DataOut : OUT std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT BitPosition : IN NATURAL
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := BitPosition;
LowBit := BitPosition;
ReadMemory (MemoryPtr, DataOut, Address, HighBit, LowBit);
END ReadMemory;
-- ----------------------------------------------------------------------------
PROCEDURE ReadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
VARIABLE DataOut : OUT std_logic_vector;
CONSTANT Address : IN INTEGER
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := MemoryPtr.NoOfBitsPerWord - 1;
LowBit := 0;
ReadMemory (MemoryPtr, DataOut, Address, HighBit, LowBit);
END ReadMemory;
-- ----------------------------------------------------------------------------
-- Procedure: LoadMemory
-- Parameters: MemoryPtr - Pointer to the memory array.
-- FileName - Name of the output file.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used to load the contents of the memory
-- from a specified input file.
-- The high bit and low bit offset are used so that same task
-- can be used for all bit/byte/word write operations.
-- In the case of a bit write RAM the HighBit and LowBit have
-- the same value.
-- This procedure is overloaded for word write operations.
-- ----------------------------------------------------------------------------
PROCEDURE LoadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT FileName : IN STRING;
CONSTANT BinaryFile : IN BOOLEAN := FALSE
) IS
FILE Fptr : TEXT OPEN read_mode IS FileName;
VARIABLE OneLine : LINE;
VARIABLE Ignore : CHARACTER;
VARIABLE Index : NATURAL := 1;
VARIABLE LineNo : NATURAL := 0;
VARIABLE Address : INTEGER := 0;
VARIABLE DataInBus : std_logic_vector(MemoryPtr.NoOfBitsPerWord-1 DOWNTO 0);
VARIABLE AddrStr : STRING(1 TO 80) ;
VARIABLE DataInStr : STRING(1 TO 255) ;
BEGIN
IF (ENDFILE(fptr)) THEN
PrintMemoryMessage (MsgVDM, ErrLdFileEmpty,
"[FileName]="&FileName);
RETURN;
END IF ;
PrintMemoryMessage (
MsgVDM,ErrLdMemInfo, "[FileName]="&FileName
);
WHILE (NOT ENDFILE(fptr)) LOOP
ReadLine(Fptr, OneLine);
LineNo := LineNo + 1 ;
-- First ignoring leading spaces.
WHILE (OneLine'LENGTH /= 0 and IsSpace(OneLine(1))) LOOP
READ (OneLine, Ignore) ; -- Ignoring the space character.
END LOOP ;
-- Note that, by now oneline has been "stripped" of its leading spaces.
IF ( OneLine(1) = '@' ) THEN
READ (OneLine, Ignore); -- Ignore the '@' character and read the string.
-- Now strip off spaces, if any, between '@' and Address string.
WHILE (OneLine'LENGTH /= 0 and IsSpace(OneLine(1))) LOOP
READ (OneLine, Ignore) ; -- Ignoring the space character.
END LOOP ;
-- Now get the string which represents the address into string variable.
Index := 1;
WHILE (OneLine'LENGTH /= 0 AND (NOT(IsSpace(OneLine(1))))) LOOP
READ(OneLine, AddrStr(Index));
Index := Index + 1;
END LOOP ;
AddrStr(Index) := NUL;
-- Now convert the hex string into a hex integer
Address := HexToInt(AddrStr) ;
ELSE
IF ( LineNo /= 1 ) THEN
Address := Address + 1;
END IF;
END IF ;
IF ( Address > (MemoryPtr.NoOfWords - 1) ) THEN
PrintMemoryMessage (MsgVDM, ErrLdAddrRng,
"[Address,lineno]=", Address, LineNo) ;
EXIT ;
END IF;
-- Now strip off spaces, between Address string and DataInBus string.
WHILE (OneLine'LENGTH /= 0 AND IsSpace(OneLine(1))) LOOP
READ (OneLine, Ignore) ; -- Ignoring the space character.
END LOOP ;
Index := 1;
WHILE (OneLine'LENGTH /= 0 AND (NOT(IsSpace(OneLine(1))))) LOOP
READ(OneLine, DataInStr(Index));
Index := Index + 1;
END LOOP ;
DataInStr(Index) := NUL;
IF (BinaryFile) THEN
DataInBus := BinToBitv (DataInStr);
ELSE
DataInBus := HexToBitv (DataInStr);
END IF ;
WriteMemory (MemoryPtr, DataInBus, Address);
END LOOP ;
END LoadMemory;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryMatch
-- Parameters: Symbol - Symbol from memory table
-- TestFlag - Interpreted data or address symbol
-- In2 - input from VitalMemoryTable procedure
-- to memory table
-- In2LastValue - Previous value of input
-- Err - TRUE if symbol is not a valid input symbol
-- ReturnValue - TRUE if match occurred
-- Description: This procedure sets ReturnValue to true if in2 matches
-- symbol (from the memory table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the memory
-- table.
-- ----------------------------------------------------------------------------
PROCEDURE MemoryMatch (
CONSTANT Symbol : IN VitalMemorySymbolType;
CONSTANT In2 : IN std_ulogic;
CONSTANT In2LastValue : IN std_ulogic;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (NOT ValidMemoryTableInput(Symbol) ) THEN
PrintMemoryMessage(MsgVMT,ErrUnknSymbol,To_MemoryChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := MemoryTableMatch(To_X01(In2LastValue), To_X01(In2), Symbol);
Err := FALSE;
END IF;
END;
-- ----------------------------------------------------------------------------
PROCEDURE MemoryMatch (
CONSTANT Symbol : IN VitalMemorySymbolType;
CONSTANT TestFlag : IN VitalMemorySymbolType;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
Err := FALSE;
ReturnValue := FALSE;
CASE Symbol IS
WHEN 'g'|'u'|'i'|'G'|'U'|'I'|'-'|'*'|'S' =>
IF (Symbol = TestFlag) THEN
ReturnValue := TRUE;
ELSE
CASE Symbol IS
WHEN '-' =>
ReturnValue := TRUE;
Err := FALSE;
WHEN '*' =>
IF (TestFlag = 'G' OR
TestFlag = 'U' OR
TestFlag = 'I') THEN
ReturnValue := TRUE;
Err := FALSE;
END IF;
WHEN 'S' =>
IF (TestFlag = 'g' OR
TestFlag = 'u' OR
TestFlag = 'i') THEN
ReturnValue := TRUE;
Err := FALSE;
END IF;
WHEN OTHERS =>
ReturnValue := FALSE;
END CASE;
END IF;
WHEN OTHERS =>
Err := TRUE;
RETURN;
END CASE;
END;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryTableCorruptMask
-- Description: Compute memory and data corruption masks for memory table
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableCorruptMask (
VARIABLE CorruptMask : OUT std_logic_vector;
CONSTANT Action : IN VitalMemorySymbolType;
CONSTANT EnableIndex : IN INTEGER;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER
) IS
VARIABLE CorruptMaskTmp : std_logic_vector (CorruptMask'RANGE)
:= (OTHERS => '0');
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE HighBit : INTEGER;
VARIABLE LowBit : INTEGER;
BEGIN
CASE (Action) IS
WHEN 'c'|'l'|'e' =>
-- Corrupt whole word
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
WHEN 'd'|'C'|'L'|'D'|'E' =>
-- Process corruption below
WHEN OTHERS =>
-- No data or memory corruption
CorruptMaskTmp := (OTHERS => '0');
CorruptMask := CorruptMaskTmp;
RETURN;
END CASE;
IF (Action = 'd') THEN
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
END IF;
-- Remaining are subword cases 'C', 'L', 'D', 'E'
CorruptMaskTmp := (OTHERS => '0');
LowBit := 0;
HighBit := BitsPerSubWord-1;
SubWordLoop:
FOR i IN 0 TO BitsPerEnable-1 LOOP
IF (i = EnableIndex) THEN
FOR j IN HighBit TO LowBit LOOP
CorruptMaskTmp(j) := 'X';
END LOOP;
END IF;
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END LOOP;
CorruptMask := CorruptMaskTmp;
RETURN;
END;
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableCorruptMask (
VARIABLE CorruptMask : OUT std_logic_vector;
CONSTANT Action : IN VitalMemorySymbolType
) IS
VARIABLE CorruptMaskTmp : std_logic_vector (0 TO CorruptMask'LENGTH-1)
:= (OTHERS => '0');
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE HighBit : INTEGER;
VARIABLE LowBit : INTEGER;
BEGIN
CASE (Action) IS
WHEN 'c'|'l'|'d'|'e'|'C'|'L'|'D'|'E' =>
-- Corrupt whole word
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
WHEN OTHERS =>
-- No data or memory corruption
CorruptMaskTmp := (OTHERS => '0');
CorruptMask := CorruptMaskTmp;
RETURN;
END CASE;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryTableCorruptMask
-- Description: Compute memory and data corruption masks for violation table
-- ----------------------------------------------------------------------------
PROCEDURE ViolationTableCorruptMask (
VARIABLE CorruptMask : OUT std_logic_vector;
CONSTANT Action : IN VitalMemorySymbolType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN std_logic_vector;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT TableIndex : IN INTEGER;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER
) IS
VARIABLE CorruptMaskTmp : std_logic_vector (CorruptMask'RANGE)
:= (OTHERS => '0');
VARIABLE ViolMaskTmp : std_logic_vector (CorruptMask'RANGE)
:= (OTHERS => '0');
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE HighBit : INTEGER;
VARIABLE LowBit : INTEGER;
CONSTANT ViolFlagsSize : INTEGER := ViolationFlags'LENGTH;
CONSTANT ViolFlArySize : INTEGER := ViolationFlagsArray'LENGTH;
CONSTANT TableEntries : INTEGER := ViolationTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := ViolationTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
BEGIN
CASE (Action) IS
WHEN 'c'|'l'|'e' =>
-- Corrupt whole word
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
WHEN 'd'|'C'|'L'|'D'|'E' =>
-- Process corruption below
WHEN OTHERS =>
-- No data or memory corruption
CorruptMaskTmp := (OTHERS => '0');
CorruptMask := CorruptMaskTmp;
RETURN;
END CASE;
RowLoop: -- Check each element of the ViolationFlags
FOR j IN 0 TO ViolFlagsSize LOOP
IF (j = ViolFlagsSize) THEN
ViolFlAryPosn := 0;
RowLoop2: -- Check relevant elements of the ViolationFlagsArray
FOR k IN 0 TO MemActionNdx - ViolFlagsSize - 1 LOOP
IF (ViolationTable(TableIndex, k + ViolFlagsSize) = 'X') THEN
MaskLoop: -- Set the 'X' bits in the violation mask
FOR m IN INTEGER RANGE 0 TO CorruptMask'LENGTH-1 LOOP
IF (m <= ViolationSizesArray(k)-1) THEN
ViolMaskTmp(m) := ViolMaskTmp(m) XOR
ViolationFlagsArray(ViolFlAryPosn+m);
ELSE
EXIT MaskLoop;
END IF;
END LOOP;
END IF;
ViolFlAryPosn := ViolFlAryPosn + ViolationSizesArray(k);
END LOOP;
ELSE
IF (ViolationTable(TableIndex, j) = 'X') THEN
ViolMaskTmp(0) := ViolMaskTmp(0) XOR ViolationFlags(j);
END IF;
END IF;
END LOOP;
IF (Action = 'd') THEN
CorruptMask := ViolMaskTmp;
RETURN;
END IF;
-- Remaining are subword cases 'C', 'L', 'D', 'E'
CorruptMaskTmp := (OTHERS => '0');
LowBit := 0;
HighBit := BitsPerSubWord-1;
SubWordLoop:
FOR i IN 0 TO BitsPerEnable-1 LOOP
IF (ViolMaskTmp(i) = 'X') THEN
FOR j IN HighBit TO LowBit LOOP
CorruptMaskTmp(j) := 'X';
END LOOP;
END IF;
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END LOOP;
CorruptMask := CorruptMaskTmp;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryTableLookUp
-- Parameters: MemoryAction - Output memory action to be performed
-- DataAction - Output data action to be performed
-- PrevControls - Previous data in for edge detection
-- PrevEnableBus - Previous enables for edge detection
-- Controls - Agregate of scalar control lines
-- EnableBus - Concatenation of vector control lines
-- EnableIndex - Current slice of vector control lines
-- AddrFlag - Matching symbol from address decoding
-- DataFlag - Matching symbol from data decoding
-- MemoryTable - Input memory action table
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
--
-- Description: This function is used to find the output of the
-- MemoryTable corresponding to a given set of inputs.
--
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableLookUp (
VARIABLE MemoryAction : OUT VitalMemorySymbolType;
VARIABLE DataAction : OUT VitalMemorySymbolType;
VARIABLE MemoryCorruptMask : OUT std_logic_vector;
VARIABLE DataCorruptMask : OUT std_logic_vector;
CONSTANT PrevControls : IN std_logic_vector;
CONSTANT Controls : IN std_logic_vector;
CONSTANT AddrFlag : IN VitalMemorySymbolType;
CONSTANT DataFlag : IN VitalMemorySymbolType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
CONSTANT ControlsSize : INTEGER := Controls'LENGTH;
CONSTANT TableEntries : INTEGER := MemoryTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := MemoryTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
CONSTANT DataInBusNdx : INTEGER := TableWidth - 3;
CONSTANT AddressBusNdx : INTEGER := TableWidth - 4;
VARIABLE AddrFlagTable : VitalMemorySymbolType;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
VARIABLE TableAlias : VitalMemoryTableType(
0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= MemoryTable;
BEGIN
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the Controls
FOR j IN 0 TO ControlsSize LOOP
IF (j = ControlsSize) THEN
-- a match occurred, now check AddrFlag, DataFlag
MemoryMatch(TableAlias(i,AddressBusNdx),AddrFlag,Err,Match);
IF (Match) THEN
MemoryMatch(TableAlias(i,DataInBusNdx),DataFlag,Err,Match);
IF (Match) THEN
MemoryTableCorruptMask (
CorruptMask => MemoryCorruptMask ,
Action => TableAlias(i, MemActionNdx)
);
MemoryTableCorruptMask (
CorruptMask => DataCorruptMask ,
Action => TableAlias(i, DatActionNdx)
);
-- get the return memory and data actions
MemoryAction := TableAlias(i, MemActionNdx);
DataAction := TableAlias(i, DatActionNdx);
-- DEBUG: The lines below report table search
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,TableAlias,i,PortName);
END IF;
-- DEBUG: The lines above report table search
RETURN;
END IF;
END IF;
ELSE
-- Match memory table inputs
MemoryMatch ( TableAlias(i,j),
Controls(j), PrevControls(j),
Err, Match);
END IF;
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
-- no match found, return default action
MemoryAction := 's'; -- no change to memory
DataAction := 'S'; -- no change to dataout
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,ErrDefMemAct,HeaderMsg,PortName);
END IF;
RETURN;
END;
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableLookUp (
VARIABLE MemoryAction : OUT VitalMemorySymbolType;
VARIABLE DataAction : OUT VitalMemorySymbolType;
VARIABLE MemoryCorruptMask : OUT std_logic_vector;
VARIABLE DataCorruptMask : OUT std_logic_vector;
CONSTANT PrevControls : IN std_logic_vector;
CONSTANT PrevEnableBus : IN std_logic_vector;
CONSTANT Controls : IN std_logic_vector;
CONSTANT EnableBus : IN std_logic_vector;
CONSTANT EnableIndex : IN INTEGER;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER;
CONSTANT AddrFlag : IN VitalMemorySymbolType;
CONSTANT DataFlag : IN VitalMemorySymbolType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
CONSTANT ControlsSize : INTEGER := Controls'LENGTH;
CONSTANT TableEntries : INTEGER := MemoryTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := MemoryTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
CONSTANT DataInBusNdx : INTEGER := TableWidth - 3;
CONSTANT AddressBusNdx : INTEGER := TableWidth - 4;
VARIABLE AddrFlagTable : VitalMemorySymbolType;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
VARIABLE TableAlias : VitalMemoryTableType(
0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= MemoryTable;
BEGIN
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the Controls
FOR j IN 0 TO ControlsSize LOOP
IF (j = ControlsSize) THEN
-- a match occurred, now check EnableBus, AddrFlag, DataFlag
IF (EnableIndex >= 0) THEN
RowLoop2: -- Check relevant elements of the EnableBus
FOR k IN 0 TO AddressBusNdx - ControlsSize - 1 LOOP
MemoryMatch ( TableAlias(i,k + ControlsSize),
EnableBus(k * BitsPerEnable + EnableIndex),
PrevEnableBus(k * BitsPerEnable + EnableIndex),
Err, Match);
EXIT RowLoop2 WHEN NOT(Match);
END LOOP;
END IF;
IF (Match) THEN
MemoryMatch(TableAlias(i,AddressBusNdx),AddrFlag,Err,Match);
IF (Match) THEN
MemoryMatch(TableAlias(i,DataInBusNdx),DataFlag,Err,Match);
IF (Match) THEN
MemoryTableCorruptMask (
CorruptMask => MemoryCorruptMask ,
Action => TableAlias(i, MemActionNdx),
EnableIndex => EnableIndex ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
MemoryTableCorruptMask (
CorruptMask => DataCorruptMask ,
Action => TableAlias(i, DatActionNdx),
EnableIndex => EnableIndex ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
-- get the return memory and data actions
MemoryAction := TableAlias(i, MemActionNdx);
DataAction := TableAlias(i, DatActionNdx);
-- DEBUG: The lines below report table search
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,TableAlias,i,PortName);
END IF;
-- DEBUG: The lines above report table search
RETURN;
END IF;
END IF;
END IF;
ELSE
-- Match memory table inputs
MemoryMatch ( TableAlias(i,j),
Controls(j), PrevControls(j),
Err, Match);
END IF;
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
-- no match found, return default action
MemoryAction := 's'; -- no change to memory
DataAction := 'S'; -- no change to dataout
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,ErrDefMemAct,HeaderMsg,PortName);
END IF;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: ViolationTableLookUp
-- Parameters: MemoryAction - Output memory action to be performed
-- DataAction - Output data action to be performed
-- TimingDataArray - This is currently not used (comment out)
-- ViolationArray - Aggregation of violation variables
-- ViolationTable - Input memory violation table
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
-- Description: This function is used to find the output of the
-- ViolationTable corresponding to a given set of inputs.
-- ----------------------------------------------------------------------------
PROCEDURE ViolationTableLookUp (
VARIABLE MemoryAction : OUT VitalMemorySymbolType;
VARIABLE DataAction : OUT VitalMemorySymbolType;
VARIABLE MemoryCorruptMask : OUT std_logic_vector;
VARIABLE DataCorruptMask : OUT std_logic_vector;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN std_logic_vector;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
CONSTANT ViolFlagsSize : INTEGER := ViolationFlags'LENGTH;
CONSTANT ViolFlArySize : INTEGER := ViolationFlagsArray'LENGTH;
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE ViolFlAryItem : std_ulogic;
CONSTANT ViolSzArySize : INTEGER := ViolationSizesArray'LENGTH;
CONSTANT TableEntries : INTEGER := ViolationTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := ViolationTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
VARIABLE HighBit : NATURAL := 0;
VARIABLE LowBit : NATURAL := 0;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
VARIABLE TableAlias : VitalMemoryTableType(
0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= ViolationTable;
BEGIN
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the ViolationFlags
FOR j IN 0 TO ViolFlagsSize LOOP
IF (j = ViolFlagsSize) THEN
ViolFlAryPosn := 0;
RowLoop2: -- Check relevant elements of the ViolationFlagsArray
FOR k IN 0 TO MemActionNdx - ViolFlagsSize - 1 LOOP
ViolFlAryItem := '0';
SubwordLoop: -- Check for 'X' in ViolationFlagsArray chunk
FOR s IN ViolFlAryPosn TO ViolFlAryPosn+ViolationSizesArray(k)-1 LOOP
IF (ViolationFlagsArray(s) = 'X') THEN
ViolFlAryItem := 'X';
EXIT SubwordLoop;
END IF;
END LOOP;
MemoryMatch ( TableAlias(i,k + ViolFlagsSize),
ViolFlAryItem,ViolFlAryItem,
Err, Match);
ViolFlAryPosn := ViolFlAryPosn + ViolationSizesArray(k);
EXIT RowLoop2 WHEN NOT(Match);
END LOOP;
IF (Match) THEN
-- Compute memory and data corruption masks
ViolationTableCorruptMask(
CorruptMask => MemoryCorruptMask ,
Action => TableAlias(i, MemActionNdx),
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => ViolationFlagsArray ,
ViolationSizesArray => ViolationSizesArray ,
ViolationTable => ViolationTable ,
TableIndex => i ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
ViolationTableCorruptMask(
CorruptMask => DataCorruptMask ,
Action => TableAlias(i, DatActionNdx),
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => ViolationFlagsArray ,
ViolationSizesArray => ViolationSizesArray ,
ViolationTable => ViolationTable ,
TableIndex => i ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
-- get the return memory and data actions
MemoryAction := TableAlias(i, MemActionNdx);
DataAction := TableAlias(i, DatActionNdx);
-- DEBUG: The lines below report table search
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMV,TableAlias,i,PortName);
END IF;
-- DEBUG: The lines above report table search
RETURN;
END IF;
ELSE
-- Match violation table inputs
Err := FALSE;
Match := FALSE;
IF (TableAlias(i,j) /= 'X' AND
TableAlias(i,j) /= '0' AND
TableAlias(i,j) /= '-') THEN
Err := TRUE;
ELSIF (TableAlias(i,j) = '-' OR
(TableAlias(i,j) = 'X' AND ViolationFlags(j) = 'X') OR
(TableAlias(i,j) = '0' AND ViolationFlags(j) = '0')) THEN
Match := TRUE;
END IF;
END IF;
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
-- no match found, return default action
MemoryAction := 's'; -- no change to memory
DataAction := 'S'; -- no change to dataout
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMV,ErrDefMemAct,HeaderMsg,PortName);
END IF;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: HandleMemoryAction
-- Parameters: MemoryData - Pointer to memory data structure
-- PortFlag - Indicates read/write mode of port
-- CorruptMask - XOR'ed with DataInBus when corrupting
-- DataInBus - Current data bus in
-- Address - Current address integer
-- HighBit - Current address high bit
-- LowBit - Current address low bit
-- MemoryTable - Input memory action table
-- MemoryAction - Memory action to be performed
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
-- Description: This procedure performs the specified memory action on
-- the input memory data structure.
-- ----------------------------------------------------------------------------
PROCEDURE HandleMemoryAction (
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagType;
CONSTANT CorruptMask : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT MemoryAction : IN VitalMemorySymbolType;
CONSTANT CallerName : IN STRING;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE DataInTmp : std_logic_vector(DataInBus'RANGE)
:= DataInBus;
BEGIN
-- Handle the memory action
CASE MemoryAction IS
WHEN 'w' =>
-- Writing data to memory
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrWrDatMem,HeaderMsg,PortName);
END IF;
WriteMemory(MemoryData,DataInBus,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN 's' =>
-- Retaining previous memory contents
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrNoChgMem,HeaderMsg,PortName);
END IF;
-- Set memory current to quiet state
PortFlag.MemoryCurrent := READ;
WHEN 'c' =>
-- Corrupting entire memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrAllMem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => 'X');
-- No need to CorruptMask
FOR i IN 0 TO MemoryData.NoOfWords-1 LOOP
WriteMemory(MemoryData,DataInTmp,i);
END LOOP;
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'l' =>
-- Corrupting a word in memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdMem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => 'X');
-- No need to CorruptMask
WriteMemory(MemoryData,DataInTmp,Address);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'd' =>
-- Corrupting a single bit in memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'e' =>
-- Corrupting a word with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
IF (DataInTmp /= DataInBus) THEN
DataInTmp := (OTHERS => 'X');
-- No need to CorruptMask
WriteMemory(MemoryData,DataInTmp,Address);
END IF;
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'C' =>
-- Corrupting a sub-word entire memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrAllSubMem,HeaderMsg,PortName);
END IF;
FOR i IN 0 TO MemoryData.NoOfWords-1 LOOP
ReadMemory(MemoryData,DataInTmp,i);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,i,HighBit,LowBit);
END LOOP;
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'L' =>
-- Corrupting a sub-word in memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdSubMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'D' =>
-- Corrupting a single bit of a memory sub-word with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitSubMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'E' =>
-- Corrupting a sub-word with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatSubMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
IF (DataInBus(HighBit DOWNTO LowBit) /=
DataInTmp(HighBit DOWNTO LowBit)) THEN
DataInTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
END IF;
--PortFlag := WRITE;
PortFlag.MemoryCurrent := CORRUPT;
WHEN '0' =>
-- Assigning low level to memory location
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg0Mem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => '0');
WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN '1' =>
-- Assigning high level to memory location
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg1Mem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => '1');
WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN 'Z' =>
-- Assigning high impedence to memory location
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsgZMem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => 'Z');
WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN OTHERS =>
-- Unknown memory action
PortFlag.MemoryCurrent := UNDEF;
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrUnknMemDo,HeaderMsg,PortName);
END IF;
END CASE;
-- Note: HandleMemoryAction does not change the PortFlag.OutputDisable
END;
-- ----------------------------------------------------------------------------
-- Procedure: HandleDataAction
-- Parameters: DataOutBus - Output result of the data action
-- MemoryData - Input pointer to memory data structure
-- PortFlag - Indicates read/write mode of port
-- CorruptMask - XOR'ed with DataInBus when corrupting
-- DataInBus - Current data bus in
-- Address - Current address integer
-- HighBit - Current address high bit
-- LowBit - Current address low bit
-- MemoryTable - Input memory action table
-- DataAction - Data action to be performed
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
-- Description: This procedure performs the specified data action based
-- on the input memory data structure. Checks whether
-- the previous state is HighZ. If yes then portFlag
-- should be NOCHANGE for VMPD to ignore IORetain
-- corruption. The idea is that the first Z should be
-- propagated but later ones should be ignored.
-- ----------------------------------------------------------------------------
PROCEDURE HandleDataAction (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagType;
CONSTANT CorruptMask : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT DataAction : IN VitalMemorySymbolType;
CONSTANT CallerName : IN STRING;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
BEGIN
-- Handle the data action
CASE DataAction IS
WHEN 'l' =>
-- Corrupting data out with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdOut,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => 'X');
-- No need to CorruptMask
PortFlag.DataCurrent := CORRUPT;
WHEN 'd' =>
-- Corrupting a single bit of data out with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitOut,HeaderMsg,PortName);
END IF;
DataOutTmp(HighBit DOWNTO LowBit) :=
DataOutTmp(HighBit DOWNTO LowBit) XOR
CorruptMask(HighBit DOWNTO LowBit);
PortFlag.DataCurrent := CORRUPT;
WHEN 'e' =>
-- Corrupting data out with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
IF (DataOutTmp /= DataInBus) THEN
DataOutTmp := (OTHERS => 'X');
-- No need to CorruptMask
END IF;
PortFlag.DataCurrent := CORRUPT;
WHEN 'L' =>
-- Corrupting data out sub-word with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdSubOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
DataOutTmp(HighBit DOWNTO LowBit) :=
DataOutTmp(HighBit DOWNTO LowBit) XOR
CorruptMask(HighBit DOWNTO LowBit);
PortFlag.DataCurrent := CORRUPT;
WHEN 'D' =>
-- Corrupting a single bit of data out sub-word with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitSubOut,HeaderMsg,PortName);
END IF;
DataOutTmp(HighBit DOWNTO LowBit) :=
DataOutTmp(HighBit DOWNTO LowBit) XOR
CorruptMask(HighBit DOWNTO LowBit);
PortFlag.DataCurrent := CORRUPT;
WHEN 'E' =>
-- Corrupting data out sub-word with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatSubOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
IF (DataInBus(HighBit DOWNTO LowBit) /=
DataOutTmp(HighBit DOWNTO LowBit)) THEN
DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
-- No need to CorruptMask
END IF;
PortFlag.DataCurrent := CORRUPT;
WHEN 'M' =>
-- Implicit read from memory to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrImplOut,HeaderMsg,PortName);
END IF;
PortFlag.DataCurrent := READ;
WHEN 'm' =>
-- Reading data from memory to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrReadOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
PortFlag.DataCurrent := READ;
WHEN 't' =>
-- Transferring from data in to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAssgOut,HeaderMsg,PortName);
END IF;
DataOutTmp := DataInBus;
PortFlag.DataCurrent := READ;
WHEN '0' =>
-- Assigning low level to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg0Out,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => '0');
PortFlag.DataCurrent := READ;
WHEN '1' =>
-- Assigning high level to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg1Out,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => '1');
PortFlag.DataCurrent := READ;
WHEN 'Z' =>
-- Assigning high impedence to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsgZOut,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => 'Z');
PortFlag.DataCurrent := HIGHZ;
WHEN 'S' =>
-- Keeping data out at steady value
PortFlag.OutputDisable := TRUE;
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsgSOut,HeaderMsg,PortName);
END IF;
WHEN OTHERS =>
-- Unknown data action
PortFlag.DataCurrent := UNDEF;
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrUnknDatDo,HeaderMsg,PortName);
END IF;
END CASE;
DataOutBus(HighBit DOWNTO LowBit) := DataOutTmp(HighBit DOWNTO LowBit);
END;
-- ----------------------------------------------------------------------------
-- Memory Table Modeling Primitives
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Procedure: VitalDeclareMemory
-- Parameters: NoOfWords - Number of words in the memory
-- NoOfBitsPerWord - Number of bits per word in memory
-- NoOfBitsPerSubWord - Number of bits per sub word
-- MemoryLoadFile - Name of data file to load
-- Description: This function is intended to be used to initialize
-- memory data declarations, i.e. to be executed duing
-- simulation elaboration time. Handles the allocation
-- and initialization of memory for the memory data.
-- Default NoOfBitsPerSubWord is NoOfBitsPerWord.
-- ----------------------------------------------------------------------------
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType IS
VARIABLE MemoryPtr : VitalMemoryDataType;
BEGIN
MemoryPtr := VitalDeclareMemory(
NoOfWords => NoOfWords,
NoOfBitsPerWord => NoOfBitsPerWord,
NoOfBitsPerSubWord => NoOfBitsPerWord,
MemoryLoadFile => MemoryLoadFile,
BinaryLoadFile => BinaryLoadFile
);
RETURN MemoryPtr;
END;
-- ----------------------------------------------------------------------------
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT NoOfBitsPerSubWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType IS
VARIABLE MemoryPtr : VitalMemoryDataType;
VARIABLE BitsPerEnable : NATURAL
:= ((NoOfBitsPerWord-1)
/NoOfBitsPerSubWord)+1;
BEGIN
PrintMemoryMessage(MsgVDM,ErrInitMem);
MemoryPtr := new VitalMemoryArrayRecType '(
NoOfWords => NoOfWords,
NoOfBitsPerWord => NoOfBitsPerWord,
NoOfBitsPerSubWord => NoOfBitsPerSubWord,
NoOfBitsPerEnable => BitsPerEnable,
MemoryArrayPtr => NULL
);
MemoryPtr.MemoryArrayPtr
:= new MemoryArrayType (0 to MemoryPtr.NoOfWords - 1);
FOR i IN 0 TO MemoryPtr.NoOfWords - 1 LOOP
MemoryPtr.MemoryArrayPtr(i)
:= new MemoryWordType (MemoryPtr.NoOfBitsPerWord - 1 DOWNTO 0);
END LOOP;
IF (MemoryLoadFile /= "") THEN
LoadMemory (MemoryPtr, MemoryLoadFile, BinaryLoadFile);
END IF;
RETURN MemoryPtr;
END;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryTable
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PrevControls - Previous data in for edge detection
-- PrevEnableBus - Previous enables for edge detection
-- PrevDataInBus - Previous data bus for edge detection
-- PrevAddressBus - Previous address bus for edge detection
-- PortFlag - Indicates port operating mode
-- PortFlagArray - Vector form of PortFlag for sub-word
-- Controls - Agregate of scalar control lines
-- EnableBus - Concatenation of vector control lines
-- DataInBus - Input value of data bus in
-- AddressBus - Input value of address bus in
-- AddressValue - Decoded value of the AddressBus
-- MemoryTable - Input memory action table
-- PortType - The type of port (currently not used)
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure implements the majority of the memory
-- modeling functionality via lookup of the memory action
-- tables and performing the specified actions if matches
-- are found, or the default actions otherwise. The
-- overloadings are provided for the word and sub-word
-- (using the EnableBus and PortFlagArray arguments) addressing
-- cases.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
VARIABLE MemoryAction : VitalMemorySymbolType;
VARIABLE DataAction : VitalMemorySymbolType;
VARIABLE HighBit : NATURAL := MemoryData.NoOfBitsPerWord-1;
VARIABLE LowBit : NATURAL := 0;
VARIABLE Address : INTEGER := 0;
VARIABLE PortFlagTmp : VitalPortFlagType;
VARIABLE AddrFlag : VitalMemorySymbolType := 'g'; -- good addr
VARIABLE DataFlag : VitalMemorySymbolType := 'g'; -- good data
VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE);
VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE);
BEGIN
-- Optimize for case when all current inputs are same as previous
IF (PrevDataInBus = DataInBus
AND PrevAddressBus = AddressBus
AND PrevControls = Controls
AND PortFlag(0).MemoryCurrent = PortFlag(0).MemoryPrevious
AND PortFlag(0).DataCurrent = PortFlag(0).DataPrevious) THEN
PortFlag(0).OutputDisable := TRUE;
RETURN;
END IF;
PortFlag(0).DataPrevious := PortFlag(0).DataCurrent;
PortFlag(0).MemoryPrevious := PortFlag(0).MemoryCurrent;
PortFlag(0).OutputDisable := FALSE;
PortFlagTmp := PortFlag(0);
-- Convert address bus to integer value and table lookup flag
DecodeAddress(
Address => Address ,
AddrFlag => AddrFlag ,
MemoryData => MemoryData ,
PrevAddressBus => PrevAddressBus ,
AddressBus => AddressBus
);
-- Interpret data bus as a table lookup flag
DecodeData (
DataFlag => DataFlag ,
PrevDataInBus => PrevDataInBus ,
DataInBus => DataInBus ,
HighBit => HighBit ,
LowBit => LowBit
);
-- Lookup memory and data actions
MemoryTableLookUp(
MemoryAction => MemoryAction ,
DataAction => DataAction ,
MemoryCorruptMask => MemCorruptMask ,
DataCorruptMask => DatCorruptMask ,
PrevControls => PrevControls ,
Controls => Controls ,
AddrFlag => AddrFlag ,
DataFlag => DataFlag ,
MemoryTable => MemoryTable ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Handle data action before memory action
-- This allows reading previous memory contents
HandleDataAction(
DataOutBus => DataOutTmp ,
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => DatCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
DataAction => DataAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
HandleMemoryAction(
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => MemCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
MemoryAction => MemoryAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Set the output PortFlag(0) value
IF (DataAction = 'S') THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
IF (PortFlagTmp.DataCurrent = PortFlagTmp.DataPrevious
AND PortFlagTmp.DataCurrent = HIGHZ) THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
PortFlag(0) := PortFlagTmp;
-- Set previous values for subsequent edge detection
PrevControls := Controls;
PrevDataInBus := DataInBus;
PrevAddressBus := AddressBus;
-- Set the candidate zero delay return value
DataOutBus := DataOutTmp;
-- Set the output AddressValue for VitalMemoryCrossPorts
AddressValue := Address;
END VitalMemoryTable;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevEnableBus : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlagArray : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT EnableBus : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
VARIABLE MemoryAction : VitalMemorySymbolType;
VARIABLE DataAction : VitalMemorySymbolType;
VARIABLE HighBit : NATURAL := BitsPerSubWord-1;
VARIABLE LowBit : NATURAL := 0;
VARIABLE Address : INTEGER := 0;
VARIABLE PortFlagTmp : VitalPortFlagType;
VARIABLE AddrFlag : VitalMemorySymbolType := 'g'; -- good addr
VARIABLE DataFlag : VitalMemorySymbolType := 'g'; -- good data
VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE);
VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE);
BEGIN
-- Optimize for case when all current inputs are same as previous
IF (PrevDataInBus = DataInBus
AND PrevAddressBus = AddressBus
AND PrevControls = Controls) THEN
CheckFlags:
FOR i IN 0 TO BitsPerEnable-1 LOOP
IF (PortFlagArray(i).MemoryCurrent /= PortFlagArray(i).MemoryPrevious
OR PortFlagArray(i).DataCurrent /= PortFlagArray(i).DataPrevious) THEN
EXIT CheckFlags;
END IF;
IF (i = BitsPerEnable-1) THEN
FOR j IN 0 TO BitsPerEnable-1 LOOP
PortFlagArray(j).OutputDisable := TRUE;
END LOOP;
RETURN;
END IF;
END LOOP;
END IF;
-- Convert address bus to integer value and table lookup flag
DecodeAddress(
Address => Address,
AddrFlag => AddrFlag,
MemoryData => MemoryData,
PrevAddressBus => PrevAddressBus,
AddressBus => AddressBus
);
-- Perform independent operations for each sub-word
FOR i IN 0 TO BitsPerEnable-1 LOOP
-- Set the output PortFlag(i) value
PortFlagArray(i).DataPrevious := PortFlagArray(i).DataCurrent;
PortFlagArray(i).MemoryPrevious := PortFlagArray(i).MemoryCurrent;
PortFlagArray(i).OutputDisable := FALSE;
PortFlagTmp := PortFlagArray(i);
-- Interpret data bus as a table lookup flag
DecodeData (
DataFlag => DataFlag ,
PrevDataInBus => PrevDataInBus ,
DataInBus => DataInBus ,
HighBit => HighBit ,
LowBit => LowBit
);
-- Lookup memory and data actions
MemoryTableLookUp(
MemoryAction => MemoryAction ,
DataAction => DataAction ,
MemoryCorruptMask => MemCorruptMask ,
DataCorruptMask => DatCorruptMask ,
PrevControls => PrevControls ,
PrevEnableBus => PrevEnableBus ,
Controls => Controls ,
EnableBus => EnableBus ,
EnableIndex => i ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable ,
AddrFlag => AddrFlag ,
DataFlag => DataFlag ,
MemoryTable => MemoryTable ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Handle data action before memory action
-- This allows reading previous memory contents
HandleDataAction(
DataOutBus => DataOutTmp ,
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => DatCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
DataAction => DataAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
HandleMemoryAction(
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => MemCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
MemoryAction => MemoryAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Set the output PortFlag(i) value
IF (DataAction = 'S') THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
IF (PortFlagTmp.DataCurrent = PortFlagTmp.DataPrevious
AND PortFlagTmp.DataCurrent = HIGHZ) THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
PortFlagArray(i) := PortFlagTmp;
IF (i < BitsPerEnable-1) THEN
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END IF;
END LOOP;
-- Set previous values for subsequent edge detection
PrevControls := Controls;
PrevEnableBus := EnableBus;
PrevDataInBus := DataInBus;
PrevAddressBus := AddressBus;
-- Set the candidate zero delay return value
DataOutBus := DataOutTmp;
-- Set the output AddressValue for VitalMemoryCrossPorts
AddressValue := Address;
END VitalMemoryTable;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryCrossPorts
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- SamePortFlag - Operating mode for same port
-- SamePortAddressValue - Operating modes for cross ports
-- CrossPortAddressArray - Decoded AddressBus for cross ports
-- CrossPortMode - Write contention and crossport read control
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- Description: These procedures control the effect of memory operations
-- on a given port due to operations on other ports in a
-- multi-port memory.
-- This includes data write through when reading and writing
-- to the same address, as well as write contention when
-- there are multiple write to the same address.
-- If addresses do not match then data bus is unchanged.
-- The DataOutBus can be diabled with 'Z' value.
-- If the WritePortFlag is 'CORRUPT', that would mean
-- that the whole memory is corrupted. So, for corrupting
-- the Read port, the Addresses need not be compared.
--
-- CrossPortMode Enum Description
-- 1. CpRead Allows Cross Port Read Only
-- No contention checking.
-- 2. WriteContention Allows for write contention checks
-- only between multiple write ports
-- 3. ReadWriteContention Allows contention between read and
-- write ports. The action is to corrupt
-- the memory and the output bus.
-- 4. CpReadAndWriteContention Is a combination of 1 & 2
-- 5. CpReadAndReadContention Allows contention between read and
-- write ports. The action is to corrupt
-- the dataout bus only. The cp read is
-- performed if not contending.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryCrossPorts (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE SamePortFlag : INOUT VitalPortFlagVectorType;
CONSTANT SamePortAddressValue : IN VitalAddressValueType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT CrossPortMode : IN VitalCrossPortModeType
:= CpReadAndWriteContention;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) := (OTHERS => 'Z');
VARIABLE MemoryTmp : std_logic_vector(DataOutBus'RANGE);
VARIABLE CrossPorts : NATURAL := CrossPortAddressArray'LENGTH;
VARIABLE LowBit : NATURAL := 0;
VARIABLE HighBit : NATURAL := BitsPerSubWord-1;
VARIABLE Address : VitalAddressValueType := SamePortAddressValue;
VARIABLE AddressJ : VitalAddressValueType;
VARIABLE AddressK : VitalAddressValueType;
VARIABLE PortFlagI : VitalPortFlagType;
VARIABLE PortFlagIJ : VitalPortFlagType;
VARIABLE PortFlagIK : VitalPortFlagType;
VARIABLE DoCpRead : BOOLEAN := FALSE;
VARIABLE DoWrCont : BOOLEAN := FALSE;
VARIABLE DoCpCont : BOOLEAN := FALSE;
VARIABLE DoRdWrCont : BOOLEAN := FALSE;
VARIABLE CpWrCont : BOOLEAN := FALSE;
VARIABLE ModeWrCont : BOOLEAN :=
(CrossPortMode=WriteContention) OR
(CrossPortMode=CpReadAndWriteContention);
VARIABLE ModeCpRead : BOOLEAN :=
(CrossPortMode=CpRead) OR
(CrossPortMode=CpReadAndWriteContention);
VARIABLE ModeCpCont : BOOLEAN := (CrossPortMode=ReadWriteContention);
VARIABLE ModeRdWrCont : BOOLEAN := (CrossPortMode=CpReadAndReadContention);
BEGIN
-- Check for disabled port (i.e. OTHERS => 'Z')
IF (DataOutBus = DataOutTmp) THEN
RETURN;
ELSE
DataOutTmp := DataOutBus;
END IF;
-- Check for error in address
IF (Address < 0) THEN
RETURN;
END IF;
ReadMemory(MemoryData,MemoryTmp,Address);
SubWordLoop: -- For each slice of the sub-word I
FOR i IN 0 TO BitsPerEnable-1 LOOP
PortFlagI := SamePortFlag(i);
-- For each cross port J: check with same port address
FOR j IN 0 TO CrossPorts-1 LOOP
PortFlagIJ := CrossPortFlagArray(i+j*BitsPerEnable);
AddressJ := CrossPortAddressArray(j);
IF (AddressJ < 0) THEN
NEXT;
END IF;
DoWrCont := (Address = AddressJ) AND
(ModeWrCont = TRUE) AND
((PortFlagI.MemoryCurrent = WRITE) OR
(PortFlagI.MemoryCurrent = CORRUPT)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
DoCpRead := (Address = AddressJ) AND
(ModeCpRead = TRUE) AND
((PortFlagI.MemoryCurrent = READ) OR
(PortFlagI.OutputDisable = TRUE)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
DoCpCont := (Address = AddressJ) AND
(ModeCpCont = TRUE) AND
((PortFlagI.MemoryCurrent = READ) OR
(PortFlagI.OutputDisable = TRUE)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
DoRdWrCont:= (Address = AddressJ) AND
(ModeRdWrCont = TRUE) AND
((PortFlagI.MemoryCurrent = READ) OR
(PortFlagI.OutputDisable = TRUE)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
IF (DoWrCont OR DoCpCont) THEN
-- Corrupt dataout and memory
MemoryTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
SamePortFlag(i).MemoryCurrent := CORRUPT;
SamePortFlag(i).DataCurrent := CORRUPT;
SamePortFlag(i).OutputDisable := FALSE;
EXIT;
END IF;
IF (DoCpRead) THEN
-- Update dataout with memory
DataOutTmp(HighBit DOWNTO LowBit) :=
MemoryTmp(HighBit DOWNTO LowBit);
SamePortFlag(i).MemoryCurrent := READ;
SamePortFlag(i).DataCurrent := READ;
SamePortFlag(i).OutputDisable := FALSE;
EXIT;
END IF;
IF (DoRdWrCont) THEN
-- Corrupt dataout only
DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
SamePortFlag(i).DataCurrent := CORRUPT;
SamePortFlag(i).OutputDisable := FALSE;
EXIT;
END IF;
END LOOP;
IF (i < BitsPerEnable-1) THEN
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END IF;
END LOOP; -- SubWordLoop
DataOutBus := DataOutTmp;
IF (DoWrCont) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpWrCont,HeaderMsg,PortName);
END IF;
WriteMemory(MemoryData,MemoryTmp,Address);
END IF;
IF (DoCpCont) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpCpCont,HeaderMsg,PortName);
END IF;
WriteMemory(MemoryData,MemoryTmp,Address);
END IF;
IF (DoCpRead) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpCpRead,HeaderMsg,PortName);
END IF;
END IF;
IF (DoRdWrCont) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpRdWrCo,HeaderMsg,PortName);
END IF;
END IF;
END VitalMemoryCrossPorts;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryCrossPorts (
VARIABLE MemoryData : INOUT VitalMemoryDataType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE MemoryTmp : std_logic_vector(BitsPerWord-1 DOWNTO 0);
VARIABLE CrossPorts : NATURAL := CrossPortAddressArray'LENGTH;
VARIABLE LowBit : NATURAL := 0;
VARIABLE HighBit : NATURAL := BitsPerSubWord-1;
VARIABLE AddressJ : VitalAddressValueType;
VARIABLE AddressK : VitalAddressValueType;
VARIABLE PortFlagIJ : VitalPortFlagType;
VARIABLE PortFlagIK : VitalPortFlagType;
VARIABLE CpWrCont : BOOLEAN := FALSE;
BEGIN
SubWordLoop: -- For each slice of the sub-word I
FOR i IN 0 TO BitsPerEnable-1 LOOP
-- For each cross port J: check with each cross port K
FOR j IN 0 TO CrossPorts-1 LOOP
PortFlagIJ := CrossPortFlagArray(i+j*BitsPerEnable);
AddressJ := CrossPortAddressArray(j);
-- Check for error in address
IF (AddressJ < 0) THEN
NEXT;
END IF;
ReadMemory(MemoryData,MemoryTmp,AddressJ);
-- For each cross port K
FOR k IN 0 TO CrossPorts-1 LOOP
IF (k <= j) THEN
NEXT;
END IF;
PortFlagIK := CrossPortFlagArray(i+k*BitsPerEnable);
AddressK := CrossPortAddressArray(k);
-- Check for error in address
IF (AddressK < 0) THEN
NEXT;
END IF;
CpWrCont := ( (AddressJ = AddressK) AND
(PortFlagIJ.MemoryCurrent = WRITE) AND
(PortFlagIK.MemoryCurrent = WRITE) ) OR
( (PortFlagIJ.MemoryCurrent = WRITE) AND
(PortFlagIK.MemoryCurrent = CORRUPT) ) OR
( (PortFlagIJ.MemoryCurrent = CORRUPT) AND
(PortFlagIK.MemoryCurrent = WRITE) ) OR
( (PortFlagIJ.MemoryCurrent = CORRUPT) AND
(PortFlagIK.MemoryCurrent = CORRUPT) ) ;
IF (CpWrCont) THEN
-- Corrupt memory only
MemoryTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
EXIT;
END IF;
END LOOP; -- FOR k IN 0 TO CrossPorts-1 LOOP
IF (CpWrCont = TRUE) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpCpWrCont,HeaderMsg);
END IF;
WriteMemory(MemoryData,MemoryTmp,AddressJ);
END IF;
END LOOP; -- FOR j IN 0 TO CrossPorts-1 LOOP
IF (i < BitsPerEnable-1) THEN
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END IF;
END LOOP; -- SubWordLoop
END VitalMemoryCrossPorts;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryViolation
-- Parameters: DataOutBus - Output zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PortFlag - Indicates port operating mode
-- TimingDataArray - This is currently not used (comment out)
-- ViolationArray - Aggregation of violation variables
-- DataInBus - Input value of data bus in
-- AddressBus - Input value of address bus in
-- AddressValue - Decoded value of the AddressBus
-- ViolationTable - Input memory violation table
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure is intended to implement all actions on the
-- memory contents and data out bus as a result of timing viols.
-- It uses the memory action table to perform various corruption
-- policies specified by the user.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN X01ArrayT;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
VARIABLE MemoryAction : VitalMemorySymbolType;
VARIABLE DataAction : VitalMemorySymbolType;
-- VMT relies on the corrupt masks so HighBit/LowBit are full word
VARIABLE HighBit : NATURAL := BitsPerWord-1;
VARIABLE LowBit : NATURAL := 0;
VARIABLE PortFlagTmp : VitalPortFlagType;
VARIABLE VFlagArrayTmp : std_logic_vector
(0 TO ViolationFlagsArray'LENGTH-1);
VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE);
VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE);
BEGIN
-- Don't do anything if given an error address
IF (AddressValue < 0) THEN
RETURN;
END IF;
FOR i IN ViolationFlagsArray'RANGE LOOP
VFlagArrayTmp(i) := ViolationFlagsArray(i);
END LOOP;
-- Lookup memory and data actions
ViolationTableLookUp(
MemoryAction => MemoryAction ,
DataAction => DataAction ,
MemoryCorruptMask => MemCorruptMask ,
DataCorruptMask => DatCorruptMask ,
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => VFlagArrayTmp ,
ViolationSizesArray => ViolationSizesArray ,
ViolationTable => ViolationTable ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Need to read incoming PF value (was not before)
PortFlagTmp := PortFlag(0);
IF (PortType = READ OR PortType = RDNWR) THEN
-- Handle data action before memory action
-- This allows reading previous memory contents
HandleDataAction(
DataOutBus => DataOutTmp ,
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => DatCorruptMask ,
DataInBus => DataInBus ,
Address => AddressValue ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => ViolationTable ,
DataAction => DataAction ,
CallerName => MsgVMV ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
END IF;
IF (PortType = WRITE OR PortType = RDNWR) THEN
HandleMemoryAction(
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => MemCorruptMask ,
DataInBus => DataInBus ,
Address => AddressValue ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => ViolationTable ,
MemoryAction => MemoryAction ,
CallerName => MsgVMV ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
END IF;
-- Check if we need to turn off PF.OutputDisable
IF (DataAction /= 'S') THEN
PortFlagTmp.OutputDisable := FALSE;
-- Set the output PortFlag(0) value
-- Note that all bits of PortFlag get PortFlagTmp
FOR i IN PortFlag'RANGE LOOP
PortFlag(i) := PortFlagTmp;
END LOOP;
END IF;
-- Set the candidate zero delay return value
DataOutBus := DataOutTmp;
END;
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE VFlagArrayTmp : X01ArrayT (0 TO 0);
BEGIN
VitalMemoryViolation (
DataOutBus => DataOutBus ,
MemoryData => MemoryData ,
PortFlag => PortFlag ,
DataInBus => DataInBus ,
AddressValue => AddressValue ,
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => VFlagArrayTmp ,
ViolationSizesArray => ( 0 => 0 ) ,
ViolationTable => ViolationTable ,
PortType => PortType ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn ,
MsgSeverity => MsgSeverity
);
END;
END Vital_Memory ;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd | 4 | 1824 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02464ent IS
END c07s03b02x02p03n02i02464ent;
ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := (1 => '0', others => '1');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02464"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02464arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug0101/repro1.vhdl | 1 | 202 | entity repro1 is
end repro1;
architecture behav of repro1 is
signal sig : bit_vector (7 downto 0);
begin
g : for i in sig1'range generate
sig (i) <= sig (i) and '1';
end generate;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd | 4 | 1440 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
-- code from book:
type controller_state is (initial, idle, active, error);
-- end of code from book
signal current_state : controller_state := initial;
begin
process_4_c : process is
begin
-- code from book:
for state in controller_state loop
-- . . .
-- not in book:
current_state <= state;
wait for 10 ns;
-- end not in book
end loop;
-- end of code from book
wait;
end process process_4_c;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue376/util.vhdl | 1 | 4635 | library ieee ;
use ieee.std_logic_1164.all ;
library std;
use std.textio.all;
-- Utility package
package util is
procedure nop( signal clock : in std_logic ; count : in natural ) ;
end package ;
package body util is
procedure nop( signal clock : in std_logic ; count : in natural ) is
begin
for i in 1 to count loop
wait until rising_edge( clock ) ;
end loop ;
end procedure ;
end package body ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity data_saver is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data : std_logic_vector(DATA_WIDTH-1 downto 0);
data_valid : std_logic
);
end entity;
architecture arch of data_saver is
begin
handler : process
FILE fp : text;
variable line_data : line;
begin
--
wait until falling_edge(reset);
file_open(fp, FILENAME, WRITE_MODE);
while (reset = '0') loop
wait until rising_edge(data_valid);
write(line_data, data);
writeline(fp,line_data);
end loop;
file_close(fp);
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity signed_saver is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data : signed(DATA_WIDTH-1 downto 0);
data_valid : std_logic
);
end entity;
architecture arch of signed_saver is
begin
handler : process
FILE fp : text;
variable line_data : line;
begin
--
wait until falling_edge(reset);
file_open(fp, FILENAME, WRITE_MODE);
while (reset = '0') loop
wait until rising_edge(clock);
if data_valid = '1' then
write(line_data, (to_integer(data)));
writeline(fp,line_data);
end if;
end loop;
file_close(fp);
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity data_reader is
generic(
FILENAME : string := "file.dat";
DATA_WIDTH : natural := 16
);
port(
reset : in std_logic;
clock : in std_logic;
data_request : in std_logic;
data : out std_logic_vector(DATA_WIDTH-1 downto 0);
data_valid : out std_logic
);
end entity;
architecture arch of data_reader is
type character_array_t is array (natural range <>) of character;
begin
handler : process
variable line_data : line;
variable tmp : integer;
variable c : character;--_array_t(0 to 3);
type bin_t is file of character ;
file fp : bin_t ;
variable fs : file_open_status ;
begin
--
data <= (others => '0');
data_valid <= '0';
wait until falling_edge(reset);
file_open(fs, fp, FILENAME, READ_MODE);
if( fs /= OPEN_OK ) then
report "File open issues" severity failure ;
end if ;
--readline(fp,line_data);
while (reset = '0') loop
wait until rising_edge(clock);
data_valid <= '0';
if data_request = '1' then
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(7 downto 0) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(15 downto 8) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(23 downto 16) <= std_logic_vector(to_unsigned(tmp,8));
read(fp, c);
tmp := integer(natural(character'pos(c)));
data(31 downto 24) <= std_logic_vector(to_unsigned(tmp,8));
data_valid <= '1';
wait until rising_edge(clock);
data_valid <= '0';
end if;
end loop;
file_close(fp);
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd | 4 | 1956 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc895.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00895ent IS
procedure xyz ( a : integer; b : real );
procedure xyz ( a : integer; b : real ) is
begin
assert NOT( b = 2.0 * real(a) )
report "***PASSED TEST: c10s02b00x00p02n02i00895"
severity NOTE;
assert ( b = 2.0 * real(a) )
report "***FAILED TEST: c10s02b00x00p02n02i00895 - The scope of the declaration that occurs immediately within a formal parameter declaration extends beyond the immediate scope."
severity ERROR;
end xyz;
END c10s02b00x00p02n02i00895ent;
ARCHITECTURE c10s02b00x00p02n02i00895arch OF c10s02b00x00p02n02i00895ent IS
BEGIN
TESTING: PROCESS
BEGIN
xyz ( a => 20, b => 40.0 ); -- extended scope for the formals
wait;
END PROCESS TESTING;
END c10s02b00x00p02n02i00895arch;
| gpl-2.0 |
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